1 files changed, 0 insertions, 130 deletions
diff --git a/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch b/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch
deleted file mode 100644
index 12f71a3e55..0000000000
--- a/target/linux/mediatek/patches-4.14/0210-arm64-dts-mt7622-add-clock-controller-device-nodes.patch
+++ /dev/null
@@ -1,130 +0,0 @@
-From 9c76dd09d27dff05207241aa67a2c6054d057b32 Mon Sep 17 00:00:00 2001
-From: Sean Wang <sean.wang@mediatek.com>
-Date: Thu, 28 Dec 2017 10:30:32 +0800
-Subject: [PATCH 210/224] arm64: dts: mt7622: add clock controller device nodes
-
-Add clock controller nodes for MT7622 and include header for topckgen,
-infracfg, pericfg, apmixedsys, ethsys, sgmiisys, pciesys and ssusbsys
-for those devices nodes to be added afterwards.
-
-In addition, provides an oscillator node for the source of PLLs and dummy
-clock for PWARP to complement missing support of clock gate for the
-wrapper circuit in the driver.
-
-Signed-off-by: Sean Wang <sean.wang@mediatek.com>
-Cc: Stephen Boyd <sboyd@codeaurora.org>
----
- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 76 ++++++++++++++++++++++++++++++++
- 1 file changed, 76 insertions(+)
-
---- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-+++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi
-@@ -8,6 +8,8 @@
- 
- #include <dt-bindings/interrupt-controller/irq.h>
- #include <dt-bindings/interrupt-controller/arm-gic.h>
-+#include <dt-bindings/clock/mt7622-clk.h>
-+#include <dt-bindings/reset/mt7622-reset.h>
- 
- / {
- 	compatible = "mediatek,mt7622";
-@@ -48,6 +50,19 @@
- 		clock-frequency = <280000000>;
- 	};
- 
-+	pwrap_clk: dummy40m {
-+		compatible = "fixed-clock";
-+		clock-frequency = <40000000>;
-+		#clock-cells = <0>;
-+	};
-+
-+	clk25m: oscillator {
-+		compatible = "fixed-clock";
-+		#clock-cells = <0>;
-+		clock-frequency = <25000000>;
-+		clock-output-names = "clkxtal";
-+	};
-+
- 	psci {
- 		compatible  = "arm,psci-0.2";
- 		method      = "smc";
-@@ -78,6 +93,22 @@
- 			      IRQ_TYPE_LEVEL_HIGH)>;
- 	};
- 
-+	infracfg: infracfg@10000000 {
-+		compatible = "mediatek,mt7622-infracfg",
-+			     "syscon";
-+		reg = <0 0x10000000 0 0x1000>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	pericfg: pericfg@10002000 {
-+		compatible = "mediatek,mt7622-pericfg",
-+			     "syscon";
-+		reg = <0 0x10002000 0 0x1000>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
- 	sysirq: interrupt-controller@10200620 {
- 		compatible = "mediatek,mt7622-sysirq",
- 			     "mediatek,mt6577-sysirq";
-@@ -87,6 +118,20 @@
- 		reg = <0 0x10200620 0 0x20>;
- 	};
- 
-+	apmixedsys: apmixedsys@10209000 {
-+		compatible = "mediatek,mt7622-apmixedsys",
-+			     "syscon";
-+		reg = <0 0x10209000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
-+
-+	topckgen: topckgen@10210000 {
-+		compatible = "mediatek,mt7622-topckgen",
-+			     "syscon";
-+		reg = <0 0x10210000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
-+
- 	gic: interrupt-controller@10300000 {
- 		compatible = "arm,gic-400";
- 		interrupt-controller;
-@@ -107,4 +152,35 @@
- 		clock-names = "baud", "bus";
- 		status = "disabled";
- 	};
-+
-+	ssusbsys: ssusbsys@1a000000 {
-+		compatible = "mediatek,mt7622-ssusbsys",
-+			     "syscon";
-+		reg = <0 0x1a000000 0 0x1000>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	pciesys: pciesys@1a100800 {
-+		compatible = "mediatek,mt7622-pciesys",
-+			     "syscon";
-+		reg = <0 0x1a100800 0 0x1000>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	ethsys: syscon@1b000000 {
-+		compatible = "mediatek,mt7622-ethsys",
-+			     "syscon";
-+		reg = <0 0x1b000000 0 0x1000>;
-+		#clock-cells = <1>;
-+		#reset-cells = <1>;
-+	};
-+
-+	sgmiisys: sgmiisys@1b128000 {
-+		compatible = "mediatek,mt7622-sgmiisys",
-+			     "syscon";
-+		reg = <0 0x1b128000 0 0x1000>;
-+		#clock-cells = <1>;
-+	};
- };