diff options
Diffstat (limited to 'target/linux/mediatek/files-5.15/arch/arm64/boot')
12 files changed, 748 insertions, 237 deletions
diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi index 304566810a..3629a6f6dd 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7981.dtsi @@ -755,7 +755,7 @@ wifi: wifi@18000000 { compatible = "mediatek,mt7981-wmac"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; pinctrl-0 = <&wifi_dbdc_pins>; pinctrl-names = "dbdc"; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso new file mode 100644 index 0000000000..779dc6782b --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; + }; + }; +}; + diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso new file mode 100644 index 0000000000..15ee8c568f --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle <daniel@makrotopia.org> + * Frank Wunderlich <frank-w@public-files.de> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + spi_nand: spi_nand@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x80000>; + read-only; + }; + + partition@80000 { + label = "reserved"; + reg = <0x80000 0x300000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso new file mode 100644 index 0000000000..e48881be4e --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */ +/* + * Authors: Daniel Golle <daniel@makrotopia.org> + * Frank Wunderlich <frank-w@public-files.de> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/spi@1100a000"; + __overlay__ { + #address-cells = <1>; + #size-cells = <0>; + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; + }; + }; + }; + }; + }; +}; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso new file mode 100644 index 0000000000..f623bce075 --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Author: Sam.Shih <sam.shih@mediatek.com> + */ + +/dts-v1/; +/plugin/; + +/ { + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + fragment@0 { + target-path = "/soc/mmc@11230000"; + __overlay__ { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; + }; + }; +}; + diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts new file mode 100644 index 0000000000..af4a4309bd --- /dev/null +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3.dts @@ -0,0 +1,499 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Sam.Shih <sam.shih@mediatek.com> + * Frank Wunderlich <frank-w@public-files.de> + * Daniel Golle <daniel@makrotopia.org> + */ + +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12vd { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* cooling level (0, 1, 2) - pwm inverted */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000 0>; + status = "okay"; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps-key { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + }; + + /* i2c of the left SFP cage (wan) */ + i2c_sfp1: i2c-gpio-0 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + /* i2c of the right SFP cage (lan) */ + i2c_sfp2: i2c-gpio-1 { + compatible = "i2c-gpio"; + sda-gpios = <&pio 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + scl-gpios = <&pio 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + i2c-gpio,delay-us = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&pio 69 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + + blue_led: led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 86 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + /* left SFP cage (wan) */ + sfp1: sfp-1 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp1>; + los-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 20 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + /* right SFP cage (lan) */ + sfp2: sfp-2 { + compatible = "sff,sfp"; + i2c-bus = <&i2c_sfp2>; + los-gpios = <&pio 31 GPIO_ACTIVE_HIGH>; + mod-def0-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + tx-disable-gpios = <&pio 15 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; + }; +}; + +&cpu_thermal { + cooling-maps { + cpu-active-high { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + cpu-active-low { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_low>; + }; + + cpu-passive { + /* passive: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_passive>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + sfp = <&sfp1>; + managed = "in-band-status"; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + switch: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0", "pwm1_0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + spic_pins: spic-pins { + mux { + function = "spi"; + groups = "spi1_0"; + }; + }; + + uart1_pins: uart1-pins { + mux { + function = "uart"; + groups = "uart1_rx_tx"; + }; + }; + + uart2_pins: uart2-pins { + mux { + function = "uart"; + groups = "uart2_0_rx_tx"; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spic_pins>; + status = "okay"; +}; + +&ssusb { + status = "okay"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "wan"; + }; + + port@1 { + reg = <1>; + label = "lan0"; + }; + + port@2 { + reg = <2>; + label = "lan1"; + }; + + port@3 { + reg = <3>; + label = "lan2"; + }; + + port@4 { + reg = <4>; + label = "lan3"; + }; + + port5: port@5 { + reg = <5>; + label = "lan4"; + phy-mode = "2500base-x"; + sfp = <&sfp2>; + managed = "in-band-status"; + }; + + port@6 { + reg = <6>; + label = "cpu"; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; +}; + diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts index 938dd181b9..83a37150cf 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nand.dts @@ -47,6 +47,6 @@ }; }; -&wmac { +&wifi { mediatek,mtd-eeprom = <&factory 0>; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts index 6342981304..868365a994 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb-spim-nor.dts @@ -46,6 +46,6 @@ }; }; -&wmac { +&wifi { mediatek,mtd-eeprom = <&factory 0>; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi index b63692c161..1ab56e37f7 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a-rfb.dtsi @@ -78,7 +78,7 @@ }; }; -&wmac { +&wifi { status = "okay"; pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi index 86090f8ebe..68539ea788 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986a.dtsi @@ -4,19 +4,19 @@ * Author: Sam.Shih <sam.shih@mediatek.com> */ -#include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/arm-gic.h> -#include <dt-bindings/phy/phy.h> +#include <dt-bindings/clock/mt7986-clk.h> #include <dt-bindings/reset/mt7986-resets.h> -#include <dt-bindings/thermal/thermal.h> +#include <dt-bindings/phy/phy.h> / { + compatible = "mediatek,mt7986a"; interrupt-parent = <&gic>; #address-cells = <2>; #size-cells = <2>; - clk40m: oscillator@0 { + clk40m: oscillator-40m { compatible = "fixed-clock"; clock-frequency = <40000000>; #clock-cells = <0>; @@ -60,22 +60,14 @@ }; psci { - compatible = "arm,psci-0.2"; - method = "smc"; + compatible = "arm,psci-0.2"; + method = "smc"; }; reserved-memory { #address-cells = <2>; #size-cells = <2>; ranges; - - /* 64 KiB reserved for ramoops/pstore */ - ramoops@42ff0000 { - compatible = "ramoops"; - reg = <0 0x42ff0000 0 0x10000>; - record-size = <0x1000>; - }; - /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ secmon_reserved: secmon@43000000 { reg = <0 0x43000000 0 0x30000>; @@ -126,6 +118,7 @@ reg = <0 0x15194000 0 0x1000>; no-map; }; + }; timer { @@ -162,6 +155,12 @@ #clock-cells = <1>; }; + wed_pcie: wed-pcie@10003000 { + compatible = "mediatek,mt7986-wed-pcie", + "syscon"; + reg = <0 0x10003000 0 0x10>; + }; + topckgen: topckgen@1001b000 { compatible = "mediatek,mt7986-topckgen", "syscon"; reg = <0 0x1001B000 0 0x1000>; @@ -169,11 +168,17 @@ }; watchdog: watchdog@1001c000 { - compatible = "mediatek,mt7986-wdt", - "mediatek,mt6589-wdt"; + compatible = "mediatek,mt7986-wdt"; reg = <0 0x1001c000 0 0x1000>; interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; #reset-cells = <1>; + status = "disabled"; + }; + + apmixedsys: apmixedsys@1001e000 { + compatible = "mediatek,mt7986-apmixedsys"; + reg = <0 0x1001E000 0 0x1000>; + #clock-cells = <1>; }; pio: pinctrl@1001f000 { @@ -197,12 +202,6 @@ #interrupt-cells = <2>; }; - apmixedsys: apmixedsys@1001e000 { - compatible = "mediatek,mt7986-apmixedsys"; - reg = <0 0x1001E000 0 0x1000>; - #clock-cells = <1>; - }; - sgmiisys0: syscon@10060000 { compatible = "mediatek,mt7986-sgmiisys_0", "syscon"; @@ -217,12 +216,13 @@ #clock-cells = <1>; }; - trng: trng@1020f000 { - compatible = "mediatek,mt7986-rng"; + trng: rng@1020f000 { + compatible = "mediatek,mt7986-rng", + "mediatek,mt7623-rng"; reg = <0 0x1020f000 0 0x100>; clocks = <&infracfg CLK_INFRA_TRNG_CK>; clock-names = "rng"; - status = "okay"; + status = "disabled"; }; crypto: crypto@10320000 { @@ -237,7 +237,7 @@ clock-names = "infra_eip97_ck"; assigned-clocks = <&topckgen CLK_TOP_EIP_B_SEL>; assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>; - status = "okay"; + status = "disabled"; }; pwm: pwm@10048000 { @@ -246,7 +246,7 @@ #clock-cells = <1>; #pwm-cells = <2>; interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CLK_INFRA_PWM_HCK>, + clocks = <&topckgen CLK_TOP_PWM_SEL>, <&infracfg CLK_INFRA_PWM_STA>, <&infracfg CLK_INFRA_PWM1_CK>, <&infracfg CLK_INFRA_PWM2_CK>; @@ -311,6 +311,8 @@ spi0: spi@1100a000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; reg = <0 0x1100a000 0 0x100>; interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, @@ -323,6 +325,8 @@ spi1: spi@1100b000 { compatible = "mediatek,mt7986-spi-ipm", "mediatek,spi-ipm"; + #address-cells = <1>; + #size-cells = <0>; reg = <0 0x1100b000 0 0x100>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&topckgen CLK_TOP_MPLL_D2>, @@ -334,12 +338,12 @@ }; auxadc: adc@1100d000 { - compatible = "mediatek,mt7986-auxadc", - "mediatek,mt7622-auxadc"; + compatible = "mediatek,mt7986-auxadc"; reg = <0 0x1100d000 0 0x1000>; clocks = <&infracfg CLK_INFRA_ADC_26M_CK>; clock-names = "main"; #io-channel-cells = <1>; + status = "disabled"; }; ssusb: usb@11200000 { @@ -350,15 +354,15 @@ reg-names = "mac", "ippc"; interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_IUSB_SYS_CK>, - <&topckgen CLK_TOP_U2U3_XHCI_SEL>, <&infracfg CLK_INFRA_IUSB_CK>, <&infracfg CLK_INFRA_IUSB_133_CK>, - <&infracfg CLK_INFRA_IUSB_66M_CK>; + <&infracfg CLK_INFRA_IUSB_66M_CK>, + <&topckgen CLK_TOP_U2U3_XHCI_SEL>; clock-names = "sys_ck", - "xhci_ck", "ref_ck", "mcu_ck", - "dma_ck"; + "dma_ck", + "xhci_ck"; phys = <&u2port0 PHY_TYPE_USB2>, <&u3port0 PHY_TYPE_USB3>, <&u2port1 PHY_TYPE_USB2>; @@ -370,15 +374,13 @@ reg = <0 0x11230000 0 0x1000>, <0 0x11c20000 0 0x1000>; interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&infracfg CLK_INFRA_MSDC_CK>, + clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, <&infracfg CLK_INFRA_MSDC_HCK_CK>, - <&infracfg CLK_INFRA_MSDC_66M_CK>, - <&infracfg CLK_INFRA_MSDC_133M_CK>; - clock-names = "source", "hclk", "axi_cg", "ahb_cg"; - assigned-clocks = <&topckgen CLK_TOP_EMMC_416M_SEL>, - <&topckgen CLK_TOP_EMMC_250M_SEL>; - assigned-clock-parents = <&apmixedsys CLK_APMIXED_MPLL>, - <&topckgen CLK_TOP_NET1PLL_D5_D2>; + <&infracfg CLK_INFRA_MSDC_CK>, + <&infracfg CLK_INFRA_MSDC_133M_CK>, + <&infracfg CLK_INFRA_MSDC_66M_CK>; + clock-names = "source", "hclk", "source_cg", "bus_clk", + "sys_cg"; status = "disabled"; }; @@ -388,8 +390,9 @@ reg = <0 0x1100c800 0 0x800>; interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>; clocks = <&infracfg CLK_INFRA_THERM_CK>, - <&infracfg CLK_INFRA_ADC_26M_CK>; - clock-names = "therm", "auxadc"; + <&infracfg CLK_INFRA_ADC_26M_CK>, + <&infracfg CLK_INFRA_ADC_FRC_CK>; + clock-names = "therm", "auxadc", "adc_32k"; mediatek,auxadc = <&auxadc>; mediatek,apmixedsys = <&apmixedsys>; nvmem-cells = <&thermal_calibration>; @@ -408,11 +411,11 @@ bus-range = <0x00 0xff>; ranges = <0x82000000 0x00 0x20000000 0x00 0x20000000 0x00 0x10000000>; - clocks = <&infracfg CLK_INFRA_PCIE_SEL>, + clocks = <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIE_CK>, - <&infracfg CLK_INFRA_IPCIE_PIPE_CK>, <&infracfg CLK_INFRA_IPCIER_CK>, <&infracfg CLK_INFRA_IPCIEB_CK>; + clock-names = "pl_250m", "tl_26m", "peri_26m", "top_133m"; status = "disabled"; phys = <&pcie_port PHY_TYPE_PCIE>; @@ -433,7 +436,7 @@ pcie_phy: t-phy@11c00000 { compatible = "mediatek,mt7986-tphy", - "mediatek,generic-tphy-v4"; + "mediatek,generic-tphy-v2"; #address-cells = <2>; #size-cells = <2>; ranges; @@ -444,30 +447,11 @@ clocks = <&clk40m>; clock-names = "ref"; #phy-cells = <1>; - auto_load_valid; - auto_load_valid_ln1; - nvmem-cells = <&pcie_intr_ln0>, - <&pcie_rx_imp_ln0>, - <&pcie_tx_imp_ln0>, - <&pcie_auto_load_valid_ln0>, - <&pcie_intr_ln1>, - <&pcie_rx_imp_ln1>, - <&pcie_tx_imp_ln1>, - <&pcie_auto_load_valid_ln1>; - nvmem-cell-names = "intr", - "rx_imp", - "tx_imp", - "auto_load_valid", - "intr_ln1", - "rx_imp_ln1", - "tx_imp_ln1", - "auto_load_valid_ln1"; }; }; efuse: efuse@11d00000 { - compatible = "mediatek,mt7986-efuse", - "mediatek,efuse"; + compatible = "mediatek,mt7986-efuse", "mediatek,efuse"; reg = <0 0x11d00000 0 0x1000>; #address-cells = <1>; #size-cells = <1>; @@ -475,149 +459,50 @@ thermal_calibration: calib@274 { reg = <0x274 0xc>; }; - - comb_auto_load_valid: usb3-alv-imp@8da { - reg = <0x8da 1>; - bits = <0 1>; - }; - - comb_rx_imp_p0: usb3-rx-imp@8d8 { - reg = <0x8d8 1>; - bits = <0 5>; - }; - - comb_tx_imp_p0: usb3-tx-imp@8d8 { - reg = <0x8d8 2>; - bits = <5 5>; - }; - - comb_intr_p0: usb3-intr@8d9 { - reg = <0x8d9 1>; - bits = <2 6>; - }; - - u2_auto_load_valid_p0: usb2-alv-p0@8e0 { - reg = <0x8e0 1>; - bits = <0 1>; - }; - - u2_intr_p0: usb2-intr-p0@8e0 { - reg = <0x8e0 1>; - bits = <1 5>; - }; - - u2_auto_load_valid_p1: usb2-alv-p1@8e0 { - reg = <0x8e0 2>; - bits = <6 1>; - }; - - u2_intr_p1: usb2-intr-p1@8e0 { - reg = <0x8e0 2>; - bits = <7 5>; - }; - - pcie_rx_imp_ln0: pcie-rx-imp@8d0 { - reg = <0x8d0 1>; - bits = <0 5>; - }; - - pcie_tx_imp_ln0: pcie-tx-imp@8d0 { - reg = <0x8d0 2>; - bits = <5 5>; - }; - - pcie_intr_ln0: pcie-intr@8d1 { - reg = <0x8d1 1>; - bits = <2 6>; - }; - - pcie_auto_load_valid_ln0: pcie-ln0-alv@8d4 { - reg = <0x8d4 1>; - bits = <0 1>; - }; - - pcie_rx_imp_ln1: pcie-rx-imp@8d2 { - reg = <0x8d2 1>; - bits = <0 5>; - }; - - pcie_tx_imp_ln1: pcie-tx-imp@8d2 { - reg = <0x8d2 2>; - bits = <5 5>; - }; - - pcie_intr_ln1: pcie-intr@8d3 { - reg = <0x8d3 1>; - bits = <2 6>; - }; - - pcie_auto_load_valid_ln1: pcie-ln1-alv@8d4 { - reg = <0x8d4 1>; - bits = <1 1>; - }; }; usb_phy: t-phy@11e10000 { compatible = "mediatek,mt7986-tphy", "mediatek,generic-tphy-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e10000 0x1700>; status = "disabled"; - u2port0: usb-phy@11e10000 { - reg = <0 0x11e10000 0 0x700>; + u2port0: usb-phy@0 { + reg = <0x0 0x700>; clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; clock-names = "ref", "da_ref"; #phy-cells = <1>; - auto_load_valid; - nvmem-cells = <&u2_intr_p0>, <&u2_auto_load_valid_p0>; - nvmem-cell-names = "intr", "auto_load_valid"; }; - u3port0: usb-phy@11e10700 { - reg = <0 0x11e10700 0 0x900>; + u3port0: usb-phy@700 { + reg = <0x700 0x900>; clocks = <&topckgen CLK_TOP_USB3_PHY_SEL>; clock-names = "ref"; #phy-cells = <1>; - auto_load_valid; - nvmem-cells = <&comb_intr_p0>, - <&comb_rx_imp_p0>, - <&comb_tx_imp_p0>, - <&comb_auto_load_valid>; - nvmem-cell-names = "intr", "rx_imp", "tx_imp", "auto_load_valid"; }; - u2port1: usb-phy@11e11000 { - reg = <0 0x11e11000 0 0x700>; + u2port1: usb-phy@1000 { + reg = <0x1000 0x700>; clocks = <&topckgen CLK_TOP_DA_U2_REFSEL>, <&topckgen CLK_TOP_DA_U2_CK_1P_SEL>; clock-names = "ref", "da_ref"; #phy-cells = <1>; - auto_load_valid; - nvmem-cells = <&u2_intr_p1>, <&u2_auto_load_valid_p1>; - nvmem-cell-names = "intr", "auto_load_valid"; }; }; ethsys: syscon@15000000 { #address-cells = <1>; #size-cells = <1>; - compatible = "mediatek,mt7986-ethsys_ck", + compatible = "mediatek,mt7986-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; - wed_pcie: wed-pcie@10003000 { - compatible = "mediatek,mt7986-wed-pcie", - "syscon"; - reg = <0 0x10003000 0 0x10>; - }; - - wed0: wed@15010000 { compatible = "mediatek,mt7986-wed", "syscon"; @@ -700,95 +585,49 @@ status = "disabled"; }; - consys: consys@10000000 { - compatible = "mediatek,mt7986-consys"; - reg = <0 0x10000000 0 0x8600000>; - memory-region = <&wmcpu_emi>; - }; - - wmac: wmac@18000000 { - compatible = "mediatek,mt7986-wmac", "mediatek,wbsys"; - resets = <&watchdog MT7986_TOPRGU_CONSYS_RST>; + wifi: wifi@18000000 { + compatible = "mediatek,mt7986-wmac"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; reset-names = "consys"; + clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; reg = <0 0x18000000 0 0x1000000>, <0 0x10003000 0 0x1000>, <0 0x11d10000 0 0x1000>; interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen CLK_TOP_CONN_MCUSYS_SEL>, - <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; - clock-names = "mcu", "ap2conn"; + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&wmcpu_emi>; - status = "disabled"; }; }; - fan: pwm-fan { - compatible = "pwm-fan"; - /* cooling level (0, 1, 2, 3) : (0% duty, 33% duty, 66% duty, 100% duty) */ - cooling-levels = <0 86 172 255>; - #cooling-cells = <2>; - status = "disabled"; - }; - thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <1000>; polling-delay = <1000>; thermal-sensors = <&thermal 0>; - trips { - cpu_trip_crit: crit { - temperature = <125000>; - hysteresis = <2000>; - type = "critical"; - }; - - cpu_trip_hot: hot { - temperature = <120000>; - hysteresis = <2000>; - type = "hot"; - }; + trips { cpu_trip_active_high: active-high { temperature = <115000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_active_med: active-med { + cpu_trip_active_low: active-low { temperature = <85000>; hysteresis = <2000>; type = "active"; }; - cpu_trip_active_low: active-low { - temperature = <60000>; + cpu_trip_passive: passive { + temperature = <40000>; hysteresis = <2000>; type = "passive"; }; }; - - cooling-maps { - cpu-active-high { - /* active: set fan to cooling level 3 */ - cooling-device = <&fan 3 3>; - trip = <&cpu_trip_active_high>; - }; - - cpu-active-med { - /* active: set fan to cooling level 2 */ - cooling-device = <&fan 2 2>; - trip = <&cpu_trip_active_med>; - }; - - cpu-active-low { - /* passive: set fan to cooling level 1 */ - cooling-device = <&fan 1 1>; - trip = <&cpu_trip_active_low>; - }; - }; }; }; }; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts index 85465223cf..83d5191671 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b-rfb.dts @@ -56,7 +56,7 @@ status = "okay"; }; -&wmac { +&wifi { status = "okay"; pinctrl-names = "default", "dbdc"; pinctrl-0 = <&wf_2g_5g_pins>; diff --git a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi index 23923b9f89..db5189664c 100644 --- a/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi +++ b/target/linux/mediatek/files-5.15/arch/arm64/boot/dts/mediatek/mt7986b.dtsi @@ -5,6 +5,9 @@ */ #include "mt7986a.dtsi" +/ { + compatible = "mediatek,mt7986b"; +}; &pio { compatible = "mediatek,mt7986b-pinctrl"; |