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-rw-r--r--target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts573
-rw-r--r--target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts612
-rw-r--r--target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts609
-rw-r--r--target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts609
-rw-r--r--target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi914
5 files changed, 0 insertions, 3317 deletions
diff --git a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
deleted file mode 100644
index f1cbd94b40..0000000000
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts
+++ /dev/null
@@ -1,573 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR MIT)
-/*
- * Copyright (c) 2018 MediaTek Inc.
- * Author: Ryder Lee <ryder.lee@mediatek.com>
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
- model = "Bananapi BPI-R64";
- compatible = "bananapi,bpi-r64", "mediatek,mt7622";
-
- chosen {
- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- };
-
- cpus {
- cpu@0 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
-
- cpu@1 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
-
- factory {
- label = "factory";
- linux,code = <BTN_0>;
- gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 GPIO_ACTIVE_HIGH>;
- };
- };
-
- gsw: gsw@0 {
- compatible = "mediatek,mt753x";
- mediatek,ethsys = <&ethsys>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- leds {
- compatible = "gpio-leds";
-
- green {
- label = "bpi-r64:pio:green";
- gpios = <&pio 89 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
-
- red {
- label = "bpi-r64:pio:red";
- gpios = <&pio 88 GPIO_ACTIVE_HIGH>;
- default-state = "off";
- };
- };
-
- memory {
- reg = <0 0x40000000 0 0x40000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
-};
-
-&bch {
- status = "disabled";
-};
-
-&btif {
- status = "okay";
-};
-
-&cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
- status = "okay";
-};
-
-&eth {
- status = "okay";
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&gsw {
- mediatek,mdio = <&mdio>;
- mediatek,portmap = "wllll";
- mediatek,mdio_master_pinmux = <0>;
- reset-gpios = <&pio 54 0>;
- interrupt-parent = <&pio>;
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
-
- port5: port@5 {
- compatible = "mediatek,mt753x-port";
- reg = <5>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port6: port@6 {
- compatible = "mediatek,mt753x-port";
- reg = <6>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&emmc_pins_default>;
- pinctrl-1 = <&emmc_pins_uhs>;
- status = "okay";
- bus-width = <8>;
- max-frequency = <50000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- non-removable;
-};
-
-&mmc1 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sd0_pins_default>;
- pinctrl-1 = <&sd0_pins_uhs>;
- status = "okay";
- bus-width = <4>;
- max-frequency = <50000000>;
- cap-sd-highspeed;
- r_smpl = <1>;
- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_3p3v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
- pinctrl-names = "default";
- pinctrl-0 = <&parallel_nand_pins>;
- status = "disabled";
-};
-
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- };
-};
-
-&pcie {
- pinctrl-names = "default";
- pinctrl-0 = <&pcie0_pins>, <&pcie1_pins>;
- status = "okay";
-
- pcie@0,0 {
- status = "okay";
- };
-
- pcie@1,0 {
- status = "okay";
- };
-};
-
-&pio {
- /* Attention: GPIO 90 is used to switch between PCIe@1,0 and
- * SATA functions. i.e. output-high: PCIe, output-low: SATA
- */
- asm_sel {
- gpio-hog;
- gpios = <90 GPIO_ACTIVE_HIGH>;
- output-high;
- };
-
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
- };
-
- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
- */
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- bias-pull-down;
- };
- };
-
- emmc_pins_uhs: emmc-pins-uhs {
- mux {
- function = "emmc";
- groups = "emmc";
- };
-
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- drive-strength = <4>;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- drive-strength = <4>;
- bias-pull-down;
- };
- };
-
- eth_pins: eth-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio", "rgmii_via_gmac2";
- };
- };
-
- i2c1_pins: i2c1-pins {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2s1_pins: i2s1-pins {
- mux {
- function = "i2s";
- groups = "i2s_out_mclk_bclk_ws",
- "i2s1_in_data",
- "i2s1_out_data";
- };
-
- conf {
- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
- "I2S_WS", "I2S_MCLK";
- drive-strength = <12>;
- bias-pull-down;
- };
- };
-
- irrx_pins: irrx-pins {
- mux {
- function = "ir";
- groups = "ir_1_rx";
- };
- };
-
- irtx_pins: irtx-pins {
- mux {
- function = "ir";
- groups = "ir_1_tx";
- };
- };
-
- /* Parallel nand is shared pin with eMMC */
- parallel_nand_pins: parallel-nand-pins {
- mux {
- function = "flash";
- groups = "par_nand";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie0_pad_perst",
- "pcie0_1_waken",
- "pcie0_1_clkreq";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie1_pad_perst",
- "pcie1_0_waken",
- "pcie1_0_clkreq";
- };
- };
-
- pmic_bus_pins: pmic-bus-pins {
- mux {
- function = "pmic";
- groups = "pmic_bus";
- };
- };
-
- pwm7_pins: pwm1-2-pins {
- mux {
- function = "pwm";
- groups = "pwm_ch7_2";
- };
- };
-
- wled_pins: wled-pins {
- mux {
- function = "led";
- groups = "wled";
- };
- };
-
- sd0_pins_default: sd0-pins-default {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
- * DAT2, DAT3, CMD, CLK for SD respectively.
- */
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- drive-strength = <8>;
- bias-pull-up;
- };
- conf-clk {
- pins = "I2S3_OUT";
- drive-strength = <12>;
- bias-pull-down;
- };
- conf-cd {
- pins = "TXD3";
- bias-pull-up;
- };
- };
-
- sd0_pins_uhs: sd0-pins-uhs {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "I2S3_OUT";
- bias-pull-down;
- };
- };
-
- /* Serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spic0_pins: spic0-pins {
- mux {
- function = "spi";
- groups = "spic0_0";
- };
- };
-
- spic1_pins: spic1-pins {
- mux {
- function = "spi";
- groups = "spic1_0";
- };
- };
-
- /* SPI-NOR is shared pin with serial NAND */
- spi_nor_pins: spi-nor-pins {
- mux {
- function = "flash";
- groups = "spi_nor";
- };
- };
-
- /* serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0_0_tx_rx" ;
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_1_tx_rx" ;
- };
- };
-
- watchdog_pins: watchdog-pins {
- mux {
- function = "watchdog";
- groups = "watchdog";
- };
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pins>;
- status = "okay";
-};
-
-&pwrap {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_bus_pins>;
-
- status = "okay";
-};
-
-&sata {
- status = "disable";
-};
-
-&sata_phy {
- status = "disable";
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic1_pins>;
- status = "okay";
-};
-
-&ssusb {
- vusb33-supply = <&reg_3p3v>;
- vbus-supply = <&reg_5v>;
- status = "okay";
-};
-
-&u3phy {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&watchdog {
- pinctrl-names = "default";
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
-};
diff --git a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
deleted file mode 100644
index 6e94e49bc1..0000000000
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-elecom-wrc-2533gent.dts
+++ /dev/null
@@ -1,612 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <ming.huang@mediatek.com>
- * Sean Wang <sean.wang@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
- model = "Elecom WRC-2533";
- compatible = "elecom,wrc-2533gent", "mediatek,mt7622";
-
- aliases {
- led-boot = &led_power;
- led-failsafe = &led_power;
- led-running = &led_power;
- led-upgrade = &led_power;
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512 console=ttyS0,115200n8";
- };
-
- cpus {
- cpu@0 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
-
- cpu@1 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- poll-interval = <100>;
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 0 GPIO_ACTIVE_HIGH>;
- };
-
- factory {
- label = "factory";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 GPIO_ACTIVE_LOW>;
- };
-
- switch0 {
- label = "switch0";
- gpios = <&pio 1 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_0>;
- linux,input-type = <EV_SW>;
- };
-
- switch1 {
- label = "switch1";
- gpios = <&pio 16 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_1>;
- linux,input-type = <EV_SW>;
- };
-
- switch2 {
- label = "switch2";
- gpios = <&pio 17 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_2>;
- linux,input-type = <EV_SW>;
- };
-
- switch3 {
- label = "switch3";
- gpios = <&pio 18 GPIO_ACTIVE_LOW>;
- linux,code = <BTN_3>;
- linux,input-type = <EV_SW>;
- };
- };
-
- leds {
- compatible = "gpio-leds";
-
- led_power: power_g {
- label = "wrc-2533:green:power";
- gpios = <&pio 2 GPIO_ACTIVE_HIGH>;
- };
-
- power_b {
- label = "wrc-2533:blue:power";
- gpios = <&pio 19 GPIO_ACTIVE_HIGH>;
- };
-
- power_r {
- label = "wrc-2533:red:power";
- gpios = <&pio 73 GPIO_ACTIVE_HIGH>;
- };
-
- usb {
- label = "wrc-2533:blue:usb";
- gpios = <&pio 74 GPIO_ACTIVE_HIGH>;
- };
-
- wps {
- label = "wrc-2533:red:wps";
- gpios = <&pio 76 GPIO_ACTIVE_LOW>;
- };
-
- wifi2 {
- label = "wrc-2533:blue:wifi2g";
- gpios = <&pio 85 GPIO_ACTIVE_LOW>;
- };
-
- wifi5 {
- label = "wrc-2533:blue:wifi5g";
- gpios = <&pio 91 GPIO_ACTIVE_LOW>;
- };
- };
-
- reg_usb_vbus: regulator {
- compatible = "regulator-fixed";
- regulator-name = "usb_vbus";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- gpio = <&pio 22 GPIO_ACTIVE_LOW>;
- enable-active-high;
- };
-
- memory {
- reg = <0 0x40000000 0 0x3F000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- rtkgsw: rtkgsw@0 {
- compatible = "mediatek,rtk-gsw";
- mediatek,ethsys = <&ethsys>;
- mediatek,mdio = <&mdio>;
- mediatek,reset-pin = <&pio 54 0>;
- status = "okay";
- };
-};
-
-&pcie {
- pinctrl-names = "default", "pcie1_pins";
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-1 = <&pcie1_pins>;
- status = "okay";
-
- pcie@0,0 {
- status = "okay";
- mt7615@0,0 {
- reg = <0x0000 0 0 0 0>;
- mediatek,mtd-eeprom = <&factory 0x05000>;
- };
- };
-
- pcie@1,0 {
- status = "okay";
- };
-};
-
-&pio {
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
- };
-
- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
- */
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- bias-pull-down;
- };
- };
-
- emmc_pins_uhs: emmc-pins-uhs {
- mux {
- function = "emmc";
- groups = "emmc";
- };
-
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- drive-strength = <4>;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- drive-strength = <4>;
- bias-pull-down;
- };
- };
-
- eth_pins: eth-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio", "rgmii_via_gmac2";
- };
- };
-
- i2c1_pins: i2c1-pins {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2s1_pins: i2s1-pins {
- mux {
- function = "i2s";
- groups = "i2s_out_mclk_bclk_ws",
- "i2s1_in_data",
- "i2s1_out_data";
- };
-
- conf {
- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
- "I2S_WS", "I2S_MCLK";
- drive-strength = <12>;
- bias-pull-down;
- };
- };
-
- irrx_pins: irrx-pins {
- mux {
- function = "ir";
- groups = "ir_1_rx";
- };
- };
-
- irtx_pins: irtx-pins {
- mux {
- function = "ir";
- groups = "ir_1_tx";
- };
- };
-
- /* Parallel nand is shared pin with eMMC */
- parallel_nand_pins: parallel-nand-pins {
- mux {
- function = "flash";
- groups = "par_nand";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie0_pad_perst",
- "pcie0_1_waken",
- "pcie0_1_clkreq";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie1_pad_perst",
- "pcie1_0_waken",
- "pcie1_0_clkreq";
- };
- };
-
- pmic_bus_pins: pmic-bus-pins {
- mux {
- function = "pmic";
- groups = "pmic_bus";
- };
- };
-
- pwm7_pins: pwm1-2-pins {
- mux {
- function = "pwm";
- groups = "pwm_ch7_2";
- };
- };
-
- wled_pins: wled-pins {
- mux {
- function = "led";
- groups = "wled";
- };
- };
-
- sd0_pins_default: sd0-pins-default {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
- * DAT2, DAT3, CMD, CLK for SD respectively.
- */
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- drive-strength = <8>;
- bias-pull-up;
- };
- conf-clk {
- pins = "I2S3_OUT";
- drive-strength = <12>;
- bias-pull-down;
- };
- conf-cd {
- pins = "TXD3";
- bias-pull-up;
- };
- };
-
- sd0_pins_uhs: sd0-pins-uhs {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "I2S3_OUT";
- bias-pull-down;
- };
- };
-
- /* Serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spic0_pins: spic0-pins {
- mux {
- function = "spi";
- groups = "spic0_0";
- };
- };
-
- spic1_pins: spic1-pins {
- mux {
- function = "spi";
- groups = "spic1_0";
- };
- };
-
- /* SPI-NOR is shared pin with serial NAND */
- spi_nor_pins: spi-nor-pins {
- mux {
- function = "flash";
- groups = "spi_nor";
- };
- };
-
- /* serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0_0_tx_rx" ;
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_1_tx_rx" ;
- };
- };
-
- watchdog_pins: watchdog-pins {
- mux {
- function = "watchdog";
- groups = "watchdog";
- };
- };
-};
-
-&bch {
- status = "okay";
-};
-
-&btif {
- status = "okay";
-};
-
-&cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
- status = "okay";
-};
-
-&eth {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&eth_pins>;
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pins>;
- status = "okay";
-};
-
-&pwrap {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_bus_pins>;
-
- status = "okay";
-};
-
-&snfi {
- pinctrl-names = "default";
- pinctrl-0 = <&serial_nand_pins>;
- status = "okay";
-
- spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <104000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "preloader";
- reg = <0x00000 0x0080000>;
- read-only;
- };
-
- partition@80000 {
- label = "ATF";
- reg = <0x80000 0x0040000>;
- read-only;
- };
-
- partition@c0000 {
- label = "uboot";
- reg = <0xc0000 0x0080000>;
- read-only;
- };
-
- partition@140000 {
- label = "uboot-env";
- reg = <0x140000 0x0080000>;
- read-only;
- };
-
- factory: partition@1c0000 {
- label = "factory";
- reg = <0x1c0000 0x0040000>;
- read-only;
- };
-
- partition@200000 {
- label = "firmware";
- reg = <0x200000 0x2000000>;
- };
-
- partition@2200000 {
- label = "reserved";
- reg = <0x2200000 0x4000000>;
- };
- };
- };
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic1_pins>;
- status = "okay";
-};
-
-&ssusb {
- vusb33-supply = <&reg_3p3v>;
- vbus-supply = <&reg_usb_vbus>;
- status = "okay";
-};
-
-&u3phy {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&watchdog {
- pinctrl-names = "default";
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
-};
-
-&wmac {
- mediatek,mtd-eeprom = <&factory 0x0000>;
- status = "okay";
-};
diff --git a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts
deleted file mode 100644
index 52db118231..0000000000
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-lynx-rfb1.dts
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <ming.huang@mediatek.com>
- * Sean Wang <sean.wang@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
- model = "MediaTek MT7622 RFB1 board";
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11002000 swiotlb=512";
- };
-
- cpus {
- cpu@0 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
-
- cpu@1 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- poll-interval = <100>;
-
- factory {
- label = "factory";
- linux,code = <BTN_0>;
- gpios = <&pio 0 0>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 0>;
- };
- };
-
- gsw: gsw@0 {
- compatible = "mediatek,mt753x";
- mediatek,ethsys = <&ethsys>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- memory {
- reg = <0 0x40000000 0 0x3F000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&pcie {
- pinctrl-names = "default", "pcie1_pins";
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-1 = <&pcie1_pins>;
- status = "okay";
-
- pcie@0,0 {
- status = "okay";
- };
-
- pcie@1,0 {
- status = "okay";
- };
-
-};
-
-&pio {
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
- };
-
- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
- */
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- bias-pull-down;
- };
- };
-
- emmc_pins_uhs: emmc-pins-uhs {
- mux {
- function = "emmc";
- groups = "emmc";
- };
-
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- drive-strength = <4>;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- drive-strength = <4>;
- bias-pull-down;
- };
- };
-
- eth_pins: eth-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio", "rgmii_via_gmac2";
- };
- };
-
- i2c1_pins: i2c1-pins {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2s1_pins: i2s1-pins {
- mux {
- function = "i2s";
- groups = "i2s_out_mclk_bclk_ws",
- "i2s1_in_data",
- "i2s1_out_data";
- };
-
- conf {
- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
- "I2S_WS", "I2S_MCLK";
- drive-strength = <12>;
- bias-pull-down;
- };
- };
-
- irrx_pins: irrx-pins {
- mux {
- function = "ir";
- groups = "ir_1_rx";
- };
- };
-
- irtx_pins: irtx-pins {
- mux {
- function = "ir";
- groups = "ir_1_tx";
- };
- };
-
- /* Parallel nand is shared pin with eMMC */
- parallel_nand_pins: parallel-nand-pins {
- mux {
- function = "flash";
- groups = "par_nand";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie0_pad_perst",
- "pcie0_1_waken",
- "pcie0_1_clkreq";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie1_pad_perst",
- "pcie1_0_waken",
- "pcie1_0_clkreq";
- };
- };
-
- pmic_bus_pins: pmic-bus-pins {
- mux {
- function = "pmic";
- groups = "pmic_bus";
- };
- };
-
- pwm7_pins: pwm1-2-pins {
- mux {
- function = "pwm";
- groups = "pwm_ch7_2";
- };
- };
-
- wled_pins: wled-pins {
- mux {
- function = "led";
- groups = "wled";
- };
- };
-
- sd0_pins_default: sd0-pins-default {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
- * DAT2, DAT3, CMD, CLK for SD respectively.
- */
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- drive-strength = <8>;
- bias-pull-up;
- };
- conf-clk {
- pins = "I2S3_OUT";
- drive-strength = <12>;
- bias-pull-down;
- };
- conf-cd {
- pins = "TXD3";
- bias-pull-up;
- };
- };
-
- sd0_pins_uhs: sd0-pins-uhs {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "I2S3_OUT";
- bias-pull-down;
- };
- };
-
- /* Serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spic0_pins: spic0-pins {
- mux {
- function = "spi";
- groups = "spic0_0";
- };
- };
-
- spic1_pins: spic1-pins {
- mux {
- function = "spi";
- groups = "spic1_0";
- };
- };
-
- /* SPI-NOR is shared pin with serial NAND */
- spi_nor_pins: spi-nor-pins {
- mux {
- function = "flash";
- groups = "spi_nor";
- };
- };
-
- /* serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0_0_tx_rx" ;
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_1_tx_rx" ;
- };
- };
-
- watchdog_pins: watchdog-pins {
- mux {
- function = "watchdog";
- groups = "watchdog";
- };
- };
-};
-
-&bch {
- status = "okay";
-};
-
-&btif {
- status = "okay";
-};
-
-&cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
- status = "okay";
-};
-
-&eth {
- status = "okay";
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&gsw {
- mediatek,mdio = <&mdio>;
- mediatek,portmap = "llllw";
- mediatek,mdio_master_pinmux = <0>;
- reset-gpios = <&pio 54 0>;
- interrupt-parent = <&pio>;
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
-
- port5: port@5 {
- compatible = "mediatek,mt753x-port";
- reg = <5>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port6: port@6 {
- compatible = "mediatek,mt753x-port";
- reg = <6>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&emmc_pins_default>;
- pinctrl-1 = <&emmc_pins_uhs>;
- status = "okay";
- bus-width = <8>;
- max-frequency = <50000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- non-removable;
-};
-
-&mmc1 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sd0_pins_default>;
- pinctrl-1 = <&sd0_pins_uhs>;
- status = "okay";
- bus-width = <4>;
- max-frequency = <50000000>;
- cap-sd-highspeed;
- r_smpl = <1>;
- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_3p3v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
- pinctrl-names = "default";
- pinctrl-0 = <&parallel_nand_pins>;
- status = "disabled";
-};
-
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pins>;
- status = "okay";
-};
-
-&pwrap {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_bus_pins>;
-
- status = "okay";
-};
-
-&snfi {
- pinctrl-names = "default";
- pinctrl-0 = <&serial_nand_pins>;
- status = "okay";
-
- spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <104000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "preloader";
- reg = <0x00000 0x0080000>;
- read-only;
- };
-
- partition@80000 {
- label = "ATF";
- reg = <0x80000 0x0040000>;
- read-only;
- };
-
- partition@c0000 {
- label = "uboot";
- reg = <0xc0000 0x0080000>;
- read-only;
- };
-
- partition@140000 {
- label = "uboot-env";
- reg = <0x140000 0x0080000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "factory";
- reg = <0x1c0000 0x0040000>;
- read-only;
- };
-
- partition@200000 {
- label = "firmware";
- reg = <0x200000 0x2000000>;
- };
-
- partition@2200000 {
- label = "reserved";
- reg = <0x2200000 0x4000000>;
- };
- };
- };
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic1_pins>;
- status = "okay";
-};
-
-&ssusb {
- vusb33-supply = <&reg_3p3v>;
- vbus-supply = <&reg_5v>;
- status = "okay";
-};
-
-&u3phy {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&watchdog {
- pinctrl-names = "default";
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
-};
diff --git a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
deleted file mode 100644
index 1002ad2b77..0000000000
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts
+++ /dev/null
@@ -1,609 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <ming.huang@mediatek.com>
- * Sean Wang <sean.wang@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
- */
-
-/dts-v1/;
-#include <dt-bindings/input/input.h>
-#include <dt-bindings/gpio/gpio.h>
-
-#include "mt7622.dtsi"
-#include "mt6380.dtsi"
-
-/ {
- model = "MediaTek MT7622 RFB1 board";
- compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
-
- aliases {
- serial0 = &uart0;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- bootargs = "earlycon=uart8250,mmio32,0x11002000 console=ttyS0,115200n1 swiotlb=512";
- };
-
- cpus {
- cpu@0 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
-
- cpu@1 {
- proc-supply = <&mt6380_vcpu_reg>;
- sram-supply = <&mt6380_vm_reg>;
- };
- };
-
- gpio-keys {
- compatible = "gpio-keys";
- poll-interval = <100>;
-
- factory {
- label = "factory";
- linux,code = <BTN_0>;
- gpios = <&pio 0 0>;
- };
-
- wps {
- label = "wps";
- linux,code = <KEY_WPS_BUTTON>;
- gpios = <&pio 102 0>;
- };
- };
-
- gsw: gsw@0 {
- compatible = "mediatek,mt753x";
- mediatek,ethsys = <&ethsys>;
- #address-cells = <1>;
- #size-cells = <0>;
- };
-
- memory {
- reg = <0 0x40000000 0 0x3F000000>;
- };
-
- reg_1p8v: regulator-1p8v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-1.8V";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- regulator-always-on;
- };
-
- reg_3p3v: regulator-3p3v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-3.3V";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- regulator-boot-on;
- regulator-always-on;
- };
-
- reg_5v: regulator-5v {
- compatible = "regulator-fixed";
- regulator-name = "fixed-5V";
- regulator-min-microvolt = <5000000>;
- regulator-max-microvolt = <5000000>;
- regulator-boot-on;
- regulator-always-on;
- };
-};
-
-&pcie {
- pinctrl-names = "default", "pcie1_pins";
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-1 = <&pcie1_pins>;
- status = "okay";
-
- pcie@0,0 {
- status = "okay";
- };
-
- pcie@1,0 {
- status = "okay";
- };
-
-};
-
-&pio {
- /* eMMC is shared pin with parallel NAND */
- emmc_pins_default: emmc-pins-default {
- mux {
- function = "emmc", "emmc_rst";
- groups = "emmc";
- };
-
- /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7",
- * "NRB","NCLE" pins are used as DAT0,DAT1,DAT2,DAT3,DAT4,
- * DAT5,DAT6,DAT7,CMD,CLK for eMMC respectively
- */
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- bias-pull-down;
- };
- };
-
- emmc_pins_uhs: emmc-pins-uhs {
- mux {
- function = "emmc";
- groups = "emmc";
- };
-
- conf-cmd-dat {
- pins = "NDL0", "NDL1", "NDL2",
- "NDL3", "NDL4", "NDL5",
- "NDL6", "NDL7", "NRB";
- input-enable;
- drive-strength = <4>;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "NCLE";
- drive-strength = <4>;
- bias-pull-down;
- };
- };
-
- eth_pins: eth-pins {
- mux {
- function = "eth";
- groups = "mdc_mdio", "rgmii_via_gmac2";
- };
- };
-
- i2c1_pins: i2c1-pins {
- mux {
- function = "i2c";
- groups = "i2c1_0";
- };
- };
-
- i2c2_pins: i2c2-pins {
- mux {
- function = "i2c";
- groups = "i2c2_0";
- };
- };
-
- i2s1_pins: i2s1-pins {
- mux {
- function = "i2s";
- groups = "i2s_out_mclk_bclk_ws",
- "i2s1_in_data",
- "i2s1_out_data";
- };
-
- conf {
- pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
- "I2S_WS", "I2S_MCLK";
- drive-strength = <12>;
- bias-pull-down;
- };
- };
-
- irrx_pins: irrx-pins {
- mux {
- function = "ir";
- groups = "ir_1_rx";
- };
- };
-
- irtx_pins: irtx-pins {
- mux {
- function = "ir";
- groups = "ir_1_tx";
- };
- };
-
- /* Parallel nand is shared pin with eMMC */
- parallel_nand_pins: parallel-nand-pins {
- mux {
- function = "flash";
- groups = "par_nand";
- };
- };
-
- pcie0_pins: pcie0-pins {
- mux {
- function = "pcie";
- groups = "pcie0_pad_perst",
- "pcie0_1_waken",
- "pcie0_1_clkreq";
- };
- };
-
- pcie1_pins: pcie1-pins {
- mux {
- function = "pcie";
- groups = "pcie1_pad_perst",
- "pcie1_0_waken",
- "pcie1_0_clkreq";
- };
- };
-
- pmic_bus_pins: pmic-bus-pins {
- mux {
- function = "pmic";
- groups = "pmic_bus";
- };
- };
-
- pwm7_pins: pwm1-2-pins {
- mux {
- function = "pwm";
- groups = "pwm_ch7_2";
- };
- };
-
- wled_pins: wled-pins {
- mux {
- function = "led";
- groups = "wled";
- };
- };
-
- sd0_pins_default: sd0-pins-default {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- /* "I2S2_OUT, "I2S4_IN"", "I2S3_IN", "I2S2_IN",
- * "I2S4_OUT", "I2S3_OUT" are used as DAT0, DAT1,
- * DAT2, DAT3, CMD, CLK for SD respectively.
- */
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- drive-strength = <8>;
- bias-pull-up;
- };
- conf-clk {
- pins = "I2S3_OUT";
- drive-strength = <12>;
- bias-pull-down;
- };
- conf-cd {
- pins = "TXD3";
- bias-pull-up;
- };
- };
-
- sd0_pins_uhs: sd0-pins-uhs {
- mux {
- function = "sd";
- groups = "sd_0";
- };
-
- conf-cmd-data {
- pins = "I2S2_OUT", "I2S4_IN", "I2S3_IN",
- "I2S2_IN","I2S4_OUT";
- input-enable;
- bias-pull-up;
- };
-
- conf-clk {
- pins = "I2S3_OUT";
- bias-pull-down;
- };
- };
-
- /* Serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- spic0_pins: spic0-pins {
- mux {
- function = "spi";
- groups = "spic0_0";
- };
- };
-
- spic1_pins: spic1-pins {
- mux {
- function = "spi";
- groups = "spic1_0";
- };
- };
-
- /* SPI-NOR is shared pin with serial NAND */
- spi_nor_pins: spi-nor-pins {
- mux {
- function = "flash";
- groups = "spi_nor";
- };
- };
-
- /* serial NAND is shared pin with SPI-NOR */
- serial_nand_pins: serial-nand-pins {
- mux {
- function = "flash";
- groups = "snfi";
- };
- };
-
- uart0_pins: uart0-pins {
- mux {
- function = "uart";
- groups = "uart0_0_tx_rx" ;
- };
- };
-
- uart2_pins: uart2-pins {
- mux {
- function = "uart";
- groups = "uart2_1_tx_rx" ;
- };
- };
-
- watchdog_pins: watchdog-pins {
- mux {
- function = "watchdog";
- groups = "watchdog";
- };
- };
-};
-
-&bch {
- status = "okay";
-};
-
-&btif {
- status = "okay";
-};
-
-&cir {
- pinctrl-names = "default";
- pinctrl-0 = <&irrx_pins>;
- status = "okay";
-};
-
-&eth {
- status = "okay";
- gmac0: mac@0 {
- compatible = "mediatek,eth-mac";
- reg = <0>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- gmac1: mac@1 {
- compatible = "mediatek,eth-mac";
- reg = <1>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- pause;
- };
- };
- mdio: mdio-bus {
- #address-cells = <1>;
- #size-cells = <0>;
- };
-};
-
-&gsw {
- mediatek,mdio = <&mdio>;
- mediatek,portmap = "llllw";
- mediatek,mdio_master_pinmux = <0>;
- reset-gpios = <&pio 54 0>;
- interrupt-parent = <&pio>;
- interrupts = <53 IRQ_TYPE_LEVEL_HIGH>;
- status = "okay";
-
- port5: port@5 {
- compatible = "mediatek,mt753x-port";
- reg = <5>;
- phy-mode = "rgmii";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
-
- port6: port@6 {
- compatible = "mediatek,mt753x-port";
- reg = <6>;
- phy-mode = "sgmii";
- fixed-link {
- speed = <2500>;
- full-duplex;
- };
- };
-};
-
-&i2c1 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c1_pins>;
- status = "okay";
-};
-
-&i2c2 {
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_pins>;
- status = "okay";
-};
-
-&mmc0 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&emmc_pins_default>;
- pinctrl-1 = <&emmc_pins_uhs>;
- status = "okay";
- bus-width = <8>;
- max-frequency = <50000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_1p8v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_0_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
- non-removable;
-};
-
-&mmc1 {
- pinctrl-names = "default", "state_uhs";
- pinctrl-0 = <&sd0_pins_default>;
- pinctrl-1 = <&sd0_pins_uhs>;
- status = "okay";
- bus-width = <4>;
- max-frequency = <50000000>;
- cap-sd-highspeed;
- r_smpl = <1>;
- cd-gpios = <&pio 81 GPIO_ACTIVE_LOW>;
- vmmc-supply = <&reg_3p3v>;
- vqmmc-supply = <&reg_3p3v>;
- assigned-clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>;
- assigned-clock-parents = <&topckgen CLK_TOP_UNIV48M>;
-};
-
-&nandc {
- pinctrl-names = "default";
- pinctrl-0 = <&parallel_nand_pins>;
- status = "disabled";
-};
-
-&nor_flash {
- pinctrl-names = "default";
- pinctrl-0 = <&spi_nor_pins>;
- status = "disabled";
-
- flash@0 {
- compatible = "jedec,spi-nor";
- reg = <0>;
- };
-};
-
-&pwm {
- pinctrl-names = "default";
- pinctrl-0 = <&pwm7_pins>;
- status = "okay";
-};
-
-&pwrap {
- pinctrl-names = "default";
- pinctrl-0 = <&pmic_bus_pins>;
-
- status = "okay";
-};
-
-&snfi {
- pinctrl-names = "default";
- pinctrl-0 = <&serial_nand_pins>;
- status = "okay";
-
- spi_nand@0 {
- #address-cells = <1>;
- #size-cells = <1>;
- compatible = "spi-nand";
- spi-max-frequency = <104000000>;
- reg = <0>;
-
- partitions {
- compatible = "fixed-partitions";
- #address-cells = <1>;
- #size-cells = <1>;
-
- partition@0 {
- label = "preloader";
- reg = <0x00000 0x0080000>;
- read-only;
- };
-
- partition@80000 {
- label = "ATF";
- reg = <0x80000 0x0040000>;
- read-only;
- };
-
- partition@c0000 {
- label = "uboot";
- reg = <0xc0000 0x0080000>;
- read-only;
- };
-
- partition@140000 {
- label = "uboot-env";
- reg = <0x140000 0x0080000>;
- read-only;
- };
-
- partition@1c0000 {
- label = "factory";
- reg = <0x1c0000 0x0040000>;
- read-only;
- };
-
- partition@200000 {
- label = "firmware";
- reg = <0x200000 0x2000000>;
- };
-
- partition@2200000 {
- label = "reserved";
- reg = <0x2200000 0x4000000>;
- };
- };
- };
-};
-
-&spi0 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic0_pins>;
- status = "okay";
-};
-
-&spi1 {
- pinctrl-names = "default";
- pinctrl-0 = <&spic1_pins>;
- status = "okay";
-};
-
-&ssusb {
- vusb33-supply = <&reg_3p3v>;
- vbus-supply = <&reg_5v>;
- status = "okay";
-};
-
-&u3phy {
- status = "okay";
-};
-
-&uart0 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart0_pins>;
- status = "okay";
-};
-
-&uart2 {
- pinctrl-names = "default";
- pinctrl-0 = <&uart2_pins>;
- status = "okay";
-};
-
-&watchdog {
- pinctrl-names = "default";
- pinctrl-0 = <&watchdog_pins>;
- status = "okay";
-};
diff --git a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi
deleted file mode 100644
index 934b4d9383..0000000000
--- a/target/linux/mediatek/files-4.19/arch/arm64/boot/dts/mediatek/mt7622.dtsi
+++ /dev/null
@@ -1,914 +0,0 @@
-/*
- * Copyright (c) 2017 MediaTek Inc.
- * Author: Ming Huang <ming.huang@mediatek.com>
- * Sean Wang <sean.wang@mediatek.com>
- *
- * SPDX-License-Identifier: (GPL-2.0-only OR MIT)
- */
-
-#include <dt-bindings/interrupt-controller/irq.h>
-#include <dt-bindings/interrupt-controller/arm-gic.h>
-#include <dt-bindings/clock/mt7622-clk.h>
-#include <dt-bindings/phy/phy.h>
-#include <dt-bindings/power/mt7622-power.h>
-#include <dt-bindings/reset/mt7622-reset.h>
-#include <dt-bindings/thermal/thermal.h>
-
-/ {
- compatible = "mediatek,mt7622";
- interrupt-parent = <&sysirq>;
- #address-cells = <2>;
- #size-cells = <2>;
-
- cpu_opp_table: opp-table {
- compatible = "operating-points-v2";
- opp-shared;
- opp-300000000 {
- opp-hz = /bits/ 64 <30000000>;
- opp-microvolt = <950000>;
- };
-
- opp-437500000 {
- opp-hz = /bits/ 64 <437500000>;
- opp-microvolt = <1000000>;
- };
-
- opp-600000000 {
- opp-hz = /bits/ 64 <600000000>;
- opp-microvolt = <1050000>;
- };
-
- opp-812500000 {
- opp-hz = /bits/ 64 <812500000>;
- opp-microvolt = <1100000>;
- };
-
- opp-1025000000 {
- opp-hz = /bits/ 64 <1025000000>;
- opp-microvolt = <1150000>;
- };
-
- opp-1137500000 {
- opp-hz = /bits/ 64 <1137500000>;
- opp-microvolt = <1200000>;
- };
-
- opp-1262500000 {
- opp-hz = /bits/ 64 <1262500000>;
- opp-microvolt = <1250000>;
- };
-
- opp-1350000000 {
- opp-hz = /bits/ 64 <1350000000>;
- opp-microvolt = <1310000>;
- };
- };
-
- cpus {
- #address-cells = <2>;
- #size-cells = <0>;
-
- cpu0: cpu@0 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x0>;
- clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
- <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cpu_opp_table>;
- #cooling-cells = <2>;
- enable-method = "psci";
- clock-frequency = <1300000000>;
- };
-
- cpu1: cpu@1 {
- device_type = "cpu";
- compatible = "arm,cortex-a53", "arm,armv8";
- reg = <0x0 0x1>;
- clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
- <&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
- clock-names = "cpu", "intermediate";
- operating-points-v2 = <&cpu_opp_table>;
- #cooling-cells = <2>;
- enable-method = "psci";
- clock-frequency = <1300000000>;
- };
- };
-
- pwrap_clk: dummy40m {
- compatible = "fixed-clock";
- clock-frequency = <40000000>;
- #clock-cells = <0>;
- };
-
- clk25m: oscillator {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <25000000>;
- clock-output-names = "clkxtal";
- };
-
- psci {
- compatible = "arm,psci-0.2";
- method = "smc";
- };
-
- reserved-memory {
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
-
- /* 192 KiB reserved for ARM Trusted Firmware (BL31) */
- secmon_reserved: secmon@43000000 {
- reg = <0 0x43000000 0 0x30000>;
- no-map;
- };
- };
-
- thermal-zones {
- cpu_thermal: cpu-thermal {
- polling-delay-passive = <1000>;
- polling-delay = <1000>;
-
- thermal-sensors = <&thermal 0>;
-
- trips {
- cpu_passive: cpu-passive {
- temperature = <47000>;
- hysteresis = <2000>;
- type = "passive";
- };
-
- cpu_active: cpu-active {
- temperature = <67000>;
- hysteresis = <2000>;
- type = "active";
- };
-
- cpu_hot: cpu-hot {
- temperature = <87000>;
- hysteresis = <2000>;
- type = "hot";
- };
-
- cpu-crit {
- temperature = <107000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
-
- cooling-maps {
- map0 {
- trip = <&cpu_passive>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map1 {
- trip = <&cpu_active>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
-
- map2 {
- trip = <&cpu_hot>;
- cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
- };
- };
- };
- };
-
- timer {
- compatible = "arm,armv8-timer";
- interrupt-parent = <&gic>;
- interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>,
- <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) |
- IRQ_TYPE_LEVEL_HIGH)>;
- };
-
- infracfg: infracfg@10000000 {
- compatible = "mediatek,mt7622-infracfg",
- "syscon";
- reg = <0 0x10000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pwrap: pwrap@10001000 {
- compatible = "mediatek,mt7622-pwrap";
- reg = <0 0x10001000 0 0x250>;
- reg-names = "pwrap";
- clocks = <&infracfg CLK_INFRA_PMIC_PD>, <&pwrap_clk>;
- clock-names = "spi", "wrap";
- resets = <&infracfg MT7622_INFRA_PMIC_WRAP_RST>;
- reset-names = "pwrap";
- interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>;
- status = "disabled";
- };
-
- pericfg: pericfg@10002000 {
- compatible = "mediatek,mt7622-pericfg",
- "syscon";
- reg = <0 0x10002000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- scpsys: scpsys@10006000 {
- compatible = "mediatek,mt7622-scpsys",
- "syscon";
- #power-domain-cells = <1>;
- reg = <0 0x10006000 0 0x1000>;
- interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 166 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 167 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 168 IRQ_TYPE_LEVEL_LOW>;
- infracfg = <&infracfg>;
- clocks = <&topckgen CLK_TOP_HIF_SEL>;
- clock-names = "hif_sel";
- };
-
- cir: cir@10009000 {
- compatible = "mediatek,mt7622-cir";
- reg = <0 0x10009000 0 0x1000>;
- interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&infracfg CLK_INFRA_IRRX_PD>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "clk", "bus";
- status = "disabled";
- };
-
- sysirq: interrupt-controller@10200620 {
- compatible = "mediatek,mt7622-sysirq",
- "mediatek,mt6577-sysirq";
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10200620 0 0x20>;
- };
-
- efuse: efuse@10206000 {
- compatible = "mediatek,mt7622-efuse",
- "mediatek,efuse";
- reg = <0 0x10206000 0 0x1000>;
- #address-cells = <1>;
- #size-cells = <1>;
-
- thermal_calibration: calib@198 {
- reg = <0x198 0xc>;
- };
- };
-
- apmixedsys: apmixedsys@10209000 {
- compatible = "mediatek,mt7622-apmixedsys",
- "syscon";
- reg = <0 0x10209000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- topckgen: topckgen@10210000 {
- compatible = "mediatek,mt7622-topckgen",
- "syscon";
- reg = <0 0x10210000 0 0x1000>;
- #clock-cells = <1>;
- };
-
- rng: rng@1020f000 {
- compatible = "mediatek,mt7622-rng",
- "mediatek,mt7623-rng";
- reg = <0 0x1020f000 0 0x1000>;
- clocks = <&infracfg CLK_INFRA_TRNG>;
- clock-names = "rng";
- };
-
- pio: pinctrl@10211000 {
- compatible = "mediatek,mt7622-pinctrl";
- reg = <0 0x10211000 0 0x1000>,
- <0 0x10005000 0 0x1000>;
- reg-names = "base", "eint";
- gpio-controller;
- #gpio-cells = <2>;
- gpio-ranges = <&pio 0 0 103>;
- interrupt-controller;
- interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-parent = <&gic>;
- #interrupt-cells = <2>;
- };
-
- watchdog: watchdog@10212000 {
- compatible = "mediatek,mt7622-wdt",
- "mediatek,mt6589-wdt";
- reg = <0 0x10212000 0 0x800>;
- };
-
- rtc: rtc@10212800 {
- compatible = "mediatek,mt7622-rtc",
- "mediatek,soc-rtc";
- reg = <0 0x10212800 0 0x200>;
- interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_RTC>;
- clock-names = "rtc";
- };
-
- gic: interrupt-controller@10300000 {
- compatible = "arm,gic-400";
- interrupt-controller;
- #interrupt-cells = <3>;
- interrupt-parent = <&gic>;
- reg = <0 0x10310000 0 0x1000>,
- <0 0x10320000 0 0x1000>,
- <0 0x10340000 0 0x2000>,
- <0 0x10360000 0 0x2000>;
- };
-
- auxadc: adc@11001000 {
- compatible = "mediatek,mt7622-auxadc";
- reg = <0 0x11001000 0 0x1000>;
- clocks = <&pericfg CLK_PERI_AUXADC_PD>;
- clock-names = "main";
- #io-channel-cells = <1>;
- };
-
- uart0: serial@11002000 {
- compatible = "mediatek,mt7622-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11002000 0 0x400>;
- interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART0_PD>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart1: serial@11003000 {
- compatible = "mediatek,mt7622-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11003000 0 0x400>;
- interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART1_PD>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart2: serial@11004000 {
- compatible = "mediatek,mt7622-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11004000 0 0x400>;
- interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART2_PD>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- uart3: serial@11005000 {
- compatible = "mediatek,mt7622-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11005000 0 0x400>;
- interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART3_PD>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- pwm: pwm@11006000 {
- compatible = "mediatek,mt7622-pwm";
- reg = <0 0x11006000 0 0x1000>;
- interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_PWM_SEL>,
- <&pericfg CLK_PERI_PWM_PD>,
- <&pericfg CLK_PERI_PWM1_PD>,
- <&pericfg CLK_PERI_PWM2_PD>,
- <&pericfg CLK_PERI_PWM3_PD>,
- <&pericfg CLK_PERI_PWM4_PD>,
- <&pericfg CLK_PERI_PWM5_PD>,
- <&pericfg CLK_PERI_PWM6_PD>;
- clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4",
- "pwm5", "pwm6";
- status = "disabled";
- };
-
- i2c0: i2c@11007000 {
- compatible = "mediatek,mt7622-i2c";
- reg = <0 0x11007000 0 0x90>,
- <0 0x11000100 0 0x80>;
- interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C0_PD>,
- <&pericfg CLK_PERI_AP_DMA_PD>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c1: i2c@11008000 {
- compatible = "mediatek,mt7622-i2c";
- reg = <0 0x11008000 0 0x90>,
- <0 0x11000180 0 0x80>;
- interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C1_PD>,
- <&pericfg CLK_PERI_AP_DMA_PD>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- i2c2: i2c@11009000 {
- compatible = "mediatek,mt7622-i2c";
- reg = <0 0x11009000 0 0x90>,
- <0 0x11000200 0 0x80>;
- interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_LOW>;
- clock-div = <16>;
- clocks = <&pericfg CLK_PERI_I2C2_PD>,
- <&pericfg CLK_PERI_AP_DMA_PD>;
- clock-names = "main", "dma";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi0: spi@1100a000 {
- compatible = "mediatek,mt7622-spi";
- reg = <0 0x1100a000 0 0x100>;
- interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI0_SEL>,
- <&pericfg CLK_PERI_SPI0_PD>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- thermal: thermal@1100b000 {
- #thermal-sensor-cells = <1>;
- compatible = "mediatek,mt7622-thermal";
- reg = <0 0x1100b000 0 0x1000>;
- interrupts = <0 78 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_THERM_PD>,
- <&pericfg CLK_PERI_AUXADC_PD>;
- clock-names = "therm", "auxadc";
- resets = <&pericfg MT7622_PERI_THERM_SW_RST>;
- reset-names = "therm";
- mediatek,auxadc = <&auxadc>;
- mediatek,apmixedsys = <&apmixedsys>;
- nvmem-cells = <&thermal_calibration>;
- nvmem-cell-names = "calibration-data";
- };
-
- btif: serial@1100c000 {
- compatible = "mediatek,mt7622-btif",
- "mediatek,mtk-btif";
- reg = <0 0x1100c000 0 0x1000>;
- interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_BTIF_PD>;
- clock-names = "main";
- reg-shift = <2>;
- reg-io-width = <4>;
- status = "disabled";
-
- bluetooth {
- compatible = "mediatek,mt7622-bluetooth";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
- clocks = <&clk25m>;
- clock-names = "ref";
- };
- };
-
- nandc: nfi@1100d000 {
- compatible = "mediatek,mt7622-nfc";
- reg = <0 0x1100D000 0 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_NFI_PD>,
- <&pericfg CLK_PERI_SNFI_PD>;
- clock-names = "nfi_clk", "pad_clk";
- ecc-engine = <&bch>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- bch: ecc@1100e000 {
- compatible = "mediatek,mt7622-ecc";
- reg = <0 0x1100e000 0 0x1000>;
- interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_NFIECC_PD>;
- clock-names = "nfiecc_clk";
- status = "disabled";
- };
-
- nor_flash: spi@11014000 {
- compatible = "mediatek,mt7622-nor",
- "mediatek,mt8173-nor";
- reg = <0 0x11014000 0 0xe0>;
- clocks = <&pericfg CLK_PERI_FLASH_PD>,
- <&topckgen CLK_TOP_FLASH_SEL>;
- clock-names = "spi", "sf";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- snfi: spi@1100d000 {
- compatible = "mediatek,mt7622-snfi";
- reg = <0 0x1100d000 0 0x1000>;
- interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_NFI_PD>,
- <&pericfg CLK_PERI_SNFI_PD>;
- clock-names = "nfi_clk", "spi_clk";
- ecc-engine = <&bch>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- spi1: spi@11016000 {
- compatible = "mediatek,mt7622-spi";
- reg = <0 0x11016000 0 0x100>;
- interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_SYSPLL3_D2>,
- <&topckgen CLK_TOP_SPI1_SEL>,
- <&pericfg CLK_PERI_SPI1_PD>;
- clock-names = "parent-clk", "sel-clk", "spi-clk";
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- uart4: serial@11019000 {
- compatible = "mediatek,mt7622-uart",
- "mediatek,mt6577-uart";
- reg = <0 0x11019000 0 0x400>;
- interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_UART_SEL>,
- <&pericfg CLK_PERI_UART4_PD>;
- clock-names = "baud", "bus";
- status = "disabled";
- };
-
- audsys: clock-controller@11220000 {
- compatible = "mediatek,mt7622-audsys", "syscon";
- reg = <0 0x11220000 0 0x2000>;
- #clock-cells = <1>;
-
- afe: audio-controller {
- compatible = "mediatek,mt7622-audio";
- interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
- interrupt-names = "afe", "asys";
-
- clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
- <&topckgen CLK_TOP_AUD1_SEL>,
- <&topckgen CLK_TOP_AUD2_SEL>,
- <&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
- <&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
- <&topckgen CLK_TOP_I2S0_MCK_SEL>,
- <&topckgen CLK_TOP_I2S1_MCK_SEL>,
- <&topckgen CLK_TOP_I2S2_MCK_SEL>,
- <&topckgen CLK_TOP_I2S3_MCK_SEL>,
- <&topckgen CLK_TOP_I2S0_MCK_DIV>,
- <&topckgen CLK_TOP_I2S1_MCK_DIV>,
- <&topckgen CLK_TOP_I2S2_MCK_DIV>,
- <&topckgen CLK_TOP_I2S3_MCK_DIV>,
- <&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
- <&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
- <&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
- <&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
- <&audsys CLK_AUDIO_I2SO1>,
- <&audsys CLK_AUDIO_I2SO2>,
- <&audsys CLK_AUDIO_I2SO3>,
- <&audsys CLK_AUDIO_I2SO4>,
- <&audsys CLK_AUDIO_I2SIN1>,
- <&audsys CLK_AUDIO_I2SIN2>,
- <&audsys CLK_AUDIO_I2SIN3>,
- <&audsys CLK_AUDIO_I2SIN4>,
- <&audsys CLK_AUDIO_ASRCO1>,
- <&audsys CLK_AUDIO_ASRCO2>,
- <&audsys CLK_AUDIO_ASRCO3>,
- <&audsys CLK_AUDIO_ASRCO4>,
- <&audsys CLK_AUDIO_AFE>,
- <&audsys CLK_AUDIO_AFE_CONN>,
- <&audsys CLK_AUDIO_A1SYS>,
- <&audsys CLK_AUDIO_A2SYS>;
-
- clock-names = "infra_sys_audio_clk",
- "top_audio_mux1_sel",
- "top_audio_mux2_sel",
- "top_audio_a1sys_hp",
- "top_audio_a2sys_hp",
- "i2s0_src_sel",
- "i2s1_src_sel",
- "i2s2_src_sel",
- "i2s3_src_sel",
- "i2s0_src_div",
- "i2s1_src_div",
- "i2s2_src_div",
- "i2s3_src_div",
- "i2s0_mclk_en",
- "i2s1_mclk_en",
- "i2s2_mclk_en",
- "i2s3_mclk_en",
- "i2so0_hop_ck",
- "i2so1_hop_ck",
- "i2so2_hop_ck",
- "i2so3_hop_ck",
- "i2si0_hop_ck",
- "i2si1_hop_ck",
- "i2si2_hop_ck",
- "i2si3_hop_ck",
- "asrc0_out_ck",
- "asrc1_out_ck",
- "asrc2_out_ck",
- "asrc3_out_ck",
- "audio_afe_pd",
- "audio_afe_conn_pd",
- "audio_a1sys_pd",
- "audio_a2sys_pd";
-
- assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
- <&topckgen CLK_TOP_A2SYS_HP_SEL>,
- <&topckgen CLK_TOP_A1SYS_HP_DIV>,
- <&topckgen CLK_TOP_A2SYS_HP_DIV>;
- assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
- <&topckgen CLK_TOP_AUD2PLL>;
- assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
- };
- };
-
- mmc0: mmc@11230000 {
- compatible = "mediatek,mt7622-mmc";
- reg = <0 0x11230000 0 0x1000>;
- interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_0_PD>,
- <&topckgen CLK_TOP_MSDC50_0_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- mmc1: mmc@11240000 {
- compatible = "mediatek,mt7622-mmc";
- reg = <0 0x11240000 0 0x1000>;
- interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pericfg CLK_PERI_MSDC30_1_PD>,
- <&topckgen CLK_TOP_AXI_SEL>;
- clock-names = "source", "hclk";
- status = "disabled";
- };
-
- wmac: wmac@18000000 {
- compatible = "mediatek,mt7622-wmac";
- reg = <0 0x18000000 0 0x100000>;
- interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_LOW>;
-
- mediatek,infracfg = <&infracfg>;
- status = "disabled";
-
- power-domains = <&scpsys MT7622_POWER_DOMAIN_WB>;
- };
-
- ssusbsys: ssusbsys@1a000000 {
- compatible = "mediatek,mt7622-ssusbsys",
- "syscon";
- reg = <0 0x1a000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- ssusb: usb@1a0c0000 {
- compatible = "mediatek,mt7622-xhci",
- "mediatek,mtk-xhci";
- reg = <0 0x1a0c0000 0 0x01000>,
- <0 0x1a0c4700 0 0x0100>;
- reg-names = "mac", "ippc";
- interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_LOW>;
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF1>;
- clocks = <&ssusbsys CLK_SSUSB_SYS_EN>,
- <&ssusbsys CLK_SSUSB_REF_EN>,
- <&ssusbsys CLK_SSUSB_MCU_EN>,
- <&ssusbsys CLK_SSUSB_DMA_EN>;
- clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
- phys = <&u2port0 PHY_TYPE_USB2>,
- <&u3port0 PHY_TYPE_USB3>,
- <&u2port1 PHY_TYPE_USB2>;
-
- status = "disabled";
- };
-
- u3phy: usb-phy@1a0c4000 {
- compatible = "mediatek,mt7622-u3phy",
- "mediatek,generic-tphy-v1";
- reg = <0 0x1a0c4000 0 0x700>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- u2port0: usb-phy@1a0c4800 {
- reg = <0 0x1a0c4800 0 0x0100>;
- #phy-cells = <1>;
- clocks = <&ssusbsys CLK_SSUSB_U2_PHY_EN>;
- clock-names = "ref";
- };
-
- u3port0: usb-phy@1a0c4900 {
- reg = <0 0x1a0c4900 0 0x0700>;
- #phy-cells = <1>;
- clocks = <&clk25m>;
- clock-names = "ref";
- };
-
- u2port1: usb-phy@1a0c5000 {
- reg = <0 0x1a0c5000 0 0x0100>;
- #phy-cells = <1>;
- clocks = <&ssusbsys CLK_SSUSB_U2_PHY_1P_EN>;
- clock-names = "ref";
- };
- };
-
- pciesys: pciesys@1a100800 {
- compatible = "mediatek,mt7622-pciesys",
- "syscon";
- reg = <0 0x1a100800 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- pcie: pcie@1a140000 {
- compatible = "mediatek,mt7622-pcie";
- device_type = "pci";
- reg = <0 0x1a140000 0 0x1000>,
- <0 0x1a143000 0 0x1000>,
- <0 0x1a145000 0 0x1000>;
- reg-names = "subsys", "port0", "port1";
- #address-cells = <3>;
- #size-cells = <2>;
- interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 229 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&pciesys CLK_PCIE_P0_MAC_EN>,
- <&pciesys CLK_PCIE_P1_MAC_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AHB_EN>,
- <&pciesys CLK_PCIE_P0_AUX_EN>,
- <&pciesys CLK_PCIE_P1_AUX_EN>,
- <&pciesys CLK_PCIE_P0_AXI_EN>,
- <&pciesys CLK_PCIE_P1_AXI_EN>,
- <&pciesys CLK_PCIE_P0_OBFF_EN>,
- <&pciesys CLK_PCIE_P1_OBFF_EN>,
- <&pciesys CLK_PCIE_P0_PIPE_EN>,
- <&pciesys CLK_PCIE_P1_PIPE_EN>;
- clock-names = "sys_ck0", "sys_ck1", "ahb_ck0", "ahb_ck1",
- "aux_ck0", "aux_ck1", "axi_ck0", "axi_ck1",
- "obff_ck0", "obff_ck1", "pipe_ck0", "pipe_ck1";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- bus-range = <0x00 0xff>;
- ranges = <0x82000000 0 0x20000000 0x0 0x20000000 0 0x10000000>;
- status = "disabled";
-
- pcie0: pcie@0,0 {
- reg = <0x0000 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- status = "disabled";
-
- num-lanes = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc0 0>,
- <0 0 0 2 &pcie_intc0 1>,
- <0 0 0 3 &pcie_intc0 2>,
- <0 0 0 4 &pcie_intc0 3>;
- pcie_intc0: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
-
- pcie1: pcie@1,0 {
- reg = <0x0800 0 0 0 0>;
- #address-cells = <3>;
- #size-cells = <2>;
- #interrupt-cells = <1>;
- ranges;
- status = "disabled";
-
- num-lanes = <1>;
- interrupt-map-mask = <0 0 0 7>;
- interrupt-map = <0 0 0 1 &pcie_intc1 0>,
- <0 0 0 2 &pcie_intc1 1>,
- <0 0 0 3 &pcie_intc1 2>,
- <0 0 0 4 &pcie_intc1 3>;
- pcie_intc1: interrupt-controller {
- interrupt-controller;
- #address-cells = <0>;
- #interrupt-cells = <1>;
- };
- };
- };
-
- sata: sata@1a200000 {
- compatible = "mediatek,mt7622-ahci",
- "mediatek,mtk-ahci";
- reg = <0 0x1a200000 0 0x1100>;
- interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "hostc";
- clocks = <&pciesys CLK_SATA_AHB_EN>,
- <&pciesys CLK_SATA_AXI_EN>,
- <&pciesys CLK_SATA_ASIC_EN>,
- <&pciesys CLK_SATA_RBC_EN>,
- <&pciesys CLK_SATA_PM_EN>;
- clock-names = "ahb", "axi", "asic", "rbc", "pm";
- phys = <&sata_port PHY_TYPE_SATA>;
- phy-names = "sata-phy";
- ports-implemented = <0x1>;
- power-domains = <&scpsys MT7622_POWER_DOMAIN_HIF0>;
- resets = <&pciesys MT7622_SATA_AXI_BUS_RST>,
- <&pciesys MT7622_SATA_PHY_SW_RST>,
- <&pciesys MT7622_SATA_PHY_REG_RST>;
- reset-names = "axi", "sw", "reg";
- mediatek,phy-mode = <&pciesys>;
- status = "disabled";
- };
-
- sata_phy: sata-phy@1a243000 {
- compatible = "mediatek,generic-tphy-v1";
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- status = "disabled";
-
- sata_port: sata-phy@1a243000 {
- reg = <0 0x1a243000 0 0x0100>;
- clocks = <&topckgen CLK_TOP_ETH_500M>;
- clock-names = "ref";
- #phy-cells = <1>;
- };
- };
-
- ethsys: syscon@1b000000 {
- compatible = "mediatek,mt7622-ethsys",
- "syscon";
- reg = <0 0x1b000000 0 0x1000>;
- #clock-cells = <1>;
- #reset-cells = <1>;
- };
-
- hsdma: dma-controller@1b007000 {
- compatible = "mediatek,mt7622-hsdma";
- reg = <0 0x1b007000 0 0x1000>;
- interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&ethsys CLK_ETH_HSDMA_EN>;
- clock-names = "hsdma";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- #dma-cells = <1>;
- };
-
- eth: ethernet@1b100000 {
- compatible = "mediatek,mt7622-eth",
- "mediatek,mt2701-eth",
- "syscon";
- reg = <0 0x1b100000 0 0x20000>;
- interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
- <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
- clocks = <&topckgen CLK_TOP_ETH_SEL>,
- <&ethsys CLK_ETH_ESW_EN>,
- <&ethsys CLK_ETH_GP0_EN>,
- <&ethsys CLK_ETH_GP1_EN>,
- <&ethsys CLK_ETH_GP2_EN>,
- <&sgmiisys CLK_SGMII_TX250M_EN>,
- <&sgmiisys CLK_SGMII_RX250M_EN>,
- <&sgmiisys CLK_SGMII_CDR_REF>,
- <&sgmiisys CLK_SGMII_CDR_FB>,
- <&topckgen CLK_TOP_SGMIIPLL>,
- <&apmixedsys CLK_APMIXED_ETH2PLL>;
- clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
- "sgmii_tx250m", "sgmii_rx250m",
- "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
- "eth2pll";
- power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
- mediatek,ethsys = <&ethsys>;
- mediatek,sgmiisys = <&sgmiisys>;
- #address-cells = <1>;
- #size-cells = <0>;
- status = "disabled";
- };
-
- sgmiisys: sgmiisys@1b128000 {
- compatible = "mediatek,mt7622-sgmiisys",
- "syscon";
- reg = <0 0x1b128000 0 0x3000>;
- #clock-cells = <1>;
- mediatek,physpeed = "2500";
- };
-};
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-26 10:05:50 +0000