diff options
Diffstat (limited to 'target/linux/mediatek/dts')
4 files changed, 480 insertions, 0 deletions
diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi new file mode 100644 index 0000000000..739e500a12 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr-common.dtsi @@ -0,0 +1,258 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> + +#include "mt7986a.dtsi" + +/ { + aliases { + serial0 = &uart0; + label-mac-device = &gmac0; + led-boot = &led_status_green; + led-failsafe = &led_status_red; + led-running = &led_status_green; + led-upgrade = &led_status_red; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + reg = <0 0x40000000 0 0x20000000>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_5v: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "fixed-5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-boot-on; + regulator-always-on; + }; + + keys { + compatible = "gpio-keys"; + + reset { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + wps { + label = "wps"; + linux,code = <KEY_WPS_BUTTON>; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + turbo { + label = "turbo"; + linux,code = <BTN_1>; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led_status_red: status_red { + label = "red:status"; + gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + }; + + led_status_green: status_green { + label = "green:status"; + gpios = <&pio 8 GPIO_ACTIVE_HIGH>; + }; + + turbo { + label = "green:turbo"; + gpios = <&pio 12 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_config_1c>; + nvmem-cell-names = "mac-address"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-handle = <&phy7>; + phy-mode = "2500base-x"; + + nvmem-cells = <&macaddr_config_1c>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mdio { + phy5: ethernet-phy@5 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <5>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 13 GPIO_ACTIVE_LOW>; + realtek,aldps-enable; + }; + + phy7: ethernet-phy@7 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <7>; + reset-assert-us = <100000>; + reset-deassert-us = <100000>; + reset-gpios = <&pio 17 GPIO_ACTIVE_LOW>; + realtek,aldps-enable; + }; + + switch: switch@31 { + compatible = "mediatek,mt7531"; + reg = <31>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + interrupt-parent = <&pio>; + interrupts = <66 IRQ_TYPE_LEVEL_HIGH>; + }; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x000000 0x0100000>; + read-only; + }; + + config: partition@100000 { + label = "config"; + reg = <0x100000 0x0060000>; + read-only; + }; + + factory: partition@160000 { + label = "factory"; + reg = <0x160000 0x0060000>; + read-only; + }; + + partition@1c0000 { + label = "reserved"; + reg = <0x1c0000 0x01c0000>; + read-only; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x0200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7800000>; + }; + }; + }; +}; + +&pio { + spi_flash_pins: spi-flash-pins-33-to-38 { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + conf-pu { + pins = "SPI2_CS", "SPI2_HOLD", "SPI2_WP"; + drive-strength = <8>; + mediatek,pull-up-adv = <0>; /* bias-disable */ + }; + conf-pd { + pins = "SPI2_CLK", "SPI2_MOSI", "SPI2_MISO"; + drive-strength = <8>; + mediatek,pull-down-adv = <0>; /* bias-disable */ + }; + }; +}; + +&ssusb { + vusb33-supply = <®_3p3v>; + vbus-supply = <®_5v>; + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&wmac { + mediatek,mtd-eeprom = <&factory 0x0>; + nvmem-cells = <&macaddr_config_1c>; + nvmem-cell-names = "mac-address"; + mac-address-increment = <2>; + status = "okay"; +}; + +&config { + compatible = "nvmem-cells"; + #address-cells = <1>; + #size-cells = <1>; + + macaddr_config_1c: macaddr@1c { + reg = <0x1c 0x6>; + }; +}; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts new file mode 100644 index 0000000000..b7f7d2d371 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr4288.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7986a-tplink-tl-xdr-common.dtsi" + +/ { + model = "TP-Link TL-XDR4288"; + compatible = "tplink,tl-xdr4288", "mediatek,mt7986a"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan5"; + phy-handle = <&phy5>; + phy-mode = "2500base-x"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&wmac { + pinctrl-names = "dbdc"; + pinctrl-0 = <&wf_dbdc_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts new file mode 100644 index 0000000000..ffe57e5502 --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6086.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7986a-tplink-tl-xdr-common.dtsi" + +/ { + model = "TP-Link TL-XDR6086"; + compatible = "tplink,tl-xdr6086", "mediatek,mt7986a"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@5 { + reg = <5>; + label = "lan2"; + phy-handle = <&phy5>; + phy-mode = "2500base-x"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; diff --git a/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts new file mode 100644 index 0000000000..213f89918f --- /dev/null +++ b/target/linux/mediatek/dts/mt7986a-tplink-tl-xdr6088.dts @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT + +/dts-v1/; +#include "mt7986a-tplink-tl-xdr-common.dtsi" + +/ { + model = "TP-Link TL-XDR6088"; + compatible = "tplink,tl-xdr6088", "mediatek,mt7986a"; +}; + +&switch { + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + label = "lan1"; + }; + + port@1 { + reg = <1>; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "lan3"; + }; + + port@3 { + reg = <3>; + label = "lan4"; + }; + + port@5 { + reg = <5>; + label = "lan5"; + phy-handle = <&phy5>; + phy-mode = "2500base-x"; + }; + + port@6 { + reg = <6>; + ethernet = <&gmac0>; + phy-mode = "2500base-x"; + + fixed-link { + speed = <2500>; + full-duplex; + pause; + }; + }; + }; +}; + +&pio { + wf_2g_5g_pins: wf_2g_5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; +}; + +&wmac { + pinctrl-names = "default"; + pinctrl-0 = <&wf_2g_5g_pins>; +}; |