diff options
Diffstat (limited to 'target/linux/linux-2.4/patches/ar7/000-ar7_support.patch')
| -rw-r--r-- | target/linux/linux-2.4/patches/ar7/000-ar7_support.patch | 1302 |
1 files changed, 947 insertions, 355 deletions
diff --git a/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch b/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch index e06c7ee89a..109c85846d 100644 --- a/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch +++ b/target/linux/linux-2.4/patches/ar7/000-ar7_support.patch @@ -1,6 +1,6 @@ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S --- linux.old/arch/mips/ar7/avalanche/avalanche_jump.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-07 04:39:14.418226000 +0200 ++++ linux.dev/arch/mips/ar7/avalanche/avalanche_jump.S 2005-07-09 08:00:15.286026000 +0200 @@ -0,0 +1,69 @@ +#include <linux/config.h> +#include <linux/threads.h> @@ -71,9 +71,340 @@ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_jump.S linux.dev/arch/mips +END(jump_dedicated_interrupt) + + .set at +diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_misc.c linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c +--- linux.old/arch/mips/ar7/avalanche/avalanche_misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/ar7/avalanche/avalanche_misc.c 2005-07-09 08:00:15.287026000 +0200 +@@ -0,0 +1,327 @@ ++#include <asm/ar7/sangam.h> ++#include <asm/ar7/avalanche_misc.h> ++#include <linux/module.h> ++#include <linux/spinlock.h> ++ ++static unsigned int avalanche_vbus_freq; ++ ++REMOTE_VLYNQ_DEV_RESET_CTRL_FN p_remote_vlynq_dev_reset_ctrl = NULL; ++ ++/***************************************************************************** ++ * Reset Control Module. ++ *****************************************************************************/ ++void avalanche_reset_ctrl(unsigned int module_reset_bit, ++ AVALANCHE_RESET_CTRL_T reset_ctrl) ++{ ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ ++ if(module_reset_bit >= 32 && module_reset_bit < 64) ++ return; ++ ++ if(module_reset_bit >= 64) ++ { ++ if(p_remote_vlynq_dev_reset_ctrl) ++ return(p_remote_vlynq_dev_reset_ctrl(module_reset_bit - 64, reset_ctrl)); ++ else ++ return; ++ } ++ ++ if(reset_ctrl == OUT_OF_RESET) ++ *reset_reg |= 1 << module_reset_bit; ++ else ++ *reset_reg &= ~(1 << module_reset_bit); ++} ++ ++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int module_reset_bit) ++{ ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ ++ return (((*reset_reg) & (1 << module_reset_bit)) ? OUT_OF_RESET : IN_RESET ); ++} ++ ++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode) ++{ ++ volatile unsigned int *sw_reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_SWRCR; ++ *sw_reset_reg = mode; ++} ++ ++#define AVALANCHE_RST_CTRL_RSR_MASK 0x3 ++ ++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status() ++{ ++ volatile unsigned int *sys_reset_status = (unsigned int*) AVALANCHE_RST_CTRL_RSR; ++ ++ return ( (AVALANCHE_SYS_RESET_STATUS_T) (*sys_reset_status & AVALANCHE_RST_CTRL_RSR_MASK) ); ++} ++ ++ ++/***************************************************************************** ++ * Power Control Module ++ *****************************************************************************/ ++#define AVALANCHE_GLOBAL_POWER_DOWN_MASK 0x3FFFFFFF /* bit 31, 30 masked */ ++#define AVALANCHE_GLOBAL_POWER_DOWN_BIT 30 /* shift to bit 30, 31 */ ++ ++ ++void avalanche_power_ctrl(unsigned int module_power_bit, AVALANCHE_POWER_CTRL_T power_ctrl) ++{ ++ volatile unsigned int *power_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ if (power_ctrl == POWER_CTRL_POWER_DOWN) ++ /* power down the module */ ++ *power_reg |= (1 << module_power_bit); ++ else ++ /* power on the module */ ++ *power_reg &= (~(1 << module_power_bit)); ++} ++ ++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int module_power_bit) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ return (((*power_status_reg) & (1 << module_power_bit)) ? POWER_CTRL_POWER_DOWN : POWER_CTRL_POWER_UP); ++} ++ ++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ *power_status_reg &= AVALANCHE_GLOBAL_POWER_DOWN_MASK; ++ *power_status_reg |= ( power_mode << AVALANCHE_GLOBAL_POWER_DOWN_BIT); ++} ++ ++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void) ++{ ++ volatile unsigned int *power_status_reg = (unsigned int*)AVALANCHE_POWER_CTRL_PDCR; ++ ++ return((AVALANCHE_SYS_POWER_MODE_T) (((*power_status_reg) & (~AVALANCHE_GLOBAL_POWER_DOWN_MASK)) ++ >> AVALANCHE_GLOBAL_POWER_DOWN_BIT)); ++} ++ ++#if defined (CONFIG_AVALANCHE_GENERIC_GPIO) ++/***************************************************************************** ++ * GPIO Control ++ *****************************************************************************/ ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_init ++ ***************************************************************************/ ++void avalanche_gpio_init(void) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *reset_reg = (unsigned int*) AVALANCHE_RST_CTRL_PRCR; ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *reset_reg |= (1 << AVALANCHE_GPIO_RESET_BIT); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_ctrl ++ ***************************************************************************/ ++int avalanche_gpio_ctrl(unsigned int gpio_pin, ++ AVALANCHE_GPIO_PIN_MODE_T pin_mode, ++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_ENBL; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ ++ if(pin_mode == GPIO_PIN) ++ { ++ *gpio_ctrl |= (1 << gpio_pin); ++ ++ gpio_ctrl = (unsigned int*)AVALANCHE_GPIO_DIR; ++ ++ if(pin_direction == GPIO_INPUT_PIN) ++ *gpio_ctrl |= (1 << gpio_pin); ++ else ++ *gpio_ctrl &= ~(1 << gpio_pin); ++ } ++ else /* FUNCTIONAL PIN */ ++ { ++ *gpio_ctrl &= ~(1 << gpio_pin); ++ } ++ ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_out ++ ***************************************************************************/ ++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ if(value == TRUE) ++ *gpio_out |= 1 << gpio_pin; ++ else ++ *gpio_out &= ~(1 << gpio_pin); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return(0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_in ++ ***************************************************************************/ ++int avalanche_gpio_in_bit(unsigned int gpio_pin) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN; ++ int ret_val = 0; ++ ++ if(gpio_pin >= 32) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ ret_val = ((*gpio_in) & (1 << gpio_pin)); ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (ret_val); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_out_val ++ ***************************************************************************/ ++int avalanche_gpio_out_value(unsigned int out_val, unsigned int out_mask, ++ unsigned int reg_index) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_out = (unsigned int*) AVALANCHE_GPIO_DATA_OUT; ++ ++ if(reg_index > 0) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *gpio_out &= ~out_mask; ++ *gpio_out |= out_val; ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return(0); ++} ++ ++/**************************************************************************** ++ * FUNCTION: avalanche_gpio_in_value ++ ***************************************************************************/ ++int avalanche_gpio_in_value(unsigned int* in_val, unsigned int reg_index) ++{ ++ spinlock_t closeLock; ++ unsigned int closeFlag; ++ volatile unsigned int *gpio_in = (unsigned int*) AVALANCHE_GPIO_DATA_IN; ++ ++ if(reg_index > 0) ++ return(-1); ++ ++ spin_lock_irqsave(&closeLock, closeFlag); ++ *in_val = *gpio_in; ++ spin_unlock_irqrestore(&closeLock, closeFlag); ++ ++ return (0); ++} ++ ++#endif ++ ++/*********************************************************************** ++ * ++ * Wakeup Control Module for TNETV1050 Communication Processor ++ * ++ ***********************************************************************/ ++ ++#define AVALANCHE_WAKEUP_POLARITY_BIT 16 ++ ++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int, ++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl, ++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity) ++{ ++ volatile unsigned int *wakeup_status_reg = (unsigned int*) AVALANCHE_WAKEUP_CTRL_WKCR; ++ ++ /* enable/disable */ ++ if (wakeup_ctrl == WAKEUP_ENABLED) ++ /* enable wakeup */ ++ *wakeup_status_reg |= wakeup_int; ++ else ++ /* disable wakeup */ ++ *wakeup_status_reg &= (~wakeup_int); ++ ++ /* set polarity */ ++ if (wakeup_polarity == WAKEUP_ACTIVE_LOW) ++ *wakeup_status_reg |= (wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT); ++ else ++ *wakeup_status_reg &= ~(wakeup_int << AVALANCHE_WAKEUP_POLARITY_BIT); ++} ++ ++void avalanche_set_vbus_freq(unsigned int new_vbus_freq) ++{ ++ avalanche_vbus_freq = new_vbus_freq; ++} ++ ++unsigned int avalanche_get_vbus_freq() ++{ ++ return(avalanche_vbus_freq); ++} ++ ++unsigned int avalanche_get_chip_version_info() ++{ ++ return(*(volatile unsigned int*)AVALANCHE_CVR); ++} ++ ++SET_MDIX_ON_CHIP_FN_T p_set_mdix_on_chip_fn = NULL; ++ ++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation) ++{ ++ if(p_set_mdix_on_chip_fn) ++ return (p_set_mdix_on_chip_fn(base_addr, operation)); ++ else ++ return(-1); ++} ++ ++unsigned int avalanche_is_mdix_on_chip(void) ++{ ++ return(p_set_mdix_on_chip_fn ? 1:0); ++} ++ ++/* software abstraction for HAL */ ++ ++ ++EXPORT_SYMBOL(avalanche_reset_ctrl); ++EXPORT_SYMBOL(avalanche_get_reset_status); ++EXPORT_SYMBOL(avalanche_sys_reset); ++EXPORT_SYMBOL(avalanche_get_sys_last_reset_status); ++EXPORT_SYMBOL(avalanche_power_ctrl); ++EXPORT_SYMBOL(avalanche_get_power_status); ++EXPORT_SYMBOL(avalanche_set_global_power_mode); ++EXPORT_SYMBOL(avalanche_get_global_power_mode); ++EXPORT_SYMBOL(avalanche_set_mdix_on_chip); ++EXPORT_SYMBOL(avalanche_is_mdix_on_chip); ++ ++ ++ ++#if defined (CONFIG_AVALANCHE_GENERIC_GPIO) ++EXPORT_SYMBOL(avalanche_gpio_init); ++EXPORT_SYMBOL(avalanche_gpio_ctrl); ++EXPORT_SYMBOL(avalanche_gpio_out_bit); ++EXPORT_SYMBOL(avalanche_gpio_in_bit); ++EXPORT_SYMBOL(avalanche_gpio_out_value); ++EXPORT_SYMBOL(avalanche_gpio_in_value); ++#endif ++ ++EXPORT_SYMBOL(avalanche_set_vbus_freq); ++EXPORT_SYMBOL(avalanche_get_vbus_freq); ++ ++EXPORT_SYMBOL(avalanche_get_chip_version_info); ++ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c --- linux.old/arch/mips/ar7/avalanche/avalanche_paging.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-07 04:39:14.418226000 +0200 ++++ linux.dev/arch/mips/ar7/avalanche/avalanche_paging.c 2005-07-09 08:00:15.287026000 +0200 @@ -0,0 +1,314 @@ +/* + * -*- linux-c -*- @@ -391,8 +722,8 @@ diff -urN linux.old/arch/mips/ar7/avalanche/avalanche_paging.c linux.dev/arch/mi +} diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/avalanche/Makefile --- linux.old/arch/mips/ar7/avalanche/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-07 04:39:14.417226000 +0200 -@@ -0,0 +1,13 @@ ++++ linux.dev/arch/mips/ar7/avalanche/Makefile 2005-07-09 08:00:15.288026000 +0200 +@@ -0,0 +1,16 @@ +.S.s: + $(CPP) $(AFLAGS) $< -o $*.s + @@ -403,12 +734,15 @@ diff -urN linux.old/arch/mips/ar7/avalanche/Makefile linux.dev/arch/mips/ar7/ava + +O_TARGET := avalanche.o + -+obj-y += avalanche_paging.o avalanche_jump.o ++export-objs := avalanche_misc.o ++ ++obj-y += avalanche_paging.o avalanche_jump.o avalanche_misc.o + +include $(TOPDIR)/Rules.make ++ diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c --- linux.old/arch/mips/ar7/cmdline.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-07 04:39:14.419226000 +0200 ++++ linux.dev/arch/mips/ar7/cmdline.c 2005-07-09 08:00:15.288026000 +0200 @@ -0,0 +1,64 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -474,10 +808,36 @@ diff -urN linux.old/arch/mips/ar7/cmdline.c linux.dev/arch/mips/ar7/cmdline.c + --cp; + *cp = '\0'; +} +diff -urN linux.old/arch/mips/ar7/hal/misc.c linux.dev/arch/mips/ar7/hal/misc.c +--- linux.old/arch/mips/ar7/hal/misc.c 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/arch/mips/ar7/hal/misc.c 2005-07-09 08:00:15.288026000 +0200 +@@ -0,0 +1,22 @@ ++#include <linux/slab.h> ++ ++void *os_platform_malloc(unsigned int size) ++{ ++ return kmalloc(size,GFP_KERNEL); ++} ++ ++void os_platform_free(void *p) ++{ ++ kfree(p); ++} ++ ++void *os_platform_memset(void *p, int num, unsigned int size) ++{ ++ return memset(p,num,size); ++} ++ ++EXPORT_SYMBOL(os_platform_malloc); ++EXPORT_SYMBOL(os_platform_free); ++EXPORT_SYMBOL(os_platform_memset); ++ ++ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c --- linux.old/arch/mips/ar7/init.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/init.c 2005-07-07 04:39:14.419226000 +0200 -@@ -0,0 +1,144 @@ ++++ linux.dev/arch/mips/ar7/init.c 2005-07-09 08:11:36.592452520 +0200 +@@ -0,0 +1,146 @@ +/* + * Carsten Langgaard, carstenl@mips.com + * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved. @@ -501,6 +861,7 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c +#include <linux/init.h> +#include <linux/string.h> +#include <linux/kernel.h> ++#include <linux/module.h> + +#include <asm/io.h> +#include <asm/mips-boards/prom.h> @@ -519,7 +880,6 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c +#define MAX_ENV_ENTRY 80 + +static t_env_var local_envp[MAX_ENV_ENTRY]; -+ +int init_debug = 0; + +char *prom_getenv(char *envname) @@ -622,9 +982,11 @@ diff -urN linux.old/arch/mips/ar7/init.c linux.dev/arch/mips/ar7/init.c + + return 0; +} ++ ++EXPORT_SYMBOL(prom_getenv); diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c --- linux.old/arch/mips/ar7/irq.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/irq.c 2005-07-07 04:39:14.420226000 +0200 ++++ linux.dev/arch/mips/ar7/irq.c 2005-07-09 08:00:15.289026000 +0200 @@ -0,0 +1,669 @@ +/* + * Nitin Dhingra, iamnd@ti.com @@ -1297,8 +1659,8 @@ diff -urN linux.old/arch/mips/ar7/irq.c linux.dev/arch/mips/ar7/irq.c + diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile --- linux.old/arch/mips/ar7/Makefile 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/Makefile 2005-07-07 04:39:14.417226000 +0200 -@@ -0,0 +1,12 @@ ++++ linux.dev/arch/mips/ar7/Makefile 2005-07-09 08:12:52.981839568 +0200 +@@ -0,0 +1,14 @@ +.S.s: + $(CPP) $(AFLAGS) $< -o $*.s + @@ -1307,13 +1669,15 @@ diff -urN linux.old/arch/mips/ar7/Makefile linux.dev/arch/mips/ar7/Makefile + +O_TARGET := ar7.o + -+obj-y := tnetd73xx_misc.o -+obj-y += setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o ++export-objs += tnetd73xx_misc.o init.o ++obj-y := setup.o irq.o mipsIRQ.o reset.o init.o memory.o printf.o cmdline.o time.o ++obj-y += tnetd73xx_misc.o ++obj-y += hal/misc.o + +include $(TOPDIR)/Rules.make diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c --- linux.old/arch/mips/ar7/memory.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/memory.c 2005-07-07 04:39:14.420226000 +0200 ++++ linux.dev/arch/mips/ar7/memory.c 2005-07-09 08:00:15.290026000 +0200 @@ -0,0 +1,130 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1447,7 +1811,7 @@ diff -urN linux.old/arch/mips/ar7/memory.c linux.dev/arch/mips/ar7/memory.c +} diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S --- linux.old/arch/mips/ar7/mipsIRQ.S 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-07 04:39:14.421226000 +0200 ++++ linux.dev/arch/mips/ar7/mipsIRQ.S 2005-07-09 08:00:15.290026000 +0200 @@ -0,0 +1,120 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1571,7 +1935,7 @@ diff -urN linux.old/arch/mips/ar7/mipsIRQ.S linux.dev/arch/mips/ar7/mipsIRQ.S +END(mipsIRQ) diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c --- linux.old/arch/mips/ar7/printf.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/printf.c 2005-07-07 04:39:14.421226000 +0200 ++++ linux.dev/arch/mips/ar7/printf.c 2005-07-09 08:00:15.291026000 +0200 @@ -0,0 +1,51 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1626,7 +1990,7 @@ diff -urN linux.old/arch/mips/ar7/printf.c linux.dev/arch/mips/ar7/printf.c +} diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c --- linux.old/arch/mips/ar7/reset.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/reset.c 2005-07-07 04:39:14.421226000 +0200 ++++ linux.dev/arch/mips/ar7/reset.c 2005-07-09 08:00:15.291026000 +0200 @@ -0,0 +1,54 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1684,7 +2048,7 @@ diff -urN linux.old/arch/mips/ar7/reset.c linux.dev/arch/mips/ar7/reset.c +} diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c --- linux.old/arch/mips/ar7/setup.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/setup.c 2005-07-07 06:45:41.786771352 +0200 ++++ linux.dev/arch/mips/ar7/setup.c 2005-07-09 08:00:15.291026000 +0200 @@ -0,0 +1,167 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1855,7 +2219,7 @@ diff -urN linux.old/arch/mips/ar7/setup.c linux.dev/arch/mips/ar7/setup.c +} diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c --- linux.old/arch/mips/ar7/time.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/time.c 2005-07-07 04:39:14.422226000 +0200 ++++ linux.dev/arch/mips/ar7/time.c 2005-07-09 08:00:15.292025000 +0200 @@ -0,0 +1,125 @@ +/* + * Carsten Langgaard, carstenl@mips.com @@ -1984,8 +2348,8 @@ diff -urN linux.old/arch/mips/ar7/time.c linux.dev/arch/mips/ar7/time.c +} diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd73xx_misc.c --- linux.old/arch/mips/ar7/tnetd73xx_misc.c 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-07 04:39:14.423225000 +0200 -@@ -0,0 +1,924 @@ ++++ linux.dev/arch/mips/ar7/tnetd73xx_misc.c 2005-07-09 08:19:34.066865376 +0200 +@@ -0,0 +1,927 @@ +/****************************************************************************** + * FILE PURPOSE: TNETD73xx Misc modules API Source + ****************************************************************************** @@ -2006,6 +2370,7 @@ diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd +#define _LINK_KSEG0_ + +#include <linux/types.h> ++#include <linux/module.h> +#include <asm/ar7/tnetd73xx.h> +#include <asm/ar7/tnetd73xx_misc.h> + @@ -2257,31 +2622,31 @@ diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd + + + -+ /**************************************************************************** -+ * DATA PURPOSE: PRIVATE Variables -+ **************************************************************************/ -+ static u32 *clk_src[4]; -+ static u32 mips_pll_out; -+ static u32 sys_pll_out; -+ static u32 afeclk_inp; -+ static u32 refclk_inp; -+ static u32 xtal_inp; -+ static u32 present_min; -+ static u32 present_max; -+ -+ /* Forward References */ -+ static u32 find_gcd(u32 min, u32 max); -+ static u32 compute_prediv( u32 divider, u32 min, u32 max); -+ static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider); -+ static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id); -+ static void find_approx(u32 *,u32 *,u32); -+ -+ /**************************************************************************** -+ * FUNCTION: tnetd73xx_clkc_init -+ **************************************************************************** -+ * Description: The routine initializes the internal variables depending on -+ * on the sources selected for different clocks. -+ ***************************************************************************/ ++/**************************************************************************** ++* DATA PURPOSE: PRIVATE Variables ++**************************************************************************/ ++static u32 *clk_src[4]; ++static u32 mips_pll_out; ++static u32 sys_pll_out; ++static u32 afeclk_inp; ++static u32 refclk_inp; ++static u32 xtal_inp; ++static u32 present_min; ++static u32 present_max; ++ ++/* Forward References */ ++static u32 find_gcd(u32 min, u32 max); ++static u32 compute_prediv( u32 divider, u32 min, u32 max); ++static void get_val(u32 base_freq, u32 output_freq,u32 *multiplier, u32 *divider); ++static u32 get_base_frequency(TNETD73XX_CLKC_ID_T clk_id); ++static void find_approx(u32 *,u32 *,u32); ++ ++/**************************************************************************** ++* FUNCTION: tnetd73xx_clkc_init ++**************************************************************************** ++* Description: The routine initializes the internal variables depending on ++* on the sources selected for different clocks. ++***************************************************************************/ +void tnetd73xx_clkc_init(u32 afeclk, u32 refclk, u32 xtal3in) +{ + @@ -2910,9 +3275,11 @@ diff -urN linux.old/arch/mips/ar7/tnetd73xx_misc.c linux.dev/arch/mips/ar7/tnetd + return ( (pin_value & (1 << gpio_pin)) ? 1 : 0 ); +} + ++EXPORT_SYMBOL(tnetd73xx_clkc_get_freq); ++ diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared.in ---- linux.old/arch/mips/config-shared.in 2005-07-07 05:38:31.343491864 +0200 -+++ linux.dev/arch/mips/config-shared.in 2005-07-07 04:39:14.424225000 +0200 +--- linux.old/arch/mips/config-shared.in 2005-07-09 08:01:49.831653720 +0200 ++++ linux.dev/arch/mips/config-shared.in 2005-07-09 08:00:15.293025000 +0200 @@ -20,6 +20,15 @@ mainmenu_option next_comment comment 'Machine selection' @@ -2958,8 +3325,8 @@ diff -urN linux.old/arch/mips/config-shared.in linux.dev/arch/mips/config-shared "$CONFIG_DECSTATION" = "y" -o \ "$CONFIG_IBM_WORKPAD" = "y" -o \ diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c ---- linux.old/arch/mips/kernel/irq.c 2005-07-07 05:38:31.343491864 +0200 -+++ linux.dev/arch/mips/kernel/irq.c 2005-07-07 04:39:14.424225000 +0200 +--- linux.old/arch/mips/kernel/irq.c 2005-07-09 08:01:49.831653720 +0200 ++++ linux.dev/arch/mips/kernel/irq.c 2005-07-09 08:00:15.294025000 +0200 @@ -76,6 +76,7 @@ * Generic, controller-independent functions: */ @@ -3009,8 +3376,8 @@ diff -urN linux.old/arch/mips/kernel/irq.c linux.dev/arch/mips/kernel/irq.c /* * IRQ autodetection code.. diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c ---- linux.old/arch/mips/kernel/setup.c 2005-07-07 05:38:31.344491712 +0200 -+++ linux.dev/arch/mips/kernel/setup.c 2005-07-07 04:39:14.425225000 +0200 +--- linux.old/arch/mips/kernel/setup.c 2005-07-09 08:01:49.832653568 +0200 ++++ linux.dev/arch/mips/kernel/setup.c 2005-07-09 08:00:15.295025000 +0200 @@ -109,6 +109,7 @@ unsigned long isa_slot_offset; EXPORT_SYMBOL(isa_slot_offset); @@ -3059,8 +3426,8 @@ diff -urN linux.old/arch/mips/kernel/setup.c linux.dev/arch/mips/kernel/setup.c panic("Unsupported architecture"); } diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c ---- linux.old/arch/mips/kernel/traps.c 2005-07-07 05:38:31.345491560 +0200 -+++ linux.dev/arch/mips/kernel/traps.c 2005-07-07 04:39:14.425225000 +0200 +--- linux.old/arch/mips/kernel/traps.c 2005-07-09 08:01:49.832653568 +0200 ++++ linux.dev/arch/mips/kernel/traps.c 2005-07-09 08:00:15.295025000 +0200 @@ -40,6 +40,10 @@ #include <asm/uaccess.h> #include <asm/mmu_context.h> @@ -3179,8 +3546,8 @@ diff -urN linux.old/arch/mips/kernel/traps.c linux.dev/arch/mips/kernel/traps.c per_cpu_trap_init(); } diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c ---- linux.old/arch/mips/lib/promlib.c 2005-07-07 05:38:31.345491560 +0200 -+++ linux.dev/arch/mips/lib/promlib.c 2005-07-07 04:39:14.426225000 +0200 +--- linux.old/arch/mips/lib/promlib.c 2005-07-09 08:01:49.833653416 +0200 ++++ linux.dev/arch/mips/lib/promlib.c 2005-07-09 08:00:15.296025000 +0200 @@ -1,3 +1,4 @@ +#ifndef CONFIG_AR7 #include <stdarg.h> @@ -3192,8 +3559,8 @@ diff -urN linux.old/arch/mips/lib/promlib.c linux.dev/arch/mips/lib/promlib.c } +#endif diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile ---- linux.old/arch/mips/Makefile 2005-07-07 05:38:31.320495360 +0200 -+++ linux.dev/arch/mips/Makefile 2005-07-07 04:39:14.510212000 +0200 +--- linux.old/arch/mips/Makefile 2005-07-09 08:01:49.833653416 +0200 ++++ linux.dev/arch/mips/Makefile 2005-07-09 08:00:15.413007000 +0200 @@ -369,6 +369,16 @@ endif @@ -3212,8 +3579,8 @@ diff -urN linux.old/arch/mips/Makefile linux.dev/arch/mips/Makefile # ifdef CONFIG_DECSTATION diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c ---- linux.old/arch/mips/mm/init.c 2005-07-07 05:38:31.345491560 +0200 -+++ linux.dev/arch/mips/mm/init.c 2005-07-07 04:39:14.426225000 +0200 +--- linux.old/arch/mips/mm/init.c 2005-07-09 08:01:49.834653264 +0200 ++++ linux.dev/arch/mips/mm/init.c 2005-07-09 08:00:15.297025000 +0200 @@ -40,8 +40,10 @@ mmu_gather_t mmu_gathers[NR_CPUS]; @@ -3281,8 +3648,8 @@ diff -urN linux.old/arch/mips/mm/init.c linux.dev/arch/mips/mm/init.c } +#endif diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c ---- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-07 05:38:31.346491408 +0200 -+++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-07 04:39:14.427225000 +0200 +--- linux.old/arch/mips/mm/tlb-r4k.c 2005-07-09 08:01:49.834653264 +0200 ++++ linux.dev/arch/mips/mm/tlb-r4k.c 2005-07-09 08:00:15.297025000 +0200 @@ -20,6 +20,10 @@ #include <asm/pgtable.h> #include <asm/system.h> @@ -3308,8 +3675,8 @@ diff -urN linux.old/arch/mips/mm/tlb-r4k.c linux.dev/arch/mips/mm/tlb-r4k.c } } diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c ---- linux.old/drivers/char/serial.c 2005-07-07 05:38:31.348491104 +0200 -+++ linux.dev/drivers/char/serial.c 2005-07-07 04:39:14.429225000 +0200 +--- linux.old/drivers/char/serial.c 2005-07-09 08:01:49.836652960 +0200 ++++ linux.dev/drivers/char/serial.c 2005-07-09 08:00:15.299024000 +0200 @@ -419,7 +419,40 @@ return 0; } @@ -3408,7 +3775,7 @@ diff -urN linux.old/drivers/char/serial.c linux.dev/drivers/char/serial.c cval >>= 8; diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar7.h --- linux.old/include/asm-mips/ar7/ar7.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-07 04:39:14.430224000 +0200 ++++ linux.dev/include/asm-mips/ar7/ar7.h 2005-07-09 08:00:15.300024000 +0200 @@ -0,0 +1,137 @@ +#ifndef _MIPS_AR7_H +#define _MIPS_AR7_H @@ -3549,7 +3916,7 @@ diff -urN linux.old/include/asm-mips/ar7/ar7.h linux.dev/include/asm-mips/ar7/ar +#endif /*_MIPS_AR7_H */ diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ar7/avalanche.h --- linux.old/include/asm-mips/ar7/avalanche.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-07 04:39:14.430224000 +0200 ++++ linux.dev/include/asm-mips/ar7/avalanche.h 2005-07-09 08:00:15.301024000 +0200 @@ -0,0 +1,183 @@ +/* $Id$ + * @@ -3736,7 +4103,7 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche.h linux.dev/include/asm-mips/ + diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm-mips/ar7/avalanche_intc.h --- linux.old/include/asm-mips/ar7/avalanche_intc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-07 04:39:14.431224000 +0200 ++++ linux.dev/include/asm-mips/ar7/avalanche_intc.h 2005-07-09 08:00:15.301024000 +0200 @@ -0,0 +1,273 @@ + /* + * Nitin Dhingra, iamnd@ti.com @@ -4011,311 +4378,162 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_intc.h linux.dev/include/asm- + + +#endif /* _AVALANCHE_INTC_H */ -diff -urN linux.old/include/asm-mips/ar7/avalanche_int.h linux.dev/include/asm-mips/ar7/avalanche_int.h ---- linux.old/include/asm-mips/ar7/avalanche_int.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_int.h 2005-07-07 04:39:14.431224000 +0200 -@@ -0,0 +1,298 @@ -+/* $Id$ -+ * -+ * avalancheint.h -+ * -+ * Jeff Harrell, jharrell@ti.com -+ * Copyright (C) 2000,2001 Texas Instruments , Inc. -+ * -+ * ######################################################################## -+ * -+ * This program is free software; you can distribute it and/or modify it -+ * under the terms of the GNU General Public License (Version 2) as -+ * published by the Free Software Foundation. -+ * -+ * This program is distributed in the hope it will be useful, but WITHOUT -+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or -+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License -+ * for more details. -+ * -+ * You should have received a copy of the GNU General Public License along -+ * with this program; if not, write to the Free Software Foundation, Inc., -+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. -+ * -+ * ######################################################################## -+ * -+ * Defines for the AVALANCHE interrupt controller. -+ * -+ */ -+#ifndef _MIPS_AVALANCHEINT_H -+#define _MIPS_AVALANCHEINT_H -+ -+#include <linux/config.h> -+ -+/* Avalanche Interrupt number */ -+#define AVINTNUM(x) ((x) - MIPS_EXCEPTION_OFFSET) -+/* Linux Interrupt number */ -+#define LNXINTNUM(x)((x) + MIPS_EXCEPTION_OFFSET) -+/* Number of IRQ supported on hw interrupt 0. */ +diff -urN linux.old/include/asm-mips/ar7/avalanche_misc.h linux.dev/include/asm-mips/ar7/avalanche_misc.h +--- linux.old/include/asm-mips/ar7/avalanche_misc.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/avalanche_misc.h 2005-07-09 08:00:15.302024000 +0200 +@@ -0,0 +1,149 @@ ++#ifndef _AVALANCHE_MISC_H_ ++#define _AVALANCHE_MISC_H_ ++ ++typedef enum AVALANCHE_ERR_t ++{ ++ AVALANCHE_ERR_OK = 0, /* OK or SUCCESS */ ++ AVALANCHE_ERR_ERROR = -1, /* Unspecified/Generic ERROR */ + -+//#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */ -+//#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */ ++ /* Pointers and args */ ++ AVALANCHE_ERR_INVARG = -2, /* Invaild argument to the call */ ++ AVALANCHE_ERR_NULLPTR = -3, /* NULL pointer */ ++ AVALANCHE_ERR_BADPTR = -4, /* Bad (out of mem) pointer */ + ++ /* Memory issues */ ++ AVALANCHE_ERR_ALLOC_FAIL = -10, /* allocation failed */ ++ AVALANCHE_ERR_FREE_FAIL = -11, /* free failed */ ++ AVALANCHE_ERR_MEM_CORRUPT = -12, /* corrupted memory */ ++ AVALANCHE_ERR_BUF_LINK = -13, /* buffer linking failed */ + -+#define MIPS_EXCEPTION_OFFSET 8 -+#define AVALANCHE_INT_END_PRIMARY (40 + MIPS_EXCEPTION_OFFSET) -+#define AVALANCHE_INT_END_SECONDARY (32 + MIPS_EXCEPTION_OFFSET) ++ /* Device issues */ ++ AVALANCHE_ERR_DEVICE_TIMEOUT = -20, /* device timeout on read/write */ ++ AVALANCHE_ERR_DEVICE_MALFUNC = -21, /* device malfunction */ + -+#define AVALANCHE_INT_END_PRIMARY_REG1 (31 + MIPS_EXCEPTION_OFFSET) -+#define AVALANCHE_INT_END_PRIMARY_REG2 (39 + MIPS_EXCEPTION_OFFSET) ++ AVALANCHE_ERR_INVID = -30 /* Invalid ID */ + ++} AVALANCHE_ERR; + -+#define AVALANCHE_INT_END (AVINTNUM(AVALANCHE_INT_END_PRIMARY) + AVINTNUM(AVALANCHE_INT_END_SECONDARY) \ -+ + MIPS_EXCEPTION_OFFSET - 1) ++/***************************************************************************** ++ * Reset Control Module ++ *****************************************************************************/ + -+struct avalanche_ictrl_regs /* Avalanche Interrupt control registers */ ++typedef enum AVALANCHE_RESET_CTRL_tag +{ -+ volatile unsigned long intsr1; /* Interrupt Status/Set Register 1 */ /* 0x00 */ -+ volatile unsigned long intsr2; /* Interrupt Status/Set Register 2 */ /* 0x04 */ -+ volatile unsigned long unused1; /* 0x08 */ -+ volatile unsigned long unused2; /* 0x0C */ -+ volatile unsigned long intcr1; /* Interrupt Clear Register 1 */ /* 0x10 */ -+ volatile unsigned long intcr2; /* Interrupt Clear Register 2 */ /* 0x14 */ -+ volatile unsigned long unused3; /* 0x18 */ -+ volatile unsigned long unused4; /* 0x1C */ -+ volatile unsigned long intesr1; /* Interrupt Enable (Set) Register 1 */ /* 0x20 */ -+ volatile unsigned long intesr2; /* Interrupt Enable (Set) Register 2 */ /* 0x24 */ -+ volatile unsigned long unused5; /* 0x28 */ -+ volatile unsigned long unused6; /* 0x2C */ -+ volatile unsigned long intecr1; /* Interrupt Enable Clear Register 1 */ /* 0x30 */ -+ volatile unsigned long intecr2; /* Interrupt Enable Clear Register 2 */ /* 0x34 */ -+ volatile unsigned long unused7; /* 0x38 */ -+ volatile unsigned long unused8; /* 0x3c */ -+ volatile unsigned long pintir; /* Priority Interrupt Index Register */ /* 0x40 */ -+ volatile unsigned long intmsr; /* Priority Interrupt Mask Index Reg.*/ /* 0x44 */ -+ volatile unsigned long unused9; /* 0x48 */ -+ volatile unsigned long unused10; /* 0x4C */ -+ volatile unsigned long intpolr1; /* Interrupt Polarity Mask register 1*/ /* 0x50 */ -+ volatile unsigned long intpolr2; /* Interrupt Polarity Mask register 2*/ /* 0x54 */ -+}; ++ IN_RESET = 0, ++ OUT_OF_RESET ++} AVALANCHE_RESET_CTRL_T; + -+struct avalanche_exctrl_regs /* Avalanche Exception control registers */ ++typedef enum AVALANCHE_SYS_RST_MODE_tag +{ -+ volatile unsigned long exsr; /* Exceptions Status/Set register */ /* 0x80 */ -+ volatile unsigned long reserved; /* 0x84 */ -+ volatile unsigned long excr; /* Exceptions Clear Register */ /* 0x88 */ -+ volatile unsigned long reserved1; /* 0x8c */ -+ volatile unsigned long exiesr; /* Exceptions Interrupt Enable (set) */ /* 0x90 */ -+ volatile unsigned long reserved2; /* 0x94 */ -+ volatile unsigned long exiecr; /* Exceptions Interrupt Enable (clear)*/ /* 0x98 */ -+}; ++ RESET_SOC_WITH_MEMCTRL = 1, /* SW0 bit in SWRCR register */ ++ RESET_SOC_WITHOUT_MEMCTRL = 2 /* SW1 bit in SWRCR register */ ++} AVALANCHE_SYS_RST_MODE_T; + -+struct avalanche_channel_int_number ++typedef enum AVALANCHE_SYS_RESET_STATUS_tag +{ -+ volatile unsigned long cintnr0; /* Channel Interrupt Number Register */ /* 0x200 */ -+ volatile unsigned long cintnr1; /* Channel Interrupt Number Register */ /* 0x204 */ -+ volatile unsigned long cintnr2; /* Channel Interrupt Number Register */ /* 0x208 */ -+ volatile unsigned long cintnr3; /* Channel Interrupt Number Register */ /* 0x20C */ -+ volatile unsigned long cintnr4; /* Channel Interrupt Number Register */ /* 0x210 */ -+ volatile unsigned long cintnr5; /* Channel Interrupt Number Register */ /* 0x214 */ -+ volatile unsigned long cintnr6; /* Channel Interrupt Number Register */ /* 0x218 */ -+ volatile unsigned long cintnr7; /* Channel Interrupt Number Register */ /* 0x21C */ -+ volatile unsigned long cintnr8; /* Channel Interrupt Number Register */ /* 0x220 */ -+ volatile unsigned long cintnr9; /* Channel Interrupt Number Register */ /* 0x224 */ -+ volatile unsigned long cintnr10; /* Channel Interrupt Number Register */ /* 0x228 */ -+ volatile unsigned long cintnr11; /* Channel Interrupt Number Register */ /* 0x22C */ -+ volatile unsigned long cintnr12; /* Channel Interrupt Number Register */ /* 0x230 */ -+ volatile unsigned long cintnr13; /* Channel Interrupt Number Register */ /* 0x234 */ -+ volatile unsigned long cintnr14; /* Channel Interrupt Number Register */ /* 0x238 */ -+ volatile unsigned long cintnr15; /* Channel Interrupt Number Register */ /* 0x23C */ -+ volatile unsigned long cintnr16; /* Channel Interrupt Number Register */ /* 0x240 */ -+ volatile unsigned long cintnr17; /* Channel Interrupt Number Register */ /* 0x244 */ -+ volatile unsigned long cintnr18; /* Channel Interrupt Number Register */ /* 0x248 */ -+ volatile unsigned long cintnr19; /* Channel Interrupt Number Register */ /* 0x24C */ -+ volatile unsigned long cintnr20; /* Channel Interrupt Number Register */ /* 0x250 */ -+ volatile unsigned long cintnr21; /* Channel Interrupt Number Register */ /* 0x254 */ -+ volatile unsigned long cintnr22; /* Channel Interrupt Number Register */ /* 0x358 */ -+ volatile unsigned long cintnr23; /* Channel Interrupt Number Register */ /* 0x35C */ -+ volatile unsigned long cintnr24; /* Channel Interrupt Number Register */ /* 0x260 */ -+ volatile unsigned long cintnr25; /* Channel Interrupt Number Register */ /* 0x264 */ -+ volatile unsigned long cintnr26; /* Channel Interrupt Number Register */ /* 0x268 */ -+ volatile unsigned long cintnr27; /* Channel Interrupt Number Register */ /* 0x26C */ -+ volatile unsigned long cintnr28; /* Channel Interrupt Number Register */ /* 0x270 */ -+ volatile unsigned long cintnr29; /* Channel Interrupt Number Register */ /* 0x274 */ -+ volatile unsigned long cintnr30; /* Channel Interrupt Number Register */ /* 0x278 */ -+ volatile unsigned long cintnr31; /* Channel Interrupt Number Register */ /* 0x27C */ -+ volatile unsigned long cintnr32; /* Channel Interrupt Number Register */ /* 0x280 */ -+ volatile unsigned long cintnr33; /* Channel Interrupt Number Register */ /* 0x284 */ -+ volatile unsigned long cintnr34; /* Channel Interrupt Number Register */ /* 0x288 */ -+ volatile unsigned long cintnr35; /* Channel Interrupt Number Register */ /* 0x28C */ -+ volatile unsigned long cintnr36; /* Channel Interrupt Number Register */ /* 0x290 */ -+ volatile unsigned long cintnr37; /* Channel Interrupt Number Register */ /* 0x294 */ -+ volatile unsigned long cintnr38; /* Channel Interrupt Number Register */ /* 0x298 */ -+ volatile unsigned long cintnr39; /* Channel Interrupt Number Register */ /* 0x29C */ -+}; ++ HARDWARE_RESET = 0, ++ SOFTWARE_RESET0, /* Caused by writing 1 to SW0 bit in SWRCR register */ ++ WATCHDOG_RESET, ++ SOFTWARE_RESET1 /* Caused by writing 1 to SW1 bit in SWRCR register */ ++} AVALANCHE_SYS_RESET_STATUS_T; ++ ++void avalanche_reset_ctrl(unsigned int reset_module,AVALANCHE_RESET_CTRL_T reset_ctrl); ++AVALANCHE_RESET_CTRL_T avalanche_get_reset_status(unsigned int reset_module); ++void avalanche_sys_reset(AVALANCHE_SYS_RST_MODE_T mode); ++AVALANCHE_SYS_RESET_STATUS_T avalanche_get_sys_last_reset_status(void); ++ ++typedef void (*REMOTE_VLYNQ_DEV_RESET_CTRL_FN)(unsigned int reset_module, ++ AVALANCHE_RESET_CTRL_T reset_ctrl); ++ ++/***************************************************************************** ++ * Power Control Module ++ *****************************************************************************/ + -+struct avalanche_interrupt_line_to_channel ++typedef enum AVALANCHE_POWER_CTRL_tag +{ -+ unsigned long int_line0; /* Start of primary interrupts */ -+ unsigned long int_line1; -+ unsigned long int_line2; -+ unsigned long int_line3; -+ unsigned long int_line4; -+ unsigned long int_line5; -+ unsigned long int_line6; -+ unsigned long int_line7; -+ unsigned long int_line8; -+ unsigned long int_line9; -+ unsigned long int_line10; -+ unsigned long int_line11; -+ unsigned long int_line12; -+ unsigned long int_line13; -+ unsigned long int_line14; -+ unsigned long int_line15; -+ unsigned long int_line16; -+ unsigned long int_line17; -+ unsigned long int_line18; -+ unsigned long int_line19; -+ unsigned long int_line20; -+ unsigned long int_line21; -+ unsigned long int_line22; -+ unsigned long int_line23; -+ unsigned long int_line24; -+ unsigned long int_line25; -+ unsigned long int_line26; -+ unsigned long int_line27; -+ unsigned long int_line28; -+ unsigned long int_line29; -+ unsigned long int_line30; -+ unsigned long int_line31; -+ unsigned long int_line32; -+ unsigned long int_line33; -+ unsigned long int_line34; -+ unsigned long int_line35; -+ unsigned long int_line36; -+ unsigned long int_line37; -+ unsigned long int_line38; -+ unsigned long int_line39; -+}; ++ POWER_CTRL_POWER_UP = 0, ++ POWER_CTRL_POWER_DOWN ++} AVALANCHE_POWER_CTRL_T; + -+/* Interrupt Line #'s (Avalanche peripherals) */ ++typedef enum AVALANCHE_SYS_POWER_MODE_tag ++{ ++ GLOBAL_POWER_MODE_RUN = 0, /* All system is up */ ++ GLOBAL_POWER_MODE_IDLE, /* MIPS is power down, all peripherals working */ ++ GLOBAL_POWER_MODE_STANDBY, /* Chip in power down, but clock to ADSKL subsystem is running */ ++ GLOBAL_POWER_MODE_POWER_DOWN /* Total chip is powered down */ ++} AVALANCHE_SYS_POWER_MODE_T; + -+/*------------------------------*/ -+/* Avalanche primary interrupts */ -+/*------------------------------*/ -+#define UNIFIED_SECONDARY_INTERRUPT 0 -+#define AVALANCHE_EXT_INT_0 1 -+#define AVALANCHE_EXT_INT_1 2 -+#define AVALANCHE_EXT_INT_2 3 -+#define AVALANCHE_EXT_INT_3 4 -+#define AVALANCHE_TIMER_0_INT 5 -+#define AVALANCHE_TIMER_1_INT 6 -+#define AVALANCHE_UART0_INT 7 -+#define AVALANCHE_UART1_INT 8 -+#define AVALANCHE_PDMA_INT0 9 -+#define AVALANCHE_PDMA_INT1 10 -+#define AVALANCHE_HDLC_TXA 11 -+#define AVALANCHE_HDLC_TXB 12 -+#define AVALANCHE_HDLC_RXA 13 -+#define AVALANCHE_HDLC_RXB 14 -+#define AVALANCHE_ATM_SAR_TXA 15 -+#define AVALANCHE_ATM_SAR_TXB 16 -+#define AVALANCHE_ATM_SAR_RXA 17 -+#define AVALANCHE_ATM_SAR_RXB 18 -+#define AVALANCHE_MAC_TXA 19 -+#define AVALANCHE_MAC_RXA 20 -+#define AVALANCHE_DSP_SUB0 21 -+#define AVALANCHE_DSP_SUB1 22 -+#define AVALANCHE_DES_INT 23 -+#define AVALANCHE_USB_INT 24 -+#define AVALANCHE_PCI_INTA 25 -+#define AVALANCHE_PCI_INTB 26 -+#define AVALANCHE_PCI_INTC 27 -+/* Line #28 Reserved */ -+#define AVALANCHE_I2CM_INT 29 -+#define AVALANCHE_PDMA_INT2 30 -+#define AVALANCHE_PDMA_INT3 31 -+#define AVALANCHE_CODEC 32 -+#define AVALANCHE_MAC_TXB 33 -+#define AVALANCHE_MAC_RXB 34 -+/* Line #35 Reserved */ -+/* Line #36 Reserved */ -+/* Line #37 Reserved */ -+/* Line #38 Reserved */ -+/* Line #39 Reserved */ ++void avalanche_power_ctrl(unsigned int power_module, AVALANCHE_POWER_CTRL_T power_ctrl); ++AVALANCHE_POWER_CTRL_T avalanche_get_power_status(unsigned int power_module); ++void avalanche_set_global_power_mode(AVALANCHE_SYS_POWER_MODE_T power_mode); ++AVALANCHE_SYS_POWER_MODE_T avalanche_get_global_power_mode(void); + -+#define DEBUG_MISSED_INTS 1 ++/***************************************************************************** ++ * Wakeup Control ++ *****************************************************************************/ + -+#ifdef DEBUG_MISSED_INTS -+struct debug_missed_int ++typedef enum AVALANCHE_WAKEUP_INTERRUPT_tag +{ -+ unsigned int atm_sar_txa; -+ unsigned int atm_sar_txb; -+ unsigned int atm_sar_rxa; -+ unsigned int atm_sar_rxb; -+ unsigned int mac_txa; -+ unsigned int mac_rxa; -+ unsigned int mac_txb; -+ unsigned int mac_rxb; -+}; -+#endif /* DEBUG_MISSED_INTS */ ++ WAKEUP_INT0 = 1, ++ WAKEUP_INT1 = 2, ++ WAKEUP_INT2 = 4, ++ WAKEUP_INT3 = 8 ++} AVALANCHE_WAKEUP_INTERRUPT_T; + -+/*-----------------------------------*/ -+/* Avalanche Secondary Interrupts */ -+/*-----------------------------------*/ -+#define PRIMARY_INTS 40 ++typedef enum TNETV1050_WAKEUP_CTRL_tag ++{ ++ WAKEUP_DISABLED = 0, ++ WAKEUP_ENABLED ++} AVALANCHE_WAKEUP_CTRL_T; + -+#define AVALANCHE_HDLC_STATUS (0 + PRIMARY_INTS) -+#define AVALANCHE_SAR_STATUS (1 + PRIMARY_INTS) -+/* Line #02 Reserved */ -+#define AVALANCHE_ETH_MACA_LNK_CHG (3 + PRIMARY_INTS) -+#define AVALANCHE_ETH_MACA_MGT (4 + PRIMARY_INTS) -+#define AVALANCHE_PCI_STATUS_INT (5 + PRIMARY_INTS) -+/* Line #06 Reserved */ -+#define AVALANCHE_EXTERN_MEM_INT (7 + PRIMARY_INTS) -+#define AVALANCHE_DSP_A_DOG (8 + PRIMARY_INTS) -+#define AVALANCHE_DSP_B_DOG (9 + PRIMARY_INTS) -+/* Line #10-#20 Reserved */ -+#define AVALANCHE_ETH_MACB_LNK_CHG (21 + PRIMARY_INTS) -+#define AVALANCHE_ETH_MACB_MGT (22 + PRIMARY_INTS) -+#define AVALANCHE_AAL2_STATUS (23 + PRIMARY_INTS) -+/* Line #24-#31 Reserved */ -+ -+#define AVALANCHEINT_UART0 LNXINTNUM(AVALANCHE_UART0_INT) -+#define AVALANCHEINT_UART1 LNXINTNUM(AVALANCHE_UART1_INT) -+#define SEADINT_UART0 3 /* TTYS0 interrupt on SEAD */ -+#define SEADINT_UART1 4 /* TTYS1 interrupt on SEAD */ -+ -+#ifdef JIMK_INT_CTRLR -+/*-----------------------------------*/ -+/* Jim Kennedy's Interrupt Controller*/ -+/*-----------------------------------*/ ++typedef enum TNETV1050_WAKEUP_POLARITY_tag ++{ ++ WAKEUP_ACTIVE_HIGH = 0, ++ WAKEUP_ACTIVE_LOW ++} AVALANCHE_WAKEUP_POLARITY_T; + -+/* to clear the interrupt write the bit back to the status reg */ ++void avalanche_wakeup_ctrl(AVALANCHE_WAKEUP_INTERRUPT_T wakeup_int, ++ AVALANCHE_WAKEUP_CTRL_T wakeup_ctrl, ++ AVALANCHE_WAKEUP_POLARITY_T wakeup_polarity); + -+#define JIMK_INT_STATUS (*(volatile unsigned int *)(0xA8612400)) -+#define JIMK_INT_MASK (*(volatile unsigned int *)(0xA8612404)) -+#define JIMK_SAR_STATUS (1<<0) -+#define JIMK_SAR_TX_A (1<<1) -+#define JIMK_SAR_TX_B (1<<2) -+#define JIMK_SAR_RX_A (1<<3) -+#define JIMK_SAR_RX_B (1<<4) -+#define JIMK_AAL2_STATUS (1<<5) -+#define JIMK_UART0_INT (1<<11) ++/***************************************************************************** ++ * GPIO Control ++ *****************************************************************************/ + -+#ifdef SEAD_USB_DEVELOPMENT -+#define JIMK_USB_INT (1<<0) -+#endif /* SEAD_USB_DEVELOPMENT */ ++typedef enum AVALANCHE_GPIO_PIN_MODE_tag ++{ ++ FUNCTIONAL_PIN = 0, ++ GPIO_PIN = 1 ++} AVALANCHE_GPIO_PIN_MODE_T; + -+#endif /* JIMK_INT_CTRLR */ ++typedef enum AVALANCHE_GPIO_PIN_DIRECTION_tag ++{ ++ GPIO_OUTPUT_PIN = 0, ++ GPIO_INPUT_PIN = 1 ++} AVALANCHE_GPIO_PIN_DIRECTION_T; + -+extern void avalanche_int_set(int channel, int line); -+extern void avalancheint_init(void); ++typedef enum { GPIO_FALSE, GPIO_TRUE } AVALANCHE_GPIO_BOOL_T; + ++void avalanche_gpio_init(void); ++int avalanche_gpio_ctrl(unsigned int gpio_pin, ++ AVALANCHE_GPIO_PIN_MODE_T pin_mode, ++ AVALANCHE_GPIO_PIN_DIRECTION_T pin_direction); ++int avalanche_gpio_out_bit(unsigned int gpio_pin, int value); ++int avalanche_gpio_in_bit(unsigned int gpio_pin); ++int avalanche_gpio_out_value(unsigned int out_val, unsigned int set_mask, ++ unsigned int reg_index); ++int avalanche_gpio_in_value(unsigned int *in_val, unsigned int reg_index); + -+#endif /* !(_MIPS_AVALANCHEINT_H) */ ++unsigned int avalanche_get_chip_version_info(void); + ++unsigned int avalanche_get_vbus_freq(void); ++void avalanche_set_vbus_freq(unsigned int); + + ++typedef int (*SET_MDIX_ON_CHIP_FN_T)(unsigned int base_addr, unsigned int operation); ++int avalanche_set_mdix_on_chip(unsigned int base_addr, unsigned int operation); ++unsigned int avalanche_is_mdix_on_chip(void); + ++#endif diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm-mips/ar7/avalanche_prom.h --- linux.old/include/asm-mips/ar7/avalanche_prom.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-07 04:39:14.431224000 +0200 ++++ linux.dev/include/asm-mips/ar7/avalanche_prom.h 2005-07-09 08:00:15.302024000 +0200 @@ -0,0 +1,54 @@ +/* $Id$ + * @@ -4373,7 +4591,7 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_prom.h linux.dev/include/asm- + diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm-mips/ar7/avalanche_regs.h --- linux.old/include/asm-mips/ar7/avalanche_regs.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-07 04:39:14.433224000 +0200 ++++ linux.dev/include/asm-mips/ar7/avalanche_regs.h 2005-07-09 08:00:15.303024000 +0200 @@ -0,0 +1,567 @@ +/* + * $Id$ @@ -4942,9 +5160,383 @@ diff -urN linux.old/include/asm-mips/ar7/avalanche_regs.h linux.dev/include/asm- + + + +diff -urN linux.old/include/asm-mips/ar7/hal/haltypes.h linux.dev/include/asm-mips/ar7/hal/haltypes.h +--- linux.old/include/asm-mips/ar7/hal/haltypes.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/hal/haltypes.h 2005-07-09 08:00:15.303024000 +0200 +@@ -0,0 +1,46 @@ ++/****************************************************************************** ++ * FILE PURPOSE: Platform dependent type information Header ++ ******************************************************************************** ++ * FILE NAME: haltypes.h ++ * ++ * DESCRIPTION: Platform dependent (tuned) types definations. ++ * Intented to be used by HAL/Drivers etc. ++ * ++ * REVISION HISTORY: ++ * 27 Nov 02 - PSP TII ++ * ++ * (C) Copyright 2002, Texas Instruments, Inc ++ *******************************************************************************/ ++ ++#ifndef __HAL_TYPES_H__ ++#define __HAL_TYPES_H__ ++ ++typedef char INT8; ++typedef short INT16; ++typedef int INT32; ++ ++typedef unsigned char UINT8; ++typedef unsigned short UINT16; ++typedef unsigned int UINT32; ++ ++typedef unsigned char UCHAR; ++typedef unsigned short USHORT; ++typedef unsigned int UINT; ++typedef unsigned long ULONG; ++ ++typedef int BOOL; ++typedef int STATUS; ++ ++#ifndef FALSE ++#define FALSE 0 ++#endif ++ ++#ifndef TRUE ++#define TRUE 1 ++#endif ++ ++#ifndef NULL ++#define NULL 0 ++#endif ++ ++#endif /* __HAL_TYPES_H__ */ +diff -urN linux.old/include/asm-mips/ar7/if_port.h linux.dev/include/asm-mips/ar7/if_port.h +--- linux.old/include/asm-mips/ar7/if_port.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/if_port.h 2005-07-09 08:00:15.304024000 +0200 +@@ -0,0 +1,26 @@ ++/******************************************************************************* ++ * FILE PURPOSE: Interface port id Header file ++ ******************************************************************************* ++ * FILE NAME: if_port.h ++ * ++ * DESCRIPTION: Header file carrying information about port ids of interfaces ++ * ++ * ++ * (C) Copyright 2003, Texas Instruments, Inc ++ ******************************************************************************/ ++#ifndef _IF_PORT_H_ ++#define _IF_PORT_H_ ++ ++#define AVALANCHE_CPMAC_LOW_PORT_ID 0 ++#define AVALANCHE_CPMAC_HIGH_PORT_ID 1 ++#define AVALANCHE_USB_PORT_ID 2 ++#define AVALANCHE_WLAN_PORT_ID 3 ++ ++ ++#define AVALANCHE_MARVELL_BASE_PORT_ID 4 ++ ++/* The marvell ports occupy port ids from 4 to 8 */ ++/* so the next port id number should start at 9 */ ++ ++ ++#endif /* _IF_PORT_H_ */ +diff -urN linux.old/include/asm-mips/ar7/sangam_boards.h linux.dev/include/asm-mips/ar7/sangam_boards.h +--- linux.old/include/asm-mips/ar7/sangam_boards.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/sangam_boards.h 2005-07-09 08:00:15.304024000 +0200 +@@ -0,0 +1,77 @@ ++#ifndef _SANGAM_BOARDS_H ++#define _SANGAM_BOARDS_H ++ ++// Let us define board specific information here. ++ ++ ++#if defined(CONFIG_AR7DB) ++ ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++ ++#endif ++ ++ ++#if defined(CONFIG_AR7RD) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++#endif ++ ++ ++#if defined(CONFIG_AR7WI) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++#endif ++ ++ ++#if defined(CONFIG_AR7V) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x2 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++#endif ++ ++ ++#if defined(CONFIG_AR7WRD) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++#endif ++ ++ ++#if defined(CONFIG_AR7VWI) ++#define AFECLK_FREQ 35328000 ++#define REFCLK_FREQ 25000000 ++#define OSC3_FREQ 24000000 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0x80000000 ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x00010000 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0x80000000 ++#endif ++ ++ ++#if defined CONFIG_SEAD2 ++#define AVALANCHE_LOW_CPMAC_PHY_MASK 0xAAAAAAAA ++#define AVALANCHE_HIGH_CPMAC_PHY_MASK 0x55555555 ++#define AVALANCHE_LOW_CPMAC_MDIX_MASK 0 ++#include <asm/mips-boards/sead.h> ++#endif ++ ++ ++#endif +diff -urN linux.old/include/asm-mips/ar7/sangam_clk_cntl.h linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h +--- linux.old/include/asm-mips/ar7/sangam_clk_cntl.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/sangam_clk_cntl.h 2005-07-09 08:00:15.304024000 +0200 +@@ -0,0 +1,25 @@ ++/***************************************************************************** ++ * Clock Control ++ *****************************************************************************/ ++#ifndef _SANGAM_CLK_CNTL_H_ ++#define _SANGAM_CLK_CNTL_H_ ++#include <asm/ar7/avalanche_misc.h> ++ ++#define CLK_MHZ(x) ( (x) * 1000000 ) ++ ++/* The order of ENUMs here should not be altered since ++ * the register addresses are derived from the order ++ */ ++ ++typedef enum AVALANCHE_CLKC_ID_tag ++{ ++ CLKC_VBUS, ++ CLKC_MIPS, ++ CLKC_USB, ++ CLKC_SYS ++} AVALANCHE_CLKC_ID_T; ++ ++void avalanche_clkc_init(unsigned int afe_clk,unsigned int refclk, unsigned int xtal3in); ++int avalanche_clkc_set_freq(AVALANCHE_CLKC_ID_T clk_id, unsigned int output_freq); ++unsigned int avalanche_clkc_get_freq(AVALANCHE_CLKC_ID_T clk_id); ++#endif +diff -urN linux.old/include/asm-mips/ar7/sangam.h linux.dev/include/asm-mips/ar7/sangam.h +--- linux.old/include/asm-mips/ar7/sangam.h 1970-01-01 01:00:00.000000000 +0100 ++++ linux.dev/include/asm-mips/ar7/sangam.h 2005-07-09 08:00:15.305023000 +0200 +@@ -0,0 +1,180 @@ ++#ifndef _SANGAM_H_ ++#define _SANGAM_H_ ++ ++#include <linux/config.h> ++#include <asm/addrspace.h> ++ ++/*---------------------------------------------------- ++ * Sangam's Module Base Addresses ++ *--------------------------------------------------*/ ++#define AVALANCHE_ADSL_SUB_SYS_MEM_BASE (KSEG1ADDR(0x01000000)) /* AVALANCHE ADSL Mem Base */ ++#define AVALANCHE_BROADBAND_INTERFACE__BASE (KSEG1ADDR(0x02000000)) /* AVALANCHE BBIF */ ++#define AVALANCHE_ATM_SAR_BASE (KSEG1ADDR(0x03000000)) /* AVALANCHE ATM SAR */ ++#define AVALANCHE_USB_SLAVE_BASE (KSEG1ADDR(0x03400000)) /* AVALANCHE USB SLAVE */ ++#define AVALANCHE_LOW_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x04000000)) /* AVALANCHE VLYNQ 0 Mem map */ ++#define AVALANCHE_LOW_CPMAC_BASE (KSEG1ADDR(0x08610000)) /* AVALANCHE CPMAC 0 */ ++#define AVALANCHE_EMIF_CONTROL_BASE (KSEG1ADDR(0x08610800)) /* AVALANCHE EMIF */ ++#define AVALANCHE_GPIO_BASE (KSEG1ADDR(0x08610900)) /* AVALANCHE GPIO */ ++#define AVALANCHE_CLOCK_CONTROL_BASE (KSEG1ADDR(0x08610A00)) /* AVALANCHE Clock Control */ ++#define AVALANCHE_WATCHDOG_TIMER_BASE (KSEG1ADDR(0x08610B00)) /* AVALANCHE Watch Dog Timer */ ++#define AVALANCHE_TIMER0_BASE (KSEG1ADDR(0x08610C00)) /* AVALANCHE Timer 1 */ ++#define AVALANCHE_TIMER1_BASE (KSEG1ADDR(0x08610D00)) /* AVALANCHE Timer 2 */ ++#define AVALANCHE_UART0_REGS_BASE (KSEG1ADDR(0x08610E00)) /* AVALANCHE UART 0 */ ++#define AVALANCHE_UART1_REGS_BASE (KSEG1ADDR(0x08610F00)) /* AVALANCHE UART 0 */ ++#define AVALANCHE_I2C_BASE (KSEG1ADDR(0x08611000)) /* AVALANCHE I2C */ ++#define AVALANCHE_USB_SLAVE_CONTROL_BASE (KSEG1ADDR(0x08611200)) /* AVALANCHE USB DMA */ ++#define AVALANCHE_MCDMA0_CTRL_BASE (KSEG1ADDR(0x08611400)) /* AVALANCHE MC DMA 0 (channels 0-3) */ ++#define AVALANCHE_RESET_CONTROL_BASE (KSEG1ADDR(0x08611600)) /* AVALANCHE Reset Control */ ++#define AVALANCHE_BIST_CONTROL_BASE (KSEG1ADDR(0x08611700)) /* AVALANCHE BIST Control */ ++#define AVALANCHE_LOW_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611800)) /* AVALANCHE VLYNQ0 Control */ ++#define AVALANCHE_DEVICE_CONFIG_LATCH_BASE (KSEG1ADDR(0x08611A00)) /* AVALANCHE Device Config Latch */ ++#define AVALANCHE_HIGH_VLYNQ_CONTROL_BASE (KSEG1ADDR(0x08611C00)) /* AVALANCHE VLYNQ1 Control */ ++#define AVALANCHE_MDIO_BASE (KSEG1ADDR(0x08611E00)) /* AVALANCHE MDIO */ ++#define AVALANCHE_FSER_BASE (KSEG1ADDR(0x08612000)) /* AVALANCHE FSER base */ ++#define AVALANCHE_INTC_BASE (KSEG1ADDR(0x08612400)) /* AVALANCHE INTC */ ++#define AVALANCHE_HIGH_CPMAC_BASE (KSEG1ADDR(0x08612800)) /* AVALANCHE CPMAC 1 */ ++#define AVALANCHE_HIGH_VLYNQ_MEM_MAP_BASE (KSEG1ADDR(0x0C000000)) /* AVALANCHE VLYNQ 1 Mem map */ ++ ++#define AVALANCHE_SDRAM_BASE 0x14000000UL ++ ++ ++/*---------------------------------------------------- ++ * Sangam Interrupt Map (Primary Interrupts) ++ *--------------------------------------------------*/ ++ ++#define AVALANCHE_UNIFIED_SECONDARY_INT 0 ++#define AVALANCHE_EXT_INT_0 1 ++#define AVALANCHE_EXT_INT_1 2 ++/* Line# 3 to 4 are reserved */ ++#define AVALANCHE_TIMER_0_INT 5 ++#define AVALANCHE_TIMER_1_INT 6 ++#define AVALANCHE_UART0_INT 7 ++#define AVALANCHE_UART1_INT 8 ++#define AVALANCHE_DMA_INT0 9 ++#define AVALANCHE_DMA_INT1 10 ++/* Line# 11 to 14 are reserved */ ++#define AVALANCHE_ATM_SAR_INT 15 ++/* Line# 16 to 18 are reserved */ ++#define AVALANCHE_LOW_CPMAC_INT 19 ++/* Line# 20 is reserved */ ++#define AVALANCHE_LOW_VLYNQ_INT 21 ++#define AVALANCHE_CODEC_WAKEUP_INT 22 ++/* Line# 23 is reserved */ ++#define AVALANCHE_USB_SLAVE_INT 24 ++#define AVALANCHE_HIGH_VLYNQ_INT 25 ++/* Line# 26 to 27 are reserved */ ++#define AVALANCHE_UNIFIED_PHY_INT 28 ++#define AVALANCHE_I2C_INT 29 ++#define AVALANCHE_DMA_INT2 30 ++#define AVALANCHE_DMA_INT3 31 ++/* Line# 32 is reserved */ ++#define AVALANCHE_HIGH_CPMAC_INT 33 ++/* Line# 34 to 36 is reserved */ ++#define AVALANCHE_VDMA_VT_RX_INT 37 ++#define AVALANCHE_VDMA_VT_TX_INT 38 ++#define AVALANCHE_ADSL_SUB_SYSTEM_INT 39 ++ ++ ++#define AVALANCHE_EMIF_INT 47 ++ ++ ++ ++/*----------------------------------------------------------- ++ * Sangam's Reset Bits ++ *---------------------------------------------------------*/ ++ ++#define AVALANCHE_UART0_RESET_BIT 0 ++#define AVALANCHE_UART1_RESET_BIT 1 ++#define AVALANCHE_I2C_RESET_BIT 2 ++#define AVALANCHE_TIMER0_RESET_BIT 3 ++#define AVALANCHE_TIMER1_RESET_BIT 4 ++/* Reset bit 5 is reserved. */ ++#define AVALANCHE_GPIO_RESET_BIT 6 ++#define AVALANCHE_ADSL_SUB_SYS_RESET_BIT 7 ++#define AVALANCHE_USB_SLAVE_RESET_BIT 8 ++#define AVALANCHE_ATM_SAR_RESET_BIT 9 ++/* Reset bit 10 is reserved. */ ++#define AVALANCHE_VDMA_VT_RESET_BIT 11 ++#define AVALANCHE_FSER_RESET_BIT 12 ++/* Reset bit 13 to 15 are reserved */ ++#define AVALANCHE_HIGH_VLYNQ_RESET_BIT 16 ++#define AVALANCHE_LOW_CPMAC_RESET_BIT 17 ++#define AVALANCHE_MCDMA_RESET_BIT 18 ++#define AVALANCHE_BIST_RESET_BIT 19 ++#define AVALANCHE_LOW_VLYNQ_RESET_BIT 20 ++#define AVALANCHE_HIGH_CPMAC_RESET_BIT 21 ++#define AVALANCHE_MDIO_RESET_BIT 22 ++#define AVALANCHE_ADSL_SUB_SYS_DSP_RESET_BIT 23 ++/* Reset bit 24 to 25 are reserved */ ++#define AVALANCHE_LOW_EPHY_RESET_BIT 26 ++/* Reset bit 27 to 31 are reserved */ ++ ++ ++#define AVALANCHE_POWER_MODULE_USBSP 0 ++#define AVALANCHE_POWER_MODULE_WDTP 1 ++#define AVALANCHE_POWER_MODULE_UT0P 2 ++#define AVALANCHE_POWER_MODULE_UT1P 3 ++#define AVALANCHE_POWER_MODULE_IICP 4 ++#define AVALANCHE_POWER_MODULE_VDMAP 5 ++#define AVALANCHE_POWER_MODULE_GPIOP 6 ++#define AVALANCHE_POWER_MODULE_VLYNQ1P 7 ++#define AVALANCHE_POWER_MODULE_SARP 8 ++#define AVALANCHE_POWER_MODULE_ADSLP 9 ++#define AVALANCHE_POWER_MODULE_EMIFP 10 ++#define AVALANCHE_POWER_MODULE_ADSPP 12 ++#define AVALANCHE_POWER_MODULE_RAMP 13 ++#define AVALANCHE_POWER_MODULE_ROMP 14 ++#define AVALANCHE_POWER_MODULE_DMAP 15 ++#define AVALANCHE_POWER_MODULE_BISTP 16 ++#define AVALANCHE_POWER_MODULE_TIMER0P 18 ++#define AVALANCHE_POWER_MODULE_TIMER1P 19 ++#define AVALANCHE_POWER_MODULE_EMAC0P 20 ++#define AVALANCHE_POWER_MODULE_EMAC1P 22 ++#define AVALANCHE_POWER_MODULE_EPHYP 24 ++#define AVALANCHE_POWER_MODULE_VLYNQ0P 27 ++ ++ ++ ++ ++ ++/* ++ * Sangam board vectors ++ */ ++ ++#define AVALANCHE_VECS (KSEG1ADDR(AVALANCHE_SDRAM_BASE)) ++#define AVALANCHE_VECS_KSEG0 (KSEG0ADDR(AVALANCHE_SDRAM_BASE)) ++ ++/*----------------------------------------------------------------------------- ++ * Sangam's system register. ++ * ++ *---------------------------------------------------------------------------*/ ++#define AVALANCHE_DCL_BOOTCR (KSEG1ADDR(0x08611A00)) ++#define AVALANCHE_EMIF_SDRAM_CFG (AVALANCHE_EMIF_CONTROL_BASE + 0x8) ++#define AVALANCHE_RST_CTRL_PRCR (KSEG1ADDR(0x08611600)) ++#define AVALANCHE_RST_CTRL_SWRCR (KSEG1ADDR(0x08611604)) ++#define AVALANCHE_RST_CTRL_RSR (KSEG1ADDR(0x08611600)) ++ ++#define AVALANCHE_POWER_CTRL_PDCR (KSEG1ADDR(0x08610A00)) ++#define AVALANCHE_WAKEUP_CTRL_WKCR (KSEG1ADDR(0x08610A0C)) ++ ++#define AVALANCHE_GPIO_DATA_IN (AVALANCHE_GPIO_BASE + 0x0) ++#define AVALANCHE_GPIO_DATA_OUT (AVALANCHE_GPIO_BASE + 0x4) ++#define AVALANCHE_GPIO_DIR (AVALANCHE_GPIO_BASE + 0x8) ++#define AVALANCHE_GPIO_ENBL (AVALANCHE_GPIO_BASE + 0xC) ++#define AVALANCHE_CVR (AVALANCHE_GPIO_BASE + 0x14) ++ ++/* ++ * Yamon Prom print address. ++ */ ++#define AVALANCHE_YAMON_FUNCTION_BASE (KSEG1ADDR(0x10000500)) ++#define AVALANCHE_YAMON_PROM_PRINT_COUNT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x4) /* print_count function */ ++#define AVALANCHE_YAMON_PROM_PRINT_ADDR (AVALANCHE_YAMON_FUNCTION_BASE + 0x34) ++ ++#define AVALANCHE_BASE_BAUD ( 3686400 / 16 ) ++ ++#define AVALANCHE_GPIO_PIN_COUNT 32 ++#define AVALANCHE_GPIO_OFF_MAP {0xF34FFFC0} ++ ++#include "sangam_boards.h" ++ ++#endif /*_SANGAM_H_ */ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-mips/ar7/tnetd73xx_err.h --- linux.old/include/asm-mips/ar7/tnetd73xx_err.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-07 04:39:14.434224000 +0200 ++++ linux.dev/include/asm-mips/ar7/tnetd73xx_err.h 2005-07-09 08:00:15.305023000 +0200 @@ -0,0 +1,42 @@ +/****************************************************************************** + * FILE PURPOSE: TNETD73xx Error Definations Header File @@ -4990,7 +5582,7 @@ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_err.h linux.dev/include/asm-m +#endif /* __TNETD73XX_ERR_H__ */ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ar7/tnetd73xx.h --- linux.old/include/asm-mips/ar7/tnetd73xx.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-07 04:39:14.433224000 +0200 ++++ linux.dev/include/asm-mips/ar7/tnetd73xx.h 2005-07-09 08:00:15.306023000 +0200 @@ -0,0 +1,340 @@ +/****************************************************************************** + * FILE PURPOSE: TNETD73xx Common Header File @@ -5334,7 +5926,7 @@ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx.h linux.dev/include/asm-mips/ +#endif /* __TNETD73XX_H_ */ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h --- linux.old/include/asm-mips/ar7/tnetd73xx_misc.h 1970-01-01 01:00:00.000000000 +0100 -+++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-07 04:39:14.434224000 +0200 ++++ linux.dev/include/asm-mips/ar7/tnetd73xx_misc.h 2005-07-09 08:00:15.306023000 +0200 @@ -0,0 +1,243 @@ +/****************************************************************************** + * FILE PURPOSE: TNETD73xx Misc modules API Header @@ -5580,8 +6172,8 @@ diff -urN linux.old/include/asm-mips/ar7/tnetd73xx_misc.h linux.dev/include/asm- + +#endif /* __TNETD73XX_MISC_H__ */ diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h ---- linux.old/include/asm-mips/io.h 2005-07-07 05:38:31.416480768 +0200 -+++ linux.dev/include/asm-mips/io.h 2005-07-07 04:39:14.434224000 +0200 +--- linux.old/include/asm-mips/io.h 2005-07-09 08:01:49.846651440 +0200 ++++ linux.dev/include/asm-mips/io.h 2005-07-09 08:00:15.307023000 +0200 @@ -63,8 +63,12 @@ #ifdef CONFIG_64BIT_PHYS_ADDR #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT) @@ -5596,8 +6188,8 @@ diff -urN linux.old/include/asm-mips/io.h linux.dev/include/asm-mips/io.h #define IO_SPACE_LIMIT 0xffff diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h ---- linux.old/include/asm-mips/irq.h 2005-07-07 05:38:31.424479552 +0200 -+++ linux.dev/include/asm-mips/irq.h 2005-07-07 04:39:14.435224000 +0200 +--- linux.old/include/asm-mips/irq.h 2005-07-09 08:01:49.847651288 +0200 ++++ linux.dev/include/asm-mips/irq.h 2005-07-09 08:00:15.307023000 +0200 @@ -14,7 +14,12 @@ #include <linux/config.h> #include <linux/linkage.h> @@ -5612,8 +6204,8 @@ diff -urN linux.old/include/asm-mips/irq.h linux.dev/include/asm-mips/irq.h #ifdef CONFIG_I8259 static inline int irq_cannonicalize(int irq) diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h ---- linux.old/include/asm-mips/page.h 2005-07-07 05:38:31.426479248 +0200 -+++ linux.dev/include/asm-mips/page.h 2005-07-07 04:39:14.435224000 +0200 +--- linux.old/include/asm-mips/page.h 2005-07-09 08:01:49.847651288 +0200 ++++ linux.dev/include/asm-mips/page.h 2005-07-09 08:00:15.308023000 +0200 @@ -129,7 +129,11 @@ #define __pa(x) ((unsigned long) (x) - PAGE_OFFSET) @@ -5627,8 +6219,8 @@ diff -urN linux.old/include/asm-mips/page.h linux.dev/include/asm-mips/page.h #define VM_DATA_DEFAULT_FLAGS (VM_READ | VM_WRITE | VM_EXEC | \ diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgtable-32.h ---- linux.old/include/asm-mips/pgtable-32.h 2005-07-07 05:38:31.434478032 +0200 -+++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-07 04:39:14.435224000 +0200 +--- linux.old/include/asm-mips/pgtable-32.h 2005-07-09 08:01:49.847651288 +0200 ++++ linux.dev/include/asm-mips/pgtable-32.h 2005-07-09 08:00:15.308023000 +0200 @@ -108,7 +108,18 @@ * and a page entry and page directory to the page they refer to. */ @@ -5670,8 +6262,8 @@ diff -urN linux.old/include/asm-mips/pgtable-32.h linux.dev/include/asm-mips/pgt #define __mk_pte(page_nr,pgprot) __pte(((page_nr) << (PAGE_SHIFT+2)) | pgprot_val(pgprot)) #else diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial.h ---- linux.old/include/asm-mips/serial.h 2005-07-07 05:38:31.470472560 +0200 -+++ linux.dev/include/asm-mips/serial.h 2005-07-07 04:39:14.436223000 +0200 +--- linux.old/include/asm-mips/serial.h 2005-07-09 08:01:49.848651136 +0200 ++++ linux.dev/include/asm-mips/serial.h 2005-07-09 08:00:15.308023000 +0200 @@ -65,6 +65,15 @@ #define C_P(card,port) (((card)<<6|(port)<<3) + 1) @@ -5697,8 +6289,8 @@ diff -urN linux.old/include/asm-mips/serial.h linux.dev/include/asm-mips/serial. AU1000_SERIAL_PORT_DEFNS \ COBALT_SERIAL_PORT_DEFNS \ diff -urN linux.old/Makefile linux.dev/Makefile ---- linux.old/Makefile 2005-07-07 05:38:31.320495360 +0200 -+++ linux.dev/Makefile 2005-07-07 04:39:14.501214000 +0200 +--- linux.old/Makefile 2005-07-09 08:01:49.848651136 +0200 ++++ linux.dev/Makefile 2005-07-09 08:00:15.404008000 +0200 @@ -91,7 +91,7 @@ CPPFLAGS := -D__KERNEL__ -I$(HPATH) |