diff options
Diffstat (limited to 'target/linux/layerscape')
13 files changed, 2094 insertions, 0 deletions
diff --git a/target/linux/layerscape/image/Makefile b/target/linux/layerscape/image/Makefile index c70955785b..341d5fbda0 100644 --- a/target/linux/layerscape/image/Makefile +++ b/target/linux/layerscape/image/Makefile @@ -106,4 +106,18 @@ endif endef TARGET_DEVICES += ls1088ardb +define Device/ls2088ardb + DEVICE_TITLE := ls2088ardb-$(SUBTARGET) + DEVICE_PACKAGES += rcw-layerscape-ls2088ardb uboot-layerscape-$(SUBTARGET)-ls2088ardb mc-binary-ls2088ardb +ifeq ($(SUBTARGET),64b) + DEVICE_DTS = freescale/fsl-ls2088a-rdb +endif +ifeq ($(SUBTARGET),32b) + DEVICE_DTS = ../../../arm64/boot/dts/freescale/fsl-ls2088a-rdb +endif + IMAGE/firmware.bin = append-ls-dtb $$(DEVICE_DTS) | pad-to 1M | append-kernel | pad-to 6M | \ + append-rootfs | pad-rootfs | check-size 24117249 +endef +TARGET_DEVICES += ls2088ardb + $(eval $(call BuildImage)) diff --git a/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch b/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch new file mode 100644 index 0000000000..d8f6c2b7df --- /dev/null +++ b/target/linux/layerscape/patches-4.4/0238-arm64-disable-CONFIG_EEPROM_AT24-for-freescale.confi.patch @@ -0,0 +1,29 @@ +From fbc31a61b7bcfbc9ae1a8acda547de891f4b8ee4 Mon Sep 17 00:00:00 2001 +From: Yangbo Lu <yangbo.lu@nxp.com> +Date: Mon, 31 Oct 2016 17:50:03 +0800 +Subject: [PATCH 238/238] arm64: disable CONFIG_EEPROM_AT24 for + freescale.config + +Disable CONFIG_EEPROM_AT24 in freescale.config. Otherwise, i2cdump +for EEPROM will get resource busy issue. + +Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> +--- + arch/arm64/configs/freescale.config | 1 - + 1 file changed, 1 deletion(-) + +diff --git a/arch/arm64/configs/freescale.config b/arch/arm64/configs/freescale.config +index a31951c..5447d7a 100644 +--- a/arch/arm64/configs/freescale.config ++++ b/arch/arm64/configs/freescale.config +@@ -121,7 +121,6 @@ CONFIG_IMX2_WDT=y + CONFIG_HWMON=y + CONFIG_SENSORS_LM90=y + CONFIG_SENSORS_INA2XX=y +-CONFIG_EEPROM_AT24=y + # lpuart + CONFIG_SERIAL_FSL_LPUART=y + CONFIG_SERIAL_FSL_LPUART_CONSOLE=y +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch b/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch new file mode 100644 index 0000000000..8254490bb0 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/1239-mtd-extend-physmap_of-to-let-the-device-tree-specify.patch @@ -0,0 +1,90 @@ +From 6b54054c4053215fe4add195c67daca9a466ba92 Mon Sep 17 00:00:00 2001 +From: "ying.zhang" <ying.zhang22455@nxp.com> +Date: Fri, 23 Dec 2016 22:21:22 +0800 +Subject: [PATCH] mtd: extend physmap_of to let the device tree specify the + parition probe + +This is to support custom partitioning schemes for embedded PPC. To use +define your own mtd_part_parser and then add something like: + linux,part-probe = "my_probe", "cmdlinepart"; + To the board's dts file. + +If linux,part-probe is not specified then this behaves the same as before. + +Signed-off-by: Jason Gunthorpe <jgunthorpe@obsidianresearch.com> +Signed-off-by: David Woodhouse <David.Woodhouse@intel.com> +--- + drivers/mtd/maps/physmap_of.c | 46 ++++++++++++++++++++++++++++++++++++++++- + 1 file changed, 45 insertions(+), 1 deletion(-) + +diff --git a/drivers/mtd/maps/physmap_of.c b/drivers/mtd/maps/physmap_of.c +index fef1d1b..e46b4e9 100644 +--- a/drivers/mtd/maps/physmap_of.c ++++ b/drivers/mtd/maps/physmap_of.c +@@ -112,9 +112,47 @@ static struct mtd_info *obsolete_probe(struct platform_device *dev, + static const char * const part_probe_types_def[] = { + "cmdlinepart", "RedBoot", "ofpart", "ofoldpart", NULL }; + ++static const char * const *of_get_probes(struct device_node *dp) ++{ ++ const char *cp; ++ int cplen; ++ unsigned int l; ++ unsigned int count; ++ const char **res; ++ ++ cp = of_get_property(dp, "linux,part-probe", &cplen); ++ if (cp == NULL) ++ return part_probe_types_def; ++ ++ count = 0; ++ for (l = 0; l != cplen; l++) ++ if (cp[l] == 0) ++ count++; ++ ++ res = kzalloc((count + 1)*sizeof(*res), GFP_KERNEL); ++ if (!res) ++ return NULL; ++ count = 0; ++ while (cplen > 0) { ++ res[count] = cp; ++ l = strlen(cp) + 1; ++ cp += l; ++ cplen -= l; ++ count++; ++ } ++ return res; ++} ++ ++static void of_free_probes(const char * const *probes) ++{ ++ if (probes != part_probe_types_def) ++ kfree(probes); ++} ++ + static const struct of_device_id of_flash_match[]; + static int of_flash_probe(struct platform_device *dev) + { ++ const char * const *part_probe_types; + const struct of_device_id *match; + struct device_node *dp = dev->dev.of_node; + struct resource res; +@@ -273,8 +311,14 @@ static int of_flash_probe(struct platform_device *dev) + goto err_out; + + ppdata.of_node = dp; +- mtd_device_parse_register(info->cmtd, part_probe_types_def, &ppdata, ++ part_probe_types = of_get_probes(dp); ++ if (!part_probe_types) { ++ err = -ENOMEM; ++ goto err_out; ++ } ++ mtd_device_parse_register(info->cmtd, part_probe_types, &ppdata, + NULL, 0); ++ of_free_probes(part_probe_types); + + kfree(mtd_list); + +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch b/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch new file mode 100644 index 0000000000..91de6f4019 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3227-ls2088a-dts-add-ls2088a-dts.patch @@ -0,0 +1,1352 @@ +From 45ba5bb2bdc9462fe5998aeb75e2c7e33b56c9fb Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <qiang.zhao@nxp.com> +Date: Mon, 7 Nov 2016 10:23:52 +0800 +Subject: [PATCH 227/238] ls2088a/dts: add ls2088a dts + +Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> +--- + arch/arm64/boot/dts/freescale/Makefile | 2 + + arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts | 241 ++++++ + arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts | 207 +++++ + arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 854 +++++++++++++++++++++ + 4 files changed, 1304 insertions(+) + create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts + create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts + create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi + +diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile +index b599645..e6c2a9f 100644 +--- a/arch/arm64/boot/dts/freescale/Makefile ++++ b/arch/arm64/boot/dts/freescale/Makefile +@@ -6,6 +6,8 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb + dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb ++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb ++dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb + + always := $(dtb-y) + subdir-y := $(dts-dirs) +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +new file mode 100644 +index 0000000..04d3726 +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts +@@ -0,0 +1,241 @@ ++/* ++ * Device Tree file for Freescale LS2080a QDS Board ++ * ++ * Copyright (C) 2016, Freescale Semiconductor ++ * ++ * Abhimanyu Saini <abhimanyu.saini@nxp.com> ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++#include "fsl-ls2088a.dtsi" ++ ++/ { ++ model = "Freescale Layerscape 2088a QDS Board"; ++ compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; ++}; ++ ++&esdhc { ++ status = "okay"; ++}; ++ ++&ifc { ++ status = "okay"; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 ++ 0x2 0x0 0x5 0x30000000 0x00010000 ++ 0x3 0x0 0x5 0x20000000 0x00010000>; ++ ++ nor@0,0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "cfi-flash"; ++ reg = <0x0 0x0 0x8000000>; ++ bank-width = <2>; ++ device-width = <1>; ++ }; ++ ++ nand@2,0 { ++ compatible = "fsl,ifc-nand"; ++ reg = <0x2 0x0 0x10000>; ++ }; ++ ++ cpld@3,0 { ++ reg = <0x3 0x0 0x10000>; ++ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis", ++ "fsl,fpga-qixis"; ++ }; ++}; ++ ++&ftm0 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ pca9547@77 { ++ compatible = "nxp,pca9547"; ++ reg = <0x77>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c@0 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x00>; ++ rtc@68 { ++ compatible = "dallas,ds3232"; ++ reg = <0x68>; ++ }; ++ }; ++ ++ i2c@2 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x02>; ++ ++ ina220@40 { ++ compatible = "ti,ina220"; ++ reg = <0x40>; ++ shunt-resistor = <500>; ++ }; ++ ina220@41 { ++ compatible = "ti,ina220"; ++ reg = <0x41>; ++ shunt-resistor = <1000>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x3>; ++ ++ adt7481@4c { ++ compatible = "adi,adt7461"; ++ reg = <0x4c>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++&dspi { ++ status = "okay"; ++ dflash0: n25q128a { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <3000000>; ++ reg = <0>; ++ }; ++ dflash1: sst25wf040b { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <3000000>; ++ reg = <1>; ++ }; ++ dflash2: en25s64 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <3000000>; ++ reg = <2>; ++ }; ++}; ++ ++&qspi { ++ status = "okay"; ++ qflash0: s25fs256s1@0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <20000000>; ++ m25p,fast-read; ++ reg = <0>; ++ }; ++ ++ qflash2: s25fs256s1@2 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <20000000>; ++ m25p,fast-read; ++ reg = <2>; ++ }; ++}; ++ ++&sata0 { ++ status = "okay"; ++}; ++ ++&sata1 { ++ status = "okay"; ++}; ++ ++&usb0 { ++ status = "okay"; ++}; ++ ++&usb1 { ++ status = "okay"; ++}; ++ ++&ifc { ++ boardctrl: board-control@3,0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; ++ reg = <3 0 0x300>; /* TODO check address */ ++ ranges = <0 3 0 0x300>; ++ ++ mdio_mux_emi1 { ++ compatible = "mdio-mux-mmioreg", "mdio-mux"; ++ mdio-parent-bus = <&emdio1>; ++ reg = <0x54 1>; /* BRDCFG4 */ ++ mux-mask = <0xe0>; /* EMI1_MDIO */ ++ ++ #address-cells=<1>; ++ #size-cells = <0>; ++ ++ /* Child MDIO buses, one for each riser card: ++ reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. ++ ++ VSC8234 PHYs on the riser cards. ++ */ ++ ++ mdio_mux3: mdio@60 { ++ reg = <0x60>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ mdio0_phy12: mdio_phy0@1c { ++ reg = <0x1c>; ++ phy-connection-type = "sgmii"; ++ }; ++ mdio0_phy13: mdio_phy1@1d { ++ reg = <0x1d>; ++ phy-connection-type = "sgmii"; ++ }; ++ mdio0_phy14: mdio_phy2@1e { ++ reg = <0x1e>; ++ phy-connection-type = "sgmii"; ++ }; ++ mdio0_phy15: mdio_phy3@1f { ++ reg = <0x1f>; ++ phy-connection-type = "sgmii"; ++ }; ++ }; ++ }; ++ }; ++}; ++ ++/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ ++&dpmac9 { ++ phy-handle = <&mdio0_phy12>; ++}; ++&dpmac10 { ++ phy-handle = <&mdio0_phy13>; ++}; ++&dpmac11 { ++ phy-handle = <&mdio0_phy14>; ++}; ++&dpmac12 { ++ phy-handle = <&mdio0_phy15>; ++}; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +new file mode 100644 +index 0000000..ce553fb +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts +@@ -0,0 +1,207 @@ ++/* ++ * Device Tree file for Freescale LS2080a RDB board ++ * ++ * Copyright (C) 2015, Freescale Semiconductor ++ * ++ * Abhimanyu Saini <abhimanyu.saini@nxp.com> ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++#include "fsl-ls2088a.dtsi" ++ ++/ { ++ model = "Freescale Layerscape 2088a RDB Board"; ++ compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; ++}; ++ ++&esdhc { ++ status = "okay"; ++}; ++ ++&ifc { ++ status = "okay"; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 ++ 0x2 0x0 0x5 0x30000000 0x00010000 ++ 0x3 0x0 0x5 0x20000000 0x00010000>; ++ ++ nor@0,0 { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "cfi-flash"; ++ reg = <0x0 0x0 0x8000000>; ++ bank-width = <2>; ++ device-width = <1>; ++ }; ++ ++ nand@2,0 { ++ compatible = "fsl,ifc-nand"; ++ reg = <0x2 0x0 0x10000>; ++ }; ++ ++ cpld@3,0 { ++ reg = <0x3 0x0 0x10000>; ++ compatible = "fsl,ls2088a-qds-qixis", "fsl,ls2080a-qds-qixis", ++ "fsl,fpga-qixis"; ++ }; ++}; ++ ++&ftm0 { ++ status = "okay"; ++}; ++ ++&i2c0 { ++ status = "okay"; ++ pca9547@75 { ++ compatible = "nxp,pca9547"; ++ reg = <0x75>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ i2c-mux-never-disable; ++ i2c@1 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x01>; ++ rtc@68 { ++ compatible = "dallas,ds3232"; ++ reg = <0x68>; ++ }; ++ }; ++ ++ i2c@3 { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x3>; ++ ++ adt7481@4c { ++ compatible = "adi,adt7461"; ++ reg = <0x4c>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c1 { ++ status = "disabled"; ++}; ++ ++&i2c2 { ++ status = "disabled"; ++}; ++ ++&i2c3 { ++ status = "disabled"; ++}; ++ ++&dspi { ++ status = "okay"; ++ dflash0: n25q512a { ++ #address-cells = <1>; ++ #size-cells = <1>; ++ compatible = "st,m25p80"; ++ spi-max-frequency = <3000000>; ++ reg = <0>; ++ }; ++}; ++ ++&qspi { ++ status = "disabled"; ++}; ++ ++&sata0 { ++ status = "okay"; ++}; ++ ++&sata1 { ++ status = "okay"; ++}; ++ ++&usb0 { ++ status = "okay"; ++}; ++ ++&usb1 { ++ status = "okay"; ++}; ++ ++&emdio1 { ++ /* CS4340 PHYs */ ++ mdio1_phy1: emdio1_phy@1 { ++ reg = <0x10>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio1_phy2: emdio1_phy@2 { ++ reg = <0x11>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio1_phy3: emdio1_phy@3 { ++ reg = <0x12>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio1_phy4: emdio1_phy@4 { ++ reg = <0x13>; ++ phy-connection-type = "xfi"; ++ }; ++}; ++ ++&emdio2 { ++ /* AQR405 PHYs */ ++ mdio2_phy1: emdio2_phy@1 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ interrupts = <0 1 0x4>; /* Level high type */ ++ reg = <0x0>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio2_phy2: emdio2_phy@2 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ interrupts = <0 2 0x4>; /* Level high type */ ++ reg = <0x1>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio2_phy3: emdio2_phy@3 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ interrupts = <0 4 0x4>; /* Level high type */ ++ reg = <0x2>; ++ phy-connection-type = "xfi"; ++ }; ++ mdio2_phy4: emdio2_phy@4 { ++ compatible = "ethernet-phy-ieee802.3-c45"; ++ interrupts = <0 5 0x4>; /* Level high type */ ++ reg = <0x3>; ++ phy-connection-type = "xfi"; ++ }; ++}; ++ ++/* Update DPMAC connections to external PHYs, under the assumption of ++ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. ++ */ ++&dpmac1 { ++ phy-handle = <&mdio1_phy1>; ++}; ++&dpmac2 { ++ phy-handle = <&mdio1_phy2>; ++}; ++&dpmac3 { ++ phy-handle = <&mdio1_phy3>; ++}; ++&dpmac4 { ++ phy-handle = <&mdio1_phy4>; ++}; ++&dpmac5 { ++ phy-handle = <&mdio2_phy1>; ++}; ++&dpmac6 { ++ phy-handle = <&mdio2_phy2>; ++}; ++&dpmac7 { ++ phy-handle = <&mdio2_phy3>; ++}; ++&dpmac8 { ++ phy-handle = <&mdio2_phy4>; ++}; +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +new file mode 100644 +index 0000000..bd69942 +--- /dev/null ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +@@ -0,0 +1,854 @@ ++/* ++ * Device Tree Include file for Freescale Layerscape-2088A family SoC. ++ * ++ * Copyright (C) 2016, Freescale Semiconductor ++ * ++ * Abhimanyu Saini <abhimanyu.saini@nxp.com> ++ * ++ * This file is dual-licensed: you can use it either under the terms ++ * of the GPLv2 or the X11 license, at your option. Note that this dual ++ * licensing only applies to this file, and not this project as a ++ * whole. ++ * ++ * a) This library is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of the ++ * License, or (at your option) any later version. ++ * ++ * This library is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * Or, alternatively, ++ * ++ * b) Permission is hereby granted, free of charge, to any person ++ * obtaining a copy of this software and associated documentation ++ * files (the "Software"), to deal in the Software without ++ * restriction, including without limitation the rights to use, ++ * copy, modify, merge, publish, distribute, sublicense, and/or ++ * sell copies of the Software, and to permit persons to whom the ++ * Software is furnished to do so, subject to the following ++ * conditions: ++ * ++ * The above copyright notice and this permission notice shall be ++ * included in all copies or substantial portions of the Software. ++ * ++ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, ++ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES ++ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND ++ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT ++ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, ++ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING ++ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR ++ * OTHER DEALINGS IN THE SOFTWARE. ++ */ ++ ++#include <dt-bindings/thermal/thermal.h> ++ ++/memreserve/ 0x80000000 0x00010000; ++ ++/ { ++ compatible = "fsl,ls2088a"; ++ interrupt-parent = <&gic>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ++ cpus { ++ #address-cells = <2>; ++ #size-cells = <0>; ++ ++ cpu0: cpu@0 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x0>; ++ clocks = <&clockgen 1 0>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu1: cpu@1 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x1>; ++ clocks = <&clockgen 1 0>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu2: cpu@100 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x100>; ++ clocks = <&clockgen 1 1>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu3: cpu@101 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x101>; ++ clocks = <&clockgen 1 1>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu4: cpu@200 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x200>; ++ clocks = <&clockgen 1 2>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu5: cpu@201 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x201>; ++ clocks = <&clockgen 1 2>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu6: cpu@300 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x300>; ++ clocks = <&clockgen 1 3>; ++ #cooling-cells = <2>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ ++ cpu7: cpu@301 { ++ device_type = "cpu"; ++ compatible = "arm,cortex-a72"; ++ reg = <0x0 0x301>; ++ clocks = <&clockgen 1 3>; ++ cpu-idle-states = <&CPU_PW20>; ++ }; ++ }; ++ ++ pmu { ++ compatible = "arm,armv8-pmuv3"; ++ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ ++ }; ++ ++ idle-states { ++ entry-method = "arm,psci"; ++ ++ CPU_PW20: cpu-pw20 { ++ compatible = "arm,idle-state"; ++ idle-state-name = "PW20"; ++ arm,psci-suspend-param = <0x00010000>; ++ entry-latency-us = <2000>; ++ exit-latency-us = <2000>; ++ min-residency-us = <6000>; ++ }; ++ }; ++ ++ gic: interrupt-controller@6000000 { ++ compatible = "arm,gic-v3"; ++ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ ++ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ ++ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ ++ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ ++ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ ++ #interrupt-cells = <3>; ++ #address-cells = <2>; ++ #size-cells = <2>; ++ ranges; ++ interrupt-controller; ++ interrupts = <1 9 0x4>; ++ ++ its: gic-its@6020000 { ++ compatible = "arm,gic-v3-its"; ++ msi-controller; ++ reg = <0x0 0x6020000 0 0x20000>; ++ }; ++ }; ++ ++ sysclk: sysclk { ++ compatible = "fixed-clock"; ++ #clock-cells = <0>; ++ clock-frequency = <100000000>; ++ clock-output-names = "sysclk"; ++ }; ++ ++ clockgen: clocking@1300000 { ++ compatible = "fsl,ls2088a-clockgen"; ++ reg = <0 0x1300000 0 0xa0000>; ++ #clock-cells = <2>; ++ clocks = <&sysclk>; ++ }; ++ ++ tmu: tmu@1f80000 { ++ compatible = "fsl,qoriq-tmu", "fsl,ls2080a-tmu", "fsl,ls2088a-tmu"; ++ reg = <0x0 0x1f80000 0x0 0x10000>; ++ interrupts = <0 23 0x4>; ++ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; ++ fsl,tmu-calibration = <0x00000000 0x00000026 ++ 0x00000001 0x0000002d ++ 0x00000002 0x00000032 ++ 0x00000003 0x00000039 ++ 0x00000004 0x0000003f ++ 0x00000005 0x00000046 ++ 0x00000006 0x0000004d ++ 0x00000007 0x00000054 ++ 0x00000008 0x0000005a ++ 0x00000009 0x00000061 ++ 0x0000000a 0x0000006a ++ 0x0000000b 0x00000071 ++ ++ 0x00010000 0x00000025 ++ 0x00010001 0x0000002c ++ 0x00010002 0x00000035 ++ 0x00010003 0x0000003d ++ 0x00010004 0x00000045 ++ 0x00010005 0x0000004e ++ 0x00010006 0x00000057 ++ 0x00010007 0x00000061 ++ 0x00010008 0x0000006b ++ 0x00010009 0x00000076 ++ ++ 0x00020000 0x00000029 ++ 0x00020001 0x00000033 ++ 0x00020002 0x0000003d ++ 0x00020003 0x00000049 ++ 0x00020004 0x00000056 ++ 0x00020005 0x00000061 ++ 0x00020006 0x0000006d ++ ++ 0x00030000 0x00000021 ++ 0x00030001 0x0000002a ++ 0x00030002 0x0000003c ++ 0x00030003 0x0000004e>; ++ little-endian; ++ #thermal-sensor-cells = <1>; ++ }; ++ ++ thermal-zones { ++ cpu_thermal: cpu-thermal { ++ polling-delay-passive = <1000>; ++ polling-delay = <5000>; ++ ++ thermal-sensors = <&tmu 4>; ++ ++ trips { ++ cpu_alert: cpu-alert { ++ temperature = <75000>; ++ hysteresis = <2000>; ++ type = "passive"; ++ }; ++ cpu_crit: cpu-crit { ++ temperature = <85000>; ++ hysteresis = <2000>; ++ type = "critical"; ++ }; ++ }; ++ ++ cooling-maps { ++ map0 { ++ trip = <&cpu_alert>; ++ cooling-device = ++ <&cpu0 THERMAL_NO_LIMIT ++ THERMAL_NO_LIMIT>; ++ }; ++ map1 { ++ trip = <&cpu_alert>; ++ cooling-device = ++ <&cpu2 THERMAL_NO_LIMIT ++ THERMAL_NO_LIMIT>; ++ }; ++ map2 { ++ trip = <&cpu_alert>; ++ cooling-device = ++ <&cpu4 THERMAL_NO_LIMIT ++ THERMAL_NO_LIMIT>; ++ }; ++ map3 { ++ trip = <&cpu_alert>; ++ cooling-device = ++ <&cpu6 THERMAL_NO_LIMIT ++ THERMAL_NO_LIMIT>; ++ }; ++ }; ++ }; ++ }; ++ ++ serial0: serial@21c0500 { ++ device_type = "serial"; ++ compatible = "fsl,ns16550", "ns16550a"; ++ reg = <0x0 0x21c0500 0x0 0x100>; ++ clocks = <&clockgen 4 3>; ++ interrupts = <0 32 0x4>; /* Level high type */ ++ }; ++ ++ serial1: serial@21c0600 { ++ device_type = "serial"; ++ compatible = "fsl,ns16550", "ns16550a"; ++ reg = <0x0 0x21c0600 0x0 0x100>; ++ clocks = <&clockgen 4 3>; ++ interrupts = <0 32 0x4>; /* Level high type */ ++ }; ++ cluster1_core0_watchdog: wdt@c000000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc000000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster1_core1_watchdog: wdt@c010000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc010000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster2_core0_watchdog: wdt@c100000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc100000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster2_core1_watchdog: wdt@c110000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc110000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster3_core0_watchdog: wdt@c200000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc200000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster3_core1_watchdog: wdt@c210000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc210000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster4_core0_watchdog: wdt@c300000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc300000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ cluster4_core1_watchdog: wdt@c310000 { ++ compatible = "arm,sp805-wdt", "arm,primecell"; ++ reg = <0x0 0xc310000 0x0 0x1000>; ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "apb_pclk", "wdog_clk"; ++ }; ++ ++ gpio0: gpio@2300000 { ++ compatible = "fsl,qoriq-gpio"; ++ reg = <0x0 0x2300000 0x0 0x10000>; ++ interrupts = <0 36 0x4>; /* Level high type */ ++ gpio-controller; ++ little-endian; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio1: gpio@2310000 { ++ compatible = "fsl,qoriq-gpio"; ++ reg = <0x0 0x2310000 0x0 0x10000>; ++ interrupts = <0 36 0x4>; /* Level high type */ ++ gpio-controller; ++ little-endian; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio2: gpio@2320000 { ++ compatible = "fsl,qoriq-gpio"; ++ reg = <0x0 0x2320000 0x0 0x10000>; ++ interrupts = <0 37 0x4>; /* Level high type */ ++ gpio-controller; ++ little-endian; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ gpio3: gpio@2330000 { ++ compatible = "fsl,qoriq-gpio"; ++ reg = <0x0 0x2330000 0x0 0x10000>; ++ interrupts = <0 37 0x4>; /* Level high type */ ++ gpio-controller; ++ little-endian; ++ #gpio-cells = <2>; ++ interrupt-controller; ++ #interrupt-cells = <2>; ++ }; ++ ++ /* TODO: WRIOP (CCSR?) */ ++ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */ ++ compatible = "fsl,fman-memac-mdio"; ++ reg = <0x0 0x8B96000 0x0 0x1000>; ++ device_type = "mdio"; /* TODO: is this necessary? */ ++ little-endian; /* force the driver in LE mode */ ++ ++ /* Not necessary on the QDS, but needed on the RDB */ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */ ++ compatible = "fsl,fman-memac-mdio"; ++ reg = <0x0 0x8B97000 0x0 0x1000>; ++ device_type = "mdio"; /* TODO: is this necessary? */ ++ little-endian; /* force the driver in LE mode */ ++ ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ ifc: ifc@2240000 { ++ compatible = "fsl,ifc", "simple-bus"; ++ reg = <0x0 0x2240000 0x0 0x20000>; ++ interrupts = <0 21 0x4>; /* Level high type */ ++ little-endian; ++ #address-cells = <2>; ++ #size-cells = <1>; ++ ++ ranges = <0 0 0x5 0x80000000 0x08000000 ++ 2 0 0x5 0x30000000 0x00010000 ++ 3 0 0x5 0x20000000 0x00010000>; ++ }; ++ ++ esdhc: esdhc@2140000 { ++ compatible = "fsl,ls2088a-esdhc", "fsl,ls2080a-esdhc", ++ "fsl,esdhc"; ++ reg = <0x0 0x2140000 0x0 0x10000>; ++ interrupts = <0 28 0x4>; /* Level high type */ ++ clock-frequency = <0>; ++ voltage-ranges = <1800 1800 3300 3300>; ++ sdhci,auto-cmd12; ++ little-endian; ++ bus-width = <4>; ++ }; ++ ++ ftm0: ftm0@2800000 { ++ compatible = "fsl,ftm-alarm"; ++ reg = <0x0 0x2800000 0x0 0x10000>; ++ interrupts = <0 44 4>; ++ }; ++ ++ reset: reset@1E60000 { ++ compatible = "fsl,ls-reset"; ++ reg = <0x0 0x1E60000 0x0 0x10000>; ++ }; ++ ++ dspi: dspi@2100000 { ++ compatible = "fsl,ls2088a-dspi", "fsl,ls2085a-dspi", ++ "fsl,ls2080a-dspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2100000 0x0 0x10000>; ++ interrupts = <0 26 0x4>; /* Level high type */ ++ clocks = <&clockgen 4 3>; ++ clock-names = "dspi"; ++ spi-num-chipselects = <5>; ++ bus-num = <0>; ++ }; ++ ++ i2c0: i2c@2000000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2000000 0x0 0x10000>; ++ interrupts = <0 34 0x4>; /* Level high type */ ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ i2c1: i2c@2010000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2010000 0x0 0x10000>; ++ interrupts = <0 34 0x4>; /* Level high type */ ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ i2c2: i2c@2020000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2020000 0x0 0x10000>; ++ interrupts = <0 35 0x4>; /* Level high type */ ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ i2c3: i2c@2030000 { ++ compatible = "fsl,vf610-i2c"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x2030000 0x0 0x10000>; ++ interrupts = <0 35 0x4>; /* Level high type */ ++ clock-names = "i2c"; ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ qspi: quadspi@20c0000 { ++ compatible = "fsl,ls2088a-qspi", "fsl,ls2080a-qspi"; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ reg = <0x0 0x20c0000 0x0 0x10000>, ++ <0x0 0x20000000 0x0 0x10000000>; ++ reg-names = "QuadSPI", "QuadSPI-memory"; ++ interrupts = <0 25 0x4>; /* Level high type */ ++ clocks = <&clockgen 4 3>, <&clockgen 4 3>; ++ clock-names = "qspi_en", "qspi"; ++ }; ++ ++ pcie1: pcie@3400000 { ++ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", ++ "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ ++ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <0 108 0x4>; /* Level high type */ ++ interrupt-names = "aer"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ dma-coherent; ++ fsl,lut_diff; ++ num-lanes = <4>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ msi-parent = <&its>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, ++ <0000 0 0 2 &gic 0 0 0 110 4>, ++ <0000 0 0 3 &gic 0 0 0 111 4>, ++ <0000 0 0 4 &gic 0 0 0 112 4>; ++ }; ++ ++ pcie2: pcie@3500000 { ++ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", ++ "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ ++ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <0 113 0x4>; /* Level high type */ ++ interrupt-names = "aer"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ dma-coherent; ++ fsl,lut_diff; ++ num-lanes = <4>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ msi-parent = <&its>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, ++ <0000 0 0 2 &gic 0 0 0 115 4>, ++ <0000 0 0 3 &gic 0 0 0 116 4>, ++ <0000 0 0 4 &gic 0 0 0 117 4>; ++ }; ++ ++ pcie3: pcie@3600000 { ++ compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", ++ "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ ++ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <0 118 0x4>; /* Level high type */ ++ interrupt-names = "aer"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ dma-coherent; ++ fsl,lut_diff; ++ num-lanes = <8>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ msi-parent = <&its>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, ++ <0000 0 0 2 &gic 0 0 0 120 4>, ++ <0000 0 0 3 &gic 0 0 0 121 4>, ++ <0000 0 0 4 &gic 0 0 0 122 4>; ++ }; ++ ++ pcie4: pcie@3700000 { ++ compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", ++ "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ ++ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ ++ reg-names = "regs", "config"; ++ interrupts = <0 123 0x4>; /* Level high type */ ++ interrupt-names = "aer"; ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ dma-coherent; ++ fsl,lut_diff; ++ num-lanes = <4>; ++ bus-range = <0x0 0xff>; ++ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 /* downstream I/O */ ++ 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ ++ msi-parent = <&its>; ++ #interrupt-cells = <1>; ++ interrupt-map-mask = <0 0 0 7>; ++ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, ++ <0000 0 0 2 &gic 0 0 0 125 4>, ++ <0000 0 0 3 &gic 0 0 0 126 4>, ++ <0000 0 0 4 &gic 0 0 0 127 4>; ++ }; ++ ++ sata0: sata@3200000 { ++ status = "disabled"; ++ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci"; ++ reg = <0x0 0x3200000 0x0 0x10000>; ++ interrupts = <0 133 0x4>; /* Level high type */ ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ sata1: sata@3210000 { ++ status = "disabled"; ++ compatible = "fsl,ls2088a-ahci", "fsl,ls2080a-ahci"; ++ reg = <0x0 0x3210000 0x0 0x10000>; ++ interrupts = <0 136 0x4>; /* Level high type */ ++ clocks = <&clockgen 4 3>; ++ }; ++ ++ usb0: usb3@3100000 { ++ status = "disabled"; ++ compatible = "snps,dwc3"; ++ reg = <0x0 0x3100000 0x0 0x10000>; ++ interrupts = <0 80 0x4>; /* Level high type */ ++ dr_mode = "host"; ++ configure-gfladj; ++ snps,dis_rxdet_inp3_quirk; ++ }; ++ ++ usb1: usb3@3110000 { ++ status = "disabled"; ++ compatible = "snps,dwc3"; ++ reg = <0x0 0x3110000 0x0 0x10000>; ++ interrupts = <0 81 0x4>; /* Level high type */ ++ dr_mode = "host"; ++ configure-gfladj; ++ snps,dis_rxdet_inp3_quirk; ++ }; ++ ++ smmu: iommu@5000000 { ++ compatible = "arm,mmu-500"; ++ reg = <0 0x5000000 0 0x800000>; ++ #global-interrupts = <12>; ++ interrupts = <0 13 4>, /* global secure fault */ ++ <0 14 4>, /* combined secure interrupt */ ++ <0 15 4>, /* global non-secure fault */ ++ <0 16 4>, /* combined non-secure interrupt */ ++ /* performance counter interrupts 0-7 */ ++ <0 211 4>, ++ <0 212 4>, ++ <0 213 4>, ++ <0 214 4>, ++ <0 215 4>, ++ <0 216 4>, ++ <0 217 4>, ++ <0 218 4>, ++ /* per context interrupt, 64 interrupts */ ++ <0 146 4>, ++ <0 147 4>, ++ <0 148 4>, ++ <0 149 4>, ++ <0 150 4>, ++ <0 151 4>, ++ <0 152 4>, ++ <0 153 4>, ++ <0 154 4>, ++ <0 155 4>, ++ <0 156 4>, ++ <0 157 4>, ++ <0 158 4>, ++ <0 159 4>, ++ <0 160 4>, ++ <0 161 4>, ++ <0 162 4>, ++ <0 163 4>, ++ <0 164 4>, ++ <0 165 4>, ++ <0 166 4>, ++ <0 167 4>, ++ <0 168 4>, ++ <0 169 4>, ++ <0 170 4>, ++ <0 171 4>, ++ <0 172 4>, ++ <0 173 4>, ++ <0 174 4>, ++ <0 175 4>, ++ <0 176 4>, ++ <0 177 4>, ++ <0 178 4>, ++ <0 179 4>, ++ <0 180 4>, ++ <0 181 4>, ++ <0 182 4>, ++ <0 183 4>, ++ <0 184 4>, ++ <0 185 4>, ++ <0 186 4>, ++ <0 187 4>, ++ <0 188 4>, ++ <0 189 4>, ++ <0 190 4>, ++ <0 191 4>, ++ <0 192 4>, ++ <0 193 4>, ++ <0 194 4>, ++ <0 195 4>, ++ <0 196 4>, ++ <0 197 4>, ++ <0 198 4>, ++ <0 199 4>, ++ <0 200 4>, ++ <0 201 4>, ++ <0 202 4>, ++ <0 203 4>, ++ <0 204 4>, ++ <0 205 4>, ++ <0 206 4>, ++ <0 207 4>, ++ <0 208 4>, ++ <0 209 4>; ++ mmu-masters = <&fsl_mc 0x300 0>; ++ }; ++ ++ timer { ++ compatible = "arm,armv8-timer"; ++ interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */ ++ <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */ ++ <1 11 0x1>, /* Virtual PPI, edge triggered */ ++ <1 10 0x1>; /* Hypervisor PPI, edge triggered */ ++ arm,reread-timer; ++ fsl,erratum-a008585; ++ }; ++ ++ fsl_mc: fsl-mc@80c000000 { ++ compatible = "fsl,qoriq-mc"; ++ #stream-id-cells = <2>; ++ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ ++ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ ++ msi-parent = <&its>; ++ #address-cells = <3>; ++ #size-cells = <1>; ++ ++ /* ++ * Region type 0x0 - MC portals ++ * Region type 0x1 - QBMAN portals ++ */ ++ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 ++ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; ++ ++ /* ++ * Define the maximum number of MACs present on the SoC. ++ * They won't necessarily be all probed, since the ++ * Data Path Layout file and the MC firmware can put fewer ++ * actual DPMAC objects on the MC bus. ++ */ ++ dpmacs { ++ #address-cells = <1>; ++ #size-cells = <0>; ++ ++ dpmac1: dpmac@1 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <1>; ++ }; ++ dpmac2: dpmac@2 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <2>; ++ }; ++ dpmac3: dpmac@3 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <3>; ++ }; ++ dpmac4: dpmac@4 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <4>; ++ }; ++ dpmac5: dpmac@5 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <5>; ++ }; ++ dpmac6: dpmac@6 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <6>; ++ }; ++ dpmac7: dpmac@7 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <7>; ++ }; ++ dpmac8: dpmac@8 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <8>; ++ }; ++ dpmac9: dpmac@9 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <9>; ++ }; ++ dpmac10: dpmac@10 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xa>; ++ }; ++ dpmac11: dpmac@11 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xb>; ++ }; ++ dpmac12: dpmac@12 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xc>; ++ }; ++ dpmac13: dpmac@13 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xd>; ++ }; ++ dpmac14: dpmac@14 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xe>; ++ }; ++ dpmac15: dpmac@15 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0xf>; ++ }; ++ dpmac16: dpmac@16 { ++ compatible = "fsl,qoriq-mc-dpmac"; ++ reg = <0x10>; ++ }; ++ }; ++ }; ++ ++ ccn@4000000 { ++ compatible = "arm,ccn-504"; ++ reg = <0x0 0x04000000 0x0 0x01000000>; ++ interrupts = <0 12 4>; ++ }; ++ ++ memory@80000000 { ++ device_type = "memory"; ++ reg = <0x00000000 0x80000000 0 0x80000000>; ++ /* DRAM space 1 - 2 GB DRAM */ ++ }; ++}; +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch b/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch new file mode 100644 index 0000000000..7fb9b17d43 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3228-ls2088a-add-ls2088a-its.patch @@ -0,0 +1,138 @@ +From e0f9ccd657893d1a10dfbae291900b3045c471fc Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <qiang.zhao@nxp.com> +Date: Mon, 7 Nov 2016 10:38:51 +0800 +Subject: [PATCH 228/238] ls2088a: add ls2088a its + +Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> +--- + kernel2088a-qds.its | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ + kernel2088a-rdb.its | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++ + 2 files changed, 110 insertions(+) + create mode 100644 kernel2088a-qds.its + create mode 100644 kernel2088a-rdb.its + +diff --git a/kernel2088a-qds.its b/kernel2088a-qds.its +new file mode 100644 +index 0000000..4732954 +--- /dev/null ++++ b/kernel2088a-qds.its +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2016, Freescale Semiconductor ++ * ++ * Abhimanyu Saini <abhimanyu.saini@nxp.com> ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ description = "QDS Image file for the LS2080A Linux Kernel"; ++ #address-cells = <1>; ++ ++ images { ++ kernel@1 { ++ description = "ARM64 Linux kernel"; ++ data = /incbin/("./arch/arm64/boot/Image.gz"); ++ type = "kernel"; ++ arch = "arm64"; ++ os = "linux"; ++ compression = "gzip"; ++ load = <0x80080000>; ++ entry = <0x80080000>; ++ }; ++ fdt@1 { ++ description = "Flattened Device Tree blob"; ++ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dtb"); ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ load = <0x90000000>; ++ }; ++ ramdisk@1 { ++ description = "LS2 Ramdisk"; ++ data = /incbin/("./fsl-image-core-ls2088aqds.ext2.gz"); ++ type = "ramdisk"; ++ arch = "arm64"; ++ os = "linux"; ++ compression = "none"; ++ }; ++ }; ++ ++ configurations { ++ default = "config@1"; ++ config@1 { ++ description = "Boot Linux kernel"; ++ kernel = "kernel@1"; ++ fdt = "fdt@1"; ++ ramdisk = "ramdisk@1"; ++ }; ++ }; ++}; +diff --git a/kernel2088a-rdb.its b/kernel2088a-rdb.its +new file mode 100644 +index 0000000..151241f +--- /dev/null ++++ b/kernel2088a-rdb.its +@@ -0,0 +1,55 @@ ++/* ++ * Copyright (C) 2016, Freescale Semiconductor ++ * ++ * Abhimanyu Saini <abhimanyu.saini@nxp.com> ++ * ++ * This file is licensed under the terms of the GNU General Public ++ * License version 2. This program is licensed "as is" without any ++ * warranty of any kind, whether express or implied. ++ */ ++ ++/dts-v1/; ++ ++/ { ++ description = "RDB Image file for the LS2080A Linux Kernel"; ++ #address-cells = <1>; ++ ++ images { ++ kernel@1 { ++ description = "ARM64 Linux kernel"; ++ data = /incbin/("./arch/arm64/boot/Image.gz"); ++ type = "kernel"; ++ arch = "arm64"; ++ os = "linux"; ++ compression = "gzip"; ++ load = <0x80080000>; ++ entry = <0x80080000>; ++ }; ++ fdt@1 { ++ description = "Flattened Device Tree blob"; ++ data = /incbin/("./arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dtb"); ++ type = "flat_dt"; ++ arch = "arm64"; ++ compression = "none"; ++ load = <0x90000000>; ++ }; ++ ramdisk@1 { ++ description = "LS2 Ramdisk"; ++ data = /incbin/("./fsl-image-core-ls2088ardb.ext2.gz"); ++ type = "ramdisk"; ++ arch = "arm64"; ++ os = "linux"; ++ compression = "none"; ++ }; ++ }; ++ ++ configurations { ++ default = "config@1"; ++ config@1 { ++ description = "Boot Linux kernel"; ++ kernel = "kernel@1"; ++ fdt = "fdt@1"; ++ ramdisk = "ramdisk@1"; ++ }; ++ }; ++}; +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch b/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch new file mode 100644 index 0000000000..f3079a51d6 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/4234-fsl-ifc-fix-compilation-error-when-COMPAT-not-enable.patch @@ -0,0 +1,34 @@ +From 6183d512e7539033ccfd177d5f5819302d1fda99 Mon Sep 17 00:00:00 2001 +From: Lijun Pan <Lijun.Pan@freescale.com> +Date: Wed, 23 Sep 2015 17:06:01 -0500 +Subject: [PATCH 234/238] fsl-ifc: fix compilation error when COMPAT not + enabled + +When CONFIG_COMPAT is not enabled for cases when 64K pages +are enabled, there are a series of include dependencies that +result in some definitions in sched.h that get missed (e.g. + TASK_NORMAL). Explictly include sched.h to resolve this. +(This seems to be what other drivers do as well) + +Signed-off-by: Lijun Pan <Lijun.Pan@freescale.com> +[Stuart: updated subject and commit message] +Signed-off-by: Stuart Yoder <stuart.yoder@freescale.com> +--- + drivers/memory/fsl_ifc.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/memory/fsl_ifc.c b/drivers/memory/fsl_ifc.c +index 03584dc..32c7752 100644 +--- a/drivers/memory/fsl_ifc.c ++++ b/drivers/memory/fsl_ifc.c +@@ -35,6 +35,7 @@ + #include <linux/irqdomain.h> + #include <linux/of_address.h> + #include <linux/of_irq.h> ++#include <linux/sched.h> + + struct fsl_ifc_ctrl *fsl_ifc_ctrl_dev; + EXPORT_SYMBOL(fsl_ifc_ctrl_dev); +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch b/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch new file mode 100644 index 0000000000..5c1fcd010b --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8229-drivers-clk-qoriq-Add-ls2088a-key-to-chipinfo-table.patch @@ -0,0 +1,35 @@ +From cb8a47d43caa2b07a62d81ee0b65c0d16560c276 Mon Sep 17 00:00:00 2001 +From: Abhimanyu Saini <abhimanyu.saini@nxp.com> +Date: Fri, 3 Jun 2016 13:15:28 +0530 +Subject: [PATCH 229/238] drivers: clk: qoriq: Add ls2088a key to chipinfo + table + +--- + drivers/clk/clk-qoriq.c | 11 +++++++++++ + 1 file changed, 11 insertions(+) + +diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c +index 164ac41..6185d6a 100644 +--- a/drivers/clk/clk-qoriq.c ++++ b/drivers/clk/clk-qoriq.c +@@ -559,6 +559,17 @@ static const struct clockgen_chipinfo chipinfo[] = { + .flags = CG_VER3 | CG_LITTLE_ENDIAN, + }, + { ++ .compat = "fsl,ls2088a-clockgen", ++ .cmux_groups = { ++ &clockgen2_cmux_cga12, &clockgen2_cmux_cgb ++ }, ++ .cmux_to_group = { ++ 0, 0, 1, 1, -1 ++ }, ++ .pll_mask = 0x37, ++ .flags = CG_VER3 | CG_LITTLE_ENDIAN, ++ }, ++ { + .compat = "fsl,p2041-clockgen", + .guts_compat = "fsl,qoriq-device-config-1.0", + .init_periph = p2041_init_periph, +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch b/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch new file mode 100644 index 0000000000..0feb800367 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8230-layerscape-pci-fix-linkup-issue.patch @@ -0,0 +1,42 @@ +From 1b23a4e0f03063f823ea38065c1106f62a56b408 Mon Sep 17 00:00:00 2001 +From: Mingkai Hu <mingkai.hu@nxp.com> +Date: Mon, 7 Nov 2016 15:03:51 +0800 +Subject: [PATCH 230/238] layerscape/pci: fix linkup issue + +commit e6612d785198abbb39142e2acb63f9bff26ab718 +[context adjustment] + +Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> +Integrated-by: Zhao Qiang <qiang.zhao@nxp.com> +--- + drivers/pci/host/pci-layerscape.c | 13 +++++++++---- + 1 file changed, 9 insertions(+), 4 deletions(-) + +diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c +index 00feabf..f85ebcf 100644 +--- a/drivers/pci/host/pci-layerscape.c ++++ b/drivers/pci/host/pci-layerscape.c +@@ -158,11 +158,16 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) + static int ls_pcie_link_up(struct pcie_port *pp) + { + struct ls_pcie *pcie = to_ls_pcie(pp); +- u32 state; ++ u32 state, offset; ++ ++ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) ++ offset = 0x407fc; ++ else ++ offset = PCIE_LUT_DBG; + +- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> +- pcie->drvdata->ltssm_shift) & +- LTSSM_STATE_MASK; ++ state = (ioread32(pcie->lut + offset) >> ++ pcie->drvdata->ltssm_shift) & ++ LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch b/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch new file mode 100644 index 0000000000..e98e5022ab --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8231-driver-clk-qoriq-Add-ls2088a-clk-support.patch @@ -0,0 +1,25 @@ +From c62b4977614e133acc95c61237bcc8fe30581d13 Mon Sep 17 00:00:00 2001 +From: "ying.zhang" <ying.zhang22455@nxp.com> +Date: Thu, 22 Dec 2016 23:29:39 +0800 +Subject: [PATCH 231/238] driver: clk: qoriq: Add ls2088a clk support + +Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com>wq +--- + drivers/clk/clk-qoriq.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/clk/clk-qoriq.c b/drivers/clk/clk-qoriq.c +index 6185d6a..efaa9c1 100644 +--- a/drivers/clk/clk-qoriq.c ++++ b/drivers/clk/clk-qoriq.c +@@ -1339,6 +1339,7 @@ CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); ++CLK_OF_DECLARE(qoriq_clockgen_ls2088a, "fsl,ls2088a-clockgen", clockgen_init); + + /* Legacy nodes */ + CLK_OF_DECLARE(qoriq_sysclk_1, "fsl,qoriq-sysclk-1.0", sysclk_init); +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch b/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch new file mode 100644 index 0000000000..0967aeb698 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8233-i2c-pca954x-Add-option-to-skip-disabling-PCA954x-Mux.patch @@ -0,0 +1,110 @@ +From a4be9046c3a3fc39a06089553df8cc19a2abd814 Mon Sep 17 00:00:00 2001 +From: Priyanka Jain <Priyanka.Jain@freescale.com> +Date: Tue, 3 Nov 2015 11:25:24 +0530 +Subject: [PATCH 233/238] i2c: pca954x: Add option to skip disabling PCA954x + Mux device + +On some Layerscape boards like LS2085ARDB/LS2080ARDB, +input pull-up resistors on PCA954x Mux device are +missing on board. So, if mux are disabled after powered-on, +input lines will float leading to incorrect functionality. + +Hence, PCA954x Mux device should never be turned-off after +power-on. + +Add option to skip disabling PCA954x Mux device +if device tree contians "i2c-mux-never-disable" property +for pca954x device node. + +Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> +--- + drivers/i2c/muxes/i2c-mux-pca954x.c | 38 +++++++++++++++++++++++++++++++++++ + 1 file changed, 38 insertions(+) + +diff --git a/drivers/i2c/muxes/i2c-mux-pca954x.c b/drivers/i2c/muxes/i2c-mux-pca954x.c +index acfcef3..386f86f 100644 +--- a/drivers/i2c/muxes/i2c-mux-pca954x.c ++++ b/drivers/i2c/muxes/i2c-mux-pca954x.c +@@ -63,6 +63,7 @@ struct pca954x { + struct i2c_adapter *virt_adaps[PCA954X_MAX_NCHANS]; + + u8 last_chan; /* last register value */ ++ u8 disable_mux; /* do not disable mux if val not 0 */ + }; + + struct chip_desc { +@@ -174,6 +175,13 @@ static int pca954x_deselect_mux(struct i2c_adapter *adap, + { + struct pca954x *data = i2c_get_clientdata(client); + ++#ifdef CONFIG_ARCH_LAYERSCAPE ++ if (data->disable_mux != 0) ++ data->last_chan = chips[data->type].nchans; ++ else ++ data->last_chan = 0; ++ return pca954x_reg_write(adap, client, data->disable_mux); ++#endif + /* Deselect active channel */ + data->last_chan = 0; + return pca954x_reg_write(adap, client, data->last_chan); +@@ -201,6 +209,23 @@ static int pca954x_probe(struct i2c_client *client, + if (!data) + return -ENOMEM; + ++#ifdef CONFIG_ARCH_LAYERSCAPE ++ /* The point here is that you must not disable a mux if there ++ * are no pullups on the input or you mess up the I2C. This ++ * needs to be put into the DTS really as the kernel cannot ++ * know this otherwise. ++ */ ++ data->type = id->driver_data; ++ data->disable_mux = of_node && ++ of_property_read_bool(of_node, "i2c-mux-never-disable") && ++ chips[data->type].muxtype == pca954x_ismux ? ++ chips[data->type].enable : 0; ++ /* force the first selection */ ++ if (data->disable_mux != 0) ++ data->last_chan = chips[data->type].nchans; ++ else ++ data->last_chan = 0; ++#endif + i2c_set_clientdata(client, data); + + /* Get the mux out of reset if a reset GPIO is specified. */ +@@ -212,13 +237,19 @@ static int pca954x_probe(struct i2c_client *client, + * that the mux is in fact present. This also + * initializes the mux to disconnected state. + */ ++#ifdef CONFIG_ARCH_LAYERSCAPE ++ if (i2c_smbus_write_byte(client, data->disable_mux) < 0) { ++#else + if (i2c_smbus_write_byte(client, 0) < 0) { ++#endif + dev_warn(&client->dev, "probe failed\n"); + return -ENODEV; + } + ++#ifndef CONFIG_ARCH_LAYERSCAPE + data->type = id->driver_data; + data->last_chan = 0; /* force the first selection */ ++#endif + + idle_disconnect_dt = of_node && + of_property_read_bool(of_node, "i2c-mux-idle-disconnect"); +@@ -289,6 +320,13 @@ static int pca954x_resume(struct device *dev) + struct i2c_client *client = to_i2c_client(dev); + struct pca954x *data = i2c_get_clientdata(client); + ++#ifdef CONFIG_ARCH_LAYERSCAPE ++ if (data->disable_mux != 0) ++ data->last_chan = chips[data->type].nchans; ++ else ++ data->last_chan = 0; ++ return i2c_smbus_write_byte(client, data->disable_mux); ++#endif + data->last_chan = 0; + return i2c_smbus_write_byte(client, 0); + } +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch b/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch new file mode 100644 index 0000000000..be91046ac1 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8235-pci-layerscape-fix-pci-lut-offset-issue.patch @@ -0,0 +1,38 @@ +From 2f3ea65dc8909cbf4116bd74b3dea8d25749508f Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <qiang.zhao@nxp.com> +Date: Wed, 23 Nov 2016 11:29:45 +0800 +Subject: [PATCH 235/238] pci/layerscape: fix pci lut offset issue + +Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> +--- + drivers/pci/host/pci-layerscape.c | 13 ++++--------- + 1 file changed, 4 insertions(+), 9 deletions(-) + +diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c +index f85ebcf..00feabf 100644 +--- a/drivers/pci/host/pci-layerscape.c ++++ b/drivers/pci/host/pci-layerscape.c +@@ -158,16 +158,11 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) + static int ls_pcie_link_up(struct pcie_port *pp) + { + struct ls_pcie *pcie = to_ls_pcie(pp); +- u32 state, offset; +- +- if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) +- offset = 0x407fc; +- else +- offset = PCIE_LUT_DBG; ++ u32 state; + +- state = (ioread32(pcie->lut + offset) >> +- pcie->drvdata->ltssm_shift) & +- LTSSM_STATE_MASK; ++ state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> ++ pcie->drvdata->ltssm_shift) & ++ LTSSM_STATE_MASK; + + if (state < LTSSM_PCIE_L0) + return 0; +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch b/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch new file mode 100644 index 0000000000..f5947f7e06 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8236-clk-add-API-of-clks.patch @@ -0,0 +1,84 @@ +From df2373ca941741f3f66750241a048ad4e2ff2c91 Mon Sep 17 00:00:00 2001 +From: Zhao Qiang <qiang.zhao@nxp.com> +Date: Thu, 24 Nov 2016 11:47:45 +0800 +Subject: [PATCH 236/238] clk: add API of clks + +Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> +--- + drivers/clk/clk.c | 19 +++++++++++++++++++ + include/linux/clk-provider.h | 1 + + include/linux/clk.h | 9 +++++++++ + 3 files changed, 29 insertions(+) + +diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c +index f13c3f4..0f6bcf5 100644 +--- a/drivers/clk/clk.c ++++ b/drivers/clk/clk.c +@@ -359,6 +359,19 @@ static struct clk_core *clk_core_get_parent_by_index(struct clk_core *core, + return core->parents[index]; + } + ++struct clk *clk_get_parent_by_index(struct clk *clk, u8 index) ++{ ++ struct clk_core *parent; ++ ++ if (!clk) ++ return NULL; ++ ++ parent = clk_core_get_parent_by_index(clk->core, index); ++ ++ return !parent ? NULL : parent->hw->clk; ++} ++EXPORT_SYMBOL_GPL(clk_get_parent_by_index); ++ + struct clk_hw * + clk_hw_get_parent_by_index(const struct clk_hw *hw, unsigned int index) + { +@@ -2033,6 +2046,12 @@ static const struct file_operations clk_summary_fops = { + .release = single_release, + }; + ++unsigned int clk_get_num_parents(struct clk *clk) ++{ ++ return !clk ? 0 : clk->core->num_parents; ++} ++EXPORT_SYMBOL_GPL(clk_get_num_parents); ++ + static void clk_dump_one(struct seq_file *s, struct clk_core *c, int level) + { + if (!c) +diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h +index 7cd0171..77dfd61 100644 +--- a/include/linux/clk-provider.h ++++ b/include/linux/clk-provider.h +@@ -650,6 +650,7 @@ unsigned int clk_hw_get_num_parents(const struct clk_hw *hw); + struct clk_hw *clk_hw_get_parent(const struct clk_hw *hw); + struct clk_hw *clk_hw_get_parent_by_index(const struct clk_hw *hw, + unsigned int index); ++struct clk *clk_get_parent_by_index(struct clk *clk, u8 index); + unsigned int __clk_get_enable_count(struct clk *clk); + unsigned long clk_hw_get_rate(const struct clk_hw *hw); + unsigned long __clk_get_flags(struct clk *clk); +diff --git a/include/linux/clk.h b/include/linux/clk.h +index 0df4a51..1df90e3 100644 +--- a/include/linux/clk.h ++++ b/include/linux/clk.h +@@ -392,6 +392,15 @@ int clk_set_parent(struct clk *clk, struct clk *parent); + struct clk *clk_get_parent(struct clk *clk); + + /** ++ * clk_get_num_parents - get number of possible parents ++ * @clk: clock source ++ * ++ * Returns the number of possible parents of this clock, ++ * which can then be enumerated using clk_get_parent_by_index(). ++ */ ++unsigned int clk_get_num_parents(struct clk *clk); ++ ++/** + * clk_get_sys - get a clock based upon the device name + * @dev_id: device name + * @con_id: connection ID +-- +1.7.9.5 + diff --git a/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch b/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch new file mode 100644 index 0000000000..08e1ecba9a --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8237-pcie-ls208x-use-unified-compatible-fsl-ls2080a-pcie-.patch @@ -0,0 +1,103 @@ +From 562f1311b529d81662ed41786b8d240db2e2ff51 Mon Sep 17 00:00:00 2001 +From: Shengzhou Liu <Shengzhou.Liu@nxp.com> +Date: Tue, 6 Dec 2016 15:30:39 +0800 +Subject: [PATCH 237/238] pcie/ls208x: use unified compatible + "fsl,ls2080a-pcie" for ls208x + +To avoid unnecessary reduplication, let's use unified compatible +"fsl,ls2080a-pcie" for ls2080a, ls2085a, ls2088a. + +This patch fixes issue of pcie not working on ls2088a. + +Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> +--- + arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 12 ++++-------- + drivers/pci/host/pci-layerscape.c | 13 ++++++++----- + 2 files changed, 12 insertions(+), 13 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +index bd69942..07c917b 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi +@@ -513,8 +513,7 @@ + }; + + pcie1: pcie@3400000 { +- compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", +- "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ + 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; +@@ -539,8 +538,7 @@ + }; + + pcie2: pcie@3500000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", +- "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ + 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; +@@ -565,8 +563,7 @@ + }; + + pcie3: pcie@3600000 { +- compatible = "fsl,ls2088a-pcie", "fsl,ls2080a-pcie", +- "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ + 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; +@@ -591,8 +588,7 @@ + }; + + pcie4: pcie@3700000 { +- compatible = "fsl,ls2080a-pcie", "fsl,ls2080a-pcie", +- "fsl,ls2085a-pcie", "snps,dw-pcie"; ++ compatible = "fsl,ls2080a-pcie", "snps,dw-pcie"; + reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ + 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; +diff --git a/drivers/pci/host/pci-layerscape.c b/drivers/pci/host/pci-layerscape.c +index 00feabf..3e2100d 100644 +--- a/drivers/pci/host/pci-layerscape.c ++++ b/drivers/pci/host/pci-layerscape.c +@@ -158,9 +158,14 @@ static void ls1021_pcie_host_init(struct pcie_port *pp) + static int ls_pcie_link_up(struct pcie_port *pp) + { + struct ls_pcie *pcie = to_ls_pcie(pp); +- u32 state; ++ u32 state, offset; ++ ++ if (of_get_property(pp->dev->of_node, "fsl,lut_diff", NULL)) ++ offset = 0x407fc; ++ else ++ offset = pcie->drvdata->lut_dbg; + +- state = (ioread32(pcie->lut + pcie->drvdata->lut_dbg) >> ++ state = (ioread32(pcie->lut + offset) >> + pcie->drvdata->ltssm_shift) & + LTSSM_STATE_MASK; + +@@ -261,7 +266,6 @@ static const struct of_device_id ls_pcie_of_match[] = { + { .compatible = "fsl,ls1046a-pcie", .data = &ls1046_drvdata }, + { .compatible = "fsl,ls1088a-pcie", .data = &ls1088_drvdata }, + { .compatible = "fsl,ls2080a-pcie", .data = &ls2080_drvdata }, +- { .compatible = "fsl,ls2085a-pcie", .data = &ls2080_drvdata }, + { }, + }; + MODULE_DEVICE_TABLE(of, ls_pcie_of_match); +@@ -315,8 +319,7 @@ static int __init ls_pcie_probe(struct platform_device *pdev) + if (!ls_pcie_is_bridge(pcie)) + return -ENODEV; + +- if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2085a-pcie") || +- of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") || ++ if (of_device_is_compatible(pdev->dev.of_node, "fsl,ls2080a-pcie") || + of_device_is_compatible(pdev->dev.of_node, "fsl,ls1088a-pcie")) { + int len; + const u32 *prop; +-- +1.7.9.5 + |