diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/820-usb-0010-MLK-22675-usb-dwc3-host-disable-park-mode.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/820-usb-0010-MLK-22675-usb-dwc3-host-disable-park-mode.patch | 88 |
1 files changed, 88 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/820-usb-0010-MLK-22675-usb-dwc3-host-disable-park-mode.patch b/target/linux/layerscape/patches-5.4/820-usb-0010-MLK-22675-usb-dwc3-host-disable-park-mode.patch new file mode 100644 index 0000000000..bca63debf8 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/820-usb-0010-MLK-22675-usb-dwc3-host-disable-park-mode.patch @@ -0,0 +1,88 @@ +From c5324b25fe98c7a4784248b53a75720b226436c2 Mon Sep 17 00:00:00 2001 +From: Li Jun <jun.li@nxp.com> +Date: Tue, 29 Oct 2019 17:40:25 +0800 +Subject: [PATCH] MLK-22675 usb: dwc3: host: disable park mode + +- Advantage of park mode + When only a single Async endpoint is active. + +- Behavior of park mode + 1. The controller prefetches data/TRBs to do 3 * burst_size worth + of packets. + 2. When park mode is disabled there will be some delay between + bursts on the USB. This can be avoided if park mode is enabled + in cases of only one endpoint is active. + 3. But this delay is significant only with systems of large + latencies. + 4. We have noticed that in cases where a device NAKs often, it + tends to bring down the performance for a single endpoint case. + +- Issue on "park mode" + 1. LSP (List Processor) goes in and out of park mode irrespective + of the fact that there are more endpoints active. #LSP consider + that there is only one endpoint active. + 2. This causes master scheduler and transaction handlers to think + that they are in park mode even though they are not. This is + because request to transaction handlers, generated by HSCH is + in park mode when the request is made + 3. This causes a case where the master scheduler calculates wrongly + the number of TRB cache space available. + 4. Because of the wrongly calculated number of TRB spaces, the core + fetches more TRBS than there is space for. + 5. This causes overwriting the TRB cache area into the TRQ cache + area which is next to the TRB cache area. + 6. This causes invalidating an entry in the TRQ + 7. This causes transaction handlers to ignore a request in the TRQ + which it should have processed. + 8. This causes the main scheduler to hang because it is waiting for + status from transaction handler. + 9. This causes host controller to hang. + +- Work Around + Disabling park mode for super speed by setting GUCTL1[17] to be 1. + +The STAR number is 9001415732, which is target to be released around +May,2020. + +Reviewed-by: Peter Chen <peter.chen@nxp.com> +Reviewed-by: Ran Wang <ran.wang_1@nxp.com> +Signed-off-by: Li Jun <jun.li@nxp.com> +--- + drivers/usb/dwc3/core.c | 15 +++++++++++++++ + drivers/usb/dwc3/core.h | 1 + + 2 files changed, 16 insertions(+) + +--- a/drivers/usb/dwc3/core.c ++++ b/drivers/usb/dwc3/core.c +@@ -1030,6 +1030,21 @@ static int dwc3_core_init(struct dwc3 *d + reg |= DWC3_GUCTL_HSTINAUTORETRY; + + dwc3_writel(dwc->regs, DWC3_GUCTL, reg); ++ ++ /* ++ * Disable Park Mode for super speed: ++ * Park mode is used in host mode when only a single async ++ * endpoint is active, but which has a known issue cause ++ * USB3.0 HC may die when read and write at the same time, ++ * considering the advantages of this mode are minimal, ++ * this issue only impacts super speed and exist on all IP ++ * versions, disable it for SS, Synopsys will release a formal ++ * STAR 9001415732, and disable it by default in next IP ++ * release. ++ */ ++ reg = dwc3_readl(dwc->regs, DWC3_GUCTL1); ++ reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS; ++ dwc3_writel(dwc->regs, DWC3_GUCTL1, reg); + } + + /* +--- a/drivers/usb/dwc3/core.h ++++ b/drivers/usb/dwc3/core.h +@@ -253,6 +253,7 @@ + /* Global User Control 1 Register */ + #define DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS BIT(28) + #define DWC3_GUCTL1_DEV_L1_EXIT_BY_HW BIT(24) ++#define DWC3_GUCTL1_PARKMODE_DISABLE_SS BIT(17) + + /* Global Status Register */ + #define DWC3_GSTS_OTG_IP BIT(10) |