diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/812-pcie-0002-PCI-dwc-Use-interrupt-disabling-instead-of-masking.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/812-pcie-0002-PCI-dwc-Use-interrupt-disabling-instead-of-masking.patch | 60 |
1 files changed, 60 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/812-pcie-0002-PCI-dwc-Use-interrupt-disabling-instead-of-masking.patch b/target/linux/layerscape/patches-5.4/812-pcie-0002-PCI-dwc-Use-interrupt-disabling-instead-of-masking.patch new file mode 100644 index 0000000000..e82b83aef1 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/812-pcie-0002-PCI-dwc-Use-interrupt-disabling-instead-of-masking.patch @@ -0,0 +1,60 @@ +From c89d85a39df353290ea7af84a32d5ca692a3c27a Mon Sep 17 00:00:00 2001 +From: Fugang Duan <fugang.duan@nxp.com> +Date: Sat, 2 Nov 2019 15:51:40 +0800 +Subject: [PATCH] PCI: dwc: Use interrupt disabling instead of masking + +commit 830920e065e9("PCI: dwc: Use interrupt masking instead +of disabling") break i.MX platform PCIe suspend/resume when +MSI enabled. + +Revert the commit to keep orinigal method that using interrupt +disabling instead of masking. + +Signed-off-by: Fugang Duan <fugang.duan@nxp.com> +--- + drivers/pci/controller/dwc/pcie-designware-host.c | 19 +++++++------------ + 1 file changed, 7 insertions(+), 12 deletions(-) + +--- a/drivers/pci/controller/dwc/pcie-designware-host.c ++++ b/drivers/pci/controller/dwc/pcie-designware-host.c +@@ -157,8 +157,8 @@ static void dw_pci_bottom_mask(struct ir + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] |= BIT(bit); +- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, +- pp->irq_mask[ctrl]); ++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, ++ ~pp->irq_mask[ctrl]); + + raw_spin_unlock_irqrestore(&pp->lock, flags); + } +@@ -176,8 +176,8 @@ static void dw_pci_bottom_unmask(struct + bit = d->hwirq % MAX_MSI_IRQS_PER_CTRL; + + pp->irq_mask[ctrl] &= ~BIT(bit); +- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + res, 4, +- pp->irq_mask[ctrl]); ++ dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, ++ ~pp->irq_mask[ctrl]); + + raw_spin_unlock_irqrestore(&pp->lock, flags); + } +@@ -657,15 +657,10 @@ void dw_pcie_setup_rc(struct pcie_port * + num_ctrls = pp->num_vectors / MAX_MSI_IRQS_PER_CTRL; + + /* Initialize IRQ Status array */ +- for (ctrl = 0; ctrl < num_ctrls; ctrl++) { +- pp->irq_mask[ctrl] = ~0; +- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_MASK + ++ for (ctrl = 0; ctrl < num_ctrls; ctrl++) ++ dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + + (ctrl * MSI_REG_CTRL_BLOCK_SIZE), +- 4, pp->irq_mask[ctrl]); +- dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + +- (ctrl * MSI_REG_CTRL_BLOCK_SIZE), +- 4, ~0); +- } ++ 4, &pp->irq_mask[ctrl]); + } + + /* Setup RC BARs */ |