diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/801-audio-0015-ASoC-fsl-sai-set-xCR4-xCR5-xMR-for-SAI-master-mode.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/801-audio-0015-ASoC-fsl-sai-set-xCR4-xCR5-xMR-for-SAI-master-mode.patch | 56 |
1 files changed, 56 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/801-audio-0015-ASoC-fsl-sai-set-xCR4-xCR5-xMR-for-SAI-master-mode.patch b/target/linux/layerscape/patches-5.4/801-audio-0015-ASoC-fsl-sai-set-xCR4-xCR5-xMR-for-SAI-master-mode.patch new file mode 100644 index 0000000000..8dbc6d1551 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/801-audio-0015-ASoC-fsl-sai-set-xCR4-xCR5-xMR-for-SAI-master-mode.patch @@ -0,0 +1,56 @@ +From 0b33246dfb59df34b2b834eb00f7aea75cbd4366 Mon Sep 17 00:00:00 2001 +From: Zidan Wang <zidan.wang@freescale.com> +Date: Mon, 9 Nov 2015 19:03:13 +0800 +Subject: [PATCH] ASoC: fsl-sai: set xCR4/xCR5/xMR for SAI master mode + +For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will +generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), +RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync +error sometimes. + +Signed-off-by: Zidan Wang <zidan.wang@freescale.com> +Acked-by: Nicolin Chen <nicoleotsuka@gmail.com> +Signed-off-by: Mark Brown <broonie@kernel.org> +(cherry picked from commit 51659ca069ce5bdf20675a7967a39ef8419e87f2) +--- + sound/soc/fsl/fsl_sai.c | 29 +++++++++++++++++++++++++++++ + 1 file changed, 29 insertions(+) + +--- a/sound/soc/fsl/fsl_sai.c ++++ b/sound/soc/fsl/fsl_sai.c +@@ -476,6 +476,35 @@ static int fsl_sai_hw_params(struct snd_ + } + } + ++ /* ++ * For SAI master mode, when Tx(Rx) sync with Rx(Tx) clock, Rx(Tx) will ++ * generate bclk and frame clock for Tx(Rx), we should set RCR4(TCR4), ++ * RCR5(TCR5) and RMR(TMR) for playback(capture), or there will be sync ++ * error. ++ */ ++ ++ if (!sai->is_slave_mode) { ++ if (!sai->synchronous[TX] && sai->synchronous[RX] && !tx) { ++ regmap_update_bits(sai->regmap, FSL_SAI_TCR4, ++ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, ++ val_cr4); ++ regmap_update_bits(sai->regmap, FSL_SAI_TCR5, ++ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | ++ FSL_SAI_CR5_FBT_MASK, val_cr5); ++ regmap_write(sai->regmap, FSL_SAI_TMR, ++ ~0UL - ((1 << channels) - 1)); ++ } else if (!sai->synchronous[RX] && sai->synchronous[TX] && tx) { ++ regmap_update_bits(sai->regmap, FSL_SAI_RCR4, ++ FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, ++ val_cr4); ++ regmap_update_bits(sai->regmap, FSL_SAI_RCR5, ++ FSL_SAI_CR5_WNW_MASK | FSL_SAI_CR5_W0W_MASK | ++ FSL_SAI_CR5_FBT_MASK, val_cr5); ++ regmap_write(sai->regmap, FSL_SAI_RMR, ++ ~0UL - ((1 << channels) - 1)); ++ } ++ } ++ + regmap_update_bits(sai->regmap, FSL_SAI_xCR4(tx), + FSL_SAI_CR4_SYWD_MASK | FSL_SAI_CR4_FRSZ_MASK, + val_cr4); |