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Diffstat (limited to 'target/linux/layerscape/patches-5.4/701-net-0393-drivers-net-dsa-felix-Handle-PAUSE-Rx-regardless-of-.patch')
-rw-r--r--target/linux/layerscape/patches-5.4/701-net-0393-drivers-net-dsa-felix-Handle-PAUSE-Rx-regardless-of-.patch35
1 files changed, 35 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/701-net-0393-drivers-net-dsa-felix-Handle-PAUSE-Rx-regardless-of-.patch b/target/linux/layerscape/patches-5.4/701-net-0393-drivers-net-dsa-felix-Handle-PAUSE-Rx-regardless-of-.patch
new file mode 100644
index 0000000000..887ca36e04
--- /dev/null
+++ b/target/linux/layerscape/patches-5.4/701-net-0393-drivers-net-dsa-felix-Handle-PAUSE-Rx-regardless-of-.patch
@@ -0,0 +1,35 @@
+From 774408ea6a55b9d40b7bdc4ff4e33f1464c605c9 Mon Sep 17 00:00:00 2001
+From: Alex Marginean <alexandru.marginean@nxp.com>
+Date: Wed, 8 Jan 2020 13:15:07 +0200
+Subject: [PATCH] drivers: net: dsa: felix: Handle PAUSE Rx regardless of AN
+ result
+
+Flow control is used with 2500Base-X and AQR PHYs to do rate adapation
+between line side 100/1000 links and MAC running at 2.5G. This is
+independent of the flow control configuration settled on line side though
+AN. In general allowing MAC to handle flow control even though AN did
+not enable it explicitly should not be a problem, so the patch enables
+it in all cases.
+
+Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
+---
+ drivers/net/dsa/ocelot/felix.c | 8 ++++++--
+ 1 file changed, 6 insertions(+), 2 deletions(-)
+
+--- a/drivers/net/dsa/ocelot/felix.c
++++ b/drivers/net/dsa/ocelot/felix.c
+@@ -267,8 +267,12 @@ static void felix_phylink_mac_config(str
+ * specification in incoming pause frames.
+ */
+ mac_fc_cfg = SYS_MAC_FC_CFG_FC_LINK_SPEED(state->speed);
+- if (state->pause & MLO_PAUSE_RX)
+- mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
++
++ /* handle Rx pause in all cases, with 2500base-X this is used for rate
++ * adaptation.
++ */
++ mac_fc_cfg |= SYS_MAC_FC_CFG_RX_FC_ENA;
++
+ if (state->pause & MLO_PAUSE_TX)
+ mac_fc_cfg |= SYS_MAC_FC_CFG_TX_FC_ENA |
+ SYS_MAC_FC_CFG_PAUSE_VAL_CFG(0xffff) |