diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/701-net-0369-Revert-net-mscc-ocelot-introduce-more-focused-PCS-op.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/701-net-0369-Revert-net-mscc-ocelot-introduce-more-focused-PCS-op.patch | 164 |
1 files changed, 164 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/701-net-0369-Revert-net-mscc-ocelot-introduce-more-focused-PCS-op.patch b/target/linux/layerscape/patches-5.4/701-net-0369-Revert-net-mscc-ocelot-introduce-more-focused-PCS-op.patch new file mode 100644 index 0000000000..9ba2030314 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/701-net-0369-Revert-net-mscc-ocelot-introduce-more-focused-PCS-op.patch @@ -0,0 +1,164 @@ +From e1aa2a770cc5f4d46693bb491ed2ca7f066c3585 Mon Sep 17 00:00:00 2001 +From: Vladimir Oltean <vladimir.oltean@nxp.com> +Date: Mon, 6 Jan 2020 14:30:41 +0200 +Subject: [PATCH] Revert "net: mscc: ocelot: introduce more focused PCS ops for + PHYLINK" + +This reverts commit 423c8b04007c85907f8f514de459ebc8541f0a54. + +Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> +--- + drivers/net/ethernet/mscc/ocelot.c | 36 ++++++++++++++++++++++++-------- + drivers/net/ethernet/mscc/ocelot_board.c | 35 +------------------------------ + include/soc/mscc/ocelot.h | 12 +++-------- + 3 files changed, 31 insertions(+), 52 deletions(-) + +--- a/drivers/net/ethernet/mscc/ocelot.c ++++ b/drivers/net/ethernet/mscc/ocelot.c +@@ -410,25 +410,43 @@ void ocelot_phylink_validate(struct ocel + unsigned long *supported, + struct phylink_link_state *state) + { +- if (ocelot->ops->pcs_validate) +- ocelot->ops->pcs_validate(ocelot, port, supported, state); ++ __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; ++ ++ if (state->interface != PHY_INTERFACE_MODE_NA && ++ state->interface != PHY_INTERFACE_MODE_GMII && ++ state->interface != PHY_INTERFACE_MODE_SGMII && ++ state->interface != PHY_INTERFACE_MODE_QSGMII) { ++ bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); ++ return; ++ } ++ ++ /* No half-duplex. */ ++ phylink_set_port_modes(mask); ++ phylink_set(mask, Autoneg); ++ phylink_set(mask, Pause); ++ phylink_set(mask, Asym_Pause); ++ phylink_set(mask, 10baseT_Full); ++ phylink_set(mask, 100baseT_Full); ++ phylink_set(mask, 1000baseT_Full); ++ phylink_set(mask, 2500baseT_Full); ++ ++ bitmap_and(supported, supported, mask, ++ __ETHTOOL_LINK_MODE_MASK_NBITS); ++ bitmap_and(state->advertising, state->advertising, mask, ++ __ETHTOOL_LINK_MODE_MASK_NBITS); + } + EXPORT_SYMBOL(ocelot_phylink_validate); + + void ocelot_phylink_mac_pcs_get_state(struct ocelot *ocelot, int port, + struct phylink_link_state *state) + { +- if (ocelot->ops->pcs_link_state) +- ocelot->ops->pcs_link_state(ocelot, port, state); +- else +- state->link = 1; ++ state->link = 1; + } + EXPORT_SYMBOL(ocelot_phylink_mac_pcs_get_state); + + void ocelot_phylink_mac_an_restart(struct ocelot *ocelot, int port) + { +- if (ocelot->ops->pcs_an_restart) +- ocelot->ops->pcs_an_restart(ocelot, port); ++ /* Not supported */ + } + EXPORT_SYMBOL(ocelot_phylink_mac_an_restart); + +@@ -472,7 +490,7 @@ void ocelot_phylink_mac_config(struct oc + ocelot_port_writel(ocelot_port, mac_mode, DEV_MAC_MODE_CFG); + + if (ocelot->ops->pcs_init) +- ocelot->ops->pcs_init(ocelot, port, link_an_mode, state); ++ ocelot->ops->pcs_init(ocelot, port); + + /* Enable MAC module */ + ocelot_port_writel(ocelot_port, DEV_MAC_ENA_CFG_RX_ENA | +--- a/drivers/net/ethernet/mscc/ocelot_board.c ++++ b/drivers/net/ethernet/mscc/ocelot_board.c +@@ -212,9 +212,7 @@ static const struct of_device_id mscc_oc + }; + MODULE_DEVICE_TABLE(of, mscc_ocelot_match); + +-static void ocelot_port_pcs_init(struct ocelot *ocelot, int port, +- unsigned int link_an_mode, +- const struct phylink_link_state *state) ++static void ocelot_port_pcs_init(struct ocelot *ocelot, int port) + { + struct ocelot_port *ocelot_port = ocelot->ports[port]; + +@@ -237,36 +235,6 @@ static void ocelot_port_pcs_init(struct + ocelot_port_writel(ocelot_port, 0, PCS1G_LB_CFG); + } + +-void ocelot_port_pcs_validate(struct ocelot *ocelot, int port, +- unsigned long *supported, +- struct phylink_link_state *state) +-{ +- __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; +- +- if (state->interface != PHY_INTERFACE_MODE_NA && +- state->interface != PHY_INTERFACE_MODE_GMII && +- state->interface != PHY_INTERFACE_MODE_SGMII && +- state->interface != PHY_INTERFACE_MODE_QSGMII) { +- bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS); +- return; +- } +- +- /* No half-duplex. */ +- phylink_set_port_modes(mask); +- phylink_set(mask, Autoneg); +- phylink_set(mask, Pause); +- phylink_set(mask, Asym_Pause); +- phylink_set(mask, 10baseT_Full); +- phylink_set(mask, 100baseT_Full); +- phylink_set(mask, 1000baseT_Full); +- phylink_set(mask, 2500baseT_Full); +- +- bitmap_and(supported, supported, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +- bitmap_and(state->advertising, state->advertising, mask, +- __ETHTOOL_LINK_MODE_MASK_NBITS); +-} +- + static int ocelot_reset(struct ocelot *ocelot) + { + int retries = 100; +@@ -292,7 +260,6 @@ static int ocelot_reset(struct ocelot *o + + static const struct ocelot_ops ocelot_ops = { + .pcs_init = ocelot_port_pcs_init, +- .pcs_validate = ocelot_port_pcs_validate, + .reset = ocelot_reset, + }; + +--- a/include/soc/mscc/ocelot.h ++++ b/include/soc/mscc/ocelot.h +@@ -412,15 +412,7 @@ enum { + struct ocelot; + + struct ocelot_ops { +- void (*pcs_init)(struct ocelot *ocelot, int port, +- unsigned int link_an_mode, +- const struct phylink_link_state *state); +- void (*pcs_an_restart)(struct ocelot *ocelot, int port); +- void (*pcs_link_state)(struct ocelot *ocelot, int port, +- struct phylink_link_state *state); +- void (*pcs_validate)(struct ocelot *ocelot, int port, +- unsigned long *supported, +- struct phylink_link_state *state); ++ void (*pcs_init)(struct ocelot *ocelot, int port); + int (*reset)(struct ocelot *ocelot); + }; + +@@ -487,6 +479,8 @@ struct ocelot { + struct mutex ptp_lock; + /* Protects the PTP clock */ + spinlock_t ptp_clock_lock; ++ ++ void (*port_pcs_init)(struct ocelot_port *port); + }; + + #define ocelot_read_ix(ocelot, reg, gi, ri) __ocelot_read_ix(ocelot, reg, reg##_GSZ * (gi) + reg##_RSZ * (ri)) |