diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/701-net-0149-soc-fsl-dpio-change-CENA-regs-to-be-cacheable.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/701-net-0149-soc-fsl-dpio-change-CENA-regs-to-be-cacheable.patch | 61 |
1 files changed, 0 insertions, 61 deletions
diff --git a/target/linux/layerscape/patches-5.4/701-net-0149-soc-fsl-dpio-change-CENA-regs-to-be-cacheable.patch b/target/linux/layerscape/patches-5.4/701-net-0149-soc-fsl-dpio-change-CENA-regs-to-be-cacheable.patch deleted file mode 100644 index eba8a12007..0000000000 --- a/target/linux/layerscape/patches-5.4/701-net-0149-soc-fsl-dpio-change-CENA-regs-to-be-cacheable.patch +++ /dev/null @@ -1,61 +0,0 @@ -From e2b0ebb44e91e3492f26d21218fb7ea5e14190ec Mon Sep 17 00:00:00 2001 -From: Haiying Wang <Haiying.Wang@nxp.com> -Date: Thu, 20 Apr 2017 11:54:22 -0400 -Subject: [PATCH] soc: fsl: dpio: change CENA regs to be cacheable - -Change cache enabled regsiter accessed to be cacheable -plus non-shareable to meet the performance requirement. -QMan's CENA region contains registers and structures that -are 64byte in size and are inteneded to be accessed using a -single 64 byte bus transaction, therefore this portal -memory should be configured as cache-enabled. Also because -the write allocate stash transcations of QBMan should be -issued as cachable and non-coherent(non-sharable), we -need to configure this region to be non-shareable. - -Signed-off-by: Haiying Wang <Haiying.Wang@nxp.com> ---- - drivers/soc/fsl/dpio/dpio-driver.c | 17 ++++++++++------- - 1 file changed, 10 insertions(+), 7 deletions(-) - ---- a/drivers/soc/fsl/dpio/dpio-driver.c -+++ b/drivers/soc/fsl/dpio/dpio-driver.c -@@ -27,6 +27,11 @@ MODULE_LICENSE("Dual BSD/GPL"); - MODULE_AUTHOR("Freescale Semiconductor, Inc"); - MODULE_DESCRIPTION("DPIO Driver"); - -+#define PROT_NORMAL_NS (PTE_TYPE_PAGE | PTE_AF | PTE_PXN | PTE_UXN | PTE_DIRTY | PTE_WRITE | PTE_ATTRINDX(MT_NORMAL)) -+ -+#define ioremap_cache_ns(addr, size) __ioremap((addr), (size), __pgprot(PROT_NORMAL_NS)) -+ -+ - struct dpio_priv { - struct dpaa2_io *io; - }; -@@ -197,13 +202,11 @@ static int dpaa2_dpio_probe(struct fsl_m - if (dpio_dev->obj_desc.region_count < 3) { - /* No support for DDR backed portals, use classic mapping */ - /* -- * Set the CENA regs to be the cache inhibited area of the -- * portal to avoid coherency issues if a user migrates to -- * another core. -+ * Set the CENA regs to be the cache enabled area of the portal to -+ * achieve the best performance. - */ -- desc.regs_cena = devm_memremap(dev, dpio_dev->regions[1].start, -- resource_size(&dpio_dev->regions[1]), -- MEMREMAP_WC); -+ desc.regs_cena = ioremap_cache_ns(dpio_dev->regions[0].start, -+ resource_size(&dpio_dev->regions[0])); - } else { - desc.regs_cena = devm_memremap(dev, dpio_dev->regions[2].start, - resource_size(&dpio_dev->regions[2]), -@@ -211,7 +214,7 @@ static int dpaa2_dpio_probe(struct fsl_m - } - - if (IS_ERR(desc.regs_cena)) { -- dev_err(dev, "devm_memremap failed\n"); -+ dev_err(dev, "ioremap_cache_ns failed\n"); - err = PTR_ERR(desc.regs_cena); - goto err_allocate_irqs; - } |