diff options
Diffstat (limited to 'target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch')
| -rw-r--r-- | target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch | 247 |
1 files changed, 247 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch b/target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch new file mode 100644 index 0000000000..9a6b32b548 --- /dev/null +++ b/target/linux/layerscape/patches-5.4/302-dts-0043-arm64-dts-lx2160aqds-Add-mdio-mux-nodes.patch @@ -0,0 +1,247 @@ +From c9be87f17c64d08c06e4858589a0014f73868867 Mon Sep 17 00:00:00 2001 +From: Pankaj Bansal <pankaj.bansal@nxp.com> +Date: Thu, 28 Feb 2019 17:28:36 +0530 +Subject: [PATCH] arm64: dts: lx2160aqds: Add mdio mux nodes + +The two external MDIO buses used to communicate with phy devices that are +external to SOC are muxed in LX2160AQDS board. +These buses can be routed to any one of the eight IO slots on LX2160AQDS +board depending on value in fpga register 0x54. +Additionally the external MDIO1 is used to communicate to the onboard +RGMII phy devices. +The mdio1 is controlled by bits 4-7 of fpga register and mdio2 is +controlled by bits 4-7 of fpga register. + +Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com> +--- + arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts | 145 ++++++++++++++++++++++ + arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts | 8 ++ + arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 24 ++-- + 3 files changed, 165 insertions(+), 12 deletions(-) + +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-qds.dts +@@ -29,6 +29,130 @@ + regulator-boot-on; + regulator-always-on; + }; ++ ++ mdio-mux-1 { ++ compatible = "mdio-mux-multiplexer"; ++ mux-controls = <&mux 0>; ++ mdio-parent-bus = <&emdio1>; ++ #address-cells=<1>; ++ #size-cells = <0>; ++ ++ mdio@0 { /* On-board PHY #1 RGMI1*/ ++ reg = <0x00>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@8 { /* On-board PHY #2 RGMI2*/ ++ reg = <0x8>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@18 { /* Slot #1 */ ++ reg = <0x18>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@19 { /* Slot #2 */ ++ reg = <0x19>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1a { /* Slot #3 */ ++ reg = <0x1a>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1b { /* Slot #4 */ ++ reg = <0x1b>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1c { /* Slot #5 */ ++ reg = <0x1c>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1d { /* Slot #6 */ ++ reg = <0x1d>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1e { /* Slot #7 */ ++ reg = <0x1e>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1f { /* Slot #8 */ ++ reg = <0x1f>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; ++ ++ mdio-mux-2 { ++ compatible = "mdio-mux-multiplexer"; ++ mux-controls = <&mux 1>; ++ mdio-parent-bus = <&emdio2>; ++ #address-cells=<1>; ++ #size-cells = <0>; ++ ++ mdio@0 { /* Slot #1 (secondary EMI) */ ++ reg = <0x00>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@1 { /* Slot #2 (secondary EMI) */ ++ reg = <0x01>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@2 { /* Slot #3 (secondary EMI) */ ++ reg = <0x02>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@3 { /* Slot #4 (secondary EMI) */ ++ reg = <0x03>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@4 { /* Slot #5 (secondary EMI) */ ++ reg = <0x04>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@5 { /* Slot #6 (secondary EMI) */ ++ reg = <0x05>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@6 { /* Slot #7 (secondary EMI) */ ++ reg = <0x06>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ ++ mdio@7 { /* Slot #8 (secondary EMI) */ ++ reg = <0x07>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ }; ++ }; + }; + + &crypto { +@@ -71,6 +195,14 @@ + }; + }; + ++&emdio1 { ++ status = "okay"; ++}; ++ ++&emdio2 { ++ status = "okay"; ++}; ++ + &esdhc0 { + status = "okay"; + }; +@@ -82,6 +214,19 @@ + &i2c0 { + status = "okay"; + ++ fpga@66 { ++ compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c", ++ "simple-mfd"; ++ reg = <0x66>; ++ ++ mux: mux-controller { ++ compatible = "reg-mux"; ++ #mux-control-cells = <1>; ++ mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */ ++ <0x54 0x07>; /* 1: reg 0x54, bit 2:0 */ ++ }; ++ }; ++ + i2c-mux@77 { + compatible = "nxp,pca9547"; + reg = <0x77>; +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-rdb.dts +@@ -35,6 +35,14 @@ + status = "okay"; + }; + ++&emdio1 { ++ status = "okay"; ++}; ++ ++&emdio2 { ++ status = "okay"; ++}; ++ + &esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; +--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +@@ -478,26 +478,26 @@ + little-endian; + }; + +- /* TODO: WRIOP (CCSR?) */ +- emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, E-MDIO1: 0x1_6000 */ ++ /* WRIOP0: 0x8b8_0000, E-MDIO1: 0x1_6000 */ ++ emdio1: mdio@8b96000 { + compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8B96000 0x0 0x1000>; +- device_type = "mdio"; /* TODO: is this necessary? */ +- little-endian; /* force the driver in LE mode */ +- +- /* Not necessary on the QDS, but needed on the RDB */ ++ reg = <0x0 0x8b96000 0x0 0x1000>; ++ interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; ++ little-endian; /* force the driver in LE mode */ ++ status = "disabled"; + }; + +- emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, E-MDIO2: 0x1_7000 */ ++ /* WRIOP0: 0x8b8_0000, E-MDIO2: 0x1_7000 */ ++ emdio2: mdio@8b97000 { + compatible = "fsl,fman-memac-mdio"; +- reg = <0x0 0x8B97000 0x0 0x1000>; +- device_type = "mdio"; /* TODO: is this necessary? */ +- little-endian; /* force the driver in LE mode */ +- ++ reg = <0x0 0x8b97000 0x0 0x1000>; ++ interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <1>; + #size-cells = <0>; ++ little-endian; /* force the driver in LE mode */ ++ status = "disabled"; + }; + + pcs_mdio1: mdio@0x8c07000 { |