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Diffstat (limited to 'target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch')
-rw-r--r--target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch38
1 files changed, 0 insertions, 38 deletions
diff --git a/target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch b/target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch
deleted file mode 100644
index 212063986b..0000000000
--- a/target/linux/layerscape/patches-5.4/302-dts-0014-arm64-dts-ls104xa-set-mask-to-drop-TBU-ID-from-Strea.patch
+++ /dev/null
@@ -1,38 +0,0 @@
-From 66307f9e693bd4822a683fac8cf1f63533822c18 Mon Sep 17 00:00:00 2001
-From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
-Date: Thu, 3 May 2018 18:05:43 +0300
-Subject: [PATCH] arm64: dts: ls104xa: set mask to drop TBU ID from StreamID
-
-The StreamID entering the SMMU is actually a concatenation of the
-SMMU TBU ID and the ICID configured in software.
-Since the TBU ID is internal to the SoC and since we want that the
-actual the ICID configured in software to enter the SMMU witout any
-additional set bits, mask out the TBU ID bits and leave only the
-relevant ICID bits to enter SMMU.
-
-Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
----
- arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 1 +
- arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 1 +
- 2 files changed, 2 insertions(+)
-
---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
-@@ -230,6 +230,7 @@
- compatible = "arm,mmu-500";
- reg = <0 0x9000000 0 0x400000>;
- dma-coherent;
-+ stream-match-mask = <0x7f00>;
- #global-interrupts = <2>;
- #iommu-cells = <1>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
---- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
-@@ -233,6 +233,7 @@
- compatible = "arm,mmu-500";
- reg = <0 0x9000000 0 0x400000>;
- dma-coherent;
-+ stream-match-mask = <0x7f00>;
- #global-interrupts = <2>;
- #iommu-cells = <1>;
- interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,