diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch | 10549 |
1 files changed, 0 insertions, 10549 deletions
diff --git a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch b/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch deleted file mode 100644 index 36854f1937..0000000000 --- a/target/linux/layerscape/patches-4.9/302-dts-support-layercape.patch +++ /dev/null @@ -1,10549 +0,0 @@ -From 2ba4c76bc645b7b4ff04364f294f3022d369108a Mon Sep 17 00:00:00 2001 -From: Yangbo Lu <yangbo.lu@nxp.com> -Date: Thu, 5 Jul 2018 16:20:56 +0800 -Subject: [PATCH 04/32] dts: support layercape - -This is an integrated patch for layerscape dts support. - -Signed-off-by: Amrita Kumari <amrita.kumari@nxp.com> -Signed-off-by: Alison Wang <b18965@freescale.com> -Signed-off-by: Li Yang <leoyang.li@nxp.com> -Signed-off-by: Ashish Kumar <Ashish.Kumar@nxp.com> -Signed-off-by: Zhao Qiang <qiang.zhao@nxp.com> -Signed-off-by: Rajesh Bhagat <rajesh.bhagat@freescale.com> -Signed-off-by: Zhang Ying-22455 <ying.zhang22455@nxp.com> -Signed-off-by: Madalin Bucur <madalin.bucur@nxp.com> -Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com> -Signed-off-by: Suresh Gupta <suresh.gupta@nxp.com> -Signed-off-by: Chenhui Zhao <chenhui.zhao@nxp.com> -Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> -Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> -Signed-off-by: Changming Huang <jerry.huang@nxp.com> -Signed-off-by: Bharat Bhushan <Bharat.Bhushan@nxp.com> -Signed-off-by: Meng Yi <meng.yi@nxp.com> -Signed-off-by: Shaohui Xie <Shaohui.Xie@nxp.com> -Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> -Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> -Signed-off-by: Ran Wang <ran.wang_1@nxp.com> -Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> ---- - arch/arm/boot/dts/alpine.dtsi | 2 +- - arch/arm/boot/dts/axm55xx.dtsi | 2 +- - arch/arm/boot/dts/ecx-2000.dts | 2 +- - arch/arm/boot/dts/imx6ul.dtsi | 4 +- - arch/arm/boot/dts/keystone.dtsi | 4 +- - arch/arm/boot/dts/ls1021a-qds.dts | 26 + - arch/arm/boot/dts/ls1021a-twr.dts | 25 + - arch/arm/boot/dts/ls1021a.dtsi | 284 ++++-- - arch/arm/boot/dts/mt6580.dtsi | 2 +- - arch/arm/boot/dts/mt6589.dtsi | 2 +- - arch/arm/boot/dts/mt8127.dtsi | 2 +- - arch/arm/boot/dts/mt8135.dtsi | 2 +- - arch/arm/boot/dts/rk3288.dtsi | 2 +- - arch/arm/boot/dts/sun6i-a31.dtsi | 2 +- - arch/arm/boot/dts/sun7i-a20.dtsi | 4 +- - arch/arm/boot/dts/sun8i-a23-a33.dtsi | 2 +- - arch/arm/boot/dts/sun9i-a80.dtsi | 2 +- - arch/arm64/boot/dts/freescale/Makefile | 18 + - .../boot/dts/freescale/fsl-ls1012a-2g5rdb.dts | 123 +++ - .../boot/dts/freescale/fsl-ls1012a-frdm.dts | 141 +++ - .../boot/dts/freescale/fsl-ls1012a-frwy.dts | 177 ++++ - .../boot/dts/freescale/fsl-ls1012a-qds.dts | 166 ++++ - .../boot/dts/freescale/fsl-ls1012a-rdb.dts | 102 ++ - .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 567 +++++++++++ - .../boot/dts/freescale/fsl-ls1043-post.dtsi | 44 + - .../dts/freescale/fsl-ls1043a-qds-sdk.dts | 71 ++ - .../boot/dts/freescale/fsl-ls1043a-qds.dts | 210 ++++- - .../dts/freescale/fsl-ls1043a-rdb-sdk.dts | 71 ++ - .../dts/freescale/fsl-ls1043a-rdb-usdpaa.dts | 117 +++ - .../boot/dts/freescale/fsl-ls1043a-rdb.dts | 152 ++- - .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 357 +++++-- - .../boot/dts/freescale/fsl-ls1046-post.dtsi | 48 + - .../dts/freescale/fsl-ls1046a-qds-sdk.dts | 112 +++ - .../boot/dts/freescale/fsl-ls1046a-qds.dts | 326 +++++++ - .../dts/freescale/fsl-ls1046a-rdb-sdk.dts | 85 ++ - .../dts/freescale/fsl-ls1046a-rdb-usdpaa.dts | 110 +++ - .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 181 ++++ - .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 771 +++++++++++++++ - .../boot/dts/freescale/fsl-ls1088a-qds.dts | 137 +++ - .../boot/dts/freescale/fsl-ls1088a-rdb.dts | 200 ++++ - .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 800 ++++++++++++++++ - .../boot/dts/freescale/fsl-ls2080a-qds.dts | 229 +---- - .../boot/dts/freescale/fsl-ls2080a-rdb.dts | 207 ++-- - .../boot/dts/freescale/fsl-ls2080a-simu.dts | 47 +- - .../arm64/boot/dts/freescale/fsl-ls2080a.dtsi | 803 ++-------------- - .../boot/dts/freescale/fsl-ls2081a-rdb.dts | 161 ++++ - .../boot/dts/freescale/fsl-ls2088a-qds.dts | 126 +++ - .../boot/dts/freescale/fsl-ls2088a-rdb.dts | 104 ++ - .../arm64/boot/dts/freescale/fsl-ls2088a.dtsi | 159 ++++ - .../boot/dts/freescale/fsl-ls208xa-qds.dtsi | 162 ++++ - .../boot/dts/freescale/fsl-ls208xa-rdb.dtsi | 136 +++ - .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 885 ++++++++++++++++++ - .../dts/freescale/qoriq-bman-portals-sdk.dtsi | 55 ++ - .../dts/freescale/qoriq-bman-portals.dtsi | 77 ++ - .../boot/dts/freescale/qoriq-dpaa-eth.dtsi | 73 ++ - .../dts/freescale/qoriq-fman3-0-10g-0.dtsi | 43 + - .../dts/freescale/qoriq-fman3-0-10g-1.dtsi | 43 + - .../dts/freescale/qoriq-fman3-0-1g-0.dtsi | 42 + - .../dts/freescale/qoriq-fman3-0-1g-1.dtsi | 42 + - .../dts/freescale/qoriq-fman3-0-1g-2.dtsi | 42 + - .../dts/freescale/qoriq-fman3-0-1g-3.dtsi | 42 + - .../dts/freescale/qoriq-fman3-0-1g-4.dtsi | 42 + - .../dts/freescale/qoriq-fman3-0-1g-5.dtsi | 42 + - .../boot/dts/freescale/qoriq-fman3-0-6oh.dtsi | 47 + - .../boot/dts/freescale/qoriq-fman3-0.dtsi | 130 +++ - .../dts/freescale/qoriq-qman-portals-sdk.dtsi | 38 + - .../dts/freescale/qoriq-qman-portals.dtsi | 87 ++ - .../boot/dts/fsl/qoriq-bman1-portals.dtsi | 10 + - .../boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi | 4 +- - .../boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi | 4 +- - 70 files changed, 8051 insertions(+), 1286 deletions(-) - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi - create mode 100644 arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi - ---- a/arch/arm/boot/dts/alpine.dtsi -+++ b/arch/arm/boot/dts/alpine.dtsi -@@ -93,7 +93,7 @@ - interrupt-controller; - reg = <0x0 0xfb001000 0x0 0x1000>, - <0x0 0xfb002000 0x0 0x2000>, -- <0x0 0xfb004000 0x0 0x1000>, -+ <0x0 0xfb004000 0x0 0x2000>, - <0x0 0xfb006000 0x0 0x2000>; - interrupts = - <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; ---- a/arch/arm/boot/dts/axm55xx.dtsi -+++ b/arch/arm/boot/dts/axm55xx.dtsi -@@ -62,7 +62,7 @@ - #address-cells = <0>; - interrupt-controller; - reg = <0x20 0x01001000 0 0x1000>, -- <0x20 0x01002000 0 0x1000>, -+ <0x20 0x01002000 0 0x2000>, - <0x20 0x01004000 0 0x2000>, - <0x20 0x01006000 0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | ---- a/arch/arm/boot/dts/ecx-2000.dts -+++ b/arch/arm/boot/dts/ecx-2000.dts -@@ -99,7 +99,7 @@ - interrupt-controller; - interrupts = <1 9 0xf04>; - reg = <0xfff11000 0x1000>, -- <0xfff12000 0x1000>, -+ <0xfff12000 0x2000>, - <0xfff14000 0x2000>, - <0xfff16000 0x2000>; - }; ---- a/arch/arm/boot/dts/imx6ul.dtsi -+++ b/arch/arm/boot/dts/imx6ul.dtsi -@@ -89,11 +89,11 @@ - }; - - intc: interrupt-controller@00a01000 { -- compatible = "arm,cortex-a7-gic"; -+ compatible = "arm,gic-400", "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x00a01000 0x1000>, -- <0x00a02000 0x1000>, -+ <0x00a02000 0x2000>, - <0x00a04000 0x2000>, - <0x00a06000 0x2000>; - }; ---- a/arch/arm/boot/dts/keystone.dtsi -+++ b/arch/arm/boot/dts/keystone.dtsi -@@ -30,12 +30,12 @@ - }; - - gic: interrupt-controller { -- compatible = "arm,cortex-a15-gic"; -+ compatible = "arm,gic-400", "arm,cortex-a15-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x02561000 0x0 0x1000>, - <0x0 0x02562000 0x0 0x2000>, -- <0x0 0x02564000 0x0 0x1000>, -+ <0x0 0x02564000 0x0 0x2000>, - <0x0 0x02566000 0x0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | - IRQ_TYPE_LEVEL_HIGH)>; ---- a/arch/arm/boot/dts/ls1021a-qds.dts -+++ b/arch/arm/boot/dts/ls1021a-qds.dts -@@ -124,6 +124,19 @@ - }; - }; - -+&qspi { -+ num-cs = <2>; -+ status = "okay"; -+ -+ qflash0: s25fl128s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ - &enet0 { - tbi-handle = <&tbi0>; - phy-handle = <&sgmii_phy1c>; -@@ -239,6 +252,11 @@ - device-width = <1>; - }; - -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ - fpga: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; -@@ -331,3 +349,11 @@ - &uart1 { - status = "okay"; - }; -+ -+&can0 { -+ status = "okay"; -+}; -+ -+&can1 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/ls1021a-twr.dts -+++ b/arch/arm/boot/dts/ls1021a-twr.dts -@@ -142,6 +142,19 @@ - }; - }; - -+&qspi { -+ num-cs = <2>; -+ status = "okay"; -+ -+ qflash0: n25q128a13@0 { -+ compatible = "n25q128a13", "jedec,spi-nor"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ - &enet0 { - tbi-handle = <&tbi1>; - phy-handle = <&sgmii_phy2>; -@@ -228,6 +241,10 @@ - }; - }; - -+&esdhc { -+ status = "okay"; -+}; -+ - &sai1 { - status = "okay"; - }; -@@ -243,3 +260,11 @@ - &uart1 { - status = "okay"; - }; -+ -+&can0 { -+ status = "okay"; -+}; -+ -+&can1 { -+ status = "okay"; -+}; ---- a/arch/arm/boot/dts/ls1021a.dtsi -+++ b/arch/arm/boot/dts/ls1021a.dtsi -@@ -47,6 +47,7 @@ - - #include "skeleton64.dtsi" - #include <dt-bindings/interrupt-controller/arm-gic.h> -+#include <dt-bindings/thermal/thermal.h> - - / { - compatible = "fsl,ls1021a"; -@@ -70,21 +71,29 @@ - #address-cells = <1>; - #size-cells = <0>; - -- cpu@f00 { -+ cpu0: @f00 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf00>; -- clocks = <&cluster1_clk>; -+ clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; - }; - -- cpu@f01 { -+ cpu1: @f01 { - compatible = "arm,cortex-a7"; - device_type = "cpu"; - reg = <0xf01>; -- clocks = <&cluster1_clk>; -+ clocks = <&clockgen 1 0>; - }; - }; - -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ - timer { - compatible = "arm,armv7-timer"; - interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>, -@@ -108,11 +117,11 @@ - ranges; - - gic: interrupt-controller@1400000 { -- compatible = "arm,cortex-a7-gic"; -+ compatible = "arm,gic-400", "arm,cortex-a7-gic"; - #interrupt-cells = <3>; - interrupt-controller; - reg = <0x0 0x1401000 0x0 0x1000>, -- <0x0 0x1402000 0x0 0x1000>, -+ <0x0 0x1402000 0x0 0x2000>, - <0x0 0x1404000 0x0 0x2000>, - <0x0 0x1406000 0x0 0x2000>; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; -@@ -120,14 +129,14 @@ - }; - - msi1: msi-controller@1570e00 { -- compatible = "fsl,1s1021a-msi"; -+ compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e00 0x0 0x8>; - msi-controller; - interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; - }; - - msi2: msi-controller@1570e08 { -- compatible = "fsl,1s1021a-msi"; -+ compatible = "fsl,ls1021a-msi"; - reg = <0x0 0x1570e08 0x0 0x8>; - msi-controller; - interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; -@@ -137,11 +146,12 @@ - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; - }; - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1021a-dcfg", "syscon"; -- reg = <0x0 0x1ee0000 0x0 0x10000>; -+ reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - -@@ -163,7 +173,7 @@ - <0x0 0x20220520 0x0 0x4>; - reg-names = "ahci", "sata-ecc"; - interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - dma-coherent; - status = "disabled"; - }; -@@ -214,43 +224,89 @@ - }; - - clockgen: clocking@1ee1000 { -- #address-cells = <1>; -- #size-cells = <1>; -- ranges = <0x0 0x0 0x1ee1000 0x10000>; -+ compatible = "fsl,ls1021a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; - -- sysclk: sysclk { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-output-names = "sysclk"; -- }; -- -- cga_pll1: pll@800 { -- compatible = "fsl,qoriq-core-pll-2.0"; -- #clock-cells = <1>; -- reg = <0x800 0x10>; -- clocks = <&sysclk>; -- clock-output-names = "cga-pll1", "cga-pll1-div2", -- "cga-pll1-div4"; -- }; -- -- platform_clk: pll@c00 { -- compatible = "fsl,qoriq-core-pll-2.0"; -- #clock-cells = <1>; -- reg = <0xc00 0x10>; -- clocks = <&sysclk>; -- clock-output-names = "platform-clk", "platform-clk-div2"; -- }; -- -- cluster1_clk: clk0c0@0 { -- compatible = "fsl,qoriq-core-mux-2.0"; -- #clock-cells = <0>; -- reg = <0x0 0x10>; -- clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4"; -- clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>; -- clock-output-names = "cluster1-clk"; -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; -+ fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x30061>; -+ fsl,tmu-calibration = <0x00000000 0x0000000f -+ 0x00000001 0x00000017 -+ 0x00000002 0x0000001e -+ 0x00000003 0x00000026 -+ 0x00000004 0x0000002e -+ 0x00000005 0x00000035 -+ 0x00000006 0x0000003d -+ 0x00000007 0x00000044 -+ 0x00000008 0x0000004c -+ 0x00000009 0x00000053 -+ 0x0000000a 0x0000005b -+ 0x0000000b 0x00000064 -+ -+ 0x00010000 0x00000011 -+ 0x00010001 0x0000001c -+ 0x00010002 0x00000024 -+ 0x00010003 0x0000002b -+ 0x00010004 0x00000034 -+ 0x00010005 0x00000039 -+ 0x00010006 0x00000042 -+ 0x00010007 0x0000004c -+ 0x00010008 0x00000051 -+ 0x00010009 0x0000005a -+ 0x0001000a 0x00000063 -+ -+ 0x00020000 0x00000013 -+ 0x00020001 0x00000019 -+ 0x00020002 0x00000024 -+ 0x00020003 0x0000002c -+ 0x00020004 0x00000035 -+ 0x00020005 0x0000003d -+ 0x00020006 0x00000046 -+ 0x00020007 0x00000050 -+ 0x00020008 0x00000059 -+ -+ 0x00030000 0x00000002 -+ 0x00030001 0x0000000d -+ 0x00030002 0x00000019 -+ 0x00030003 0x00000024>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 0>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; - }; - }; -- - dspi0: dspi@2100000 { - compatible = "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; -@@ -258,7 +314,7 @@ - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; -@@ -271,31 +327,48 @@ - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - spi-num-chipselects = <6>; - big-endian; - status = "disabled"; - }; - -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x4000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ big-endian; -+ amba-base = <0x40000000>; -+ status = "disabled"; -+ }; -+ - i2c0: i2c@2180000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; - interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; -+ fsl-scl-gpio = <&gpio3 23 0>; - status = "disabled"; - }; - - i2c1: i2c@2190000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1021a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2190000 0x0 0x10000>; - interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; -+ fsl-scl-gpio = <&gpio3 23 0>; - status = "disabled"; - }; - -@@ -306,7 +379,7 @@ - reg = <0x0 0x21a0000 0x0 0x10000>; - interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - status = "disabled"; - }; - -@@ -399,7 +472,7 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2960000 0x0 0x1000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; -@@ -408,7 +481,7 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2970000 0x0 0x1000>; - interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; -@@ -417,7 +490,7 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2980000 0x0 0x1000>; - interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; -@@ -426,7 +499,7 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2990000 0x0 0x1000>; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; -@@ -435,16 +508,26 @@ - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x29a0000 0x0 0x1000>; - interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "ipg"; - status = "disabled"; - }; - -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ls1021a-ftm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; -+ status = "okay"; -+ }; -+ - wdog0: watchdog@2ad0000 { - compatible = "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; - interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>; -+ clocks = <&clockgen 4 1>; - clock-names = "wdog-en"; - big-endian; - }; -@@ -454,8 +537,8 @@ - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b50000 0x0 0x10000>; - interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>, <&platform_clk 1>, -- <&platform_clk 1>, <&platform_clk 1>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 47>, -@@ -468,8 +551,8 @@ - compatible = "fsl,vf610-sai"; - reg = <0x0 0x2b60000 0x0 0x10000>; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 1>, <&platform_clk 1>, -- <&platform_clk 1>, <&platform_clk 1>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>, -+ <&clockgen 4 1>, <&clockgen 4 1>; - clock-names = "bus", "mclk1", "mclk2", "mclk3"; - dma-names = "tx", "rx"; - dmas = <&edma0 1 45>, -@@ -489,16 +572,31 @@ - dma-channels = <32>; - big-endian; - clock-names = "dmamux0", "dmamux1"; -- clocks = <&platform_clk 1>, -- <&platform_clk 1>; -+ clocks = <&clockgen 4 1>, -+ <&clockgen 4 1>; -+ }; -+ -+ qdma: qdma@8390000 { -+ compatible = "fsl,ls1021a-qdma"; -+ reg = <0x0 0x8398000 0x0 0x1000>, /* Controller regs */ -+ <0x0 0x8399000 0x0 0x1000>, /* Status regs */ -+ <0x0 0x839a000 0x0 0x2000>; /* Block regs */ -+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "qdma-error", "qdma-queue"; -+ channels = <8>; -+ queues = <2>; -+ status-sizes = <64>; -+ queue-sizes = <64 64>; -+ big-endian; - }; - - dcu: dcu@2ce0000 { - compatible = "fsl,ls1021a-dcu"; - reg = <0x0 0x2ce0000 0x0 0x10000>; - interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; -- clocks = <&platform_clk 0>, -- <&platform_clk 0>; -+ clocks = <&clockgen 4 0>, -+ <&clockgen 4 0>; - clock-names = "dcu", "pix"; - big-endian; - status = "disabled"; -@@ -626,7 +724,11 @@ - interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; -+ configure-gfladj; -+ dma-coherent; - snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - }; - - pcie@3400000 { -@@ -634,7 +736,9 @@ - reg = <0x00 0x03400000 0x0 0x00010000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */ -+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "pme", "aer"; - fsl,pcie-scfg = <&scfg 0>; - #address-cells = <3>; - #size-cells = <2>; -@@ -643,7 +747,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi1>; -+ msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, -@@ -657,7 +761,9 @@ - reg = <0x00 0x03500000 0x0 0x00010000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; -+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "pme", "aer"; - fsl,pcie-scfg = <&scfg 1>; - #address-cells = <3>; - #size-cells = <2>; -@@ -666,7 +772,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi2>; -+ msi-parent = <&msi1>, <&msi2>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, -@@ -674,5 +780,45 @@ - <0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, - <0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>; - }; -+ -+ can0: can@2a70000 { -+ compatible = "fsl,ls1021ar2-flexcan"; -+ reg = <0x0 0x2a70000 0x0 0x1000>; -+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ clock-names = "ipg", "per"; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ can1: can@2a80000 { -+ compatible = "fsl,ls1021ar2-flexcan"; -+ reg = <0x0 0x2a80000 0x0 0x1000>; -+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ clock-names = "ipg", "per"; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ can2: can@2a90000 { -+ compatible = "fsl,ls1021ar2-flexcan"; -+ reg = <0x0 0x2a90000 0x0 0x1000>; -+ interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ clock-names = "ipg", "per"; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ can3: can@2aa0000 { -+ compatible = "fsl,ls1021ar2-flexcan"; -+ reg = <0x0 0x2aa0000 0x0 0x1000>; -+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ clock-names = "ipg", "per"; -+ big-endian; -+ status = "disabled"; -+ }; - }; - }; ---- a/arch/arm/boot/dts/mt6580.dtsi -+++ b/arch/arm/boot/dts/mt6580.dtsi -@@ -91,7 +91,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, -- <0x10212000 0x1000>, -+ <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; ---- a/arch/arm/boot/dts/mt6589.dtsi -+++ b/arch/arm/boot/dts/mt6589.dtsi -@@ -102,7 +102,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0x10211000 0x1000>, -- <0x10212000 0x1000>, -+ <0x10212000 0x2000>, - <0x10214000 0x2000>, - <0x10216000 0x2000>; - }; ---- a/arch/arm/boot/dts/mt8127.dtsi -+++ b/arch/arm/boot/dts/mt8127.dtsi -@@ -129,7 +129,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, -- <0 0x10212000 0 0x1000>, -+ <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; ---- a/arch/arm/boot/dts/mt8135.dtsi -+++ b/arch/arm/boot/dts/mt8135.dtsi -@@ -221,7 +221,7 @@ - #interrupt-cells = <3>; - interrupt-parent = <&gic>; - reg = <0 0x10211000 0 0x1000>, -- <0 0x10212000 0 0x1000>, -+ <0 0x10212000 0 0x2000>, - <0 0x10214000 0 0x2000>, - <0 0x10216000 0 0x2000>; - }; ---- a/arch/arm/boot/dts/rk3288.dtsi -+++ b/arch/arm/boot/dts/rk3288.dtsi -@@ -1109,7 +1109,7 @@ - #address-cells = <0>; - - reg = <0xffc01000 0x1000>, -- <0xffc02000 0x1000>, -+ <0xffc02000 0x2000>, - <0xffc04000 0x2000>, - <0xffc06000 0x2000>; - interrupts = <GIC_PPI 9 0xf04>; ---- a/arch/arm/boot/dts/sun6i-a31.dtsi -+++ b/arch/arm/boot/dts/sun6i-a31.dtsi -@@ -791,7 +791,7 @@ - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, -- <0x01c82000 0x1000>, -+ <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; ---- a/arch/arm/boot/dts/sun7i-a20.dtsi -+++ b/arch/arm/boot/dts/sun7i-a20.dtsi -@@ -1685,9 +1685,9 @@ - }; - - gic: interrupt-controller@01c81000 { -- compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; -+ compatible = "arm,gic-400", "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, -- <0x01c82000 0x1000>, -+ <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; ---- a/arch/arm/boot/dts/sun8i-a23-a33.dtsi -+++ b/arch/arm/boot/dts/sun8i-a23-a33.dtsi -@@ -488,7 +488,7 @@ - gic: interrupt-controller@01c81000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c81000 0x1000>, -- <0x01c82000 0x1000>, -+ <0x01c82000 0x2000>, - <0x01c84000 0x2000>, - <0x01c86000 0x2000>; - interrupt-controller; ---- a/arch/arm/boot/dts/sun9i-a80.dtsi -+++ b/arch/arm/boot/dts/sun9i-a80.dtsi -@@ -613,7 +613,7 @@ - gic: interrupt-controller@01c41000 { - compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic"; - reg = <0x01c41000 0x1000>, -- <0x01c42000 0x1000>, -+ <0x01c42000 0x2000>, - <0x01c44000 0x2000>, - <0x01c46000 0x2000>; - interrupt-controller; ---- a/arch/arm64/boot/dts/freescale/Makefile -+++ b/arch/arm64/boot/dts/freescale/Makefile -@@ -1,8 +1,26 @@ -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frdm.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-frwy.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1012a-2g5rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds-sdk.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb-usdpaa.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-sdk.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb-usdpaa.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb - dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-simu.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-qds.dtb -+dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2088a-rdb.dtb - - always := $(dtb-y) - subdir-y := $(dts-dirs) ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-2g5rdb.dts -@@ -0,0 +1,123 @@ -+/* -+ * Device Tree file for NXP LS1012A 2G5RDB Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Bhaskar Upadhaya <bhaskar.upadhaya@nxp.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A 2G5RDB Board"; -+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frdm.dts -@@ -0,0 +1,141 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS1012A Freedom Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A Freedom Board"; -+ compatible = "fsl,ls1012a-frdm", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ system-clock-frequency = <25000000>; -+ }; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ codec: sgtl5000@a { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,sgtl5000"; -+ reg = <0xa>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_1p8v>; -+ clocks = <&sys_mclk>; -+ }; -+}; -+ -+&qspi { -+ num-cs = <1>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ -+&sai2 { -+ status = "okay"; -+}; -+ -+&sata { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-frwy.dts -@@ -0,0 +1,177 @@ -+/* -+ * Device Tree file for NXP LS1012A FRWY Board. -+ * -+ * Copyright 2018 NXP -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A FRWY Board"; -+ compatible = "fsl,ls1012a-frwy", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <25000000>; -+ }; -+ -+ reg_1p8v: regulator-1p8v { -+ compatible = "regulator-fixed"; -+ regulator-name = "1P8V"; -+ regulator-min-microvolt = <1800000>; -+ regulator-max-microvolt = <1800000>; -+ regulator-always-on; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ system-clock-frequency = <25000000>; -+ }; -+ }; -+}; -+ -+&pcie { -+ status = "okay"; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ codec: sgtl5000@a { -+ compatible = "fsl,sgtl5000"; -+ #sound-dai-cells = <0>; -+ reg = <0xa>; -+ VDDA-supply = <®_1p8v>; -+ VDDIO-supply = <®_1p8v>; -+ clocks = <&sys_mclk>; -+ }; -+}; -+ -+&qspi { -+ num-cs = <1>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: w25q16dw@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ -+&sai2 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-qds.dts -@@ -0,0 +1,166 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS1012A QDS Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A QDS Board"; -+ compatible = "fsl,ls1012a-qds", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+ -+ sys_mclk: clock-mclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <24576000>; -+ }; -+ -+ reg_3p3v: regulator-3p3v { -+ compatible = "regulator-fixed"; -+ regulator-name = "3P3V"; -+ regulator-min-microvolt = <3300000>; -+ regulator-max-microvolt = <3300000>; -+ regulator-always-on; -+ }; -+ -+ sound { -+ compatible = "simple-audio-card"; -+ simple-audio-card,format = "i2s"; -+ simple-audio-card,widgets = -+ "Microphone", "Microphone Jack", -+ "Headphone", "Headphone Jack", -+ "Speaker", "Speaker Ext", -+ "Line", "Line In Jack"; -+ simple-audio-card,routing = -+ "MIC_IN", "Microphone Jack", -+ "Microphone Jack", "Mic Bias", -+ "LINE_IN", "Line In Jack", -+ "Headphone Jack", "HP_OUT", -+ "Speaker Ext", "LINE_OUT"; -+ -+ simple-audio-card,cpu { -+ sound-dai = <&sai2>; -+ frame-master; -+ bitclock-master; -+ }; -+ -+ simple-audio-card,codec { -+ sound-dai = <&codec>; -+ frame-master; -+ bitclock-master; -+ system-clock-frequency = <24576000>; -+ }; -+ }; -+}; -+ -+&pcie { -+ status = "okay"; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ pca9547@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@4 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x4>; -+ -+ codec: sgtl5000@a { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,sgtl5000"; -+ reg = <0xa>; -+ VDDA-supply = <®_3p3v>; -+ VDDIO-supply = <®_3p3v>; -+ clocks = <&sys_mclk>; -+ }; -+ }; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x1>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x2>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x1>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x3>; -+ phy-mode = "sgmii-2500"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; -+ -+&sai2 { -+ status = "okay"; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&esdhc0 { -+ status = "okay"; -+}; -+ -+&esdhc1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a-rdb.dts -@@ -0,0 +1,102 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS1012A RDB Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ */ -+/dts-v1/; -+ -+#include "fsl-ls1012a.dtsi" -+ -+/ { -+ model = "LS1012A RDB Board"; -+ compatible = "fsl,ls1012a-rdb", "fsl,ls1012a"; -+ -+ aliases { -+ ethernet0 = &pfe_mac0; -+ ethernet1 = &pfe_mac1; -+ }; -+}; -+ -+&pcie { -+ status = "okay"; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&esdhc0 { -+ sd-uhs-sdr104; -+ sd-uhs-sdr50; -+ sd-uhs-sdr25; -+ sd-uhs-sdr12; -+ status = "okay"; -+}; -+ -+&esdhc1 { -+ mmc-hs200-1_8v; -+ status = "okay"; -+}; -+ -+&pfe { -+ status = "okay"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ ethernet@0 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0>; /* GEM_ID */ -+ fsl,gemac-bus-id = <0x0>; /* BUS_ID */ -+ fsl,gemac-phy-id = <0x2>; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "sgmii"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x1>; /* enabled/disabled */ -+ }; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,pfe-gemac-port"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x1>; /* GEM_ID */ -+ fsl,gemac-bus-id = < 0x1 >; /* BUS_ID */ -+ fsl,gemac-phy-id = < 0x1 >; /* PHY_ID */ -+ fsl,mdio-mux-val = <0x0>; -+ phy-mode = "rgmii-txid"; -+ fsl,pfe-phy-if-flags = <0x0>; -+ -+ mdio@0 { -+ reg = <0x0>; /* enabled/disabled */ -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi -@@ -0,0 +1,567 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1012A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ */ -+ -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+#include <dt-bindings/thermal/thermal.h> -+ -+/ { -+ compatible = "fsl,ls1012a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ crypto = &crypto; -+ rtic_a = &rtic_a; -+ rtic_b = &rtic_b; -+ rtic_c = &rtic_c; -+ rtic_d = &rtic_d; -+ sec_mon = &sec_mon; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ }; -+ -+ idle-states { -+ /* -+ * PSCI node is not added default, U-boot will add missing -+ * parts if it determines to use PSCI. -+ */ -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x0>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <125000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ coreclk: coreclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "coreclk"; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ -+ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ -+ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ -+ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <0 106 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ gic: interrupt-controller@1400000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x1401000 0 0x1000>, /* GICD */ -+ <0x0 0x1402000 0 0x2000>, /* GICC */ -+ <0x0 0x1404000 0 0x2000>, /* GICH */ -+ <0x0 0x1406000 0 0x2000>; /* GICV */ -+ interrupts = <1 9 IRQ_TYPE_LEVEL_LOW>; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&dcfg>; -+ offset = <0xb0>; -+ mask = <0x02>; -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ scfg: scfg@1570000 { -+ compatible = "fsl,ls1012a-scfg", "syscon"; -+ reg = <0x0 0x1570000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ crypto: crypto@1700000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x1700000 0x100000>; -+ reg = <0x00 0x1700000 0x0 0x100000>; -+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ caam-dma { -+ compatible = "fsl,sec-v5.4-dma", -+ "fsl,sec-v5.0-dma", -+ "fsl,sec-v4.0-dma"; -+ }; -+ -+ rtic@60000 { -+ compatible = "fsl,sec-v5.4-rtic", -+ "fsl,sec-v5.0-rtic", -+ "fsl,sec-v4.0-rtic"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x60000 0x100 0x60e00 0x18>; -+ ranges = <0x0 0x60100 0x500>; -+ -+ rtic_a: rtic-a@0 { -+ compatible = "fsl,sec-v5.4-rtic-memory", -+ "fsl,sec-v5.0-rtic-memory", -+ "fsl,sec-v4.0-rtic-memory"; -+ reg = <0x00 0x20 0x100 0x100>; -+ }; -+ -+ rtic_b: rtic-b@20 { -+ compatible = "fsl,sec-v5.4-rtic-memory", -+ "fsl,sec-v5.0-rtic-memory", -+ "fsl,sec-v4.0-rtic-memory"; -+ reg = <0x20 0x20 0x200 0x100>; -+ }; -+ -+ rtic_c: rtic-c@40 { -+ compatible = "fsl,sec-v5.4-rtic-memory", -+ "fsl,sec-v5.0-rtic-memory", -+ "fsl,sec-v4.0-rtic-memory"; -+ reg = <0x40 0x20 0x300 0x100>; -+ }; -+ -+ rtic_d: rtic-d@60 { -+ compatible = "fsl,sec-v5.4-rtic-memory", -+ "fsl,sec-v5.0-rtic-memory", -+ "fsl,sec-v4.0-rtic-memory"; -+ reg = <0x60 0x20 0x400 0x100>; -+ }; -+ }; -+ }; -+ -+ sec_mon: sec_mon@1e90000 { -+ compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon", -+ "fsl,sec-v4.0-mon"; -+ reg = <0x0 0x1e90000 0x0 0x10000>; -+ interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ dcfg: dcfg@1ee0000 { -+ compatible = "fsl,ls1012a-dcfg", -+ "syscon"; -+ reg = <0x0 0x1ee0000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ clockgen: clocking@1ee1000 { -+ compatible = "fsl,ls1012a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk &coreclk>; -+ clock-names = "sysclk", "coreclk"; -+ }; -+ -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <0 33 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ big-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ thermal-sensors = <&tmu 0>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ esdhc0: esdhc@1560000 { -+ compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x1560000 0x0 0x10000>; -+ interrupts = <0 62 0x4>; -+ clocks = <&clockgen 4 0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ esdhc1: esdhc@1580000 { -+ compatible = "fsl,ls1012a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ interrupts = <0 65 0x4>; -+ clocks = <&clockgen 4 0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ broken-cd; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ rcpm: rcpm@1ee2000 { -+ compatible = "fsl,ls1012a-rcpm", "fsl,qoriq-rcpm-2.1"; -+ reg = <0x0 0x1ee2000 0x0 0x1000>; -+ fsl,#rcpm-wakeup-cells = <1>; -+ }; -+ -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ls1012a-ftm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ }; -+ -+ i2c0: i2c@2180000 { -+ compatible = "fsl,vf610-i2c", "fsl,ls1012a-vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = <0 56 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 3>; -+ fsl-scl-gpio = <&gpio0 13 0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2190000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = <0 57 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 3>; -+ status = "disabled"; -+ }; -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0500 0x0 0x100>; -+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0600 0x0 0x100>; -+ interrupts = <0 54 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 0>; -+ status = "disabled"; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 66 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 67 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1012a-qspi", "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 0>, <&clockgen 4 0>; -+ big-endian; -+ fsl,qspi-has-second-chip; -+ status = "disabled"; -+ }; -+ -+ wdog0: wdog@2ad0000 { -+ compatible = "fsl,ls1012a-wdt", -+ "fsl,imx21-wdt"; -+ reg = <0x0 0x2ad0000 0x0 0x10000>; -+ interrupts = <0 83 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 0>; -+ big-endian; -+ }; -+ -+ sai1: sai@2b50000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,vf610-sai"; -+ reg = <0x0 0x2b50000 0x0 0x10000>; -+ interrupts = <0 148 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>, -+ <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx", "rx"; -+ dmas = <&edma0 1 47>, -+ <&edma0 1 46>; -+ status = "disabled"; -+ }; -+ -+ sai2: sai@2b60000 { -+ #sound-dai-cells = <0>; -+ compatible = "fsl,vf610-sai"; -+ reg = <0x0 0x2b60000 0x0 0x10000>; -+ interrupts = <0 149 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>, -+ <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "bus", "mclk1", "mclk2", "mclk3"; -+ dma-names = "tx", "rx"; -+ dmas = <&edma0 1 45>, -+ <&edma0 1 44>; -+ status = "disabled"; -+ }; -+ -+ edma0: edma@2c00000 { -+ #dma-cells = <2>; -+ compatible = "fsl,vf610-edma"; -+ reg = <0x0 0x2c00000 0x0 0x10000>, -+ <0x0 0x2c10000 0x0 0x10000>, -+ <0x0 0x2c20000 0x0 0x10000>; -+ interrupts = <0 103 IRQ_TYPE_LEVEL_HIGH>, -+ <0 103 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "edma-tx", "edma-err"; -+ dma-channels = <32>; -+ big-endian; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clockgen 4 3>, -+ <&clockgen 4 3>; -+ }; -+ -+ usb0: usb3@2f00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <0 60 0x4>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb2@8600000 { -+ compatible = "fsl-usb2-dr-v2.5", "fsl-usb2-dr"; -+ reg = <0x0 0x8600000 0x0 0x1000>; -+ interrupts = <0 139 0x4>; -+ dr_mode = "host"; -+ phy_type = "ulpi"; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1012a-ahci", "fsl,ls1043a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x0 0x20140520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; -+ interrupts = <0 69 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 0>; -+ dma-coherent; -+ status = "disabled"; -+ }; -+ -+ msi: msi-controller1@1572000 { -+ compatible = "fsl,ls1012a-msi"; -+ reg = <0x0 0x1572000 0x0 0x8>; -+ msi-controller; -+ interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie: pcie@3400000 { -+ compatible = "fsl,ls1012a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>, /* AER interrupt */ -+ <0 117 0x4>; /* PME interrupt */ -+ interrupt-names = "aer", "pme"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 111 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 112 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 113 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ pfe_reserved: packetbuffer@83400000 { -+ reg = <0 0x83400000 0 0xc00000>; -+ }; -+ }; -+ -+ pfe: pfe@04000000 { -+ compatible = "fsl,pfe"; -+ reg = <0x0 0x04000000 0x0 0xc00000>, /* AXI 16M */ -+ <0x0 0x83400000 0x0 0xc00000>; /* PFE DDR 12M */ -+ reg-names = "pfe", "pfe-ddr"; -+ fsl,pfe-num-interfaces = <0x2>; -+ interrupts = <0 172 0x4>, /* HIF interrupt */ -+ <0 173 0x4>, /*HIF_NOCPY interrupt */ -+ <0 174 0x4>; /* WoL interrupt */ -+ interrupt-names = "pfe_hif", "pfe_hif_nocpy", "pfe_wol"; -+ memory-region = <&pfe_reserved>; -+ fsl,pfe-scfg = <&scfg 0>; -+ fsl,rcpm-wakeup = <&rcpm 0xf0000020>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "pfe"; -+ -+ status = "okay"; -+ pfe_mac0: ethernet@0 { -+ }; -+ -+ pfe_mac1: ethernet@1 { -+ }; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043-post.dtsi -@@ -0,0 +1,44 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 device tree nodes for ls1043 -+ * -+ * Copyright 2015-2016 Freescale Semiconductor Inc. -+ */ -+ -+&soc { -+ -+/* include used FMan blocks */ -+#include "qoriq-fman3-0.dtsi" -+#include "qoriq-fman3-0-1g-0.dtsi" -+#include "qoriq-fman3-0-1g-1.dtsi" -+#include "qoriq-fman3-0-1g-2.dtsi" -+#include "qoriq-fman3-0-1g-3.dtsi" -+#include "qoriq-fman3-0-1g-4.dtsi" -+#include "qoriq-fman3-0-1g-5.dtsi" -+#include "qoriq-fman3-0-10g-0.dtsi" -+ -+}; -+ -+&fman0 { -+ /* these aliases provide the FMan ports mapping */ -+ enet0: ethernet@e0000 { -+ }; -+ -+ enet1: ethernet@e2000 { -+ }; -+ -+ enet2: ethernet@e4000 { -+ }; -+ -+ enet3: ethernet@e6000 { -+ }; -+ -+ enet4: ethernet@e8000 { -+ }; -+ -+ enet5: ethernet@ea000 { -+ }; -+ -+ enet6: ethernet@f0000 { -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds-sdk.dts -@@ -0,0 +1,71 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <Mingkai.hu@freescale.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1043a-qds.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-qds.dts -@@ -1,51 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * -- * Copyright 2014-2015, Freescale Semiconductor -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Mingkai Hu <Mingkai.hu@freescale.com> -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - - /dts-v1/; --/include/ "fsl-ls1043a.dtsi" -+#include "fsl-ls1043a.dtsi" - - / { - model = "LS1043A QDS Board"; -@@ -60,6 +23,22 @@ - serial1 = &duart1; - serial2 = &duart2; - serial3 = &duart3; -+ sgmii_riser_s1_p1 = &sgmii_phy_s1_p1; -+ sgmii_riser_s2_p1 = &sgmii_phy_s2_p1; -+ sgmii_riser_s3_p1 = &sgmii_phy_s3_p1; -+ sgmii_riser_s4_p1 = &sgmii_phy_s4_p1; -+ qsgmii_s1_p1 = &qsgmii_phy_s1_p1; -+ qsgmii_s1_p2 = &qsgmii_phy_s1_p2; -+ qsgmii_s1_p3 = &qsgmii_phy_s1_p3; -+ qsgmii_s1_p4 = &qsgmii_phy_s1_p4; -+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1; -+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2; -+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3; -+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4; -+ emi1_slot1 = &ls1043mdio_s1; -+ emi1_slot2 = &ls1043mdio_s2; -+ emi1_slot3 = &ls1043mdio_s3; -+ emi1_slot4 = &ls1043mdio_s4; - }; - - chosen { -@@ -97,8 +76,11 @@ - }; - - fpga: board-control@2,0 { -- compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,ls1043aqds-fpga", "fsl,fpga-qixis", "simple-bus"; - reg = <0x2 0x0 0x0000100>; -+ ranges = <0 2 0 0x100>; - }; - }; - -@@ -181,3 +163,149 @@ - reg = <0>; - }; - }; -+ -+#include "fsl-ls1043-post.dtsi" -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy_s2_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&qsgmii_phy_s2_p2>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&qsgmii_phy_s2_p3>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&qsgmii_phy_s2_p4>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* DTSEC9/10GEC1 */ -+ fixed-link = <1 1 10000 0 0>; -+ phy-connection-type = "xgmii"; -+ }; -+}; -+ -+&fpga { -+ mdio-mux-emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&mdio0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1 */ -+ -+ /* On-board RGMII1 PHY */ -+ ls1043mdio0: mdio@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */ -+ reg = <0x1>; -+ }; -+ }; -+ -+ /* On-board RGMII2 PHY */ -+ ls1043mdio1: mdio@1 { -+ reg = <0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */ -+ reg = <0x2>; -+ }; -+ }; -+ -+ /* Slot 1 */ -+ ls1043mdio_s1: mdio@2 { -+ reg = <0x40>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s1_p1: ethernet-phy@4 { -+ reg = <0x4>; -+ }; -+ qsgmii_phy_s1_p2: ethernet-phy@5 { -+ reg = <0x5>; -+ }; -+ qsgmii_phy_s1_p3: ethernet-phy@6 { -+ reg = <0x6>; -+ }; -+ qsgmii_phy_s1_p4: ethernet-phy@7 { -+ reg = <0x7>; -+ }; -+ -+ sgmii_phy_s1_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 2 */ -+ ls1043mdio_s2: mdio@3 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s2_p1: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ qsgmii_phy_s2_p2: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ qsgmii_phy_s2_p3: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ qsgmii_phy_s2_p4: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ -+ sgmii_phy_s2_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 3 */ -+ ls1043mdio_s3: mdio@4 { -+ reg = <0x80>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s3_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ -+ /* Slot 4 */ -+ ls1043mdio_s4: mdio@5 { -+ reg = <0xa0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s4_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-sdk.dts -@@ -0,0 +1,71 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <Mingkai.hu@freescale.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1043a-rdb.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb-usdpaa.dts -@@ -0,0 +1,117 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1043A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "fsl-ls1043a-rdb-sdk.dts" -+ -+&soc { -+ bp7: buffer-pool@7 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,p4080-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1043a", "fsl,dpaa", "simple-bus"; -+ -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x50 1 0x51 1>; -+ fsl,qman-frame-queues-tx = <0x70 1 0x71 1>; -+ }; -+ -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x52 1 0x53 1>; -+ fsl,qman-frame-queues-tx = <0x72 1 0x73 1>; -+ }; -+ -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x60 1 0x61 1>; -+ fsl,qman-frame-queues-tx = <0x80 1 0x81 1>; -+ }; -+ -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; -+ -+ }; -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* <OH Rx error, OH Rx default> */ -+ fsl,qman-frame-queues-oh = <0x5a 1 0x5b 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-rdb.dts -@@ -1,51 +1,14 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * -- * Copyright 2014-2015, Freescale Semiconductor -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Mingkai Hu <Mingkai.hu@freescale.com> -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - - /dts-v1/; --/include/ "fsl-ls1043a.dtsi" -+#include "fsl-ls1043a.dtsi" - - / { - model = "LS1043A RDB Board"; -@@ -86,6 +49,10 @@ - compatible = "pericom,pt7c4338"; - reg = <0x68>; - }; -+ rtc@51 { -+ compatible = "nxp,pcf85263"; -+ reg = <0x51>; -+ }; - }; - - &ifc { -@@ -130,6 +97,38 @@ - reg = <0>; - spi-max-frequency = <1000000>; /* input clock */ - }; -+ -+ slic@2 { -+ compatible = "maxim,ds26522"; -+ reg = <2>; -+ spi-max-frequency = <2000000>; -+ fsl,spi-cs-sck-delay = <100>; -+ fsl,spi-sck-cs-delay = <50>; -+ }; -+ -+ slic@3 { -+ compatible = "maxim,ds26522"; -+ reg = <3>; -+ spi-max-frequency = <2000000>; -+ fsl,spi-cs-sck-delay = <100>; -+ fsl,spi-sck-cs-delay = <50>; -+ }; -+}; -+ -+&uqe { -+ ucc_hdlc: ucc@2000 { -+ compatible = "fsl,ucc-hdlc"; -+ rx-clock-name = "clk8"; -+ tx-clock-name = "clk9"; -+ fsl,rx-sync-clock = "rsync_pin"; -+ fsl,tx-sync-clock = "tsync_pin"; -+ fsl,tx-timeslot-mask = <0xfffffffe>; -+ fsl,rx-timeslot-mask = <0xfffffffe>; -+ fsl,tdm-framer-type = "e1"; -+ fsl,tdm-id = <0>; -+ fsl,siram-entry-id = <0>; -+ fsl,tdm-interface; -+ }; - }; - - &duart0 { -@@ -139,3 +138,76 @@ - &duart1 { - status = "okay"; - }; -+ -+#include "fsl-ls1043-post.dtsi" -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy1>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&qsgmii_phy2>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii-txid"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii-txid"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&qsgmii_phy3>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&qsgmii_phy4>; -+ phy-connection-type = "qsgmii"; -+ }; -+ -+ ethernet@f0000 { /* 10GEC1 */ -+ phy-handle = <&aqr105_phy>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ mdio@fc000 { -+ rgmii_phy1: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ -+ rgmii_phy2: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ qsgmii_phy1: ethernet-phy@4 { -+ reg = <0x4>; -+ }; -+ -+ qsgmii_phy2: ethernet-phy@5 { -+ reg = <0x5>; -+ }; -+ -+ qsgmii_phy3: ethernet-phy@6 { -+ reg = <0x6>; -+ }; -+ -+ qsgmii_phy4: ethernet-phy@7 { -+ reg = <0x7>; -+ }; -+ }; -+ -+ mdio@fd000 { -+ aqr105_phy: ethernet-phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 132 4>; -+ reg = <0x1>; -+ }; -+ }; -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi -@@ -1,55 +1,32 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree Include file for Freescale Layerscape-1043A family SoC. - * -- * Copyright 2014-2015, Freescale Semiconductor -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Mingkai Hu <Mingkai.hu@freescale.com> -- * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - -+#include <dt-bindings/thermal/thermal.h> -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+ - / { - compatible = "fsl,ls1043a"; - interrupt-parent = <&gic>; - #address-cells = <2>; - #size-cells = <2>; - -+ aliases { -+ fman0 = &fman0; -+ ethernet0 = &enet0; -+ ethernet1 = &enet1; -+ ethernet2 = &enet2; -+ ethernet3 = &enet3; -+ ethernet4 = &enet4; -+ ethernet5 = &enet5; -+ ethernet6 = &enet6; -+ }; -+ - cpus { - #address-cells = <1>; - #size-cells = <0>; -@@ -66,6 +43,8 @@ - reg = <0x0>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu1: cpu@1 { -@@ -74,6 +53,7 @@ - reg = <0x1>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu2: cpu@2 { -@@ -82,6 +62,7 @@ - reg = <0x2>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - cpu3: cpu@3 { -@@ -90,6 +71,7 @@ - reg = <0x3>; - clocks = <&clockgen 1 0>; - next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; - }; - - l2: l2-cache { -@@ -97,12 +79,56 @@ - }; - }; - -+ idle-states { -+ /* -+ * PSCI node is not added default, U-boot will add missing -+ * parts if it determines to use PSCI. -+ */ -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x0>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ - memory@80000000 { - device_type = "memory"; - reg = <0x0 0x80000000 0 0x80000000>; - /* DRAM space 1, size: 2GiB DRAM */ - }; - -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ bman_fbpr: bman-fbpr { -+ compatible = "shared-dma-pool"; -+ size = <0 0x1000000>; -+ alignment = <0 0x1000000>; -+ no-map; -+ }; -+ -+ qman_fqd: qman-fqd { -+ compatible = "shared-dma-pool"; -+ size = <0 0x400000>; -+ alignment = <0 0x400000>; -+ no-map; -+ }; -+ -+ qman_pfdr: qman-pfdr { -+ compatible = "shared-dma-pool"; -+ size = <0 0x2000000>; -+ alignment = <0 0x2000000>; -+ no-map; -+ }; -+ }; -+ - sysclk: sysclk { - compatible = "fixed-clock"; - #clock-cells = <0>; -@@ -149,7 +175,7 @@ - interrupts = <1 9 0xf08>; - }; - -- soc { -+ soc: soc { - compatible = "simple-bus"; - #address-cells = <2>; - #size-cells = <2>; -@@ -213,13 +239,14 @@ - - dcfg: dcfg@1ee0000 { - compatible = "fsl,ls1043a-dcfg", "syscon"; -- reg = <0x0 0x1ee0000 0x0 0x10000>; -+ reg = <0x0 0x1ee0000 0x0 0x1000>; - big-endian; - }; - - ifc: ifc@1530000 { - compatible = "fsl,ifc", "simple-bus"; - reg = <0x0 0x1530000 0x0 0x10000>; -+ big-endian; - interrupts = <0 43 0x4>; - }; - -@@ -255,6 +282,103 @@ - big-endian; - }; - -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <0 33 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 3>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ qman: qman@1880000 { -+ compatible = "fsl,qman"; -+ reg = <0x00 0x1880000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ memory-region = <&qman_fqd &qman_pfdr>; -+ }; -+ -+ bman: bman@1890000 { -+ compatible = "fsl,bman"; -+ reg = <0x00 0x1890000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ memory-region = <&bman_fbpr>; -+ }; -+ -+ bportals: bman-portals@508000000 { -+ ranges = <0x0 0x5 0x08000000 0x8000000>; -+ }; -+ -+ qportals: qman-portals@500000000 { -+ ranges = <0x0 0x5 0x00000000 0x8000000>; -+ }; -+ - dspi0: dspi@2100000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; -@@ -282,7 +406,7 @@ - }; - - i2c0: i2c@2180000 { -- compatible = "fsl,vf610-i2c"; -+ compatible = "fsl,vf610-i2c", "fsl,ls1043a-vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2180000 0x0 0x10000>; -@@ -292,6 +416,7 @@ - dmas = <&edma0 1 39>, - <&edma0 1 38>; - dma-names = "tx", "rx"; -+ fsl-scl-gpio = <&gpio4 12 0>; - status = "disabled"; - }; - -@@ -396,6 +521,72 @@ - #interrupt-cells = <2>; - }; - -+ uqe: uqe@2400000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ device_type = "qe"; -+ compatible = "fsl,qe", "simple-bus"; -+ ranges = <0x0 0x0 0x2400000 0x40000>; -+ reg = <0x0 0x2400000 0x0 0x480>; -+ brg-frequency = <100000000>; -+ bus-frequency = <200000000>; -+ -+ fsl,qe-num-riscs = <1>; -+ fsl,qe-num-snums = <28>; -+ -+ qeic: qeic@80 { -+ compatible = "fsl,qe-ic"; -+ reg = <0x80 0x80>; -+ #address-cells = <0>; -+ interrupt-controller; -+ #interrupt-cells = <1>; -+ interrupts = <0 77 0x04 0 77 0x04>; -+ }; -+ -+ si1: si@700 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,ls1043-qe-si", -+ "fsl,t1040-qe-si"; -+ reg = <0x700 0x80>; -+ }; -+ -+ siram1: siram@1000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,ls1043-qe-siram", -+ "fsl,t1040-qe-siram"; -+ reg = <0x1000 0x800>; -+ }; -+ -+ ucc@2000 { -+ cell-index = <1>; -+ reg = <0x2000 0x200>; -+ interrupts = <32>; -+ interrupt-parent = <&qeic>; -+ }; -+ -+ ucc@2200 { -+ cell-index = <3>; -+ reg = <0x2200 0x200>; -+ interrupts = <34>; -+ interrupt-parent = <&qeic>; -+ }; -+ -+ muram@10000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,qe-muram", "fsl,cpm-muram"; -+ ranges = <0x0 0x10000 0x6000>; -+ -+ data-only@0 { -+ compatible = "fsl,qe-muram-data", -+ "fsl,cpm-muram-data"; -+ reg = <0x0 0x6000>; -+ }; -+ }; -+ }; -+ - lpuart0: serial@2950000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2950000 0x0 0x1000>; -@@ -450,6 +641,16 @@ - status = "disabled"; - }; - -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ls1043a-ftm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = <0 86 0x4>; -+ big-endian; -+ status = "okay"; -+ }; -+ - wdog0: wdog@2ad0000 { - compatible = "fsl,ls1043a-wdt", "fsl,imx21-wdt"; - reg = <0x0 0x2ad0000 0x0 0x10000>; -@@ -482,6 +683,10 @@ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,dma-snooping; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - }; - - usb1: usb3@3000000 { -@@ -491,6 +696,11 @@ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,dma-snooping; -+ configure-gfladj; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - }; - - usb2: usb3@3100000 { -@@ -500,32 +710,54 @@ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,dma-snooping; -+ configure-gfladj; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; - }; - - sata: sata@3200000 { - compatible = "fsl,ls1043a-ahci"; -- reg = <0x0 0x3200000 0x0 0x10000>; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x0 0x20140520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; - interrupts = <0 69 0x4>; - clocks = <&clockgen 4 0>; - dma-coherent; - }; - -+ qdma: qdma@8380000 { -+ compatible = "fsl,ls1021a-qdma", "fsl,ls1043a-qdma"; -+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ -+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */ -+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ -+ interrupts = <0 152 0x4>, -+ <0 39 0x4>; -+ interrupt-names = "qdma-error", "qdma-queue"; -+ channels = <8>; -+ queues = <2>; -+ status-sizes = <64>; -+ queue-sizes = <64 64>; -+ big-endian; -+ }; -+ - msi1: msi-controller1@1571000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1571000 0x0 0x8>; - msi-controller; - interrupts = <0 116 0x4>; - }; - - msi2: msi-controller2@1572000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1572000 0x0 0x8>; - msi-controller; - interrupts = <0 126 0x4>; - }; - - msi3: msi-controller3@1573000 { -- compatible = "fsl,1s1043a-msi"; -+ compatible = "fsl,ls1043a-msi"; - reg = <0x0 0x1573000 0x0 0x8>; - msi-controller; - interrupts = <0 160 0x4>; -@@ -536,9 +768,9 @@ - reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ - 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 118 0x4>, /* controller interrupt */ -- <0 117 0x4>; /* PME interrupt */ -- interrupt-names = "intr", "pme"; -+ interrupts = <0 117 0x4>, /* PME interrupt */ -+ <0 118 0x4>; /* aer interrupt */ -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -547,7 +779,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi1>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, -@@ -561,9 +793,9 @@ - reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ - 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 128 0x4>, -- <0 127 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupts = <0 127 0x4>, -+ <0 128 0x4>; -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -572,7 +804,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi2>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, -@@ -586,9 +818,9 @@ - reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ - 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ - reg-names = "regs", "config"; -- interrupts = <0 162 0x4>, -- <0 161 0x4>; -- interrupt-names = "intr", "pme"; -+ interrupts = <0 161 0x4>, -+ <0 162 0x4>; -+ interrupt-names = "pme", "aer"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; -@@ -597,7 +829,7 @@ - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&msi3>; -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; - #interrupt-cells = <1>; - interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, -@@ -607,4 +839,13 @@ - }; - }; - -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; - }; -+ -+#include "qoriq-qman-portals.dtsi" -+#include "qoriq-bman-portals.dtsi" ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046-post.dtsi -@@ -0,0 +1,48 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 device tree nodes for ls1046 -+ * -+ * Copyright 2015-2016 Freescale Semiconductor Inc. -+ * -+ */ -+ -+&soc { -+ -+/* include used FMan blocks */ -+#include "qoriq-fman3-0.dtsi" -+#include "qoriq-fman3-0-1g-0.dtsi" -+#include "qoriq-fman3-0-1g-1.dtsi" -+#include "qoriq-fman3-0-1g-2.dtsi" -+#include "qoriq-fman3-0-1g-3.dtsi" -+#include "qoriq-fman3-0-1g-4.dtsi" -+#include "qoriq-fman3-0-1g-5.dtsi" -+#include "qoriq-fman3-0-10g-0.dtsi" -+#include "qoriq-fman3-0-10g-1.dtsi" -+}; -+ -+&fman0 { -+ /* these aliases provide the FMan ports mapping */ -+ enet0: ethernet@e0000 { -+ }; -+ -+ enet1: ethernet@e2000 { -+ }; -+ -+ enet2: ethernet@e4000 { -+ }; -+ -+ enet3: ethernet@e6000 { -+ }; -+ -+ enet4: ethernet@e8000 { -+ }; -+ -+ enet5: ethernet@ea000 { -+ }; -+ -+ enet6: ethernet@f0000 { -+ }; -+ -+ enet7: ethernet@f2000 { -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds-sdk.dts -@@ -0,0 +1,112 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <Mingkai.hu@freescale.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1046a-qds.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+}; -+ -+&fsldpaa { -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet7>; -+ dma-coherent; -+ }; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; -+ -+&dspi { -+ bus-num = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "n25q128a11", "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "sst25wf040b", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <1>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "en25s64", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <2>; -+ spi-max-frequency = <10000000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-qds.dts -@@ -0,0 +1,326 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * Shaohui Xie <Shaohui.Xie@nxp.com> -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls1046a.dtsi" -+ -+/ { -+ model = "LS1046A QDS Board"; -+ compatible = "fsl,ls1046a-qds", "fsl,ls1046a"; -+ -+ aliases { -+ gpio0 = &gpio0; -+ gpio1 = &gpio1; -+ gpio2 = &gpio2; -+ gpio3 = &gpio3; -+ serial0 = &duart0; -+ serial1 = &duart1; -+ serial2 = &duart2; -+ serial3 = &duart3; -+ -+ emi1_slot1 = &ls1046mdio_s1; -+ emi1_slot2 = &ls1046mdio_s2; -+ emi1_slot4 = &ls1046mdio_s4; -+ -+ sgmii_s1_p1 = &sgmii_phy_s1_p1; -+ sgmii_s1_p2 = &sgmii_phy_s1_p2; -+ sgmii_s1_p3 = &sgmii_phy_s1_p3; -+ sgmii_s1_p4 = &sgmii_phy_s1_p4; -+ sgmii_s4_p1 = &sgmii_phy_s4_p1; -+ qsgmii_s2_p1 = &qsgmii_phy_s2_p1; -+ qsgmii_s2_p2 = &qsgmii_phy_s2_p2; -+ qsgmii_s2_p3 = &qsgmii_phy_s2_p3; -+ qsgmii_s2_p4 = &qsgmii_phy_s2_p4; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&dspi { -+ bus-num = <0>; -+ status = "okay"; -+ -+ flash@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "n25q128a11", "jedec,spi-nor"; -+ reg = <0>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "sst25wf040b", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <1>; -+ spi-max-frequency = <10000000>; -+ }; -+ -+ flash@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "en25s64", "jedec,spi-nor"; -+ spi-cpol; -+ spi-cpha; -+ reg = <2>; -+ spi-max-frequency = <10000000>; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ pca9547@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ -+ ina220@41 { -+ compatible = "ti,ina220"; -+ reg = <0x41>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ /* IRQ10_B */ -+ interrupts = <0 150 0x4>; -+ }; -+ -+ eeprom@56 { -+ compatible = "atmel,24c512"; -+ reg = <0x56>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c512"; -+ reg = <0x57>; -+ }; -+ -+ temp-sensor@4c { -+ compatible = "adi,adt7461a"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&ifc { -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* NOR, NAND Flashes and FPGA on board */ -+ ranges = <0x0 0x0 0x0 0x60000000 0x08000000 -+ 0x1 0x0 0x0 0x7e800000 0x00010000 -+ 0x2 0x0 0x0 0x7fb00000 0x00000100>; -+ status = "okay"; -+ -+ nor@0,0 { -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@1,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x1 0x0 0x10000>; -+ }; -+ -+ fpga: board-control@2,0 { -+ compatible = "fsl,ls1046aqds-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <0x2 0x0 0x0000100>; -+ ranges = <0 2 0 0x100>; -+ }; -+}; -+ -+&lpuart0 { -+ status = "okay"; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fl128s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+#include "fsl-ls1046-post.dtsi" -+ -+&fman0 { -+ ethernet@e0000 { -+ phy-handle = <&qsgmii_phy_s2_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e2000 { -+ phy-handle = <&sgmii_phy_s4_p1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&sgmii_phy_s1_p3>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&sgmii_phy_s1_p4>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* DTSEC9/10GEC1 */ -+ phy-handle = <&sgmii_phy_s1_p1>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ ethernet@f2000 { /* DTSEC10/10GEC2 */ -+ phy-handle = <&sgmii_phy_s1_p2>; -+ phy-connection-type = "xgmii"; -+ }; -+}; -+ -+&fpga { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ mdio-mux-emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&mdio0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1 */ -+ -+ /* On-board RGMII1 PHY */ -+ ls1046mdio0: mdio@0 { -+ reg = <0>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy1: ethernet-phy@1 { /* MAC3 */ -+ reg = <0x1>; -+ }; -+ }; -+ -+ /* On-board RGMII2 PHY */ -+ ls1046mdio1: mdio@1 { -+ reg = <0x20>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ rgmii_phy2: ethernet-phy@2 { /* MAC4 */ -+ reg = <0x2>; -+ }; -+ }; -+ -+ /* Slot 1 */ -+ ls1046mdio_s1: mdio@2 { -+ reg = <0x40>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s1_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ -+ sgmii_phy_s1_p2: ethernet-phy@1d { -+ reg = <0x1d>; -+ }; -+ -+ sgmii_phy_s1_p3: ethernet-phy@1e { -+ reg = <0x1e>; -+ }; -+ -+ sgmii_phy_s1_p4: ethernet-phy@1f { -+ reg = <0x1f>; -+ }; -+ }; -+ -+ /* Slot 2 */ -+ ls1046mdio_s2: mdio@3 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ qsgmii_phy_s2_p1: ethernet-phy@8 { -+ reg = <0x8>; -+ }; -+ qsgmii_phy_s2_p2: ethernet-phy@9 { -+ reg = <0x9>; -+ }; -+ qsgmii_phy_s2_p3: ethernet-phy@a { -+ reg = <0xa>; -+ }; -+ qsgmii_phy_s2_p4: ethernet-phy@b { -+ reg = <0xb>; -+ }; -+ }; -+ -+ /* Slot 4 */ -+ ls1046mdio_s4: mdio@5 { -+ reg = <0x80>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ status = "disabled"; -+ -+ sgmii_phy_s4_p1: ethernet-phy@1c { -+ reg = <0x1c>; -+ }; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-sdk.dts -@@ -0,0 +1,85 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <Mingkai.hu@freescale.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include "fsl-ls1046a-rdb.dts" -+#include "qoriq-qman-portals-sdk.dtsi" -+#include "qoriq-bman-portals-sdk.dtsi" -+ -+&bman_fbpr { -+ compatible = "fsl,bman-fbpr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_fqd { -+ compatible = "fsl,qman-fqd"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+&qman_pfdr { -+ compatible = "fsl,qman-pfdr"; -+ alloc-ranges = <0 0 0x10000 0>; -+}; -+ -+&soc { -+#include "qoriq-dpaa-eth.dtsi" -+#include "qoriq-fman3-0-6oh.dtsi" -+}; -+ -+&fsldpaa { -+ ethernet@0 { -+ status = "disabled"; -+ }; -+ ethernet@1 { -+ status = "disabled"; -+ }; -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet7>; -+ dma-coherent; -+ }; -+}; -+ -+&fman0 { -+ compatible = "fsl,fman", "simple-bus"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb-usdpaa.dts -@@ -0,0 +1,110 @@ -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * This file is licensed under the terms of the GNU General Public -+ * License version 2. This program is licensed "as is" without any -+ * warranty of any kind, whether express or implied. -+ */ -+ -+#include "fsl-ls1046a-rdb-sdk.dts" -+ -+&soc { -+ bp7: buffer-pool@7 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <7>; -+ fsl,bpool-ethernet-cfg = <0 0 0 192 0 0xdeadbeef>; -+ fsl,bpool-thresholds = <0x400 0xc00 0x0 0x0>; -+ }; -+ -+ bp8: buffer-pool@8 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <8>; -+ fsl,bpool-ethernet-cfg = <0 0 0 576 0 0xabbaf00d>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ }; -+ -+ bp9: buffer-pool@9 { -+ compatible = "fsl,ls1046a-bpool", "fsl,bpool"; -+ fsl,bpid = <9>; -+ fsl,bpool-ethernet-cfg = <0 0 0 2048 0 0xfeedabba>; -+ fsl,bpool-thresholds = <0x100 0x300 0x0 0x0>; -+ }; -+ -+ fsl,dpaa { -+ compatible = "fsl,ls1046a", "fsl,dpaa", "simple-bus"; -+ -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x54 1 0x55 1>; -+ fsl,qman-frame-queues-tx = <0x74 1 0x75 1>; -+ }; -+ -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x56 1 0x57 1>; -+ fsl,qman-frame-queues-tx = <0x76 1 0x77 1>; -+ }; -+ -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x58 1 0x59 1>; -+ fsl,qman-frame-queues-tx = <0x78 1 0x79 1>; -+ }; -+ -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5a 1 0x5b 1>; -+ fsl,qman-frame-queues-tx = <0x7a 1 0x7b 1>; -+ }; -+ -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5c 1 0x5d 1>; -+ fsl,qman-frame-queues-tx = <0x7c 1 0x7d 1>; -+ }; -+ -+ ethernet@9 { -+ compatible = "fsl,dpa-ethernet-init"; -+ fsl,bman-buffer-pools = <&bp7 &bp8 &bp9>; -+ fsl,qman-frame-queues-rx = <0x5e 1 0x5f 1>; -+ fsl,qman-frame-queues-tx = <0x7e 1 0x7f 1>; -+ }; -+ -+ dpa-fman0-oh@2 { -+ compatible = "fsl,dpa-oh"; -+ /* Define frame queues for the OH port*/ -+ /* <OH Rx error, OH Rx default> */ -+ fsl,qman-frame-queues-oh = <0x60 1 0x61 1>; -+ fsl,fman-oh-port = <&fman0_oh2>; -+ }; -+ }; -+}; -+/ { -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ usdpaa_mem: usdpaa_mem { -+ compatible = "fsl,usdpaa-mem"; -+ alloc-ranges = <0 0 0x10000 0>; -+ size = <0 0x10000000>; -+ alignment = <0 0x10000000>; -+ }; -+ }; -+}; -+ -+&fman0 { -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-rdb.dts -@@ -0,0 +1,181 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <mingkai.hu@nxp.com> -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls1046a.dtsi" -+ -+/ { -+ model = "LS1046A RDB Board"; -+ compatible = "fsl,ls1046a-rdb", "fsl,ls1046a"; -+ -+ aliases { -+ serial0 = &duart0; -+ serial1 = &duart1; -+ serial2 = &duart2; -+ serial3 = &duart3; -+ }; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&esdhc { -+ mmc-hs200-1_8v; -+ sd-uhs-sdr104; -+ sd-uhs-sdr50; -+ sd-uhs-sdr25; -+ sd-uhs-sdr12; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ -+ temp-sensor@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ -+ eeprom@56 { -+ compatible = "atmel,24c512"; -+ reg = <0x52>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c512"; -+ reg = <0x53>; -+ }; -+}; -+ -+&i2c3 { -+ status = "okay"; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ }; -+}; -+ -+&ifc { -+ #address-cells = <2>; -+ #size-cells = <1>; -+ /* NAND Flashe and CPLD on board */ -+ ranges = <0x0 0x0 0x0 0x7e800000 0x00010000 -+ 0x2 0x0 0x0 0x7fb00000 0x00000100>; -+ status = "okay"; -+ -+ nand@0,0 { -+ compatible = "fsl,ifc-nand"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ reg = <0x0 0x0 0x10000>; -+ }; -+ -+ cpld: board-control@2,0 { -+ compatible = "fsl,ls1046ardb-cpld"; -+ reg = <0x2 0x0 0x0000100>; -+ }; -+}; -+ -+&qspi { -+ num-cs = <2>; -+ bus-num = <0>; -+ status = "okay"; -+ -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ -+ qflash1: s25fs512s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+}; -+ -+#include "fsl-ls1046-post.dtsi" -+ -+&fman0 { -+ ethernet@e4000 { -+ phy-handle = <&rgmii_phy1>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e6000 { -+ phy-handle = <&rgmii_phy2>; -+ phy-connection-type = "rgmii"; -+ }; -+ -+ ethernet@e8000 { -+ phy-handle = <&sgmii_phy1>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@ea000 { -+ phy-handle = <&sgmii_phy2>; -+ phy-connection-type = "sgmii"; -+ }; -+ -+ ethernet@f0000 { /* 10GEC1 */ -+ phy-handle = <&aqr106_phy>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ ethernet@f2000 { /* 10GEC2 */ -+ fixed-link = <0 1 1000 0 0>; -+ phy-connection-type = "xgmii"; -+ }; -+ -+ mdio@fc000 { -+ rgmii_phy1: ethernet-phy@1 { -+ reg = <0x1>; -+ }; -+ -+ rgmii_phy2: ethernet-phy@2 { -+ reg = <0x2>; -+ }; -+ -+ sgmii_phy1: ethernet-phy@3 { -+ reg = <0x3>; -+ }; -+ -+ sgmii_phy2: ethernet-phy@4 { -+ reg = <0x4>; -+ }; -+ }; -+ -+ mdio@fd000 { -+ aqr106_phy: ethernet-phy@0 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 131 4>; -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi -@@ -0,0 +1,771 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-1046A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * -+ * Mingkai Hu <mingkai.hu@nxp.com> -+ */ -+ -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+#include <dt-bindings/thermal/thermal.h> -+ -+/ { -+ compatible = "fsl,ls1046a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ crypto = &crypto; -+ fman0 = &fman0; -+ ethernet0 = &enet0; -+ ethernet1 = &enet1; -+ ethernet2 = &enet2; -+ ethernet3 = &enet3; -+ ethernet4 = &enet4; -+ ethernet5 = &enet5; -+ ethernet6 = &enet6; -+ ethernet7 = &enet7; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x1>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x2>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x3>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ l2: l2-cache { -+ compatible = "cache"; -+ }; -+ }; -+ -+ idle-states { -+ /* -+ * PSCI node is not added default, U-boot will add missing -+ * parts if it determines to use PSCI. -+ */ -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x0>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ reboot { -+ compatible ="syscon-reboot"; -+ regmap = <&dcfg>; -+ offset = <0xb0>; -+ mask = <0x02>; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(0xf) | -+ IRQ_TYPE_LEVEL_LOW)>, -+ <GIC_PPI 14 (GIC_CPU_MASK_RAW(0xf) | -+ IRQ_TYPE_LEVEL_LOW)>, -+ <GIC_PPI 11 (GIC_CPU_MASK_RAW(0xf) | -+ IRQ_TYPE_LEVEL_LOW)>, -+ <GIC_PPI 10 (GIC_CPU_MASK_RAW(0xf) | -+ IRQ_TYPE_LEVEL_LOW)>; -+ }; -+ -+ pmu { -+ compatible = "arm,cortex-a72-pmu"; -+ interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-affinity = <&cpu0>, -+ <&cpu1>, -+ <&cpu2>, -+ <&cpu3>; -+ }; -+ -+ gic: interrupt-controller@1400000 { -+ compatible = "arm,gic-400"; -+ #interrupt-cells = <3>; -+ interrupt-controller; -+ reg = <0x0 0x1410000 0 0x10000>, /* GICD */ -+ <0x0 0x1420000 0 0x20000>, /* GICC */ -+ <0x0 0x1440000 0 0x20000>, /* GICH */ -+ <0x0 0x1460000 0 0x20000>; /* GICV */ -+ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | -+ IRQ_TYPE_LEVEL_LOW)>; -+ }; -+ -+ soc: soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ ddr: memory-controller@1080000 { -+ compatible = "fsl,qoriq-memory-controller"; -+ reg = <0x0 0x1080000 0x0 0x1000>; -+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; -+ }; -+ -+ ifc: ifc@1530000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x1530000 0x0 0x10000>; -+ big-endian; -+ interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ qspi: quadspi@1550000 { -+ compatible = "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x1550000 0x0 0x10000>, -+ <0x0 0x40000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>; -+ clock-names = "qspi_en", "qspi"; -+ clocks = <&clockgen 4 1>, <&clockgen 4 1>; -+ big-endian; -+ fsl,qspi-has-second-chip; -+ status = "disabled"; -+ }; -+ -+ esdhc: esdhc@1560000 { -+ compatible = "fsl,ls1046a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x1560000 0x0 0x10000>; -+ interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 2 1>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ big-endian; -+ bus-width = <4>; -+ }; -+ -+ scfg: scfg@1570000 { -+ compatible = "fsl,ls1046a-scfg", "syscon"; -+ reg = <0x0 0x1570000 0x0 0x10000>; -+ big-endian; -+ }; -+ -+ crypto: crypto@1700000 { -+ compatible = "fsl,sec-v5.4", "fsl,sec-v5.0", -+ "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x1700000 0x100000>; -+ reg = <0x00 0x1700000 0x0 0x100000>; -+ interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.4-job-ring", -+ "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ -+ qman: qman@1880000 { -+ compatible = "fsl,qman"; -+ reg = <0x00 0x1880000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ memory-region = <&qman_fqd &qman_pfdr>; -+ -+ }; -+ -+ bman: bman@1890000 { -+ compatible = "fsl,bman"; -+ reg = <0x00 0x1890000 0x0 0x10000>; -+ interrupts = <0 45 0x4>; -+ memory-region = <&bman_fbpr>; -+ -+ }; -+ -+ qportals: qman-portals@500000000 { -+ ranges = <0x0 0x5 0x00000000 0x8000000>; -+ }; -+ -+ bportals: bman-portals@508000000 { -+ ranges = <0x0 0x5 0x08000000 0x8000000>; -+ }; -+ -+ dcfg: dcfg@1ee0000 { -+ compatible = "fsl,ls1046a-dcfg", "syscon"; -+ reg = <0x0 0x1ee0000 0x0 0x1000>; -+ big-endian; -+ }; -+ -+ clockgen: clocking@1ee1000 { -+ compatible = "fsl,ls1046a-clockgen"; -+ reg = <0x0 0x1ee1000 0x0 0x1000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ tmu: tmu@1f00000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f00000 0x0 0x10000>; -+ interrupts = <0 33 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = -+ /* Calibration data group 1 */ -+ <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ /* Calibration data group 2 */ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ /* Calibration data group 3 */ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ /* Calibration data group 4 */ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ big-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ thermal-sensors = <&tmu 3>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ dspi: dspi@2100000 { -+ compatible = "fsl,ls1021a-v1.0-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; -+ clock-names = "dspi"; -+ clocks = <&clockgen 4 1>; -+ spi-num-chipselects = <5>; -+ big-endian; -+ status = "disabled"; -+ }; -+ -+ i2c0: i2c@2180000 { -+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2180000 0x0 0x10000>; -+ interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ dmas = <&edma0 1 39>, -+ <&edma0 1 38>; -+ dma-names = "tx", "rx"; -+ fsl-scl-gpio = <&gpio3 12 0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2190000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2190000 0x0 0x10000>; -+ interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@21a0000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21a0000 0x0 0x10000>; -+ interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@21b0000 { -+ compatible = "fsl,vf610-i2c", "fsl,ls1046a-vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x21b0000 0x0 0x10000>; -+ interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ fsl-scl-gpio = <&gpio3 12 0>; -+ status = "disabled"; -+ }; -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0500 0x0 0x100>; -+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x00 0x21c0600 0x0 0x100>; -+ interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart2: serial@21d0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0500 0x0 0x100>; -+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ duart3: serial@21d0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21d0600 0x0 0x100>; -+ interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ lpuart0: serial@2950000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2950000 0x0 0x1000>; -+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 0>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart1: serial@2960000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2960000 0x0 0x1000>; -+ interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart2: serial@2970000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2970000 0x0 0x1000>; -+ interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart3: serial@2980000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2980000 0x0 0x1000>; -+ interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart4: serial@2990000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x2990000 0x0 0x1000>; -+ interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ lpuart5: serial@29a0000 { -+ compatible = "fsl,ls1021a-lpuart"; -+ reg = <0x0 0x29a0000 0x0 0x1000>; -+ interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ clock-names = "ipg"; -+ status = "disabled"; -+ }; -+ -+ ftm0: ftm0@29d0000 { -+ compatible = "fsl,ls1046a-ftm"; -+ reg = <0x0 0x29d0000 0x0 0x10000>, -+ <0x0 0x1ee2140 0x0 0x4>; -+ reg-names = "ftm", "FlexTimer1"; -+ interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; -+ big-endian; -+ }; -+ -+ wdog0: watchdog@2ad0000 { -+ compatible = "fsl,imx21-wdt"; -+ reg = <0x0 0x2ad0000 0x0 0x10000>; -+ interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ big-endian; -+ }; -+ -+ edma0: edma@2c00000 { -+ #dma-cells = <2>; -+ compatible = "fsl,vf610-edma"; -+ reg = <0x0 0x2c00000 0x0 0x10000>, -+ <0x0 0x2c10000 0x0 0x10000>, -+ <0x0 0x2c20000 0x0 0x10000>; -+ interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "edma-tx", "edma-err"; -+ dma-channels = <32>; -+ big-endian; -+ clock-names = "dmamux0", "dmamux1"; -+ clocks = <&clockgen 4 1>, -+ <&clockgen 4 1>; -+ }; -+ -+ usb0: usb@2f00000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x2f00000 0x0 0x10000>; -+ interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ }; -+ -+ usb1: usb@3000000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3000000 0x0 0x10000>; -+ interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ }; -+ -+ usb2: usb@3100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ usb3-lpm-capable; -+ snps,dis-u1u2-when-u3-quirk; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1046a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x0 0x20140520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; -+ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 1>; -+ dma-coherent; -+ }; -+ -+ qdma: qdma@8380000 { -+ compatible = "fsl,ls1046a-qdma", "fsl,ls1021a-qdma"; -+ reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ -+ <0x0 0x8390000 0x0 0x10000>, /* Status regs */ -+ <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ -+ interrupts = <0 153 0x4>, -+ <0 39 0x4>; -+ interrupt-names = "qdma-error", "qdma-queue"; -+ channels = <8>; -+ queues = <2>; -+ status-sizes = <64>; -+ queue-sizes = <64 64>; -+ big-endian; -+ }; -+ -+ msi1: msi-controller@1580000 { -+ compatible = "fsl,ls1046a-msi"; -+ msi-controller; -+ reg = <0x0 0x1580000 0x0 0x10000>; -+ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ msi2: msi-controller@1590000 { -+ compatible = "fsl,ls1046a-msi"; -+ msi-controller; -+ reg = <0x0 0x1590000 0x0 0x10000>; -+ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ msi3: msi-controller@15a0000 { -+ compatible = "fsl,ls1046a-msi"; -+ msi-controller; -+ reg = <0x0 0x15a0000 0x0 0x10000>; -+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x40 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ -+ <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "pme", "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3500000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x48 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "pme", "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3600000 { -+ compatible = "fsl,ls1046a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x50 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, -+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; -+ interrupt-names = "pme", "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <2>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&msi1>, <&msi2>, <&msi3>; -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ }; -+ -+ reserved-memory { -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ -+ bman_fbpr: bman-fbpr { -+ compatible = "shared-dma-pool"; -+ size = <0 0x1000000>; -+ alignment = <0 0x1000000>; -+ no-map; -+ }; -+ qman_fqd: qman-fqd { -+ compatible = "shared-dma-pool"; -+ size = <0 0x800000>; -+ alignment = <0 0x800000>; -+ no-map; -+ }; -+ qman_pfdr: qman-pfdr { -+ compatible = "shared-dma-pool"; -+ size = <0 0x2000000>; -+ alignment = <0 0x2000000>; -+ no-map; -+ }; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+}; -+ -+#include "qoriq-qman-portals.dtsi" -+#include "qoriq-bman-portals.dtsi" ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-qds.dts -@@ -0,0 +1,137 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for NXP LS1088A QDS Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Harninder Rai <harninder.rai@nxp.com> -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls1088a.dtsi" -+ -+/ { -+ model = "LS1088A QDS Board"; -+ compatible = "fsl,ls1088a-qds", "fsl,ls1088a"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ i2c-switch@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ -+ ina220@41 { -+ compatible = "ti,ina220"; -+ reg = <0x41>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ temp-sensor@4c { -+ compatible = "adi,adt7461a"; -+ reg = <0x4c>; -+ }; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ /* IRQ10_B */ -+ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ eeprom@56 { -+ compatible = "atmel,24c512"; -+ reg = <0x56>; -+ }; -+ -+ eeprom@57 { -+ compatible = "atmel,24c512"; -+ reg = <0x57>; -+ }; -+ }; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <0>; -+ }; -+ -+ qflash1: s25fs512s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ spi-max-frequency = <20000000>; -+ m25p,fast-read; -+ reg = <1>; -+ }; -+}; -+ -+&ifc { -+ status = "okay"; -+ -+ ranges = <0 0 0x5 0x80000000 0x08000000 -+ 2 0 0x5 0x30000000 0x00010000 -+ 3 0 0x5 0x20000000 0x00010000>; -+ -+ nor@0,0 { -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ -+ fpga: board-control@3,0 { -+ compatible = "fsl,ls1088aqds-fpga", "fsl,fpga-qixis"; -+ reg = <0x3 0x0 0x0000100>; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&sata { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-rdb.dts -@@ -0,0 +1,200 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for NXP LS1088A RDB Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Harninder Rai <harninder.rai@nxp.com> -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls1088a.dtsi" -+ -+/ { -+ model = "L1088A RDB Board"; -+ compatible = "fsl,ls1088a-rdb", "fsl,ls1088a"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ -+ i2c-switch@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x2>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ temp-sensor@4c { -+ compatible = "adi,adt7461a"; -+ reg = <0x4c>; -+ }; -+ -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ /* IRQ10_B */ -+ interrupts = <0 150 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ qflash0: s25fs512s@0 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ -+ qflash1: s25fs512s@1 { -+ compatible = "spansion,m25p80"; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+}; -+ -+&ifc { -+ status = "okay"; -+ -+ ranges = <0 0 0x5 0x30000000 0x00010000 -+ 2 0 0x5 0x20000000 0x00010000>; -+ -+ nand@0,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x0 0x0 0x10000>; -+ }; -+ -+ fpga: board-control@2,0 { -+ compatible = "fsl,ls1088ardb-fpga", "fsl,fpga-qixis"; -+ reg = <0x2 0x0 0x0000100>; -+ }; -+}; -+ -+&duart0 { -+ status = "okay"; -+}; -+ -+&duart1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&sata { -+ status = "okay"; -+}; -+ -+&emdio1 { -+ /* Freescale F104 PHY1 */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x1c>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x1d>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x1e>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x1f>; -+ phy-connection-type = "qsgmii"; -+ }; -+ /* F104 PHY2 */ -+ mdio1_phy5: emdio1_phy@5 { -+ reg = <0x0c>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy6: emdio1_phy@6 { -+ reg = <0x0d>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy7: emdio1_phy@7 { -+ reg = <0x0e>; -+ phy-connection-type = "qsgmii"; -+ }; -+ mdio1_phy8: emdio1_phy@8 { -+ reg = <0x0f>; -+ phy-connection-type = "qsgmii"; -+ }; -+}; -+ -+&emdio2 { -+ /* Aquantia AQR105 10G PHY */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 2 0x4>; -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+/* DPMAC connections to external PHYs -+ * based on LS1088A RM RevC - $24.1.2 SerDes Options -+ */ -+/* DPMAC1 is 10G SFP+, fixed link */ -+&dpmac2 { -+ phy-handle = <&mdio2_phy1>; -+}; -+&dpmac3 { -+ phy-handle = <&mdio1_phy5>; -+}; -+&dpmac4 { -+ phy-handle = <&mdio1_phy6>; -+}; -+&dpmac5 { -+ phy-handle = <&mdio1_phy7>; -+}; -+&dpmac6 { -+ phy-handle = <&mdio1_phy8>; -+}; -+&dpmac7 { -+ phy-handle = <&mdio1_phy1>; -+}; -+&dpmac8 { -+ phy-handle = <&mdio1_phy2>; -+}; -+&dpmac9 { -+ phy-handle = <&mdio1_phy3>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio1_phy4>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi -@@ -0,0 +1,800 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for NXP Layerscape-1088A family SoC. -+ * -+ * Copyright 2017 NXP -+ * -+ * Harninder Rai <harninder.rai@nxp.com> -+ * -+ */ -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+#include <dt-bindings/thermal/thermal.h> -+ -+/ { -+ compatible = "fsl,ls1088a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ crypto = &crypto; -+ }; -+ -+ cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ /* We have 2 clusters having 4 Cortex-A53 cores each */ -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x1>; -+ clocks = <&clockgen 1 0>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu2: cpu@2 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x2>; -+ clocks = <&clockgen 1 0>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu3: cpu@3 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x3>; -+ clocks = <&clockgen 1 0>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu4: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x100>; -+ clocks = <&clockgen 1 1>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu5: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x101>; -+ clocks = <&clockgen 1 1>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu6: cpu@102 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x102>; -+ clocks = <&clockgen 1 1>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu7: cpu@103 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a53"; -+ reg = <0x103>; -+ clocks = <&clockgen 1 1>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ }; -+ -+ idle-states { -+ /* -+ * PSCI node is not added default, U-boot will add missing -+ * parts if it determines to use PSCI. -+ */ -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x0>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ -+ gic: interrupt-controller@6000000 { -+ compatible = "arm,gic-v3"; -+ #interrupt-cells = <3>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ interrupt-controller; -+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/ -+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ -+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ -+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ -+ interrupts = <1 9 IRQ_TYPE_LEVEL_HIGH>; -+ -+ its: gic-its@6020000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ reg = <0x0 0x6020000 0 0x20000>; -+ }; -+ }; -+ -+ timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 IRQ_TYPE_LEVEL_LOW>,/* Physical Secure PPI */ -+ <1 14 IRQ_TYPE_LEVEL_LOW>,/* Physical Non-Secure PPI */ -+ <1 11 IRQ_TYPE_LEVEL_LOW>,/* Virtual PPI */ -+ <1 10 IRQ_TYPE_LEVEL_LOW>;/* Hypervisor PPI */ -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ dcfg: dcfg@1e00000 { -+ compatible = "fsl,ls1088a-dcfg", "syscon"; -+ reg = <0x0 0x1e00000 0x0 0x10000>; -+ little-endian; -+ }; -+ -+ rstcr: syscon@1e60000 { -+ compatible = "fsl,ls1088a-rstcr", "syscon"; -+ reg = <0x0 0x1e60000 0x0 0x4>; -+ }; -+ -+ reboot { -+ compatible = "syscon-reboot"; -+ regmap = <&rstcr>; -+ offset = <0x0>; -+ mask = <0x02>; -+ }; -+ -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; -+ -+ clockgen: clocking@1300000 { -+ compatible = "fsl,ls1088a-clockgen"; -+ reg = <0 0x1300000 0 0xa0000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ tmu: tmu@1f80000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f80000 0x0 0x10000>; -+ interrupts = <0 23 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = -+ /* Calibration data group 1 */ -+ <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ /* Calibration data group 2 */ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ /* Calibration data group 3 */ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ /* Calibration data group 4 */ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ little-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ thermal-sensors = <&tmu 0>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ -+ cpu_crit: cpu-crit { -+ temperature = <95000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map1 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu4 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ duart0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0500 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ duart1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0600 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 IRQ_TYPE_LEVEL_HIGH>; -+ status = "disabled"; -+ }; -+ -+ cluster1_core0_watchdog: wdt@c000000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc000000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster1_core1_watchdog: wdt@c010000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc010000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster1_core2_watchdog: wdt@c020000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc020000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster1_core3_watchdog: wdt@c030000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc030000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core0_watchdog: wdt@c100000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc100000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core1_watchdog: wdt@c110000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc110000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core2_watchdog: wdt@c120000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc120000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core3_watchdog: wdt@c130000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc130000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 36 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 37 IRQ_TYPE_LEVEL_HIGH>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ /* TODO: WRIOP (CCSR?) */ -+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, -+ * E-MDIO1: 0x1_6000 -+ */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B96000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; /* force the driver in LE mode */ -+ -+ /* Not necessary on the QDS, but needed on the RDB */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, -+ * E-MDIO2: 0x1_7000 -+ */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B97000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; /* force the driver in LE mode */ -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ ifc: ifc@2240000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x2240000 0x0 0x20000>; -+ interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>; -+ little-endian; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ -+ }; -+ -+ ftm0: ftm0@2800000 { -+ compatible = "fsl,ls1088a-ftm"; -+ reg = <0x0 0x2800000 0x0 0x10000>, -+ <0x0 0x1e34050 0x0 0x4>; -+ interrupts = <0 44 4>; -+ reg-names = "ftm", "FlexTimer1"; -+ }; -+ -+ i2c0: i2c@2000000 { -+ compatible = "fsl,vf610-i2c", "fsl,ls1088a-vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2000000 0x0 0x10000>; -+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 7>; -+ fsl-scl-gpio = <&gpio3 30 0>; -+ status = "disabled"; -+ }; -+ -+ i2c1: i2c@2010000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2010000 0x0 0x10000>; -+ interrupts = <0 34 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 7>; -+ status = "disabled"; -+ }; -+ -+ i2c2: i2c@2020000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2020000 0x0 0x10000>; -+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 7>; -+ status = "disabled"; -+ }; -+ -+ i2c3: i2c@2030000 { -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2030000 0x0 0x10000>; -+ interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 7>; -+ status = "disabled"; -+ }; -+ -+ qspi: quadspi@20c0000 { -+ compatible = "fsl,ls2080a-qspi", "fsl,ls1088a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20c0000 0x0 0x10000>, -+ <0x0 0x20000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 25 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "qspi_en", "qspi"; -+ fsl,qspi-has-second-chip; -+ }; -+ -+ esdhc: esdhc@2140000 { -+ compatible = "fsl,ls1088a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x2140000 0x0 0x10000>; -+ interrupts = <0 28 0x4>; /* Level high type */ -+ clock-frequency = <0>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ little-endian; -+ bus-width = <4>; -+ status = "disabled"; -+ }; -+ -+ usb0: usb3@3100000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 80 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb3@3110000 { -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3110000 0x0 0x10000>; -+ interrupts = <0 81 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ configure-gfladj; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ sata: sata@3200000 { -+ compatible = "fsl,ls1088a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>, -+ <0x7 0x100520 0x0 0x4>; -+ reg-names = "ahci", "sata-ecc"; -+ interrupts = <0 133 IRQ_TYPE_LEVEL_HIGH>; -+ clocks = <&clockgen 4 3>; -+ dma-coherent; -+ status = "disabled"; -+ }; -+ -+ pcie@3400000 { -+ compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie", -+ "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 108 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 0 110 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 0 111 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 0 112 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3500000 { -+ compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie", -+ "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 113 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 0 115 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 0 116 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 0 117 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ pcie@3600000 { -+ compatible = "fsl,ls2088a-pcie", "fsl,ls1088a-pcie", -+ "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ -+ reg-names = "regs", "config"; -+ interrupts = <0 118 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <8>; -+ bus-range = <0x0 0xff>; -+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 2 &gic 0 0 0 120 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 3 &gic 0 0 0 121 IRQ_TYPE_LEVEL_HIGH>, -+ <0000 0 0 4 &gic 0 0 0 122 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ fsl_mc: fsl-mc@80c000000 { -+ compatible = "fsl,qoriq-mc"; -+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ -+ dma-coherent; -+ #address-cells = <3>; -+ #size-cells = <1>; -+ -+ /* -+ * Region type 0x0 - MC portals -+ * Region type 0x1 - QBMAN portals -+ */ -+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 -+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; -+ -+ dpmacs { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpmac1: dpmac@1 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <1>; -+ }; -+ -+ dpmac2: dpmac@2 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <2>; -+ }; -+ -+ dpmac3: dpmac@3 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <3>; -+ }; -+ -+ dpmac4: dpmac@4 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <4>; -+ }; -+ -+ dpmac5: dpmac@5 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <5>; -+ }; -+ -+ dpmac6: dpmac@6 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <6>; -+ }; -+ -+ dpmac7: dpmac@7 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <7>; -+ }; -+ -+ dpmac8: dpmac@8 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <8>; -+ }; -+ -+ dpmac9: dpmac@9 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <9>; -+ }; -+ -+ dpmac10: dpmac@a { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xa>; -+ }; -+ }; -+ }; -+ -+ smmu: iommu@5000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x5000000 0 0x800000>; -+ #global-interrupts = <12>; -+ #iommu-cells = <1>; -+ stream-match-mask = <0x7C00>; -+ interrupts = <0 13 4>, /* global secure fault */ -+ <0 14 4>, /* combined secure interrupt */ -+ <0 15 4>, /* global non-secure fault */ -+ <0 16 4>, /* combined non-secure interrupt */ -+ /* performance counter interrupts 0-7 */ -+ <0 211 4>, -+ <0 212 4>, -+ <0 213 4>, -+ <0 214 4>, -+ <0 215 4>, -+ <0 216 4>, -+ <0 217 4>, -+ <0 218 4>, -+ /* per context interrupt, 64 interrupts */ -+ <0 146 4>, -+ <0 147 4>, -+ <0 148 4>, -+ <0 149 4>, -+ <0 150 4>, -+ <0 151 4>, -+ <0 152 4>, -+ <0 153 4>, -+ <0 154 4>, -+ <0 155 4>, -+ <0 156 4>, -+ <0 157 4>, -+ <0 158 4>, -+ <0 159 4>, -+ <0 160 4>, -+ <0 161 4>, -+ <0 162 4>, -+ <0 163 4>, -+ <0 164 4>, -+ <0 165 4>, -+ <0 166 4>, -+ <0 167 4>, -+ <0 168 4>, -+ <0 169 4>, -+ <0 170 4>, -+ <0 171 4>, -+ <0 172 4>, -+ <0 173 4>, -+ <0 174 4>, -+ <0 175 4>, -+ <0 176 4>, -+ <0 177 4>, -+ <0 178 4>, -+ <0 179 4>, -+ <0 180 4>, -+ <0 181 4>, -+ <0 182 4>, -+ <0 183 4>, -+ <0 184 4>, -+ <0 185 4>, -+ <0 186 4>, -+ <0 187 4>, -+ <0 188 4>, -+ <0 189 4>, -+ <0 190 4>, -+ <0 191 4>, -+ <0 192 4>, -+ <0 193 4>, -+ <0 194 4>, -+ <0 195 4>, -+ <0 196 4>, -+ <0 197 4>, -+ <0 198 4>, -+ <0 199 4>, -+ <0 200 4>, -+ <0 201 4>, -+ <0 202 4>, -+ <0 203 4>, -+ <0 204 4>, -+ <0 205 4>, -+ <0 206 4>, -+ <0 207 4>, -+ <0 208 4>, -+ <0 209 4>; -+ }; -+ -+ crypto: crypto@8000000 { -+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x8000000 0x100000>; -+ reg = <0x00 0x8000000 0x0 0x100000>; -+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; -+ dma-coherent; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+ -+}; ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-qds.dts -@@ -1,214 +1,87 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree file for Freescale LS2080a QDS Board. - * -- * Copyright (C) 2015, Freescale Semiconductor -+ * Copyright 2015-2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP - * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> - * Bhupesh Sharma <bhupesh.sharma@freescale.com> - * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - - /dts-v1/; - --/include/ "fsl-ls2080a.dtsi" -+#include "fsl-ls2080a.dtsi" -+#include "fsl-ls208xa-qds.dtsi" - - / { - model = "Freescale Layerscape 2080a QDS Board"; - compatible = "fsl,ls2080a-qds", "fsl,ls2080a"; - -- aliases { -- serial0 = &serial0; -- serial1 = &serial1; -- }; -- - chosen { - stdout-path = "serial0:115200n8"; - }; - }; - --&esdhc { -- status = "okay"; --}; -- - &ifc { -- status = "okay"; -- #address-cells = <2>; -- #size-cells = <1>; -- ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -- 0x2 0x0 0x5 0x30000000 0x00010000 -- 0x3 0x0 0x5 0x20000000 0x00010000>; -- -- nor@0,0 { -+ boardctrl: board-control@3,0 { - #address-cells = <1>; - #size-cells = <1>; -- compatible = "cfi-flash"; -- reg = <0x0 0x0 0x8000000>; -- bank-width = <2>; -- device-width = <1>; -- }; -- -- nand@2,0 { -- compatible = "fsl,ifc-nand"; -- reg = <0x2 0x0 0x10000>; -- }; -+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <3 0 0x300>; /* TODO check address */ -+ ranges = <0 3 0 0x300>; - -- cpld@3,0 { -- reg = <0x3 0x0 0x10000>; -- compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; -- }; --}; -- --&i2c0 { -- status = "okay"; -- pca9547@77 { -- compatible = "nxp,pca9547"; -- reg = <0x77>; -- #address-cells = <1>; -- #size-cells = <0>; -- i2c@0 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x00>; -- rtc@68 { -- compatible = "dallas,ds3232"; -- reg = <0x68>; -- }; -- }; -- -- i2c@2 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x02>; -- -- ina220@40 { -- compatible = "ti,ina220"; -- reg = <0x40>; -- shunt-resistor = <500>; -- }; -- -- ina220@41 { -- compatible = "ti,ina220"; -- reg = <0x41>; -- shunt-resistor = <1000>; -- }; -- }; -+ mdio_mux_emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&emdio1>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1_MDIO */ - -- i2c@3 { -- #address-cells = <1>; -+ #address-cells=<1>; - #size-cells = <0>; -- reg = <0x3>; - -- adt7481@4c { -- compatible = "adi,adt7461"; -- reg = <0x4c>; -+ /* Child MDIO buses, one for each riser card: -+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. -+ * VSC8234 PHYs on the riser cards. -+ */ -+ -+ mdio_mux3: mdio@60 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio0_phy12: mdio_phy0@1c { -+ reg = <0x1c>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy13: mdio_phy1@1d { -+ reg = <0x1d>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy14: mdio_phy2@1e { -+ reg = <0x1e>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy15: mdio_phy3@1f { -+ reg = <0x1f>; -+ phy-connection-type = "sgmii"; -+ }; - }; - }; - }; - }; - --&i2c1 { -- status = "disabled"; -+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ -+&dpmac9 { -+ phy-handle = <&mdio0_phy12>; - }; -- --&i2c2 { -- status = "disabled"; --}; -- --&i2c3 { -- status = "disabled"; --}; -- --&dspi { -- status = "okay"; -- dflash0: n25q128a { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <3000000>; -- reg = <0>; -- }; -- dflash1: sst25wf040b { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <3000000>; -- reg = <1>; -- }; -- dflash2: en25s64 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <3000000>; -- reg = <2>; -- }; -+&dpmac10 { -+ phy-handle = <&mdio0_phy13>; - }; -- --&qspi { -- status = "okay"; -- flash0: s25fl256s1@0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <20000000>; -- reg = <0>; -- }; -- flash2: s25fl256s1@2 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <20000000>; -- reg = <0>; -- }; -+&dpmac11 { -+ phy-handle = <&mdio0_phy14>; - }; -- --&sata0 { -- status = "okay"; --}; -- --&sata1 { -- status = "okay"; --}; -- --&usb0 { -- status = "okay"; --}; -- --&usb1 { -- status = "okay"; -+&dpmac12 { -+ phy-handle = <&mdio0_phy15>; - }; ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-rdb.dts -@@ -1,170 +1,105 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree file for Freescale LS2080a RDB Board. - * -- * Copyright (C) 2015, Freescale Semiconductor -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP - * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> - * Bhupesh Sharma <bhupesh.sharma@freescale.com> - * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - - /dts-v1/; - --/include/ "fsl-ls2080a.dtsi" -+#include "fsl-ls2080a.dtsi" -+#include "fsl-ls208xa-rdb.dtsi" - - / { - model = "Freescale Layerscape 2080a RDB Board"; - compatible = "fsl,ls2080a-rdb", "fsl,ls2080a"; - -- aliases { -- serial0 = &serial0; -- serial1 = &serial1; -- }; -- - chosen { - stdout-path = "serial1:115200n8"; - }; - }; - --&esdhc { -- status = "okay"; --}; -- --&ifc { -- status = "okay"; -- #address-cells = <2>; -- #size-cells = <1>; -- ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -- 0x2 0x0 0x5 0x30000000 0x00010000 -- 0x3 0x0 0x5 0x20000000 0x00010000>; -- -- nor@0,0 { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "cfi-flash"; -- reg = <0x0 0x0 0x8000000>; -- bank-width = <2>; -- device-width = <1>; -- }; -- -- nand@2,0 { -- compatible = "fsl,ifc-nand"; -- reg = <0x2 0x0 0x10000>; -- }; -- -- cpld@3,0 { -- reg = <0x3 0x0 0x10000>; -- compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; -- }; -- --}; -- --&i2c0 { -- status = "okay"; -- pca9547@75 { -- compatible = "nxp,pca9547"; -- reg = <0x75>; -- #address-cells = <1>; -- #size-cells = <0>; -- status = "disabled"; -- i2c@1 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x01>; -- rtc@68 { -- compatible = "dallas,ds3232"; -- reg = <0x68>; -- }; -- }; -- -- i2c@3 { -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x3>; -- -- adt7481@4c { -- compatible = "adi,adt7461"; -- reg = <0x4c>; -- }; -- }; -- }; --}; -- --&i2c1 { -- status = "disabled"; --}; -- --&i2c2 { -- status = "disabled"; --}; -- --&i2c3 { -+&emdio1 { - status = "disabled"; -+ /* CS4340 PHYs */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x10>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x11>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x12>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x13>; -+ phy-connection-type = "xfi"; -+ }; - }; - --&dspi { -- status = "okay"; -- dflash0: n25q512a { -- #address-cells = <1>; -- #size-cells = <1>; -- compatible = "st,m25p80"; -- spi-max-frequency = <3000000>; -- reg = <0>; -+&emdio2 { -+ /* AQR405 PHYs */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 1 0x4>; /* Level high type */ -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy2: emdio2_phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 2 0x4>; /* Level high type */ -+ reg = <0x1>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy3: emdio2_phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 4 0x4>; /* Level high type */ -+ reg = <0x2>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy4: emdio2_phy@4 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 5 0x4>; /* Level high type */ -+ reg = <0x3>; -+ phy-connection-type = "xfi"; - }; - }; - --&qspi { -- status = "disabled"; --}; -+/* Update DPMAC connections to external PHYs, under the assumption of -+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. -+ */ -+/* Leave Cortina nodes commented out until driver is integrated -+ *&dpmac1 { -+ * phy-handle = <&mdio1_phy1>; -+ *}; -+ *&dpmac2 { -+ * phy-handle = <&mdio1_phy2>; -+ *}; -+ *&dpmac3 { -+ * phy-handle = <&mdio1_phy3>; -+ *}; -+ *&dpmac4 { -+ * phy-handle = <&mdio1_phy4>; -+ *}; -+ */ - --&sata0 { -- status = "okay"; -+&dpmac5 { -+ phy-handle = <&mdio2_phy1>; - }; -- --&sata1 { -- status = "okay"; -+&dpmac6 { -+ phy-handle = <&mdio2_phy2>; - }; -- --&usb0 { -- status = "okay"; -+&dpmac7 { -+ phy-handle = <&mdio2_phy3>; - }; -- --&usb1 { -- status = "okay"; -+&dpmac8 { -+ phy-handle = <&mdio2_phy4>; - }; ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a-simu.dts -@@ -1,62 +1,21 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree file for Freescale LS2080a software Simulator model - * -- * Copyright (C) 2014-2015, Freescale Semiconductor -+ * Copyright 2014-2015 Freescale Semiconductor, Inc. - * - * Bhupesh Sharma <bhupesh.sharma@freescale.com> - * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPL or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - - /dts-v1/; - --/include/ "fsl-ls2080a.dtsi" -+#include "fsl-ls2080a.dtsi" - - / { - model = "Freescale Layerscape 2080a software Simulator model"; - compatible = "fsl,ls2080a-simu", "fsl,ls2080a"; - -- aliases { -- serial0 = &serial0; -- serial1 = &serial1; -- }; -- - ethernet@2210000 { - compatible = "smsc,lan91c111"; - reg = <0x0 0x2210000 0x0 0x100>; ---- a/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2080a.dtsi -@@ -1,739 +1,144 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) - /* - * Device Tree Include file for Freescale Layerscape-2080A family SoC. - * -- * Copyright (C) 2014-2015, Freescale Semiconductor -+ * Copyright 2014-2016 Freescale Semiconductor, Inc. - * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> - * Bhupesh Sharma <bhupesh.sharma@freescale.com> - * -- * This file is dual-licensed: you can use it either under the terms -- * of the GPLv2 or the X11 license, at your option. Note that this dual -- * licensing only applies to this file, and not this project as a -- * whole. -- * -- * a) This library is free software; you can redistribute it and/or -- * modify it under the terms of the GNU General Public License as -- * published by the Free Software Foundation; either version 2 of the -- * License, or (at your option) any later version. -- * -- * This library is distributed in the hope that it will be useful, -- * but WITHOUT ANY WARRANTY; without even the implied warranty of -- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -- * GNU General Public License for more details. -- * -- * Or, alternatively, -- * -- * b) Permission is hereby granted, free of charge, to any person -- * obtaining a copy of this software and associated documentation -- * files (the "Software"), to deal in the Software without -- * restriction, including without limitation the rights to use, -- * copy, modify, merge, publish, distribute, sublicense, and/or -- * sell copies of the Software, and to permit persons to whom the -- * Software is furnished to do so, subject to the following -- * conditions: -- * -- * The above copyright notice and this permission notice shall be -- * included in all copies or substantial portions of the Software. -- * -- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -- * OTHER DEALINGS IN THE SOFTWARE. - */ - --/ { -- compatible = "fsl,ls2080a"; -- interrupt-parent = <&gic>; -- #address-cells = <2>; -- #size-cells = <2>; -- -- cpus { -- #address-cells = <1>; -- #size-cells = <0>; -- -- /* -- * We expect the enable-method for cpu's to be "psci", but this -- * is dependent on the SoC FW, which will fill this in. -- * -- * Currently supported enable-method is psci v0.2 -- */ -- -- /* We have 4 clusters having 2 Cortex-A57 cores each */ -- cpu@0 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x0>; -- clocks = <&clockgen 1 0>; -- next-level-cache = <&cluster0_l2>; -- }; -- -- cpu@1 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x1>; -- clocks = <&clockgen 1 0>; -- next-level-cache = <&cluster0_l2>; -- }; -- -- cpu@100 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x100>; -- clocks = <&clockgen 1 1>; -- next-level-cache = <&cluster1_l2>; -- }; -- -- cpu@101 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x101>; -- clocks = <&clockgen 1 1>; -- next-level-cache = <&cluster1_l2>; -- }; -- -- cpu@200 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x200>; -- clocks = <&clockgen 1 2>; -- next-level-cache = <&cluster2_l2>; -- }; -- -- cpu@201 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x201>; -- clocks = <&clockgen 1 2>; -- next-level-cache = <&cluster2_l2>; -- }; -- -- cpu@300 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x300>; -- clocks = <&clockgen 1 3>; -- next-level-cache = <&cluster3_l2>; -- }; -- -- cpu@301 { -- device_type = "cpu"; -- compatible = "arm,cortex-a57"; -- reg = <0x301>; -- clocks = <&clockgen 1 3>; -- next-level-cache = <&cluster3_l2>; -- }; -- -- cluster0_l2: l2-cache0 { -- compatible = "cache"; -- }; -- -- cluster1_l2: l2-cache1 { -- compatible = "cache"; -- }; -- -- cluster2_l2: l2-cache2 { -- compatible = "cache"; -- }; -- -- cluster3_l2: l2-cache3 { -- compatible = "cache"; -- }; -- }; -- -- memory@80000000 { -- device_type = "memory"; -- reg = <0x00000000 0x80000000 0 0x80000000>; -- /* DRAM space - 1, size : 2 GB DRAM */ -- }; -- -- sysclk: sysclk { -- compatible = "fixed-clock"; -- #clock-cells = <0>; -- clock-frequency = <100000000>; -- clock-output-names = "sysclk"; -- }; -- -- gic: interrupt-controller@6000000 { -- compatible = "arm,gic-v3"; -- reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ -- <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ -- <0x0 0x0c0c0000 0 0x2000>, /* GICC */ -- <0x0 0x0c0d0000 0 0x1000>, /* GICH */ -- <0x0 0x0c0e0000 0 0x20000>; /* GICV */ -- #interrupt-cells = <3>; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- interrupt-controller; -- interrupts = <1 9 0x4>; -- -- its: gic-its@6020000 { -- compatible = "arm,gic-v3-its"; -- msi-controller; -- reg = <0x0 0x6020000 0 0x20000>; -- }; -- }; -- -- rstcr: syscon@1e60000 { -- compatible = "fsl,ls2080a-rstcr", "syscon"; -- reg = <0x0 0x1e60000 0x0 0x4>; -- }; -- -- reboot { -- compatible ="syscon-reboot"; -- regmap = <&rstcr>; -- offset = <0x0>; -- mask = <0x2>; -- }; -- -- timer { -- compatible = "arm,armv8-timer"; -- interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ -- <1 14 4>, /* Physical Non-Secure PPI, active-low */ -- <1 11 4>, /* Virtual PPI, active-low */ -- <1 10 4>; /* Hypervisor PPI, active-low */ -- fsl,erratum-a008585; -- }; -- -- pmu { -- compatible = "arm,armv8-pmuv3"; -- interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ -- }; -- -- soc { -- compatible = "simple-bus"; -- #address-cells = <2>; -- #size-cells = <2>; -- ranges; -- -- clockgen: clocking@1300000 { -- compatible = "fsl,ls2080a-clockgen"; -- reg = <0 0x1300000 0 0xa0000>; -- #clock-cells = <2>; -- clocks = <&sysclk>; -- }; -- -- serial0: serial@21c0500 { -- compatible = "fsl,ns16550", "ns16550a"; -- reg = <0x0 0x21c0500 0x0 0x100>; -- clocks = <&clockgen 4 3>; -- interrupts = <0 32 0x4>; /* Level high type */ -- }; -- -- serial1: serial@21c0600 { -- compatible = "fsl,ns16550", "ns16550a"; -- reg = <0x0 0x21c0600 0x0 0x100>; -- clocks = <&clockgen 4 3>; -- interrupts = <0 32 0x4>; /* Level high type */ -- }; -- -- cluster1_core0_watchdog: wdt@c000000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc000000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster1_core1_watchdog: wdt@c010000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc010000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster2_core0_watchdog: wdt@c100000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc100000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster2_core1_watchdog: wdt@c110000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc110000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster3_core0_watchdog: wdt@c200000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc200000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster3_core1_watchdog: wdt@c210000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc210000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster4_core0_watchdog: wdt@c300000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc300000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- cluster4_core1_watchdog: wdt@c310000 { -- compatible = "arm,sp805-wdt", "arm,primecell"; -- reg = <0x0 0xc310000 0x0 0x1000>; -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "apb_pclk", "wdog_clk"; -- }; -- -- fsl_mc: fsl-mc@80c000000 { -- compatible = "fsl,qoriq-mc"; -- reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -- <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ -- msi-parent = <&its>; -- #address-cells = <3>; -- #size-cells = <1>; -- -- /* -- * Region type 0x0 - MC portals -- * Region type 0x1 - QBMAN portals -- */ -- ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 -- 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; -- -- /* -- * Define the maximum number of MACs present on the SoC. -- */ -- dpmacs { -- #address-cells = <1>; -- #size-cells = <0>; -- -- dpmac1: dpmac@1 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x1>; -- }; -- -- dpmac2: dpmac@2 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x2>; -- }; -- -- dpmac3: dpmac@3 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x3>; -- }; -- -- dpmac4: dpmac@4 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x4>; -- }; -- -- dpmac5: dpmac@5 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x5>; -- }; -- -- dpmac6: dpmac@6 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x6>; -- }; -- -- dpmac7: dpmac@7 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x7>; -- }; -- -- dpmac8: dpmac@8 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x8>; -- }; -- -- dpmac9: dpmac@9 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x9>; -- }; -- -- dpmac10: dpmac@a { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xa>; -- }; -- -- dpmac11: dpmac@b { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xb>; -- }; -- -- dpmac12: dpmac@c { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xc>; -- }; -- -- dpmac13: dpmac@d { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xd>; -- }; -- -- dpmac14: dpmac@e { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xe>; -- }; -- -- dpmac15: dpmac@f { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0xf>; -- }; -- -- dpmac16: dpmac@10 { -- compatible = "fsl,qoriq-mc-dpmac"; -- reg = <0x10>; -- }; -- }; -- }; -- -- smmu: iommu@5000000 { -- compatible = "arm,mmu-500"; -- reg = <0 0x5000000 0 0x800000>; -- #global-interrupts = <12>; -- interrupts = <0 13 4>, /* global secure fault */ -- <0 14 4>, /* combined secure interrupt */ -- <0 15 4>, /* global non-secure fault */ -- <0 16 4>, /* combined non-secure interrupt */ -- /* performance counter interrupts 0-7 */ -- <0 211 4>, <0 212 4>, -- <0 213 4>, <0 214 4>, -- <0 215 4>, <0 216 4>, -- <0 217 4>, <0 218 4>, -- /* per context interrupt, 64 interrupts */ -- <0 146 4>, <0 147 4>, -- <0 148 4>, <0 149 4>, -- <0 150 4>, <0 151 4>, -- <0 152 4>, <0 153 4>, -- <0 154 4>, <0 155 4>, -- <0 156 4>, <0 157 4>, -- <0 158 4>, <0 159 4>, -- <0 160 4>, <0 161 4>, -- <0 162 4>, <0 163 4>, -- <0 164 4>, <0 165 4>, -- <0 166 4>, <0 167 4>, -- <0 168 4>, <0 169 4>, -- <0 170 4>, <0 171 4>, -- <0 172 4>, <0 173 4>, -- <0 174 4>, <0 175 4>, -- <0 176 4>, <0 177 4>, -- <0 178 4>, <0 179 4>, -- <0 180 4>, <0 181 4>, -- <0 182 4>, <0 183 4>, -- <0 184 4>, <0 185 4>, -- <0 186 4>, <0 187 4>, -- <0 188 4>, <0 189 4>, -- <0 190 4>, <0 191 4>, -- <0 192 4>, <0 193 4>, -- <0 194 4>, <0 195 4>, -- <0 196 4>, <0 197 4>, -- <0 198 4>, <0 199 4>, -- <0 200 4>, <0 201 4>, -- <0 202 4>, <0 203 4>, -- <0 204 4>, <0 205 4>, -- <0 206 4>, <0 207 4>, -- <0 208 4>, <0 209 4>; -- mmu-masters = <&fsl_mc 0x300 0>; -- }; -- -- dspi: dspi@2100000 { -- status = "disabled"; -- compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x2100000 0x0 0x10000>; -- interrupts = <0 26 0x4>; /* Level high type */ -- clocks = <&clockgen 4 3>; -- clock-names = "dspi"; -- spi-num-chipselects = <5>; -- bus-num = <0>; -- }; -- -- esdhc: esdhc@2140000 { -- status = "disabled"; -- compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; -- reg = <0x0 0x2140000 0x0 0x10000>; -- interrupts = <0 28 0x4>; /* Level high type */ -- clock-frequency = <0>; /* Updated by bootloader */ -- voltage-ranges = <1800 1800 3300 3300>; -- sdhci,auto-cmd12; -- little-endian; -- bus-width = <4>; -- }; -- -- gpio0: gpio@2300000 { -- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -- reg = <0x0 0x2300000 0x0 0x10000>; -- interrupts = <0 36 0x4>; /* Level high type */ -- gpio-controller; -- little-endian; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio1: gpio@2310000 { -- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -- reg = <0x0 0x2310000 0x0 0x10000>; -- interrupts = <0 36 0x4>; /* Level high type */ -- gpio-controller; -- little-endian; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio2: gpio@2320000 { -- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -- reg = <0x0 0x2320000 0x0 0x10000>; -- interrupts = <0 37 0x4>; /* Level high type */ -- gpio-controller; -- little-endian; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- gpio3: gpio@2330000 { -- compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -- reg = <0x0 0x2330000 0x0 0x10000>; -- interrupts = <0 37 0x4>; /* Level high type */ -- gpio-controller; -- little-endian; -- #gpio-cells = <2>; -- interrupt-controller; -- #interrupt-cells = <2>; -- }; -- -- i2c0: i2c@2000000 { -- status = "disabled"; -- compatible = "fsl,vf610-i2c"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x2000000 0x0 0x10000>; -- interrupts = <0 34 0x4>; /* Level high type */ -- clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -- }; -- -- i2c1: i2c@2010000 { -- status = "disabled"; -- compatible = "fsl,vf610-i2c"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x2010000 0x0 0x10000>; -- interrupts = <0 34 0x4>; /* Level high type */ -- clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -- }; -- -- i2c2: i2c@2020000 { -- status = "disabled"; -- compatible = "fsl,vf610-i2c"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x2020000 0x0 0x10000>; -- interrupts = <0 35 0x4>; /* Level high type */ -- clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -- }; -- -- i2c3: i2c@2030000 { -- status = "disabled"; -- compatible = "fsl,vf610-i2c"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x2030000 0x0 0x10000>; -- interrupts = <0 35 0x4>; /* Level high type */ -- clock-names = "i2c"; -- clocks = <&clockgen 4 3>; -- }; -- -- ifc: ifc@2240000 { -- compatible = "fsl,ifc", "simple-bus"; -- reg = <0x0 0x2240000 0x0 0x20000>; -- interrupts = <0 21 0x4>; /* Level high type */ -- little-endian; -- #address-cells = <2>; -- #size-cells = <1>; -- -- ranges = <0 0 0x5 0x80000000 0x08000000 -- 2 0 0x5 0x30000000 0x00010000 -- 3 0 0x5 0x20000000 0x00010000>; -- }; -- -- qspi: quadspi@20c0000 { -- status = "disabled"; -- compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; -- #address-cells = <1>; -- #size-cells = <0>; -- reg = <0x0 0x20c0000 0x0 0x10000>, -- <0x0 0x20000000 0x0 0x10000000>; -- reg-names = "QuadSPI", "QuadSPI-memory"; -- interrupts = <0 25 0x4>; /* Level high type */ -- clocks = <&clockgen 4 3>, <&clockgen 4 3>; -- clock-names = "qspi_en", "qspi"; -- }; -- -- pcie@3400000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -- "snps,dw-pcie"; -- reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -- 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ -- reg-names = "regs", "config"; -- interrupts = <0 108 0x4>; /* Level high type */ -- interrupt-names = "intr"; -- #address-cells = <3>; -- #size-cells = <2>; -- device_type = "pci"; -- dma-coherent; -- num-lanes = <4>; -- bus-range = <0x0 0xff>; -- ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ -- 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&its>; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, -- <0000 0 0 2 &gic 0 0 0 110 4>, -- <0000 0 0 3 &gic 0 0 0 111 4>, -- <0000 0 0 4 &gic 0 0 0 112 4>; -- }; -- -- pcie@3500000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -- "snps,dw-pcie"; -- reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -- 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ -- reg-names = "regs", "config"; -- interrupts = <0 113 0x4>; /* Level high type */ -- interrupt-names = "intr"; -- #address-cells = <3>; -- #size-cells = <2>; -- device_type = "pci"; -- dma-coherent; -- num-lanes = <4>; -- bus-range = <0x0 0xff>; -- ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ -- 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&its>; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, -- <0000 0 0 2 &gic 0 0 0 115 4>, -- <0000 0 0 3 &gic 0 0 0 116 4>, -- <0000 0 0 4 &gic 0 0 0 117 4>; -- }; -- -- pcie@3600000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -- "snps,dw-pcie"; -- reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -- 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ -- reg-names = "regs", "config"; -- interrupts = <0 118 0x4>; /* Level high type */ -- interrupt-names = "intr"; -- #address-cells = <3>; -- #size-cells = <2>; -- device_type = "pci"; -- dma-coherent; -- num-lanes = <8>; -- bus-range = <0x0 0xff>; -- ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ -- 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&its>; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, -- <0000 0 0 2 &gic 0 0 0 120 4>, -- <0000 0 0 3 &gic 0 0 0 121 4>, -- <0000 0 0 4 &gic 0 0 0 122 4>; -- }; -- -- pcie@3700000 { -- compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -- "snps,dw-pcie"; -- reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -- 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ -- reg-names = "regs", "config"; -- interrupts = <0 123 0x4>; /* Level high type */ -- interrupt-names = "intr"; -- #address-cells = <3>; -- #size-cells = <2>; -- device_type = "pci"; -- dma-coherent; -- num-lanes = <4>; -- bus-range = <0x0 0xff>; -- ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ -- 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -- msi-parent = <&its>; -- #interrupt-cells = <1>; -- interrupt-map-mask = <0 0 0 7>; -- interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, -- <0000 0 0 2 &gic 0 0 0 125 4>, -- <0000 0 0 3 &gic 0 0 0 126 4>, -- <0000 0 0 4 &gic 0 0 0 127 4>; -- }; -- -- sata0: sata@3200000 { -- status = "disabled"; -- compatible = "fsl,ls2080a-ahci"; -- reg = <0x0 0x3200000 0x0 0x10000>; -- interrupts = <0 133 0x4>; /* Level high type */ -- clocks = <&clockgen 4 3>; -- dma-coherent; -- }; -- -- sata1: sata@3210000 { -- status = "disabled"; -- compatible = "fsl,ls2080a-ahci"; -- reg = <0x0 0x3210000 0x0 0x10000>; -- interrupts = <0 136 0x4>; /* Level high type */ -- clocks = <&clockgen 4 3>; -- dma-coherent; -- }; -- -- usb0: usb3@3100000 { -- status = "disabled"; -- compatible = "snps,dwc3"; -- reg = <0x0 0x3100000 0x0 0x10000>; -- interrupts = <0 80 0x4>; /* Level high type */ -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- }; -- -- usb1: usb3@3110000 { -- status = "disabled"; -- compatible = "snps,dwc3"; -- reg = <0x0 0x3110000 0x0 0x10000>; -- interrupts = <0 81 0x4>; /* Level high type */ -- dr_mode = "host"; -- snps,quirk-frame-length-adjustment = <0x20>; -- snps,dis_rxdet_inp3_quirk; -- }; -- -- ccn@4000000 { -- compatible = "arm,ccn-504"; -- reg = <0x0 0x04000000 0x0 0x01000000>; -- interrupts = <0 12 4>; -- }; -- }; -- -- ddr1: memory-controller@1080000 { -- compatible = "fsl,qoriq-memory-controller"; -- reg = <0x0 0x1080000 0x0 0x1000>; -- interrupts = <0 17 0x4>; -- little-endian; -- }; -- -- ddr2: memory-controller@1090000 { -- compatible = "fsl,qoriq-memory-controller"; -- reg = <0x0 0x1090000 0x0 0x1000>; -- interrupts = <0 18 0x4>; -- little-endian; -+#include "fsl-ls208xa.dtsi" -+ -+&cpu { -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&cluster0_l2>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x1>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&cluster0_l2>; -+ }; -+ -+ cpu2: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x100>; -+ clocks = <&clockgen 1 1>; -+ next-level-cache = <&cluster1_l2>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu3: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x101>; -+ clocks = <&clockgen 1 1>; -+ next-level-cache = <&cluster1_l2>; -+ }; -+ -+ cpu4: cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x200>; -+ clocks = <&clockgen 1 2>; -+ next-level-cache = <&cluster2_l2>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu5: cpu@201 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x201>; -+ clocks = <&clockgen 1 2>; -+ next-level-cache = <&cluster2_l2>; -+ }; -+ -+ cpu6: cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x300>; -+ clocks = <&clockgen 1 3>; -+ next-level-cache = <&cluster3_l2>; -+ #cooling-cells = <2>; -+ }; -+ -+ cpu7: cpu@301 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a57"; -+ reg = <0x301>; -+ clocks = <&clockgen 1 3>; -+ next-level-cache = <&cluster3_l2>; - }; -+ -+ cluster0_l2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ -+ cluster1_l2: l2-cache1 { -+ compatible = "cache"; -+ }; -+ -+ cluster2_l2: l2-cache2 { -+ compatible = "cache"; -+ }; -+ -+ cluster3_l2: l2-cache3 { -+ compatible = "cache"; -+ }; -+}; -+ -+&usb0 { -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,dma-snooping; -+}; -+ -+&usb1 { -+ snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; -+ snps,dma-snooping; -+}; -+ -+&timer { -+ fsl,erratum-a008585; -+}; -+ -+&pcie1 { -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x10 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x10 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+}; -+ -+&pcie2 { -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x12 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x12 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+}; -+ -+&pcie3 { -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x14 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x14 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ -+}; -+ -+&pcie4 { -+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -+ 0x16 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x16 0x00010000 0x0 0x00010000 /* downstream I/O */ -+ 0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2081a-rdb.dts -@@ -0,0 +1,161 @@ -+/* -+ * Device Tree file for NXP LS2081A RDB Board. -+ * -+ * Copyright 2017 NXP -+ * -+ * Priyanka Jain <priyanka.jain@nxp.com> -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPLv2 or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This library is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of the -+ * License, or (at your option) any later version. -+ * -+ * This library is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+ -+/ { -+ model = "NXP Layerscape 2081A RDB Board"; -+ compatible = "fsl,ls2081a-rdb", "fsl,ls2081a"; -+ -+ aliases { -+ serial0 = &serial0; -+ serial1 = &serial1; -+ }; -+ -+ chosen { -+ stdout-path = "serial1:115200n8"; -+ }; -+}; -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "disabled"; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@75 { -+ compatible = "nxp,pca9547"; -+ reg = <0x75>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x01>; -+ rtc@51 { -+ compatible = "nxp,pcf2129"; -+ reg = <0x51>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x02>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q512a { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ fsl,qspi-has-second-chip; -+ flash0: s25fs512s@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spansion,m25p80"; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ flash1: s25fs512s@1 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spansion,m25p80"; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <1>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-qds.dts -@@ -0,0 +1,126 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS2088A QDS Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+#include "fsl-ls208xa-qds.dtsi" -+ -+/ { -+ model = "Freescale Layerscape 2088A QDS Board"; -+ compatible = "fsl,ls2088a-qds", "fsl,ls2088a"; -+ -+ chosen { -+ stdout-path = "serial0:115200n8"; -+ }; -+}; -+ -+&ifc { -+ boardctrl: board-control@3,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "fsl,tetra-fpga", "fsl,fpga-qixis", "simple-bus"; -+ reg = <3 0 0x300>; /* TODO check address */ -+ ranges = <0 3 0 0x300>; -+ -+ mdio_mux_emi1 { -+ compatible = "mdio-mux-mmioreg", "mdio-mux"; -+ mdio-parent-bus = <&emdio1>; -+ reg = <0x54 1>; /* BRDCFG4 */ -+ mux-mask = <0xe0>; /* EMI1_MDIO */ -+ -+ #address-cells=<1>; -+ #size-cells = <0>; -+ -+ /* Child MDIO buses, one for each riser card: -+ * reg = 0x0, 0x20, 0x40, 0x60, 0x80, 0xa0. -+ * VSC8234 PHYs on the riser cards. -+ */ -+ -+ mdio_mux3: mdio@60 { -+ reg = <0x60>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ mdio0_phy12: mdio_phy0@1c { -+ reg = <0x1c>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy13: mdio_phy1@1d { -+ reg = <0x1d>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy14: mdio_phy2@1e { -+ reg = <0x1e>; -+ phy-connection-type = "sgmii"; -+ }; -+ mdio0_phy15: mdio_phy3@1f { -+ reg = <0x1f>; -+ phy-connection-type = "sgmii"; -+ }; -+ }; -+ }; -+ }; -+}; -+ -+&pcs_mdio1 { -+ pcs_phy1: ethernet-phy@0 { -+ backplane-mode = "10gbase-kr"; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ fsl,lane-handle = <&serdes1>; -+ fsl,lane-reg = <0x9C0 0x40>;/* lane H */ -+ }; -+}; -+ -+&pcs_mdio2 { -+ pcs_phy2: ethernet-phy@0 { -+ backplane-mode = "10gbase-kr"; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ fsl,lane-handle = <&serdes1>; -+ fsl,lane-reg = <0x980 0x40>;/* lane G */ -+ }; -+}; -+ -+&pcs_mdio3 { -+ pcs_phy3: ethernet-phy@0 { -+ backplane-mode = "10gbase-kr"; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ fsl,lane-handle = <&serdes1>; -+ fsl,lane-reg = <0x940 0x40>;/* lane F */ -+ }; -+}; -+ -+&pcs_mdio4 { -+ pcs_phy4: ethernet-phy@0 { -+ backplane-mode = "10gbase-kr"; -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ reg = <0x0>; -+ fsl,lane-handle = <&serdes1>; -+ fsl,lane-reg = <0x900 0x40>;/* lane E */ -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under SerDes 0x2a_0x49. */ -+&dpmac9 { -+ phy-handle = <&mdio0_phy12>; -+}; -+&dpmac10 { -+ phy-handle = <&mdio0_phy13>; -+}; -+&dpmac11 { -+ phy-handle = <&mdio0_phy14>; -+}; -+&dpmac12 { -+ phy-handle = <&mdio0_phy15>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a-rdb.dts -@@ -0,0 +1,104 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS2088A RDB Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+/dts-v1/; -+ -+#include "fsl-ls2088a.dtsi" -+#include "fsl-ls208xa-rdb.dtsi" -+ -+/ { -+ model = "Freescale Layerscape 2088A RDB Board"; -+ compatible = "fsl,ls2088a-rdb", "fsl,ls2088a"; -+ -+ chosen { -+ stdout-path = "serial1:115200n8"; -+ }; -+}; -+ -+&emdio1 { -+ status = "disabled"; -+ /* CS4340 PHYs */ -+ mdio1_phy1: emdio1_phy@1 { -+ reg = <0x10>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy2: emdio1_phy@2 { -+ reg = <0x11>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy3: emdio1_phy@3 { -+ reg = <0x12>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio1_phy4: emdio1_phy@4 { -+ reg = <0x13>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+&emdio2 { -+ /* AQR405 PHYs */ -+ mdio2_phy1: emdio2_phy@1 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 1 0x4>; /* Level high type */ -+ reg = <0x0>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy2: emdio2_phy@2 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 2 0x4>; /* Level high type */ -+ reg = <0x1>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy3: emdio2_phy@3 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 4 0x4>; /* Level high type */ -+ reg = <0x2>; -+ phy-connection-type = "xfi"; -+ }; -+ mdio2_phy4: emdio2_phy@4 { -+ compatible = "ethernet-phy-ieee802.3-c45"; -+ interrupts = <0 5 0x4>; /* Level high type */ -+ reg = <0x3>; -+ phy-connection-type = "xfi"; -+ }; -+}; -+ -+/* Update DPMAC connections to external PHYs, under the assumption of -+ * SerDes 0x2a_0x41. This is currently the only SerDes supported on the board. -+ */ -+/* Leave Cortina PHYs commented out until proper driver is integrated -+ *&dpmac1 { -+ * phy-handle = <&mdio1_phy1>; -+ *}; -+ *&dpmac2 { -+ * phy-handle = <&mdio1_phy2>; -+ *}; -+ *&dpmac3 { -+ * phy-handle = <&mdio1_phy3>; -+ *}; -+ *&dpmac4 { -+ * phy-handle = <&mdio1_phy4>; -+ *}; -+ */ -+ -+&dpmac5 { -+ phy-handle = <&mdio2_phy1>; -+}; -+&dpmac6 { -+ phy-handle = <&mdio2_phy2>; -+}; -+&dpmac7 { -+ phy-handle = <&mdio2_phy3>; -+}; -+&dpmac8 { -+ phy-handle = <&mdio2_phy4>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls2088a.dtsi -@@ -0,0 +1,159 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-2088A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+#include "fsl-ls208xa.dtsi" -+ -+&cpu { -+ cpu0: cpu@0 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x0>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&cluster0_l2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu1: cpu@1 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x1>; -+ clocks = <&clockgen 1 0>; -+ next-level-cache = <&cluster0_l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu2: cpu@100 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x100>; -+ clocks = <&clockgen 1 1>; -+ next-level-cache = <&cluster1_l2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu3: cpu@101 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x101>; -+ clocks = <&clockgen 1 1>; -+ next-level-cache = <&cluster1_l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu4: cpu@200 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x200>; -+ clocks = <&clockgen 1 2>; -+ next-level-cache = <&cluster2_l2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu5: cpu@201 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x201>; -+ clocks = <&clockgen 1 2>; -+ next-level-cache = <&cluster2_l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu6: cpu@300 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x300>; -+ clocks = <&clockgen 1 3>; -+ next-level-cache = <&cluster3_l2>; -+ #cooling-cells = <2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ cpu7: cpu@301 { -+ device_type = "cpu"; -+ compatible = "arm,cortex-a72"; -+ reg = <0x301>; -+ clocks = <&clockgen 1 3>; -+ next-level-cache = <&cluster3_l2>; -+ cpu-idle-states = <&CPU_PH20>; -+ }; -+ -+ idle-states { -+ /* -+ * PSCI node is not added default, U-boot will add missing -+ * parts if it determines to use PSCI. -+ */ -+ entry-method = "arm,psci"; -+ -+ CPU_PH20: cpu-ph20 { -+ compatible = "arm,idle-state"; -+ idle-state-name = "PH20"; -+ arm,psci-suspend-param = <0x0>; -+ entry-latency-us = <1000>; -+ exit-latency-us = <1000>; -+ min-residency-us = <3000>; -+ }; -+ }; -+ -+ cluster0_l2: l2-cache0 { -+ compatible = "cache"; -+ }; -+ -+ cluster1_l2: l2-cache1 { -+ compatible = "cache"; -+ }; -+ -+ cluster2_l2: l2-cache2 { -+ compatible = "cache"; -+ }; -+ -+ cluster3_l2: l2-cache3 { -+ compatible = "cache"; -+ }; -+}; -+ -+&pcie1 { -+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03400000 0x0 0x00100000 /* controller registers */ -+ 0x20 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x20 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x20 0x40000000 0x0 0x40000000>; -+}; -+ -+&pcie2 { -+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03500000 0x0 0x00100000 /* controller registers */ -+ 0x28 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x28 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x28 0x40000000 0x0 0x40000000>; -+}; -+ -+&pcie3 { -+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03600000 0x0 0x00100000 /* controller registers */ -+ 0x30 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x30 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x30 0x40000000 0x0 0x40000000>; -+}; -+ -+&pcie4 { -+ compatible = "fsl,ls2088a-pcie", "snps,dw-pcie"; -+ reg = <0x00 0x03700000 0x0 0x00100000 /* controller registers */ -+ 0x38 0x00000000 0x0 0x00002000>; /* configuration space */ -+ -+ ranges = <0x81000000 0x0 0x00000000 0x38 0x00010000 0x0 0x00010000 -+ 0x82000000 0x0 0x40000000 0x38 0x40000000 0x0 0x40000000>; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-qds.dtsi -@@ -0,0 +1,162 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS2080A QDS Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+&esdhc { -+ mmc-hs200-1_8v; -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -+ 0x2 0x0 0x5 0x30000000 0x00010000 -+ 0x3 0x0 0x5 0x20000000 0x00010000>; -+ -+ nor@0,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ -+ cpld@3,0 { -+ reg = <0x3 0x0 0x10000>; -+ compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; -+ }; -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@77 { -+ compatible = "nxp,pca9547"; -+ reg = <0x77>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c@0 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x00>; -+ rtc@68 { -+ compatible = "dallas,ds3232"; -+ reg = <0x68>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x02>; -+ -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ -+ ina220@41 { -+ compatible = "ti,ina220"; -+ reg = <0x41>; -+ shunt-resistor = <1000>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q128a { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+ dflash1: sst25wf040b { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <1>; -+ }; -+ dflash2: en25s64 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <2>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ flash0: s25fl256s1@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+ flash2: s25fl256s1@2 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa-rdb.dtsi -@@ -0,0 +1,136 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree file for Freescale LS2080A RDB Board. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+&esdhc { -+ status = "okay"; -+}; -+ -+&ifc { -+ status = "okay"; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ ranges = <0x0 0x0 0x5 0x80000000 0x08000000 -+ 0x2 0x0 0x5 0x30000000 0x00010000 -+ 0x3 0x0 0x5 0x20000000 0x00010000>; -+ -+ nor@0,0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "cfi-flash"; -+ reg = <0x0 0x0 0x8000000>; -+ bank-width = <2>; -+ device-width = <1>; -+ }; -+ -+ nand@2,0 { -+ compatible = "fsl,ifc-nand"; -+ reg = <0x2 0x0 0x10000>; -+ }; -+ -+ cpld@3,0 { -+ reg = <0x3 0x0 0x10000>; -+ compatible = "fsl,ls2080aqds-fpga", "fsl,fpga-qixis"; -+ }; -+ -+}; -+ -+&i2c0 { -+ status = "okay"; -+ pca9547@75 { -+ compatible = "nxp,pca9547"; -+ reg = <0x75>; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ i2c-mux-never-disable; -+ i2c@1 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x01>; -+ rtc@68 { -+ compatible = "dallas,ds3232"; -+ reg = <0x68>; -+ }; -+ }; -+ -+ i2c@2 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x02>; -+ ina220@40 { -+ compatible = "ti,ina220"; -+ reg = <0x40>; -+ shunt-resistor = <500>; -+ }; -+ }; -+ -+ i2c@3 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x3>; -+ -+ adt7481@4c { -+ compatible = "adi,adt7461"; -+ reg = <0x4c>; -+ }; -+ }; -+ }; -+}; -+ -+&i2c1 { -+ status = "disabled"; -+}; -+ -+&i2c2 { -+ status = "disabled"; -+}; -+ -+&i2c3 { -+ status = "disabled"; -+}; -+ -+&dspi { -+ status = "okay"; -+ dflash0: n25q512a { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "st,m25p80"; -+ spi-max-frequency = <3000000>; -+ reg = <0>; -+ }; -+}; -+ -+&qspi { -+ status = "okay"; -+ flash0: s25fs512s@0 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "spansion,m25p80"; -+ m25p,fast-read; -+ spi-max-frequency = <20000000>; -+ reg = <0>; -+ }; -+}; -+ -+&sata0 { -+ status = "okay"; -+}; -+ -+&sata1 { -+ status = "okay"; -+}; -+ -+&usb0 { -+ status = "okay"; -+}; -+ -+&usb1 { -+ status = "okay"; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi -@@ -0,0 +1,885 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR MIT) -+/* -+ * Device Tree Include file for Freescale Layerscape-2080A family SoC. -+ * -+ * Copyright 2016 Freescale Semiconductor, Inc. -+ * Copyright 2017 NXP -+ * -+ * Abhimanyu Saini <abhimanyu.saini@nxp.com> -+ * -+ */ -+ -+#include <dt-bindings/thermal/thermal.h> -+#include <dt-bindings/interrupt-controller/arm-gic.h> -+ -+/ { -+ compatible = "fsl,ls2080a"; -+ interrupt-parent = <&gic>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ -+ aliases { -+ crypto = &crypto; -+ serial0 = &serial0; -+ serial1 = &serial1; -+ }; -+ -+ cpu: cpus { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ memory@80000000 { -+ device_type = "memory"; -+ reg = <0x00000000 0x80000000 0 0x80000000>; -+ /* DRAM space - 1, size : 2 GB DRAM */ -+ }; -+ -+ sysclk: sysclk { -+ compatible = "fixed-clock"; -+ #clock-cells = <0>; -+ clock-frequency = <100000000>; -+ clock-output-names = "sysclk"; -+ }; -+ -+ gic: interrupt-controller@6000000 { -+ compatible = "arm,gic-v3"; -+ reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ -+ <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */ -+ <0x0 0x0c0c0000 0 0x2000>, /* GICC */ -+ <0x0 0x0c0d0000 0 0x1000>, /* GICH */ -+ <0x0 0x0c0e0000 0 0x20000>; /* GICV */ -+ #interrupt-cells = <3>; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ interrupt-controller; -+ interrupts = <1 9 0x4>; -+ -+ its: gic-its@6020000 { -+ compatible = "arm,gic-v3-its"; -+ msi-controller; -+ reg = <0x0 0x6020000 0 0x20000>; -+ }; -+ }; -+ -+ rstcr: syscon@1e60000 { -+ compatible = "fsl,ls2080a-rstcr", "syscon"; -+ reg = <0x0 0x1e60000 0x0 0x4>; -+ }; -+ -+ reboot { -+ compatible ="syscon-reboot"; -+ regmap = <&rstcr>; -+ offset = <0x0>; -+ mask = <0x2>; -+ }; -+ -+ timer: timer { -+ compatible = "arm,armv8-timer"; -+ interrupts = <1 13 4>, /* Physical Secure PPI, active-low */ -+ <1 14 4>, /* Physical Non-Secure PPI, active-low */ -+ <1 11 4>, /* Virtual PPI, active-low */ -+ <1 10 4>; /* Hypervisor PPI, active-low */ -+ }; -+ -+ pmu { -+ compatible = "arm,armv8-pmuv3"; -+ interrupts = <1 7 0x8>; /* PMU PPI, Level low type */ -+ }; -+ -+ soc { -+ compatible = "simple-bus"; -+ #address-cells = <2>; -+ #size-cells = <2>; -+ ranges; -+ dma-ranges = <0x0 0x0 0x0 0x0 0x10000 0x00000000>; -+ -+ clockgen: clocking@1300000 { -+ compatible = "fsl,ls2080a-clockgen"; -+ reg = <0 0x1300000 0 0xa0000>; -+ #clock-cells = <2>; -+ clocks = <&sysclk>; -+ }; -+ -+ dcfg: dcfg@1e00000 { -+ compatible = "fsl,ls2080a-dcfg", "syscon"; -+ reg = <0x0 0x1e00000 0x0 0x10000>; -+ little-endian; -+ }; -+ -+ tmu: tmu@1f80000 { -+ compatible = "fsl,qoriq-tmu"; -+ reg = <0x0 0x1f80000 0x0 0x10000>; -+ interrupts = <0 23 0x4>; -+ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; -+ fsl,tmu-calibration = <0x00000000 0x00000026 -+ 0x00000001 0x0000002d -+ 0x00000002 0x00000032 -+ 0x00000003 0x00000039 -+ 0x00000004 0x0000003f -+ 0x00000005 0x00000046 -+ 0x00000006 0x0000004d -+ 0x00000007 0x00000054 -+ 0x00000008 0x0000005a -+ 0x00000009 0x00000061 -+ 0x0000000a 0x0000006a -+ 0x0000000b 0x00000071 -+ -+ 0x00010000 0x00000025 -+ 0x00010001 0x0000002c -+ 0x00010002 0x00000035 -+ 0x00010003 0x0000003d -+ 0x00010004 0x00000045 -+ 0x00010005 0x0000004e -+ 0x00010006 0x00000057 -+ 0x00010007 0x00000061 -+ 0x00010008 0x0000006b -+ 0x00010009 0x00000076 -+ -+ 0x00020000 0x00000029 -+ 0x00020001 0x00000033 -+ 0x00020002 0x0000003d -+ 0x00020003 0x00000049 -+ 0x00020004 0x00000056 -+ 0x00020005 0x00000061 -+ 0x00020006 0x0000006d -+ -+ 0x00030000 0x00000021 -+ 0x00030001 0x0000002a -+ 0x00030002 0x0000003c -+ 0x00030003 0x0000004e>; -+ little-endian; -+ #thermal-sensor-cells = <1>; -+ }; -+ -+ thermal-zones { -+ cpu_thermal: cpu-thermal { -+ polling-delay-passive = <1000>; -+ polling-delay = <5000>; -+ -+ thermal-sensors = <&tmu 4>; -+ -+ trips { -+ cpu_alert: cpu-alert { -+ temperature = <75000>; -+ hysteresis = <2000>; -+ type = "passive"; -+ }; -+ cpu_crit: cpu-crit { -+ temperature = <85000>; -+ hysteresis = <2000>; -+ type = "critical"; -+ }; -+ }; -+ -+ cooling-maps { -+ map0 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu0 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map1 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu2 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map2 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu4 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ map3 { -+ trip = <&cpu_alert>; -+ cooling-device = -+ <&cpu6 THERMAL_NO_LIMIT -+ THERMAL_NO_LIMIT>; -+ }; -+ }; -+ }; -+ }; -+ -+ serial0: serial@21c0500 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0500 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ -+ serial1: serial@21c0600 { -+ compatible = "fsl,ns16550", "ns16550a"; -+ reg = <0x0 0x21c0600 0x0 0x100>; -+ clocks = <&clockgen 4 3>; -+ interrupts = <0 32 0x4>; /* Level high type */ -+ }; -+ -+ cluster1_core0_watchdog: wdt@c000000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc000000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster1_core1_watchdog: wdt@c010000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc010000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core0_watchdog: wdt@c100000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc100000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster2_core1_watchdog: wdt@c110000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc110000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster3_core0_watchdog: wdt@c200000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc200000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster3_core1_watchdog: wdt@c210000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc210000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster4_core0_watchdog: wdt@c300000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc300000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ cluster4_core1_watchdog: wdt@c310000 { -+ compatible = "arm,sp805-wdt", "arm,primecell"; -+ reg = <0x0 0xc310000 0x0 0x1000>; -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "apb_pclk", "wdog_clk"; -+ }; -+ -+ crypto: crypto@8000000 { -+ compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; -+ fsl,sec-era = <8>; -+ #address-cells = <1>; -+ #size-cells = <1>; -+ ranges = <0x0 0x00 0x8000000 0x100000>; -+ reg = <0x00 0x8000000 0x0 0x100000>; -+ interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; -+ dma-coherent; -+ -+ sec_jr0: jr@10000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x10000 0x10000>; -+ interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr1: jr@20000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x20000 0x10000>; -+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr2: jr@30000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x30000 0x10000>; -+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ sec_jr3: jr@40000 { -+ compatible = "fsl,sec-v5.0-job-ring", -+ "fsl,sec-v4.0-job-ring"; -+ reg = <0x40000 0x10000>; -+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ }; -+ -+ fsl_mc: fsl-mc@80c000000 { -+ compatible = "fsl,qoriq-mc"; -+ reg = <0x00000008 0x0c000000 0 0x40>, /* MC portal base */ -+ <0x00000000 0x08340000 0 0x40000>; /* MC control reg */ -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 0>; /* This is fixed-up by u-boot */ -+ dma-coherent; -+ #address-cells = <3>; -+ #size-cells = <1>; -+ -+ /* -+ * Region type 0x0 - MC portals -+ * Region type 0x1 - QBMAN portals -+ */ -+ ranges = <0x0 0x0 0x0 0x8 0x0c000000 0x4000000 -+ 0x1 0x0 0x0 0x8 0x18000000 0x8000000>; -+ -+ /* -+ * Define the maximum number of MACs present on the SoC. -+ */ -+ dpmacs { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ dpmac1: dpmac@1 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x1>; -+ }; -+ -+ dpmac2: dpmac@2 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x2>; -+ }; -+ -+ dpmac3: dpmac@3 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x3>; -+ }; -+ -+ dpmac4: dpmac@4 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x4>; -+ }; -+ -+ dpmac5: dpmac@5 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x5>; -+ }; -+ -+ dpmac6: dpmac@6 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x6>; -+ }; -+ -+ dpmac7: dpmac@7 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x7>; -+ }; -+ -+ dpmac8: dpmac@8 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x8>; -+ }; -+ -+ dpmac9: dpmac@9 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x9>; -+ }; -+ -+ dpmac10: dpmac@a { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xa>; -+ }; -+ -+ dpmac11: dpmac@b { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xb>; -+ }; -+ -+ dpmac12: dpmac@c { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xc>; -+ }; -+ -+ dpmac13: dpmac@d { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xd>; -+ }; -+ -+ dpmac14: dpmac@e { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xe>; -+ }; -+ -+ dpmac15: dpmac@f { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0xf>; -+ }; -+ -+ dpmac16: dpmac@10 { -+ compatible = "fsl,qoriq-mc-dpmac"; -+ reg = <0x10>; -+ }; -+ }; -+ }; -+ -+ smmu: iommu@5000000 { -+ compatible = "arm,mmu-500"; -+ reg = <0 0x5000000 0 0x800000>; -+ #global-interrupts = <12>; -+ #iommu-cells = <1>; -+ stream-match-mask = <0x7C00>; -+ interrupts = <0 13 4>, /* global secure fault */ -+ <0 14 4>, /* combined secure interrupt */ -+ <0 15 4>, /* global non-secure fault */ -+ <0 16 4>, /* combined non-secure interrupt */ -+ /* performance counter interrupts 0-7 */ -+ <0 211 4>, <0 212 4>, -+ <0 213 4>, <0 214 4>, -+ <0 215 4>, <0 216 4>, -+ <0 217 4>, <0 218 4>, -+ /* per context interrupt, 64 interrupts */ -+ <0 146 4>, <0 147 4>, -+ <0 148 4>, <0 149 4>, -+ <0 150 4>, <0 151 4>, -+ <0 152 4>, <0 153 4>, -+ <0 154 4>, <0 155 4>, -+ <0 156 4>, <0 157 4>, -+ <0 158 4>, <0 159 4>, -+ <0 160 4>, <0 161 4>, -+ <0 162 4>, <0 163 4>, -+ <0 164 4>, <0 165 4>, -+ <0 166 4>, <0 167 4>, -+ <0 168 4>, <0 169 4>, -+ <0 170 4>, <0 171 4>, -+ <0 172 4>, <0 173 4>, -+ <0 174 4>, <0 175 4>, -+ <0 176 4>, <0 177 4>, -+ <0 178 4>, <0 179 4>, -+ <0 180 4>, <0 181 4>, -+ <0 182 4>, <0 183 4>, -+ <0 184 4>, <0 185 4>, -+ <0 186 4>, <0 187 4>, -+ <0 188 4>, <0 189 4>, -+ <0 190 4>, <0 191 4>, -+ <0 192 4>, <0 193 4>, -+ <0 194 4>, <0 195 4>, -+ <0 196 4>, <0 197 4>, -+ <0 198 4>, <0 199 4>, -+ <0 200 4>, <0 201 4>, -+ <0 202 4>, <0 203 4>, -+ <0 204 4>, <0 205 4>, -+ <0 206 4>, <0 207 4>, -+ <0 208 4>, <0 209 4>; -+ }; -+ -+ dspi: dspi@2100000 { -+ status = "disabled"; -+ compatible = "fsl,ls2080a-dspi", "fsl,ls2085a-dspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2100000 0x0 0x10000>; -+ interrupts = <0 26 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ clock-names = "dspi"; -+ spi-num-chipselects = <5>; -+ bus-num = <0>; -+ }; -+ -+ esdhc: esdhc@2140000 { -+ status = "disabled"; -+ compatible = "fsl,ls2080a-esdhc", "fsl,esdhc"; -+ reg = <0x0 0x2140000 0x0 0x10000>; -+ interrupts = <0 28 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 1>; -+ voltage-ranges = <1800 1800 3300 3300>; -+ sdhci,auto-cmd12; -+ little-endian; -+ bus-width = <4>; -+ }; -+ -+ gpio0: gpio@2300000 { -+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -+ reg = <0x0 0x2300000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio1: gpio@2310000 { -+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -+ reg = <0x0 0x2310000 0x0 0x10000>; -+ interrupts = <0 36 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio2: gpio@2320000 { -+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -+ reg = <0x0 0x2320000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ gpio3: gpio@2330000 { -+ compatible = "fsl,ls2080a-gpio", "fsl,qoriq-gpio"; -+ reg = <0x0 0x2330000 0x0 0x10000>; -+ interrupts = <0 37 0x4>; /* Level high type */ -+ gpio-controller; -+ little-endian; -+ #gpio-cells = <2>; -+ interrupt-controller; -+ #interrupt-cells = <2>; -+ }; -+ -+ /* TODO: WRIOP (CCSR?) */ -+ emdio1: mdio@0x8B96000 { /* WRIOP0: 0x8B8_0000, -+ * E-MDIO1: 0x1_6000 -+ */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B96000 0x0 0x1000>; -+ device_type = "mdio"; /* TODO: is this necessary? */ -+ little-endian; /* force the driver in LE mode */ -+ -+ /* Not necessary on the QDS, but needed on the RDB */ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ emdio2: mdio@0x8B97000 { /* WRIOP0: 0x8B8_0000, -+ * E-MDIO2: 0x1_7000 -+ */ -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8B97000 0x0 0x1000>; -+ device_type = "mdio"; /* TODO: is this necessary? */ -+ little-endian; /* force the driver in LE mode */ -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio1: mdio@0x8c07000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c07000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio2: mdio@0x8c0b000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0b000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio3: mdio@0x8c0f000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c0f000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio4: mdio@0x8c13000 { -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c13000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio5: mdio@0x8c17000 { -+ status = "disabled"; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c17000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio6: mdio@0x8c1b000 { -+ status = "disabled"; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1b000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio7: mdio@0x8c1f000 { -+ status = "disabled"; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c1f000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ pcs_mdio8: mdio@0x8c23000 { -+ status = "disabled"; -+ compatible = "fsl,fman-memac-mdio"; -+ reg = <0x0 0x8c23000 0x0 0x1000>; -+ device_type = "mdio"; -+ little-endian; -+ -+ #address-cells = <1>; -+ #size-cells = <0>; -+ }; -+ -+ i2c0: i2c@2000000 { -+ status = "disabled"; -+ compatible = "fsl,vf610-i2c", "fsl,ls208xa-vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2000000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ fsl-scl-gpio = <&gpio3 10 0>; -+ }; -+ -+ i2c1: i2c@2010000 { -+ status = "disabled"; -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2010000 0x0 0x10000>; -+ interrupts = <0 34 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ i2c2: i2c@2020000 { -+ status = "disabled"; -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2020000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ i2c3: i2c@2030000 { -+ status = "disabled"; -+ compatible = "fsl,vf610-i2c"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x2030000 0x0 0x10000>; -+ interrupts = <0 35 0x4>; /* Level high type */ -+ clock-names = "i2c"; -+ clocks = <&clockgen 4 1>; -+ }; -+ -+ ifc: ifc@2240000 { -+ compatible = "fsl,ifc", "simple-bus"; -+ reg = <0x0 0x2240000 0x0 0x20000>; -+ interrupts = <0 21 0x4>; /* Level high type */ -+ little-endian; -+ #address-cells = <2>; -+ #size-cells = <1>; -+ -+ ranges = <0 0 0x5 0x80000000 0x08000000 -+ 2 0 0x5 0x30000000 0x00010000 -+ 3 0 0x5 0x20000000 0x00010000>; -+ }; -+ -+ qspi: quadspi@20c0000 { -+ status = "disabled"; -+ compatible = "fsl,ls2080a-qspi", "fsl,ls1021a-qspi"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ reg = <0x0 0x20c0000 0x0 0x10000>, -+ <0x0 0x20000000 0x0 0x10000000>; -+ reg-names = "QuadSPI", "QuadSPI-memory"; -+ interrupts = <0 25 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>, <&clockgen 4 3>; -+ clock-names = "qspi_en", "qspi"; -+ }; -+ -+ pcie1: pcie@3400000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -+ "snps,dw-pcie"; -+ reg-names = "regs", "config"; -+ interrupts = <0 108 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 109 4>, -+ <0000 0 0 2 &gic 0 0 0 110 4>, -+ <0000 0 0 3 &gic 0 0 0 111 4>, -+ <0000 0 0 4 &gic 0 0 0 112 4>; -+ }; -+ -+ pcie2: pcie@3500000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -+ "snps,dw-pcie"; -+ reg-names = "regs", "config"; -+ interrupts = <0 113 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 114 4>, -+ <0000 0 0 2 &gic 0 0 0 115 4>, -+ <0000 0 0 3 &gic 0 0 0 116 4>, -+ <0000 0 0 4 &gic 0 0 0 117 4>; -+ }; -+ -+ pcie3: pcie@3600000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -+ "snps,dw-pcie"; -+ reg-names = "regs", "config"; -+ interrupts = <0 118 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <8>; -+ bus-range = <0x0 0xff>; -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 119 4>, -+ <0000 0 0 2 &gic 0 0 0 120 4>, -+ <0000 0 0 3 &gic 0 0 0 121 4>, -+ <0000 0 0 4 &gic 0 0 0 122 4>; -+ }; -+ -+ pcie4: pcie@3700000 { -+ compatible = "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", -+ "snps,dw-pcie"; -+ reg-names = "regs", "config"; -+ interrupts = <0 123 0x4>; /* aer interrupt */ -+ interrupt-names = "aer"; -+ #address-cells = <3>; -+ #size-cells = <2>; -+ device_type = "pci"; -+ dma-coherent; -+ num-lanes = <4>; -+ bus-range = <0x0 0xff>; -+ msi-parent = <&its>; -+ iommu-map = <0 &smmu 0 1>; /* This is fixed-up by u-boot */ -+ #interrupt-cells = <1>; -+ interrupt-map-mask = <0 0 0 7>; -+ interrupt-map = <0000 0 0 1 &gic 0 0 0 124 4>, -+ <0000 0 0 2 &gic 0 0 0 125 4>, -+ <0000 0 0 3 &gic 0 0 0 126 4>, -+ <0000 0 0 4 &gic 0 0 0 127 4>; -+ }; -+ -+ sata0: sata@3200000 { -+ status = "disabled"; -+ compatible = "fsl,ls2080a-ahci"; -+ reg = <0x0 0x3200000 0x0 0x10000>; -+ interrupts = <0 133 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ dma-coherent; -+ }; -+ -+ sata1: sata@3210000 { -+ status = "disabled"; -+ compatible = "fsl,ls2080a-ahci"; -+ reg = <0x0 0x3210000 0x0 0x10000>; -+ interrupts = <0 136 0x4>; /* Level high type */ -+ clocks = <&clockgen 4 3>; -+ dma-coherent; -+ }; -+ -+ usb0: usb3@3100000 { -+ status = "disabled"; -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3100000 0x0 0x10000>; -+ interrupts = <0 80 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ usb1: usb3@3110000 { -+ status = "disabled"; -+ compatible = "snps,dwc3"; -+ reg = <0x0 0x3110000 0x0 0x10000>; -+ interrupts = <0 81 0x4>; /* Level high type */ -+ dr_mode = "host"; -+ snps,quirk-frame-length-adjustment = <0x20>; -+ snps,dis_rxdet_inp3_quirk; -+ }; -+ -+ serdes1: serdes@1ea0000 { -+ reg = <0x0 0x1ea0000 0 0x00002000>; -+ }; -+ -+ ccn@4000000 { -+ compatible = "arm,ccn-504"; -+ reg = <0x0 0x04000000 0x0 0x01000000>; -+ interrupts = <0 12 4>; -+ }; -+ -+ ftm0: ftm0@2800000 { -+ compatible = "fsl,ls208xa-ftm"; -+ reg = <0x0 0x2800000 0x0 0x10000>, -+ <0x0 0x1e34050 0x0 0x4>; -+ interrupts = <0 44 4>; -+ reg-names = "ftm", "FlexTimer1"; -+ }; -+ }; -+ -+ ddr1: memory-controller@1080000 { -+ compatible = "fsl,qoriq-memory-controller"; -+ reg = <0x0 0x1080000 0x0 0x1000>; -+ interrupts = <0 17 0x4>; -+ little-endian; -+ }; -+ -+ ddr2: memory-controller@1090000 { -+ compatible = "fsl,qoriq-memory-controller"; -+ reg = <0x0 0x1090000 0x0 0x1000>; -+ interrupts = <0 18 0x4>; -+ little-endian; -+ }; -+ -+ firmware { -+ optee { -+ compatible = "linaro,optee-tz"; -+ method = "smc"; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals-sdk.dtsi -@@ -0,0 +1,55 @@ -+/* -+ * QorIQ BMan SDK Portals device tree nodes -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+&bportals { -+ bman-portal@0 { -+ cell-index = <0>; -+ }; -+ -+ bman-portal@10000 { -+ cell-index = <1>; -+ }; -+ -+ bman-portal@20000 { -+ cell-index = <2>; -+ }; -+ -+ bman-portal@30000 { -+ cell-index = <3>; -+ }; -+ -+ bman-portal@40000 { -+ cell-index = <4>; -+ }; -+ -+ bman-portal@50000 { -+ cell-index = <5>; -+ }; -+ -+ bman-portal@60000 { -+ cell-index = <6>; -+ }; -+ -+ bman-portal@70000 { -+ cell-index = <7>; -+ }; -+ -+ bman-portal@80000 { -+ cell-index = <8>; -+ }; -+ -+ bman-portal@90000 { -+ cell-index = <9>; -+ }; -+ -+ bman-bpids@0 { -+ compatible = "fsl,bpid-range"; -+ fsl,bpid-range = <32 32>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-bman-portals.dtsi -@@ -0,0 +1,77 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ BMan Portals device tree -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * -+ */ -+ -+&bportals { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "simple-bus"; -+ -+ bman-portal@0 { -+ /* -+ * bootloader fix-ups are expected to provide the -+ * "fsl,bman-portal-<hardware revision>" compatible -+ */ -+ compatible = "fsl,bman-portal"; -+ reg = <0x0 0x4000>, <0x4000000 0x4000>; -+ interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@10000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x10000 0x4000>, <0x4010000 0x4000>; -+ interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@20000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x20000 0x4000>, <0x4020000 0x4000>; -+ interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@30000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x30000 0x4000>, <0x4030000 0x4000>; -+ interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@40000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x40000 0x4000>, <0x4040000 0x4000>; -+ interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@50000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x50000 0x4000>, <0x4050000 0x4000>; -+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@60000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x60000 0x4000>, <0x4060000 0x4000>; -+ interrupts = <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@70000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x70000 0x4000>, <0x4070000 0x4000>; -+ interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@80000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x80000 0x4000>, <0x4080000 0x4000>; -+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+ -+ bman-portal@90000 { -+ compatible = "fsl,bman-portal"; -+ reg = <0x90000 0x4000>, <0x4090000 0x4000>; -+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-dpaa-eth.dtsi -@@ -0,0 +1,73 @@ -+/* -+ * QorIQ FMan v3 10g port #1 device tree stub [ controller @ offset 0x400000 ] -+ * -+ * Copyright 2012 - 2015 Freescale Semiconductor Inc. -+ * -+ * Redistribution and use in source and binary forms, with or without -+ * modification, are permitted provided that the following conditions are met: -+ * * Redistributions of source code must retain the above copyright -+ * notice, this list of conditions and the following disclaimer. -+ * * Redistributions in binary form must reproduce the above copyright -+ * notice, this list of conditions and the following disclaimer in the -+ * documentation and/or other materials provided with the distribution. -+ * * Neither the name of Freescale Semiconductor nor the -+ * names of its contributors may be used to endorse or promote products -+ * derived from this software without specific prior written permission. -+ * -+ * -+ * ALTERNATIVELY, this software may be distributed under the terms of the -+ * GNU General Public License ("GPL") as published by the Free Software -+ * Foundation, either version 2 of that License or (at your option) any -+ * later version. -+ * -+ * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY -+ * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -+ * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY -+ * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND -+ * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -+ */ -+ -+fsldpaa: fsl,dpaa { -+ compatible = "fsl,ls1043a-dpaa", "simple-bus", "fsl,dpaa"; -+ ethernet@0 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet0>; -+ dma-coherent; -+ }; -+ ethernet@1 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet1>; -+ dma-coherent; -+ }; -+ ethernet@2 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet2>; -+ dma-coherent; -+ }; -+ ethernet@3 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet3>; -+ dma-coherent; -+ }; -+ ethernet@4 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet4>; -+ dma-coherent; -+ }; -+ ethernet@5 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet5>; -+ dma-coherent; -+ }; -+ ethernet@8 { -+ compatible = "fsl,dpa-ethernet"; -+ fsl,fman-mac = <&enet6>; -+ dma-coherent; -+ }; -+}; -+ ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-0.dtsi -@@ -0,0 +1,43 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 10g port #0 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x10: port@90000 { -+ cell-index = <0x10>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; -+ reg = <0x90000 0x1000>; -+ fsl,fman-10g-port; -+ }; -+ -+ fman0_tx_0x30: port@b0000 { -+ cell-index = <0x30>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; -+ reg = <0xb0000 0x1000>; -+ fsl,fman-10g-port; -+ fsl,qman-channel-id = <0x800>; -+ }; -+ -+ ethernet@f0000 { -+ cell-index = <0x8>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xf0000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x10 &fman0_tx_0x30>; -+ pcsphy-handle = <&pcsphy6>; -+ }; -+ -+ mdio@f1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xf1000 0x1000>; -+ -+ pcsphy6: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-10g-1.dtsi -@@ -0,0 +1,43 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 10g port #1 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x11: port@91000 { -+ cell-index = <0x11>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; -+ reg = <0x91000 0x1000>; -+ fsl,fman-10g-port; -+ }; -+ -+ fman0_tx_0x31: port@b1000 { -+ cell-index = <0x31>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; -+ reg = <0xb1000 0x1000>; -+ fsl,fman-10g-port; -+ fsl,qman-channel-id = <0x801>; -+ }; -+ -+ ethernet@f2000 { -+ cell-index = <0x9>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xf2000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x11 &fman0_tx_0x31>; -+ pcsphy-handle = <&pcsphy7>; -+ }; -+ -+ mdio@f3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xf3000 0x1000>; -+ -+ pcsphy7: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-0.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #0 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x08: port@88000 { -+ cell-index = <0x8>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x88000 0x1000>; -+ }; -+ -+ fman0_tx_0x28: port@a8000 { -+ cell-index = <0x28>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xa8000 0x1000>; -+ fsl,qman-channel-id = <0x802>; -+ }; -+ -+ ethernet@e0000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe0000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x08 &fman0_tx_0x28>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy0>; -+ }; -+ -+ mdio@e1000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xe1000 0x1000>; -+ -+ pcsphy0: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-1.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #1 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x09: port@89000 { -+ cell-index = <0x9>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x89000 0x1000>; -+ }; -+ -+ fman0_tx_0x29: port@a9000 { -+ cell-index = <0x29>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xa9000 0x1000>; -+ fsl,qman-channel-id = <0x803>; -+ }; -+ -+ ethernet@e2000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe2000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x09 &fman0_tx_0x29>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy1>; -+ }; -+ -+ mdio@e3000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xe3000 0x1000>; -+ -+ pcsphy1: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-2.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #2 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x0a: port@8a000 { -+ cell-index = <0xa>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x8a000 0x1000>; -+ }; -+ -+ fman0_tx_0x2a: port@aa000 { -+ cell-index = <0x2a>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xaa000 0x1000>; -+ fsl,qman-channel-id = <0x804>; -+ }; -+ -+ ethernet@e4000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe4000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x0a &fman0_tx_0x2a>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy2>; -+ }; -+ -+ mdio@e5000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xe5000 0x1000>; -+ -+ pcsphy2: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-3.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #3 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x0b: port@8b000 { -+ cell-index = <0xb>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x8b000 0x1000>; -+ }; -+ -+ fman0_tx_0x2b: port@ab000 { -+ cell-index = <0x2b>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xab000 0x1000>; -+ fsl,qman-channel-id = <0x805>; -+ }; -+ -+ ethernet@e6000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe6000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x0b &fman0_tx_0x2b>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy3>; -+ }; -+ -+ mdio@e7000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xe7000 0x1000>; -+ -+ pcsphy3: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-4.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #4 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x0c: port@8c000 { -+ cell-index = <0xc>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x8c000 0x1000>; -+ }; -+ -+ fman0_tx_0x2c: port@ac000 { -+ cell-index = <0x2c>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xac000 0x1000>; -+ fsl,qman-channel-id = <0x806>; -+ }; -+ -+ ethernet@e8000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xe8000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x0c &fman0_tx_0x2c>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy4>; -+ }; -+ -+ mdio@e9000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xe9000 0x1000>; -+ -+ pcsphy4: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-1g-5.dtsi -@@ -0,0 +1,42 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 1g port #5 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman@1a00000 { -+ fman0_rx_0x0d: port@8d000 { -+ cell-index = <0xd>; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx"; -+ reg = <0x8d000 0x1000>; -+ }; -+ -+ fman0_tx_0x2d: port@ad000 { -+ cell-index = <0x2d>; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-1g-tx"; -+ reg = <0xad000 0x1000>; -+ fsl,qman-channel-id = <0x807>; -+ }; -+ -+ ethernet@ea000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-memac"; -+ reg = <0xea000 0x1000>; -+ fsl,fman-ports = <&fman0_rx_0x0d &fman0_tx_0x2d>; -+ ptp-timer = <&ptp_timer0>; -+ pcsphy-handle = <&pcsphy5>; -+ }; -+ -+ mdio@eb000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xeb000 0x1000>; -+ -+ pcsphy5: ethernet-phy@0 { -+ reg = <0x0>; -+ }; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0-6oh.dtsi -@@ -0,0 +1,47 @@ -+/* -+ * QorIQ FMan v3 OH ports device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+fman@1a00000 { -+ -+ fman0_oh1: port@82000 { -+ cell-index = <0>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x82000 0x1000>; -+ }; -+ -+ fman0_oh2: port@83000 { -+ cell-index = <1>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x83000 0x1000>; -+ }; -+ -+ fman0_oh3: port@84000 { -+ cell-index = <2>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x84000 0x1000>; -+ }; -+ -+ fman0_oh4: port@85000 { -+ cell-index = <3>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x85000 0x1000>; -+ }; -+ -+ fman0_oh5: port@86000 { -+ cell-index = <4>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x86000 0x1000>; -+ }; -+ -+ fman0_oh6: port@87000 { -+ cell-index = <5>; -+ compatible = "fsl,fman-port-oh"; -+ reg = <0x87000 0x1000>; -+ }; -+ -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-fman3-0.dtsi -@@ -0,0 +1,130 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ FMan v3 device tree -+ * -+ * Copyright 2012-2015 Freescale Semiconductor Inc. -+ * -+ */ -+ -+fman0: fman@1a00000 { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ cell-index = <0>; -+ compatible = "fsl,fman"; -+ ranges = <0x0 0x00 0x1a00000 0x100000>; -+ reg = <0x0 0x1a00000 0x0 0x100000>; -+ interrupts = <0 44 0x4>, <0 45 0x4>; -+ clocks = <&clockgen 3 0>; -+ clock-names = "fmanclk"; -+ fsl,qman-channel-range = <0x800 0x10>; -+ -+ cc { -+ compatible = "fsl,fman-cc"; -+ }; -+ -+ muram@0 { -+ compatible = "fsl,fman-muram"; -+ reg = <0x0 0x60000>; -+ }; -+ -+ bmi@80000 { -+ compatible = "fsl,fman-bmi"; -+ reg = <0x80000 0x400>; -+ }; -+ -+ qmi@80400 { -+ compatible = "fsl,fman-qmi"; -+ reg = <0x80400 0x400>; -+ }; -+ -+ fman0_oh_0x2: port@82000 { -+ cell-index = <0x2>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x82000 0x1000>; -+ fsl,qman-channel-id = <0x809>; -+ }; -+ -+ fman0_oh_0x3: port@83000 { -+ cell-index = <0x3>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x83000 0x1000>; -+ fsl,qman-channel-id = <0x80a>; -+ }; -+ -+ fman0_oh_0x4: port@84000 { -+ cell-index = <0x4>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x84000 0x1000>; -+ fsl,qman-channel-id = <0x80b>; -+ }; -+ -+ fman0_oh_0x5: port@85000 { -+ cell-index = <0x5>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x85000 0x1000>; -+ fsl,qman-channel-id = <0x80c>; -+ }; -+ -+ fman0_oh_0x6: port@86000 { -+ cell-index = <0x6>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x86000 0x1000>; -+ fsl,qman-channel-id = <0x80d>; -+ }; -+ -+ fman0_oh_0x7: port@87000 { -+ cell-index = <0x7>; -+ compatible = "fsl,fman-v3-port-oh"; -+ reg = <0x87000 0x1000>; -+ fsl,qman-channel-id = <0x80e>; -+ }; -+ -+ policer@c0000 { -+ compatible = "fsl,fman-policer"; -+ reg = <0xc0000 0x1000>; -+ }; -+ -+ keygen@c1000 { -+ compatible = "fsl,fman-keygen"; -+ reg = <0xc1000 0x1000>; -+ }; -+ -+ dma@c2000 { -+ compatible = "fsl,fman-dma"; -+ reg = <0xc2000 0x1000>; -+ }; -+ -+ fpm@c3000 { -+ compatible = "fsl,fman-fpm"; -+ reg = <0xc3000 0x1000>; -+ }; -+ -+ parser@c7000 { -+ compatible = "fsl,fman-parser"; -+ reg = <0xc7000 0x1000>; -+ }; -+ -+ vsps@dc000 { -+ compatible = "fsl,fman-vsps"; -+ reg = <0xdc000 0x1000>; -+ }; -+ -+ mdio0: mdio@fc000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xfc000 0x1000>; -+ }; -+ -+ xmdio0: mdio@fd000 { -+ #address-cells = <1>; -+ #size-cells = <0>; -+ compatible = "fsl,fman-memac-mdio", "fsl,fman-xmdio"; -+ reg = <0xfd000 0x1000>; -+ }; -+ -+ ptp_timer0: ptp-timer@fe000 { -+ compatible = "fsl,fman-ptp-timer", "fsl,fman-rtc"; -+ reg = <0xfe000 0x1000>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals-sdk.dtsi -@@ -0,0 +1,38 @@ -+/* -+ * QorIQ QMan SDK Portals device tree nodes -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * Copyright 2017 NXP -+ * -+ * SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+ */ -+ -+&qportals { -+ qman-fqids@0 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <256 256>; -+ }; -+ -+ qman-fqids@1 { -+ compatible = "fsl,fqid-range"; -+ fsl,fqid-range = <32768 32768>; -+ }; -+ -+ qman-pools@0 { -+ compatible = "fsl,pool-channel-range"; -+ fsl,pool-channel-range = <0x401 0xf>; -+ }; -+ -+ qman-cgrids@0 { -+ compatible = "fsl,cgrid-range"; -+ fsl,cgrid-range = <0 256>; -+ }; -+ -+ qman-ceetm@0 { -+ compatible = "fsl,qman-ceetm"; -+ fsl,ceetm-lfqid-range = <0xf00000 0x1000>; -+ fsl,ceetm-sp-range = <0 16>; -+ fsl,ceetm-lni-range = <0 8>; -+ fsl,ceetm-channel-range = <0 32>; -+ }; -+}; ---- /dev/null -+++ b/arch/arm64/boot/dts/freescale/qoriq-qman-portals.dtsi -@@ -0,0 +1,87 @@ -+// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) -+/* -+ * QorIQ QMan Portals device tree -+ * -+ * Copyright 2011-2016 Freescale Semiconductor Inc. -+ * -+ */ -+ -+&qportals { -+ #address-cells = <1>; -+ #size-cells = <1>; -+ compatible = "simple-bus"; -+ -+ qportal0: qman-portal@0 { -+ /* -+ * bootloader fix-ups are expected to provide the -+ * "fsl,bman-portal-<hardware revision>" compatible -+ */ -+ compatible = "fsl,qman-portal"; -+ reg = <0x0 0x4000>, <0x4000000 0x4000>; -+ interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <0>; -+ }; -+ -+ qportal1: qman-portal@10000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x10000 0x4000>, <0x4010000 0x4000>; -+ interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <1>; -+ }; -+ -+ qportal2: qman-portal@20000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x20000 0x4000>, <0x4020000 0x4000>; -+ interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <2>; -+ }; -+ -+ qportal3: qman-portal@30000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x30000 0x4000>, <0x4030000 0x4000>; -+ interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <3>; -+ }; -+ -+ qportal4: qman-portal@40000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x40000 0x4000>, <0x4040000 0x4000>; -+ interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <4>; -+ }; -+ -+ qportal5: qman-portal@50000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x50000 0x4000>, <0x4050000 0x4000>; -+ interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <5>; -+ }; -+ -+ qportal6: qman-portal@60000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x60000 0x4000>, <0x4060000 0x4000>; -+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <6>; -+ }; -+ -+ qportal7: qman-portal@70000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x70000 0x4000>, <0x4070000 0x4000>; -+ interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <7>; -+ }; -+ -+ qportal8: qman-portal@80000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x80000 0x4000>, <0x4080000 0x4000>; -+ interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <8>; -+ }; -+ -+ qportal9: qman-portal@90000 { -+ compatible = "fsl,qman-portal"; -+ reg = <0x90000 0x4000>, <0x4090000 0x4000>; -+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; -+ cell-index = <9>; -+ }; -+}; ---- a/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi -+++ b/arch/powerpc/boot/dts/fsl/qoriq-bman1-portals.dtsi -@@ -38,51 +38,61 @@ - compatible = "simple-bus"; - - bman-portal@0 { -+ cell-index = <0>; - compatible = "fsl,bman-portal"; - reg = <0x0 0x4000>, <0x100000 0x1000>; - interrupts = <105 2 0 0>; - }; - bman-portal@4000 { -+ cell-index = <1>; - compatible = "fsl,bman-portal"; - reg = <0x4000 0x4000>, <0x101000 0x1000>; - interrupts = <107 2 0 0>; - }; - bman-portal@8000 { -+ cell-index = <2>; - compatible = "fsl,bman-portal"; - reg = <0x8000 0x4000>, <0x102000 0x1000>; - interrupts = <109 2 0 0>; - }; - bman-portal@c000 { -+ cell-index = <3>; - compatible = "fsl,bman-portal"; - reg = <0xc000 0x4000>, <0x103000 0x1000>; - interrupts = <111 2 0 0>; - }; - bman-portal@10000 { -+ cell-index = <4>; - compatible = "fsl,bman-portal"; - reg = <0x10000 0x4000>, <0x104000 0x1000>; - interrupts = <113 2 0 0>; - }; - bman-portal@14000 { -+ cell-index = <5>; - compatible = "fsl,bman-portal"; - reg = <0x14000 0x4000>, <0x105000 0x1000>; - interrupts = <115 2 0 0>; - }; - bman-portal@18000 { -+ cell-index = <6>; - compatible = "fsl,bman-portal"; - reg = <0x18000 0x4000>, <0x106000 0x1000>; - interrupts = <117 2 0 0>; - }; - bman-portal@1c000 { -+ cell-index = <7>; - compatible = "fsl,bman-portal"; - reg = <0x1c000 0x4000>, <0x107000 0x1000>; - interrupts = <119 2 0 0>; - }; - bman-portal@20000 { -+ cell-index = <8>; - compatible = "fsl,bman-portal"; - reg = <0x20000 0x4000>, <0x108000 0x1000>; - interrupts = <121 2 0 0>; - }; - bman-portal@24000 { -+ cell-index = <9>; - compatible = "fsl,bman-portal"; - reg = <0x24000 0x4000>, <0x109000 0x1000>; - interrupts = <123 2 0 0>; ---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi -+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-0.dtsi -@@ -35,14 +35,14 @@ - fman@400000 { - fman0_rx_0x10: port@90000 { - cell-index = <0x10>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; - reg = <0x90000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x30: port@b0000 { - cell-index = <0x30>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; - reg = <0xb0000 0x1000>; - fsl,fman-10g-port; - }; ---- a/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi -+++ b/arch/powerpc/boot/dts/fsl/qoriq-fman3-0-10g-1.dtsi -@@ -35,14 +35,14 @@ - fman@400000 { - fman0_rx_0x11: port@91000 { - cell-index = <0x11>; -- compatible = "fsl,fman-v3-port-rx"; -+ compatible = "fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx"; - reg = <0x91000 0x1000>; - fsl,fman-10g-port; - }; - - fman0_tx_0x31: port@b1000 { - cell-index = <0x31>; -- compatible = "fsl,fman-v3-port-tx"; -+ compatible = "fsl,fman-v3-port-tx", "fsl,fman-port-10g-tx"; - reg = <0xb1000 0x1000>; - fsl,fman-10g-port; - }; |