diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch | 75 |
1 files changed, 75 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch b/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch new file mode 100644 index 0000000000..8dd5cdbc8e --- /dev/null +++ b/target/linux/layerscape/patches-4.4/8129-clk-qoriq-add-ls1046a-support.patch @@ -0,0 +1,75 @@ +From 4fe33d4f4dc608fc5013390db58df06723282d01 Mon Sep 17 00:00:00 2001 +From: Mingkai Hu <mingkai.hu@nxp.com> +Date: Thu, 2 Jun 2016 11:15:58 +0800 +Subject: [PATCH 129/141] clk: qoriq: add ls1046a support + +Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com> +Integated-by: Yutang Jiang <yutang.jiang@nxp.com> +--- + drivers/clk/clk-qoriq.c | 41 +++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 41 insertions(+) + +--- a/drivers/clk/clk-qoriq.c ++++ b/drivers/clk/clk-qoriq.c +@@ -275,6 +275,31 @@ static const struct clockgen_muxinfo ls1 + }, + }; + ++static const struct clockgen_muxinfo ls1046a_hwa1 = { ++ { ++ {}, ++ {}, ++ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, ++ { CLKSEL_VALID, CGA_PLL1, PLL_DIV3 }, ++ { CLKSEL_VALID, CGA_PLL1, PLL_DIV4 }, ++ { CLKSEL_VALID, PLATFORM_PLL, PLL_DIV1 }, ++ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, ++ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, ++ }, ++}; ++ ++static const struct clockgen_muxinfo ls1046a_hwa2 = { ++ { ++ {}, ++ { CLKSEL_VALID, CGA_PLL2, PLL_DIV1 }, ++ { CLKSEL_VALID, CGA_PLL2, PLL_DIV2 }, ++ { CLKSEL_VALID, CGA_PLL2, PLL_DIV3 }, ++ {}, ++ {}, ++ { CLKSEL_VALID, CGA_PLL1, PLL_DIV2 }, ++ }, ++}; ++ + static const struct clockgen_muxinfo t1023_hwa1 = { + { + {}, +@@ -508,6 +533,21 @@ static const struct clockgen_chipinfo ch + .flags = CG_PLL_8BIT, + }, + { ++ .compat = "fsl,ls1046a-clockgen", ++ .init_periph = t2080_init_periph, ++ .cmux_groups = { ++ &t1040_cmux ++ }, ++ .hwaccel = { ++ &ls1046a_hwa1, &ls1046a_hwa2 ++ }, ++ .cmux_to_group = { ++ 0, -1 ++ }, ++ .pll_mask = 0x07, ++ .flags = CG_PLL_8BIT, ++ }, ++ { + .compat = "fsl,ls2080a-clockgen", + .cmux_groups = { + &clockgen2_cmux_cga12, &clockgen2_cmux_cgb +@@ -1285,6 +1325,7 @@ CLK_OF_DECLARE(qoriq_clockgen_1, "fsl,qo + CLK_OF_DECLARE(qoriq_clockgen_2, "fsl,qoriq-clockgen-2.0", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls1021a, "fsl,ls1021a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls1043a, "fsl,ls1043a-clockgen", clockgen_init); ++CLK_OF_DECLARE(qoriq_clockgen_ls1046a, "fsl,ls1046a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls2080a, "fsl,ls2080a-clockgen", clockgen_init); + CLK_OF_DECLARE(qoriq_clockgen_ls1012a, "fsl,ls1012a-clockgen", clockgen_init); + |