diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch | 1317 |
1 files changed, 0 insertions, 1317 deletions
diff --git a/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch b/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch deleted file mode 100644 index e6962c2665..0000000000 --- a/target/linux/layerscape/patches-4.4/7014-temp-QE-headers-are-needed-by-FMD.patch +++ /dev/null @@ -1,1317 +0,0 @@ -From 03c463111e16f9bae8a659408e5f02333af13239 Mon Sep 17 00:00:00 2001 -From: Madalin Bucur <madalin.bucur@freescale.com> -Date: Tue, 5 Jan 2016 15:41:28 +0200 -Subject: [PATCH 14/70] temp: QE headers are needed by FMD - -Signed-off-by: Madalin Bucur <madalin.bucur@freescale.com> ---- - include/linux/fsl/immap_qe.h | 488 +++++++++++++++++++++++++ - include/linux/fsl/qe.h | 810 ++++++++++++++++++++++++++++++++++++++++++ - 2 files changed, 1298 insertions(+) - create mode 100644 include/linux/fsl/immap_qe.h - create mode 100644 include/linux/fsl/qe.h - ---- /dev/null -+++ b/include/linux/fsl/immap_qe.h -@@ -0,0 +1,488 @@ -+/* -+ * QUICC Engine (QE) Internal Memory Map. -+ * The Internal Memory Map for devices with QE on them. This -+ * is the superset of all QE devices (8360, etc.). -+ * Copyright (C) 2006. Freescale Semiconductor, Inc. All rights reserved. -+ * -+ * Authors: -+ * Shlomi Gridish <gridish@freescale.com> -+ * Li Yang <leoli@freescale.com> -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+#ifndef _ASM_POWERPC_IMMAP_QE_H -+#define _ASM_POWERPC_IMMAP_QE_H -+#ifdef __KERNEL__ -+ -+#include <linux/kernel.h> -+#include <linux/io.h> -+ -+#define QE_IMMAP_SIZE (1024 * 1024) /* 1MB from 1MB+IMMR */ -+ -+/* QE I-RAM */ -+struct qe_iram { -+ __be32 iadd; /* I-RAM Address Register */ -+ __be32 idata; /* I-RAM Data Register */ -+ u8 res0[0x04]; -+ __be32 iready; /* I-RAM Ready Register */ -+ u8 res1[0x70]; -+} __packed; -+ -+/* QE Interrupt Controller */ -+struct qe_ic_regs { -+ __be32 qicr; -+ __be32 qivec; -+ __be32 qripnr; -+ __be32 qipnr; -+ __be32 qipxcc; -+ __be32 qipycc; -+ __be32 qipwcc; -+ __be32 qipzcc; -+ __be32 qimr; -+ __be32 qrimr; -+ __be32 qicnr; -+ u8 res0[0x4]; -+ __be32 qiprta; -+ __be32 qiprtb; -+ u8 res1[0x4]; -+ __be32 qricr; -+ u8 res2[0x20]; -+ __be32 qhivec; -+ u8 res3[0x1C]; -+} __packed; -+ -+/* Communications Processor */ -+struct cp_qe { -+ __be32 cecr; /* QE command register */ -+ __be32 ceccr; /* QE controller configuration register */ -+ __be32 cecdr; /* QE command data register */ -+ u8 res0[0xA]; -+ __be16 ceter; /* QE timer event register */ -+ u8 res1[0x2]; -+ __be16 cetmr; /* QE timers mask register */ -+ __be32 cetscr; /* QE time-stamp timer control register */ -+ __be32 cetsr1; /* QE time-stamp register 1 */ -+ __be32 cetsr2; /* QE time-stamp register 2 */ -+ u8 res2[0x8]; -+ __be32 cevter; /* QE virtual tasks event register */ -+ __be32 cevtmr; /* QE virtual tasks mask register */ -+ __be16 cercr; /* QE RAM control register */ -+ u8 res3[0x2]; -+ u8 res4[0x24]; -+ __be16 ceexe1; /* QE external request 1 event register */ -+ u8 res5[0x2]; -+ __be16 ceexm1; /* QE external request 1 mask register */ -+ u8 res6[0x2]; -+ __be16 ceexe2; /* QE external request 2 event register */ -+ u8 res7[0x2]; -+ __be16 ceexm2; /* QE external request 2 mask register */ -+ u8 res8[0x2]; -+ __be16 ceexe3; /* QE external request 3 event register */ -+ u8 res9[0x2]; -+ __be16 ceexm3; /* QE external request 3 mask register */ -+ u8 res10[0x2]; -+ __be16 ceexe4; /* QE external request 4 event register */ -+ u8 res11[0x2]; -+ __be16 ceexm4; /* QE external request 4 mask register */ -+ u8 res12[0x3A]; -+ __be32 ceurnr; /* QE microcode revision number register */ -+ u8 res13[0x244]; -+} __packed; -+ -+/* QE Multiplexer */ -+struct qe_mux { -+ __be32 cmxgcr; /* CMX general clock route register */ -+ __be32 cmxsi1cr_l; /* CMX SI1 clock route low register */ -+ __be32 cmxsi1cr_h; /* CMX SI1 clock route high register */ -+ __be32 cmxsi1syr; /* CMX SI1 SYNC route register */ -+ __be32 cmxucr[4]; /* CMX UCCx clock route registers */ -+ __be32 cmxupcr; /* CMX UPC clock route register */ -+ u8 res0[0x1C]; -+} __packed; -+ -+/* QE Timers */ -+struct qe_timers { -+ u8 gtcfr1; /* Timer 1 and Timer 2 global config register*/ -+ u8 res0[0x3]; -+ u8 gtcfr2; /* Timer 3 and timer 4 global config register*/ -+ u8 res1[0xB]; -+ __be16 gtmdr1; /* Timer 1 mode register */ -+ __be16 gtmdr2; /* Timer 2 mode register */ -+ __be16 gtrfr1; /* Timer 1 reference register */ -+ __be16 gtrfr2; /* Timer 2 reference register */ -+ __be16 gtcpr1; /* Timer 1 capture register */ -+ __be16 gtcpr2; /* Timer 2 capture register */ -+ __be16 gtcnr1; /* Timer 1 counter */ -+ __be16 gtcnr2; /* Timer 2 counter */ -+ __be16 gtmdr3; /* Timer 3 mode register */ -+ __be16 gtmdr4; /* Timer 4 mode register */ -+ __be16 gtrfr3; /* Timer 3 reference register */ -+ __be16 gtrfr4; /* Timer 4 reference register */ -+ __be16 gtcpr3; /* Timer 3 capture register */ -+ __be16 gtcpr4; /* Timer 4 capture register */ -+ __be16 gtcnr3; /* Timer 3 counter */ -+ __be16 gtcnr4; /* Timer 4 counter */ -+ __be16 gtevr1; /* Timer 1 event register */ -+ __be16 gtevr2; /* Timer 2 event register */ -+ __be16 gtevr3; /* Timer 3 event register */ -+ __be16 gtevr4; /* Timer 4 event register */ -+ __be16 gtps; /* Timer 1 prescale register */ -+ u8 res2[0x46]; -+} __packed; -+ -+/* BRG */ -+struct qe_brg { -+ __be32 brgc[16]; /* BRG configuration registers */ -+ u8 res0[0x40]; -+} __packed; -+ -+/* SPI */ -+struct spi { -+ u8 res0[0x20]; -+ __be32 spmode; /* SPI mode register */ -+ u8 res1[0x2]; -+ u8 spie; /* SPI event register */ -+ u8 res2[0x1]; -+ u8 res3[0x2]; -+ u8 spim; /* SPI mask register */ -+ u8 res4[0x1]; -+ u8 res5[0x1]; -+ u8 spcom; /* SPI command register */ -+ u8 res6[0x2]; -+ __be32 spitd; /* SPI transmit data register (cpu mode) */ -+ __be32 spird; /* SPI receive data register (cpu mode) */ -+ u8 res7[0x8]; -+} __packed; -+ -+/* SI */ -+struct si1 { -+ __be16 sixmr1[4]; /* SI1 TDMx (x = A B C D) mode register */ -+ u8 siglmr1_h; /* SI1 global mode register high */ -+ u8 res0[0x1]; -+ u8 sicmdr1_h; /* SI1 command register high */ -+ u8 res2[0x1]; -+ u8 sistr1_h; /* SI1 status register high */ -+ u8 res3[0x1]; -+ __be16 sirsr1_h; /* SI1 RAM shadow address register high */ -+ u8 sitarc1; /* SI1 RAM counter Tx TDMA */ -+ u8 sitbrc1; /* SI1 RAM counter Tx TDMB */ -+ u8 sitcrc1; /* SI1 RAM counter Tx TDMC */ -+ u8 sitdrc1; /* SI1 RAM counter Tx TDMD */ -+ u8 sirarc1; /* SI1 RAM counter Rx TDMA */ -+ u8 sirbrc1; /* SI1 RAM counter Rx TDMB */ -+ u8 sircrc1; /* SI1 RAM counter Rx TDMC */ -+ u8 sirdrc1; /* SI1 RAM counter Rx TDMD */ -+ u8 res4[0x8]; -+ __be16 siemr1; /* SI1 TDME mode register 16 bits */ -+ __be16 sifmr1; /* SI1 TDMF mode register 16 bits */ -+ __be16 sigmr1; /* SI1 TDMG mode register 16 bits */ -+ __be16 sihmr1; /* SI1 TDMH mode register 16 bits */ -+ u8 siglmg1_l; /* SI1 global mode register low 8 bits */ -+ u8 res5[0x1]; -+ u8 sicmdr1_l; /* SI1 command register low 8 bits */ -+ u8 res6[0x1]; -+ u8 sistr1_l; /* SI1 status register low 8 bits */ -+ u8 res7[0x1]; -+ __be16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits*/ -+ u8 siterc1; /* SI1 RAM counter Tx TDME 8 bits */ -+ u8 sitfrc1; /* SI1 RAM counter Tx TDMF 8 bits */ -+ u8 sitgrc1; /* SI1 RAM counter Tx TDMG 8 bits */ -+ u8 sithrc1; /* SI1 RAM counter Tx TDMH 8 bits */ -+ u8 sirerc1; /* SI1 RAM counter Rx TDME 8 bits */ -+ u8 sirfrc1; /* SI1 RAM counter Rx TDMF 8 bits */ -+ u8 sirgrc1; /* SI1 RAM counter Rx TDMG 8 bits */ -+ u8 sirhrc1; /* SI1 RAM counter Rx TDMH 8 bits */ -+ u8 res8[0x8]; -+ __be32 siml1; /* SI1 multiframe limit register */ -+ u8 siedm1; /* SI1 extended diagnostic mode register */ -+ u8 res9[0xBB]; -+} __packed; -+ -+/* SI Routing Tables */ -+struct sir { -+ u8 tx[0x400]; -+ u8 rx[0x400]; -+ u8 res0[0x800]; -+} __packed; -+ -+/* USB Controller */ -+struct qe_usb_ctlr { -+ u8 usb_usmod; -+ u8 usb_usadr; -+ u8 usb_uscom; -+ u8 res1[1]; -+ __be16 usb_usep[4]; -+ u8 res2[4]; -+ __be16 usb_usber; -+ u8 res3[2]; -+ __be16 usb_usbmr; -+ u8 res4[1]; -+ u8 usb_usbs; -+ __be16 usb_ussft; -+ u8 res5[2]; -+ __be16 usb_usfrn; -+ u8 res6[0x22]; -+} __packed; -+ -+/* MCC */ -+struct qe_mcc { -+ __be32 mcce; /* MCC event register */ -+ __be32 mccm; /* MCC mask register */ -+ __be32 mccf; /* MCC configuration register */ -+ __be32 merl; /* MCC emergency request level register */ -+ u8 res0[0xF0]; -+} __packed; -+ -+/* QE UCC Slow */ -+struct ucc_slow { -+ __be32 gumr_l; /* UCCx general mode register (low) */ -+ __be32 gumr_h; /* UCCx general mode register (high) */ -+ __be16 upsmr; /* UCCx protocol-specific mode register */ -+ u8 res0[0x2]; -+ __be16 utodr; /* UCCx transmit on demand register */ -+ __be16 udsr; /* UCCx data synchronization register */ -+ __be16 ucce; /* UCCx event register */ -+ u8 res1[0x2]; -+ __be16 uccm; /* UCCx mask register */ -+ u8 res2[0x1]; -+ u8 uccs; /* UCCx status register */ -+ u8 res3[0x24]; -+ __be16 utpt; -+ u8 res4[0x52]; -+ u8 guemr; /* UCC general extended mode register */ -+} __packed; -+ -+/* QE UCC Fast */ -+struct ucc_fast { -+ __be32 gumr; /* UCCx general mode register */ -+ __be32 upsmr; /* UCCx protocol-specific mode register */ -+ __be16 utodr; /* UCCx transmit on demand register */ -+ u8 res0[0x2]; -+ __be16 udsr; /* UCCx data synchronization register */ -+ u8 res1[0x2]; -+ __be32 ucce; /* UCCx event register */ -+ __be32 uccm; /* UCCx mask register */ -+ u8 uccs; /* UCCx status register */ -+ u8 res2[0x7]; -+ __be32 urfb; /* UCC receive FIFO base */ -+ __be16 urfs; /* UCC receive FIFO size */ -+ u8 res3[0x2]; -+ __be16 urfet; /* UCC receive FIFO emergency threshold */ -+ __be16 urfset; /* UCC receive FIFO special emergency -+ threshold */ -+ __be32 utfb; /* UCC transmit FIFO base */ -+ __be16 utfs; /* UCC transmit FIFO size */ -+ u8 res4[0x2]; -+ __be16 utfet; /* UCC transmit FIFO emergency threshold */ -+ u8 res5[0x2]; -+ __be16 utftt; /* UCC transmit FIFO transmit threshold */ -+ u8 res6[0x2]; -+ __be16 utpt; /* UCC transmit polling timer */ -+ u8 res7[0x2]; -+ __be32 urtry; /* UCC retry counter register */ -+ u8 res8[0x4C]; -+ u8 guemr; /* UCC general extended mode register */ -+} __packed; -+ -+struct ucc { -+ union { -+ struct ucc_slow slow; -+ struct ucc_fast fast; -+ u8 res[0x200]; /* UCC blocks are 512 bytes each */ -+ }; -+} __packed; -+ -+/* MultiPHY UTOPIA POS Controllers (UPC) */ -+struct upc { -+ __be32 upgcr; /* UTOPIA/POS general configuration register */ -+ __be32 uplpa; /* UTOPIA/POS last PHY address */ -+ __be32 uphec; /* ATM HEC register */ -+ __be32 upuc; /* UTOPIA/POS UCC configuration */ -+ __be32 updc1; /* UTOPIA/POS device 1 configuration */ -+ __be32 updc2; /* UTOPIA/POS device 2 configuration */ -+ __be32 updc3; /* UTOPIA/POS device 3 configuration */ -+ __be32 updc4; /* UTOPIA/POS device 4 configuration */ -+ __be32 upstpa; /* UTOPIA/POS STPA threshold */ -+ u8 res0[0xC]; -+ __be32 updrs1_h; /* UTOPIA/POS device 1 rate select */ -+ __be32 updrs1_l; /* UTOPIA/POS device 1 rate select */ -+ __be32 updrs2_h; /* UTOPIA/POS device 2 rate select */ -+ __be32 updrs2_l; /* UTOPIA/POS device 2 rate select */ -+ __be32 updrs3_h; /* UTOPIA/POS device 3 rate select */ -+ __be32 updrs3_l; /* UTOPIA/POS device 3 rate select */ -+ __be32 updrs4_h; /* UTOPIA/POS device 4 rate select */ -+ __be32 updrs4_l; /* UTOPIA/POS device 4 rate select */ -+ __be32 updrp1; /* UTOPIA/POS device 1 receive priority low */ -+ __be32 updrp2; /* UTOPIA/POS device 2 receive priority low */ -+ __be32 updrp3; /* UTOPIA/POS device 3 receive priority low */ -+ __be32 updrp4; /* UTOPIA/POS device 4 receive priority low */ -+ __be32 upde1; /* UTOPIA/POS device 1 event */ -+ __be32 upde2; /* UTOPIA/POS device 2 event */ -+ __be32 upde3; /* UTOPIA/POS device 3 event */ -+ __be32 upde4; /* UTOPIA/POS device 4 event */ -+ __be16 uprp1; -+ __be16 uprp2; -+ __be16 uprp3; -+ __be16 uprp4; -+ u8 res1[0x8]; -+ __be16 uptirr1_0; /* Device 1 transmit internal rate 0 */ -+ __be16 uptirr1_1; /* Device 1 transmit internal rate 1 */ -+ __be16 uptirr1_2; /* Device 1 transmit internal rate 2 */ -+ __be16 uptirr1_3; /* Device 1 transmit internal rate 3 */ -+ __be16 uptirr2_0; /* Device 2 transmit internal rate 0 */ -+ __be16 uptirr2_1; /* Device 2 transmit internal rate 1 */ -+ __be16 uptirr2_2; /* Device 2 transmit internal rate 2 */ -+ __be16 uptirr2_3; /* Device 2 transmit internal rate 3 */ -+ __be16 uptirr3_0; /* Device 3 transmit internal rate 0 */ -+ __be16 uptirr3_1; /* Device 3 transmit internal rate 1 */ -+ __be16 uptirr3_2; /* Device 3 transmit internal rate 2 */ -+ __be16 uptirr3_3; /* Device 3 transmit internal rate 3 */ -+ __be16 uptirr4_0; /* Device 4 transmit internal rate 0 */ -+ __be16 uptirr4_1; /* Device 4 transmit internal rate 1 */ -+ __be16 uptirr4_2; /* Device 4 transmit internal rate 2 */ -+ __be16 uptirr4_3; /* Device 4 transmit internal rate 3 */ -+ __be32 uper1; /* Device 1 port enable register */ -+ __be32 uper2; /* Device 2 port enable register */ -+ __be32 uper3; /* Device 3 port enable register */ -+ __be32 uper4; /* Device 4 port enable register */ -+ u8 res2[0x150]; -+} __packed; -+ -+/* SDMA */ -+struct sdma { -+ __be32 sdsr; /* Serial DMA status register */ -+ __be32 sdmr; /* Serial DMA mode register */ -+ __be32 sdtr1; /* SDMA system bus threshold register */ -+ __be32 sdtr2; /* SDMA secondary bus threshold register */ -+ __be32 sdhy1; /* SDMA system bus hysteresis register */ -+ __be32 sdhy2; /* SDMA secondary bus hysteresis register */ -+ __be32 sdta1; /* SDMA system bus address register */ -+ __be32 sdta2; /* SDMA secondary bus address register */ -+ __be32 sdtm1; /* SDMA system bus MSNUM register */ -+ __be32 sdtm2; /* SDMA secondary bus MSNUM register */ -+ u8 res0[0x10]; -+ __be32 sdaqr; /* SDMA address bus qualify register */ -+ __be32 sdaqmr; /* SDMA address bus qualify mask register */ -+ u8 res1[0x4]; -+ __be32 sdebcr; /* SDMA CAM entries base register */ -+ u8 res2[0x38]; -+} __packed; -+ -+/* Debug Space */ -+struct dbg { -+ __be32 bpdcr; /* Breakpoint debug command register */ -+ __be32 bpdsr; /* Breakpoint debug status register */ -+ __be32 bpdmr; /* Breakpoint debug mask register */ -+ __be32 bprmrr0; /* Breakpoint request mode risc register 0 */ -+ __be32 bprmrr1; /* Breakpoint request mode risc register 1 */ -+ u8 res0[0x8]; -+ __be32 bprmtr0; /* Breakpoint request mode trb register 0 */ -+ __be32 bprmtr1; /* Breakpoint request mode trb register 1 */ -+ u8 res1[0x8]; -+ __be32 bprmir; /* Breakpoint request mode immediate register */ -+ __be32 bprmsr; /* Breakpoint request mode serial register */ -+ __be32 bpemr; /* Breakpoint exit mode register */ -+ u8 res2[0x48]; -+} __packed; -+ -+/* -+ * RISC Special Registers (Trap and Breakpoint). These are described in -+ * the QE Developer's Handbook. -+ */ -+struct rsp { -+ __be32 tibcr[16]; /* Trap/instruction breakpoint control regs */ -+ u8 res0[64]; -+ __be32 ibcr0; -+ __be32 ibs0; -+ __be32 ibcnr0; -+ u8 res1[4]; -+ __be32 ibcr1; -+ __be32 ibs1; -+ __be32 ibcnr1; -+ __be32 npcr; -+ __be32 dbcr; -+ __be32 dbar; -+ __be32 dbamr; -+ __be32 dbsr; -+ __be32 dbcnr; -+ u8 res2[12]; -+ __be32 dbdr_h; -+ __be32 dbdr_l; -+ __be32 dbdmr_h; -+ __be32 dbdmr_l; -+ __be32 bsr; -+ __be32 bor; -+ __be32 bior; -+ u8 res3[4]; -+ __be32 iatr[4]; -+ __be32 eccr; /* Exception control configuration register */ -+ __be32 eicr; -+ u8 res4[0x100-0xf8]; -+} __packed; -+ -+struct qe_immap { -+ struct qe_iram iram; /* I-RAM */ -+ struct qe_ic_regs ic; /* Interrupt Controller */ -+ struct cp_qe cp; /* Communications Processor */ -+ struct qe_mux qmx; /* QE Multiplexer */ -+ struct qe_timers qet; /* QE Timers */ -+ struct spi spi[0x2]; /* spi */ -+ struct qe_mcc mcc; /* mcc */ -+ struct qe_brg brg; /* brg */ -+ struct qe_usb_ctlr usb; /* USB */ -+ struct si1 si1; /* SI */ -+ u8 res11[0x800]; -+ struct sir sir; /* SI Routing Tables */ -+ struct ucc ucc1; /* ucc1 */ -+ struct ucc ucc3; /* ucc3 */ -+ struct ucc ucc5; /* ucc5 */ -+ struct ucc ucc7; /* ucc7 */ -+ u8 res12[0x600]; -+ struct upc upc1; /* MultiPHY UTOPIA POS Ctrlr 1*/ -+ struct ucc ucc2; /* ucc2 */ -+ struct ucc ucc4; /* ucc4 */ -+ struct ucc ucc6; /* ucc6 */ -+ struct ucc ucc8; /* ucc8 */ -+ u8 res13[0x600]; -+ struct upc upc2; /* MultiPHY UTOPIA POS Ctrlr 2*/ -+ struct sdma sdma; /* SDMA */ -+ struct dbg dbg; /* 0x104080 - 0x1040FF -+ Debug Space */ -+ struct rsp rsp[0x2]; /* 0x104100 - 0x1042FF -+ RISC Special Registers -+ (Trap and Breakpoint) */ -+ u8 res14[0x300]; /* 0x104300 - 0x1045FF */ -+ u8 res15[0x3A00]; /* 0x104600 - 0x107FFF */ -+ u8 res16[0x8000]; /* 0x108000 - 0x110000 */ -+ u8 muram[0xC000]; /* 0x110000 - 0x11C000 -+ Multi-user RAM */ -+ u8 res17[0x24000]; /* 0x11C000 - 0x140000 */ -+ u8 res18[0xC0000]; /* 0x140000 - 0x200000 */ -+} __packed; -+ -+extern struct qe_immap __iomem *qe_immr; -+extern phys_addr_t get_qe_base(void); -+ -+/* -+ * Returns the offset within the QE address space of the given pointer. -+ * -+ * Note that the QE does not support 36-bit physical addresses, so if -+ * get_qe_base() returns a number above 4GB, the caller will probably fail. -+ */ -+static inline phys_addr_t immrbar_virt_to_phys(void *address) -+{ -+ void *q = (void *)qe_immr; -+ -+ /* Is it a MURAM address? */ -+ if ((address >= q) && (address < (q + QE_IMMAP_SIZE))) -+ return get_qe_base() + (address - q); -+ -+ /* It's an address returned by kmalloc */ -+ return virt_to_phys(address); -+} -+ -+#endif /* __KERNEL__ */ -+#endif /* _ASM_POWERPC_IMMAP_QE_H */ ---- /dev/null -+++ b/include/linux/fsl/qe.h -@@ -0,0 +1,810 @@ -+/* -+ * Copyright (C) 2006, 2012 Freescale Semiconductor, Inc. All rights reserved. -+ * -+ * Authors: Shlomi Gridish <gridish@freescale.com> -+ * Li Yang <leoli@freescale.com> -+ * -+ * Description: -+ * QUICC Engine (QE) external definitions and structure. -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License as published by the -+ * Free Software Foundation; either version 2 of the License, or (at your -+ * option) any later version. -+ */ -+#ifndef _ASM_POWERPC_QE_H -+#define _ASM_POWERPC_QE_H -+#ifdef __KERNEL__ -+ -+#include <linux/spinlock.h> -+#include <linux/errno.h> -+#include <linux/err.h> -+#include <linux/of.h> -+#include <linux/of_address.h> -+#include <linux/fsl/immap_qe.h> -+ -+#define QE_NUM_OF_SNUM 256 /* There are 256 serial number in QE */ -+#define QE_NUM_OF_BRGS 16 -+#define QE_NUM_OF_PORTS 1024 -+ -+/* Memory partitions -+*/ -+#define MEM_PART_SYSTEM 0 -+#define MEM_PART_SECONDARY 1 -+#define MEM_PART_MURAM 2 -+ -+extern int siram_init_flag; -+ -+/* Clocks and BRGs */ -+enum qe_clock { -+ QE_CLK_NONE = 0, -+ QE_BRG1, /* Baud Rate Generator 1 */ -+ QE_BRG2, /* Baud Rate Generator 2 */ -+ QE_BRG3, /* Baud Rate Generator 3 */ -+ QE_BRG4, /* Baud Rate Generator 4 */ -+ QE_BRG5, /* Baud Rate Generator 5 */ -+ QE_BRG6, /* Baud Rate Generator 6 */ -+ QE_BRG7, /* Baud Rate Generator 7 */ -+ QE_BRG8, /* Baud Rate Generator 8 */ -+ QE_BRG9, /* Baud Rate Generator 9 */ -+ QE_BRG10, /* Baud Rate Generator 10 */ -+ QE_BRG11, /* Baud Rate Generator 11 */ -+ QE_BRG12, /* Baud Rate Generator 12 */ -+ QE_BRG13, /* Baud Rate Generator 13 */ -+ QE_BRG14, /* Baud Rate Generator 14 */ -+ QE_BRG15, /* Baud Rate Generator 15 */ -+ QE_BRG16, /* Baud Rate Generator 16 */ -+ QE_CLK1, /* Clock 1 */ -+ QE_CLK2, /* Clock 2 */ -+ QE_CLK3, /* Clock 3 */ -+ QE_CLK4, /* Clock 4 */ -+ QE_CLK5, /* Clock 5 */ -+ QE_CLK6, /* Clock 6 */ -+ QE_CLK7, /* Clock 7 */ -+ QE_CLK8, /* Clock 8 */ -+ QE_CLK9, /* Clock 9 */ -+ QE_CLK10, /* Clock 10 */ -+ QE_CLK11, /* Clock 11 */ -+ QE_CLK12, /* Clock 12 */ -+ QE_CLK13, /* Clock 13 */ -+ QE_CLK14, /* Clock 14 */ -+ QE_CLK15, /* Clock 15 */ -+ QE_CLK16, /* Clock 16 */ -+ QE_CLK17, /* Clock 17 */ -+ QE_CLK18, /* Clock 18 */ -+ QE_CLK19, /* Clock 19 */ -+ QE_CLK20, /* Clock 20 */ -+ QE_CLK21, /* Clock 21 */ -+ QE_CLK22, /* Clock 22 */ -+ QE_CLK23, /* Clock 23 */ -+ QE_CLK24, /* Clock 24 */ -+ QE_RSYNC_PIN, /* RSYNC from pin */ -+ QE_TSYNC_PIN, /* TSYNC from pin */ -+ QE_CLK_DUMMY -+}; -+ -+static inline bool qe_clock_is_brg(enum qe_clock clk) -+{ -+ return clk >= QE_BRG1 && clk <= QE_BRG16; -+} -+ -+extern spinlock_t cmxgcr_lock; -+ -+/* Export QE common operations */ -+#ifdef CONFIG_QUICC_ENGINE -+extern void qe_reset(void); -+#else -+static inline void qe_reset(void) {} -+#endif -+ -+/* QE PIO */ -+#define QE_PIO_PINS 32 -+ -+struct qe_pio_regs { -+ __be32 cpodr; /* Open drain register */ -+ __be32 cpdata; /* Data register */ -+ __be32 cpdir1; /* Direction register */ -+ __be32 cpdir2; /* Direction register */ -+ __be32 cppar1; /* Pin assignment register */ -+ __be32 cppar2; /* Pin assignment register */ -+#ifdef CONFIG_PPC_85xx -+ u8 pad[8]; -+#endif -+}; -+ -+#define QE_PIO_DIR_IN 2 -+#define QE_PIO_DIR_OUT 1 -+extern void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, -+ int dir, int open_drain, int assignment, -+ int has_irq); -+#ifdef CONFIG_QUICC_ENGINE -+extern int par_io_init(struct device_node *np); -+extern int par_io_of_config(struct device_node *np); -+extern int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, -+ int assignment, int has_irq); -+extern int par_io_data_set(u8 port, u8 pin, u8 val); -+#else -+static inline int par_io_init(struct device_node *np) { return -ENOSYS; } -+static inline int par_io_of_config(struct device_node *np) { return -ENOSYS; } -+static inline int par_io_config_pin(u8 port, u8 pin, int dir, int open_drain, -+ int assignment, int has_irq) { return -ENOSYS; } -+static inline int par_io_data_set(u8 port, u8 pin, u8 val) { return -ENOSYS; } -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* -+ * Pin multiplexing functions. -+ */ -+struct qe_pin; -+#ifdef CONFIG_QE_GPIO -+extern struct qe_pin *qe_pin_request(struct device_node *np, int index); -+extern void qe_pin_free(struct qe_pin *qe_pin); -+extern void qe_pin_set_gpio(struct qe_pin *qe_pin); -+extern void qe_pin_set_dedicated(struct qe_pin *pin); -+#else -+static inline struct qe_pin *qe_pin_request(struct device_node *np, int index) -+{ -+ return ERR_PTR(-ENOSYS); -+} -+static inline void qe_pin_free(struct qe_pin *qe_pin) {} -+static inline void qe_pin_set_gpio(struct qe_pin *qe_pin) {} -+static inline void qe_pin_set_dedicated(struct qe_pin *pin) {} -+#endif /* CONFIG_QE_GPIO */ -+ -+#ifdef CONFIG_QUICC_ENGINE -+int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input); -+#else -+static inline int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, -+ u32 cmd_input) -+{ -+ return -ENOSYS; -+} -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* QE internal API */ -+enum qe_clock qe_clock_source(const char *source); -+unsigned int qe_get_brg_clk(void); -+int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier); -+int qe_get_snum(void); -+void qe_put_snum(u8 snum); -+unsigned int qe_get_num_of_risc(void); -+unsigned int qe_get_num_of_snums(void); -+ -+static inline int qe_alive_during_sleep(void) -+{ -+ /* -+ * MPC8568E reference manual says: -+ * -+ * "...power down sequence waits for all I/O interfaces to become idle. -+ * In some applications this may happen eventually without actively -+ * shutting down interfaces, but most likely, software will have to -+ * take steps to shut down the eTSEC, QUICC Engine Block, and PCI -+ * interfaces before issuing the command (either the write to the core -+ * MSR[WE] as described above or writing to POWMGTCSR) to put the -+ * device into sleep state." -+ * -+ * MPC8569E reference manual has a similar paragraph. -+ */ -+#ifdef CONFIG_PPC_85xx -+ return 0; -+#else -+ return 1; -+#endif -+} -+ -+int qe_muram_init(void); -+ -+#if defined(CONFIG_QUICC_ENGINE) -+unsigned long qe_muram_alloc(unsigned long size, unsigned long align); -+int qe_muram_free(unsigned long offset); -+unsigned long qe_muram_alloc_fixed(unsigned long offset, unsigned long size); -+void __iomem *qe_muram_addr(unsigned long offset); -+unsigned long qe_muram_offset(void __iomem *addr); -+dma_addr_t qe_muram_dma(void __iomem *addr); -+#else -+static inline unsigned long qe_muram_alloc(unsigned long size, -+ unsigned long align) -+{ -+ return -ENOSYS; -+} -+ -+static inline int qe_muram_free(unsigned long offset) -+{ -+ return -ENOSYS; -+} -+ -+static inline unsigned long qe_muram_alloc_fixed(unsigned long offset, -+ unsigned long size) -+{ -+ return -ENOSYS; -+} -+ -+static inline void __iomem *qe_muram_addr(unsigned long offset) -+{ -+ return NULL; -+} -+ -+static inline unsigned long qe_muram_offset(void __iomem *addr) -+{ -+ return -ENOSYS; -+} -+ -+static inline dma_addr_t qe_muram_dma(void __iomem *addr) -+{ -+ return 0; -+} -+#endif /* defined(CONFIG_QUICC_ENGINE) */ -+ -+/* Structure that defines QE firmware binary files. -+ * -+ * See Documentation/powerpc/qe_firmware.txt for a description of these -+ * fields. -+ */ -+struct qe_firmware { -+ struct qe_header { -+ __be32 length; /* Length of the entire structure, in bytes */ -+ u8 magic[3]; /* Set to { 'Q', 'E', 'F' } */ -+ u8 version; /* Version of this layout. First ver is '1' */ -+ } header; -+ u8 id[62]; /* Null-terminated identifier string */ -+ u8 split; /* 0 = shared I-RAM, 1 = split I-RAM */ -+ u8 count; /* Number of microcode[] structures */ -+ struct { -+ __be16 model; /* The SOC model */ -+ u8 major; /* The SOC revision major */ -+ u8 minor; /* The SOC revision minor */ -+ } __packed soc; -+ u8 padding[4]; /* Reserved, for alignment */ -+ __be64 extended_modes; /* Extended modes */ -+ __be32 vtraps[8]; /* Virtual trap addresses */ -+ u8 reserved[4]; /* Reserved, for future expansion */ -+ struct qe_microcode { -+ u8 id[32]; /* Null-terminated identifier */ -+ __be32 traps[16]; /* Trap addresses, 0 == ignore */ -+ __be32 eccr; /* The value for the ECCR register */ -+ __be32 iram_offset; /* Offset into I-RAM for the code */ -+ __be32 count; /* Number of 32-bit words of the code */ -+ __be32 code_offset; /* Offset of the actual microcode */ -+ u8 major; /* The microcode version major */ -+ u8 minor; /* The microcode version minor */ -+ u8 revision; /* The microcode version revision */ -+ u8 padding; /* Reserved, for alignment */ -+ u8 reserved[4]; /* Reserved, for future expansion */ -+ } __packed microcode[1]; -+ /* All microcode binaries should be located here */ -+ /* CRC32 should be located here, after the microcode binaries */ -+} __packed; -+ -+struct qe_firmware_info { -+ char id[64]; /* Firmware name */ -+ u32 vtraps[8]; /* Virtual trap addresses */ -+ u64 extended_modes; /* Extended modes */ -+}; -+ -+#ifdef CONFIG_QUICC_ENGINE -+/* Upload a firmware to the QE */ -+int qe_upload_firmware(const struct qe_firmware *firmware); -+#else -+static inline int qe_upload_firmware(const struct qe_firmware *firmware) -+{ -+ return -ENOSYS; -+} -+#endif /* CONFIG_QUICC_ENGINE */ -+ -+/* Obtain information on the uploaded firmware */ -+struct qe_firmware_info *qe_get_firmware_info(void); -+ -+/* QE USB */ -+int qe_usb_clock_set(enum qe_clock clk, int rate); -+ -+/* Buffer descriptors */ -+struct qe_bd { -+ __be16 status; -+ __be16 length; -+ __be32 buf; -+} __packed; -+ -+#define BD_STATUS_MASK 0xffff0000 -+#define BD_LENGTH_MASK 0x0000ffff -+ -+/* Buffer descriptor control/status used by serial -+ */ -+ -+#define BD_SC_EMPTY (0x8000) /* Receive is empty */ -+#define BD_SC_READY (0x8000) /* Transmit is ready */ -+#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */ -+#define BD_SC_INTRPT (0x1000) /* Interrupt on change */ -+#define BD_SC_LAST (0x0800) /* Last buffer in frame */ -+#define BD_SC_TC (0x0400) /* Transmit CRC */ -+#define BD_SC_CM (0x0200) /* Continuous mode */ -+#define BD_SC_ID (0x0100) /* Rec'd too many idles */ -+#define BD_SC_P (0x0100) /* xmt preamble */ -+#define BD_SC_BR (0x0020) /* Break received */ -+#define BD_SC_FR (0x0010) /* Framing error */ -+#define BD_SC_PR (0x0008) /* Parity error */ -+#define BD_SC_NAK (0x0004) /* NAK - did not respond */ -+#define BD_SC_OV (0x0002) /* Overrun */ -+#define BD_SC_UN (0x0002) /* Underrun */ -+#define BD_SC_CD (0x0001) /* */ -+#define BD_SC_CL (0x0001) /* Collision */ -+ -+/* Alignment */ -+#define QE_INTR_TABLE_ALIGN 16 /* ??? */ -+#define QE_ALIGNMENT_OF_BD 8 -+#define QE_ALIGNMENT_OF_PRAM 64 -+ -+/* RISC allocation */ -+#define QE_RISC_ALLOCATION_RISC1 0x1 /* RISC 1 */ -+#define QE_RISC_ALLOCATION_RISC2 0x2 /* RISC 2 */ -+#define QE_RISC_ALLOCATION_RISC3 0x4 /* RISC 3 */ -+#define QE_RISC_ALLOCATION_RISC4 0x8 /* RISC 4 */ -+#define QE_RISC_ALLOCATION_RISC1_AND_RISC2 (QE_RISC_ALLOCATION_RISC1 | \ -+ QE_RISC_ALLOCATION_RISC2) -+#define QE_RISC_ALLOCATION_FOUR_RISCS (QE_RISC_ALLOCATION_RISC1 | \ -+ QE_RISC_ALLOCATION_RISC2 | \ -+ QE_RISC_ALLOCATION_RISC3 | \ -+ QE_RISC_ALLOCATION_RISC4) -+ -+/* QE extended filtering Table Lookup Key Size */ -+enum qe_fltr_tbl_lookup_key_size { -+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES -+ = 0x3f, /* LookupKey parsed by the Generate LookupKey -+ CMD is truncated to 8 bytes */ -+ QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES -+ = 0x5f, /* LookupKey parsed by the Generate LookupKey -+ CMD is truncated to 16 bytes */ -+}; -+ -+/* QE FLTR extended filtering Largest External Table Lookup Key Size */ -+enum qe_fltr_largest_external_tbl_lookup_key_size { -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_NONE -+ = 0x0,/* not used */ -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_8_BYTES -+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_8_BYTES, /* 8 bytes */ -+ QE_FLTR_LARGEST_EXTERNAL_TABLE_LOOKUP_KEY_SIZE_16_BYTES -+ = QE_FLTR_TABLE_LOOKUP_KEY_SIZE_16_BYTES, /* 16 bytes */ -+}; -+ -+/* structure representing QE parameter RAM */ -+struct qe_timer_tables { -+ u16 tm_base; /* QE timer table base adr */ -+ u16 tm_ptr; /* QE timer table pointer */ -+ u16 r_tmr; /* QE timer mode register */ -+ u16 r_tmv; /* QE timer valid register */ -+ u32 tm_cmd; /* QE timer cmd register */ -+ u32 tm_cnt; /* QE timer internal cnt */ -+} __packed; -+ -+#define QE_FLTR_TAD_SIZE 8 -+ -+/* QE extended filtering Termination Action Descriptor (TAD) */ -+struct qe_fltr_tad { -+ u8 serialized[QE_FLTR_TAD_SIZE]; -+} __packed; -+ -+/* Communication Direction */ -+enum comm_dir { -+ COMM_DIR_NONE = 0, -+ COMM_DIR_RX = 1, -+ COMM_DIR_TX = 2, -+ COMM_DIR_RX_AND_TX = 3 -+}; -+ -+/* QE CMXUCR Registers. -+ * There are two UCCs represented in each of the four CMXUCR registers. -+ * These values are for the UCC in the LSBs -+ */ -+#define QE_CMXUCR_MII_ENET_MNG 0x00007000 -+#define QE_CMXUCR_MII_ENET_MNG_SHIFT 12 -+#define QE_CMXUCR_GRANT 0x00008000 -+#define QE_CMXUCR_TSA 0x00004000 -+#define QE_CMXUCR_BKPT 0x00000100 -+#define QE_CMXUCR_TX_CLK_SRC_MASK 0x0000000F -+ -+/* QE CMXGCR Registers. -+*/ -+#define QE_CMXGCR_MII_ENET_MNG 0x00007000 -+#define QE_CMXGCR_MII_ENET_MNG_SHIFT 12 -+#define QE_CMXGCR_USBCS 0x0000000f -+#define QE_CMXGCR_USBCS_CLK3 0x1 -+#define QE_CMXGCR_USBCS_CLK5 0x2 -+#define QE_CMXGCR_USBCS_CLK7 0x3 -+#define QE_CMXGCR_USBCS_CLK9 0x4 -+#define QE_CMXGCR_USBCS_CLK13 0x5 -+#define QE_CMXGCR_USBCS_CLK17 0x6 -+#define QE_CMXGCR_USBCS_CLK19 0x7 -+#define QE_CMXGCR_USBCS_CLK21 0x8 -+#define QE_CMXGCR_USBCS_BRG9 0x9 -+#define QE_CMXGCR_USBCS_BRG10 0xa -+ -+/* QE CECR Commands. -+*/ -+#define QE_CR_FLG 0x00010000 -+#define QE_RESET 0x80000000 -+#define QE_INIT_TX_RX 0x00000000 -+#define QE_INIT_RX 0x00000001 -+#define QE_INIT_TX 0x00000002 -+#define QE_ENTER_HUNT_MODE 0x00000003 -+#define QE_STOP_TX 0x00000004 -+#define QE_GRACEFUL_STOP_TX 0x00000005 -+#define QE_RESTART_TX 0x00000006 -+#define QE_CLOSE_RX_BD 0x00000007 -+#define QE_SWITCH_COMMAND 0x00000007 -+#define QE_SET_GROUP_ADDRESS 0x00000008 -+#define QE_START_IDMA 0x00000009 -+#define QE_MCC_STOP_RX 0x00000009 -+#define QE_ATM_TRANSMIT 0x0000000a -+#define QE_HPAC_CLEAR_ALL 0x0000000b -+#define QE_GRACEFUL_STOP_RX 0x0000001a -+#define QE_RESTART_RX 0x0000001b -+#define QE_HPAC_SET_PRIORITY 0x0000010b -+#define QE_HPAC_STOP_TX 0x0000020b -+#define QE_HPAC_STOP_RX 0x0000030b -+#define QE_HPAC_GRACEFUL_STOP_TX 0x0000040b -+#define QE_HPAC_GRACEFUL_STOP_RX 0x0000050b -+#define QE_HPAC_START_TX 0x0000060b -+#define QE_HPAC_START_RX 0x0000070b -+#define QE_USB_STOP_TX 0x0000000a -+#define QE_USB_RESTART_TX 0x0000000c -+#define QE_QMC_STOP_TX 0x0000000c -+#define QE_QMC_STOP_RX 0x0000000d -+#define QE_SS7_SU_FIL_RESET 0x0000000e -+/* jonathbr added from here down for 83xx */ -+#define QE_RESET_BCS 0x0000000a -+#define QE_MCC_INIT_TX_RX_16 0x00000003 -+#define QE_MCC_STOP_TX 0x00000004 -+#define QE_MCC_INIT_TX_1 0x00000005 -+#define QE_MCC_INIT_RX_1 0x00000006 -+#define QE_MCC_RESET 0x00000007 -+#define QE_SET_TIMER 0x00000008 -+#define QE_RANDOM_NUMBER 0x0000000c -+#define QE_ATM_MULTI_THREAD_INIT 0x00000011 -+#define QE_ASSIGN_PAGE 0x00000012 -+#define QE_ADD_REMOVE_HASH_ENTRY 0x00000013 -+#define QE_START_FLOW_CONTROL 0x00000014 -+#define QE_STOP_FLOW_CONTROL 0x00000015 -+#define QE_ASSIGN_PAGE_TO_DEVICE 0x00000016 -+ -+#define QE_ASSIGN_RISC 0x00000010 -+#define QE_CR_MCN_NORMAL_SHIFT 6 -+#define QE_CR_MCN_USB_SHIFT 4 -+#define QE_CR_MCN_RISC_ASSIGN_SHIFT 8 -+#define QE_CR_SNUM_SHIFT 17 -+ -+/* QE CECR Sub Block - sub block of QE command. -+*/ -+#define QE_CR_SUBBLOCK_INVALID 0x00000000 -+#define QE_CR_SUBBLOCK_USB 0x03200000 -+#define QE_CR_SUBBLOCK_UCCFAST1 0x02000000 -+#define QE_CR_SUBBLOCK_UCCFAST2 0x02200000 -+#define QE_CR_SUBBLOCK_UCCFAST3 0x02400000 -+#define QE_CR_SUBBLOCK_UCCFAST4 0x02600000 -+#define QE_CR_SUBBLOCK_UCCFAST5 0x02800000 -+#define QE_CR_SUBBLOCK_UCCFAST6 0x02a00000 -+#define QE_CR_SUBBLOCK_UCCFAST7 0x02c00000 -+#define QE_CR_SUBBLOCK_UCCFAST8 0x02e00000 -+#define QE_CR_SUBBLOCK_UCCSLOW1 0x00000000 -+#define QE_CR_SUBBLOCK_UCCSLOW2 0x00200000 -+#define QE_CR_SUBBLOCK_UCCSLOW3 0x00400000 -+#define QE_CR_SUBBLOCK_UCCSLOW4 0x00600000 -+#define QE_CR_SUBBLOCK_UCCSLOW5 0x00800000 -+#define QE_CR_SUBBLOCK_UCCSLOW6 0x00a00000 -+#define QE_CR_SUBBLOCK_UCCSLOW7 0x00c00000 -+#define QE_CR_SUBBLOCK_UCCSLOW8 0x00e00000 -+#define QE_CR_SUBBLOCK_MCC1 0x03800000 -+#define QE_CR_SUBBLOCK_MCC2 0x03a00000 -+#define QE_CR_SUBBLOCK_MCC3 0x03000000 -+#define QE_CR_SUBBLOCK_IDMA1 0x02800000 -+#define QE_CR_SUBBLOCK_IDMA2 0x02a00000 -+#define QE_CR_SUBBLOCK_IDMA3 0x02c00000 -+#define QE_CR_SUBBLOCK_IDMA4 0x02e00000 -+#define QE_CR_SUBBLOCK_HPAC 0x01e00000 -+#define QE_CR_SUBBLOCK_SPI1 0x01400000 -+#define QE_CR_SUBBLOCK_SPI2 0x01600000 -+#define QE_CR_SUBBLOCK_RAND 0x01c00000 -+#define QE_CR_SUBBLOCK_TIMER 0x01e00000 -+#define QE_CR_SUBBLOCK_GENERAL 0x03c00000 -+ -+/* QE CECR Protocol - For non-MCC, specifies mode for QE CECR command */ -+#define QE_CR_PROTOCOL_UNSPECIFIED 0x00 /* For all other protocols */ -+#define QE_CR_PROTOCOL_HDLC_TRANSPARENT 0x00 -+#define QE_CR_PROTOCOL_QMC 0x02 -+#define QE_CR_PROTOCOL_UART 0x04 -+#define QE_CR_PROTOCOL_ATM_POS 0x0A -+#define QE_CR_PROTOCOL_ETHERNET 0x0C -+#define QE_CR_PROTOCOL_L2_SWITCH 0x0D -+ -+/* BRG configuration register */ -+#define QE_BRGC_ENABLE 0x00010000 -+#define QE_BRGC_DIVISOR_SHIFT 1 -+#define QE_BRGC_DIVISOR_MAX 0xFFF -+#define QE_BRGC_DIV16 1 -+ -+/* QE Timers registers */ -+#define QE_GTCFR1_PCAS 0x80 -+#define QE_GTCFR1_STP2 0x20 -+#define QE_GTCFR1_RST2 0x10 -+#define QE_GTCFR1_GM2 0x08 -+#define QE_GTCFR1_GM1 0x04 -+#define QE_GTCFR1_STP1 0x02 -+#define QE_GTCFR1_RST1 0x01 -+ -+/* SDMA registers */ -+#define QE_SDSR_BER1 0x02000000 -+#define QE_SDSR_BER2 0x01000000 -+ -+#define QE_SDMR_GLB_1_MSK 0x80000000 -+#define QE_SDMR_ADR_SEL 0x20000000 -+#define QE_SDMR_BER1_MSK 0x02000000 -+#define QE_SDMR_BER2_MSK 0x01000000 -+#define QE_SDMR_EB1_MSK 0x00800000 -+#define QE_SDMR_ER1_MSK 0x00080000 -+#define QE_SDMR_ER2_MSK 0x00040000 -+#define QE_SDMR_CEN_MASK 0x0000E000 -+#define QE_SDMR_SBER_1 0x00000200 -+#define QE_SDMR_SBER_2 0x00000200 -+#define QE_SDMR_EB1_PR_MASK 0x000000C0 -+#define QE_SDMR_ER1_PR 0x00000008 -+ -+#define QE_SDMR_CEN_SHIFT 13 -+#define QE_SDMR_EB1_PR_SHIFT 6 -+ -+#define QE_SDTM_MSNUM_SHIFT 24 -+ -+#define QE_SDEBCR_BA_MASK 0x01FFFFFF -+ -+/* Communication Processor */ -+#define QE_CP_CERCR_MEE 0x8000 /* Multi-user RAM ECC enable */ -+#define QE_CP_CERCR_IEE 0x4000 /* Instruction RAM ECC enable */ -+#define QE_CP_CERCR_CIR 0x0800 /* Common instruction RAM */ -+ -+/* I-RAM */ -+#define QE_IRAM_IADD_AIE 0x80000000 /* Auto Increment Enable */ -+#define QE_IRAM_IADD_BADDR 0x00080000 /* Base Address */ -+#define QE_IRAM_READY 0x80000000 /* Ready */ -+ -+/* UPC */ -+#define UPGCR_PROTOCOL 0x80000000 /* protocol ul2 or pl2 */ -+#define UPGCR_TMS 0x40000000 /* Transmit master/slave mode */ -+#define UPGCR_RMS 0x20000000 /* Receive master/slave mode */ -+#define UPGCR_ADDR 0x10000000 /* Master MPHY Addr multiplexing */ -+#define UPGCR_DIAG 0x01000000 /* Diagnostic mode */ -+ -+/* UCC GUEMR register */ -+#define UCC_GUEMR_MODE_MASK_RX 0x02 -+#define UCC_GUEMR_MODE_FAST_RX 0x02 -+#define UCC_GUEMR_MODE_SLOW_RX 0x00 -+#define UCC_GUEMR_MODE_MASK_TX 0x01 -+#define UCC_GUEMR_MODE_FAST_TX 0x01 -+#define UCC_GUEMR_MODE_SLOW_TX 0x00 -+#define UCC_GUEMR_MODE_MASK (UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX) -+#define UCC_GUEMR_SET_RESERVED3 0x10 /* Bit 3 in the guemr is reserved but -+ must be set 1 */ -+ -+/* structure representing UCC SLOW parameter RAM */ -+struct ucc_slow_pram { -+ __be16 rbase; /* RX BD base address */ -+ __be16 tbase; /* TX BD base address */ -+ u8 rbmr; /* RX bus mode register (same as CPM's RFCR) */ -+ u8 tbmr; /* TX bus mode register (same as CPM's TFCR) */ -+ __be16 mrblr; /* Rx buffer length */ -+ __be32 rstate; /* Rx internal state */ -+ __be32 rptr; /* Rx internal data pointer */ -+ __be16 rbptr; /* rb BD Pointer */ -+ __be16 rcount; /* Rx internal byte count */ -+ __be32 rtemp; /* Rx temp */ -+ __be32 tstate; /* Tx internal state */ -+ __be32 tptr; /* Tx internal data pointer */ -+ __be16 tbptr; /* Tx BD pointer */ -+ __be16 tcount; /* Tx byte count */ -+ __be32 ttemp; /* Tx temp */ -+ __be32 rcrc; /* temp receive CRC */ -+ __be32 tcrc; /* temp transmit CRC */ -+} __packed; -+ -+/* General UCC SLOW Mode Register (GUMRH & GUMRL) */ -+#define UCC_SLOW_GUMR_H_SAM_QMC 0x00000000 -+#define UCC_SLOW_GUMR_H_SAM_SATM 0x00008000 -+#define UCC_SLOW_GUMR_H_REVD 0x00002000 -+#define UCC_SLOW_GUMR_H_TRX 0x00001000 -+#define UCC_SLOW_GUMR_H_TTX 0x00000800 -+#define UCC_SLOW_GUMR_H_CDP 0x00000400 -+#define UCC_SLOW_GUMR_H_CTSP 0x00000200 -+#define UCC_SLOW_GUMR_H_CDS 0x00000100 -+#define UCC_SLOW_GUMR_H_CTSS 0x00000080 -+#define UCC_SLOW_GUMR_H_TFL 0x00000040 -+#define UCC_SLOW_GUMR_H_RFW 0x00000020 -+#define UCC_SLOW_GUMR_H_TXSY 0x00000010 -+#define UCC_SLOW_GUMR_H_4SYNC 0x00000004 -+#define UCC_SLOW_GUMR_H_8SYNC 0x00000008 -+#define UCC_SLOW_GUMR_H_16SYNC 0x0000000c -+#define UCC_SLOW_GUMR_H_RTSM 0x00000002 -+#define UCC_SLOW_GUMR_H_RSYN 0x00000001 -+ -+#define UCC_SLOW_GUMR_L_TCI 0x10000000 -+#define UCC_SLOW_GUMR_L_RINV 0x02000000 -+#define UCC_SLOW_GUMR_L_TINV 0x01000000 -+#define UCC_SLOW_GUMR_L_TEND 0x00040000 -+#define UCC_SLOW_GUMR_L_TDCR_MASK 0x00030000 -+#define UCC_SLOW_GUMR_L_TDCR_32 0x00030000 -+#define UCC_SLOW_GUMR_L_TDCR_16 0x00020000 -+#define UCC_SLOW_GUMR_L_TDCR_8 0x00010000 -+#define UCC_SLOW_GUMR_L_TDCR_1 0x00000000 -+#define UCC_SLOW_GUMR_L_RDCR_MASK 0x0000c000 -+#define UCC_SLOW_GUMR_L_RDCR_32 0x0000c000 -+#define UCC_SLOW_GUMR_L_RDCR_16 0x00008000 -+#define UCC_SLOW_GUMR_L_RDCR_8 0x00004000 -+#define UCC_SLOW_GUMR_L_RDCR_1 0x00000000 -+#define UCC_SLOW_GUMR_L_RENC_NRZI 0x00000800 -+#define UCC_SLOW_GUMR_L_RENC_NRZ 0x00000000 -+#define UCC_SLOW_GUMR_L_TENC_NRZI 0x00000100 -+#define UCC_SLOW_GUMR_L_TENC_NRZ 0x00000000 -+#define UCC_SLOW_GUMR_L_DIAG_MASK 0x000000c0 -+#define UCC_SLOW_GUMR_L_DIAG_LE 0x000000c0 -+#define UCC_SLOW_GUMR_L_DIAG_ECHO 0x00000080 -+#define UCC_SLOW_GUMR_L_DIAG_LOOP 0x00000040 -+#define UCC_SLOW_GUMR_L_DIAG_NORM 0x00000000 -+#define UCC_SLOW_GUMR_L_ENR 0x00000020 -+#define UCC_SLOW_GUMR_L_ENT 0x00000010 -+#define UCC_SLOW_GUMR_L_MODE_MASK 0x0000000F -+#define UCC_SLOW_GUMR_L_MODE_BISYNC 0x00000008 -+#define UCC_SLOW_GUMR_L_MODE_AHDLC 0x00000006 -+#define UCC_SLOW_GUMR_L_MODE_UART 0x00000004 -+#define UCC_SLOW_GUMR_L_MODE_QMC 0x00000002 -+ -+/* General UCC FAST Mode Register */ -+#define UCC_FAST_GUMR_TCI 0x20000000 -+#define UCC_FAST_GUMR_TRX 0x10000000 -+#define UCC_FAST_GUMR_TTX 0x08000000 -+#define UCC_FAST_GUMR_CDP 0x04000000 -+#define UCC_FAST_GUMR_CTSP 0x02000000 -+#define UCC_FAST_GUMR_CDS 0x01000000 -+#define UCC_FAST_GUMR_CTSS 0x00800000 -+#define UCC_FAST_GUMR_TXSY 0x00020000 -+#define UCC_FAST_GUMR_RSYN 0x00010000 -+#define UCC_FAST_GUMR_RTSM 0x00002000 -+#define UCC_FAST_GUMR_REVD 0x00000400 -+#define UCC_FAST_GUMR_ENR 0x00000020 -+#define UCC_FAST_GUMR_ENT 0x00000010 -+ -+/* UART Slow UCC Event Register (UCCE) */ -+#define UCC_UART_UCCE_AB 0x0200 -+#define UCC_UART_UCCE_IDLE 0x0100 -+#define UCC_UART_UCCE_GRA 0x0080 -+#define UCC_UART_UCCE_BRKE 0x0040 -+#define UCC_UART_UCCE_BRKS 0x0020 -+#define UCC_UART_UCCE_CCR 0x0008 -+#define UCC_UART_UCCE_BSY 0x0004 -+#define UCC_UART_UCCE_TX 0x0002 -+#define UCC_UART_UCCE_RX 0x0001 -+ -+/* HDLC Slow UCC Event Register (UCCE) */ -+#define UCC_HDLC_UCCE_GLR 0x1000 -+#define UCC_HDLC_UCCE_GLT 0x0800 -+#define UCC_HDLC_UCCE_IDLE 0x0100 -+#define UCC_HDLC_UCCE_BRKE 0x0040 -+#define UCC_HDLC_UCCE_BRKS 0x0020 -+#define UCC_HDLC_UCCE_TXE 0x0010 -+#define UCC_HDLC_UCCE_RXF 0x0008 -+#define UCC_HDLC_UCCE_BSY 0x0004 -+#define UCC_HDLC_UCCE_TXB 0x0002 -+#define UCC_HDLC_UCCE_RXB 0x0001 -+ -+/* BISYNC Slow UCC Event Register (UCCE) */ -+#define UCC_BISYNC_UCCE_GRA 0x0080 -+#define UCC_BISYNC_UCCE_TXE 0x0010 -+#define UCC_BISYNC_UCCE_RCH 0x0008 -+#define UCC_BISYNC_UCCE_BSY 0x0004 -+#define UCC_BISYNC_UCCE_TXB 0x0002 -+#define UCC_BISYNC_UCCE_RXB 0x0001 -+ -+/* Transparent UCC Event Register (UCCE) */ -+#define UCC_TRANS_UCCE_GRA 0x0080 -+#define UCC_TRANS_UCCE_TXE 0x0010 -+#define UCC_TRANS_UCCE_RXF 0x0008 -+#define UCC_TRANS_UCCE_BSY 0x0004 -+#define UCC_TRANS_UCCE_TXB 0x0002 -+#define UCC_TRANS_UCCE_RXB 0x0001 -+ -+ -+/* Gigabit Ethernet Fast UCC Event Register (UCCE) */ -+#define UCC_GETH_UCCE_MPD 0x80000000 -+#define UCC_GETH_UCCE_SCAR 0x40000000 -+#define UCC_GETH_UCCE_GRA 0x20000000 -+#define UCC_GETH_UCCE_CBPR 0x10000000 -+#define UCC_GETH_UCCE_BSY 0x08000000 -+#define UCC_GETH_UCCE_RXC 0x04000000 -+#define UCC_GETH_UCCE_TXC 0x02000000 -+#define UCC_GETH_UCCE_TXE 0x01000000 -+#define UCC_GETH_UCCE_TXB7 0x00800000 -+#define UCC_GETH_UCCE_TXB6 0x00400000 -+#define UCC_GETH_UCCE_TXB5 0x00200000 -+#define UCC_GETH_UCCE_TXB4 0x00100000 -+#define UCC_GETH_UCCE_TXB3 0x00080000 -+#define UCC_GETH_UCCE_TXB2 0x00040000 -+#define UCC_GETH_UCCE_TXB1 0x00020000 -+#define UCC_GETH_UCCE_TXB0 0x00010000 -+#define UCC_GETH_UCCE_RXB7 0x00008000 -+#define UCC_GETH_UCCE_RXB6 0x00004000 -+#define UCC_GETH_UCCE_RXB5 0x00002000 -+#define UCC_GETH_UCCE_RXB4 0x00001000 -+#define UCC_GETH_UCCE_RXB3 0x00000800 -+#define UCC_GETH_UCCE_RXB2 0x00000400 -+#define UCC_GETH_UCCE_RXB1 0x00000200 -+#define UCC_GETH_UCCE_RXB0 0x00000100 -+#define UCC_GETH_UCCE_RXF7 0x00000080 -+#define UCC_GETH_UCCE_RXF6 0x00000040 -+#define UCC_GETH_UCCE_RXF5 0x00000020 -+#define UCC_GETH_UCCE_RXF4 0x00000010 -+#define UCC_GETH_UCCE_RXF3 0x00000008 -+#define UCC_GETH_UCCE_RXF2 0x00000004 -+#define UCC_GETH_UCCE_RXF1 0x00000002 -+#define UCC_GETH_UCCE_RXF0 0x00000001 -+ -+/* UCC Protocol Specific Mode Register (UPSMR), when used for UART */ -+#define UCC_UART_UPSMR_FLC 0x8000 -+#define UCC_UART_UPSMR_SL 0x4000 -+#define UCC_UART_UPSMR_CL_MASK 0x3000 -+#define UCC_UART_UPSMR_CL_8 0x3000 -+#define UCC_UART_UPSMR_CL_7 0x2000 -+#define UCC_UART_UPSMR_CL_6 0x1000 -+#define UCC_UART_UPSMR_CL_5 0x0000 -+#define UCC_UART_UPSMR_UM_MASK 0x0c00 -+#define UCC_UART_UPSMR_UM_NORMAL 0x0000 -+#define UCC_UART_UPSMR_UM_MAN_MULTI 0x0400 -+#define UCC_UART_UPSMR_UM_AUTO_MULTI 0x0c00 -+#define UCC_UART_UPSMR_FRZ 0x0200 -+#define UCC_UART_UPSMR_RZS 0x0100 -+#define UCC_UART_UPSMR_SYN 0x0080 -+#define UCC_UART_UPSMR_DRT 0x0040 -+#define UCC_UART_UPSMR_PEN 0x0010 -+#define UCC_UART_UPSMR_RPM_MASK 0x000c -+#define UCC_UART_UPSMR_RPM_ODD 0x0000 -+#define UCC_UART_UPSMR_RPM_LOW 0x0004 -+#define UCC_UART_UPSMR_RPM_EVEN 0x0008 -+#define UCC_UART_UPSMR_RPM_HIGH 0x000C -+#define UCC_UART_UPSMR_TPM_MASK 0x0003 -+#define UCC_UART_UPSMR_TPM_ODD 0x0000 -+#define UCC_UART_UPSMR_TPM_LOW 0x0001 -+#define UCC_UART_UPSMR_TPM_EVEN 0x0002 -+#define UCC_UART_UPSMR_TPM_HIGH 0x0003 -+ -+/* UCC Protocol Specific Mode Register (UPSMR), when used for Ethernet */ -+#define UCC_GETH_UPSMR_FTFE 0x80000000 -+#define UCC_GETH_UPSMR_PTPE 0x40000000 -+#define UCC_GETH_UPSMR_ECM 0x04000000 -+#define UCC_GETH_UPSMR_HSE 0x02000000 -+#define UCC_GETH_UPSMR_PRO 0x00400000 -+#define UCC_GETH_UPSMR_CAP 0x00200000 -+#define UCC_GETH_UPSMR_RSH 0x00100000 -+#define UCC_GETH_UPSMR_RPM 0x00080000 -+#define UCC_GETH_UPSMR_R10M 0x00040000 -+#define UCC_GETH_UPSMR_RLPB 0x00020000 -+#define UCC_GETH_UPSMR_TBIM 0x00010000 -+#define UCC_GETH_UPSMR_RES1 0x00002000 -+#define UCC_GETH_UPSMR_RMM 0x00001000 -+#define UCC_GETH_UPSMR_CAM 0x00000400 -+#define UCC_GETH_UPSMR_BRO 0x00000200 -+#define UCC_GETH_UPSMR_SMM 0x00000080 -+#define UCC_GETH_UPSMR_SGMM 0x00000020 -+ -+/* UCC Transmit On Demand Register (UTODR) */ -+#define UCC_SLOW_TOD 0x8000 -+#define UCC_FAST_TOD 0x8000 -+ -+/* UCC Bus Mode Register masks */ -+/* Not to be confused with the Bundle Mode Register */ -+#define UCC_BMR_GBL 0x20 -+#define UCC_BMR_BO_BE 0x10 -+#define UCC_BMR_CETM 0x04 -+#define UCC_BMR_DTB 0x02 -+#define UCC_BMR_BDB 0x01 -+ -+/* Function code masks */ -+#define FC_GBL 0x20 -+#define FC_DTB_LCL 0x02 -+#define UCC_FAST_FUNCTION_CODE_GBL 0x20 -+#define UCC_FAST_FUNCTION_CODE_DTB_LCL 0x02 -+#define UCC_FAST_FUNCTION_CODE_BDB_LCL 0x01 -+ -+#endif /* __KERNEL__ */ -+#endif /* _ASM_POWERPC_QE_H */ |