diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch | 118 |
1 files changed, 118 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch b/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch new file mode 100644 index 0000000000..3bfcd297b2 --- /dev/null +++ b/target/linux/layerscape/patches-4.4/3233-arm64-dts-ls1046a-update-MSI-dts-node.patch @@ -0,0 +1,118 @@ +From 1569c166572f9576c6726472b5a726a1a56900bd Mon Sep 17 00:00:00 2001 +From: Yangbo Lu <yangbo.lu@nxp.com> +Date: Thu, 16 Feb 2017 18:00:14 +0800 +Subject: [PATCH] arm64: dts: ls1046a: update MSI dts node + +Update MSI dts node according to below patchwork patch. + +arm64: dts: ls1046a: add MSI dts node +https://patchwork.kernel.org/patch/9520299 + +Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> +--- + arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 58 +++++++++++++------------- + 1 file changed, 30 insertions(+), 28 deletions(-) + +diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +index 179c38b..f96be34 100644 +--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi ++++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +@@ -44,6 +44,8 @@ + * OTHER DEALINGS IN THE SOFTWARE. + */ + ++#include <dt-bindings/interrupt-controller/arm-gic.h> ++ + / { + compatible = "fsl,ls1046a"; + interrupt-parent = <&gic>; +@@ -870,34 +872,34 @@ + big-endian; + }; + +- msi: msi-controller@1580000 { ++ msi1: msi-controller@1580000 { + compatible = "fsl,ls1046a-msi"; +- #address-cells = <2>; +- #size-cells = <2>; +- ranges; + msi-controller; ++ reg = <0x0 0x1580000 0x0 0x10000>; ++ interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; ++ }; + +- msi-bank@1580000 { +- reg = <0x0 0x1580000 0x0 0x10000>; +- interrupts = <0 116 0x4>, +- <0 111 0x4>, +- <0 112 0x4>, +- <0 113 0x4>; +- }; +- msi-bank@1590000 { +- reg = <0x0 0x1590000 0x0 0x10000>; +- interrupts = <0 126 0x4>, +- <0 121 0x4>, +- <0 122 0x4>, +- <0 123 0x4>; +- }; +- msi-bank@15a0000 { +- reg = <0x0 0x15a0000 0x0 0x10000>; +- interrupts = <0 160 0x4>, +- <0 155 0x4>, +- <0 156 0x4>, +- <0 157 0x4>; +- }; ++ msi2: msi-controller@1590000 { ++ compatible = "fsl,ls1046a-msi"; ++ msi-controller; ++ reg = <0x0 0x1590000 0x0 0x10000>; ++ interrupts = <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; ++ }; ++ ++ msi3: msi-controller@15a0000 { ++ compatible = "fsl,ls1046a-msi"; ++ msi-controller; ++ reg = <0x0 0x15a0000 0x0 0x10000>; ++ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, ++ <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; + }; + + pcie@3400000 { +@@ -916,7 +918,7 @@ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi>; ++ msi-parent = <&msi1>, <&msi2>, <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 110 0x4>, +@@ -941,7 +943,7 @@ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi>; ++ msi-parent = <&msi1>, <&msi2>, <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 120 0x4>, +@@ -966,7 +968,7 @@ + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x50 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ +- msi-parent = <&msi>; ++ msi-parent = <&msi1>, <&msi2>, <&msi3>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 154 0x4>, +-- +2.1.0.27.g96db324 + |