diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch b/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch new file mode 100644 index 0000000000..733b62c7fc --- /dev/null +++ b/target/linux/layerscape/patches-4.4/1100-mtd-spi_nor-Disable-Micron-flash-HW-protection.patch @@ -0,0 +1,41 @@ +From e892dea7229d56b75c46a76b9039f9e179584a91 Mon Sep 17 00:00:00 2001 +From: Yunhui Cui <B56489@freescale.com> +Date: Mon, 1 Feb 2016 18:48:49 +0800 +Subject: [PATCH 100/113] mtd:spi_nor: Disable Micron flash HW protection + +For Micron family ,The status register write enable/disable bit, +provides hardware data protection for the device. +When the enable/disable bit is set to 1, the status register +nonvolatile bits become read-only and the WRITE STATUS REGISTER +operation will not execute. + +Signed-off-by: Yunhui Cui <B56489@freescale.com> +--- + drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++ + 1 file changed, 9 insertions(+) + +--- a/drivers/mtd/spi-nor/spi-nor.c ++++ b/drivers/mtd/spi-nor/spi-nor.c +@@ -39,6 +39,7 @@ + + #define SPI_NOR_MAX_ID_LEN 6 + #define SPI_NOR_MAX_ADDR_WIDTH 4 ++#define SPI_NOR_MICRON_WRITE_ENABLE 0x7f + + struct flash_info { + char *name; +@@ -1237,6 +1238,14 @@ int spi_nor_scan(struct spi_nor *nor, co + if (ret) + return ret; + ++ if (JEDEC_MFR(info) == SNOR_MFR_MICRON) { ++ ret = read_sr(nor); ++ ret &= SPI_NOR_MICRON_WRITE_ENABLE; ++ ++ write_enable(nor); ++ write_sr(nor, ret); ++ } ++ + if (!mtd->name) + mtd->name = dev_name(dev); + mtd->priv = nor; |