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Diffstat (limited to 'target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch')
-rw-r--r--target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch59
1 files changed, 59 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch b/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch
new file mode 100644
index 0000000000..8f7ae19a7a
--- /dev/null
+++ b/target/linux/layerscape/patches-4.4/0241-dt-bindings-Add-bindings-for-Layerscape-SCFG-MSI.patch
@@ -0,0 +1,59 @@
+From 066320dd0643e66bc5afe0d0984e77b2e938a6f4 Mon Sep 17 00:00:00 2001
+From: Minghuan Lian <Minghuan.Lian@nxp.com>
+Date: Wed, 23 Mar 2016 19:08:19 +0800
+Subject: [PATCH 03/13] dt/bindings: Add bindings for Layerscape SCFG MSI
+
+Cherry-pick upstream patch.
+
+Some Layerscape SoCs use a simple MSI controller implementation.
+It contains only two SCFG register to trigger and describe a
+group 32 MSI interrupts. The patch adds bindings to describe
+the controller.
+
+Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
+Acked-by: Rob Herring <robh@kernel.org>
+Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
+---
+ .../interrupt-controller/fsl,ls-scfg-msi.txt | 30 ++++++++++++++++++++++
+ 1 file changed, 30 insertions(+)
+ create mode 100644 Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+
+diff --git a/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+new file mode 100644
+index 0000000..9e38949
+--- /dev/null
++++ b/Documentation/devicetree/bindings/interrupt-controller/fsl,ls-scfg-msi.txt
+@@ -0,0 +1,30 @@
++* Freescale Layerscape SCFG PCIe MSI controller
++
++Required properties:
++
++- compatible: should be "fsl,<soc-name>-msi" to identify
++ Layerscape PCIe MSI controller block such as:
++ "fsl,1s1021a-msi"
++ "fsl,1s1043a-msi"
++- msi-controller: indicates that this is a PCIe MSI controller node
++- reg: physical base address of the controller and length of memory mapped.
++- interrupts: an interrupt to the parent interrupt controller.
++
++Optional properties:
++- interrupt-parent: the phandle to the parent interrupt controller.
++
++This interrupt controller hardware is a second level interrupt controller that
++is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
++platforms. If interrupt-parent is not provided, the default parent interrupt
++controller will be used.
++Each PCIe node needs to have property msi-parent that points to
++MSI controller node
++
++Examples:
++
++ msi1: msi-controller@1571000 {
++ compatible = "fsl,1s1043a-msi";
++ reg = <0x0 0x1571000 0x0 0x8>,
++ msi-controller;
++ interrupts = <0 116 0x4>;
++ };
+--
+2.1.0.27.g96db324
+