diff options
Diffstat (limited to 'target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch')
| -rw-r--r-- | target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch b/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch new file mode 100644 index 0000000000..aaf677b564 --- /dev/null +++ b/target/linux/layerscape/patches-4.14/801-sata-support-layerscape.patch @@ -0,0 +1,68 @@ +From 918f966af1f0e42ff8ac298e1d7d02e67afcfab4 Mon Sep 17 00:00:00 2001 +From: Biwen Li <biwen.li@nxp.com> +Date: Tue, 30 Oct 2018 18:27:42 +0800 +Subject: [PATCH 18/40] sata: support layerscape +This is an integrated patch of sata for layerscape + +Signed-off-by: Tang Yuantian <andy.tang@nxp.com> +Signed-off-by: Biwen Li <biwen.li@nxp.com> +--- + drivers/ata/ahci_qoriq.c | 12 ++++++++++++ + 1 file changed, 12 insertions(+) + +--- a/drivers/ata/ahci_qoriq.c ++++ b/drivers/ata/ahci_qoriq.c +@@ -35,6 +35,8 @@ + + /* port register default value */ + #define AHCI_PORT_PHY_1_CFG 0xa003fffe ++#define AHCI_PORT_PHY2_CFG 0x28184d1f ++#define AHCI_PORT_PHY3_CFG 0x0e081509 + #define AHCI_PORT_TRANS_CFG 0x08000029 + #define AHCI_PORT_AXICC_CFG 0x3fffffff + +@@ -183,6 +185,8 @@ static int ahci_qoriq_phy_init(struct ah + writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, + qpriv->ecc_addr); + writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ++ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); ++ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); + if (qpriv->is_dmacoherent) + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); +@@ -190,6 +194,8 @@ static int ahci_qoriq_phy_init(struct ah + + case AHCI_LS2080A: + writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ++ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); ++ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); + if (qpriv->is_dmacoherent) + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); +@@ -201,6 +207,8 @@ static int ahci_qoriq_phy_init(struct ah + writel(readl(qpriv->ecc_addr) | ECC_DIS_ARMV8_CH2, + qpriv->ecc_addr); + writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ++ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); ++ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); + if (qpriv->is_dmacoherent) + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); +@@ -212,6 +220,8 @@ static int ahci_qoriq_phy_init(struct ah + writel(readl(qpriv->ecc_addr) | ECC_DIS_LS1088A, + qpriv->ecc_addr); + writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ++ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); ++ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); + if (qpriv->is_dmacoherent) + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); +@@ -219,6 +229,8 @@ static int ahci_qoriq_phy_init(struct ah + + case AHCI_LS2088A: + writel(AHCI_PORT_PHY_1_CFG, reg_base + PORT_PHY1); ++ writel(AHCI_PORT_PHY2_CFG, reg_base + PORT_PHY2); ++ writel(AHCI_PORT_PHY3_CFG, reg_base + PORT_PHY3); + writel(AHCI_PORT_TRANS_CFG, reg_base + PORT_TRANS); + if (qpriv->is_dmacoherent) + writel(AHCI_PORT_AXICC_CFG, reg_base + PORT_AXICC); |