diff options
Diffstat (limited to 'target/linux/lantiq/patches')
35 files changed, 40000 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches/0001-MIPS-lantiq-fix-early-printk.patch b/target/linux/lantiq/patches/0001-MIPS-lantiq-fix-early-printk.patch new file mode 100644 index 0000000000..57b330d2a7 --- /dev/null +++ b/target/linux/lantiq/patches/0001-MIPS-lantiq-fix-early-printk.patch @@ -0,0 +1,60 @@ +From 91f8d0c8fbb9ea70bf78a291e312157177be8ee3 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 20 Aug 2011 18:55:13 +0200 +Subject: [PATCH 01/24] MIPS: lantiq: fix early printk + +The code was using a 32bit write operation in the early_printk code. This +resulted in 3 zero bytes also being written to the serial port. Change the +memory access to 8bit. + +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 4 ++++ + arch/mips/lantiq/early_printk.c | 14 ++++++++------ + 2 files changed, 12 insertions(+), 6 deletions(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -34,6 +34,10 @@ + #define LTQ_ASC1_BASE_ADDR 0x1E100C00 + #define LTQ_ASC_SIZE 0x400 + ++/* during early_printk no ioremap is possible ++ lets use KSEG1 instead */ ++#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC1_BASE_ADDR) ++ + /* RCU - reset control unit */ + #define LTQ_RCU_BASE_ADDR 0x1F203000 + #define LTQ_RCU_SIZE 0x1000 +--- a/arch/mips/lantiq/early_printk.c ++++ b/arch/mips/lantiq/early_printk.c +@@ -12,11 +12,13 @@ + #include <lantiq.h> + #include <lantiq_soc.h> + +-/* no ioremap possible at this early stage, lets use KSEG1 instead */ +-#define LTQ_ASC_BASE KSEG1ADDR(LTQ_ASC1_BASE_ADDR) + #define ASC_BUF 1024 +-#define LTQ_ASC_FSTAT ((u32 *)(LTQ_ASC_BASE + 0x0048)) +-#define LTQ_ASC_TBUF ((u32 *)(LTQ_ASC_BASE + 0x0020)) ++#define LTQ_ASC_FSTAT ((u32 *)(LTQ_EARLY_ASC + 0x0048)) ++#ifdef __BIG_ENDIAN ++#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020 + 3)) ++#else ++#define LTQ_ASC_TBUF ((u32 *)(LTQ_EARLY_ASC + 0x0020)) ++#endif + #define TXMASK 0x3F00 + #define TXOFFSET 8 + +@@ -27,7 +29,7 @@ void prom_putchar(char c) + local_irq_save(flags); + do { } while ((ltq_r32(LTQ_ASC_FSTAT) & TXMASK) >> TXOFFSET); + if (c == '\n') +- ltq_w32('\r', LTQ_ASC_TBUF); +- ltq_w32(c, LTQ_ASC_TBUF); ++ ltq_w8('\r', LTQ_ASC_TBUF); ++ ltq_w8(c, LTQ_ASC_TBUF); + local_irq_restore(flags); + } diff --git a/target/linux/lantiq/patches/0002-MIPS-lantiq-fix-cmdline-parsing.patch b/target/linux/lantiq/patches/0002-MIPS-lantiq-fix-cmdline-parsing.patch new file mode 100644 index 0000000000..6966e1cbc0 --- /dev/null +++ b/target/linux/lantiq/patches/0002-MIPS-lantiq-fix-cmdline-parsing.patch @@ -0,0 +1,32 @@ +From b85d5204f2fe8c3b5e6172f7cc1741ad6e849334 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Fri, 12 Aug 2011 16:27:38 +0200 +Subject: [PATCH 02/24] MIPS: lantiq: fix cmdline parsing + +The code tested if the KSEG1 mapped address of argv was != 0. We need to use +CPHYSADDR instead to make the conditional actually work. + +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + arch/mips/lantiq/prom.c | 6 ++++-- + 1 files changed, 4 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -45,10 +45,12 @@ static void __init prom_init_cmdline(voi + char **argv = (char **) KSEG1ADDR(fw_arg1); + int i; + ++ arcs_cmdline[0] = '\0'; ++ + for (i = 0; i < argc; i++) { +- char *p = (char *) KSEG1ADDR(argv[i]); ++ char *p = (char *) KSEG1ADDR(argv[i]); + +- if (p && *p) { ++ if (CPHYSADDR(p) && *p) { + strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } diff --git a/target/linux/lantiq/patches/0004-MIPS-lantiq-reorganize-xway-code.patch b/target/linux/lantiq/patches/0004-MIPS-lantiq-reorganize-xway-code.patch new file mode 100644 index 0000000000..982b69da0d --- /dev/null +++ b/target/linux/lantiq/patches/0004-MIPS-lantiq-reorganize-xway-code.patch @@ -0,0 +1,835 @@ +From d90739a8962b541969b4c5f7ef1df8fec9c7f153 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Wed, 10 Aug 2011 14:57:04 +0200 +Subject: [PATCH 04/24] MIPS: lantiq: reorganize xway code + +Inside the folder arch/mips/lantiq/xway, there were alot of small files with +lots of duplicated code. This patch adds a wrapper function for inserting and +requesting resources and unifies the small files into one bigger file. + +This patch makes the xway code consistent with the falcon support added later +in this series. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Cc: linux-mips@linux-mips.org +--- + arch/mips/include/asm/mach-lantiq/lantiq.h | 14 +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 14 ++++ + arch/mips/lantiq/clk.c | 25 +------ + arch/mips/lantiq/devices.c | 30 ++------ + arch/mips/lantiq/devices.h | 4 + + arch/mips/lantiq/prom.c | 50 +++++++++++-- + arch/mips/lantiq/prom.h | 4 + + arch/mips/lantiq/xway/Makefile | 6 +- + arch/mips/lantiq/xway/devices.c | 42 ++--------- + arch/mips/lantiq/xway/dma.c | 21 ++---- + arch/mips/lantiq/xway/ebu.c | 53 -------------- + arch/mips/lantiq/xway/pmu.c | 70 ------------------ + arch/mips/lantiq/xway/prom-ase.c | 9 +++ + arch/mips/lantiq/xway/prom-xway.c | 10 +++ + arch/mips/lantiq/xway/reset.c | 21 ++---- + arch/mips/lantiq/xway/setup-ase.c | 19 ----- + arch/mips/lantiq/xway/setup-xway.c | 20 ----- + arch/mips/lantiq/xway/sysctrl.c | 77 ++++++++++++++++++++ + drivers/watchdog/lantiq_wdt.c | 2 +- + 19 files changed, 197 insertions(+), 294 deletions(-) + delete mode 100644 arch/mips/lantiq/xway/ebu.c + delete mode 100644 arch/mips/lantiq/xway/pmu.c + delete mode 100644 arch/mips/lantiq/xway/setup-ase.c + delete mode 100644 arch/mips/lantiq/xway/setup-xway.c + create mode 100644 arch/mips/lantiq/xway/sysctrl.c + +--- a/arch/mips/include/asm/mach-lantiq/lantiq.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h +@@ -9,6 +9,7 @@ + #define _LANTIQ_H__ + + #include <linux/irq.h> ++#include <linux/ioport.h> + + /* generic reg access functions */ + #define ltq_r32(reg) __raw_readl(reg) +@@ -18,15 +19,6 @@ + #define ltq_r8(reg) __raw_readb(reg) + #define ltq_w8(val, reg) __raw_writeb(val, reg) + +-/* register access macros for EBU and CGU */ +-#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) +-#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) +-#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) +-#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) +- +-extern __iomem void *ltq_ebu_membase; +-extern __iomem void *ltq_cgu_membase; +- + extern unsigned int ltq_get_cpu_ver(void); + extern unsigned int ltq_get_soc_type(void); + +@@ -51,7 +43,9 @@ extern void ltq_enable_irq(struct irq_da + + /* find out what caused the last cpu reset */ + extern int ltq_reset_cause(void); +-#define LTQ_RST_CAUSE_WDTRST 0x20 ++ ++/* helper for requesting and remapping resources */ ++extern void __iomem *ltq_remap_resource(struct resource *res); + + #define IOPORT_RESOURCE_START 0x10000000 + #define IOPORT_RESOURCE_END 0xffffffff +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -65,6 +65,8 @@ + #define LTQ_CGU_BASE_ADDR 0x1F103000 + #define LTQ_CGU_SIZE 0x1000 + ++#define CGU_EPHY 0x10 ++ + /* ICU - interrupt control unit */ + #define LTQ_ICU_BASE_ADDR 0x1F880200 + #define LTQ_ICU_SIZE 0x100 +@@ -101,6 +103,8 @@ + #define LTQ_WDT_BASE_ADDR 0x1F8803F0 + #define LTQ_WDT_SIZE 0x10 + ++#define LTQ_RST_CAUSE_WDTRST 0x20 ++ + /* STP - serial to parallel conversion unit */ + #define LTQ_STP_BASE_ADDR 0x1E100BB0 + #define LTQ_STP_SIZE 0x40 +@@ -125,11 +129,21 @@ + #define LTQ_MPS_BASE_ADDR (KSEG1 + 0x1F107000) + #define LTQ_MPS_CHIPID ((u32 *)(LTQ_MPS_BASE_ADDR + 0x0344)) + ++/* register access macros for EBU and CGU */ ++#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) ++#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ++#define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) ++#define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) ++ ++extern __iomem void *ltq_ebu_membase; ++extern __iomem void *ltq_cgu_membase; ++ + /* request a non-gpio and set the PIO config */ + extern int ltq_gpio_request(unsigned int pin, unsigned int alt0, + unsigned int alt1, unsigned int dir, const char *name); + extern void ltq_pmu_enable(unsigned int module); + extern void ltq_pmu_disable(unsigned int module); ++extern void ltq_cgu_enable(unsigned int clk); + + static inline int ltq_is_ar9(void) + { +--- a/arch/mips/lantiq/clk.c ++++ b/arch/mips/lantiq/clk.c +@@ -22,6 +22,7 @@ + #include <lantiq_soc.h> + + #include "clk.h" ++#include "prom.h" + + struct clk { + const char *name; +@@ -46,16 +47,6 @@ static struct clk cpu_clk_generic[] = { + }, + }; + +-static struct resource ltq_cgu_resource = { +- .name = "cgu", +- .start = LTQ_CGU_BASE_ADDR, +- .end = LTQ_CGU_BASE_ADDR + LTQ_CGU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-/* remapped clock register range */ +-void __iomem *ltq_cgu_membase; +- + void clk_init(void) + { + cpu_clk = cpu_clk_generic; +@@ -133,21 +124,11 @@ void __init plat_time_init(void) + { + struct clk *clk; + +- if (insert_resource(&iomem_resource, <q_cgu_resource) < 0) +- panic("Failed to insert cgu memory\n"); ++ ltq_soc_init(); + +- if (request_mem_region(ltq_cgu_resource.start, +- resource_size(<q_cgu_resource), "cgu") < 0) +- panic("Failed to request cgu memory\n"); +- +- ltq_cgu_membase = ioremap_nocache(ltq_cgu_resource.start, +- resource_size(<q_cgu_resource)); +- if (!ltq_cgu_membase) { +- pr_err("Failed to remap cgu memory\n"); +- unreachable(); +- } + clk = clk_get(0, "cpu"); + mips_hpt_frequency = clk_get_rate(clk) / ltq_get_counter_resolution(); + write_c0_compare(read_c0_count()); ++ pr_info("CPU Clock: %ldMHz\n", clk_get_rate(clk) / 1000000); + clk_put(clk); + } +--- a/arch/mips/lantiq/devices.c ++++ b/arch/mips/lantiq/devices.c +@@ -27,12 +27,8 @@ + #include "devices.h" + + /* nor flash */ +-static struct resource ltq_nor_resource = { +- .name = "nor", +- .start = LTQ_FLASH_START, +- .end = LTQ_FLASH_START + LTQ_FLASH_MAX - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_nor_resource = ++ MEM_RES("nor", LTQ_FLASH_START, LTQ_FLASH_MAX); + + static struct platform_device ltq_nor = { + .name = "ltq_nor", +@@ -47,12 +43,8 @@ void __init ltq_register_nor(struct phys + } + + /* watchdog */ +-static struct resource ltq_wdt_resource = { +- .name = "watchdog", +- .start = LTQ_WDT_BASE_ADDR, +- .end = LTQ_WDT_BASE_ADDR + LTQ_WDT_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_wdt_resource = ++ MEM_RES("watchdog", LTQ_WDT_BASE_ADDR, LTQ_WDT_SIZE); + + void __init ltq_register_wdt(void) + { +@@ -61,24 +53,14 @@ void __init ltq_register_wdt(void) + + /* asc ports */ + static struct resource ltq_asc0_resources[] = { +- { +- .name = "asc0", +- .start = LTQ_ASC0_BASE_ADDR, +- .end = LTQ_ASC0_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc0", LTQ_ASC0_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_TIR(0)), + IRQ_RES(rx, LTQ_ASC_RIR(0)), + IRQ_RES(err, LTQ_ASC_EIR(0)), + }; + + static struct resource ltq_asc1_resources[] = { +- { +- .name = "asc1", +- .start = LTQ_ASC1_BASE_ADDR, +- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc1", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_TIR(1)), + IRQ_RES(rx, LTQ_ASC_RIR(1)), + IRQ_RES(err, LTQ_ASC_EIR(1)), +--- a/arch/mips/lantiq/devices.h ++++ b/arch/mips/lantiq/devices.h +@@ -14,6 +14,10 @@ + + #define IRQ_RES(resname, irq) \ + {.name = #resname, .start = (irq), .flags = IORESOURCE_IRQ} ++#define MEM_RES(resname, adr_start, adr_size) \ ++ { .name = resname, .flags = IORESOURCE_MEM, \ ++ .start = ((adr_start) & ~KSEG1), \ ++ .end = ((adr_start + adr_size - 1) & ~KSEG1) } + + extern void ltq_register_nor(struct physmap_flash_data *data); + extern void ltq_register_wdt(void); +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -16,6 +16,10 @@ + #include "prom.h" + #include "clk.h" + ++/* access to the ebu needs to be locked between different drivers */ ++DEFINE_SPINLOCK(ebu_lock); ++EXPORT_SYMBOL_GPL(ebu_lock); ++ + static struct ltq_soc_info soc_info; + + unsigned int ltq_get_cpu_ver(void) +@@ -57,16 +61,50 @@ static void __init prom_init_cmdline(voi + } + } + +-void __init prom_init(void) ++void __iomem *ltq_remap_resource(struct resource *res) + { +- struct clk *clk; ++ __iomem void *ret = NULL; ++ struct resource *lookup = lookup_resource(&iomem_resource, res->start); + ++ if (lookup && strcmp(lookup->name, res->name)) { ++ panic("conflicting memory range %s\n", res->name); ++ return NULL; ++ } ++ if (!lookup) { ++ if (insert_resource(&iomem_resource, res) < 0) { ++ panic("Failed to insert %s memory\n", res->name); ++ return NULL; ++ } ++ } ++ if (request_mem_region(res->start, ++ resource_size(res), res->name) < 0) { ++ panic("Failed to request %s memory\n", res->name); ++ goto err_res; ++ } ++ ++ ret = ioremap_nocache(res->start, resource_size(res)); ++ if (!ret) ++ goto err_mem; ++ ++ pr_debug("remap: 0x%08X-0x%08X : \"%s\"\n", ++ res->start, res->end, res->name); ++ return ret; ++ ++err_mem: ++ panic("Failed to remap %s memory\n", res->name); ++ release_mem_region(res->start, resource_size(res)); ++ ++err_res: ++ release_resource(res); ++ return NULL; ++} ++ ++void __init prom_init(void) ++{ + ltq_soc_detect(&soc_info); + clk_init(); +- clk = clk_get(0, "cpu"); +- snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev1.%d", +- soc_info.name, soc_info.rev); +- clk_put(clk); ++ snprintf(soc_info.sys_type, LTQ_SYS_TYPE_LEN - 1, "%s rev %s", ++ soc_info.name, soc_info.rev_type); + soc_info.sys_type[LTQ_SYS_TYPE_LEN - 1] = '\0'; + pr_info("SoC: %s\n", soc_info.sys_type); + prom_init_cmdline(); +--- a/arch/mips/lantiq/prom.h ++++ b/arch/mips/lantiq/prom.h +@@ -9,17 +9,21 @@ + #ifndef _LTQ_PROM_H__ + #define _LTQ_PROM_H__ + ++#define LTQ_SYS_REV_LEN 0x10 + #define LTQ_SYS_TYPE_LEN 0x100 + + struct ltq_soc_info { + unsigned char *name; + unsigned int rev; ++ unsigned char rev_type[LTQ_SYS_REV_LEN]; ++ unsigned int srev; + unsigned int partnum; + unsigned int type; + unsigned char sys_type[LTQ_SYS_TYPE_LEN]; + }; + + extern void ltq_soc_detect(struct ltq_soc_info *i); ++extern void ltq_soc_init(void); + extern void ltq_soc_setup(void); + + #endif +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,7 +1,7 @@ +-obj-y := pmu.o ebu.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o ++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o + +-obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o setup-xway.o +-obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o setup-ase.o ++obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o ++obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o + + obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o + obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -31,22 +31,9 @@ + + /* gpio */ + static struct resource ltq_gpio_resource[] = { +- { +- .name = "gpio0", +- .start = LTQ_GPIO0_BASE_ADDR, +- .end = LTQ_GPIO0_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .name = "gpio1", +- .start = LTQ_GPIO1_BASE_ADDR, +- .end = LTQ_GPIO1_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, { +- .name = "gpio2", +- .start = LTQ_GPIO2_BASE_ADDR, +- .end = LTQ_GPIO2_BASE_ADDR + LTQ_GPIO_SIZE - 1, +- .flags = IORESOURCE_MEM, +- } ++ MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), + }; + + void __init ltq_register_gpio(void) +@@ -64,12 +51,8 @@ void __init ltq_register_gpio(void) + } + + /* serial to parallel conversion */ +-static struct resource ltq_stp_resource = { +- .name = "stp", +- .start = LTQ_STP_BASE_ADDR, +- .end = LTQ_STP_BASE_ADDR + LTQ_STP_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_stp_resource = ++ MEM_RES("stp", LTQ_STP_BASE_ADDR, LTQ_STP_SIZE); + + void __init ltq_register_gpio_stp(void) + { +@@ -78,12 +61,7 @@ void __init ltq_register_gpio_stp(void) + + /* asc ports - amazon se has its own serial mapping */ + static struct resource ltq_ase_asc_resources[] = { +- { +- .name = "asc0", +- .start = LTQ_ASC1_BASE_ADDR, +- .end = LTQ_ASC1_BASE_ADDR + LTQ_ASC_SIZE - 1, +- .flags = IORESOURCE_MEM, +- }, ++ MEM_RES("asc0", LTQ_ASC1_BASE_ADDR, LTQ_ASC_SIZE), + IRQ_RES(tx, LTQ_ASC_ASE_TIR), + IRQ_RES(rx, LTQ_ASC_ASE_RIR), + IRQ_RES(err, LTQ_ASC_ASE_EIR), +@@ -96,12 +74,8 @@ void __init ltq_register_ase_asc(void) + } + + /* ethernet */ +-static struct resource ltq_etop_resources = { +- .name = "etop", +- .start = LTQ_ETOP_BASE_ADDR, +- .end = LTQ_ETOP_BASE_ADDR + LTQ_ETOP_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_etop_resources = ++ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); + + static struct platform_device ltq_etop = { + .name = "ltq_etop", +--- a/arch/mips/lantiq/xway/dma.c ++++ b/arch/mips/lantiq/xway/dma.c +@@ -23,6 +23,8 @@ + #include <lantiq_soc.h> + #include <xway_dma.h> + ++#include "../devices.h" ++ + #define LTQ_DMA_CTRL 0x10 + #define LTQ_DMA_CPOLL 0x14 + #define LTQ_DMA_CS 0x18 +@@ -54,12 +56,8 @@ + #define ltq_dma_w32_mask(x, y, z) ltq_w32_mask(x, y, \ + ltq_dma_membase + (z)) + +-static struct resource ltq_dma_resource = { +- .name = "dma", +- .start = LTQ_DMA_BASE_ADDR, +- .end = LTQ_DMA_BASE_ADDR + LTQ_DMA_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_dma_resource = ++ MEM_RES("dma", LTQ_DMA_BASE_ADDR, LTQ_DMA_SIZE); + + static void __iomem *ltq_dma_membase; + +@@ -219,17 +217,8 @@ ltq_dma_init(void) + { + int i; + +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_dma_resource) < 0) +- panic("Failed to insert dma memory\n"); +- +- if (request_mem_region(ltq_dma_resource.start, +- resource_size(<q_dma_resource), "dma") < 0) +- panic("Failed to request dma memory\n"); +- + /* remap dma register range */ +- ltq_dma_membase = ioremap_nocache(ltq_dma_resource.start, +- resource_size(<q_dma_resource)); ++ ltq_dma_membase = ltq_remap_resource(<q_dma_resource); + if (!ltq_dma_membase) + panic("Failed to remap dma memory\n"); + +--- a/arch/mips/lantiq/xway/ebu.c ++++ /dev/null +@@ -1,52 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * EBU - the external bus unit attaches PCI, NOR and NAND +- * +- * Copyright (C) 2010 John Crispin <blogic@openwrt.org> +- */ +- +-#include <linux/kernel.h> +-#include <linux/module.h> +-#include <linux/ioport.h> +- +-#include <lantiq_soc.h> +- +-/* all access to the ebu must be locked */ +-DEFINE_SPINLOCK(ebu_lock); +-EXPORT_SYMBOL_GPL(ebu_lock); +- +-static struct resource ltq_ebu_resource = { +- .name = "ebu", +- .start = LTQ_EBU_BASE_ADDR, +- .end = LTQ_EBU_BASE_ADDR + LTQ_EBU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-/* remapped base addr of the clock unit and external bus unit */ +-void __iomem *ltq_ebu_membase; +- +-static int __init lantiq_ebu_init(void) +-{ +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_ebu_resource) < 0) +- panic("Failed to insert ebu memory\n"); +- +- if (request_mem_region(ltq_ebu_resource.start, +- resource_size(<q_ebu_resource), "ebu") < 0) +- panic("Failed to request ebu memory\n"); +- +- /* remap ebu register range */ +- ltq_ebu_membase = ioremap_nocache(ltq_ebu_resource.start, +- resource_size(<q_ebu_resource)); +- if (!ltq_ebu_membase) +- panic("Failed to remap ebu memory\n"); +- +- /* make sure to unprotect the memory region where flash is located */ +- ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); +- return 0; +-} +- +-postcore_initcall(lantiq_ebu_init); +--- a/arch/mips/lantiq/xway/pmu.c ++++ /dev/null +@@ -1,69 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2010 John Crispin <blogic@openwrt.org> +- */ +- +-#include <linux/kernel.h> +-#include <linux/module.h> +-#include <linux/ioport.h> +- +-#include <lantiq_soc.h> +- +-/* PMU - the power management unit allows us to turn part of the core +- * on and off +- */ +- +-/* the enable / disable registers */ +-#define LTQ_PMU_PWDCR 0x1C +-#define LTQ_PMU_PWDSR 0x20 +- +-#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) +-#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) +- +-static struct resource ltq_pmu_resource = { +- .name = "pmu", +- .start = LTQ_PMU_BASE_ADDR, +- .end = LTQ_PMU_BASE_ADDR + LTQ_PMU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; +- +-static void __iomem *ltq_pmu_membase; +- +-void ltq_pmu_enable(unsigned int module) +-{ +- int err = 1000000; +- +- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); +- do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); +- +- if (!err) +- panic("activating PMU module failed!\n"); +-} +-EXPORT_SYMBOL(ltq_pmu_enable); +- +-void ltq_pmu_disable(unsigned int module) +-{ +- ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); +-} +-EXPORT_SYMBOL(ltq_pmu_disable); +- +-int __init ltq_pmu_init(void) +-{ +- if (insert_resource(&iomem_resource, <q_pmu_resource) < 0) +- panic("Failed to insert pmu memory\n"); +- +- if (request_mem_region(ltq_pmu_resource.start, +- resource_size(<q_pmu_resource), "pmu") < 0) +- panic("Failed to request pmu memory\n"); +- +- ltq_pmu_membase = ioremap_nocache(ltq_pmu_resource.start, +- resource_size(<q_pmu_resource)); +- if (!ltq_pmu_membase) +- panic("Failed to remap pmu memory\n"); +- return 0; +-} +- +-core_initcall(ltq_pmu_init); +--- a/arch/mips/lantiq/xway/prom-ase.c ++++ b/arch/mips/lantiq/xway/prom-ase.c +@@ -13,6 +13,7 @@ + + #include <lantiq_soc.h> + ++#include "devices.h" + #include "../prom.h" + + #define SOC_AMAZON_SE "Amazon_SE" +@@ -26,6 +27,7 @@ void __init ltq_soc_detect(struct ltq_so + { + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; ++ sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_AMAZON_SE: + i->name = SOC_AMAZON_SE; +@@ -37,3 +39,10 @@ void __init ltq_soc_detect(struct ltq_so + break; + } + } ++ ++void __init ltq_soc_setup(void) ++{ ++ ltq_register_ase_asc(); ++ ltq_register_gpio(); ++ ltq_register_wdt(); ++} +--- a/arch/mips/lantiq/xway/prom-xway.c ++++ b/arch/mips/lantiq/xway/prom-xway.c +@@ -13,6 +13,7 @@ + + #include <lantiq_soc.h> + ++#include "devices.h" + #include "../prom.h" + + #define SOC_DANUBE "Danube" +@@ -28,6 +29,7 @@ void __init ltq_soc_detect(struct ltq_so + { + i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; + i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; ++ sprintf(i->rev_type, "1.%d", i->rev); + switch (i->partnum) { + case SOC_ID_DANUBE1: + case SOC_ID_DANUBE2: +@@ -52,3 +54,11 @@ void __init ltq_soc_detect(struct ltq_so + break; + } + } ++ ++void __init ltq_soc_setup(void) ++{ ++ ltq_register_asc(0); ++ ltq_register_asc(1); ++ ltq_register_gpio(); ++ ltq_register_wdt(); ++} +--- a/arch/mips/lantiq/xway/reset.c ++++ b/arch/mips/lantiq/xway/reset.c +@@ -15,6 +15,8 @@ + + #include <lantiq_soc.h> + ++#include "../devices.h" ++ + #define ltq_rcu_w32(x, y) ltq_w32((x), ltq_rcu_membase + (y)) + #define ltq_rcu_r32(x) ltq_r32(ltq_rcu_membase + (x)) + +@@ -25,12 +27,8 @@ + #define LTQ_RCU_RST_STAT 0x0014 + #define LTQ_RCU_STAT_SHIFT 26 + +-static struct resource ltq_rcu_resource = { +- .name = "rcu", +- .start = LTQ_RCU_BASE_ADDR, +- .end = LTQ_RCU_BASE_ADDR + LTQ_RCU_SIZE - 1, +- .flags = IORESOURCE_MEM, +-}; ++static struct resource ltq_rcu_resource = ++ MEM_RES("rcu", LTQ_RCU_BASE_ADDR, LTQ_RCU_SIZE); + + /* remapped base addr of the reset control unit */ + static void __iomem *ltq_rcu_membase; +@@ -67,17 +65,8 @@ static void ltq_machine_power_off(void) + + static int __init mips_reboot_setup(void) + { +- /* insert and request the memory region */ +- if (insert_resource(&iomem_resource, <q_rcu_resource) < 0) +- panic("Failed to insert rcu memory\n"); +- +- if (request_mem_region(ltq_rcu_resource.start, +- resource_size(<q_rcu_resource), "rcu") < 0) +- panic("Failed to request rcu memory\n"); +- + /* remap rcu register range */ +- ltq_rcu_membase = ioremap_nocache(ltq_rcu_resource.start, +- resource_size(<q_rcu_resource)); ++ ltq_rcu_membase = ltq_remap_resource(<q_rcu_resource); + if (!ltq_rcu_membase) + panic("Failed to remap rcu memory\n"); + +--- a/arch/mips/lantiq/xway/setup-ase.c ++++ /dev/null +@@ -1,19 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 John Crispin <blogic@openwrt.org> +- */ +- +-#include <lantiq_soc.h> +- +-#include "../prom.h" +-#include "devices.h" +- +-void __init ltq_soc_setup(void) +-{ +- ltq_register_ase_asc(); +- ltq_register_gpio(); +- ltq_register_wdt(); +-} +--- a/arch/mips/lantiq/xway/setup-xway.c ++++ /dev/null +@@ -1,20 +0,0 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 John Crispin <blogic@openwrt.org> +- */ +- +-#include <lantiq_soc.h> +- +-#include "../prom.h" +-#include "devices.h" +- +-void __init ltq_soc_setup(void) +-{ +- ltq_register_asc(0); +- ltq_register_asc(1); +- ltq_register_gpio(); +- ltq_register_wdt(); +-} +--- /dev/null ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -0,0 +1,77 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/ioport.h> ++ ++#include <lantiq_soc.h> ++ ++#include "../devices.h" ++ ++/* clock control register */ ++#define LTQ_CGU_IFCCR 0x0018 ++ ++/* the enable / disable registers */ ++#define LTQ_PMU_PWDCR 0x1C ++#define LTQ_PMU_PWDSR 0x20 ++ ++#define ltq_pmu_w32(x, y) ltq_w32((x), ltq_pmu_membase + (y)) ++#define ltq_pmu_r32(x) ltq_r32(ltq_pmu_membase + (x)) ++ ++static struct resource ltq_cgu_resource = ++ MEM_RES("cgu", LTQ_CGU_BASE_ADDR, LTQ_CGU_SIZE); ++ ++static struct resource ltq_pmu_resource = ++ MEM_RES("pmu", LTQ_PMU_BASE_ADDR, LTQ_PMU_SIZE); ++ ++static struct resource ltq_ebu_resource = ++ MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); ++ ++void __iomem *ltq_cgu_membase; ++void __iomem *ltq_ebu_membase; ++static void __iomem *ltq_pmu_membase; ++ ++void ltq_cgu_enable(unsigned int clk) ++{ ++ ltq_cgu_w32(ltq_cgu_r32(LTQ_CGU_IFCCR) | clk, LTQ_CGU_IFCCR); ++} ++ ++void ltq_pmu_enable(unsigned int module) ++{ ++ int err = 1000000; ++ ++ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) & ~module, LTQ_PMU_PWDCR); ++ do {} while (--err && (ltq_pmu_r32(LTQ_PMU_PWDSR) & module)); ++ ++ if (!err) ++ panic("activating PMU module failed!\n"); ++} ++EXPORT_SYMBOL(ltq_pmu_enable); ++ ++void ltq_pmu_disable(unsigned int module) ++{ ++ ltq_pmu_w32(ltq_pmu_r32(LTQ_PMU_PWDCR) | module, LTQ_PMU_PWDCR); ++} ++EXPORT_SYMBOL(ltq_pmu_disable); ++ ++void __init ltq_soc_init(void) ++{ ++ ltq_pmu_membase = ltq_remap_resource(<q_pmu_resource); ++ if (!ltq_pmu_membase) ++ panic("Failed to remap pmu memory\n"); ++ ++ ltq_cgu_membase = ltq_remap_resource(<q_cgu_resource); ++ if (!ltq_cgu_membase) ++ panic("Failed to remap cgu memory\n"); ++ ++ ltq_ebu_membase = ltq_remap_resource(<q_ebu_resource); ++ if (!ltq_ebu_membase) ++ panic("Failed to remap ebu memory\n"); ++ ++ /* make sure to unprotect the memory region where flash is located */ ++ ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_BUSCON0) & ~EBU_WRDIS, LTQ_EBU_BUSCON0); ++} +--- a/drivers/watchdog/lantiq_wdt.c ++++ b/drivers/watchdog/lantiq_wdt.c +@@ -16,7 +16,7 @@ + #include <linux/clk.h> + #include <linux/io.h> + +-#include <lantiq.h> ++#include <lantiq_soc.h> + + /* Section 3.4 of the datasheet + * The password sequence protects the WDT control register from unintended diff --git a/target/linux/lantiq/patches/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch b/target/linux/lantiq/patches/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch new file mode 100644 index 0000000000..97d9461a59 --- /dev/null +++ b/target/linux/lantiq/patches/0005-MIPS-lantiq-make-irq.c-support-the-FALC-ON.patch @@ -0,0 +1,70 @@ +From d9355bb07878f9aa40856cc437c43cedc87662fc Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 11 Aug 2011 12:25:55 +0200 +Subject: [PATCH 05/24] MIPS: lantiq: make irq.c support the FALC-ON + +There are minor differences in how irqs work on xway and falcon socs. +Xway needs 2 quirks that we need to disable for falcon to also work with +this code. + +* EBU irq does not need to send a special ack to the EBU +* The EIU does not exist + +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Cc: linux-mips@linux-mips.org +--- + arch/mips/lantiq/irq.c | 24 +++++++++++++----------- + 1 files changed, 13 insertions(+), 11 deletions(-) + +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -195,7 +195,7 @@ static void ltq_hw_irqdispatch(int modul + do_IRQ((int)irq + INT_NUM_IM0_IRL0 + (INT_NUM_IM_OFFSET * module)); + + /* if this is a EBU irq, we need to ack it or get a deadlock */ +- if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0)) ++ if ((irq == LTQ_ICU_EBU_IRQ) && (module == 0) && LTQ_EBU_PCC_ISTAT) + ltq_ebu_w32(ltq_ebu_r32(LTQ_EBU_PCC_ISTAT) | 0x10, + LTQ_EBU_PCC_ISTAT); + } +@@ -260,17 +260,19 @@ void __init arch_init_irq(void) + if (!ltq_icu_membase) + panic("Failed to remap icu memory\n"); + +- if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) +- panic("Failed to insert eiu memory\n"); ++ if (LTQ_EIU_BASE_ADDR) { ++ if (insert_resource(&iomem_resource, <q_eiu_resource) < 0) ++ panic("Failed to insert eiu memory\n"); ++ ++ if (request_mem_region(ltq_eiu_resource.start, ++ resource_size(<q_eiu_resource), "eiu") < 0) ++ panic("Failed to request eiu memory\n"); + +- if (request_mem_region(ltq_eiu_resource.start, +- resource_size(<q_eiu_resource), "eiu") < 0) +- panic("Failed to request eiu memory\n"); +- +- ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, ++ ltq_eiu_membase = ioremap_nocache(ltq_eiu_resource.start, + resource_size(<q_eiu_resource)); +- if (!ltq_eiu_membase) +- panic("Failed to remap eiu memory\n"); ++ if (!ltq_eiu_membase) ++ panic("Failed to remap eiu memory\n"); ++ } + + /* make sure all irqs are turned off by default */ + for (i = 0; i < 5; i++) +@@ -296,8 +298,8 @@ void __init arch_init_irq(void) + + for (i = INT_NUM_IRQ0; + i <= (INT_NUM_IRQ0 + (5 * INT_NUM_IM_OFFSET)); i++) +- if ((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || +- (i == LTQ_EIU_IR2)) ++ if (((i == LTQ_EIU_IR0) || (i == LTQ_EIU_IR1) || ++ (i == LTQ_EIU_IR2)) && LTQ_EIU_BASE_ADDR) + irq_set_chip_and_handler(i, <q_eiu_type, + handle_level_irq); + /* EIU3-5 only exist on ar9 and vr9 */ diff --git a/target/linux/lantiq/patches/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch b/target/linux/lantiq/patches/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch new file mode 100644 index 0000000000..780afa0025 --- /dev/null +++ b/target/linux/lantiq/patches/0006-MIPS-lantiq-add-basic-support-for-FALC-ON.patch @@ -0,0 +1,1023 @@ +From ff57bc17a9964d24708759c6d78a51e337563d5f Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 11 Aug 2011 14:33:04 +0200 +Subject: [PATCH 06/24] MIPS: lantiq: add basic support for FALC-ON + +Adds support for the FALC-ON SoC. This SoC is from the fiber to the home GPON +series. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Cc: linux-mips@linux-mips.org +--- + .../include/asm/mach-lantiq/falcon/falcon_irq.h | 268 ++++++++++++++++++++ + arch/mips/include/asm/mach-lantiq/falcon/irq.h | 18 ++ + .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 140 ++++++++++ + arch/mips/include/asm/mach-lantiq/lantiq.h | 1 + + arch/mips/lantiq/Kconfig | 4 + + arch/mips/lantiq/Makefile | 1 + + arch/mips/lantiq/Platform | 1 + + arch/mips/lantiq/falcon/Makefile | 1 + + arch/mips/lantiq/falcon/clk.c | 44 ++++ + arch/mips/lantiq/falcon/devices.c | 87 +++++++ + arch/mips/lantiq/falcon/devices.h | 18 ++ + arch/mips/lantiq/falcon/prom.c | 72 ++++++ + arch/mips/lantiq/falcon/reset.c | 87 +++++++ + arch/mips/lantiq/falcon/sysctrl.c | 181 +++++++++++++ + 14 files changed, 923 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/irq.h + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h + create mode 100644 arch/mips/lantiq/falcon/Makefile + create mode 100644 arch/mips/lantiq/falcon/clk.c + create mode 100644 arch/mips/lantiq/falcon/devices.c + create mode 100644 arch/mips/lantiq/falcon/devices.h + create mode 100644 arch/mips/lantiq/falcon/prom.c + create mode 100644 arch/mips/lantiq/falcon/reset.c + create mode 100644 arch/mips/lantiq/falcon/sysctrl.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h +@@ -0,0 +1,268 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> ++ */ ++ ++#ifndef _FALCON_IRQ__ ++#define _FALCON_IRQ__ ++ ++#define INT_NUM_IRQ0 8 ++#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) ++#define INT_NUM_IM1_IRL0 (INT_NUM_IM0_IRL0 + 32) ++#define INT_NUM_IM2_IRL0 (INT_NUM_IM1_IRL0 + 32) ++#define INT_NUM_IM3_IRL0 (INT_NUM_IM2_IRL0 + 32) ++#define INT_NUM_IM4_IRL0 (INT_NUM_IM3_IRL0 + 32) ++#define INT_NUM_EXTRA_START (INT_NUM_IM4_IRL0 + 32) ++#define INT_NUM_IM_OFFSET (INT_NUM_IM1_IRL0 - INT_NUM_IM0_IRL0) ++ ++#define MIPS_CPU_TIMER_IRQ 7 ++ ++/* HOST IF Event Interrupt */ ++#define FALCON_IRQ_HOST (INT_NUM_IM0_IRL0 + 0) ++/* HOST IF Mailbox0 Receive Interrupt */ ++#define FALCON_IRQ_HOST_MB0_RX (INT_NUM_IM0_IRL0 + 1) ++/* HOST IF Mailbox0 Transmit Interrupt */ ++#define FALCON_IRQ_HOST_MB0_TX (INT_NUM_IM0_IRL0 + 2) ++/* HOST IF Mailbox1 Receive Interrupt */ ++#define FALCON_IRQ_HOST_MB1_RX (INT_NUM_IM0_IRL0 + 3) ++/* HOST IF Mailbox1 Transmit Interrupt */ ++#define FALCON_IRQ_HOST_MB1_TX (INT_NUM_IM0_IRL0 + 4) ++/* I2C Last Single Data Transfer Request */ ++#define FALCON_IRQ_I2C_LSREQ (INT_NUM_IM0_IRL0 + 8) ++/* I2C Single Data Transfer Request */ ++#define FALCON_IRQ_I2C_SREQ (INT_NUM_IM0_IRL0 + 9) ++/* I2C Last Burst Data Transfer Request */ ++#define FALCON_IRQ_I2C_LBREQ (INT_NUM_IM0_IRL0 + 10) ++/* I2C Burst Data Transfer Request */ ++#define FALCON_IRQ_I2C_BREQ (INT_NUM_IM0_IRL0 + 11) ++/* I2C Error Interrupt */ ++#define FALCON_IRQ_I2C_I2C_ERR (INT_NUM_IM0_IRL0 + 12) ++/* I2C Protocol Interrupt */ ++#define FALCON_IRQ_I2C_I2C_P (INT_NUM_IM0_IRL0 + 13) ++/* SSC Transmit Interrupt */ ++#define FALCON_IRQ_SSC_T (INT_NUM_IM0_IRL0 + 14) ++/* SSC Receive Interrupt */ ++#define FALCON_IRQ_SSC_R (INT_NUM_IM0_IRL0 + 15) ++/* SSC Error Interrupt */ ++#define FALCON_IRQ_SSC_E (INT_NUM_IM0_IRL0 + 16) ++/* SSC Frame Interrupt */ ++#define FALCON_IRQ_SSC_F (INT_NUM_IM0_IRL0 + 17) ++/* Advanced Encryption Standard Interrupt */ ++#define FALCON_IRQ_AES_AES (INT_NUM_IM0_IRL0 + 27) ++/* Secure Hash Algorithm Interrupt */ ++#define FALCON_IRQ_SHA_HASH (INT_NUM_IM0_IRL0 + 28) ++/* PCM Receive Interrupt */ ++#define FALCON_IRQ_PCM_RX (INT_NUM_IM0_IRL0 + 29) ++/* PCM Transmit Interrupt */ ++#define FALCON_IRQ_PCM_TX (INT_NUM_IM0_IRL0 + 30) ++/* PCM Transmit Crash Interrupt */ ++#define FALCON_IRQ_PCM_HW2_CRASH (INT_NUM_IM0_IRL0 + 31) ++ ++/* EBU Serial Flash Command Error */ ++#define FALCON_IRQ_EBU_SF_CMDERR (INT_NUM_IM1_IRL0 + 0) ++/* EBU Serial Flash Command Overwrite Error */ ++#define FALCON_IRQ_EBU_SF_COVERR (INT_NUM_IM1_IRL0 + 1) ++/* EBU Serial Flash Busy */ ++#define FALCON_IRQ_EBU_SF_BUSY (INT_NUM_IM1_IRL0 + 2) ++/* External Interrupt from GPIO P0 */ ++#define FALCON_IRQ_GPIO_P0 (INT_NUM_IM1_IRL0 + 4) ++/* External Interrupt from GPIO P1 */ ++#define FALCON_IRQ_GPIO_P1 (INT_NUM_IM1_IRL0 + 5) ++/* External Interrupt from GPIO P2 */ ++#define FALCON_IRQ_GPIO_P2 (INT_NUM_IM1_IRL0 + 6) ++/* External Interrupt from GPIO P3 */ ++#define FALCON_IRQ_GPIO_P3 (INT_NUM_IM1_IRL0 + 7) ++/* External Interrupt from GPIO P4 */ ++#define FALCON_IRQ_GPIO_P4 (INT_NUM_IM1_IRL0 + 8) ++/* 8kHz backup interrupt derived from core-PLL */ ++#define FALCON_IRQ_FSC_BKP (INT_NUM_IM1_IRL0 + 10) ++/* FSC Timer Interrupt 0 */ ++#define FALCON_IRQ_FSCT_CMP0 (INT_NUM_IM1_IRL0 + 11) ++/* FSC Timer Interrupt 1 */ ++#define FALCON_IRQ_FSCT_CMP1 (INT_NUM_IM1_IRL0 + 12) ++/* 8kHz root interrupt derived from GPON interface */ ++#define FALCON_IRQ_FSC_ROOT (INT_NUM_IM1_IRL0 + 13) ++/* Time of Day */ ++#define FALCON_IRQ_TOD (INT_NUM_IM1_IRL0 + 14) ++/* PMA Interrupt from IntNode of the 200MHz Domain */ ++#define FALCON_IRQ_PMA_200M (INT_NUM_IM1_IRL0 + 15) ++/* PMA Interrupt from IntNode of the TX Clk Domain */ ++#define FALCON_IRQ_PMA_TX (INT_NUM_IM1_IRL0 + 16) ++/* PMA Interrupt from IntNode of the RX Clk Domain */ ++#define FALCON_IRQ_PMA_RX (INT_NUM_IM1_IRL0 + 17) ++/* SYS1 Interrupt */ ++#define FALCON_IRQ_SYS1 (INT_NUM_IM1_IRL0 + 20) ++/* SYS GPE Interrupt */ ++#define FALCON_IRQ_SYS_GPE (INT_NUM_IM1_IRL0 + 21) ++/* Watchdog Access Error Interrupt */ ++#define FALCON_IRQ_WDT_AEIR (INT_NUM_IM1_IRL0 + 24) ++/* Watchdog Prewarning Interrupt */ ++#define FALCON_IRQ_WDT_PIR (INT_NUM_IM1_IRL0 + 25) ++/* SBIU interrupt */ ++#define FALCON_IRQ_SBIU0 (INT_NUM_IM1_IRL0 + 27) ++/* FPI Bus Control Unit Interrupt */ ++#define FALCON_IRQ_BCU0 (INT_NUM_IM1_IRL0 + 29) ++/* DDR Controller Interrupt */ ++#define FALCON_IRQ_DDR (INT_NUM_IM1_IRL0 + 30) ++/* Crossbar Error Interrupt */ ++#define FALCON_IRQ_XBAR_ERROR (INT_NUM_IM1_IRL0 + 31) ++ ++/* ICTRLL 0 Interrupt */ ++#define FALCON_IRQ_ICTRLL0 (INT_NUM_IM2_IRL0 + 0) ++/* ICTRLL 1 Interrupt */ ++#define FALCON_IRQ_ICTRLL1 (INT_NUM_IM2_IRL0 + 1) ++/* ICTRLL 2 Interrupt */ ++#define FALCON_IRQ_ICTRLL2 (INT_NUM_IM2_IRL0 + 2) ++/* ICTRLL 3 Interrupt */ ++#define FALCON_IRQ_ICTRLL3 (INT_NUM_IM2_IRL0 + 3) ++/* OCTRLL 0 Interrupt */ ++#define FALCON_IRQ_OCTRLL0 (INT_NUM_IM2_IRL0 + 4) ++/* OCTRLL 1 Interrupt */ ++#define FALCON_IRQ_OCTRLL1 (INT_NUM_IM2_IRL0 + 5) ++/* OCTRLL 2 Interrupt */ ++#define FALCON_IRQ_OCTRLL2 (INT_NUM_IM2_IRL0 + 6) ++/* OCTRLL 3 Interrupt */ ++#define FALCON_IRQ_OCTRLL3 (INT_NUM_IM2_IRL0 + 7) ++/* OCTRLG Interrupt */ ++#define FALCON_IRQ_OCTRLG (INT_NUM_IM2_IRL0 + 9) ++/* IQM Interrupt */ ++#define FALCON_IRQ_IQM (INT_NUM_IM2_IRL0 + 10) ++/* FSQM Interrupt */ ++#define FALCON_IRQ_FSQM (INT_NUM_IM2_IRL0 + 11) ++/* TMU Interrupt */ ++#define FALCON_IRQ_TMU (INT_NUM_IM2_IRL0 + 12) ++/* LINK1 Interrupt */ ++#define FALCON_IRQ_LINK1 (INT_NUM_IM2_IRL0 + 14) ++/* ICTRLC 0 Interrupt */ ++#define FALCON_IRQ_ICTRLC0 (INT_NUM_IM2_IRL0 + 16) ++/* ICTRLC 1 Interrupt */ ++#define FALCON_IRQ_ICTRLC1 (INT_NUM_IM2_IRL0 + 17) ++/* OCTRLC Interrupt */ ++#define FALCON_IRQ_OCTRLC (INT_NUM_IM2_IRL0 + 18) ++/* CONFIG Break Interrupt */ ++#define FALCON_IRQ_CONFIG_BREAK (INT_NUM_IM2_IRL0 + 19) ++/* CONFIG Interrupt */ ++#define FALCON_IRQ_CONFIG (INT_NUM_IM2_IRL0 + 20) ++/* Dispatcher Interrupt */ ++#define FALCON_IRQ_DISP (INT_NUM_IM2_IRL0 + 21) ++/* TBM Interrupt */ ++#define FALCON_IRQ_TBM (INT_NUM_IM2_IRL0 + 22) ++/* GTC Downstream Interrupt */ ++#define FALCON_IRQ_GTC_DS (INT_NUM_IM2_IRL0 + 29) ++/* GTC Upstream Interrupt */ ++#define FALCON_IRQ_GTC_US (INT_NUM_IM2_IRL0 + 30) ++/* EIM Interrupt */ ++#define FALCON_IRQ_EIM (INT_NUM_IM2_IRL0 + 31) ++ ++/* ASC0 Transmit Interrupt */ ++#define FALCON_IRQ_ASC0_T (INT_NUM_IM3_IRL0 + 0) ++/* ASC0 Receive Interrupt */ ++#define FALCON_IRQ_ASC0_R (INT_NUM_IM3_IRL0 + 1) ++/* ASC0 Error Interrupt */ ++#define FALCON_IRQ_ASC0_E (INT_NUM_IM3_IRL0 + 2) ++/* ASC0 Transmit Buffer Interrupt */ ++#define FALCON_IRQ_ASC0_TB (INT_NUM_IM3_IRL0 + 3) ++/* ASC0 Autobaud Start Interrupt */ ++#define FALCON_IRQ_ASC0_ABST (INT_NUM_IM3_IRL0 + 4) ++/* ASC0 Autobaud Detection Interrupt */ ++#define FALCON_IRQ_ASC0_ABDET (INT_NUM_IM3_IRL0 + 5) ++/* ASC1 Modem Status Interrupt */ ++#define FALCON_IRQ_ASC0_MS (INT_NUM_IM3_IRL0 + 6) ++/* ASC0 Soft Flow Control Interrupt */ ++#define FALCON_IRQ_ASC0_SFC (INT_NUM_IM3_IRL0 + 7) ++/* ASC1 Transmit Interrupt */ ++#define FALCON_IRQ_ASC1_T (INT_NUM_IM3_IRL0 + 8) ++/* ASC1 Receive Interrupt */ ++#define FALCON_IRQ_ASC1_R (INT_NUM_IM3_IRL0 + 9) ++/* ASC1 Error Interrupt */ ++#define FALCON_IRQ_ASC1_E (INT_NUM_IM3_IRL0 + 10) ++/* ASC1 Transmit Buffer Interrupt */ ++#define FALCON_IRQ_ASC1_TB (INT_NUM_IM3_IRL0 + 11) ++/* ASC1 Autobaud Start Interrupt */ ++#define FALCON_IRQ_ASC1_ABST (INT_NUM_IM3_IRL0 + 12) ++/* ASC1 Autobaud Detection Interrupt */ ++#define FALCON_IRQ_ASC1_ABDET (INT_NUM_IM3_IRL0 + 13) ++/* ASC1 Modem Status Interrupt */ ++#define FALCON_IRQ_ASC1_MS (INT_NUM_IM3_IRL0 + 14) ++/* ASC1 Soft Flow Control Interrupt */ ++#define FALCON_IRQ_ASC1_SFC (INT_NUM_IM3_IRL0 + 15) ++/* GPTC Timer/Counter 1A Interrupt */ ++#define FALCON_IRQ_GPTC_TC1A (INT_NUM_IM3_IRL0 + 16) ++/* GPTC Timer/Counter 1B Interrupt */ ++#define FALCON_IRQ_GPTC_TC1B (INT_NUM_IM3_IRL0 + 17) ++/* GPTC Timer/Counter 2A Interrupt */ ++#define FALCON_IRQ_GPTC_TC2A (INT_NUM_IM3_IRL0 + 18) ++/* GPTC Timer/Counter 2B Interrupt */ ++#define FALCON_IRQ_GPTC_TC2B (INT_NUM_IM3_IRL0 + 19) ++/* GPTC Timer/Counter 3A Interrupt */ ++#define FALCON_IRQ_GPTC_TC3A (INT_NUM_IM3_IRL0 + 20) ++/* GPTC Timer/Counter 3B Interrupt */ ++#define FALCON_IRQ_GPTC_TC3B (INT_NUM_IM3_IRL0 + 21) ++/* DFEV0, Channel 1 Transmit Interrupt */ ++#define FALCON_IRQ_DFEV0_2TX (INT_NUM_IM3_IRL0 + 26) ++/* DFEV0, Channel 1 Receive Interrupt */ ++#define FALCON_IRQ_DFEV0_2RX (INT_NUM_IM3_IRL0 + 27) ++/* DFEV0, Channel 1 General Purpose Interrupt */ ++#define FALCON_IRQ_DFEV0_2GP (INT_NUM_IM3_IRL0 + 28) ++/* DFEV0, Channel 0 Transmit Interrupt */ ++#define FALCON_IRQ_DFEV0_1TX (INT_NUM_IM3_IRL0 + 29) ++/* DFEV0, Channel 0 Receive Interrupt */ ++#define FALCON_IRQ_DFEV0_1RX (INT_NUM_IM3_IRL0 + 30) ++/* DFEV0, Channel 0 General Purpose Interrupt */ ++#define FALCON_IRQ_DFEV0_1GP (INT_NUM_IM3_IRL0 + 31) ++ ++/* ICTRLL 0 Error */ ++#define FALCON_IRQ_ICTRLL0_ERR (INT_NUM_IM4_IRL0 + 0) ++/* ICTRLL 1 Error */ ++#define FALCON_IRQ_ICTRLL1_ERR (INT_NUM_IM4_IRL0 + 1) ++/* ICTRLL 2 Error */ ++#define FALCON_IRQ_ICTRLL2_ERR (INT_NUM_IM4_IRL0 + 2) ++/* ICTRLL 3 Error */ ++#define FALCON_IRQ_ICTRLL3_ERR (INT_NUM_IM4_IRL0 + 3) ++/* OCTRLL 0 Error */ ++#define FALCON_IRQ_OCTRLL0_ERR (INT_NUM_IM4_IRL0 + 4) ++/* OCTRLL 1 Error */ ++#define FALCON_IRQ_OCTRLL1_ERR (INT_NUM_IM4_IRL0 + 5) ++/* OCTRLL 2 Error */ ++#define FALCON_IRQ_OCTRLL2_ERR (INT_NUM_IM4_IRL0 + 6) ++/* OCTRLL 3 Error */ ++#define FALCON_IRQ_OCTRLL3_ERR (INT_NUM_IM4_IRL0 + 7) ++/* ICTRLG Error */ ++#define FALCON_IRQ_ICTRLG_ERR (INT_NUM_IM4_IRL0 + 8) ++/* OCTRLG Error */ ++#define FALCON_IRQ_OCTRLG_ERR (INT_NUM_IM4_IRL0 + 9) ++/* IQM Error */ ++#define FALCON_IRQ_IQM_ERR (INT_NUM_IM4_IRL0 + 10) ++/* FSQM Error */ ++#define FALCON_IRQ_FSQM_ERR (INT_NUM_IM4_IRL0 + 11) ++/* TMU Error */ ++#define FALCON_IRQ_TMU_ERR (INT_NUM_IM4_IRL0 + 12) ++/* MPS Status Interrupt #0 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR0 (INT_NUM_IM4_IRL0 + 14) ++/* MPS Status Interrupt #1 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR1 (INT_NUM_IM4_IRL0 + 15) ++/* MPS Status Interrupt #2 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR2 (INT_NUM_IM4_IRL0 + 16) ++/* MPS Status Interrupt #3 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR3 (INT_NUM_IM4_IRL0 + 17) ++/* MPS Status Interrupt #4 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR4 (INT_NUM_IM4_IRL0 + 18) ++/* MPS Status Interrupt #5 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR5 (INT_NUM_IM4_IRL0 + 19) ++/* MPS Status Interrupt #6 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR6 (INT_NUM_IM4_IRL0 + 20) ++/* MPS Status Interrupt #7 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR7 (INT_NUM_IM4_IRL0 + 21) ++/* MPS Status Interrupt #8 (VPE1 to VPE0) */ ++#define FALCON_IRQ_MPS_IR8 (INT_NUM_IM4_IRL0 + 22) ++/* VPE0 Exception Level Flag Interrupt */ ++#define FALCON_IRQ_VPE0_EXL (INT_NUM_IM4_IRL0 + 29) ++/* VPE0 Error Level Flag Interrupt */ ++#define FALCON_IRQ_VPE0_ERL (INT_NUM_IM4_IRL0 + 30) ++/* VPE0 Performance Monitoring Counter Interrupt */ ++#define FALCON_IRQ_VPE0_PMCIR (INT_NUM_IM4_IRL0 + 31) ++ ++#endif /* _FALCON_IRQ__ */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/irq.h +@@ -0,0 +1,18 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ */ ++ ++#ifndef __FALCON_IRQ_H ++#define __FALCON_IRQ_H ++ ++#include <falcon_irq.h> ++ ++#define NR_IRQS 328 ++ ++#include_next <irq.h> ++ ++#endif +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +@@ -0,0 +1,140 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _LTQ_FALCON_H__ ++#define _LTQ_FALCON_H__ ++ ++#ifdef CONFIG_SOC_FALCON ++ ++#include <lantiq.h> ++ ++/* Chip IDs */ ++#define SOC_ID_FALCON 0x01B8 ++ ++/* SoC Types */ ++#define SOC_TYPE_FALCON 0x01 ++ ++/* ASC0/1 - serial port */ ++#define LTQ_ASC0_BASE_ADDR 0x1E100C00 ++#define LTQ_ASC1_BASE_ADDR 0x1E100B00 ++#define LTQ_ASC_SIZE 0x100 ++ ++#define LTQ_ASC_TIR(x) (INT_NUM_IM3_IRL0 + (x * 8)) ++#define LTQ_ASC_RIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 1) ++#define LTQ_ASC_EIR(x) (INT_NUM_IM3_IRL0 + (x * 8) + 2) ++ ++/* during early_printk no ioremap possible at this early stage ++ lets use KSEG1 instead */ ++#define LTQ_EARLY_ASC KSEG1ADDR(LTQ_ASC0_BASE_ADDR) ++ ++/* ICU - interrupt control unit */ ++#define LTQ_ICU_BASE_ADDR 0x1F880200 ++#define LTQ_ICU_SIZE 0x100 ++ ++/* WDT */ ++#define LTQ_WDT_BASE_ADDR 0x1F8803F0 ++#define LTQ_WDT_SIZE 0x10 ++ ++#define LTQ_RST_CAUSE_WDTRST 0x0002 ++ ++/* EBU - external bus unit */ ++#define LTQ_EBU_BASE_ADDR 0x18000000 ++#define LTQ_EBU_SIZE 0x0100 ++ ++#define LTQ_EBU_MODCON 0x000C ++ ++/* GPIO */ ++#define LTQ_GPIO0_BASE_ADDR 0x1D810000 ++#define LTQ_GPIO0_SIZE 0x0080 ++#define LTQ_GPIO1_BASE_ADDR 0x1E800100 ++#define LTQ_GPIO1_SIZE 0x0080 ++#define LTQ_GPIO2_BASE_ADDR 0x1D810100 ++#define LTQ_GPIO2_SIZE 0x0080 ++#define LTQ_GPIO3_BASE_ADDR 0x1E800200 ++#define LTQ_GPIO3_SIZE 0x0080 ++#define LTQ_GPIO4_BASE_ADDR 0x1E800300 ++#define LTQ_GPIO4_SIZE 0x0080 ++#define LTQ_PADCTRL0_BASE_ADDR 0x1DB01000 ++#define LTQ_PADCTRL0_SIZE 0x0100 ++#define LTQ_PADCTRL1_BASE_ADDR 0x1E800400 ++#define LTQ_PADCTRL1_SIZE 0x0100 ++#define LTQ_PADCTRL2_BASE_ADDR 0x1DB02000 ++#define LTQ_PADCTRL2_SIZE 0x0100 ++#define LTQ_PADCTRL3_BASE_ADDR 0x1E800500 ++#define LTQ_PADCTRL3_SIZE 0x0100 ++#define LTQ_PADCTRL4_BASE_ADDR 0x1E800600 ++#define LTQ_PADCTRL4_SIZE 0x0100 ++ ++/* CHIP ID */ ++#define LTQ_STATUS_BASE_ADDR 0x1E802000 ++ ++#define LTQ_FALCON_CHIPID ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x0c)) ++#define LTQ_FALCON_CHIPCONF ((u32 *)(KSEG1 + LTQ_STATUS_BASE_ADDR + 0x40)) ++ ++/* SYSCTL - start/stop/restart/configure/... different parts of the Soc */ ++#define LTQ_SYS1_BASE_ADDR 0x1EF00000 ++#define LTQ_SYS1_SIZE 0x0100 ++#define LTQ_STATUS_BASE_ADDR 0x1E802000 ++#define LTQ_STATUS_SIZE 0x0080 ++#define LTQ_SYS_ETH_BASE_ADDR 0x1DB00000 ++#define LTQ_SYS_ETH_SIZE 0x0100 ++#define LTQ_SYS_GPE_BASE_ADDR 0x1D700000 ++#define LTQ_SYS_GPE_SIZE 0x0100 ++ ++#define SYSCTL_SYS1 0 ++#define SYSCTL_SYSETH 1 ++#define SYSCTL_SYSGPE 2 ++ ++/* Activation Status Register */ ++#define ACTS_ASC1_ACT 0x00000800 ++#define ACTS_P0 0x00010000 ++#define ACTS_P1 0x00010000 ++#define ACTS_P2 0x00020000 ++#define ACTS_P3 0x00020000 ++#define ACTS_P4 0x00040000 ++#define ACTS_PADCTRL0 0x00100000 ++#define ACTS_PADCTRL1 0x00100000 ++#define ACTS_PADCTRL2 0x00200000 ++#define ACTS_PADCTRL3 0x00200000 ++#define ACTS_PADCTRL4 0x00400000 ++ ++extern void ltq_sysctl_activate(int module, unsigned int mask); ++extern void ltq_sysctl_deactivate(int module, unsigned int mask); ++extern void ltq_sysctl_clken(int module, unsigned int mask); ++extern void ltq_sysctl_clkdis(int module, unsigned int mask); ++extern void ltq_sysctl_reboot(int module, unsigned int mask); ++extern int ltq_gpe_is_activated(unsigned int mask); ++ ++/* global register ranges */ ++extern __iomem void *ltq_ebu_membase; ++extern __iomem void *ltq_sys1_membase; ++#define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) ++#define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ++#define ltq_ebu_w32_mask(clear, set, reg) \ ++ ltq_ebu_w32((ltq_ebu_r32(reg) & ~(clear)) | (set), reg) ++ ++#define ltq_sys1_w32(x, y) ltq_w32((x), ltq_sys1_membase + (y)) ++#define ltq_sys1_r32(x) ltq_r32(ltq_sys1_membase + (x)) ++#define ltq_sys1_w32_mask(clear, set, reg) \ ++ ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg) ++ ++/* gpio_request wrapper to help configure the pin */ ++extern int ltq_gpio_request(unsigned int pin, unsigned int val, ++ unsigned int dir, const char *name); ++extern int ltq_gpio_mux_set(unsigned int pin, unsigned int mux); ++ ++/* to keep the irq code generic we need to define these to 0 as falcon ++ has no EIU/EBU */ ++#define LTQ_EIU_BASE_ADDR 0 ++#define LTQ_EBU_PCC_ISTAT 0 ++ ++#define ltq_is_ar9() 0 ++#define ltq_is_vr9() 0 ++ ++#endif /* CONFIG_SOC_FALCON */ ++#endif /* _LTQ_XWAY_H__ */ +--- a/arch/mips/include/asm/mach-lantiq/lantiq.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq.h +@@ -25,6 +25,7 @@ extern unsigned int ltq_get_soc_type(voi + /* clock speeds */ + #define CLOCK_60M 60000000 + #define CLOCK_83M 83333333 ++#define CLOCK_100M 100000000 + #define CLOCK_111M 111111111 + #define CLOCK_133M 133333333 + #define CLOCK_167M 166666667 +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -16,8 +16,12 @@ config SOC_XWAY + bool "XWAY" + select SOC_TYPE_XWAY + select HW_HAS_PCI ++ ++config SOC_FALCON ++ bool "FALCON" + endchoice + + source "arch/mips/lantiq/xway/Kconfig" ++source "arch/mips/lantiq/falcon/Kconfig" + + endif +--- a/arch/mips/lantiq/Makefile ++++ b/arch/mips/lantiq/Makefile +@@ -9,3 +9,4 @@ obj-y := irq.o setup.o clk.o prom.o devi + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + + obj-$(CONFIG_SOC_TYPE_XWAY) += xway/ ++obj-$(CONFIG_SOC_FALCON) += falcon/ +--- a/arch/mips/lantiq/Platform ++++ b/arch/mips/lantiq/Platform +@@ -6,3 +6,4 @@ platform-$(CONFIG_LANTIQ) += lantiq/ + cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq + load-$(CONFIG_LANTIQ) = 0xffffffff80002000 + cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway ++cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon +--- /dev/null ++++ b/arch/mips/lantiq/falcon/Makefile +@@ -0,0 +1 @@ ++obj-y := clk.o prom.o reset.o sysctrl.o devices.o +--- /dev/null ++++ b/arch/mips/lantiq/falcon/clk.c +@@ -0,0 +1,44 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/ioport.h> ++#include <linux/module.h> ++ ++#include <lantiq_soc.h> ++ ++#include "devices.h" ++ ++/* CPU0 Clock Control Register */ ++#define LTQ_SYS1_CPU0CC 0x0040 ++/* clock divider bit */ ++#define LTQ_CPU0CC_CPUDIV 0x0001 ++ ++unsigned int ++ltq_get_io_region_clock(void) ++{ ++ return CLOCK_200M; ++} ++EXPORT_SYMBOL(ltq_get_io_region_clock); ++ ++unsigned int ++ltq_get_cpu_hz(void) ++{ ++ if (ltq_sys1_r32(LTQ_SYS1_CPU0CC) & LTQ_CPU0CC_CPUDIV) ++ return CLOCK_200M; ++ else ++ return CLOCK_400M; ++} ++EXPORT_SYMBOL(ltq_get_cpu_hz); ++ ++unsigned int ++ltq_get_fpi_hz(void) ++{ ++ return CLOCK_100M; ++} ++EXPORT_SYMBOL(ltq_get_fpi_hz); +--- /dev/null ++++ b/arch/mips/lantiq/falcon/devices.c +@@ -0,0 +1,87 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/platform_device.h> ++#include <linux/mtd/nand.h> ++ ++#include <lantiq_soc.h> ++ ++#include "devices.h" ++ ++/* nand flash */ ++/* address lines used for NAND control signals */ ++#define NAND_ADDR_ALE 0x10000 ++#define NAND_ADDR_CLE 0x20000 ++/* Ready/Busy Status */ ++#define MODCON_STS 0x0002 ++/* Ready/Busy Status Edge */ ++#define MODCON_STSEDGE 0x0004 ++ ++static const char *part_probes[] = { "cmdlinepart", NULL }; ++ ++static int ++falcon_nand_ready(struct mtd_info *mtd) ++{ ++ u32 modcon = ltq_ebu_r32(LTQ_EBU_MODCON); ++ ++ return (((modcon & (MODCON_STS | MODCON_STSEDGE)) == ++ (MODCON_STS | MODCON_STSEDGE))); ++} ++ ++static void ++falcon_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) ++{ ++ struct nand_chip *this = mtd->priv; ++ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ nandaddr &= ~(NAND_ADDR_ALE | NAND_ADDR_CLE); ++ ++ if (ctrl & NAND_CLE) ++ nandaddr |= NAND_ADDR_CLE; ++ if (ctrl & NAND_ALE) ++ nandaddr |= NAND_ADDR_ALE; ++ ++ this->IO_ADDR_W = (void __iomem *) nandaddr; ++ } ++ ++ if (cmd != NAND_CMD_NONE) ++ writeb(cmd, this->IO_ADDR_W); ++} ++ ++static struct platform_nand_data falcon_flash_nand_data = { ++ .chip = { ++ .nr_chips = 1, ++ .chip_delay = 25, ++ .part_probe_types = part_probes, ++ }, ++ .ctrl = { ++ .cmd_ctrl = falcon_hwcontrol, ++ .dev_ready = falcon_nand_ready, ++ } ++}; ++ ++static struct resource ltq_nand_res = ++ MEM_RES("nand", LTQ_FLASH_START, LTQ_FLASH_MAX); ++ ++static struct platform_device ltq_flash_nand = { ++ .name = "gen_nand", ++ .id = -1, ++ .num_resources = 1, ++ .resource = <q_nand_res, ++ .dev = { ++ .platform_data = &falcon_flash_nand_data, ++ }, ++}; ++ ++void __init ++falcon_register_nand(void) ++{ ++ platform_device_register(<q_flash_nand); ++} +--- /dev/null ++++ b/arch/mips/lantiq/falcon/devices.h +@@ -0,0 +1,18 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#ifndef _FALCON_DEVICES_H__ ++#define _FALCON_DEVICES_H__ ++ ++#include "../devices.h" ++ ++extern void falcon_register_nand(void); ++ ++#endif +--- /dev/null ++++ b/arch/mips/lantiq/falcon/prom.c +@@ -0,0 +1,72 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <lantiq_soc.h> ++ ++#include "devices.h" ++ ++#include "../prom.h" ++ ++#define SOC_FALCON "Falcon" ++ ++#define PART_SHIFT 12 ++#define PART_MASK 0x0FFFF000 ++#define REV_SHIFT 28 ++#define REV_MASK 0xF0000000 ++#define SREV_SHIFT 22 ++#define SREV_MASK 0x03C00000 ++ ++#define MUXC_SIF_RX_PIN 112 ++#define MUXC_SIF_TX_PIN 113 ++ ++/* this parameter allows us enable/disable asc1 via commandline */ ++static int register_asc1; ++static int __init ++ltq_parse_asc1(char *p) ++{ ++ register_asc1 = 1; ++ return 0; ++} ++__setup("use_asc1", ltq_parse_asc1); ++ ++void __init ++ltq_soc_setup(void) ++{ ++ ltq_register_asc(0); ++ ltq_register_wdt(); ++ falcon_register_gpio(); ++ if (register_asc1) { ++ ltq_register_asc(1); ++ if (ltq_gpio_request(MUXC_SIF_RX_PIN, 3, 0, "asc1-rx")) ++ pr_err("failed to request asc1-rx"); ++ if (ltq_gpio_request(MUXC_SIF_TX_PIN, 3, 1, "asc1-tx")) ++ pr_err("failed to request asc1-tx"); ++ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_ASC1_ACT); ++ } ++} ++ ++void __init ++ltq_soc_detect(struct ltq_soc_info *i) ++{ ++ i->partnum = (ltq_r32(LTQ_FALCON_CHIPID) & PART_MASK) >> PART_SHIFT; ++ i->rev = (ltq_r32(LTQ_FALCON_CHIPID) & REV_MASK) >> REV_SHIFT; ++ i->srev = (ltq_r32(LTQ_FALCON_CHIPCONF) & SREV_MASK) >> SREV_SHIFT; ++ sprintf(i->rev_type, "%c%d%d", (i->srev & 0x4) ? ('B') : ('A'), ++ i->rev & 0x7, i->srev & 0x3); ++ switch (i->partnum) { ++ case SOC_ID_FALCON: ++ i->name = SOC_FALCON; ++ i->type = SOC_TYPE_FALCON; ++ break; ++ ++ default: ++ unreachable(); ++ break; ++ } ++} +--- /dev/null ++++ b/arch/mips/lantiq/falcon/reset.c +@@ -0,0 +1,87 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/init.h> ++#include <linux/io.h> ++#include <linux/pm.h> ++#include <asm/reboot.h> ++#include <linux/module.h> ++ ++#include <lantiq_soc.h> ++ ++/* CPU0 Reset Source Register */ ++#define LTQ_SYS1_CPU0RS 0x0040 ++/* reset cause mask */ ++#define LTQ_CPU0RS_MASK 0x0003 ++ ++int ++ltq_reset_cause(void) ++{ ++ return ltq_sys1_r32(LTQ_SYS1_CPU0RS) & LTQ_CPU0RS_MASK; ++} ++EXPORT_SYMBOL_GPL(ltq_reset_cause); ++ ++#define BOOT_REG_BASE (KSEG1 | 0x1F200000) ++#define BOOT_PW1_REG (BOOT_REG_BASE | 0x20) ++#define BOOT_PW2_REG (BOOT_REG_BASE | 0x24) ++#define BOOT_PW1 0x4C545100 ++#define BOOT_PW2 0x0051544C ++ ++#define WDT_REG_BASE (KSEG1 | 0x1F8803F0) ++#define WDT_PW1 0x00BE0000 ++#define WDT_PW2 0x00DC0000 ++ ++static void ++ltq_machine_restart(char *command) ++{ ++ pr_notice("System restart\n"); ++ local_irq_disable(); ++ ++ /* reboot magic */ ++ ltq_w32(BOOT_PW1, (void *)BOOT_PW1_REG); /* 'LTQ\0' */ ++ ltq_w32(BOOT_PW2, (void *)BOOT_PW2_REG); /* '\0QTL' */ ++ ltq_w32(0, (void *)BOOT_REG_BASE); /* reset Bootreg RVEC */ ++ ++ /* watchdog magic */ ++ ltq_w32(WDT_PW1, (void *)WDT_REG_BASE); ++ ltq_w32(WDT_PW2 | ++ (0x3 << 26) | /* PWL */ ++ (0x2 << 24) | /* CLKDIV */ ++ (0x1 << 31) | /* enable */ ++ (1), /* reload */ ++ (void *)WDT_REG_BASE); ++ unreachable(); ++} ++ ++static void ++ltq_machine_halt(void) ++{ ++ pr_notice("System halted.\n"); ++ local_irq_disable(); ++ unreachable(); ++} ++ ++static void ++ltq_machine_power_off(void) ++{ ++ pr_notice("Please turn off the power now.\n"); ++ local_irq_disable(); ++ unreachable(); ++} ++ ++static int __init ++mips_reboot_setup(void) ++{ ++ _machine_restart = ltq_machine_restart; ++ _machine_halt = ltq_machine_halt; ++ pm_power_off = ltq_machine_power_off; ++ return 0; ++} ++ ++arch_initcall(mips_reboot_setup); +--- /dev/null ++++ b/arch/mips/lantiq/falcon/sysctrl.c +@@ -0,0 +1,181 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/ioport.h> ++#include <asm/delay.h> ++ ++#include <lantiq_soc.h> ++ ++#include "devices.h" ++ ++/* infrastructure control register */ ++#define SYS1_INFRAC 0x00bc ++/* Configuration fuses for drivers and pll */ ++#define STATUS_CONFIG 0x0040 ++ ++/* GPE frequency selection */ ++#define GPPC_OFFSET 24 ++#define GPEFREQ_MASK 0x00000C0 ++#define GPEFREQ_OFFSET 10 ++/* Clock status register */ ++#define LTQ_SYSCTL_CLKS 0x0000 ++/* Clock enable register */ ++#define LTQ_SYSCTL_CLKEN 0x0004 ++/* Clock clear register */ ++#define LTQ_SYSCTL_CLKCLR 0x0008 ++/* Activation Status Register */ ++#define LTQ_SYSCTL_ACTS 0x0020 ++/* Activation Register */ ++#define LTQ_SYSCTL_ACT 0x0024 ++/* Deactivation Register */ ++#define LTQ_SYSCTL_DEACT 0x0028 ++/* reboot Register */ ++#define LTQ_SYSCTL_RBT 0x002c ++ ++static struct resource ltq_sysctl_res[] = { ++ MEM_RES("sys1", LTQ_SYS1_BASE_ADDR, LTQ_SYS1_SIZE), ++ MEM_RES("syseth", LTQ_SYS_ETH_BASE_ADDR, LTQ_SYS_ETH_SIZE), ++ MEM_RES("sysgpe", LTQ_SYS_GPE_BASE_ADDR, LTQ_SYS_GPE_SIZE), ++}; ++ ++static struct resource ltq_status_res = ++ MEM_RES("status", LTQ_STATUS_BASE_ADDR, LTQ_STATUS_SIZE); ++static struct resource ltq_ebu_res = ++ MEM_RES("ebu", LTQ_EBU_BASE_ADDR, LTQ_EBU_SIZE); ++ ++static void __iomem *ltq_sysctl[3]; ++static void __iomem *ltq_status_membase; ++void __iomem *ltq_sys1_membase; ++void __iomem *ltq_ebu_membase; ++ ++#define ltq_reg_w32(m, x, y) ltq_w32((x), ltq_sysctl[m] + (y)) ++#define ltq_reg_r32(m, x) ltq_r32(ltq_sysctl[m] + (x)) ++#define ltq_reg_w32_mask(m, clear, set, reg) \ ++ ltq_reg_w32(m, (ltq_reg_r32(m, reg) & ~(clear)) | (set), reg) ++ ++#define ltq_status_w32(x, y) ltq_w32((x), ltq_status_membase + (y)) ++#define ltq_status_r32(x) ltq_r32(ltq_status_membase + (x)) ++ ++static inline void ++ltq_sysctl_wait(int module, unsigned int mask, unsigned int test) ++{ ++ int err = 1000000; ++ ++ do {} while (--err && ((ltq_reg_r32(module, LTQ_SYSCTL_ACTS) ++ & mask) != test)); ++ if (!err) ++ pr_err("module de/activation failed %d %08X %08X\n", ++ module, mask, test); ++} ++ ++void ++ltq_sysctl_activate(int module, unsigned int mask) ++{ ++ if (module > SYSCTL_SYSGPE) ++ return; ++ ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_ACT); ++ ltq_sysctl_wait(module, mask, mask); ++} ++EXPORT_SYMBOL(ltq_sysctl_activate); ++ ++void ++ltq_sysctl_deactivate(int module, unsigned int mask) ++{ ++ if (module > SYSCTL_SYSGPE) ++ return; ++ ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_DEACT); ++ ltq_sysctl_wait(module, mask, 0); ++} ++EXPORT_SYMBOL(ltq_sysctl_deactivate); ++ ++void ++ltq_sysctl_clken(int module, unsigned int mask) ++{ ++ if (module > SYSCTL_SYSGPE) ++ return; ++ ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKEN); ++ ltq_sysctl_wait(module, mask, mask); ++} ++EXPORT_SYMBOL(ltq_sysctl_clken); ++ ++void ++ltq_sysctl_clkdis(int module, unsigned int mask) ++{ ++ if (module > SYSCTL_SYSGPE) ++ return; ++ ++ ltq_reg_w32(module, mask, LTQ_SYSCTL_CLKCLR); ++ ltq_sysctl_wait(module, mask, 0); ++} ++EXPORT_SYMBOL(ltq_sysctl_clkdis); ++ ++void ++ltq_sysctl_reboot(int module, unsigned int mask) ++{ ++ unsigned int act; ++ ++ if (module > SYSCTL_SYSGPE) ++ return; ++ ++ act = ltq_reg_r32(module, LTQ_SYSCTL_ACT); ++ if ((~act & mask) != 0) ++ ltq_sysctl_activate(module, ~act & mask); ++ ltq_reg_w32(module, act & mask, LTQ_SYSCTL_RBT); ++ ltq_sysctl_wait(module, mask, mask); ++} ++EXPORT_SYMBOL(ltq_sysctl_reboot); ++ ++/* enable the ONU core */ ++static void ++ltq_gpe_enable(void) ++{ ++ unsigned int freq; ++ unsigned int status; ++ ++ /* if if the clock is already enabled */ ++ status = ltq_reg_r32(SYSCTL_SYS1, SYS1_INFRAC); ++ if (status & (1 << (GPPC_OFFSET + 1))) ++ return; ++ ++ if (ltq_status_r32(STATUS_CONFIG) == 0) ++ freq = 1; /* use 625MHz on unfused chip */ ++ else ++ freq = (ltq_status_r32(STATUS_CONFIG) & ++ GPEFREQ_MASK) >> ++ GPEFREQ_OFFSET; ++ ++ /* apply new frequency */ ++ ltq_reg_w32_mask(SYSCTL_SYS1, 7 << (GPPC_OFFSET + 1), ++ freq << (GPPC_OFFSET + 2) , SYS1_INFRAC); ++ udelay(1); ++ ++ /* enable new frequency */ ++ ltq_reg_w32_mask(SYSCTL_SYS1, 0, 1 << (GPPC_OFFSET + 1), SYS1_INFRAC); ++ udelay(1); ++} ++ ++void __init ++ltq_soc_init(void) ++{ ++ int i; ++ ++ for (i = 0; i < 3; i++) ++ ltq_sysctl[i] = ltq_remap_resource(<q_sysctl_res[i]); ++ ++ ltq_sys1_membase = ltq_sysctl[0]; ++ ltq_status_membase = ltq_remap_resource(<q_status_res); ++ ltq_ebu_membase = ltq_remap_resource(<q_ebu_res); ++ ++ ltq_gpe_enable(); ++} diff --git a/target/linux/lantiq/patches/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch b/target/linux/lantiq/patches/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch new file mode 100644 index 0000000000..2f747d93d2 --- /dev/null +++ b/target/linux/lantiq/patches/0007-MIPS-lantiq-add-support-for-FALC-ON-GPIOs.patch @@ -0,0 +1,489 @@ +From 02d9df56be1ba23c7bec51c94e5d2ac0d13d2d78 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 11 Aug 2011 14:35:02 +0200 +Subject: [PATCH 07/24] MIPS: lantiq: add support for FALC-ON GPIOs + +FALC-ON uses a different GPIO core than the other Lantiq SoCs. This patch adds +the new driver. + +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + arch/mips/lantiq/falcon/Makefile | 2 +- + arch/mips/lantiq/falcon/devices.c | 41 ++++ + arch/mips/lantiq/falcon/devices.h | 2 + + arch/mips/lantiq/falcon/gpio.c | 398 +++++++++++++++++++++++++++++++++++++ + 4 files changed, 442 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/lantiq/falcon/gpio.c + +--- a/arch/mips/lantiq/falcon/Makefile ++++ b/arch/mips/lantiq/falcon/Makefile +@@ -1 +1 @@ +-obj-y := clk.o prom.o reset.o sysctrl.o devices.o ++obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o +--- a/arch/mips/lantiq/falcon/devices.c ++++ b/arch/mips/lantiq/falcon/devices.c +@@ -9,6 +9,7 @@ + + #include <linux/platform_device.h> + #include <linux/mtd/nand.h> ++#include <linux/gpio.h> + + #include <lantiq_soc.h> + +@@ -85,3 +86,43 @@ falcon_register_nand(void) + { + platform_device_register(<q_flash_nand); + } ++ ++/* gpio */ ++#define DECLARE_GPIO_RES(port) \ ++static struct resource falcon_gpio ## port ## _res[] = { \ ++ MEM_RES("gpio"#port, LTQ_GPIO ## port ## _BASE_ADDR, \ ++ LTQ_GPIO ## port ## _SIZE), \ ++ MEM_RES("padctrl"#port, LTQ_PADCTRL ## port ## _BASE_ADDR, \ ++ LTQ_PADCTRL ## port ## _SIZE), \ ++ IRQ_RES("gpio_mux"#port, FALCON_IRQ_GPIO_P ## port) \ ++} ++DECLARE_GPIO_RES(0); ++DECLARE_GPIO_RES(1); ++DECLARE_GPIO_RES(2); ++DECLARE_GPIO_RES(3); ++DECLARE_GPIO_RES(4); ++ ++void __init ++falcon_register_gpio(void) ++{ ++ platform_device_register_simple("falcon_gpio", 0, ++ falcon_gpio0_res, ARRAY_SIZE(falcon_gpio0_res)); ++ platform_device_register_simple("falcon_gpio", 1, ++ falcon_gpio1_res, ARRAY_SIZE(falcon_gpio1_res)); ++ platform_device_register_simple("falcon_gpio", 2, ++ falcon_gpio2_res, ARRAY_SIZE(falcon_gpio2_res)); ++ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_PADCTRL1 | ACTS_P1); ++ ltq_sysctl_activate(SYSCTL_SYSETH, ACTS_PADCTRL0 | ++ ACTS_PADCTRL2 | ACTS_P0 | ACTS_P2); ++} ++ ++void __init ++falcon_register_gpio_extra(void) ++{ ++ platform_device_register_simple("falcon_gpio", 3, ++ falcon_gpio3_res, ARRAY_SIZE(falcon_gpio3_res)); ++ platform_device_register_simple("falcon_gpio", 4, ++ falcon_gpio4_res, ARRAY_SIZE(falcon_gpio4_res)); ++ ltq_sysctl_activate(SYSCTL_SYS1, ++ ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); ++} +--- a/arch/mips/lantiq/falcon/devices.h ++++ b/arch/mips/lantiq/falcon/devices.h +@@ -14,5 +14,7 @@ + #include "../devices.h" + + extern void falcon_register_nand(void); ++extern void falcon_register_gpio(void); ++extern void falcon_register_gpio_extra(void); + + #endif +--- /dev/null ++++ b/arch/mips/lantiq/falcon/gpio.c +@@ -0,0 +1,398 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/gpio.h> ++#include <linux/interrupt.h> ++#include <linux/slab.h> ++#include <linux/platform_device.h> ++ ++#include <lantiq_soc.h> ++ ++/* Multiplexer Control Register */ ++#define LTQ_PADC_MUX(x) (x * 0x4) ++/* Pad Control Availability Register */ ++#define LTQ_PADC_AVAIL 0x000000F0 ++ ++/* Data Output Register */ ++#define LTQ_GPIO_OUT 0x00000000 ++/* Data Input Register */ ++#define LTQ_GPIO_IN 0x00000004 ++/* Direction Register */ ++#define LTQ_GPIO_DIR 0x00000008 ++/* External Interrupt Control Register 0 */ ++#define LTQ_GPIO_EXINTCR0 0x00000018 ++/* External Interrupt Control Register 1 */ ++#define LTQ_GPIO_EXINTCR1 0x0000001C ++/* IRN Capture Register */ ++#define LTQ_GPIO_IRNCR 0x00000020 ++/* IRN Interrupt Configuration Register */ ++#define LTQ_GPIO_IRNCFG 0x0000002C ++/* IRN Interrupt Enable Set Register */ ++#define LTQ_GPIO_IRNRNSET 0x00000030 ++/* IRN Interrupt Enable Clear Register */ ++#define LTQ_GPIO_IRNENCLR 0x00000034 ++/* Output Set Register */ ++#define LTQ_GPIO_OUTSET 0x00000040 ++/* Output Cler Register */ ++#define LTQ_GPIO_OUTCLR 0x00000044 ++/* Direction Clear Register */ ++#define LTQ_GPIO_DIRSET 0x00000048 ++/* Direction Set Register */ ++#define LTQ_GPIO_DIRCLR 0x0000004C ++ ++/* turn a gpio_chip into a falcon_gpio_port */ ++#define ctop(c) container_of(c, struct falcon_gpio_port, gpio_chip) ++/* turn a irq_data into a falcon_gpio_port */ ++#define itop(i) ((struct falcon_gpio_port *) irq_get_chip_data(i->irq)) ++ ++#define ltq_pad_r32(p, reg) ltq_r32(p->pad + reg) ++#define ltq_pad_w32(p, val, reg) ltq_w32(val, p->pad + reg) ++#define ltq_pad_w32_mask(c, clear, set, reg) \ ++ ltq_pad_w32(c, (ltq_pad_r32(c, reg) & ~(clear)) | (set), reg) ++ ++#define ltq_port_r32(p, reg) ltq_r32(p->port + reg) ++#define ltq_port_w32(p, val, reg) ltq_w32(val, p->port + reg) ++#define ltq_port_w32_mask(p, clear, set, reg) \ ++ ltq_port_w32(p, (ltq_port_r32(p, reg) & ~(clear)) | (set), reg) ++ ++#define MAX_PORTS 5 ++#define PINS_PER_PORT 32 ++ ++struct falcon_gpio_port { ++ struct gpio_chip gpio_chip; ++ void __iomem *pad; ++ void __iomem *port; ++ unsigned int irq_base; ++ unsigned int chained_irq; ++}; ++ ++static struct falcon_gpio_port ltq_gpio_port[MAX_PORTS]; ++ ++int gpio_to_irq(unsigned int gpio) ++{ ++ return __gpio_to_irq(gpio); ++} ++EXPORT_SYMBOL(gpio_to_irq); ++ ++int ltq_gpio_mux_set(unsigned int pin, unsigned int mux) ++{ ++ int port = pin / 100; ++ int offset = pin % 100; ++ struct falcon_gpio_port *gpio_port; ++ ++ if ((offset >= PINS_PER_PORT) || (port >= MAX_PORTS)) ++ return -EINVAL; ++ ++ gpio_port = <q_gpio_port[port]; ++ ltq_pad_w32(gpio_port, mux & 0x3, LTQ_PADC_MUX(offset)); ++ ++ return 0; ++} ++EXPORT_SYMBOL(ltq_gpio_mux_set); ++ ++int ltq_gpio_request(unsigned int pin, unsigned int val, ++ unsigned int dir, const char *name) ++{ ++ int port = pin / 100; ++ int offset = pin % 100; ++ ++ if (offset >= PINS_PER_PORT || port >= MAX_PORTS) ++ return -EINVAL; ++ ++ if (gpio_request(pin, name)) { ++ pr_err("failed to setup lantiq gpio: %s\n", name); ++ return -EBUSY; ++ } ++ ++ if (dir) ++ gpio_direction_output(pin, 1); ++ else ++ gpio_direction_input(pin); ++ ++ return ltq_gpio_mux_set(pin, val); ++} ++EXPORT_SYMBOL(ltq_gpio_request); ++ ++static int ++falcon_gpio_direction_input(struct gpio_chip *chip, unsigned int offset) ++{ ++ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRCLR); ++ ++ return 0; ++} ++ ++static void ++falcon_gpio_set(struct gpio_chip *chip, unsigned int offset, int value) ++{ ++ if (value) ++ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTSET); ++ else ++ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_OUTCLR); ++} ++ ++static int ++falcon_gpio_direction_output(struct gpio_chip *chip, ++ unsigned int offset, int value) ++{ ++ falcon_gpio_set(chip, offset, value); ++ ltq_port_w32(ctop(chip), 1 << offset, LTQ_GPIO_DIRSET); ++ ++ return 0; ++} ++ ++static int ++falcon_gpio_get(struct gpio_chip *chip, unsigned int offset) ++{ ++ if ((ltq_port_r32(ctop(chip), LTQ_GPIO_DIR) >> offset) & 1) ++ return (ltq_port_r32(ctop(chip), LTQ_GPIO_OUT) >> offset) & 1; ++ else ++ return (ltq_port_r32(ctop(chip), LTQ_GPIO_IN) >> offset) & 1; ++} ++ ++static int ++falcon_gpio_request(struct gpio_chip *chip, unsigned offset) ++{ ++ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { ++ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) ++ return -EBUSY; ++ /* switch on gpio function */ ++ ltq_pad_w32(ctop(chip), 1, LTQ_PADC_MUX(offset)); ++ return 0; ++ } ++ ++ return -ENODEV; ++} ++ ++static void ++falcon_gpio_free(struct gpio_chip *chip, unsigned offset) ++{ ++ if ((ltq_pad_r32(ctop(chip), LTQ_PADC_AVAIL) >> offset) & 1) { ++ if (ltq_pad_r32(ctop(chip), LTQ_PADC_MUX(offset)) > 1) ++ return; ++ /* switch off gpio function */ ++ ltq_pad_w32(ctop(chip), 0, LTQ_PADC_MUX(offset)); ++ } ++} ++ ++static int ++falcon_gpio_to_irq(struct gpio_chip *chip, unsigned offset) ++{ ++ return ctop(chip)->irq_base + offset; ++} ++ ++static void ++falcon_gpio_disable_irq(struct irq_data *d) ++{ ++ unsigned int offset = d->irq - itop(d)->irq_base; ++ ++ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); ++} ++ ++static void ++falcon_gpio_enable_irq(struct irq_data *d) ++{ ++ unsigned int offset = d->irq - itop(d)->irq_base; ++ ++ if (!ltq_pad_r32(itop(d), LTQ_PADC_MUX(offset)) < 1) ++ /* switch on gpio function */ ++ ltq_pad_w32(itop(d), 1, LTQ_PADC_MUX(offset)); ++ ++ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNRNSET); ++} ++ ++static void ++falcon_gpio_ack_irq(struct irq_data *d) ++{ ++ unsigned int offset = d->irq - itop(d)->irq_base; ++ ++ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); ++} ++ ++static void ++falcon_gpio_mask_and_ack_irq(struct irq_data *d) ++{ ++ unsigned int offset = d->irq - itop(d)->irq_base; ++ ++ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNENCLR); ++ ltq_port_w32(itop(d), 1 << offset, LTQ_GPIO_IRNCR); ++} ++ ++static struct irq_chip falcon_gpio_irq_chip; ++static int ++falcon_gpio_irq_type(struct irq_data *d, unsigned int type) ++{ ++ unsigned int offset = d->irq - itop(d)->irq_base; ++ unsigned int mask = 1 << offset; ++ ++ if ((type & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_NONE) ++ return 0; ++ ++ if ((type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) != 0) { ++ /* level triggered */ ++ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_IRNCFG); ++ irq_set_chip_and_handler_name(d->irq, ++ &falcon_gpio_irq_chip, handle_level_irq, "mux"); ++ } else { ++ /* edge triggered */ ++ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_IRNCFG); ++ irq_set_chip_and_handler_name(d->irq, ++ &falcon_gpio_irq_chip, handle_simple_irq, "mux"); ++ } ++ ++ if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) { ++ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); ++ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR1); ++ } else { ++ if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) != 0) ++ /* positive logic: rising edge, high level */ ++ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR0); ++ else ++ /* negative logic: falling edge, low level */ ++ ltq_port_w32_mask(itop(d), 0, mask, LTQ_GPIO_EXINTCR0); ++ ltq_port_w32_mask(itop(d), mask, 0, LTQ_GPIO_EXINTCR1); ++ } ++ ++ return gpio_direction_input(itop(d)->gpio_chip.base + offset); ++} ++ ++static void ++falcon_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) ++{ ++ struct falcon_gpio_port *gpio_port = irq_desc_get_handler_data(desc); ++ unsigned long irncr; ++ int offset; ++ ++ /* acknowledge interrupt */ ++ irncr = ltq_port_r32(gpio_port, LTQ_GPIO_IRNCR); ++ ltq_port_w32(gpio_port, irncr, LTQ_GPIO_IRNCR); ++ ++ desc->irq_data.chip->irq_ack(&desc->irq_data); ++ ++ for_each_set_bit(offset, &irncr, gpio_port->gpio_chip.ngpio) ++ generic_handle_irq(gpio_port->irq_base + offset); ++} ++ ++static struct irq_chip falcon_gpio_irq_chip = { ++ .name = "gpio_irq_mux", ++ .irq_mask = falcon_gpio_disable_irq, ++ .irq_unmask = falcon_gpio_enable_irq, ++ .irq_ack = falcon_gpio_ack_irq, ++ .irq_mask_ack = falcon_gpio_mask_and_ack_irq, ++ .irq_set_type = falcon_gpio_irq_type, ++}; ++ ++static struct irqaction gpio_cascade = { ++ .handler = no_action, ++ .flags = IRQF_DISABLED, ++ .name = "gpio_cascade", ++}; ++ ++static int ++falcon_gpio_probe(struct platform_device *pdev) ++{ ++ struct falcon_gpio_port *gpio_port; ++ int ret, i; ++ struct resource *gpiores, *padres; ++ int irq; ++ ++ if (pdev->id >= MAX_PORTS) ++ return -ENODEV; ++ ++ gpiores = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ padres = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ irq = platform_get_irq(pdev, 0); ++ if (!gpiores || !padres) ++ return -ENODEV; ++ ++ gpio_port = <q_gpio_port[pdev->id]; ++ gpio_port->gpio_chip.label = "falcon-gpio"; ++ gpio_port->gpio_chip.direction_input = falcon_gpio_direction_input; ++ gpio_port->gpio_chip.direction_output = falcon_gpio_direction_output; ++ gpio_port->gpio_chip.get = falcon_gpio_get; ++ gpio_port->gpio_chip.set = falcon_gpio_set; ++ gpio_port->gpio_chip.request = falcon_gpio_request; ++ gpio_port->gpio_chip.free = falcon_gpio_free; ++ gpio_port->gpio_chip.base = 100 * pdev->id; ++ gpio_port->gpio_chip.ngpio = 32; ++ gpio_port->gpio_chip.dev = &pdev->dev; ++ ++ gpio_port->port = ltq_remap_resource(gpiores); ++ gpio_port->pad = ltq_remap_resource(padres); ++ ++ if (!gpio_port->port || !gpio_port->pad) { ++ dev_err(&pdev->dev, "Could not map io ranges\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ if (irq > 0) { ++ /* irq_chip support */ ++ gpio_port->gpio_chip.to_irq = falcon_gpio_to_irq; ++ gpio_port->irq_base = INT_NUM_EXTRA_START + (32 * pdev->id); ++ ++ for (i = 0; i < 32; i++) { ++ irq_set_chip_and_handler_name(gpio_port->irq_base + i, ++ &falcon_gpio_irq_chip, handle_simple_irq, ++ "mux"); ++ irq_set_chip_data(gpio_port->irq_base + i, gpio_port); ++ /* set to negative logic (falling edge, low level) */ ++ ltq_port_w32_mask(gpio_port, 0, 1 << i, ++ LTQ_GPIO_EXINTCR0); ++ } ++ ++ gpio_port->chained_irq = irq; ++ setup_irq(irq, &gpio_cascade); ++ irq_set_handler_data(irq, gpio_port); ++ irq_set_chained_handler(irq, falcon_gpio_irq_handler); ++ } ++ ++ ret = gpiochip_add(&gpio_port->gpio_chip); ++ if (ret < 0) { ++ dev_err(&pdev->dev, "Could not register gpiochip %d, %d\n", ++ pdev->id, ret); ++ goto err; ++ } ++ platform_set_drvdata(pdev, gpio_port); ++ return ret; ++ ++err: ++ dev_err(&pdev->dev, "Error in gpio_probe %d, %d\n", pdev->id, ret); ++ if (gpiores) ++ release_resource(gpiores); ++ if (padres) ++ release_resource(padres); ++ ++ if (gpio_port->port) ++ iounmap(gpio_port->port); ++ if (gpio_port->pad) ++ iounmap(gpio_port->pad); ++ return ret; ++} ++ ++static struct platform_driver falcon_gpio_driver = { ++ .probe = falcon_gpio_probe, ++ .driver = { ++ .name = "falcon_gpio", ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++int __init ++falcon_gpio_init(void) ++{ ++ int ret; ++ ++ pr_info("FALC(tm) ON GPIO Driver, (C) 2011 Lantiq Deutschland Gmbh\n"); ++ ret = platform_driver_register(&falcon_gpio_driver); ++ if (ret) ++ pr_err("falcon_gpio: Error registering platform driver!"); ++ return ret; ++} ++ ++postcore_initcall(falcon_gpio_init); diff --git a/target/linux/lantiq/patches/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch b/target/linux/lantiq/patches/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch new file mode 100644 index 0000000000..10c73f5498 --- /dev/null +++ b/target/linux/lantiq/patches/0008-MIPS-lantiq-add-support-for-the-EASY98000-evaluation.patch @@ -0,0 +1,166 @@ +From ec6ba0f79c010a878d679c057fb6306b50a201b0 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 11 Aug 2011 14:09:35 +0200 +Subject: [PATCH 08/24] MIPS: lantiq: add support for the EASY98000 evaluation + board + +This patch adds the machine code for the EASY9800 evaluation board. + +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + arch/mips/lantiq/falcon/Kconfig | 11 +++ + arch/mips/lantiq/falcon/Makefile | 1 + + arch/mips/lantiq/falcon/mach-easy98000.c | 110 ++++++++++++++++++++++++++++++ + arch/mips/lantiq/machtypes.h | 5 ++ + 4 files changed, 127 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/lantiq/falcon/Kconfig + create mode 100644 arch/mips/lantiq/falcon/mach-easy98000.c + +--- /dev/null ++++ b/arch/mips/lantiq/falcon/Kconfig +@@ -0,0 +1,11 @@ ++if SOC_FALCON ++ ++menu "MIPS Machine" ++ ++config LANTIQ_MACH_EASY98000 ++ bool "Easy98000" ++ default y ++ ++endmenu ++ ++endif +--- a/arch/mips/lantiq/falcon/Makefile ++++ b/arch/mips/lantiq/falcon/Makefile +@@ -1 +1,2 @@ + obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o +--- /dev/null ++++ b/arch/mips/lantiq/falcon/mach-easy98000.c +@@ -0,0 +1,110 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> ++ * Copyright (C) 2011 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/platform_device.h> ++#include <linux/mtd/partitions.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/spi_gpio.h> ++#include <linux/spi/eeprom.h> ++ ++#include "../machtypes.h" ++ ++#include "devices.h" ++ ++static struct mtd_partition easy98000_nor_partitions[] = { ++ { ++ .name = "uboot", ++ .offset = 0x0, ++ .size = 0x40000, ++ }, ++ { ++ .name = "uboot_env", ++ .offset = 0x40000, ++ .size = 0x40000, /* 2 sectors for redundant env. */ ++ }, ++ { ++ .name = "linux", ++ .offset = 0x80000, ++ .size = 0xF80000, /* map only 16 MiB */ ++ }, ++}; ++ ++struct physmap_flash_data easy98000_nor_flash_data = { ++ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), ++ .parts = easy98000_nor_partitions, ++}; ++ ++/* setup gpio based spi bus/device for access to the eeprom on the board */ ++#define SPI_GPIO_MRST 102 ++#define SPI_GPIO_MTSR 103 ++#define SPI_GPIO_CLK 104 ++#define SPI_GPIO_CS0 105 ++#define SPI_GPIO_CS1 106 ++#define SPI_GPIO_BUS_NUM 1 ++ ++static struct spi_gpio_platform_data easy98000_spi_gpio_data = { ++ .sck = SPI_GPIO_CLK, ++ .mosi = SPI_GPIO_MTSR, ++ .miso = SPI_GPIO_MRST, ++ .num_chipselect = 2, ++}; ++ ++static struct platform_device easy98000_spi_gpio_device = { ++ .name = "spi_gpio", ++ .id = SPI_GPIO_BUS_NUM, ++ .dev.platform_data = &easy98000_spi_gpio_data, ++}; ++ ++static struct spi_eeprom at25160n = { ++ .byte_len = 16 * 1024 / 8, ++ .name = "at25160n", ++ .page_size = 32, ++ .flags = EE_ADDR2, ++}; ++ ++static struct spi_board_info easy98000_spi_gpio_devices __initdata = { ++ .modalias = "at25", ++ .bus_num = SPI_GPIO_BUS_NUM, ++ .max_speed_hz = 1000 * 1000, ++ .mode = SPI_MODE_3, ++ .chip_select = 1, ++ .controller_data = (void *) SPI_GPIO_CS1, ++ .platform_data = &at25160n, ++}; ++ ++static void __init ++easy98000_init_common(void) ++{ ++ spi_register_board_info(&easy98000_spi_gpio_devices, 1); ++ platform_device_register(&easy98000_spi_gpio_device); ++} ++ ++static void __init ++easy98000_init(void) ++{ ++ easy98000_init_common(); ++ ltq_register_nor(&easy98000_nor_flash_data); ++} ++ ++static void __init ++easy98000nand_init(void) ++{ ++ easy98000_init_common(); ++ falcon_register_nand(); ++} ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY98000, ++ "EASY98000", ++ "EASY98000 Eval Board", ++ easy98000_init); ++ ++MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, ++ "EASY98000NAND", ++ "EASY98000 Eval Board (NAND Flash)", ++ easy98000nand_init); +--- a/arch/mips/lantiq/machtypes.h ++++ b/arch/mips/lantiq/machtypes.h +@@ -15,6 +15,11 @@ enum lantiq_mach_type { + LTQ_MACH_GENERIC = 0, + LTQ_MACH_EASY50712, /* Danube evaluation board */ + LTQ_MACH_EASY50601, /* Amazon SE evaluation board */ ++ ++ /* FALCON */ ++ LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ ++ LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ ++ LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ + }; + + #endif diff --git a/target/linux/lantiq/patches/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch b/target/linux/lantiq/patches/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch new file mode 100644 index 0000000000..1d42341b3b --- /dev/null +++ b/target/linux/lantiq/patches/0009-MIPS-make-oprofile-use-cp0_perfcount_irq-if-it-is-se.patch @@ -0,0 +1,51 @@ +From 88bb1794592e3fe9c8d65ce73ee851e11dbbd26b Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Wed, 24 Aug 2011 13:24:11 +0200 +Subject: [PATCH 09/24] MIPS: make oprofile use cp0_perfcount_irq if it is set + +The patch makes the oprofile code use the performance counters irq. + +This patch is written by Felix Fietkau. + +Signed-off-by: Felix Fietkau <nbd@openwrt.org> +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + arch/mips/oprofile/op_model_mipsxx.c | 12 ++++++++++++ + 1 files changed, 12 insertions(+), 0 deletions(-) + +--- a/arch/mips/oprofile/op_model_mipsxx.c ++++ b/arch/mips/oprofile/op_model_mipsxx.c +@@ -303,6 +303,11 @@ static irqreturn_t mipsxx_perfcount_int( + return mipsxx_perfcount_handler(); + } + ++static irqreturn_t mipsxx_perfcount_int(int irq, void *dev_id) ++{ ++ return mipsxx_perfcount_handler(); ++} ++ + static int __init mipsxx_init(void) + { + int counters; +@@ -383,6 +388,10 @@ static int __init mipsxx_init(void) + return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, + IRQF_SHARED, "Perfcounter", save_perf_irq); + ++ if (cp0_perfcount_irq >= 0) ++ return request_irq(cp0_perfcount_irq, mipsxx_perfcount_int, ++ IRQF_SHARED, "Perfcounter", save_perf_irq); ++ + return 0; + } + +@@ -392,6 +401,9 @@ static void mipsxx_exit(void) + + if (cp0_perfcount_irq >= 0) + free_irq(cp0_perfcount_irq, save_perf_irq); ++ ++ if (cp0_perfcount_irq >= 0) ++ free_irq(cp0_perfcount_irq, save_perf_irq); + + counters = counters_per_cpu_to_total(counters); + on_each_cpu(reset_counters, (void *)(long)counters, 1); diff --git a/target/linux/lantiq/patches/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch b/target/linux/lantiq/patches/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch new file mode 100644 index 0000000000..d05178861f --- /dev/null +++ b/target/linux/lantiq/patches/0010-MIPS-enable-oprofile-support-on-lantiq-targets.patch @@ -0,0 +1,45 @@ +From cc4b9cdff8665a414ae51101d3a0ca6ed7444a27 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Wed, 24 Aug 2011 13:28:55 +0200 +Subject: [PATCH 10/24] MIPS: enable oprofile support on lantiq targets + +This patch sets the performance counters irq and HAVE_OPROFILE flag. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Cc: linux-mips@linux-mips.org +--- + arch/mips/Kconfig | 1 + + arch/mips/lantiq/irq.c | 5 +++++ + 2 files changed, 6 insertions(+), 0 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -230,6 +230,7 @@ config LANTIQ + select SWAP_IO_SPACE + select BOOT_RAW + select HAVE_CLK ++ select HAVE_OPROFILE + select MIPS_MACHINE + + config LASAT +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -40,6 +40,9 @@ + + #define MAX_EIU 6 + ++/* the performance counter */ ++#define LTQ_PERF_IRQ (INT_NUM_IM4_IRL0 + 31) ++ + /* irqs generated by device attached to the EBU need to be acked in + * a special manner + */ +@@ -318,6 +321,8 @@ void __init arch_init_irq(void) + set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ0 | IE_IRQ1 | + IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5); + #endif ++ ++ cp0_perfcount_irq = LTQ_PERF_IRQ; + } + + unsigned int __cpuinit get_c0_compare_int(void) diff --git a/target/linux/lantiq/patches/0011-MIPS-lantiq-adds-falcon-I2C.patch b/target/linux/lantiq/patches/0011-MIPS-lantiq-adds-falcon-I2C.patch new file mode 100644 index 0000000000..eceb1e4f2e --- /dev/null +++ b/target/linux/lantiq/patches/0011-MIPS-lantiq-adds-falcon-I2C.patch @@ -0,0 +1,890 @@ +From 6437f41dfdf9475178e22ab0dd886af033f90cc2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 21:10:16 +0200 +Subject: [PATCH 11/24] MIPS: lantiq: adds falcon I2C + +--- + arch/mips/lantiq/falcon/devices.c | 21 + + arch/mips/lantiq/falcon/devices.h | 1 + + drivers/i2c/busses/Kconfig | 4 + + drivers/i2c/busses/Makefile | 1 + + drivers/i2c/busses/i2c-falcon.c | 815 +++++++++++++++++++++++++++++++++++++ + 5 files changed, 842 insertions(+), 0 deletions(-) + create mode 100644 drivers/i2c/busses/i2c-falcon.c + +--- a/arch/mips/lantiq/falcon/devices.c ++++ b/arch/mips/lantiq/falcon/devices.c +@@ -126,3 +126,24 @@ falcon_register_gpio_extra(void) + ltq_sysctl_activate(SYSCTL_SYS1, + ACTS_PADCTRL3 | ACTS_PADCTRL4 | ACTS_P3 | ACTS_P4); + } ++ ++/* i2c */ ++static struct resource falcon_i2c_resources[] = { ++ MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END), ++ IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ), ++ IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ), ++ IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR), ++ IRQ_RES("i2c_p", FALCON_IRQ_I2C_I2C_P), ++}; ++ ++void __init falcon_register_i2c(void) ++{ ++ platform_device_register_simple("i2c-falcon", 0, ++ falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); ++ sys1_hw_activate(ACTS_I2C_ACT); ++} ++ ++void __init falcon_register_crypto(void) ++{ ++ platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0); ++} +--- a/arch/mips/lantiq/falcon/devices.h ++++ b/arch/mips/lantiq/falcon/devices.h +@@ -16,5 +16,6 @@ + extern void falcon_register_nand(void); + extern void falcon_register_gpio(void); + extern void falcon_register_gpio_extra(void); ++extern void falcon_register_i2c(void); + + #endif +--- a/drivers/i2c/busses/Kconfig ++++ b/drivers/i2c/busses/Kconfig +@@ -284,6 +284,10 @@ config I2C_POWERMAC + + comment "I2C system bus drivers (mostly embedded / system-on-chip)" + ++config I2C_FALCON ++ tristate "Falcon I2C interface" ++# depends on SOC_FALCON ++ + config I2C_AT91 + tristate "Atmel AT91 I2C Two-Wire interface (TWI)" + depends on ARCH_AT91 && EXPERIMENTAL && BROKEN +--- a/drivers/i2c/busses/Makefile ++++ b/drivers/i2c/busses/Makefile +@@ -82,5 +82,6 @@ obj-$(CONFIG_I2C_SIBYTE) += i2c-sibyte.o + obj-$(CONFIG_I2C_STUB) += i2c-stub.o + obj-$(CONFIG_SCx200_ACB) += scx200_acb.o + obj-$(CONFIG_SCx200_I2C) += scx200_i2c.o ++obj-$(CONFIG_I2C_FALCON) += i2c-falcon.o + + ccflags-$(CONFIG_I2C_DEBUG_BUS) := -DDEBUG +--- /dev/null ++++ b/drivers/i2c/busses/i2c-falcon.c +@@ -0,0 +1,815 @@ ++/* ++ * Lantiq FALC(tm) ON - I2C bus adapter ++ * ++ * Parts based on i2c-designware.c and other i2c drivers from Linux 2.6.33 ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. ++ */ ++ ++/* #define DEBUG */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/delay.h> ++#include <linux/slab.h> /* for kzalloc, kfree */ ++#include <linux/i2c.h> ++#include <linux/clk.h> ++#include <linux/errno.h> ++#include <linux/sched.h> ++#include <linux/err.h> ++#include <linux/interrupt.h> ++#include <linux/platform_device.h> ++#include <linux/io.h> ++#include <linux/gpio.h> ++ ++#include <falcon/lantiq_soc.h> ++ ++/* CURRENT ISSUES: ++ * - no high speed support ++ * - supports only master mode ++ * - ten bit mode is not tested (no slave devices) ++ */ ++ ++/* mapping for access macros */ ++#define reg_r32(reg) __raw_readl(reg) ++#define reg_w32(val, reg) __raw_writel(val, reg) ++#define reg_w32_mask(clear, set, reg) \ ++ reg_w32((reg_r32(reg) & ~(clear)) | (set), reg) ++#define reg_r32_table(reg, idx) reg_r32(&((uint32_t *)®)[idx]) ++#define reg_w32_table(val, reg, idx) reg_w32(val, &((uint32_t *)®)[idx]) ++#define i2c (priv->membase) ++#include <falcon/i2c_reg.h> ++ ++#define DRV_NAME "i2c-falcon" ++#define DRV_VERSION "1.01" ++ ++#define FALCON_I2C_BUSY_TIMEOUT 20 /* ms */ ++ ++#ifdef DEBUG ++#define FALCON_I2C_XFER_TIMEOUT 25*HZ ++#else ++#define FALCON_I2C_XFER_TIMEOUT HZ ++#endif ++#if defined(DEBUG) && 0 ++#define PRINTK(arg...) printk(arg) ++#else ++#define PRINTK(arg...) do {} while (0) ++#endif ++ ++#define FALCON_I2C_IMSC_DEFAULT_MASK (I2C_IMSC_I2C_P_INT_EN | \ ++ I2C_IMSC_I2C_ERR_INT_EN) ++ ++#define FALCON_I2C_ARB_LOST (1 << 0) ++#define FALCON_I2C_NACK (1 << 1) ++#define FALCON_I2C_RX_UFL (1 << 2) ++#define FALCON_I2C_RX_OFL (1 << 3) ++#define FALCON_I2C_TX_UFL (1 << 4) ++#define FALCON_I2C_TX_OFL (1 << 5) ++ ++struct falcon_i2c { ++ struct mutex mutex; ++ ++ enum { ++ FALCON_I2C_MODE_100 = 1, ++ FALCON_I2C_MODE_400 = 2, ++ FALCON_I2C_MODE_3400 = 3 ++ } mode; /* current speed mode */ ++ ++ struct clk *clk; /* clock input for i2c hardware block */ ++ struct gpon_reg_i2c __iomem *membase; /* base of mapped registers */ ++ int irq_lb, irq_b, irq_err, irq_p; /* last burst, burst, error, ++ protocol IRQs */ ++ ++ struct i2c_adapter adap; ++ struct device *dev; ++ ++ struct completion cmd_complete; ++ ++ /* message transfer data */ ++ /* current message */ ++ struct i2c_msg *current_msg; ++ /* number of messages to handle */ ++ int msgs_num; ++ /* current buffer */ ++ u8 *msg_buf; ++ /* remaining length of current buffer */ ++ u32 msg_buf_len; ++ /* error status of the current transfer */ ++ int msg_err; ++ ++ /* master status codes */ ++ enum { ++ STATUS_IDLE, ++ STATUS_ADDR, /* address phase */ ++ STATUS_WRITE, ++ STATUS_READ, ++ STATUS_READ_END, ++ STATUS_STOP ++ } status; ++}; ++ ++static irqreturn_t falcon_i2c_isr(int irq, void *dev_id); ++ ++static inline void enable_burst_irq(struct falcon_i2c *priv) ++{ ++ i2c_w32_mask(0, I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, imsc); ++} ++static inline void disable_burst_irq(struct falcon_i2c *priv) ++{ ++ i2c_w32_mask(I2C_IMSC_LBREQ_INT_EN | I2C_IMSC_BREQ_INT_EN, 0, imsc); ++} ++ ++static void prepare_msg_send_addr(struct falcon_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int rd = !!(msg->flags & I2C_M_RD); /* extends to 0 or 1 */ ++ u16 addr = msg->addr; ++ ++ /* new i2c_msg */ ++ priv->msg_buf = msg->buf; ++ priv->msg_buf_len = msg->len; ++ if (rd) ++ priv->status = STATUS_READ; ++ else ++ priv->status = STATUS_WRITE; ++ ++ /* send slave address */ ++ if (msg->flags & I2C_M_TEN) { ++ i2c_w32(0xf0 | ((addr & 0x300) >> 7) | rd, txd); ++ i2c_w32(addr & 0xff, txd); ++ } else ++ i2c_w32((addr & 0x7f) << 1 | rd, txd); ++} ++ ++static void set_tx_len(struct falcon_i2c *priv) ++{ ++ struct i2c_msg *msg = priv->current_msg; ++ int len = (msg->flags & I2C_M_TEN) ? 2 : 1; ++ ++ PRINTK("set_tx_len %cX\n", (msg->flags & I2C_M_RD)?'R':'T'); ++ ++ priv->status = STATUS_ADDR; ++ ++ if (!(msg->flags & I2C_M_RD)) { ++ len += msg->len; ++ } else { ++ /* set maximum received packet size (before rx int!) */ ++ i2c_w32(msg->len, mrps_ctrl); ++ } ++ i2c_w32(len, tps_ctrl); ++ enable_burst_irq(priv); ++} ++ ++static int falcon_i2c_hw_init(struct i2c_adapter *adap) ++{ ++ struct falcon_i2c *priv = i2c_get_adapdata(adap); ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++#ifndef DEBUG ++ /* set normal operation clock divider */ ++ i2c_w32(1 << I2C_CLC_RMC_OFFSET, clc); ++#else ++ /* for debugging a higher divider value! */ ++ i2c_w32(0xF0 << I2C_CLC_RMC_OFFSET, clc); ++#endif ++ ++ /* set frequency */ ++ if (priv->mode == FALCON_I2C_MODE_100) { ++ dev_dbg(priv->dev, "set standard mode (100 kHz)\n"); ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | ++ (499 << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ } else if (priv->mode == FALCON_I2C_MODE_400) { ++ dev_dbg(priv->dev, "set fast mode (400 kHz)\n"); ++ i2c_w32(0, fdiv_high_cfg); ++ i2c_w32((1 << I2C_FDIV_CFG_INC_OFFSET) | ++ (124 << I2C_FDIV_CFG_DEC_OFFSET), ++ fdiv_cfg); ++ } else if (priv->mode == FALCON_I2C_MODE_3400) { ++ dev_dbg(priv->dev, "set high mode (3.4 MHz)\n"); ++ i2c_w32(0, fdiv_cfg); ++ /* TODO recalculate value for 100MHz input */ ++ i2c_w32((41 << I2C_FDIV_HIGH_CFG_INC_OFFSET) | ++ (152 << I2C_FDIV_HIGH_CFG_DEC_OFFSET), ++ fdiv_high_cfg); ++ } else { ++ dev_warn(priv->dev, "unknown mode\n"); ++ return -ENODEV; ++ } ++ ++ /* configure fifo */ ++ i2c_w32(I2C_FIFO_CFG_TXFC | /* tx fifo as flow controller */ ++ I2C_FIFO_CFG_RXFC | /* rx fifo as flow controller */ ++ I2C_FIFO_CFG_TXFA_TXFA2 | /* tx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_RXFA_RXFA2 | /* rx fifo 4-byte aligned */ ++ I2C_FIFO_CFG_TXBS_TXBS0 | /* tx fifo burst size is 1 word */ ++ I2C_FIFO_CFG_RXBS_RXBS0, /* rx fifo burst size is 1 word */ ++ fifo_cfg); ++ ++ /* configure address */ ++ i2c_w32(I2C_ADDR_CFG_SOPE_EN | /* generate stop when no more data in the ++ fifo */ ++ I2C_ADDR_CFG_SONA_EN | /* generate stop when NA received */ ++ I2C_ADDR_CFG_MnS_EN | /* we are master device */ ++ 0, /* our slave address (not used!) */ ++ addr_cfg); ++ ++ /* enable bus */ ++ i2c_w32_mask(0, I2C_RUN_CTRL_RUN_EN, run_ctrl); ++ ++ return 0; ++} ++ ++static int falcon_i2c_wait_bus_not_busy(struct falcon_i2c *priv) ++{ ++ int timeout = FALCON_I2C_BUSY_TIMEOUT; ++ ++ while ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) ++ != I2C_BUS_STAT_BS_FREE) { ++ if (timeout <= 0) { ++ dev_warn(priv->dev, "timeout waiting for bus ready\n"); ++ return -ETIMEDOUT; ++ } ++ timeout--; ++ mdelay(1); ++ } ++ ++ return 0; ++} ++ ++static void falcon_i2c_tx(struct falcon_i2c *priv, int last) ++{ ++ if (priv->msg_buf_len && priv->msg_buf) { ++ i2c_w32(*priv->msg_buf, txd); ++ ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else ++ priv->msg_buf = NULL; ++ } else ++ last = 1; ++ ++ if (last) { ++ disable_burst_irq(priv); ++ } ++} ++ ++static void falcon_i2c_rx(struct falcon_i2c *priv, int last) ++{ ++ u32 fifo_stat,timeout; ++ if (priv->msg_buf_len && priv->msg_buf) { ++ timeout = 5000000; ++ do { ++ fifo_stat = i2c_r32(ffs_stat); ++ } while (!fifo_stat && --timeout); ++ if (!timeout) { ++ last = 1; ++ PRINTK("\nrx timeout\n"); ++ goto err; ++ } ++ while (fifo_stat) { ++ *priv->msg_buf = i2c_r32(rxd); ++ if (--priv->msg_buf_len) ++ priv->msg_buf++; ++ else { ++ priv->msg_buf = NULL; ++ last = 1; ++ break; ++ } ++ #if 0 ++ fifo_stat = i2c_r32(ffs_stat); ++ #else ++ /* do not read more than burst size, otherwise no "last ++ burst" is generated and the transaction is blocked! */ ++ fifo_stat = 0; ++ #endif ++ } ++ } else { ++ last = 1; ++ } ++err: ++ if (last) { ++ disable_burst_irq(priv); ++ ++ if (priv->status == STATUS_READ_END) { ++ /* do the STATUS_STOP and complete() here, as sometimes ++ the tx_end is already seen before this is finished */ ++ priv->status = STATUS_STOP; ++ complete(&priv->cmd_complete); ++ } else { ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++ priv->status = STATUS_READ_END; ++ } ++ } ++} ++ ++static void falcon_i2c_xfer_init(struct falcon_i2c *priv) ++{ ++ /* enable interrupts */ ++ i2c_w32(FALCON_I2C_IMSC_DEFAULT_MASK, imsc); ++ ++ /* trigger transfer of first msg */ ++ set_tx_len(priv); ++} ++ ++static void dump_msgs(struct i2c_msg msgs[], int num, int rx) ++{ ++#if defined(DEBUG) ++ int i, j; ++ printk("Messages %d %s\n", num, rx ? "out" : "in"); ++ for (i = 0; i < num; i++) { ++ printk("%2d %cX Msg(%d) addr=0x%X: ", i, ++ (msgs[i].flags & I2C_M_RD)?'R':'T', ++ msgs[i].len, msgs[i].addr); ++ if (!(msgs[i].flags & I2C_M_RD) || rx) { ++ for (j = 0; j < msgs[i].len; j++) ++ printk("%02X ", msgs[i].buf[j]); ++ } ++ printk("\n"); ++ } ++#endif ++} ++ ++static void falcon_i2c_release_bus(struct falcon_i2c *priv) ++{ ++ if ((i2c_r32(bus_stat) & I2C_BUS_STAT_BS_MASK) == I2C_BUS_STAT_BS_BM) ++ i2c_w32(I2C_ENDD_CTRL_SETEND, endd_ctrl); ++} ++ ++static int falcon_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], ++ int num) ++{ ++ struct falcon_i2c *priv = i2c_get_adapdata(adap); ++ int ret; ++ ++ dev_dbg(priv->dev, "xfer %u messages\n", num); ++ dump_msgs(msgs, num, 0); ++ ++ mutex_lock(&priv->mutex); ++ ++ INIT_COMPLETION(priv->cmd_complete); ++ priv->current_msg = msgs; ++ priv->msgs_num = num; ++ priv->msg_err = 0; ++ priv->status = STATUS_IDLE; ++ ++ /* wait for the bus to become ready */ ++ ret = falcon_i2c_wait_bus_not_busy(priv); ++ if (ret) ++ goto done; ++ ++ while (priv->msgs_num) { ++ /* start the transfers */ ++ falcon_i2c_xfer_init(priv); ++ ++ /* wait for transfers to complete */ ++ ret = wait_for_completion_interruptible_timeout( ++ &priv->cmd_complete, FALCON_I2C_XFER_TIMEOUT); ++ if (ret == 0) { ++ dev_err(priv->dev, "controller timed out\n"); ++ falcon_i2c_hw_init(adap); ++ ret = -ETIMEDOUT; ++ goto done; ++ } else if (ret < 0) ++ goto done; ++ ++ if (priv->msg_err) { ++ if (priv->msg_err & FALCON_I2C_NACK) ++ ret = -ENXIO; ++ else ++ ret = -EREMOTEIO; ++ goto done; ++ } ++ if (--priv->msgs_num) { ++ priv->current_msg++; ++ } ++ } ++ /* no error? */ ++ ret = num; ++ ++done: ++ falcon_i2c_release_bus(priv); ++ ++ mutex_unlock(&priv->mutex); ++ ++ if (ret>=0) ++ dump_msgs(msgs, num, 1); ++ ++ PRINTK("XFER ret %d\n", ret); ++ return ret; ++} ++ ++static irqreturn_t falcon_i2c_isr_burst(int irq, void *dev_id) ++{ ++ struct falcon_i2c *priv = dev_id; ++ struct i2c_msg *msg = priv->current_msg; ++ int last = (irq == priv->irq_lb); ++ ++ if (last) ++ PRINTK("LB "); ++ else ++ PRINTK("B "); ++ ++ if (msg->flags & I2C_M_RD) { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ PRINTK("X"); ++ prepare_msg_send_addr(priv); ++ disable_burst_irq(priv); ++ break; ++ case STATUS_READ: ++ case STATUS_READ_END: ++ PRINTK("R"); ++ falcon_i2c_rx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ printk("Status R %d\n", priv->status); ++ break; ++ } ++ } else { ++ switch (priv->status) { ++ case STATUS_ADDR: ++ PRINTK("x"); ++ prepare_msg_send_addr(priv); ++ break; ++ case STATUS_WRITE: ++ PRINTK("w"); ++ falcon_i2c_tx(priv, last); ++ break; ++ default: ++ disable_burst_irq(priv); ++ printk("Status W %d\n", priv->status); ++ break; ++ } ++ } ++ ++ i2c_w32(I2C_ICR_BREQ_INT_CLR | I2C_ICR_LBREQ_INT_CLR, icr); ++ return IRQ_HANDLED; ++} ++ ++static void falcon_i2c_isr_prot(struct falcon_i2c *priv) ++{ ++ u32 i_pro = i2c_r32(p_irqss); ++ ++ PRINTK("i2c-p"); ++ ++ /* not acknowledge */ ++ if (i_pro & I2C_P_IRQSS_NACK) { ++ priv->msg_err |= FALCON_I2C_NACK; ++ PRINTK(" nack"); ++ } ++ ++ /* arbitration lost */ ++ if (i_pro & I2C_P_IRQSS_AL) { ++ priv->msg_err |= FALCON_I2C_ARB_LOST; ++ PRINTK(" arb-lost"); ++ } ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) ++ PRINTK(" rx"); ++ ++ /* tx end */ ++ if (i_pro & I2C_P_IRQSS_TX_END) ++ PRINTK(" txend"); ++ PRINTK("\n"); ++ ++ if (!priv->msg_err) { ++ /* tx -> rx switch */ ++ if (i_pro & I2C_P_IRQSS_RX) { ++ priv->status = STATUS_READ; ++ enable_burst_irq(priv); ++ } ++ if (i_pro & I2C_P_IRQSS_TX_END) { ++ if (priv->status == STATUS_READ) ++ priv->status = STATUS_READ_END; ++ else { ++ disable_burst_irq(priv); ++ priv->status = STATUS_STOP; ++ } ++ } ++ } ++ ++ i2c_w32(i_pro, p_irqsc); ++} ++ ++static irqreturn_t falcon_i2c_isr(int irq, void *dev_id) ++{ ++ u32 i_raw, i_err=0; ++ struct falcon_i2c *priv = dev_id; ++ ++ i_raw = i2c_r32(mis); ++ PRINTK("i_raw 0x%08X\n", i_raw); ++ ++ /* error interrupt */ ++ if (i_raw & I2C_RIS_I2C_ERR_INT_INTOCC) { ++ i_err = i2c_r32(err_irqss); ++ PRINTK("i_err 0x%08X bus_stat 0x%04X\n", ++ i_err, i2c_r32(bus_stat)); ++ ++ /* tx fifo overflow (8) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_OFL) ++ priv->msg_err |= FALCON_I2C_TX_OFL; ++ ++ /* tx fifo underflow (4) */ ++ if (i_err & I2C_ERR_IRQSS_TXF_UFL) ++ priv->msg_err |= FALCON_I2C_TX_UFL; ++ ++ /* rx fifo overflow (2) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_OFL) ++ priv->msg_err |= FALCON_I2C_RX_OFL; ++ ++ /* rx fifo underflow (1) */ ++ if (i_err & I2C_ERR_IRQSS_RXF_UFL) ++ priv->msg_err |= FALCON_I2C_RX_UFL; ++ ++ i2c_w32(i_err, err_irqsc); ++ } ++ ++ /* protocol interrupt */ ++ if (i_raw & I2C_RIS_I2C_P_INT_INTOCC) ++ falcon_i2c_isr_prot(priv); ++ ++ if ((priv->msg_err) || (priv->status == STATUS_STOP)) ++ complete(&priv->cmd_complete); ++ ++ return IRQ_HANDLED; ++} ++ ++static u32 falcon_i2c_functionality(struct i2c_adapter *adap) ++{ ++ return I2C_FUNC_I2C | ++ I2C_FUNC_10BIT_ADDR | ++ I2C_FUNC_SMBUS_EMUL; ++} ++ ++static struct i2c_algorithm falcon_i2c_algorithm = { ++ .master_xfer = falcon_i2c_xfer, ++ .functionality = falcon_i2c_functionality, ++}; ++ ++static int __devinit falcon_i2c_probe(struct platform_device *pdev) ++{ ++ int ret = 0; ++ struct falcon_i2c *priv; ++ struct i2c_adapter *adap; ++ struct resource *mmres, *ioarea, ++ *irqres_lb, *irqres_b, *irqres_err, *irqres_p; ++ struct clk *clk; ++ ++ dev_dbg(&pdev->dev, "probing\n"); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ irqres_lb = platform_get_resource_byname(pdev, IORESOURCE_IRQ, ++ "i2c_lb"); ++ irqres_b = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_b"); ++ irqres_err = platform_get_resource_byname(pdev, IORESOURCE_IRQ, ++ "i2c_err"); ++ irqres_p = platform_get_resource_byname(pdev, IORESOURCE_IRQ, "i2c_p"); ++ ++ if (!mmres || !irqres_lb || !irqres_b || !irqres_err || !irqres_p) { ++ dev_err(&pdev->dev, "no resources\n"); ++ return -ENODEV; ++ } ++ ++ clk = clk_get(&pdev->dev, "fpi"); ++ if (IS_ERR(clk)) { ++ dev_err(&pdev->dev, "failed to get fpi clk\n"); ++ return -ENOENT; ++ } ++ ++ if (clk_get_rate(clk) != 100000000) { ++ dev_err(&pdev->dev, "input clock is not 100MHz\n"); ++ return -ENOENT; ++ } ++ ++ /* allocate private data */ ++ priv = kzalloc(sizeof(*priv), GFP_KERNEL); ++ if (!priv) { ++ dev_err(&pdev->dev, "can't allocate private data\n"); ++ return -ENOMEM; ++ } ++ ++ adap = &priv->adap; ++ i2c_set_adapdata(adap, priv); ++ adap->owner = THIS_MODULE; ++ adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; ++ strlcpy(adap->name, DRV_NAME "-adapter", sizeof(adap->name)); ++ adap->algo = &falcon_i2c_algorithm; ++ ++ priv->mode = FALCON_I2C_MODE_100; ++ priv->clk = clk; ++ priv->dev = &pdev->dev; ++ ++ init_completion(&priv->cmd_complete); ++ mutex_init(&priv->mutex); ++ ++ ret = ltq_gpio_request(107, 0, 0, 0, DRV_NAME":sda"); ++ if (ret) { ++ dev_err(&pdev->dev, "I2C gpio 107 (sda) not available\n"); ++ ret = -ENXIO; ++ goto err_free_priv; ++ } ++ ret = ltq_gpio_request(108, 0, 0, 0, DRV_NAME":scl"); ++ if (ret) { ++ gpio_free(107); ++ dev_err(&pdev->dev, "I2C gpio 108 (scl) not available\n"); ++ ret = -ENXIO; ++ goto err_free_priv; ++ } ++ ++ ioarea = request_mem_region(mmres->start, resource_size(mmres), ++ pdev->name); ++ ++ if (ioarea == NULL) { ++ dev_err(&pdev->dev, "I2C region already claimed\n"); ++ ret = -ENXIO; ++ goto err_free_gpio; ++ } ++ ++ /* map memory */ ++ priv->membase = ioremap_nocache(mmres->start & ~KSEG1, ++ resource_size(mmres)); ++ if (priv->membase == NULL) { ++ ret = -ENOMEM; ++ goto err_release_region; ++ } ++ ++ priv->irq_lb = irqres_lb->start; ++ ret = request_irq(priv->irq_lb, falcon_i2c_isr_burst, IRQF_DISABLED, ++ irqres_lb->name, priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get last burst IRQ %d\n", irqres_lb->start); ++ ret = -ENODEV; ++ goto err_unmap_mem; ++ } ++ ++ priv->irq_b = irqres_b->start; ++ ret = request_irq(priv->irq_b, falcon_i2c_isr_burst, IRQF_DISABLED, ++ irqres_b->name, priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get burst IRQ %d\n", irqres_b->start); ++ ret = -ENODEV; ++ goto err_free_lb_irq; ++ } ++ ++ priv->irq_err = irqres_err->start; ++ ret = request_irq(priv->irq_err, falcon_i2c_isr, IRQF_DISABLED, ++ irqres_err->name, priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get error IRQ %d\n", irqres_err->start); ++ ret = -ENODEV; ++ goto err_free_b_irq; ++ } ++ ++ priv->irq_p = irqres_p->start; ++ ret = request_irq(priv->irq_p, falcon_i2c_isr, IRQF_DISABLED, ++ irqres_p->name, priv); ++ if (ret) { ++ dev_err(&pdev->dev, "can't get protocol IRQ %d\n", irqres_p->start); ++ ret = -ENODEV; ++ goto err_free_err_irq; ++ } ++ ++ dev_dbg(&pdev->dev, "mapped io-space to %p\n", priv->membase); ++ dev_dbg(&pdev->dev, "use IRQs %d, %d, %d, %d\n", irqres_lb->start, ++ irqres_b->start, irqres_err->start, irqres_p->start); ++ ++ /* add our adapter to the i2c stack */ ++ ret = i2c_add_numbered_adapter(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't register I2C adapter\n"); ++ goto err_free_p_irq; ++ } ++ ++ platform_set_drvdata(pdev, priv); ++ i2c_set_adapdata(adap, priv); ++ ++ /* print module version information */ ++ dev_dbg(&pdev->dev, "module id=%u revision=%u\n", ++ (i2c_r32(id) & I2C_ID_ID_MASK) >> I2C_ID_ID_OFFSET, ++ (i2c_r32(id) & I2C_ID_REV_MASK) >> I2C_ID_REV_OFFSET); ++ ++ /* initialize HW */ ++ ret = falcon_i2c_hw_init(adap); ++ if (ret) { ++ dev_err(&pdev->dev, "can't configure adapter\n"); ++ goto err_remove_adapter; ++ } ++ ++ dev_info(&pdev->dev, "version %s\n", DRV_VERSION); ++ ++ return 0; ++ ++err_remove_adapter: ++ i2c_del_adapter(adap); ++ platform_set_drvdata(pdev, NULL); ++ ++err_free_p_irq: ++ free_irq(priv->irq_p, priv); ++ ++err_free_err_irq: ++ free_irq(priv->irq_err, priv); ++ ++err_free_b_irq: ++ free_irq(priv->irq_b, priv); ++ ++err_free_lb_irq: ++ free_irq(priv->irq_lb, priv); ++ ++err_unmap_mem: ++ iounmap(priv->membase); ++ ++err_release_region: ++ release_mem_region(mmres->start, resource_size(mmres)); ++ ++err_free_gpio: ++ gpio_free(108); ++ gpio_free(107); ++ ++err_free_priv: ++ kfree(priv); ++ ++ return ret; ++} ++ ++static int __devexit falcon_i2c_remove(struct platform_device *pdev) ++{ ++ struct falcon_i2c *priv = platform_get_drvdata(pdev); ++ struct resource *mmres; ++ ++ /* disable bus */ ++ i2c_w32_mask(I2C_RUN_CTRL_RUN_EN, 0, run_ctrl); ++ ++ /* remove driver */ ++ platform_set_drvdata(pdev, NULL); ++ i2c_del_adapter(&priv->adap); ++ ++ free_irq(priv->irq_lb, priv); ++ free_irq(priv->irq_b, priv); ++ free_irq(priv->irq_err, priv); ++ free_irq(priv->irq_p, priv); ++ ++ iounmap(priv->membase); ++ ++ gpio_free(108); ++ gpio_free(107); ++ ++ kfree(priv); ++ ++ mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ release_mem_region(mmres->start, resource_size(mmres)); ++ ++ dev_dbg(&pdev->dev, "removed\n"); ++ ++ return 0; ++} ++ ++static struct platform_driver falcon_i2c_driver = { ++ .probe = falcon_i2c_probe, ++ .remove = __devexit_p(falcon_i2c_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE, ++ }, ++}; ++ ++static int __init falcon_i2c_init(void) ++{ ++ int ret; ++ ++ ret = platform_driver_register(&falcon_i2c_driver); ++ ++ if (ret) ++ pr_debug(DRV_NAME ": can't register platform driver\n"); ++ ++ return ret; ++} ++ ++static void __exit falcon_i2c_exit(void) ++{ ++ platform_driver_unregister(&falcon_i2c_driver); ++} ++ ++module_init(falcon_i2c_init); ++module_exit(falcon_i2c_exit); ++ ++MODULE_DESCRIPTION("Lantiq FALC(tm) ON - I2C bus adapter"); ++MODULE_ALIAS("platform:" DRV_NAME); ++MODULE_LICENSE("GPL"); ++MODULE_VERSION(DRV_VERSION); diff --git a/target/linux/lantiq/patches/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch b/target/linux/lantiq/patches/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch new file mode 100644 index 0000000000..079e401f7c --- /dev/null +++ b/target/linux/lantiq/patches/0013-MIPS-lantiq-adds-FALC-ON-spi-driver.patch @@ -0,0 +1,645 @@ +From 2bd534c30688bcb3f70f1816fbcff813fc746103 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 27 Aug 2011 18:12:26 +0200 +Subject: [PATCH 13/24] MIPS: lantiq: adds FALC-ON spi driver + +The external bus unit (EBU) found on the FALC-ON SoC has spi emulation that is +designed for serial flash access. + +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/lantiq/falcon/devices.c | 12 +- + arch/mips/lantiq/falcon/devices.h | 4 + + arch/mips/lantiq/falcon/mach-easy98000.c | 27 ++ + drivers/spi/Kconfig | 4 + + drivers/spi/Makefile | 1 + + drivers/spi/spi-falcon.c | 477 ++++++++++++++++++++++++++++++ + 6 files changed, 523 insertions(+), 2 deletions(-) + create mode 100644 drivers/spi/spi-falcon.c + +--- a/arch/mips/lantiq/falcon/devices.c ++++ b/arch/mips/lantiq/falcon/devices.c +@@ -129,7 +129,7 @@ falcon_register_gpio_extra(void) + + /* i2c */ + static struct resource falcon_i2c_resources[] = { +- MEM_RES("i2c", GPON_I2C_BASE,GPON_I2C_END), ++ MEM_RES("i2c", LTQ_I2C_BASE_ADDR, LTQ_I2C_SIZE), + IRQ_RES("i2c_lb", FALCON_IRQ_I2C_LBREQ), + IRQ_RES("i2c_b", FALCON_IRQ_I2C_BREQ), + IRQ_RES("i2c_err", FALCON_IRQ_I2C_I2C_ERR), +@@ -140,10 +140,18 @@ void __init falcon_register_i2c(void) + { + platform_device_register_simple("i2c-falcon", 0, + falcon_i2c_resources, ARRAY_SIZE(falcon_i2c_resources)); +- sys1_hw_activate(ACTS_I2C_ACT); ++ ltq_sysctl_activate(SYSCTL_SYS1, ACTS_I2C_ACT); + } + +-void __init falcon_register_crypto(void) ++/* spi flash */ ++static struct platform_device ltq_spi = { ++ .name = "falcon_spi", ++ .num_resources = 0, ++}; ++ ++void __init ++falcon_register_spi_flash(struct spi_board_info *data) + { +- platform_device_register_simple("ltq_falcon_deu", 0, NULL, 0); ++ spi_register_board_info(data, 1); ++ platform_device_register(<q_spi); + } +--- a/arch/mips/lantiq/falcon/devices.h ++++ b/arch/mips/lantiq/falcon/devices.h +@@ -11,11 +11,15 @@ + #ifndef _FALCON_DEVICES_H__ + #define _FALCON_DEVICES_H__ + ++#include <linux/spi/spi.h> ++#include <linux/spi/flash.h> ++ + #include "../devices.h" + + extern void falcon_register_nand(void); + extern void falcon_register_gpio(void); + extern void falcon_register_gpio_extra(void); + extern void falcon_register_i2c(void); ++extern void falcon_register_spi_flash(struct spi_board_info *data); + + #endif +--- a/arch/mips/lantiq/falcon/mach-easy98000.c ++++ b/arch/mips/lantiq/falcon/mach-easy98000.c +@@ -40,6 +40,21 @@ struct physmap_flash_data easy98000_nor_ + .parts = easy98000_nor_partitions, + }; + ++static struct flash_platform_data easy98000_spi_flash_platform_data = { ++ .name = "sflash", ++ .parts = easy98000_nor_partitions, ++ .nr_parts = ARRAY_SIZE(easy98000_nor_partitions) ++}; ++ ++static struct spi_board_info easy98000_spi_flash_data __initdata = { ++ .modalias = "m25p80", ++ .bus_num = 0, ++ .chip_select = 0, ++ .max_speed_hz = 10 * 1000 * 1000, ++ .mode = SPI_MODE_3, ++ .platform_data = &easy98000_spi_flash_platform_data ++}; ++ + /* setup gpio based spi bus/device for access to the eeprom on the board */ + #define SPI_GPIO_MRST 102 + #define SPI_GPIO_MTSR 103 +@@ -93,6 +108,13 @@ easy98000_init(void) + } + + static void __init ++easy98000sf_init(void) ++{ ++ easy98000_init_common(); ++ falcon_register_spi_flash(&easy98000_spi_flash_data); ++} ++ ++static void __init + easy98000nand_init(void) + { + easy98000_init_common(); +@@ -104,6 +126,11 @@ MIPS_MACHINE(LANTIQ_MACH_EASY98000, + "EASY98000 Eval Board", + easy98000_init); + ++MIPS_MACHINE(LANTIQ_MACH_EASY98000SF, ++ "EASY98000SF", ++ "EASY98000 Eval Board (Serial Flash)", ++ easy98000sf_init); ++ + MIPS_MACHINE(LANTIQ_MACH_EASY98000NAND, + "EASY98000NAND", + "EASY98000 Eval Board (NAND Flash)", +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -189,6 +189,10 @@ config SPI_MPC52xx + This drivers supports the MPC52xx SPI controller in master SPI + mode. + ++config SPI_FALCON ++ tristate "Falcon SPI controller support" ++ depends on SOC_FALCON ++ + config SPI_MPC52xx_PSC + tristate "Freescale MPC52xx PSC SPI controller" + depends on PPC_MPC52xx && EXPERIMENTAL +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -25,6 +25,7 @@ obj-$(CONFIG_SPI_DW_MMIO) += spi-dw-mmi + obj-$(CONFIG_SPI_DW_PCI) += spi-dw-midpci.o + spi-dw-midpci-objs := spi-dw-pci.o spi-dw-mid.o + obj-$(CONFIG_SPI_EP93XX) += spi-ep93xx.o ++obj-$(CONFIG_SPI_FALCON) += spi-falcon.o + obj-$(CONFIG_SPI_FSL_LIB) += spi-fsl-lib.o + obj-$(CONFIG_SPI_FSL_ESPI) += spi-fsl-espi.o + obj-$(CONFIG_SPI_FSL_SPI) += spi-fsl-spi.o +--- /dev/null ++++ b/drivers/spi/spi-falcon.c +@@ -0,0 +1,477 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 Thomas Langer <thomas.langer@lantiq.com> ++ */ ++ ++#include <linux/module.h> ++#include <linux/device.h> ++#include <linux/platform_device.h> ++#include <linux/spi/spi.h> ++#include <linux/delay.h> ++#include <linux/workqueue.h> ++ ++#include <lantiq_soc.h> ++ ++#define DRV_NAME "falcon_spi" ++ ++#define FALCON_SPI_XFER_BEGIN (1 << 0) ++#define FALCON_SPI_XFER_END (1 << 1) ++ ++/* Bus Read Configuration Register0 */ ++#define LTQ_BUSRCON0 0x00000010 ++/* Bus Write Configuration Register0 */ ++#define LTQ_BUSWCON0 0x00000018 ++/* Serial Flash Configuration Register */ ++#define LTQ_SFCON 0x00000080 ++/* Serial Flash Time Register */ ++#define LTQ_SFTIME 0x00000084 ++/* Serial Flash Status Register */ ++#define LTQ_SFSTAT 0x00000088 ++/* Serial Flash Command Register */ ++#define LTQ_SFCMD 0x0000008C ++/* Serial Flash Address Register */ ++#define LTQ_SFADDR 0x00000090 ++/* Serial Flash Data Register */ ++#define LTQ_SFDATA 0x00000094 ++/* Serial Flash I/O Control Register */ ++#define LTQ_SFIO 0x00000098 ++/* EBU Clock Control Register */ ++#define LTQ_EBUCC 0x000000C4 ++ ++/* Dummy Phase Length */ ++#define SFCMD_DUMLEN_OFFSET 16 ++#define SFCMD_DUMLEN_MASK 0x000F0000 ++/* Chip Select */ ++#define SFCMD_CS_OFFSET 24 ++#define SFCMD_CS_MASK 0x07000000 ++/* field offset */ ++#define SFCMD_ALEN_OFFSET 20 ++#define SFCMD_ALEN_MASK 0x00700000 ++/* SCK Rise-edge Position */ ++#define SFTIME_SCKR_POS_OFFSET 8 ++#define SFTIME_SCKR_POS_MASK 0x00000F00 ++/* SCK Period */ ++#define SFTIME_SCK_PER_OFFSET 0 ++#define SFTIME_SCK_PER_MASK 0x0000000F ++/* SCK Fall-edge Position */ ++#define SFTIME_SCKF_POS_OFFSET 12 ++#define SFTIME_SCKF_POS_MASK 0x0000F000 ++/* Device Size */ ++#define SFCON_DEV_SIZE_A23_0 0x03000000 ++#define SFCON_DEV_SIZE_MASK 0x0F000000 ++/* Read Data Position */ ++#define SFTIME_RD_POS_MASK 0x000F0000 ++/* Data Output */ ++#define SFIO_UNUSED_WD_MASK 0x0000000F ++/* Command Opcode mask */ ++#define SFCMD_OPC_MASK 0x000000FF ++/* dlen bytes of data to write */ ++#define SFCMD_DIR_WRITE 0x00000100 ++/* Data Length offset */ ++#define SFCMD_DLEN_OFFSET 9 ++/* Command Error */ ++#define SFSTAT_CMD_ERR 0x20000000 ++/* Access Command Pending */ ++#define SFSTAT_CMD_PEND 0x00400000 ++/* Frequency set to 100MHz. */ ++#define EBUCC_EBUDIV_SELF100 0x00000001 ++/* Serial Flash */ ++#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/* 8-bit multiplexed */ ++#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 ++/* Serial Flash */ ++#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/* Chip Select after opcode */ ++#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 ++ ++struct falcon_spi { ++ u32 sfcmd; /* for caching of opcode, direction, ... */ ++ struct spi_master *master; ++}; ++ ++int ++falcon_spi_xfer(struct spi_device *spi, ++ struct spi_transfer *t, ++ unsigned long flags) ++{ ++ struct device *dev = &spi->dev; ++ struct falcon_spi *priv = spi_master_get_devdata(spi->master); ++ const u8 *txp = t->tx_buf; ++ u8 *rxp = t->rx_buf; ++ unsigned int bytelen = ((8 * t->len + 7) / 8); ++ unsigned int len, alen, dumlen; ++ u32 val; ++ enum { ++ state_init, ++ state_command_prepare, ++ state_write, ++ state_read, ++ state_disable_cs, ++ state_end ++ } state = state_init; ++ ++ do { ++ switch (state) { ++ case state_init: /* detect phase of upper layer sequence */ ++ { ++ /* initial write ? */ ++ if (flags & FALCON_SPI_XFER_BEGIN) { ++ if (!txp) { ++ dev_err(dev, ++ "BEGIN without tx data!\n"); ++ return -1; ++ } ++ /* ++ * Prepare the parts of the sfcmd register, ++ * which should not ++ * change during a sequence! ++ * Only exception are the length fields, ++ * especially alen and dumlen. ++ */ ++ ++ priv->sfcmd = ((spi->chip_select ++ << SFCMD_CS_OFFSET) ++ & SFCMD_CS_MASK); ++ priv->sfcmd |= SFCMD_KEEP_CS_KEEP_SELECTED; ++ priv->sfcmd |= *txp; ++ txp++; ++ bytelen--; ++ if (bytelen) { ++ /* more data: ++ * maybe address and/or dummy */ ++ state = state_command_prepare; ++ break; ++ } else { ++ dev_dbg(dev, "write cmd %02X\n", ++ priv->sfcmd & SFCMD_OPC_MASK); ++ } ++ } ++ /* continued write ? */ ++ if (txp && bytelen) { ++ state = state_write; ++ break; ++ } ++ /* read data? */ ++ if (rxp && bytelen) { ++ state = state_read; ++ break; ++ } ++ /* end of sequence? */ ++ if (flags & FALCON_SPI_XFER_END) ++ state = state_disable_cs; ++ else ++ state = state_end; ++ break; ++ } ++ case state_command_prepare: /* collect tx data for ++ address and dummy phase */ ++ { ++ /* txp is valid, already checked */ ++ val = 0; ++ alen = 0; ++ dumlen = 0; ++ while (bytelen > 0) { ++ if (alen < 3) { ++ val = (val<<8)|(*txp++); ++ alen++; ++ } else if ((dumlen < 15) && (*txp == 0)) { ++ /* ++ * assume dummy bytes are set to 0 ++ * from upper layer ++ */ ++ dumlen++; ++ txp++; ++ } else ++ break; ++ bytelen--; ++ } ++ priv->sfcmd &= ~(SFCMD_ALEN_MASK | SFCMD_DUMLEN_MASK); ++ priv->sfcmd |= (alen << SFCMD_ALEN_OFFSET) | ++ (dumlen << SFCMD_DUMLEN_OFFSET); ++ if (alen > 0) ++ ltq_ebu_w32(val, LTQ_SFADDR); ++ ++ dev_dbg(dev, "write cmd %02X, alen=%d " ++ "(addr=%06X) dumlen=%d\n", ++ priv->sfcmd & SFCMD_OPC_MASK, ++ alen, val, dumlen); ++ ++ if (bytelen > 0) { ++ /* continue with write */ ++ state = state_write; ++ } else if (flags & FALCON_SPI_XFER_END) { ++ /* end of sequence? */ ++ state = state_disable_cs; ++ } else { ++ /* go to end and expect another ++ * call (read or write) */ ++ state = state_end; ++ } ++ break; ++ } ++ case state_write: ++ { ++ /* txp still valid */ ++ priv->sfcmd |= SFCMD_DIR_WRITE; ++ len = 0; ++ val = 0; ++ do { ++ if (bytelen--) ++ val |= (*txp++) << (8 * len++); ++ if ((flags & FALCON_SPI_XFER_END) ++ && (bytelen == 0)) { ++ priv->sfcmd &= ++ ~SFCMD_KEEP_CS_KEEP_SELECTED; ++ } ++ if ((len == 4) || (bytelen == 0)) { ++ ltq_ebu_w32(val, LTQ_SFDATA); ++ ltq_ebu_w32(priv->sfcmd ++ | (len<<SFCMD_DLEN_OFFSET), ++ LTQ_SFCMD); ++ len = 0; ++ val = 0; ++ priv->sfcmd &= ~(SFCMD_ALEN_MASK ++ | SFCMD_DUMLEN_MASK); ++ } ++ } while (bytelen); ++ state = state_end; ++ break; ++ } ++ case state_read: ++ { ++ /* read data */ ++ priv->sfcmd &= ~SFCMD_DIR_WRITE; ++ do { ++ if ((flags & FALCON_SPI_XFER_END) ++ && (bytelen <= 4)) { ++ priv->sfcmd &= ++ ~SFCMD_KEEP_CS_KEEP_SELECTED; ++ } ++ len = (bytelen > 4) ? 4 : bytelen; ++ bytelen -= len; ++ ltq_ebu_w32(priv->sfcmd ++ |(len<<SFCMD_DLEN_OFFSET), LTQ_SFCMD); ++ priv->sfcmd &= ~(SFCMD_ALEN_MASK ++ | SFCMD_DUMLEN_MASK); ++ do { ++ val = ltq_ebu_r32(LTQ_SFSTAT); ++ if (val & SFSTAT_CMD_ERR) { ++ /* reset error status */ ++ dev_err(dev, "SFSTAT: CMD_ERR " ++ "(%x)\n", val); ++ ltq_ebu_w32(SFSTAT_CMD_ERR, ++ LTQ_SFSTAT); ++ return -1; ++ } ++ } while (val & SFSTAT_CMD_PEND); ++ val = ltq_ebu_r32(LTQ_SFDATA); ++ do { ++ *rxp = (val & 0xFF); ++ rxp++; ++ val >>= 8; ++ len--; ++ } while (len); ++ } while (bytelen); ++ state = state_end; ++ break; ++ } ++ case state_disable_cs: ++ { ++ priv->sfcmd &= ~SFCMD_KEEP_CS_KEEP_SELECTED; ++ ltq_ebu_w32(priv->sfcmd | (0 << SFCMD_DLEN_OFFSET), ++ LTQ_SFCMD); ++ val = ltq_ebu_r32(LTQ_SFSTAT); ++ if (val & SFSTAT_CMD_ERR) { ++ /* reset error status */ ++ dev_err(dev, "SFSTAT: CMD_ERR (%x)\n", val); ++ ltq_ebu_w32(SFSTAT_CMD_ERR, LTQ_SFSTAT); ++ return -1; ++ } ++ state = state_end; ++ break; ++ } ++ case state_end: ++ break; ++ } ++ } while (state != state_end); ++ ++ return 0; ++} ++ ++static int ++falcon_spi_setup(struct spi_device *spi) ++{ ++ struct device *dev = &spi->dev; ++ const u32 ebuclk = CLOCK_100M; ++ unsigned int i; ++ unsigned long flags; ++ ++ dev_dbg(dev, "setup\n"); ++ ++ if (spi->master->bus_num > 0 || spi->chip_select > 0) ++ return -ENODEV; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ ++ if (ebuclk < spi->max_speed_hz) { ++ /* set EBU clock to 100 MHz */ ++ ltq_sys1_w32_mask(0, EBUCC_EBUDIV_SELF100, LTQ_EBUCC); ++ i = 1; /* divider */ ++ } else { ++ /* set EBU clock to 50 MHz */ ++ ltq_sys1_w32_mask(EBUCC_EBUDIV_SELF100, 0, LTQ_EBUCC); ++ ++ /* search for suitable divider */ ++ for (i = 1; i < 7; i++) { ++ if (ebuclk / i <= spi->max_speed_hz) ++ break; ++ } ++ } ++ ++ /* setup period of serial clock */ ++ ltq_ebu_w32_mask(SFTIME_SCKF_POS_MASK ++ | SFTIME_SCKR_POS_MASK ++ | SFTIME_SCK_PER_MASK, ++ (i << SFTIME_SCKR_POS_OFFSET) ++ | (i << (SFTIME_SCK_PER_OFFSET + 1)), ++ LTQ_SFTIME); ++ ++ /* set some bits of unused_wd, to not trigger HOLD/WP ++ * signals on non QUAD flashes */ ++ ltq_ebu_w32((SFIO_UNUSED_WD_MASK & (0x8 | 0x4)), LTQ_SFIO); ++ ++ ltq_ebu_w32(BUSRCON0_AGEN_SERIAL_FLASH | BUSRCON0_PORTW_8_BIT_MUX, ++ LTQ_BUSRCON0); ++ ltq_ebu_w32(BUSWCON0_AGEN_SERIAL_FLASH, LTQ_BUSWCON0); ++ /* set address wrap around to maximum for 24-bit addresses */ ++ ltq_ebu_w32_mask(SFCON_DEV_SIZE_MASK, SFCON_DEV_SIZE_A23_0, LTQ_SFCON); ++ ++ spin_unlock_irqrestore(&ebu_lock, flags); ++ ++ return 0; ++} ++ ++static int ++falcon_spi_transfer(struct spi_device *spi, struct spi_message *m) ++{ ++ struct falcon_spi *priv = spi_master_get_devdata(spi->master); ++ struct spi_transfer *t; ++ unsigned long spi_flags; ++ unsigned long flags; ++ int ret = 0; ++ ++ priv->sfcmd = 0; ++ m->actual_length = 0; ++ ++ spi_flags = FALCON_SPI_XFER_BEGIN; ++ list_for_each_entry(t, &m->transfers, transfer_list) { ++ if (list_is_last(&t->transfer_list, &m->transfers)) ++ spi_flags |= FALCON_SPI_XFER_END; ++ ++ spin_lock_irqsave(&ebu_lock, flags); ++ ret = falcon_spi_xfer(spi, t, spi_flags); ++ spin_unlock_irqrestore(&ebu_lock, flags); ++ ++ if (ret) ++ break; ++ ++ m->actual_length += t->len; ++ ++ if (t->delay_usecs || t->cs_change) ++ BUG(); ++ ++ spi_flags = 0; ++ } ++ ++ m->status = ret; ++ m->complete(m->context); ++ ++ return 0; ++} ++ ++static void ++falcon_spi_cleanup(struct spi_device *spi) ++{ ++ struct device *dev = &spi->dev; ++ ++ dev_dbg(dev, "cleanup\n"); ++} ++ ++static int __devinit ++falcon_spi_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct falcon_spi *priv; ++ struct spi_master *master; ++ int ret; ++ ++ dev_dbg(dev, "probing\n"); ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(*priv)); ++ if (!master) { ++ dev_err(dev, "no memory for spi_master\n"); ++ return -ENOMEM; ++ } ++ ++ priv = spi_master_get_devdata(master); ++ priv->master = master; ++ ++ master->mode_bits = SPI_MODE_3; ++ master->num_chipselect = 1; ++ master->bus_num = 0; ++ ++ master->setup = falcon_spi_setup; ++ master->transfer = falcon_spi_transfer; ++ master->cleanup = falcon_spi_cleanup; ++ ++ platform_set_drvdata(pdev, priv); ++ ++ ret = spi_register_master(master); ++ if (ret) ++ spi_master_put(master); ++ ++ return ret; ++} ++ ++static int __devexit ++falcon_spi_remove(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct falcon_spi *priv = platform_get_drvdata(pdev); ++ ++ dev_dbg(dev, "removed\n"); ++ ++ spi_unregister_master(priv->master); ++ ++ return 0; ++} ++ ++static struct platform_driver falcon_spi_driver = { ++ .probe = falcon_spi_probe, ++ .remove = __devexit_p(falcon_spi_remove), ++ .driver = { ++ .name = DRV_NAME, ++ .owner = THIS_MODULE ++ } ++}; ++ ++static int __init ++falcon_spi_init(void) ++{ ++ return platform_driver_register(&falcon_spi_driver); ++} ++ ++static void __exit ++falcon_spi_exit(void) ++{ ++ platform_driver_unregister(&falcon_spi_driver); ++} ++ ++module_init(falcon_spi_init); ++module_exit(falcon_spi_exit); ++ ++MODULE_LICENSE("GPL"); ++MODULE_DESCRIPTION("Lantiq Falcon SPI controller driver"); +--- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h +@@ -48,6 +48,10 @@ + + #define LTQ_EBU_MODCON 0x000C + ++/* I2C */ ++#define LTQ_I2C_BASE_ADDR 0x1E200000 ++#define LTQ_I2C_SIZE 0x00010000 ++ + /* GPIO */ + #define LTQ_GPIO0_BASE_ADDR 0x1D810000 + #define LTQ_GPIO0_SIZE 0x0080 +@@ -92,6 +96,7 @@ + + /* Activation Status Register */ + #define ACTS_ASC1_ACT 0x00000800 ++#define ACTS_I2C_ACT 0x00004000 + #define ACTS_P0 0x00010000 + #define ACTS_P1 0x00010000 + #define ACTS_P2 0x00020000 diff --git a/target/linux/lantiq/patches/0014-MIPS-lantiq-adds-xway-spi.patch b/target/linux/lantiq/patches/0014-MIPS-lantiq-adds-xway-spi.patch new file mode 100644 index 0000000000..76ab292011 --- /dev/null +++ b/target/linux/lantiq/patches/0014-MIPS-lantiq-adds-xway-spi.patch @@ -0,0 +1,1142 @@ +From e29263339db41d49d79482c93463c4c0cbe764d7 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Fri, 30 Sep 2011 14:23:42 +0200 +Subject: [PATCH 14/24] MIPS: lantiq: adds xway spi + +--- + .../mips/include/asm/mach-lantiq/lantiq_platform.h | 9 + + .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 + + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 + + drivers/spi/Kconfig | 8 + + drivers/spi/Makefile | 2 +- + drivers/spi/spi-xway.c | 1062 ++++++++++++++++++++ + 6 files changed, 1083 insertions(+), 1 deletions(-) + create mode 100644 drivers/spi/spi-xway.c + +--- a/arch/mips/include/asm/mach-lantiq/lantiq_platform.h ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_platform.h +@@ -50,4 +50,13 @@ struct ltq_eth_data { + int mii_mode; + }; + ++ ++struct ltq_spi_platform_data { ++ u16 num_chipselect; ++}; ++ ++struct ltq_spi_controller_data { ++ unsigned gpio; ++}; ++ + #endif +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +@@ -27,6 +27,8 @@ + + #define LTQ_SSC_TIR (INT_NUM_IM0_IRL0 + 15) + #define LTQ_SSC_RIR (INT_NUM_IM0_IRL0 + 14) ++#define LTQ_SSC_TIR_AR9 (INT_NUM_IM0_IRL0 + 14) ++#define LTQ_SSC_RIR_AR9 (INT_NUM_IM0_IRL0 + 15) + #define LTQ_SSC_EIR (INT_NUM_IM0_IRL0 + 16) + + #define LTQ_MEI_DYING_GASP_INT (INT_NUM_IM1_IRL0 + 21) +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -81,6 +81,7 @@ + + #define PMU_DMA 0x0020 + #define PMU_USB 0x8041 ++#define PMU_SPI 0x0100 + #define PMU_LED 0x0800 + #define PMU_GPT 0x1000 + #define PMU_PPE 0x2000 +--- a/drivers/spi/Kconfig ++++ b/drivers/spi/Kconfig +@@ -393,6 +393,14 @@ config SPI_NUC900 + help + SPI driver for Nuvoton NUC900 series ARM SoCs + ++config SPI_XWAY ++ tristate "Lantiq XWAY SPI controller" ++ depends on LANTIQ && SOC_TYPE_XWAY ++ select SPI_BITBANG ++ help ++ This driver supports the Lantiq SoC SPI controller in master ++ mode. ++ + # + # Add new SPI master controllers in alphabetical order above this line + # +--- a/drivers/spi/Makefile ++++ b/drivers/spi/Makefile +@@ -60,4 +60,5 @@ obj-$(CONFIG_SPI_TLE62X0) += spi-tle62x + obj-$(CONFIG_SPI_TOPCLIFF_PCH) += spi-topcliff-pch.o + obj-$(CONFIG_SPI_TXX9) += spi-txx9.o + obj-$(CONFIG_SPI_XILINX) += spi-xilinx.o ++obj-$(CONFIG_SPI_XWAY) += spi-xway.o + +--- /dev/null ++++ b/drivers/spi/spi-xway.c +@@ -0,0 +1,1062 @@ ++/* ++ * Lantiq SoC SPI controller ++ * ++ * Copyright (C) 2011 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com> ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/workqueue.h> ++#include <linux/platform_device.h> ++#include <linux/io.h> ++#include <linux/sched.h> ++#include <linux/delay.h> ++#include <linux/interrupt.h> ++#include <linux/completion.h> ++#include <linux/spinlock.h> ++#include <linux/err.h> ++#include <linux/clk.h> ++#include <linux/gpio.h> ++#include <linux/spi/spi.h> ++#include <linux/spi/spi_bitbang.h> ++ ++#include <lantiq_soc.h> ++#include <lantiq_platform.h> ++ ++#define LTQ_SPI_CLC 0x00 /* Clock control */ ++#define LTQ_SPI_PISEL 0x04 /* Port input select */ ++#define LTQ_SPI_ID 0x08 /* Identification */ ++#define LTQ_SPI_CON 0x10 /* Control */ ++#define LTQ_SPI_STAT 0x14 /* Status */ ++#define LTQ_SPI_WHBSTATE 0x18 /* Write HW modified state */ ++#define LTQ_SPI_TB 0x20 /* Transmit buffer */ ++#define LTQ_SPI_RB 0x24 /* Receive buffer */ ++#define LTQ_SPI_RXFCON 0x30 /* Receive FIFO control */ ++#define LTQ_SPI_TXFCON 0x34 /* Transmit FIFO control */ ++#define LTQ_SPI_FSTAT 0x38 /* FIFO status */ ++#define LTQ_SPI_BRT 0x40 /* Baudrate timer */ ++#define LTQ_SPI_BRSTAT 0x44 /* Baudrate timer status */ ++#define LTQ_SPI_SFCON 0x60 /* Serial frame control */ ++#define LTQ_SPI_SFSTAT 0x64 /* Serial frame status */ ++#define LTQ_SPI_GPOCON 0x70 /* General purpose output control */ ++#define LTQ_SPI_GPOSTAT 0x74 /* General purpose output status */ ++#define LTQ_SPI_FGPO 0x78 /* Forced general purpose output */ ++#define LTQ_SPI_RXREQ 0x80 /* Receive request */ ++#define LTQ_SPI_RXCNT 0x84 /* Receive count */ ++#define LTQ_SPI_DMACON 0xEC /* DMA control */ ++#define LTQ_SPI_IRNEN 0xF4 /* Interrupt node enable */ ++#define LTQ_SPI_IRNICR 0xF8 /* Interrupt node interrupt capture */ ++#define LTQ_SPI_IRNCR 0xFC /* Interrupt node control */ ++ ++#define LTQ_SPI_CLC_SMC_SHIFT 16 /* Clock divider for sleep mode */ ++#define LTQ_SPI_CLC_SMC_MASK 0xFF ++#define LTQ_SPI_CLC_RMC_SHIFT 8 /* Clock divider for normal run mode */ ++#define LTQ_SPI_CLC_RMC_MASK 0xFF ++#define LTQ_SPI_CLC_DISS BIT(1) /* Disable status bit */ ++#define LTQ_SPI_CLC_DISR BIT(0) /* Disable request bit */ ++ ++#define LTQ_SPI_ID_TXFS_SHIFT 24 /* Implemented TX FIFO size */ ++#define LTQ_SPI_ID_TXFS_MASK 0x3F ++#define LTQ_SPI_ID_RXFS_SHIFT 16 /* Implemented RX FIFO size */ ++#define LTQ_SPI_ID_RXFS_MASK 0x3F ++#define LTQ_SPI_ID_REV_MASK 0x1F /* Hardware revision number */ ++#define LTQ_SPI_ID_CFG BIT(5) /* DMA interface support */ ++ ++#define LTQ_SPI_CON_BM_SHIFT 16 /* Data width selection */ ++#define LTQ_SPI_CON_BM_MASK 0x1F ++#define LTQ_SPI_CON_EM BIT(24) /* Echo mode */ ++#define LTQ_SPI_CON_IDLE BIT(23) /* Idle bit value */ ++#define LTQ_SPI_CON_ENBV BIT(22) /* Enable byte valid control */ ++#define LTQ_SPI_CON_RUEN BIT(12) /* Receive underflow error enable */ ++#define LTQ_SPI_CON_TUEN BIT(11) /* Transmit underflow error enable */ ++#define LTQ_SPI_CON_AEN BIT(10) /* Abort error enable */ ++#define LTQ_SPI_CON_REN BIT(9) /* Receive overflow error enable */ ++#define LTQ_SPI_CON_TEN BIT(8) /* Transmit overflow error enable */ ++#define LTQ_SPI_CON_LB BIT(7) /* Loopback control */ ++#define LTQ_SPI_CON_PO BIT(6) /* Clock polarity control */ ++#define LTQ_SPI_CON_PH BIT(5) /* Clock phase control */ ++#define LTQ_SPI_CON_HB BIT(4) /* Heading control */ ++#define LTQ_SPI_CON_RXOFF BIT(1) /* Switch receiver off */ ++#define LTQ_SPI_CON_TXOFF BIT(0) /* Switch transmitter off */ ++ ++#define LTQ_SPI_STAT_RXBV_MASK 0x7 ++#define LTQ_SPI_STAT_RXBV_SHIFT 28 ++#define LTQ_SPI_STAT_BSY BIT(13) /* Busy flag */ ++#define LTQ_SPI_STAT_RUE BIT(12) /* Receive underflow error flag */ ++#define LTQ_SPI_STAT_TUE BIT(11) /* Transmit underflow error flag */ ++#define LTQ_SPI_STAT_AE BIT(10) /* Abort error flag */ ++#define LTQ_SPI_STAT_RE BIT(9) /* Receive error flag */ ++#define LTQ_SPI_STAT_TE BIT(8) /* Transmit error flag */ ++#define LTQ_SPI_STAT_MS BIT(1) /* Master/slave select bit */ ++#define LTQ_SPI_STAT_EN BIT(0) /* Enable bit */ ++ ++#define LTQ_SPI_WHBSTATE_SETTUE BIT(15) /* Set transmit underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETAE BIT(14) /* Set abort error flag */ ++#define LTQ_SPI_WHBSTATE_SETRE BIT(13) /* Set receive error flag */ ++#define LTQ_SPI_WHBSTATE_SETTE BIT(12) /* Set transmit error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTUE BIT(11) /* Clear transmit underflow error flag */ ++#define LTQ_SPI_WHBSTATE_CLRAE BIT(10) /* Clear abort error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRE BIT(9) /* Clear receive error flag */ ++#define LTQ_SPI_WHBSTATE_CLRTE BIT(8) /* Clear transmit error flag */ ++#define LTQ_SPI_WHBSTATE_SETME BIT(7) /* Set mode error flag */ ++#define LTQ_SPI_WHBSTATE_CLRME BIT(6) /* Clear mode error flag */ ++#define LTQ_SPI_WHBSTATE_SETRUE BIT(5) /* Set receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_CLRRUE BIT(4) /* Clear receive underflow error flag */ ++#define LTQ_SPI_WHBSTATE_SETMS BIT(3) /* Set master select bit */ ++#define LTQ_SPI_WHBSTATE_CLRMS BIT(2) /* Clear master select bit */ ++#define LTQ_SPI_WHBSTATE_SETEN BIT(1) /* Set enable bit (operational mode) */ ++#define LTQ_SPI_WHBSTATE_CLREN BIT(0) /* Clear enable bit (config mode */ ++#define LTQ_SPI_WHBSTATE_CLR_ERRORS 0x0F50 ++ ++#define LTQ_SPI_RXFCON_RXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_RXFCON_RXFITL_MASK 0x3F ++#define LTQ_SPI_RXFCON_RXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_RXFCON_RXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_TXFCON_TXFITL_SHIFT 8 /* FIFO interrupt trigger level */ ++#define LTQ_SPI_TXFCON_TXFITL_MASK 0x3F ++#define LTQ_SPI_TXFCON_TXFLU BIT(1) /* FIFO flush */ ++#define LTQ_SPI_TXFCON_TXFEN BIT(0) /* FIFO enable */ ++ ++#define LTQ_SPI_FSTAT_RXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_RXFFL_SHIFT 0 ++#define LTQ_SPI_FSTAT_TXFFL_MASK 0x3f ++#define LTQ_SPI_FSTAT_TXFFL_SHIFT 8 ++ ++#define LTQ_SPI_GPOCON_ISCSBN_SHIFT 8 ++#define LTQ_SPI_GPOCON_INVOUTN_SHIFT 0 ++ ++#define LTQ_SPI_FGPO_SETOUTN_SHIFT 8 ++#define LTQ_SPI_FGPO_CLROUTN_SHIFT 0 ++ ++#define LTQ_SPI_RXREQ_RXCNT_MASK 0xFFFF /* Receive count value */ ++#define LTQ_SPI_RXCNT_TODO_MASK 0xFFFF /* Recevie to-do value */ ++ ++#define LTQ_SPI_IRNEN_F BIT(3) /* Frame end interrupt request */ ++#define LTQ_SPI_IRNEN_E BIT(2) /* Error end interrupt request */ ++#define LTQ_SPI_IRNEN_T BIT(1) /* Transmit end interrupt request */ ++#define LTQ_SPI_IRNEN_R BIT(0) /* Receive end interrupt request */ ++#define LTQ_SPI_IRNEN_ALL 0xF ++ ++/* Hard-wired GPIOs used by SPI controller */ ++#define LTQ_SPI_GPIO_DI 16 ++#define LTQ_SPI_GPIO_DO 17 ++#define LTQ_SPI_GPIO_CLK 18 ++ ++struct ltq_spi { ++ struct spi_bitbang bitbang; ++ struct completion done; ++ spinlock_t lock; ++ ++ struct device *dev; ++ void __iomem *base; ++ struct clk *clk; ++ ++ int status; ++ int irq[3]; ++ ++ const u8 *tx; ++ u8 *rx; ++ u32 tx_cnt; ++ u32 rx_cnt; ++ u32 len; ++ struct spi_transfer *curr_transfer; ++ ++ u32 (*get_tx) (struct ltq_spi *); ++ ++ u16 txfs; ++ u16 rxfs; ++ unsigned dma_support:1; ++ unsigned cfg_mode:1; ++ ++}; ++ ++struct ltq_spi_controller_state { ++ void (*cs_activate) (struct spi_device *); ++ void (*cs_deactivate) (struct spi_device *); ++}; ++ ++struct ltq_spi_irq_map { ++ char *name; ++ irq_handler_t handler; ++}; ++ ++struct ltq_spi_cs_gpio_map { ++ unsigned gpio; ++ unsigned altsel0; ++ unsigned altsel1; ++}; ++ ++static inline struct ltq_spi *ltq_spi_to_hw(struct spi_device *spi) ++{ ++ return spi_master_get_devdata(spi->master); ++} ++ ++static inline u32 ltq_spi_reg_read(struct ltq_spi *hw, u32 reg) ++{ ++ return ioread32be(hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_write(struct ltq_spi *hw, u32 val, u32 reg) ++{ ++ iowrite32be(val, hw->base + reg); ++} ++ ++static inline void ltq_spi_reg_setbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val |= bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static inline void ltq_spi_reg_clearbit(struct ltq_spi *hw, u32 bits, u32 reg) ++{ ++ u32 val; ++ ++ val = ltq_spi_reg_read(hw, reg); ++ val &= ~bits; ++ ltq_spi_reg_write(hw, val, reg); ++} ++ ++static void ltq_spi_hw_enable(struct ltq_spi *hw) ++{ ++ u32 clc; ++ ++ /* Power-up mdule */ ++ ltq_pmu_enable(PMU_SPI); ++ ++ /* ++ * Set clock divider for run mode to 1 to ++ * run at same frequency as FPI bus ++ */ ++ clc = (1 << LTQ_SPI_CLC_RMC_SHIFT); ++ ltq_spi_reg_write(hw, clc, LTQ_SPI_CLC); ++} ++ ++static void ltq_spi_hw_disable(struct ltq_spi *hw) ++{ ++ /* Set clock divider to 0 and set module disable bit */ ++ ltq_spi_reg_write(hw, LTQ_SPI_CLC_DISS, LTQ_SPI_CLC); ++ ++ /* Power-down mdule */ ++ ltq_pmu_disable(PMU_SPI); ++} ++ ++static void ltq_spi_reset_fifos(struct ltq_spi *hw) ++{ ++ u32 val; ++ ++ /* ++ * Enable and flush FIFOs. Set interrupt trigger level to ++ * half of FIFO count implemented in hardware. ++ */ ++ if (hw->txfs > 1) { ++ val = hw->txfs << (LTQ_SPI_TXFCON_TXFITL_SHIFT - 1); ++ val |= LTQ_SPI_TXFCON_TXFEN | LTQ_SPI_TXFCON_TXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_TXFCON); ++ } ++ ++ if (hw->rxfs > 1) { ++ val = hw->rxfs << (LTQ_SPI_RXFCON_RXFITL_SHIFT - 1); ++ val |= LTQ_SPI_RXFCON_RXFEN | LTQ_SPI_RXFCON_RXFLU; ++ ltq_spi_reg_write(hw, val, LTQ_SPI_RXFCON); ++ } ++} ++ ++static inline int ltq_spi_wait_ready(struct ltq_spi *hw) ++{ ++ u32 stat; ++ unsigned long timeout; ++ ++ timeout = jiffies + msecs_to_jiffies(200); ++ ++ do { ++ stat = ltq_spi_reg_read(hw, LTQ_SPI_STAT); ++ if (!(stat & LTQ_SPI_STAT_BSY)) ++ return 0; ++ ++ cond_resched(); ++ } while (!time_after_eq(jiffies, timeout)); ++ ++ dev_err(hw->dev, "SPI wait ready timed out\n"); ++ ++ return -ETIMEDOUT; ++} ++ ++static void ltq_spi_config_mode_set(struct ltq_spi *hw) ++{ ++ if (hw->cfg_mode) ++ return; ++ ++ /* ++ * Putting the SPI module in config mode is only safe if no ++ * transfer is in progress as indicated by busy flag STATE.BSY. ++ */ ++ if (ltq_spi_wait_ready(hw)) { ++ ltq_spi_reset_fifos(hw); ++ hw->status = -ETIMEDOUT; ++ } ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLREN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 1; ++} ++ ++static void ltq_spi_run_mode_set(struct ltq_spi *hw) ++{ ++ if (!hw->cfg_mode) ++ return; ++ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETEN, LTQ_SPI_WHBSTATE); ++ ++ hw->cfg_mode = 0; ++} ++ ++static u32 ltq_spi_tx_word_u8(struct ltq_spi *hw) ++{ ++ const u8 *tx = hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt++; ++ hw->tx++; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u16(struct ltq_spi *hw) ++{ ++ const u16 *tx = (u16 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 2; ++ hw->tx += 2; ++ ++ return data; ++} ++ ++static u32 ltq_spi_tx_word_u32(struct ltq_spi *hw) ++{ ++ const u32 *tx = (u32 *) hw->tx; ++ u32 data = *tx++; ++ ++ hw->tx_cnt += 4; ++ hw->tx += 4; ++ ++ return data; ++} ++ ++static void ltq_spi_bits_per_word_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 bm; ++ u8 bits_per_word = spi->bits_per_word; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->bits_per_word) ++ bits_per_word = hw->curr_transfer->bits_per_word; ++ ++ if (bits_per_word <= 8) ++ hw->get_tx = ltq_spi_tx_word_u8; ++ else if (bits_per_word <= 16) ++ hw->get_tx = ltq_spi_tx_word_u16; ++ else if (bits_per_word <= 32) ++ hw->get_tx = ltq_spi_tx_word_u32; ++ ++ /* CON.BM value = bits_per_word - 1 */ ++ bm = (bits_per_word - 1) << LTQ_SPI_CON_BM_SHIFT; ++ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_CON_BM_MASK << ++ LTQ_SPI_CON_BM_SHIFT, LTQ_SPI_CON); ++ ltq_spi_reg_setbit(hw, bm, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_speed_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 br, max_speed_hz, spi_clk; ++ u32 speed_hz = spi->max_speed_hz; ++ ++ /* ++ * Use either default value of SPI device or value ++ * from current transfer. ++ */ ++ if (hw->curr_transfer && hw->curr_transfer->speed_hz) ++ speed_hz = hw->curr_transfer->speed_hz; ++ ++ /* ++ * SPI module clock is derived from FPI bus clock dependent on ++ * divider value in CLC.RMS which is always set to 1. ++ */ ++ spi_clk = clk_get_rate(hw->clk); ++ ++ /* ++ * Maximum SPI clock frequency in master mode is half of ++ * SPI module clock frequency. Maximum reload value of ++ * baudrate generator BR is 2^16. ++ */ ++ max_speed_hz = spi_clk / 2; ++ if (speed_hz >= max_speed_hz) ++ br = 0; ++ else ++ br = (max_speed_hz / speed_hz) - 1; ++ ++ if (br > 0xFFFF) ++ br = 0xFFFF; ++ ++ ltq_spi_reg_write(hw, br, LTQ_SPI_BRT); ++} ++ ++static void ltq_spi_clockmode_set(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ /* ++ * SPI mode mapping in CON register: ++ * Mode CPOL CPHA CON.PO CON.PH ++ * 0 0 0 0 1 ++ * 1 0 1 0 0 ++ * 2 1 0 1 1 ++ * 3 1 1 1 0 ++ */ ++ if (spi->mode & SPI_CPHA) ++ con &= ~LTQ_SPI_CON_PH; ++ else ++ con |= LTQ_SPI_CON_PH; ++ ++ if (spi->mode & SPI_CPOL) ++ con |= LTQ_SPI_CON_PO; ++ else ++ con &= ~LTQ_SPI_CON_PO; ++ ++ /* Set heading control */ ++ if (spi->mode & SPI_LSB_FIRST) ++ con &= ~LTQ_SPI_CON_HB; ++ else ++ con |= LTQ_SPI_CON_HB; ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_xmit_set(struct ltq_spi *hw, struct spi_transfer *t) ++{ ++ u32 con; ++ ++ con = ltq_spi_reg_read(hw, LTQ_SPI_CON); ++ ++ if (t) { ++ if (t->tx_buf && t->rx_buf) { ++ con &= ~(LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ } else if (t->rx_buf) { ++ con &= ~LTQ_SPI_CON_RXOFF; ++ con |= LTQ_SPI_CON_TXOFF; ++ } else if (t->tx_buf) { ++ con &= ~LTQ_SPI_CON_TXOFF; ++ con |= LTQ_SPI_CON_RXOFF; ++ } ++ } else ++ con |= (LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF); ++ ++ ltq_spi_reg_write(hw, con, LTQ_SPI_CON); ++} ++ ++static void ltq_spi_gpio_cs_activate(struct spi_device *spi) ++{ ++ struct ltq_spi_controller_data *cdata = spi->controller_data; ++ int val = spi->mode & SPI_CS_HIGH ? 1 : 0; ++ ++ gpio_set_value(cdata->gpio, val); ++} ++ ++static void ltq_spi_gpio_cs_deactivate(struct spi_device *spi) ++{ ++ struct ltq_spi_controller_data *cdata = spi->controller_data; ++ int val = spi->mode & SPI_CS_HIGH ? 0 : 1; ++ ++ gpio_set_value(cdata->gpio, val); ++} ++ ++static void ltq_spi_internal_cs_activate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_CLROUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_internal_cs_deactivate(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 fgpo; ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++} ++ ++static void ltq_spi_chipselect(struct spi_device *spi, int cs) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ struct ltq_spi_controller_state *cstate = spi->controller_state; ++ ++ switch (cs) { ++ case BITBANG_CS_ACTIVE: ++ ltq_spi_bits_per_word_set(spi); ++ ltq_spi_speed_set(spi); ++ ltq_spi_clockmode_set(spi); ++ ltq_spi_run_mode_set(hw); ++ ++ cstate->cs_activate(spi); ++ break; ++ ++ case BITBANG_CS_INACTIVE: ++ cstate->cs_deactivate(spi); ++ ++ ltq_spi_config_mode_set(hw); ++ ++ break; ++ } ++} ++ ++static int ltq_spi_setup_transfer(struct spi_device *spi, ++ struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u8 bits_per_word = spi->bits_per_word; ++ ++ hw->curr_transfer = t; ++ ++ if (t && t->bits_per_word) ++ bits_per_word = t->bits_per_word; ++ ++ if (bits_per_word > 32) ++ return -EINVAL; ++ ++ ltq_spi_config_mode_set(hw); ++ ++ return 0; ++} ++ ++static const struct ltq_spi_cs_gpio_map ltq_spi_cs[] = { ++ { 15, 1, 0 }, ++ { 22, 1, 0 }, ++ { 13, 0, 1 }, ++ { 10, 0, 1 }, ++ { 9, 0, 1 }, ++ { 11, 1, 1 }, ++}; ++ ++static int ltq_spi_setup(struct spi_device *spi) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ struct ltq_spi_controller_data *cdata = spi->controller_data; ++ struct ltq_spi_controller_state *cstate; ++ u32 gpocon, fgpo; ++ int ret; ++ ++ /* Set default word length to 8 if not set */ ++ if (!spi->bits_per_word) ++ spi->bits_per_word = 8; ++ ++ if (spi->bits_per_word > 32) ++ return -EINVAL; ++ ++ if (!spi->controller_state) { ++ cstate = kzalloc(sizeof(struct ltq_spi_controller_state), ++ GFP_KERNEL); ++ if (!cstate) ++ return -ENOMEM; ++ ++ spi->controller_state = cstate; ++ } else ++ return 0; ++ ++ /* ++ * Up to six GPIOs can be connected to the SPI module ++ * via GPIO alternate function to control the chip select lines. ++ * For more flexibility in board layout this driver can also control ++ * the CS lines via GPIO API. If GPIOs should be used, board setup code ++ * have to register the SPI device with struct ltq_spi_controller_data ++ * attached. ++ */ ++ if (cdata && cdata->gpio) { ++ ret = gpio_request(cdata->gpio, "spi-cs"); ++ if (ret) ++ return -EBUSY; ++ ++ ret = spi->mode & SPI_CS_HIGH ? 0 : 1; ++ gpio_direction_output(cdata->gpio, ret); ++ ++ cstate->cs_activate = ltq_spi_gpio_cs_activate; ++ cstate->cs_deactivate = ltq_spi_gpio_cs_deactivate; ++ } else { ++ ret = ltq_gpio_request(ltq_spi_cs[spi->chip_select].gpio, ++ ltq_spi_cs[spi->chip_select].altsel0, ++ ltq_spi_cs[spi->chip_select].altsel1, ++ 1, "spi-cs"); ++ if (ret) ++ return -EBUSY; ++ ++ gpocon = (1 << (spi->chip_select + ++ LTQ_SPI_GPOCON_ISCSBN_SHIFT)); ++ ++ if (spi->mode & SPI_CS_HIGH) ++ gpocon |= (1 << spi->chip_select); ++ ++ fgpo = (1 << (spi->chip_select + LTQ_SPI_FGPO_SETOUTN_SHIFT)); ++ ++ ltq_spi_reg_setbit(hw, gpocon, LTQ_SPI_GPOCON); ++ ltq_spi_reg_setbit(hw, fgpo, LTQ_SPI_FGPO); ++ ++ cstate->cs_activate = ltq_spi_internal_cs_activate; ++ cstate->cs_deactivate = ltq_spi_internal_cs_deactivate; ++ } ++ ++ return 0; ++} ++ ++static void ltq_spi_cleanup(struct spi_device *spi) ++{ ++ struct ltq_spi_controller_data *cdata = spi->controller_data; ++ struct ltq_spi_controller_state *cstate = spi->controller_state; ++ unsigned gpio; ++ ++ if (cdata && cdata->gpio) ++ gpio = cdata->gpio; ++ else ++ gpio = ltq_spi_cs[spi->chip_select].gpio; ++ ++ gpio_free(gpio); ++ kfree(cstate); ++} ++ ++static void ltq_spi_txfifo_write(struct ltq_spi *hw) ++{ ++ u32 fstat, data; ++ u16 fifo_space; ++ ++ /* Determine how much FIFOs are free for TX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_space = hw->txfs - ((fstat >> LTQ_SPI_FSTAT_TXFFL_SHIFT) & ++ LTQ_SPI_FSTAT_TXFFL_MASK); ++ ++ if (!fifo_space) ++ return; ++ ++ while (hw->tx_cnt < hw->len && fifo_space) { ++ data = hw->get_tx(hw); ++ ltq_spi_reg_write(hw, data, LTQ_SPI_TB); ++ fifo_space--; ++ } ++} ++ ++static void ltq_spi_rxfifo_read(struct ltq_spi *hw) ++{ ++ u32 fstat, data, *rx32; ++ u16 fifo_fill; ++ u8 rxbv, shift, *rx8; ++ ++ /* Determine how much FIFOs are filled with RX data */ ++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT); ++ fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT) ++ & LTQ_SPI_FSTAT_RXFFL_MASK); ++ ++ if (!fifo_fill) ++ return; ++ ++ /* ++ * The 32 bit FIFO is always used completely independent from the ++ * bits_per_word value. Thus four bytes have to be read at once ++ * per FIFO. ++ */ ++ rx32 = (u32 *) hw->rx; ++ while (hw->len - hw->rx_cnt >= 4 && fifo_fill) { ++ *rx32++ = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ hw->rx_cnt += 4; ++ hw->rx += 4; ++ fifo_fill--; ++ } ++ ++ /* ++ * If there are remaining bytes, read byte count from STAT.RXBV ++ * register and read the data byte-wise. ++ */ ++ while (fifo_fill && hw->rx_cnt < hw->len) { ++ rxbv = (ltq_spi_reg_read(hw, LTQ_SPI_STAT) >> ++ LTQ_SPI_STAT_RXBV_SHIFT) & LTQ_SPI_STAT_RXBV_MASK; ++ data = ltq_spi_reg_read(hw, LTQ_SPI_RB); ++ ++ shift = (rxbv - 1) * 8; ++ rx8 = hw->rx; ++ ++ while (rxbv) { ++ *rx8++ = (data >> shift) & 0xFF; ++ rxbv--; ++ shift -= 8; ++ hw->rx_cnt++; ++ hw->rx++; ++ } ++ ++ fifo_fill--; ++ } ++} ++ ++static void ltq_spi_rxreq_set(struct ltq_spi *hw) ++{ ++ u32 rxreq, rxreq_max, rxtodo; ++ ++ rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK; ++ ++ /* ++ * In RX-only mode the serial clock is activated only after writing ++ * the expected amount of RX bytes into RXREQ register. ++ * To avoid receive overflows at high clocks it is better to request ++ * only the amount of bytes that fits into all FIFOs. This value ++ * depends on the FIFO size implemented in hardware. ++ */ ++ rxreq = hw->len - hw->rx_cnt; ++ rxreq_max = hw->rxfs << 2; ++ rxreq = min(rxreq_max, rxreq); ++ ++ if (!rxtodo && rxreq) ++ ltq_spi_reg_write(hw, rxreq, LTQ_SPI_RXREQ); ++} ++ ++static inline void ltq_spi_complete(struct ltq_spi *hw) ++{ ++ complete(&hw->done); ++} ++ ++irqreturn_t ltq_spi_tx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ ++ if (hw->tx_cnt == hw->len) ++ completed = 1; ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_rx_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ int completed = 0; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ if (hw->rx_cnt < hw->len) { ++ ltq_spi_rxfifo_read(hw); ++ ++ if (hw->tx && hw->tx_cnt < hw->len) ++ ltq_spi_txfifo_write(hw); ++ } ++ ++ if (hw->rx_cnt == hw->len) ++ completed = 1; ++ else if (!hw->tx) ++ ltq_spi_rxreq_set(hw); ++ ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ if (completed) ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++irqreturn_t ltq_spi_err_irq(int irq, void *data) ++{ ++ struct ltq_spi *hw = data; ++ unsigned long flags; ++ ++ spin_lock_irqsave(&hw->lock, flags); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ /* Clear all error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Flush FIFOs */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_RXFCON_RXFLU, LTQ_SPI_RXFCON); ++ ltq_spi_reg_setbit(hw, LTQ_SPI_TXFCON_TXFLU, LTQ_SPI_TXFCON); ++ ++ hw->status = -EIO; ++ spin_unlock_irqrestore(&hw->lock, flags); ++ ++ ltq_spi_complete(hw); ++ ++ return IRQ_HANDLED; ++} ++ ++static int ltq_spi_txrx_bufs(struct spi_device *spi, struct spi_transfer *t) ++{ ++ struct ltq_spi *hw = ltq_spi_to_hw(spi); ++ u32 irq_flags = 0; ++ ++ hw->tx = t->tx_buf; ++ hw->rx = t->rx_buf; ++ hw->len = t->len; ++ hw->tx_cnt = 0; ++ hw->rx_cnt = 0; ++ hw->status = 0; ++ INIT_COMPLETION(hw->done); ++ ++ ltq_spi_xmit_set(hw, t); ++ ++ /* Enable error interrupts */ ++ ltq_spi_reg_setbit(hw, LTQ_SPI_IRNEN_E, LTQ_SPI_IRNEN); ++ ++ if (hw->tx) { ++ /* Initially fill TX FIFO with as much data as possible */ ++ ltq_spi_txfifo_write(hw); ++ irq_flags |= LTQ_SPI_IRNEN_T; ++ ++ /* Always enable RX interrupt in Full Duplex mode */ ++ if (hw->rx) ++ irq_flags |= LTQ_SPI_IRNEN_R; ++ } else if (hw->rx) { ++ /* Start RX clock */ ++ ltq_spi_rxreq_set(hw); ++ ++ /* Enable RX interrupt to receive data from RX FIFOs */ ++ irq_flags |= LTQ_SPI_IRNEN_R; ++ } ++ ++ /* Enable TX or RX interrupts */ ++ ltq_spi_reg_setbit(hw, irq_flags, LTQ_SPI_IRNEN); ++ wait_for_completion_interruptible(&hw->done); ++ ++ /* Disable all interrupts */ ++ ltq_spi_reg_clearbit(hw, LTQ_SPI_IRNEN_ALL, LTQ_SPI_IRNEN); ++ ++ /* ++ * Return length of current transfer for bitbang utility code if ++ * no errors occured during transmission. ++ */ ++ if (!hw->status) ++ hw->status = hw->len; ++ ++ return hw->status; ++} ++ ++static const struct ltq_spi_irq_map ltq_spi_irqs[] = { ++ { "spi_tx", ltq_spi_tx_irq }, ++ { "spi_rx", ltq_spi_rx_irq }, ++ { "spi_err", ltq_spi_err_irq }, ++}; ++ ++static int __init ltq_spi_probe(struct platform_device *pdev) ++{ ++ struct spi_master *master; ++ struct resource *r; ++ struct ltq_spi *hw; ++ struct ltq_spi_platform_data *pdata = pdev->dev.platform_data; ++ int ret, i; ++ u32 data, id; ++ ++ master = spi_alloc_master(&pdev->dev, sizeof(struct ltq_spi)); ++ if (!master) { ++ dev_err(&pdev->dev, "spi_alloc_master\n"); ++ ret = -ENOMEM; ++ goto err; ++ } ++ ++ hw = spi_master_get_devdata(master); ++ ++ r = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (r == NULL) { ++ dev_err(&pdev->dev, "platform_get_resource\n"); ++ ret = -ENOENT; ++ goto err_master; ++ } ++ ++ r = devm_request_mem_region(&pdev->dev, r->start, resource_size(r), ++ pdev->name); ++ if (!r) { ++ dev_err(&pdev->dev, "devm_request_mem_region\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ hw->base = devm_ioremap_nocache(&pdev->dev, r->start, resource_size(r)); ++ if (!hw->base) { ++ dev_err(&pdev->dev, "devm_ioremap_nocache\n"); ++ ret = -ENXIO; ++ goto err_master; ++ } ++ ++ hw->clk = clk_get(&pdev->dev, "fpi"); ++ if (IS_ERR(hw->clk)) { ++ dev_err(&pdev->dev, "clk_get\n"); ++ ret = PTR_ERR(hw->clk); ++ goto err_master; ++ } ++ ++ memset(hw->irq, 0, sizeof(hw->irq)); ++ for (i = 0; i < ARRAY_SIZE(ltq_spi_irqs); i++) { ++ ret = platform_get_irq_byname(pdev, ltq_spi_irqs[i].name); ++ if (0 > ret) { ++ dev_err(&pdev->dev, "platform_get_irq_byname\n"); ++ goto err_irq; ++ } ++ ++ hw->irq[i] = ret; ++ ret = request_irq(hw->irq[i], ltq_spi_irqs[i].handler, ++ 0, ltq_spi_irqs[i].name, hw); ++ if (ret) { ++ dev_err(&pdev->dev, "request_irq\n"); ++ goto err_irq; ++ } ++ } ++ ++ hw->bitbang.master = spi_master_get(master); ++ hw->bitbang.chipselect = ltq_spi_chipselect; ++ hw->bitbang.setup_transfer = ltq_spi_setup_transfer; ++ hw->bitbang.txrx_bufs = ltq_spi_txrx_bufs; ++ ++ master->bus_num = pdev->id; ++ master->num_chipselect = pdata->num_chipselect; ++ master->setup = ltq_spi_setup; ++ master->cleanup = ltq_spi_cleanup; ++ ++ hw->dev = &pdev->dev; ++ init_completion(&hw->done); ++ spin_lock_init(&hw->lock); ++ ++ /* Set GPIO alternate functions to SPI */ ++ ltq_gpio_request(LTQ_SPI_GPIO_DI, 1, 0, 0, "spi-di"); ++ ltq_gpio_request(LTQ_SPI_GPIO_DO, 1, 0, 1, "spi-do"); ++ ltq_gpio_request(LTQ_SPI_GPIO_CLK, 1, 0, 1, "spi-clk"); ++ ++ ltq_spi_hw_enable(hw); ++ ++ /* Read module capabilities */ ++ id = ltq_spi_reg_read(hw, LTQ_SPI_ID); ++ hw->txfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->rxfs = (id >> LTQ_SPI_ID_TXFS_SHIFT) & LTQ_SPI_ID_TXFS_MASK; ++ hw->dma_support = (id & LTQ_SPI_ID_CFG) ? 1 : 0; ++ ++ ltq_spi_config_mode_set(hw); ++ ++ /* Enable error checking, disable TX/RX, set idle value high */ ++ data = LTQ_SPI_CON_RUEN | LTQ_SPI_CON_AEN | ++ LTQ_SPI_CON_TEN | LTQ_SPI_CON_REN | ++ LTQ_SPI_CON_TXOFF | LTQ_SPI_CON_RXOFF | LTQ_SPI_CON_IDLE; ++ ltq_spi_reg_write(hw, data, LTQ_SPI_CON); ++ ++ /* Enable master mode and clear error flags */ ++ ltq_spi_reg_write(hw, LTQ_SPI_WHBSTATE_SETMS | ++ LTQ_SPI_WHBSTATE_CLR_ERRORS, LTQ_SPI_WHBSTATE); ++ ++ /* Reset GPIO/CS registers */ ++ ltq_spi_reg_write(hw, 0x0, LTQ_SPI_GPOCON); ++ ltq_spi_reg_write(hw, 0xFF00, LTQ_SPI_FGPO); ++ ++ /* Enable and flush FIFOs */ ++ ltq_spi_reset_fifos(hw); ++ ++ ret = spi_bitbang_start(&hw->bitbang); ++ if (ret) { ++ dev_err(&pdev->dev, "spi_bitbang_start\n"); ++ goto err_bitbang; ++ } ++ ++ platform_set_drvdata(pdev, hw); ++ ++ pr_info("Lantiq SoC SPI controller rev %u (TXFS %u, RXFS %u, DMA %u)\n", ++ id & LTQ_SPI_ID_REV_MASK, hw->txfs, hw->rxfs, hw->dma_support); ++ ++ return 0; ++ ++err_bitbang: ++ ltq_spi_hw_disable(hw); ++ ++err_irq: ++ clk_put(hw->clk); ++ ++ for (; i > 0; i--) ++ free_irq(hw->irq[i], hw); ++ ++err_master: ++ spi_master_put(master); ++ ++err: ++ return ret; ++} ++ ++static int __exit ltq_spi_remove(struct platform_device *pdev) ++{ ++ struct ltq_spi *hw = platform_get_drvdata(pdev); ++ int ret, i; ++ ++ ret = spi_bitbang_stop(&hw->bitbang); ++ if (ret) ++ return ret; ++ ++ platform_set_drvdata(pdev, NULL); ++ ++ ltq_spi_config_mode_set(hw); ++ ltq_spi_hw_disable(hw); ++ ++ for (i = 0; i < ARRAY_SIZE(hw->irq); i++) ++ if (0 < hw->irq[i]) ++ free_irq(hw->irq[i], hw); ++ ++ gpio_free(LTQ_SPI_GPIO_DI); ++ gpio_free(LTQ_SPI_GPIO_DO); ++ gpio_free(LTQ_SPI_GPIO_CLK); ++ ++ clk_put(hw->clk); ++ spi_master_put(hw->bitbang.master); ++ ++ return 0; ++} ++ ++static struct platform_driver ltq_spi_driver = { ++ .driver = { ++ .name = "ltq-spi", ++ .owner = THIS_MODULE, ++ }, ++ .remove = __exit_p(ltq_spi_remove), ++}; ++ ++static int __init ltq_spi_init(void) ++{ ++ return platform_driver_probe(<q_spi_driver, ltq_spi_probe); ++} ++module_init(ltq_spi_init); ++ ++static void __exit ltq_spi_exit(void) ++{ ++ platform_driver_unregister(<q_spi_driver); ++} ++module_exit(ltq_spi_exit); ++ ++MODULE_DESCRIPTION("Lantiq SoC SPI controller driver"); ++MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>"); ++MODULE_LICENSE("GPL"); ++MODULE_ALIAS("platform:ltq-spi"); diff --git a/target/linux/lantiq/patches/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch b/target/linux/lantiq/patches/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch new file mode 100644 index 0000000000..10e69df4ea --- /dev/null +++ b/target/linux/lantiq/patches/0015-MIPS-lantiq-adds-etop-support-for-ase-ar9.patch @@ -0,0 +1,409 @@ +From c7881d8d2b3aed9a90aa37dcf797328a9cfbe7b6 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Wed, 10 Aug 2011 15:32:16 +0200 +Subject: [PATCH 15/24] MIPS: lantiq: adds etop support for ase/ar9 + +Extend the driver to handle the different DMA channel layout for AR9 and +SoCs. The patch also adds support for the integrated PHY found on Amazon-SE +and the gigabit switch found inside the AR9. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 22 +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 10 ++ + arch/mips/lantiq/xway/devices.c | 11 +- + arch/mips/lantiq/xway/mach-easy50601.c | 5 + + drivers/net/lantiq_etop.c | 172 ++++++++++++++++++-- + 5 files changed, 180 insertions(+), 40 deletions(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h +@@ -40,26 +40,8 @@ + + #define MIPS_CPU_TIMER_IRQ 7 + +-#define LTQ_DMA_CH0_INT (INT_NUM_IM2_IRL0) +-#define LTQ_DMA_CH1_INT (INT_NUM_IM2_IRL0 + 1) +-#define LTQ_DMA_CH2_INT (INT_NUM_IM2_IRL0 + 2) +-#define LTQ_DMA_CH3_INT (INT_NUM_IM2_IRL0 + 3) +-#define LTQ_DMA_CH4_INT (INT_NUM_IM2_IRL0 + 4) +-#define LTQ_DMA_CH5_INT (INT_NUM_IM2_IRL0 + 5) +-#define LTQ_DMA_CH6_INT (INT_NUM_IM2_IRL0 + 6) +-#define LTQ_DMA_CH7_INT (INT_NUM_IM2_IRL0 + 7) +-#define LTQ_DMA_CH8_INT (INT_NUM_IM2_IRL0 + 8) +-#define LTQ_DMA_CH9_INT (INT_NUM_IM2_IRL0 + 9) +-#define LTQ_DMA_CH10_INT (INT_NUM_IM2_IRL0 + 10) +-#define LTQ_DMA_CH11_INT (INT_NUM_IM2_IRL0 + 11) +-#define LTQ_DMA_CH12_INT (INT_NUM_IM2_IRL0 + 25) +-#define LTQ_DMA_CH13_INT (INT_NUM_IM2_IRL0 + 26) +-#define LTQ_DMA_CH14_INT (INT_NUM_IM2_IRL0 + 27) +-#define LTQ_DMA_CH15_INT (INT_NUM_IM2_IRL0 + 28) +-#define LTQ_DMA_CH16_INT (INT_NUM_IM2_IRL0 + 29) +-#define LTQ_DMA_CH17_INT (INT_NUM_IM2_IRL0 + 30) +-#define LTQ_DMA_CH18_INT (INT_NUM_IM2_IRL0 + 16) +-#define LTQ_DMA_CH19_INT (INT_NUM_IM2_IRL0 + 21) ++#define LTQ_DMA_ETOP ((ltq_is_ase()) ? \ ++ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0)) + + #define LTQ_PPE_MBOX_INT (INT_NUM_IM2_IRL0 + 24) + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -80,6 +80,7 @@ + #define LTQ_PMU_SIZE 0x1000 + + #define PMU_DMA 0x0020 ++#define PMU_EPHY 0x0080 + #define PMU_USB 0x8041 + #define PMU_SPI 0x0100 + #define PMU_LED 0x0800 +@@ -92,6 +93,10 @@ + #define LTQ_ETOP_BASE_ADDR 0x1E180000 + #define LTQ_ETOP_SIZE 0x40000 + ++/* GBIT - gigabit switch */ ++#define LTQ_GBIT_BASE_ADDR 0x1E108000 ++#define LTQ_GBIT_SIZE 0x200 ++ + /* DMA */ + #define LTQ_DMA_BASE_ADDR 0x1E104100 + #define LTQ_DMA_SIZE 0x800 +@@ -148,6 +153,11 @@ extern void ltq_pmu_enable(unsigned int + extern void ltq_pmu_disable(unsigned int module); + extern void ltq_cgu_enable(unsigned int clk); + ++static inline int ltq_is_ase(void) ++{ ++ return (ltq_get_soc_type() == SOC_TYPE_AMAZON_SE); ++} ++ + static inline int ltq_is_ar9(void) + { + return (ltq_get_soc_type() == SOC_TYPE_AR9); +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -77,18 +77,23 @@ void __init ltq_register_ase_asc(void) + } + + /* ethernet */ +-static struct resource ltq_etop_resources = +- MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE); ++static struct resource ltq_etop_resources[] = { ++ MEM_RES("etop", LTQ_ETOP_BASE_ADDR, LTQ_ETOP_SIZE), ++ MEM_RES("gbit", LTQ_GBIT_BASE_ADDR, LTQ_GBIT_SIZE), ++}; + + static struct platform_device ltq_etop = { + .name = "ltq_etop", +- .resource = <q_etop_resources, ++ .resource = ltq_etop_resources, + .num_resources = 1, + }; + + void __init + ltq_register_etop(struct ltq_eth_data *eth) + { ++ /* only register the gphy on socs that have one */ ++ if (ltq_is_ar9() | ltq_is_vr9()) ++ ltq_etop.num_resources = 2; + if (eth) { + ltq_etop.dev.platform_data = eth; + platform_device_register(<q_etop); +--- a/drivers/net/lantiq_etop.c ++++ b/drivers/net/lantiq_etop.c +@@ -34,6 +34,7 @@ + #include <linux/init.h> + #include <linux/delay.h> + #include <linux/io.h> ++#include <linux/dma-mapping.h> + + #include <asm/checksum.h> + +@@ -69,10 +70,43 @@ + #define ETOP_MII_REVERSE 0xe + #define ETOP_PLEN_UNDER 0x40 + #define ETOP_CGEN 0x800 ++#define ETOP_CFG_MII0 0x01 + +-/* use 2 static channels for TX/RX */ ++#define LTQ_GBIT_MDIO_CTL 0xCC ++#define LTQ_GBIT_MDIO_DATA 0xd0 ++#define LTQ_GBIT_GCTL0 0x68 ++#define LTQ_GBIT_PMAC_HD_CTL 0x8c ++#define LTQ_GBIT_P0_CTL 0x4 ++#define LTQ_GBIT_PMAC_RX_IPG 0xa8 ++ ++#define PMAC_HD_CTL_AS (1 << 19) ++#define PMAC_HD_CTL_RXSH (1 << 22) ++ ++/* Switch Enable (0=disable, 1=enable) */ ++#define GCTL0_SE 0x80000000 ++/* Disable MDIO auto polling (0=disable, 1=enable) */ ++#define PX_CTL_DMDIO 0x00400000 ++ ++/* register information for the gbit's MDIO bus */ ++#define MDIO_XR9_REQUEST 0x00008000 ++#define MDIO_XR9_READ 0x00000800 ++#define MDIO_XR9_WRITE 0x00000400 ++#define MDIO_XR9_REG_MASK 0x1f ++#define MDIO_XR9_ADDR_MASK 0x1f ++#define MDIO_XR9_RD_MASK 0xffff ++#define MDIO_XR9_REG_OFFSET 0 ++#define MDIO_XR9_ADDR_OFFSET 5 ++#define MDIO_XR9_WR_OFFSET 16 ++ ++/* the newer xway socks have a embedded 3/7 port gbit multiplexer */ ++#define ltq_has_gbit() (ltq_is_ar9() || ltq_is_vr9()) ++ ++/* use 2 static channels for TX/RX ++ depending on the SoC we need to use different DMA channels for ethernet */ + #define LTQ_ETOP_TX_CHANNEL 1 +-#define LTQ_ETOP_RX_CHANNEL 6 ++#define LTQ_ETOP_RX_CHANNEL ((ltq_is_ase()) ? (5) : \ ++ ((ltq_has_gbit()) ? (0) : (6))) ++ + #define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL) + #define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL) + +@@ -81,9 +115,15 @@ + #define ltq_etop_w32_mask(x, y, z) \ + ltq_w32_mask(x, y, ltq_etop_membase + (z)) + ++#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x)) ++#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y)) ++#define ltq_gbit_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_gbit_membase + (z)) ++ + #define DRV_VERSION "1.0" + + static void __iomem *ltq_etop_membase; ++static void __iomem *ltq_gbit_membase; + + struct ltq_etop_chan { + int idx; +@@ -108,6 +148,9 @@ struct ltq_etop_priv { + spinlock_t lock; + }; + ++static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data); ++ + static int + ltq_etop_alloc_skb(struct ltq_etop_chan *ch) + { +@@ -209,7 +252,7 @@ static irqreturn_t + ltq_etop_dma_irq(int irq, void *_priv) + { + struct ltq_etop_priv *priv = _priv; +- int ch = irq - LTQ_DMA_CH0_INT; ++ int ch = irq - LTQ_DMA_ETOP; + + napi_schedule(&priv->ch[ch].napi); + return IRQ_HANDLED; +@@ -242,26 +285,66 @@ ltq_etop_hw_exit(struct net_device *dev) + ltq_etop_free_channel(dev, &priv->ch[i]); + } + ++static void ++ltq_etop_gbit_init(void) ++{ ++ ltq_pmu_enable(PMU_SWITCH); ++ ++ ltq_gpio_request(42, 1, 0, 1, "MDIO"); ++ ltq_gpio_request(43, 1, 0, 1, "MDC"); ++ ++ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0); ++ /** Disable MDIO auto polling mode */ ++ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL); ++ /* set 1522 packet size */ ++ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0); ++ /* disable pmac & dmac headers */ ++ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0, ++ LTQ_GBIT_PMAC_HD_CTL); ++ /* Due to traffic halt when burst length 8, ++ replace default IPG value with 0x3B */ ++ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG); ++} ++ + static int + ltq_etop_hw_init(struct net_device *dev) + { + struct ltq_etop_priv *priv = netdev_priv(dev); ++ unsigned int mii_mode = priv->pldata->mii_mode; + int i; + + ltq_pmu_enable(PMU_PPE); + +- switch (priv->pldata->mii_mode) { ++ if (ltq_has_gbit()) { ++ ltq_etop_gbit_init(); ++ } ++ ++ switch (mii_mode) { ++ case PHY_INTERFACE_MODE_RGMII: + case PHY_INTERFACE_MODE_RMII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_REVERSE, LTQ_ETOP_CFG); + break; + ++ case PHY_INTERFACE_MODE_GMII: + case PHY_INTERFACE_MODE_MII: + ltq_etop_w32_mask(ETOP_MII_MASK, + ETOP_MII_NORMAL, LTQ_ETOP_CFG); + break; + + default: ++ if (ltq_is_ase()) { ++ ltq_pmu_enable(PMU_EPHY); ++ /* disable external MII */ ++ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG); ++ /* enable clock for internal PHY */ ++ ltq_cgu_enable(CGU_EPHY); ++ /* we need to write this magic to the internal phy to ++ make it work */ ++ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020); ++ pr_info("Selected EPHY mode\n"); ++ break; ++ } + netdev_err(dev, "unknown mii mode %d\n", + priv->pldata->mii_mode); + return -ENOTSUPP; +@@ -273,7 +356,7 @@ ltq_etop_hw_init(struct net_device *dev) + ltq_dma_init_port(DMA_PORT_ETOP); + + for (i = 0; i < MAX_DMA_CHAN; i++) { +- int irq = LTQ_DMA_CH0_INT + i; ++ int irq = LTQ_DMA_ETOP + i; + struct ltq_etop_chan *ch = &priv->ch[i]; + + ch->idx = ch->dma.nr = i; +@@ -337,6 +420,39 @@ static const struct ethtool_ops ltq_etop + }; + + static int ++ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr, ++ int phy_reg, u16 phy_data) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE | ++ (phy_data << MDIO_XR9_WR_OFFSET) | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ return 0; ++} ++ ++static int ++ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg) ++{ ++ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ | ++ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) | ++ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET); ++ ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL); ++ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST) ++ ; ++ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK; ++ return val; ++} ++ ++static int + ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data) + { + u32 val = MDIO_REQUEST | +@@ -377,14 +493,11 @@ ltq_etop_mdio_probe(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + struct phy_device *phydev = NULL; +- int phy_addr; + +- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) { +- if (priv->mii_bus->phy_map[phy_addr]) { +- phydev = priv->mii_bus->phy_map[phy_addr]; +- break; +- } +- } ++ if (ltq_is_ase()) ++ phydev = priv->mii_bus->phy_map[8]; ++ else ++ phydev = priv->mii_bus->phy_map[0]; + + if (!phydev) { + netdev_err(dev, "no PHY found\n"); +@@ -406,6 +519,9 @@ ltq_etop_mdio_probe(struct net_device *d + | SUPPORTED_Autoneg + | SUPPORTED_MII + | SUPPORTED_TP); ++ if (ltq_has_gbit()) ++ phydev->supported &= SUPPORTED_1000baseT_Half ++ | SUPPORTED_1000baseT_Full; + + phydev->advertising = phydev->supported; + priv->phydev = phydev; +@@ -431,8 +547,13 @@ ltq_etop_mdio_init(struct net_device *de + } + + priv->mii_bus->priv = dev; +- priv->mii_bus->read = ltq_etop_mdio_rd; +- priv->mii_bus->write = ltq_etop_mdio_wr; ++ if (ltq_has_gbit()) { ++ priv->mii_bus->read = ltq_etop_mdio_rd_xr9; ++ priv->mii_bus->write = ltq_etop_mdio_wr_xr9; ++ } else { ++ priv->mii_bus->read = ltq_etop_mdio_rd; ++ priv->mii_bus->write = ltq_etop_mdio_wr; ++ } + priv->mii_bus->name = "ltq_mii"; + snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0); + priv->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); +@@ -522,9 +643,9 @@ ltq_etop_tx(struct sk_buff *skb, struct + struct ltq_etop_priv *priv = netdev_priv(dev); + struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1]; + struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc]; +- int len; + unsigned long flags; + u32 byte_offset; ++ int len; + + len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len; + +@@ -698,7 +819,7 @@ ltq_etop_probe(struct platform_device *p + { + struct net_device *dev; + struct ltq_etop_priv *priv; +- struct resource *res; ++ struct resource *res, *gbit_res; + int err; + int i; + +@@ -726,6 +847,23 @@ ltq_etop_probe(struct platform_device *p + goto err_out; + } + ++ if (ltq_has_gbit()) { ++ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); ++ if (!gbit_res) { ++ dev_err(&pdev->dev, "failed to get gbit resource\n"); ++ err = -ENOENT; ++ goto err_out; ++ } ++ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev, ++ gbit_res->start, resource_size(gbit_res)); ++ if (!ltq_gbit_membase) { ++ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n", ++ pdev->id); ++ err = -ENOMEM; ++ goto err_out; ++ } ++ } ++ + dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4); + strcpy(dev->name, "eth%d"); + dev->netdev_ops = <q_eth_netdev_ops; diff --git a/target/linux/lantiq/patches/0016-MIPS-lantiq-adds-xway-nand-driver.patch b/target/linux/lantiq/patches/0016-MIPS-lantiq-adds-xway-nand-driver.patch new file mode 100644 index 0000000000..fbcdb2762a --- /dev/null +++ b/target/linux/lantiq/patches/0016-MIPS-lantiq-adds-xway-nand-driver.patch @@ -0,0 +1,253 @@ +From e2d5b4ba92289cb0fcc9db741d159ef5eb852d9f Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 27 Aug 2011 20:08:14 +0200 +Subject: [PATCH 16/24] MIPS: lantiq: adds xway nand driver + +This patch adds a nand driver for XWAY SoCs. The patch makes use of the +plat_nand driver. As with the EBU NOR driver merged in 3.0, we have the +endianess swap problem on read. To workaround this problem we make the +read_byte() callback available via the plat_nand driver causing the nand +layer to do byte reads. + +Signed-off-by: John Crispin <blogic@openwrt.org> + +TODO : memory ranges + cs lines + plat dev + ebu2 and not ebu1 ? +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/nand.c | 185 ++++++++++++++++++++ + drivers/mtd/nand/plat_nand.c | 1 + + include/linux/mtd/nand.h | 1 + + 5 files changed, 190 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/lantiq/xway/nand.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -140,6 +140,8 @@ + /* register access macros for EBU and CGU */ + #define ltq_ebu_w32(x, y) ltq_w32((x), ltq_ebu_membase + (y)) + #define ltq_ebu_r32(x) ltq_r32(ltq_ebu_membase + (x)) ++#define ltq_ebu_w32_mask(x, y, z) \ ++ ltq_w32_mask(x, y, ltq_ebu_membase + (z)) + #define ltq_cgu_w32(x, y) ltq_w32((x), ltq_cgu_membase + (y)) + #define ltq_cgu_r32(x) ltq_r32(ltq_cgu_membase + (x)) + +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,4 @@ +-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o ++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o + + obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o + obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/nand.c +@@ -0,0 +1,185 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/mtd/physmap.h> ++#include <linux/mtd/nand.h> ++#include <linux/platform_device.h> ++ ++#include <lantiq_soc.h> ++#include <lantiq_irq.h> ++#include <lantiq_platform.h> ++ ++#include "devices.h" ++ ++/* nand registers */ ++#define LTQ_EBU_NAND_WAIT 0xB4 ++#define LTQ_EBU_NAND_ECC0 0xB8 ++#define LTQ_EBU_NAND_ECC_AC 0xBC ++#define LTQ_EBU_NAND_CON 0xB0 ++#define LTQ_EBU_ADDSEL1 0x24 ++ ++/* gpio definitions */ ++#define PIN_ALE 13 ++#define PIN_CLE 24 ++#define PIN_CS1 23 ++#define PIN_RDY 48 /* NFLASH_READY */ ++#define PIN_RD 49 /* NFLASH_READ_N */ ++ ++#define NAND_CMD_ALE (1 << 2) ++#define NAND_CMD_CLE (1 << 3) ++#define NAND_CMD_CS (1 << 4) ++#define NAND_WRITE_CMD_RESET 0xff ++#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE) ++#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE) ++#define NAND_WRITE_DATA (NAND_CMD_CS) ++#define NAND_READ_DATA (NAND_CMD_CS) ++#define NAND_WAIT_WR_C (1 << 3) ++#define NAND_WAIT_RD (0x1) ++ ++#define ADDSEL1_MASK(x) (x << 4) ++#define ADDSEL1_REGEN 1 ++#define BUSCON1_SETUP (1 << 22) ++#define BUSCON1_BCGEN_RES (0x3 << 12) ++#define BUSCON1_WAITWRC2 (2 << 8) ++#define BUSCON1_WAITRDC2 (2 << 6) ++#define BUSCON1_HOLDC1 (1 << 4) ++#define BUSCON1_RECOVC1 (1 << 2) ++#define BUSCON1_CMULT4 1 ++#define NAND_CON_NANDM 1 ++#define NAND_CON_CSMUX (1 << 1) ++#define NAND_CON_CS_P (1 << 4) ++#define NAND_CON_SE_P (1 << 5) ++#define NAND_CON_WP_P (1 << 6) ++#define NAND_CON_PRE_P (1 << 7) ++#define NAND_CON_IN_CS0 0 ++#define NAND_CON_OUT_CS0 0 ++#define NAND_CON_IN_CS1 (1 << 8) ++#define NAND_CON_OUT_CS1 (1 << 10) ++#define NAND_CON_CE (1 << 20) ++ ++#define NAND_BASE_ADDRESS (KSEG1 | 0x14000000) ++ ++static const char *part_probes[] = { "cmdlinepart", NULL }; ++ ++static void ++xway_select_chip(struct mtd_info *mtd, int chip) ++{ ++ switch (chip) { ++ case -1: ++ ltq_ebu_w32_mask(NAND_CON_CE, 0, LTQ_EBU_NAND_CON); ++ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, LTQ_EBU_NAND_CON); ++ break; ++ case 0: ++ ltq_ebu_w32_mask(0, NAND_CON_NANDM, LTQ_EBU_NAND_CON); ++ ltq_ebu_w32_mask(0, NAND_CON_CE, LTQ_EBU_NAND_CON); ++ /* reset the nand chip */ ++ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); ++ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); ++ break; ++ default: ++ BUG(); ++ } ++} ++ ++static void ++xway_cmd_ctrl(struct mtd_info *mtd, int data, unsigned int ctrl) ++{ ++ struct nand_chip *this = mtd->priv; ++ ++ if (ctrl & NAND_CTRL_CHANGE) { ++ if(ctrl & NAND_CLE) ++ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_CMD); ++ else if(ctrl & NAND_ALE) ++ this->IO_ADDR_W = (void __iomem *)(NAND_BASE_ADDRESS | NAND_WRITE_ADDR); ++ } ++ ++ if(data != NAND_CMD_NONE) { ++ *(volatile u8*)((u32)this->IO_ADDR_W) = data; ++ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); ++ } ++} ++ ++static int ++xway_dev_ready(struct mtd_info *mtd) ++{ ++ return ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_RD; ++} ++ ++void ++nand_write(unsigned int addr, unsigned int val) ++{ ++ ltq_w32(val, ((u32*)(NAND_BASE_ADDRESS | addr))); ++ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); ++} ++ ++unsigned char ++ltq_nand_read_byte(struct mtd_info *mtd) ++{ ++ return ltq_r8((void __iomem *)(NAND_BASE_ADDRESS | (NAND_READ_DATA))); ++} ++ ++int xway_nand_probe(struct platform_device *pdev) ++{ ++// ltq_gpio_request(PIN_CS1, 1, 0, 1, "NAND_CS1"); ++ ltq_gpio_request(PIN_CLE, 1, 0, 1, "NAND_CLE"); ++ ltq_gpio_request(PIN_ALE, 1, 0, 1, "NAND_ALE"); ++ if (ltq_is_ar9() || ltq_is_vr9()) { ++ ltq_gpio_request(PIN_RDY, 1, 0, 0, "NAND_BSY"); ++ ltq_gpio_request(PIN_RD, 1, 0, 1, "NAND_RD"); ++ } ++ ++ ltq_ebu_w32((NAND_BASE_ADDRESS & 0x1fffff00) ++ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, LTQ_EBU_ADDSEL1); ++ ++ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2 ++ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1 ++ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1); ++ ++ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P ++ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P ++ | NAND_CON_IN_CS0 | NAND_CON_OUT_CS0, LTQ_EBU_NAND_CON); ++ ++ ltq_w32(NAND_WRITE_CMD_RESET, ((u32*)(NAND_BASE_ADDRESS | NAND_WRITE_CMD))); ++ while((ltq_ebu_r32(LTQ_EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0); ++ ++ return 0; ++} ++ ++static struct platform_nand_data falcon_flash_nand_data = { ++ .chip = { ++ .nr_chips = 1, ++ .chip_delay = 30, ++ .part_probe_types = part_probes, ++ }, ++ .ctrl = { ++ .probe = xway_nand_probe, ++ .cmd_ctrl = xway_cmd_ctrl, ++ .dev_ready = xway_dev_ready, ++ .select_chip = xway_select_chip, ++ .read_byte = ltq_nand_read_byte, ++ } ++}; ++ ++static struct resource ltq_nand_res = ++ MEM_RES("nand", 0x14000000, 0x3ffffff); ++ ++static struct platform_device ltq_flash_nand = { ++ .name = "gen_nand", ++ .id = -1, ++ .num_resources = 1, ++ .resource = <q_nand_res, ++ .dev = { ++ .platform_data = &falcon_flash_nand_data, ++ }, ++}; ++ ++void __init ++xway_register_nand(void) ++{ ++ platform_device_register(<q_flash_nand); ++} +--- a/drivers/mtd/nand/plat_nand.c ++++ b/drivers/mtd/nand/plat_nand.c +@@ -77,6 +77,7 @@ static int __devinit plat_nand_probe(str + data->chip.select_chip = pdata->ctrl.select_chip; + data->chip.write_buf = pdata->ctrl.write_buf; + data->chip.read_buf = pdata->ctrl.read_buf; ++ data->chip.read_byte = pdata->ctrl.read_byte; + data->chip.chip_delay = pdata->chip.chip_delay; + data->chip.options |= pdata->chip.options; + +--- a/include/linux/mtd/nand.h ++++ b/include/linux/mtd/nand.h +@@ -657,6 +657,7 @@ struct platform_nand_ctrl { + void (*cmd_ctrl)(struct mtd_info *mtd, int dat, unsigned int ctrl); + void (*write_buf)(struct mtd_info *mtd, const uint8_t *buf, int len); + void (*read_buf)(struct mtd_info *mtd, uint8_t *buf, int len); ++ unsigned char (*read_byte)(struct mtd_info *mtd); + void *priv; + }; + diff --git a/target/linux/lantiq/patches/0017-MIPS-lantiq-adds-GPTU-driver.patch b/target/linux/lantiq/patches/0017-MIPS-lantiq-adds-GPTU-driver.patch new file mode 100644 index 0000000000..4b7c7b5488 --- /dev/null +++ b/target/linux/lantiq/patches/0017-MIPS-lantiq-adds-GPTU-driver.patch @@ -0,0 +1,1012 @@ +From 45dbb232686978816e8148753e12f27caa2b2eb3 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 17:16:38 +0200 +Subject: [PATCH 17/24] MIPS: lantiq: adds GPTU driver + +--- + arch/mips/include/asm/mach-lantiq/lantiq_timer.h | 155 ++++ + arch/mips/lantiq/xway/Makefile | 2 +- + arch/mips/lantiq/xway/timer.c | 830 ++++++++++++++++++++++ + 3 files changed, 986 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/lantiq_timer.h + create mode 100644 arch/mips/lantiq/xway/timer.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/lantiq_timer.h +@@ -0,0 +1,155 @@ ++#ifndef __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++#define __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ ++ ++ ++/****************************************************************************** ++ Copyright (c) 2002, Infineon Technologies. All rights reserved. ++ ++ No Warranty ++ Because the program is licensed free of charge, there is no warranty for ++ the program, to the extent permitted by applicable law. Except when ++ otherwise stated in writing the copyright holders and/or other parties ++ provide the program "as is" without warranty of any kind, either ++ expressed or implied, including, but not limited to, the implied ++ warranties of merchantability and fitness for a particular purpose. The ++ entire risk as to the quality and performance of the program is with ++ you. should the program prove defective, you assume the cost of all ++ necessary servicing, repair or correction. ++ ++ In no event unless required by applicable law or agreed to in writing ++ will any copyright holder, or any other party who may modify and/or ++ redistribute the program as permitted above, be liable to you for ++ damages, including any general, special, incidental or consequential ++ damages arising out of the use or inability to use the program ++ (including but not limited to loss of data or data being rendered ++ inaccurate or losses sustained by you or third parties or a failure of ++ the program to operate with any other programs), even if such holder or ++ other party has been advised of the possibility of such damages. ++******************************************************************************/ ++ ++ ++/* ++ * #################################### ++ * Definition ++ * #################################### ++ */ ++ ++/* ++ * Available Timer/Counter Index ++ */ ++#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) ++#define TIMER_ANY 0x00 ++#define TIMER1A TIMER(1, 0) ++#define TIMER1B TIMER(1, 1) ++#define TIMER2A TIMER(2, 0) ++#define TIMER2B TIMER(2, 1) ++#define TIMER3A TIMER(3, 0) ++#define TIMER3B TIMER(3, 1) ++ ++/* ++ * Flag of Timer/Counter ++ * These flags specify the way in which timer is configured. ++ */ ++/* Bit size of timer/counter. */ ++#define TIMER_FLAG_16BIT 0x0000 ++#define TIMER_FLAG_32BIT 0x0001 ++/* Switch between timer and counter. */ ++#define TIMER_FLAG_TIMER 0x0000 ++#define TIMER_FLAG_COUNTER 0x0002 ++/* Stop or continue when overflowing/underflowing. */ ++#define TIMER_FLAG_ONCE 0x0000 ++#define TIMER_FLAG_CYCLIC 0x0004 ++/* Count up or counter down. */ ++#define TIMER_FLAG_UP 0x0000 ++#define TIMER_FLAG_DOWN 0x0008 ++/* Count on specific level or edge. */ ++#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 ++#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 ++#define TIMER_FLAG_RISE_EDGE 0x0010 ++#define TIMER_FLAG_FALL_EDGE 0x0020 ++#define TIMER_FLAG_ANY_EDGE 0x0030 ++/* Signal is syncronous to module clock or not. */ ++#define TIMER_FLAG_UNSYNC 0x0000 ++#define TIMER_FLAG_SYNC 0x0080 ++/* Different interrupt handle type. */ ++#define TIMER_FLAG_NO_HANDLE 0x0000 ++#if defined(__KERNEL__) ++ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 ++#endif // defined(__KERNEL__) ++#define TIMER_FLAG_SIGNAL 0x0300 ++/* Internal clock source or external clock source */ ++#define TIMER_FLAG_INT_SRC 0x0000 ++#define TIMER_FLAG_EXT_SRC 0x1000 ++ ++ ++/* ++ * ioctl Command ++ */ ++#define GPTU_REQUEST_TIMER 0x01 /* General method to setup timer/counter. */ ++#define GPTU_FREE_TIMER 0x02 /* Free timer/counter. */ ++#define GPTU_START_TIMER 0x03 /* Start or resume timer/counter. */ ++#define GPTU_STOP_TIMER 0x04 /* Suspend timer/counter. */ ++#define GPTU_GET_COUNT_VALUE 0x05 /* Get current count value. */ ++#define GPTU_CALCULATE_DIVIDER 0x06 /* Calculate timer divider from given freq.*/ ++#define GPTU_SET_TIMER 0x07 /* Simplified method to setup timer. */ ++#define GPTU_SET_COUNTER 0x08 /* Simplified method to setup counter. */ ++ ++/* ++ * Data Type Used to Call ioctl ++ */ ++struct gptu_ioctl_param { ++ unsigned int timer; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field is ID of expected * ++ * timer/counter. If it's zero, a timer/counter would * ++ * be dynamically allocated and ID would be stored in * ++ * this field. * ++ * In command GPTU_GET_COUNT_VALUE, this field is * ++ * ignored. * ++ * In other command, this field is ID of timer/counter * ++ * allocated. */ ++ unsigned int flag; /* In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and * ++ * GPTU_SET_COUNTER, this field contains flags to * ++ * specify how to configure timer/counter. * ++ * In command GPTU_START_TIMER, zero indicate start * ++ * and non-zero indicate resume timer/counter. * ++ * In other command, this field is ignored. */ ++ unsigned long value; /* In command GPTU_REQUEST_TIMER, this field contains * ++ * init/reload value. * ++ * In command GPTU_SET_TIMER, this field contains * ++ * frequency (0.001Hz) of timer. * ++ * In command GPTU_GET_COUNT_VALUE, current count * ++ * value would be stored in this field. * ++ * In command GPTU_CALCULATE_DIVIDER, this field * ++ * contains frequency wanted, and after calculation, * ++ * divider would be stored in this field to overwrite * ++ * the frequency. * ++ * In other command, this field is ignored. */ ++ int pid; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains process * ++ * ID to which signal would be sent. * ++ * In other command, this field is ignored. */ ++ int sig; /* In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, * ++ * if signal is required, this field contains signal * ++ * number which would be sent. * ++ * In other command, this field is ignored. */ ++}; ++ ++/* ++ * #################################### ++ * Data Type ++ * #################################### ++ */ ++typedef void (*timer_callback)(unsigned long arg); ++ ++extern int lq_request_timer(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); ++extern int lq_free_timer(unsigned int); ++extern int lq_start_timer(unsigned int, int); ++extern int lq_stop_timer(unsigned int); ++extern int lq_reset_counter_flags(u32 timer, u32 flags); ++extern int lq_get_count_value(unsigned int, unsigned long *); ++extern u32 lq_cal_divider(unsigned long); ++extern int lq_set_timer(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); ++extern int lq_set_counter(unsigned int timer, unsigned int flag, ++ u32 reload, unsigned long arg1, unsigned long arg2); ++ ++#endif /* __DANUBE_GPTU_DEV_H__2005_07_26__10_19__ */ +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,4 +1,4 @@ +-obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o ++obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o + + obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o + obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/timer.c +@@ -0,0 +1,830 @@ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/version.h> ++#include <linux/types.h> ++#include <linux/fs.h> ++#include <linux/miscdevice.h> ++#include <linux/init.h> ++#include <linux/uaccess.h> ++#include <linux/unistd.h> ++#include <linux/errno.h> ++#include <linux/interrupt.h> ++#include <linux/sched.h> ++ ++#include <asm/irq.h> ++#include <asm/div64.h> ++ ++#include <lantiq_soc.h> ++#include <lantiq_irq.h> ++#include <lantiq_timer.h> ++ ++#define MAX_NUM_OF_32BIT_TIMER_BLOCKS 6 ++ ++#ifdef TIMER1A ++#define FIRST_TIMER TIMER1A ++#else ++#define FIRST_TIMER 2 ++#endif ++ ++/* ++ * GPTC divider is set or not. ++ */ ++#define GPTU_CLC_RMC_IS_SET 0 ++ ++/* ++ * Timer Interrupt (IRQ) ++ */ ++/* Must be adjusted when ICU driver is available */ ++#define TIMER_INTERRUPT (INT_NUM_IM3_IRL0 + 22) ++ ++/* ++ * Bits Operation ++ */ ++#define GET_BITS(x, msb, lsb) \ ++ (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) ++#define SET_BITS(x, msb, lsb, value) \ ++ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | \ ++ (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) ++ ++/* ++ * GPTU Register Mapping ++ */ ++#define LQ_GPTU (KSEG1 + 0x1E100A00) ++#define LQ_GPTU_CLC ((volatile u32 *)(LQ_GPTU + 0x0000)) ++#define LQ_GPTU_ID ((volatile u32 *)(LQ_GPTU + 0x0008)) ++#define LQ_GPTU_CON(n, X) ((volatile u32 *)(LQ_GPTU + 0x0010 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RUN(n, X) ((volatile u32 *)(LQ_GPTU + 0x0018 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_RELOAD(n, X) ((volatile u32 *)(LQ_GPTU + 0x0020 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_COUNT(n, X) ((volatile u32 *)(LQ_GPTU + 0x0028 + ((X) * 4) + ((n) - 1) * 0x0020)) /* X must be either A or B */ ++#define LQ_GPTU_IRNEN ((volatile u32 *)(LQ_GPTU + 0x00F4)) ++#define LQ_GPTU_IRNICR ((volatile u32 *)(LQ_GPTU + 0x00F8)) ++#define LQ_GPTU_IRNCR ((volatile u32 *)(LQ_GPTU + 0x00FC)) ++ ++/* ++ * Clock Control Register ++ */ ++#define GPTU_CLC_SMC GET_BITS(*LQ_GPTU_CLC, 23, 16) ++#define GPTU_CLC_RMC GET_BITS(*LQ_GPTU_CLC, 15, 8) ++#define GPTU_CLC_FSOE (*LQ_GPTU_CLC & (1 << 5)) ++#define GPTU_CLC_EDIS (*LQ_GPTU_CLC & (1 << 3)) ++#define GPTU_CLC_SPEN (*LQ_GPTU_CLC & (1 << 2)) ++#define GPTU_CLC_DISS (*LQ_GPTU_CLC & (1 << 1)) ++#define GPTU_CLC_DISR (*LQ_GPTU_CLC & (1 << 0)) ++ ++#define GPTU_CLC_SMC_SET(value) SET_BITS(0, 23, 16, (value)) ++#define GPTU_CLC_RMC_SET(value) SET_BITS(0, 15, 8, (value)) ++#define GPTU_CLC_FSOE_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CLC_SBWE_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CLC_EDIS_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CLC_SPEN_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CLC_DISR_SET(value) ((value) ? (1 << 0) : 0) ++ ++/* ++ * ID Register ++ */ ++#define GPTU_ID_ID GET_BITS(*LQ_GPTU_ID, 15, 8) ++#define GPTU_ID_CFG GET_BITS(*LQ_GPTU_ID, 7, 5) ++#define GPTU_ID_REV GET_BITS(*LQ_GPTU_ID, 4, 0) ++ ++/* ++ * Control Register of Timer/Counter nX ++ * n is the index of block (1 based index) ++ * X is either A or B ++ */ ++#define GPTU_CON_SRC_EG(n, X) (*LQ_GPTU_CON(n, X) & (1 << 10)) ++#define GPTU_CON_SRC_EXT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 9)) ++#define GPTU_CON_SYNC(n, X) (*LQ_GPTU_CON(n, X) & (1 << 8)) ++#define GPTU_CON_EDGE(n, X) GET_BITS(*LQ_GPTU_CON(n, X), 7, 6) ++#define GPTU_CON_INV(n, X) (*LQ_GPTU_CON(n, X) & (1 << 5)) ++#define GPTU_CON_EXT(n, X) (*LQ_GPTU_CON(n, A) & (1 << 4)) /* Timer/Counter B does not have this bit */ ++#define GPTU_CON_STP(n, X) (*LQ_GPTU_CON(n, X) & (1 << 3)) ++#define GPTU_CON_CNT(n, X) (*LQ_GPTU_CON(n, X) & (1 << 2)) ++#define GPTU_CON_DIR(n, X) (*LQ_GPTU_CON(n, X) & (1 << 1)) ++#define GPTU_CON_EN(n, X) (*LQ_GPTU_CON(n, X) & (1 << 0)) ++ ++#define GPTU_CON_SRC_EG_SET(value) ((value) ? 0 : (1 << 10)) ++#define GPTU_CON_SRC_EXT_SET(value) ((value) ? (1 << 9) : 0) ++#define GPTU_CON_SYNC_SET(value) ((value) ? (1 << 8) : 0) ++#define GPTU_CON_EDGE_SET(value) SET_BITS(0, 7, 6, (value)) ++#define GPTU_CON_INV_SET(value) ((value) ? (1 << 5) : 0) ++#define GPTU_CON_EXT_SET(value) ((value) ? (1 << 4) : 0) ++#define GPTU_CON_STP_SET(value) ((value) ? (1 << 3) : 0) ++#define GPTU_CON_CNT_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_CON_DIR_SET(value) ((value) ? (1 << 1) : 0) ++ ++#define GPTU_RUN_RL_SET(value) ((value) ? (1 << 2) : 0) ++#define GPTU_RUN_CEN_SET(value) ((value) ? (1 << 1) : 0) ++#define GPTU_RUN_SEN_SET(value) ((value) ? (1 << 0) : 0) ++ ++#define GPTU_IRNEN_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++#define GPTU_IRNCR_TC_SET(n, X, value) ((value) ? (1 << (((n) - 1) * 2 + (X))) : 0) ++ ++#define TIMER_FLAG_MASK_SIZE(x) (x & 0x0001) ++#define TIMER_FLAG_MASK_TYPE(x) (x & 0x0002) ++#define TIMER_FLAG_MASK_STOP(x) (x & 0x0004) ++#define TIMER_FLAG_MASK_DIR(x) (x & 0x0008) ++#define TIMER_FLAG_NONE_EDGE 0x0000 ++#define TIMER_FLAG_MASK_EDGE(x) (x & 0x0030) ++#define TIMER_FLAG_REAL 0x0000 ++#define TIMER_FLAG_INVERT 0x0040 ++#define TIMER_FLAG_MASK_INVERT(x) (x & 0x0040) ++#define TIMER_FLAG_MASK_TRIGGER(x) (x & 0x0070) ++#define TIMER_FLAG_MASK_SYNC(x) (x & 0x0080) ++#define TIMER_FLAG_CALLBACK_IN_HB 0x0200 ++#define TIMER_FLAG_MASK_HANDLE(x) (x & 0x0300) ++#define TIMER_FLAG_MASK_SRC(x) (x & 0x1000) ++ ++struct timer_dev_timer { ++ unsigned int f_irq_on; ++ unsigned int irq; ++ unsigned int flag; ++ unsigned long arg1; ++ unsigned long arg2; ++}; ++ ++struct timer_dev { ++ struct mutex gptu_mutex; ++ unsigned int number_of_timers; ++ unsigned int occupation; ++ unsigned int f_gptu_on; ++ struct timer_dev_timer timer[MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2]; ++}; ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi); ++ ++static long gptu_ioctl(struct file *, unsigned int, unsigned long); ++static int gptu_open(struct inode *, struct file *); ++static int gptu_release(struct inode *, struct file *); ++ ++static struct file_operations gptu_fops = { ++ .owner = THIS_MODULE, ++ .unlocked_ioctl = gptu_ioctl, ++ .open = gptu_open, ++ .release = gptu_release ++}; ++ ++static struct miscdevice gptu_miscdev = { ++ .minor = MISC_DYNAMIC_MINOR, ++ .name = "gptu", ++ .fops = &gptu_fops, ++}; ++ ++static struct timer_dev timer_dev; ++ ++static irqreturn_t timer_irq_handler(int irq, void *p) ++{ ++ unsigned int timer; ++ unsigned int flag; ++ struct timer_dev_timer *dev_timer = (struct timer_dev_timer *)p; ++ ++ timer = irq - TIMER_INTERRUPT; ++ if (timer < timer_dev.number_of_timers ++ && dev_timer == &timer_dev.timer[timer]) { ++ /* Clear interrupt. */ ++ ltq_w32(1 << timer, LQ_GPTU_IRNCR); ++ ++ /* Call user hanler or signal. */ ++ flag = dev_timer->flag; ++ if (!(timer & 0x01) ++ || TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ /* 16-bit timer or timer A of 32-bit timer */ ++ switch (TIMER_FLAG_MASK_HANDLE(flag)) { ++ case TIMER_FLAG_CALLBACK_IN_IRQ: ++ case TIMER_FLAG_CALLBACK_IN_HB: ++ if (dev_timer->arg1) ++ (*(timer_callback)dev_timer->arg1)(dev_timer->arg2); ++ break; ++ case TIMER_FLAG_SIGNAL: ++ send_sig((int)dev_timer->arg2, (struct task_struct *)dev_timer->arg1, 0); ++ break; ++ } ++ } ++ } ++ return IRQ_HANDLED; ++} ++ ++static inline void lq_enable_gptu(void) ++{ ++ ltq_pmu_enable(PMU_GPT); ++ ++ /* Set divider as 1, disable write protection for SPEN, enable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x01) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(1) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(0); ++} ++ ++static inline void lq_disable_gptu(void) ++{ ++ ltq_w32(0x00, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ /* Set divider as 0, enable write protection for SPEN, disable module. */ ++ *LQ_GPTU_CLC = ++ GPTU_CLC_SMC_SET(0x00) | ++ GPTU_CLC_RMC_SET(0x00) | ++ GPTU_CLC_FSOE_SET(0) | ++ GPTU_CLC_SBWE_SET(0) | ++ GPTU_CLC_EDIS_SET(0) | ++ GPTU_CLC_SPEN_SET(0) | ++ GPTU_CLC_DISR_SET(1); ++ ++ ltq_pmu_disable(PMU_GPT); ++} ++ ++int lq_request_timer(unsigned int timer, unsigned int flag, ++ unsigned long value, unsigned long arg1, unsigned long arg2) ++{ ++ int ret = 0; ++ unsigned int con_reg, irnen_reg; ++ int n, X; ++ ++ if (timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ printk(KERN_INFO "request_timer(%d, 0x%08X, %lu)...", ++ timer, flag, value); ++ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) ++ value &= 0xFFFF; ++ else ++ timer &= ~0x01; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ /* ++ * Allocate timer. ++ */ ++ if (timer < FIRST_TIMER) { ++ unsigned int mask; ++ unsigned int shift; ++ /* This takes care of TIMER1B which is the only choice for Voice TAPI system */ ++ unsigned int offset = TIMER2A; ++ ++ /* ++ * Pick up a free timer. ++ */ ++ if (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT) { ++ mask = 1 << offset; ++ shift = 1; ++ } else { ++ mask = 3 << offset; ++ shift = 2; ++ } ++ for (timer = offset; ++ timer < offset + timer_dev.number_of_timers; ++ timer += shift, mask <<= shift) ++ if (!(timer_dev.occupation & mask)) { ++ timer_dev.occupation |= mask; ++ break; ++ } ++ if (timer >= offset + timer_dev.number_of_timers) { ++ printk("failed![%d]\n", __LINE__); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } else ++ ret = timer; ++ } else { ++ register unsigned int mask; ++ ++ /* ++ * Check if the requested timer is free. ++ */ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if ((timer_dev.occupation & mask)) { ++ printk("failed![%d] mask %#x, timer_dev.occupation %#x\n", ++ __LINE__, mask, timer_dev.occupation); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EBUSY; ++ } else { ++ timer_dev.occupation |= mask; ++ ret = 0; ++ } ++ } ++ ++ /* ++ * Prepare control register value. ++ */ ++ switch (TIMER_FLAG_MASK_EDGE(flag)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flag) == TIMER_FLAG_TIMER) ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : ++ GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= ++ TIMER_FLAG_MASK_SRC(flag) == ++ TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : ++ GPTU_CON_SRC_EG_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_SYNC(flag) == ++ TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : ++ GPTU_CON_SYNC_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_INVERT(flag) == ++ TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : ++ GPTU_CON_EXT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_STOP(flag) == ++ TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= ++ TIMER_FLAG_MASK_TYPE(flag) == ++ TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : ++ GPTU_CON_CNT_SET(1); ++ con_reg |= ++ TIMER_FLAG_MASK_DIR(flag) == ++ TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ /* ++ * Fill up running data. ++ */ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flag; ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = arg1; ++ timer_dev.timer[timer - FIRST_TIMER].arg2 = arg2; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flag; ++ ++ /* ++ * Enable GPTU module. ++ */ ++ if (!timer_dev.f_gptu_on) { ++ lq_enable_gptu(); ++ timer_dev.f_gptu_on = 1; ++ } ++ ++ /* ++ * Enable IRQ. ++ */ ++ if (TIMER_FLAG_MASK_HANDLE(flag) != TIMER_FLAG_NO_HANDLE) { ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL) ++ timer_dev.timer[timer - FIRST_TIMER].arg1 = ++ (unsigned long) find_task_by_vpid((int) arg1); ++ ++ irnen_reg = 1 << (timer - FIRST_TIMER); ++ ++ if (TIMER_FLAG_MASK_HANDLE(flag) == TIMER_FLAG_SIGNAL ++ || (TIMER_FLAG_MASK_HANDLE(flag) == ++ TIMER_FLAG_CALLBACK_IN_IRQ ++ && timer_dev.timer[timer - FIRST_TIMER].arg1)) { ++ enable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 1; ++ } ++ } else ++ irnen_reg = 0; ++ ++ /* ++ * Write config register, reload value and enable interrupt. ++ */ ++ n = timer >> 1; ++ X = timer & 0x01; ++ *LQ_GPTU_CON(n, X) = con_reg; ++ *LQ_GPTU_RELOAD(n, X) = value; ++ /* printk("reload value = %d\n", (u32)value); */ ++ *LQ_GPTU_IRNEN |= irnen_reg; ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ printk("successful!\n"); ++ return ret; ++} ++EXPORT_SYMBOL(lq_request_timer); ++ ++int lq_free_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ if (GPTU_CON_EN(n, X)) ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ *LQ_GPTU_IRNEN &= ~GPTU_IRNEN_TC_SET(n, X, 1); ++ *LQ_GPTU_IRNCR |= GPTU_IRNCR_TC_SET(n, X, 1); ++ ++ if (timer_dev.timer[timer - FIRST_TIMER].f_irq_on) { ++ disable_irq(timer_dev.timer[timer - FIRST_TIMER].irq); ++ timer_dev.timer[timer - FIRST_TIMER].f_irq_on = 0; ++ } ++ ++ timer_dev.occupation &= ~mask; ++ if (!timer_dev.occupation && timer_dev.f_gptu_on) { ++ lq_disable_gptu(); ++ timer_dev.f_gptu_on = 0; ++ } ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_free_timer); ++ ++int lq_start_timer(unsigned int timer, int is_resume) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == ++ TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_RL_SET(!is_resume) | GPTU_RUN_SEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_start_timer); ++ ++int lq_stop_timer(unsigned int timer) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_RUN(n, X) = GPTU_RUN_CEN_SET(1); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_stop_timer); ++ ++int lq_reset_counter_flags(u32 timer, u32 flags) ++{ ++ unsigned int oflag; ++ unsigned int mask, con_reg; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ oflag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(oflag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(oflag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ switch (TIMER_FLAG_MASK_EDGE(flags)) { ++ default: ++ case TIMER_FLAG_NONE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x00); ++ break; ++ case TIMER_FLAG_RISE_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x01); ++ break; ++ case TIMER_FLAG_FALL_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x02); ++ break; ++ case TIMER_FLAG_ANY_EDGE: ++ con_reg = GPTU_CON_EDGE_SET(0x03); ++ break; ++ } ++ if (TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER) ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EXT_SET(1) : GPTU_CON_SRC_EXT_SET(0); ++ else ++ con_reg |= TIMER_FLAG_MASK_SRC(flags) == TIMER_FLAG_EXT_SRC ? GPTU_CON_SRC_EG_SET(1) : GPTU_CON_SRC_EG_SET(0); ++ con_reg |= TIMER_FLAG_MASK_SYNC(flags) == TIMER_FLAG_UNSYNC ? GPTU_CON_SYNC_SET(0) : GPTU_CON_SYNC_SET(1); ++ con_reg |= TIMER_FLAG_MASK_INVERT(flags) == TIMER_FLAG_REAL ? GPTU_CON_INV_SET(0) : GPTU_CON_INV_SET(1); ++ con_reg |= TIMER_FLAG_MASK_SIZE(flags) == TIMER_FLAG_16BIT ? GPTU_CON_EXT_SET(0) : GPTU_CON_EXT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_STOP(flags) == TIMER_FLAG_ONCE ? GPTU_CON_STP_SET(1) : GPTU_CON_STP_SET(0); ++ con_reg |= TIMER_FLAG_MASK_TYPE(flags) == TIMER_FLAG_TIMER ? GPTU_CON_CNT_SET(0) : GPTU_CON_CNT_SET(1); ++ con_reg |= TIMER_FLAG_MASK_DIR(flags) == TIMER_FLAG_UP ? GPTU_CON_DIR_SET(1) : GPTU_CON_DIR_SET(0); ++ ++ timer_dev.timer[timer - FIRST_TIMER].flag = flags; ++ if (TIMER_FLAG_MASK_SIZE(flags) != TIMER_FLAG_16BIT) ++ timer_dev.timer[timer - FIRST_TIMER + 1].flag = flags; ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *LQ_GPTU_CON(n, X) = con_reg; ++ smp_wmb(); ++ printk(KERN_INFO "[%s]: counter%d oflags %#x, nflags %#x, GPTU_CON %#x\n", __func__, timer, oflag, flags, *LQ_GPTU_CON(n, X)); ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return 0; ++} ++EXPORT_SYMBOL(lq_reset_counter_flags); ++ ++int lq_get_count_value(unsigned int timer, unsigned long *value) ++{ ++ unsigned int flag; ++ unsigned int mask; ++ int n, X; ++ ++ if (!timer_dev.f_gptu_on) ++ return -EINVAL; ++ ++ if (timer < FIRST_TIMER ++ || timer >= FIRST_TIMER + timer_dev.number_of_timers) ++ return -EINVAL; ++ ++ mutex_lock(&timer_dev.gptu_mutex); ++ ++ flag = timer_dev.timer[timer - FIRST_TIMER].flag; ++ if (TIMER_FLAG_MASK_SIZE(flag) != TIMER_FLAG_16BIT) ++ timer &= ~0x01; ++ ++ mask = (TIMER_FLAG_MASK_SIZE(flag) == TIMER_FLAG_16BIT ? 1 : 3) << timer; ++ if (((timer_dev.occupation & mask) ^ mask)) { ++ mutex_unlock(&timer_dev.gptu_mutex); ++ return -EINVAL; ++ } ++ ++ n = timer >> 1; ++ X = timer & 0x01; ++ ++ *value = *LQ_GPTU_COUNT(n, X); ++ ++ mutex_unlock(&timer_dev.gptu_mutex); ++ ++ return 0; ++} ++EXPORT_SYMBOL(lq_get_count_value); ++ ++u32 lq_cal_divider(unsigned long freq) ++{ ++ u64 module_freq, fpi = ltq_get_fpi_bus_clock(2); ++ u32 clock_divider = 1; ++ module_freq = fpi * 1000; ++ do_div(module_freq, clock_divider * freq); ++ return module_freq; ++} ++EXPORT_SYMBOL(lq_cal_divider); ++ ++int lq_set_timer(unsigned int timer, unsigned int freq, int is_cyclic, ++ int is_ext_src, unsigned int handle_flag, unsigned long arg1, ++ unsigned long arg2) ++{ ++ unsigned long divider; ++ unsigned int flag; ++ ++ divider = lq_cal_divider(freq); ++ if (divider == 0) ++ return -EINVAL; ++ flag = ((divider & ~0xFFFF) ? TIMER_FLAG_32BIT : TIMER_FLAG_16BIT) ++ | (is_cyclic ? TIMER_FLAG_CYCLIC : TIMER_FLAG_ONCE) ++ | (is_ext_src ? TIMER_FLAG_EXT_SRC : TIMER_FLAG_INT_SRC) ++ | TIMER_FLAG_TIMER | TIMER_FLAG_DOWN ++ | TIMER_FLAG_MASK_HANDLE(handle_flag); ++ ++ printk(KERN_INFO "lq_set_timer(%d, %d), divider = %lu\n", ++ timer, freq, divider); ++ return lq_request_timer(timer, flag, divider, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_timer); ++ ++int lq_set_counter(unsigned int timer, unsigned int flag, u32 reload, ++ unsigned long arg1, unsigned long arg2) ++{ ++ printk(KERN_INFO "lq_set_counter(%d, %#x, %d)\n", timer, flag, reload); ++ return lq_request_timer(timer, flag, reload, arg1, arg2); ++} ++EXPORT_SYMBOL(lq_set_counter); ++ ++static long gptu_ioctl(struct file *file, unsigned int cmd, ++ unsigned long arg) ++{ ++ int ret; ++ struct gptu_ioctl_param param; ++ ++ if (!access_ok(VERIFY_READ, arg, sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ copy_from_user(¶m, (void *) arg, sizeof(param)); ++ ++ if ((((cmd == GPTU_REQUEST_TIMER || cmd == GPTU_SET_TIMER ++ || GPTU_SET_COUNTER) && param.timer < 2) ++ || cmd == GPTU_GET_COUNT_VALUE || cmd == GPTU_CALCULATE_DIVIDER) ++ && !access_ok(VERIFY_WRITE, arg, ++ sizeof(struct gptu_ioctl_param))) ++ return -EFAULT; ++ ++ switch (cmd) { ++ case GPTU_REQUEST_TIMER: ++ ret = lq_request_timer(param.timer, param.flag, param.value, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_FREE_TIMER: ++ ret = lq_free_timer(param.timer); ++ break; ++ case GPTU_START_TIMER: ++ ret = lq_start_timer(param.timer, param.flag); ++ break; ++ case GPTU_STOP_TIMER: ++ ret = lq_stop_timer(param.timer); ++ break; ++ case GPTU_GET_COUNT_VALUE: ++ ret = lq_get_count_value(param.timer, ¶m.value); ++ if (!ret) ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ break; ++ case GPTU_CALCULATE_DIVIDER: ++ param.value = lq_cal_divider(param.value); ++ if (param.value == 0) ++ ret = -EINVAL; ++ else { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ value, ¶m.value, ++ sizeof(param.value)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_TIMER: ++ ret = lq_set_timer(param.timer, param.value, ++ TIMER_FLAG_MASK_STOP(param.flag) != ++ TIMER_FLAG_ONCE ? 1 : 0, ++ TIMER_FLAG_MASK_SRC(param.flag) == ++ TIMER_FLAG_EXT_SRC ? 1 : 0, ++ TIMER_FLAG_MASK_HANDLE(param.flag) == ++ TIMER_FLAG_SIGNAL ? TIMER_FLAG_SIGNAL : ++ TIMER_FLAG_NO_HANDLE, ++ (unsigned long) param.pid, ++ (unsigned long) param.sig); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ case GPTU_SET_COUNTER: ++ lq_set_counter(param.timer, param.flag, param.value, 0, 0); ++ if (ret > 0) { ++ copy_to_user(&((struct gptu_ioctl_param *) arg)-> ++ timer, &ret, sizeof(&ret)); ++ ret = 0; ++ } ++ break; ++ default: ++ ret = -ENOTTY; ++ } ++ ++ return ret; ++} ++ ++static int gptu_open(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++static int gptu_release(struct inode *inode, struct file *file) ++{ ++ return 0; ++} ++ ++int __init lq_gptu_init(void) ++{ ++ int ret; ++ unsigned int i; ++ ++ ltq_w32(0, LQ_GPTU_IRNEN); ++ ltq_w32(0xfff, LQ_GPTU_IRNCR); ++ ++ memset(&timer_dev, 0, sizeof(timer_dev)); ++ mutex_init(&timer_dev.gptu_mutex); ++ ++ lq_enable_gptu(); ++ timer_dev.number_of_timers = GPTU_ID_CFG * 2; ++ lq_disable_gptu(); ++ if (timer_dev.number_of_timers > MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2) ++ timer_dev.number_of_timers = MAX_NUM_OF_32BIT_TIMER_BLOCKS * 2; ++ printk(KERN_INFO "gptu: totally %d 16-bit timers/counters\n", timer_dev.number_of_timers); ++ ++ ret = misc_register(&gptu_miscdev); ++ if (ret) { ++ printk(KERN_ERR "gptu: can't misc_register, get error %d\n", -ret); ++ return ret; ++ } else { ++ printk(KERN_INFO "gptu: misc_register on minor %d\n", gptu_miscdev.minor); ++ } ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ ret = request_irq(TIMER_INTERRUPT + i, timer_irq_handler, IRQF_TIMER, gptu_miscdev.name, &timer_dev.timer[i]); ++ if (ret) { ++ for (; i >= 0; i--) ++ free_irq(TIMER_INTERRUPT + i, &timer_dev.timer[i]); ++ misc_deregister(&gptu_miscdev); ++ printk(KERN_ERR "gptu: failed in requesting irq (%d), get error %d\n", i, -ret); ++ return ret; ++ } else { ++ timer_dev.timer[i].irq = TIMER_INTERRUPT + i; ++ disable_irq(timer_dev.timer[i].irq); ++ printk(KERN_INFO "gptu: succeeded to request irq %d\n", timer_dev.timer[i].irq); ++ } ++ } ++ ++ return 0; ++} ++ ++void __exit lq_gptu_exit(void) ++{ ++ unsigned int i; ++ ++ for (i = 0; i < timer_dev.number_of_timers; i++) { ++ if (timer_dev.timer[i].f_irq_on) ++ disable_irq(timer_dev.timer[i].irq); ++ free_irq(timer_dev.timer[i].irq, &timer_dev.timer[i]); ++ } ++ lq_disable_gptu(); ++ misc_deregister(&gptu_miscdev); ++} ++ ++module_init(lq_gptu_init); ++module_exit(lq_gptu_exit); diff --git a/target/linux/lantiq/patches/0018-MIPS-lantiq-adds-dwc_otg.patch b/target/linux/lantiq/patches/0018-MIPS-lantiq-adds-dwc_otg.patch new file mode 100644 index 0000000000..ccb698b1f3 --- /dev/null +++ b/target/linux/lantiq/patches/0018-MIPS-lantiq-adds-dwc_otg.patch @@ -0,0 +1,15576 @@ +From ffd7924fcc69ff146d62f131d72ef18575bf0227 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Fri, 30 Sep 2011 14:37:36 +0200 +Subject: [PATCH 18/24] MIPS: lantiq: adds dwc_otg + +--- + drivers/usb/Kconfig | 2 + + drivers/usb/Makefile | 2 + + drivers/usb/core/hub.c | 4 +- + drivers/usb/dwc_otg/Kconfig | 37 + + drivers/usb/dwc_otg/Makefile | 39 + + drivers/usb/dwc_otg/dwc_otg_attr.c | 802 ++++++++ + drivers/usb/dwc_otg/dwc_otg_attr.h | 67 + + drivers/usb/dwc_otg/dwc_otg_cil.c | 3025 +++++++++++++++++++++++++++++++ + drivers/usb/dwc_otg/dwc_otg_cil.h | 911 ++++++++++ + drivers/usb/dwc_otg/dwc_otg_cil_ifx.h | 58 + + drivers/usb/dwc_otg/dwc_otg_cil_intr.c | 708 ++++++++ + drivers/usb/dwc_otg/dwc_otg_driver.c | 1274 +++++++++++++ + drivers/usb/dwc_otg/dwc_otg_driver.h | 84 + + drivers/usb/dwc_otg/dwc_otg_hcd.c | 2870 +++++++++++++++++++++++++++++ + drivers/usb/dwc_otg/dwc_otg_hcd.h | 676 +++++++ + drivers/usb/dwc_otg/dwc_otg_hcd_intr.c | 1841 +++++++++++++++++++ + drivers/usb/dwc_otg/dwc_otg_hcd_queue.c | 794 ++++++++ + drivers/usb/dwc_otg/dwc_otg_ifx.c | 100 + + drivers/usb/dwc_otg/dwc_otg_ifx.h | 85 + + drivers/usb/dwc_otg/dwc_otg_plat.h | 269 +++ + drivers/usb/dwc_otg/dwc_otg_regs.h | 1797 ++++++++++++++++++ + 21 files changed, 15443 insertions(+), 2 deletions(-) + create mode 100644 drivers/usb/dwc_otg/Kconfig + create mode 100644 drivers/usb/dwc_otg/Makefile + create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_attr.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_ifx.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_cil_intr.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_driver.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_intr.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_hcd_queue.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.c + create mode 100644 drivers/usb/dwc_otg/dwc_otg_ifx.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_plat.h + create mode 100644 drivers/usb/dwc_otg/dwc_otg_regs.h + +--- a/drivers/usb/Kconfig ++++ b/drivers/usb/Kconfig +@@ -116,6 +116,8 @@ source "drivers/usb/wusbcore/Kconfig" + + source "drivers/usb/host/Kconfig" + ++source "drivers/usb/dwc_otg/Kconfig" ++ + source "drivers/usb/musb/Kconfig" + + source "drivers/usb/renesas_usbhs/Kconfig" +--- a/drivers/usb/Makefile ++++ b/drivers/usb/Makefile +@@ -28,6 +28,8 @@ obj-$(CONFIG_USB_C67X00_HCD) += c67x00/ + + obj-$(CONFIG_USB_WUSB) += wusbcore/ + ++obj-$(CONFIG_DWC_OTG) += dwc_otg/ ++ + obj-$(CONFIG_USB_ACM) += class/ + obj-$(CONFIG_USB_PRINTER) += class/ + obj-$(CONFIG_USB_WDM) += class/ +--- a/drivers/usb/core/hub.c ++++ b/drivers/usb/core/hub.c +@@ -2885,11 +2885,11 @@ hub_port_init (struct usb_hub *hub, stru + udev->ttport = hdev->ttport; + } else if (udev->speed != USB_SPEED_HIGH + && hdev->speed == USB_SPEED_HIGH) { +- if (!hub->tt.hub) { ++/* if (!hub->tt.hub) { + dev_err(&udev->dev, "parent hub has no TT\n"); + retval = -EINVAL; + goto fail; +- } ++ }*/ + udev->tt = &hub->tt; + udev->ttport = port1; + } +--- /dev/null ++++ b/drivers/usb/dwc_otg/Kconfig +@@ -0,0 +1,37 @@ ++config DWC_OTG ++ tristate "Synopsis DWC_OTG support" ++ depends on USB ++ help ++ This driver supports Synopsis DWC_OTG IP core ++ embebbed on many SOCs (ralink, infineon, etc) ++ ++choice ++ prompt "USB Operation Mode" ++ depends on DWC_OTG ++ default DWC_OTG_HOST_ONLY ++ ++config DWC_OTG_HOST_ONLY ++ bool "HOST ONLY MODE" ++ depends on DWC_OTG ++ ++#config DWC_OTG_DEVICE_ONLY ++# bool "DEVICE ONLY MODE" ++# depends on DWC_OTG ++endchoice ++ ++choice ++ prompt "Platform" ++ depends on DWC_OTG ++ default DWC_OTG_LANTIQ ++ ++config DWC_OTG_LANTIQ ++ bool "Lantiq" ++ depends on LANTIQ ++ help ++ Danube USB Host Controller ++ platform support ++endchoice ++ ++config DWC_OTG_DEBUG ++ bool "Enable debug mode" ++ depends on DWC_OTG +--- /dev/null ++++ b/drivers/usb/dwc_otg/Makefile +@@ -0,0 +1,39 @@ ++# ++# Makefile for DWC_otg Highspeed USB controller driver ++# ++ ++ifeq ($(CONFIG_DWC_OTG_DEBUG),y) ++EXTRA_CFLAGS += -DDEBUG ++endif ++ ++# Use one of the following flags to compile the software in host-only or ++# device-only mode based on the configuration selected by the user ++ifeq ($(CONFIG_DWC_OTG_HOST_ONLY),y) ++ EXTRA_CFLAGS += -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY ++ EXTRA_CFLAGS += -DDWC_OTG_EN_ISOC -DDWC_EN_ISOC ++else ifeq ($(CONFIG_DWC_OTG_DEVICE_ONLY),y) ++ EXTRA_CFLAGS += -DDWC_OTG_DEVICE_ONLY ++else ++ EXTRA_CFLAGS += -DDWC_OTG_MODE ++endif ++ ++# EXTRA_CFLAGS += -DDWC_HS_ELECT_TST ++# EXTRA_CFLAGS += -DDWC_OTG_EXT_CHG_PUMP ++ ++ifeq ($(CONFIG_DWC_OTG_LANTIQ),y) ++ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_OTG_HOST_ONLY -DDWC_HOST_ONLY -D__KERNEL__ ++endif ++ifeq ($(CONFIG_DWC_OTG_LANTIQ),m) ++ EXTRA_CFLAGS += -Dlinux -D__LINUX__ -DDWC_OTG_IFX -DDWC_HOST_ONLY -DMODULE -D__KERNEL__ -DDEBUG ++endif ++ ++obj-$(CONFIG_DWC_OTG) := dwc_otg.o ++dwc_otg-objs := dwc_otg_hcd.o dwc_otg_hcd_intr.o dwc_otg_hcd_queue.o ++#dwc_otg-objs += dwc_otg_pcd.o dwc_otg_pcd_intr.o ++dwc_otg-objs += dwc_otg_attr.o ++dwc_otg-objs += dwc_otg_cil.o dwc_otg_cil_intr.o ++dwc_otg-objs += dwc_otg_ifx.o ++dwc_otg-objs += dwc_otg_driver.o ++ ++#obj-$(CONFIG_DWC_OTG_IFX) := dwc_otg_ifx.o ++#dwc_otg_ifx-objs := dwc_otg_ifx.o +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_attr.c +@@ -0,0 +1,802 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 537387 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. The Linux driver attributes ++ * feature will be used to provide the Linux Diagnostic ++ * Interface. These attributes are accessed through sysfs. ++ */ ++ ++/** @page "Linux Module Attributes" ++ * ++ * The Linux module attributes feature is used to provide the Linux ++ * Diagnostic Interface. These attributes are accessed through sysfs. ++ * The diagnostic interface will provide access to the controller for ++ * bringing up the hardware and testing. ++ ++ ++ The following table shows the attributes. ++ <table> ++ <tr> ++ <td><b> Name</b></td> ++ <td><b> Description</b></td> ++ <td><b> Access</b></td> ++ </tr> ++ ++ <tr> ++ <td> mode </td> ++ <td> Returns the current mode: 0 for device mode, 1 for host mode</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> hnpcapable </td> ++ <td> Gets or sets the "HNP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> srpcapable </td> ++ <td> Gets or sets the "SRP-capable" bit in the Core USB Configuraton Register. ++ Read returns the current value.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> hnp </td> ++ <td> Initiates the Host Negotiation Protocol. Read returns the status.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> srp </td> ++ <td> Initiates the Session Request Protocol. Read returns the status.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> buspower </td> ++ <td> Gets or sets the Power State of the bus (0 - Off or 1 - On)</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> bussuspend </td> ++ <td> Suspends the USB bus.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> busconnected </td> ++ <td> Gets the connection status of the bus</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> gotgctl </td> ++ <td> Gets or sets the Core Control Status Register.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> gusbcfg </td> ++ <td> Gets or sets the Core USB Configuration Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> grxfsiz </td> ++ <td> Gets or sets the Receive FIFO Size Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> gnptxfsiz </td> ++ <td> Gets or sets the non-periodic Transmit Size Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> gpvndctl </td> ++ <td> Gets or sets the PHY Vendor Control Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> ggpio </td> ++ <td> Gets the value in the lower 16-bits of the General Purpose IO Register ++ or sets the upper 16 bits.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> guid </td> ++ <td> Gets or sets the value of the User ID Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> gsnpsid </td> ++ <td> Gets the value of the Synopsys ID Regester</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> devspeed </td> ++ <td> Gets or sets the device speed setting in the DCFG register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> enumspeed </td> ++ <td> Gets the device enumeration Speed.</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> hptxfsiz </td> ++ <td> Gets the value of the Host Periodic Transmit FIFO</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> hprt0 </td> ++ <td> Gets or sets the value in the Host Port Control and Status Register</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> regoffset </td> ++ <td> Sets the register offset for the next Register Access</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> regvalue </td> ++ <td> Gets or sets the value of the register at the offset in the regoffset attribute.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> remote_wakeup </td> ++ <td> On read, shows the status of Remote Wakeup. On write, initiates a remote ++ wakeup of the host. When bit 0 is 1 and Remote Wakeup is enabled, the Remote ++ Wakeup signalling bit in the Device Control Register is set for 1 ++ milli-second.</td> ++ <td> Read/Write</td> ++ </tr> ++ ++ <tr> ++ <td> regdump </td> ++ <td> Dumps the contents of core registers.</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> hcddump </td> ++ <td> Dumps the current HCD state.</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> hcd_frrem </td> ++ <td> Shows the average value of the Frame Remaining ++ field in the Host Frame Number/Frame Remaining register when an SOF interrupt ++ occurs. This can be used to determine the average interrupt latency. Also ++ shows the average Frame Remaining value for start_transfer and the "a" and ++ "b" sample points. The "a" and "b" sample points may be used during debugging ++ bto determine how long it takes to execute a section of the HCD code.</td> ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> rd_reg_test </td> ++ <td> Displays the time required to read the GNPTXFSIZ register many times ++ (the output shows the number of times the register is read). ++ <td> Read</td> ++ </tr> ++ ++ <tr> ++ <td> wr_reg_test </td> ++ <td> Displays the time required to write the GNPTXFSIZ register many times ++ (the output shows the number of times the register is written). ++ <td> Read</td> ++ </tr> ++ ++ </table> ++ ++ Example usage: ++ To get the current mode: ++ cat /sys/devices/lm0/mode ++ ++ To power down the USB: ++ echo 0 > /sys/devices/lm0/buspower ++ */ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/errno.h> ++#include <linux/types.h> ++#include <linux/stat.h> /* permission constants */ ++ ++#include <asm/io.h> ++ ++#include "dwc_otg_plat.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_driver.h" ++// #include "dwc_otg_pcd.h" ++#include "dwc_otg_hcd.h" ++ ++// 20070316, winder added. ++#ifndef SZ_256K ++#define SZ_256K 0x00040000 ++#endif ++ ++/* ++ * MACROs for defining sysfs attribute ++ */ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ ++ uint32_t val; \ ++ val = dwc_read_reg32 (_addr_); \ ++ val = (val & (_mask_)) >> _shift_; \ ++ return sprintf (buf, "%s = 0x%x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ ++ uint32_t set = simple_strtoul(buf, NULL, 16); \ ++ uint32_t clear = set; \ ++ clear = ((~clear) << _shift_) & _mask_; \ ++ set = (set << _shift_) & _mask_; \ ++ dev_dbg(_dev, "Storing Address=0x%08x Set=0x%08x Clear=0x%08x\n", (uint32_t)_addr_, set, clear); \ ++ dwc_modify_reg32(_addr_, clear, set); \ ++ return count; \ ++} ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_STORE(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_BITFIELD_RO(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++DWC_OTG_DEVICE_ATTR_BITFIELD_SHOW(_otg_attr_name_,_addr_,_mask_,_shift_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++/* ++ * MACROs for defining sysfs attribute for 32-bit registers ++ */ ++#define DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ ++static ssize_t _otg_attr_name_##_show (struct device *_dev, struct device_attribute *attr, char *buf) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ ++ uint32_t val; \ ++ val = dwc_read_reg32 (_addr_); \ ++ return sprintf (buf, "%s = 0x%08x\n", _string_, val); \ ++} ++#define DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ ++static ssize_t _otg_attr_name_##_store (struct device *_dev, struct device_attribute *attr, const char *buf, size_t count) \ ++{ \ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev);\ ++ uint32_t val = simple_strtoul(buf, NULL, 16); \ ++ dev_dbg(_dev, "Storing Address=0x%08x Val=0x%08x\n", (uint32_t)_addr_, val); \ ++ dwc_write_reg32(_addr_, val); \ ++ return count; \ ++} ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RW(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_STORE(_otg_attr_name_,_addr_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0644,_otg_attr_name_##_show,_otg_attr_name_##_store); ++ ++#define DWC_OTG_DEVICE_ATTR_REG32_RO(_otg_attr_name_,_addr_,_string_) \ ++DWC_OTG_DEVICE_ATTR_REG_SHOW(_otg_attr_name_,_addr_,_string_) \ ++DEVICE_ATTR(_otg_attr_name_,0444,_otg_attr_name_##_show,NULL); ++ ++ ++/** @name Functions for Show/Store of Attributes */ ++/**@{*/ ++ ++/** ++ * Show the register offset of the Register Access. ++ */ ++static ssize_t regoffset_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ return snprintf(buf, sizeof("0xFFFFFFFF\n")+1,"0x%08x\n", otg_dev->reg_offset); ++} ++ ++/** ++ * Set the register offset for the next Register Access Read/Write ++ */ ++static ssize_t regoffset_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t offset = simple_strtoul(buf, NULL, 16); ++ //dev_dbg(_dev, "Offset=0x%08x\n", offset); ++ if (offset < SZ_256K ) { ++ otg_dev->reg_offset = offset; ++ } ++ else { ++ dev_err( _dev, "invalid offset\n" ); ++ } ++ ++ return count; ++} ++DEVICE_ATTR(regoffset, S_IRUGO|S_IWUSR, regoffset_show, regoffset_store); ++ ++/** ++ * Show the value of the register at the offset in the reg_offset ++ * attribute. ++ */ ++static ssize_t regvalue_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t val; ++ volatile uint32_t *addr; ++ ++ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ /* Calculate the address */ ++ addr = (uint32_t*)(otg_dev->reg_offset + ++ (uint8_t*)otg_dev->base); ++ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); ++ val = dwc_read_reg32( addr ); ++ return snprintf(buf, sizeof("Reg@0xFFFFFFFF = 0xFFFFFFFF\n")+1, ++ "Reg@0x%06x = 0x%08x\n", ++ otg_dev->reg_offset, val); ++ } ++ else { ++ dev_err(_dev, "Invalid offset (0x%0x)\n", ++ otg_dev->reg_offset); ++ return sprintf(buf, "invalid offset\n" ); ++ } ++} ++ ++/** ++ * Store the value in the register at the offset in the reg_offset ++ * attribute. ++ * ++ */ ++static ssize_t regvalue_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ volatile uint32_t * addr; ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ //dev_dbg(_dev, "Offset=0x%08x Val=0x%08x\n", otg_dev->reg_offset, val); ++ if (otg_dev->reg_offset != 0xFFFFFFFF && 0 != otg_dev->base) { ++ /* Calculate the address */ ++ addr = (uint32_t*)(otg_dev->reg_offset + ++ (uint8_t*)otg_dev->base); ++ //dev_dbg(_dev, "@0x%08x\n", (unsigned)addr); ++ dwc_write_reg32( addr, val ); ++ } ++ else { ++ dev_err(_dev, "Invalid Register Offset (0x%08x)\n", ++ otg_dev->reg_offset); ++ } ++ return count; ++} ++DEVICE_ATTR(regvalue, S_IRUGO|S_IWUSR, regvalue_show, regvalue_store); ++ ++/* ++ * Attributes ++ */ ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(mode,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<20),20,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(hnpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<9),9,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(srpcapable,&(otg_dev->core_if->core_global_regs->gusbcfg),(1<<8),8,"Mode"); ++ ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(buspower,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++//DWC_OTG_DEVICE_ATTR_BITFIELD_RW(bussuspend,&(otg_dev->core_if->core_global_regs->gotgctl),(1<<8),8,"Mode"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(busconnected,otg_dev->core_if->host_if->hprt0,0x01,0,"Bus Connected"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RW(gotgctl,&(otg_dev->core_if->core_global_regs->gotgctl),"GOTGCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gusbcfg,&(otg_dev->core_if->core_global_regs->gusbcfg),"GUSBCFG"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(grxfsiz,&(otg_dev->core_if->core_global_regs->grxfsiz),"GRXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gnptxfsiz,&(otg_dev->core_if->core_global_regs->gnptxfsiz),"GNPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(gpvndctl,&(otg_dev->core_if->core_global_regs->gpvndctl),"GPVNDCTL"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(ggpio,&(otg_dev->core_if->core_global_regs->ggpio),"GGPIO"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(guid,&(otg_dev->core_if->core_global_regs->guid),"GUID"); ++DWC_OTG_DEVICE_ATTR_REG32_RO(gsnpsid,&(otg_dev->core_if->core_global_regs->gsnpsid),"GSNPSID"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RW(devspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dcfg),0x3,0,"Device Speed"); ++DWC_OTG_DEVICE_ATTR_BITFIELD_RO(enumspeed,&(otg_dev->core_if->dev_if->dev_global_regs->dsts),0x6,1,"Device Enumeration Speed"); ++ ++DWC_OTG_DEVICE_ATTR_REG32_RO(hptxfsiz,&(otg_dev->core_if->core_global_regs->hptxfsiz),"HPTXFSIZ"); ++DWC_OTG_DEVICE_ATTR_REG32_RW(hprt0,otg_dev->core_if->host_if->hprt0,"HPRT0"); ++ ++ ++/** ++ * @todo Add code to initiate the HNP. ++ */ ++/** ++ * Show the HNP status bit ++ */ ++static ssize_t hnp_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ gotgctl_data_t val; ++ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); ++ return sprintf (buf, "HstNegScs = 0x%x\n", val.b.hstnegscs); ++} ++ ++/** ++ * Set the HNP Request bit ++ */ ++static ssize_t hnp_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ uint32_t *addr = (uint32_t *)&(otg_dev->core_if->core_global_regs->gotgctl); ++ gotgctl_data_t mem; ++ mem.d32 = dwc_read_reg32(addr); ++ mem.b.hnpreq = in; ++ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); ++ dwc_write_reg32(addr, mem.d32); ++ return count; ++} ++DEVICE_ATTR(hnp, 0644, hnp_show, hnp_store); ++ ++/** ++ * @todo Add code to initiate the SRP. ++ */ ++/** ++ * Show the SRP status bit ++ */ ++static ssize_t srp_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ gotgctl_data_t val; ++ val.d32 = dwc_read_reg32 (&(otg_dev->core_if->core_global_regs->gotgctl)); ++ return sprintf (buf, "SesReqScs = 0x%x\n", val.b.sesreqscs); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif ++} ++ ++/** ++ * Set the SRP Request bit ++ */ ++static ssize_t srp_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ dwc_otg_pcd_initiate_srp(otg_dev->pcd); ++#endif ++ return count; ++} ++DEVICE_ATTR(srp, 0644, srp_show, srp_store); ++ ++/** ++ * @todo Need to do more for power on/off? ++ */ ++/** ++ * Show the Bus Power status ++ */ ++static ssize_t buspower_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ hprt0_data_t val; ++ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); ++ return sprintf (buf, "Bus Power = 0x%x\n", val.b.prtpwr); ++} ++ ++ ++/** ++ * Set the Bus Power status ++ */ ++static ssize_t buspower_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t on = simple_strtoul(buf, NULL, 16); ++ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; ++ hprt0_data_t mem; ++ ++ mem.d32 = dwc_read_reg32(addr); ++ mem.b.prtpwr = on; ++ ++ //dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); ++ dwc_write_reg32(addr, mem.d32); ++ ++ return count; ++} ++DEVICE_ATTR(buspower, 0644, buspower_show, buspower_store); ++ ++/** ++ * @todo Need to do more for suspend? ++ */ ++/** ++ * Show the Bus Suspend status ++ */ ++static ssize_t bussuspend_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ hprt0_data_t val; ++ val.d32 = dwc_read_reg32 (otg_dev->core_if->host_if->hprt0); ++ return sprintf (buf, "Bus Suspend = 0x%x\n", val.b.prtsusp); ++} ++ ++/** ++ * Set the Bus Suspend status ++ */ ++static ssize_t bussuspend_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t in = simple_strtoul(buf, NULL, 16); ++ uint32_t *addr = (uint32_t *)otg_dev->core_if->host_if->hprt0; ++ hprt0_data_t mem; ++ mem.d32 = dwc_read_reg32(addr); ++ mem.b.prtsusp = in; ++ dev_dbg(_dev, "Storing Address=0x%08x Data=0x%08x\n", (uint32_t)addr, mem.d32); ++ dwc_write_reg32(addr, mem.d32); ++ return count; ++} ++DEVICE_ATTR(bussuspend, 0644, bussuspend_show, bussuspend_store); ++ ++/** ++ * Show the status of Remote Wakeup. ++ */ ++static ssize_t remote_wakeup_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_HOST_ONLY ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ dctl_data_t val; ++ val.d32 = dwc_read_reg32( &otg_dev->core_if->dev_if->dev_global_regs->dctl); ++ return sprintf( buf, "Remote Wakeup = %d Enabled = %d\n", ++ val.b.rmtwkupsig, otg_dev->pcd->remote_wakeup_enable); ++#else ++ return sprintf(buf, "Host Only Mode!\n"); ++#endif ++} ++ ++/** ++ * Initiate a remote wakeup of the host. The Device control register ++ * Remote Wakeup Signal bit is written if the PCD Remote wakeup enable ++ * flag is set. ++ * ++ */ ++static ssize_t remote_wakeup_store( struct device *_dev, struct device_attribute *attr, const char *buf, ++ size_t count ) ++{ ++#ifndef DWC_HOST_ONLY ++ uint32_t val = simple_strtoul(buf, NULL, 16); ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ if (val&1) { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 1); ++ } ++ else { ++ dwc_otg_pcd_remote_wakeup(otg_dev->pcd, 0); ++ } ++#endif ++ return count; ++} ++DEVICE_ATTR(remote_wakeup, S_IRUGO|S_IWUSR, remote_wakeup_show, ++ remote_wakeup_store); ++ ++/** ++ * Dump global registers and either host or device registers (depending on the ++ * current mode of the core). ++ */ ++static ssize_t regdump_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++#ifdef DEBUG ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ printk("%s otg_dev=0x%p\n", __FUNCTION__, otg_dev); ++ ++ dwc_otg_dump_global_registers( otg_dev->core_if); ++ if (dwc_otg_is_host_mode(otg_dev->core_if)) { ++ dwc_otg_dump_host_registers( otg_dev->core_if); ++ } else { ++ dwc_otg_dump_dev_registers( otg_dev->core_if); ++ } ++#endif ++ ++ return sprintf( buf, "Register Dump\n" ); ++} ++ ++DEVICE_ATTR(regdump, S_IRUGO|S_IWUSR, regdump_show, 0); ++ ++/** ++ * Dump the current hcd state. ++ */ ++static ssize_t hcddump_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ dwc_otg_hcd_dump_state(otg_dev->hcd); ++#endif ++ return sprintf( buf, "HCD Dump\n" ); ++} ++ ++DEVICE_ATTR(hcddump, S_IRUGO|S_IWUSR, hcddump_show, 0); ++ ++/** ++ * Dump the average frame remaining at SOF. This can be used to ++ * determine average interrupt latency. Frame remaining is also shown for ++ * start transfer and two additional sample points. ++ */ ++static ssize_t hcd_frrem_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++#ifndef DWC_DEVICE_ONLY ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ dwc_otg_hcd_dump_frrem(otg_dev->hcd); ++#endif ++ return sprintf( buf, "HCD Dump Frame Remaining\n" ); ++} ++ ++DEVICE_ATTR(hcd_frrem, S_IRUGO|S_IWUSR, hcd_frrem_show, 0); ++ ++/** ++ * Displays the time required to read the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is read). ++ */ ++#define RW_REG_COUNT 10000000 ++#define MSEC_PER_JIFFIE 1000/HZ ++static ssize_t rd_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ int i; ++ int time; ++ int start_jiffies; ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf( buf, "Time to read GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time ); ++} ++ ++DEVICE_ATTR(rd_reg_test, S_IRUGO|S_IWUSR, rd_reg_test_show, 0); ++ ++/** ++ * Displays the time required to write the GNPTXFSIZ register many times (the ++ * output shows the number of times the register is written). ++ */ ++static ssize_t wr_reg_test_show( struct device *_dev, struct device_attribute *attr, char *buf) ++{ ++ int i; ++ int time; ++ int start_jiffies; ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ uint32_t reg_val; ++ ++ printk("HZ %d, MSEC_PER_JIFFIE %d, loops_per_jiffy %lu\n", ++ HZ, MSEC_PER_JIFFIE, loops_per_jiffy); ++ reg_val = dwc_read_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz); ++ start_jiffies = jiffies; ++ for (i = 0; i < RW_REG_COUNT; i++) { ++ dwc_write_reg32(&otg_dev->core_if->core_global_regs->gnptxfsiz, reg_val); ++ } ++ time = jiffies - start_jiffies; ++ return sprintf( buf, "Time to write GNPTXFSIZ reg %d times: %d msecs (%d jiffies)\n", ++ RW_REG_COUNT, time * MSEC_PER_JIFFIE, time); ++} ++ ++DEVICE_ATTR(wr_reg_test, S_IRUGO|S_IWUSR, wr_reg_test_show, 0); ++/**@}*/ ++ ++/** ++ * Create the device files ++ */ ++void dwc_otg_attr_create (struct device *_dev) ++{ ++ int retval; ++ ++ retval = device_create_file(_dev, &dev_attr_regoffset); ++ retval += device_create_file(_dev, &dev_attr_regvalue); ++ retval += device_create_file(_dev, &dev_attr_mode); ++ retval += device_create_file(_dev, &dev_attr_hnpcapable); ++ retval += device_create_file(_dev, &dev_attr_srpcapable); ++ retval += device_create_file(_dev, &dev_attr_hnp); ++ retval += device_create_file(_dev, &dev_attr_srp); ++ retval += device_create_file(_dev, &dev_attr_buspower); ++ retval += device_create_file(_dev, &dev_attr_bussuspend); ++ retval += device_create_file(_dev, &dev_attr_busconnected); ++ retval += device_create_file(_dev, &dev_attr_gotgctl); ++ retval += device_create_file(_dev, &dev_attr_gusbcfg); ++ retval += device_create_file(_dev, &dev_attr_grxfsiz); ++ retval += device_create_file(_dev, &dev_attr_gnptxfsiz); ++ retval += device_create_file(_dev, &dev_attr_gpvndctl); ++ retval += device_create_file(_dev, &dev_attr_ggpio); ++ retval += device_create_file(_dev, &dev_attr_guid); ++ retval += device_create_file(_dev, &dev_attr_gsnpsid); ++ retval += device_create_file(_dev, &dev_attr_devspeed); ++ retval += device_create_file(_dev, &dev_attr_enumspeed); ++ retval += device_create_file(_dev, &dev_attr_hptxfsiz); ++ retval += device_create_file(_dev, &dev_attr_hprt0); ++ retval += device_create_file(_dev, &dev_attr_remote_wakeup); ++ retval += device_create_file(_dev, &dev_attr_regdump); ++ retval += device_create_file(_dev, &dev_attr_hcddump); ++ retval += device_create_file(_dev, &dev_attr_hcd_frrem); ++ retval += device_create_file(_dev, &dev_attr_rd_reg_test); ++ retval += device_create_file(_dev, &dev_attr_wr_reg_test); ++ ++ if(retval != 0) ++ { ++ DWC_PRINT("cannot create sysfs device files.\n"); ++ // DWC_PRINT("killing own sysfs device files!\n"); ++ dwc_otg_attr_remove(_dev); ++ } ++} ++ ++/** ++ * Remove the device files ++ */ ++void dwc_otg_attr_remove (struct device *_dev) ++{ ++ device_remove_file(_dev, &dev_attr_regoffset); ++ device_remove_file(_dev, &dev_attr_regvalue); ++ device_remove_file(_dev, &dev_attr_mode); ++ device_remove_file(_dev, &dev_attr_hnpcapable); ++ device_remove_file(_dev, &dev_attr_srpcapable); ++ device_remove_file(_dev, &dev_attr_hnp); ++ device_remove_file(_dev, &dev_attr_srp); ++ device_remove_file(_dev, &dev_attr_buspower); ++ device_remove_file(_dev, &dev_attr_bussuspend); ++ device_remove_file(_dev, &dev_attr_busconnected); ++ device_remove_file(_dev, &dev_attr_gotgctl); ++ device_remove_file(_dev, &dev_attr_gusbcfg); ++ device_remove_file(_dev, &dev_attr_grxfsiz); ++ device_remove_file(_dev, &dev_attr_gnptxfsiz); ++ device_remove_file(_dev, &dev_attr_gpvndctl); ++ device_remove_file(_dev, &dev_attr_ggpio); ++ device_remove_file(_dev, &dev_attr_guid); ++ device_remove_file(_dev, &dev_attr_gsnpsid); ++ device_remove_file(_dev, &dev_attr_devspeed); ++ device_remove_file(_dev, &dev_attr_enumspeed); ++ device_remove_file(_dev, &dev_attr_hptxfsiz); ++ device_remove_file(_dev, &dev_attr_hprt0); ++ device_remove_file(_dev, &dev_attr_remote_wakeup); ++ device_remove_file(_dev, &dev_attr_regdump); ++ device_remove_file(_dev, &dev_attr_hcddump); ++ device_remove_file(_dev, &dev_attr_hcd_frrem); ++ device_remove_file(_dev, &dev_attr_rd_reg_test); ++ device_remove_file(_dev, &dev_attr_wr_reg_test); ++} +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_attr.h +@@ -0,0 +1,67 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_attr.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 510275 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_ATTR_H__) ++#define __DWC_OTG_ATTR_H__ ++ ++/** @file ++ * This file contains the interface to the Linux device attributes. ++ */ ++extern struct device_attribute dev_attr_regoffset; ++extern struct device_attribute dev_attr_regvalue; ++ ++extern struct device_attribute dev_attr_mode; ++extern struct device_attribute dev_attr_hnpcapable; ++extern struct device_attribute dev_attr_srpcapable; ++extern struct device_attribute dev_attr_hnp; ++extern struct device_attribute dev_attr_srp; ++extern struct device_attribute dev_attr_buspower; ++extern struct device_attribute dev_attr_bussuspend; ++extern struct device_attribute dev_attr_busconnected; ++extern struct device_attribute dev_attr_gotgctl; ++extern struct device_attribute dev_attr_gusbcfg; ++extern struct device_attribute dev_attr_grxfsiz; ++extern struct device_attribute dev_attr_gnptxfsiz; ++extern struct device_attribute dev_attr_gpvndctl; ++extern struct device_attribute dev_attr_ggpio; ++extern struct device_attribute dev_attr_guid; ++extern struct device_attribute dev_attr_gsnpsid; ++extern struct device_attribute dev_attr_devspeed; ++extern struct device_attribute dev_attr_enumspeed; ++extern struct device_attribute dev_attr_hptxfsiz; ++extern struct device_attribute dev_attr_hprt0; ++ ++void dwc_otg_attr_create (struct device *_dev); ++void dwc_otg_attr_remove (struct device *_dev); ++ ++#endif +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_cil.c +@@ -0,0 +1,3025 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 631780 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * The CIL manages the memory map for the core so that the HCD and PCD ++ * don't have to do this separately. It also handles basic tasks like ++ * reading/writing the registers and data FIFOs in the controller. ++ * Some of the data access functions provide encapsulation of several ++ * operations required to perform a task, such as writing multiple ++ * registers to start a transfer. Finally, the CIL performs basic ++ * services that are not specific to either the host or device modes ++ * of operation. These services include management of the OTG Host ++ * Negotiation Protocol (HNP) and Session Request Protocol (SRP). A ++ * Diagnostic API is also provided to allow testing of the controller ++ * hardware. ++ * ++ * The Core Interface Layer has the following requirements: ++ * - Provides basic controller operations. ++ * - Minimal use of OS services. ++ * - The OS services used will be abstracted by using inline functions ++ * or macros. ++ * ++ */ ++#include <asm/unaligned.h> ++ ++#ifdef DEBUG ++#include <linux/jiffies.h> ++#endif ++ ++#include "dwc_otg_plat.h" ++ ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++/** ++ * This function is called to initialize the DWC_otg CSR data ++ * structures. The register addresses in the device and host ++ * structures are initialized from the base address supplied by the ++ * caller. The calling function must make the OS calls to get the ++ * base address of the DWC_otg controller registers. The core_params ++ * argument holds the parameters that specify how the core should be ++ * configured. ++ * ++ * @param[in] _reg_base_addr Base address of DWC_otg core registers ++ * @param[in] _core_params Pointer to the core configuration parameters ++ * ++ */ ++dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, ++ dwc_otg_core_params_t *_core_params) ++{ ++ dwc_otg_core_if_t *core_if = 0; ++ dwc_otg_dev_if_t *dev_if = 0; ++ dwc_otg_host_if_t *host_if = 0; ++ uint8_t *reg_base = (uint8_t *)_reg_base_addr; ++ int i = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s(%p,%p)\n", __func__, _reg_base_addr, _core_params); ++ ++ core_if = kmalloc( sizeof(dwc_otg_core_if_t), GFP_KERNEL); ++ if (core_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_core_if_t failed\n"); ++ return 0; ++ } ++ memset(core_if, 0, sizeof(dwc_otg_core_if_t)); ++ ++ core_if->core_params = _core_params; ++ core_if->core_global_regs = (dwc_otg_core_global_regs_t *)reg_base; ++ /* ++ * Allocate the Device Mode structures. ++ */ ++ dev_if = kmalloc( sizeof(dwc_otg_dev_if_t), GFP_KERNEL); ++ if (dev_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_dev_if_t failed\n"); ++ kfree( core_if ); ++ return 0; ++ } ++ ++ dev_if->dev_global_regs = ++ (dwc_otg_device_global_regs_t *)(reg_base + DWC_DEV_GLOBAL_REG_OFFSET); ++ ++ for (i=0; i<MAX_EPS_CHANNELS; i++) { ++ dev_if->in_ep_regs[i] = (dwc_otg_dev_in_ep_regs_t *) ++ (reg_base + DWC_DEV_IN_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ ++ dev_if->out_ep_regs[i] = (dwc_otg_dev_out_ep_regs_t *) ++ (reg_base + DWC_DEV_OUT_EP_REG_OFFSET + ++ (i * DWC_EP_REG_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "in_ep_regs[%d]->diepctl=%p\n", ++ i, &dev_if->in_ep_regs[i]->diepctl); ++ DWC_DEBUGPL(DBG_CILV, "out_ep_regs[%d]->doepctl=%p\n", ++ i, &dev_if->out_ep_regs[i]->doepctl); ++ } ++ dev_if->speed = 0; // unknown ++ //dev_if->num_eps = MAX_EPS_CHANNELS; ++ //dev_if->num_perio_eps = 0; ++ ++ core_if->dev_if = dev_if; ++ /* ++ * Allocate the Host Mode structures. ++ */ ++ host_if = kmalloc( sizeof(dwc_otg_host_if_t), GFP_KERNEL); ++ if (host_if == 0) { ++ DWC_DEBUGPL(DBG_CIL, "Allocation of dwc_otg_host_if_t failed\n"); ++ kfree( dev_if ); ++ kfree( core_if ); ++ return 0; ++ } ++ ++ host_if->host_global_regs = (dwc_otg_host_global_regs_t *) ++ (reg_base + DWC_OTG_HOST_GLOBAL_REG_OFFSET); ++ host_if->hprt0 = (uint32_t*)(reg_base + DWC_OTG_HOST_PORT_REGS_OFFSET); ++ for (i=0; i<MAX_EPS_CHANNELS; i++) { ++ host_if->hc_regs[i] = (dwc_otg_hc_regs_t *) ++ (reg_base + DWC_OTG_HOST_CHAN_REGS_OFFSET + ++ (i * DWC_OTG_CHAN_REGS_OFFSET)); ++ DWC_DEBUGPL(DBG_CILV, "hc_reg[%d]->hcchar=%p\n", ++ i, &host_if->hc_regs[i]->hcchar); ++ } ++ host_if->num_host_channels = MAX_EPS_CHANNELS; ++ core_if->host_if = host_if; ++ ++ for (i=0; i<MAX_EPS_CHANNELS; i++) { ++ core_if->data_fifo[i] = ++ (uint32_t *)(reg_base + DWC_OTG_DATA_FIFO_OFFSET + ++ (i * DWC_OTG_DATA_FIFO_SIZE)); ++ DWC_DEBUGPL(DBG_CILV, "data_fifo[%d]=0x%08x\n", ++ i, (unsigned)core_if->data_fifo[i]); ++ } // for loop. ++ ++ core_if->pcgcctl = (uint32_t*)(reg_base + DWC_OTG_PCGCCTL_OFFSET); ++ ++ /* ++ * Store the contents of the hardware configuration registers here for ++ * easy access later. ++ */ ++ core_if->hwcfg1.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg1); ++ core_if->hwcfg2.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg2); ++ core_if->hwcfg3.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg3); ++ core_if->hwcfg4.d32 = dwc_read_reg32(&core_if->core_global_regs->ghwcfg4); ++ ++ DWC_DEBUGPL(DBG_CILV,"hwcfg1=%08x\n",core_if->hwcfg1.d32); ++ DWC_DEBUGPL(DBG_CILV,"hwcfg2=%08x\n",core_if->hwcfg2.d32); ++ DWC_DEBUGPL(DBG_CILV,"hwcfg3=%08x\n",core_if->hwcfg3.d32); ++ DWC_DEBUGPL(DBG_CILV,"hwcfg4=%08x\n",core_if->hwcfg4.d32); ++ ++ ++ DWC_DEBUGPL(DBG_CILV,"op_mode=%0x\n",core_if->hwcfg2.b.op_mode); ++ DWC_DEBUGPL(DBG_CILV,"arch=%0x\n",core_if->hwcfg2.b.architecture); ++ DWC_DEBUGPL(DBG_CILV,"num_dev_ep=%d\n",core_if->hwcfg2.b.num_dev_ep); ++ DWC_DEBUGPL(DBG_CILV,"num_host_chan=%d\n",core_if->hwcfg2.b.num_host_chan); ++ DWC_DEBUGPL(DBG_CILV,"nonperio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.nonperio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV,"host_perio_tx_q_depth=0x%0x\n",core_if->hwcfg2.b.host_perio_tx_q_depth); ++ DWC_DEBUGPL(DBG_CILV,"dev_token_q_depth=0x%0x\n",core_if->hwcfg2.b.dev_token_q_depth); ++ ++ DWC_DEBUGPL(DBG_CILV,"Total FIFO SZ=%d\n", core_if->hwcfg3.b.dfifo_depth); ++ DWC_DEBUGPL(DBG_CILV,"xfer_size_cntr_width=%0x\n", core_if->hwcfg3.b.xfer_size_cntr_width); ++ ++ /* ++ * Set the SRP sucess bit for FS-I2c ++ */ ++ core_if->srp_success = 0; ++ core_if->srp_timer_started = 0; ++ ++ return core_if; ++} ++/** ++ * This function frees the structures allocated by dwc_otg_cil_init(). ++ * ++ * @param[in] _core_if The core interface pointer returned from ++ * dwc_otg_cil_init(). ++ * ++ */ ++void dwc_otg_cil_remove( dwc_otg_core_if_t *_core_if ) ++{ ++ /* Disable all interrupts */ ++ dwc_modify_reg32( &_core_if->core_global_regs->gahbcfg, 1, 0); ++ dwc_write_reg32( &_core_if->core_global_regs->gintmsk, 0); ++ ++ if ( _core_if->dev_if ) { ++ kfree( _core_if->dev_if ); ++ } ++ if ( _core_if->host_if ) { ++ kfree( _core_if->host_if ); ++ } ++ kfree( _core_if ); ++} ++ ++/** ++ * This function enables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param[in] _core_if Programming view of DWC_otg controller. ++ */ ++extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ) ++{ ++ gahbcfg_data_t ahbcfg = { .d32 = 0}; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, 0, ahbcfg.d32); ++} ++/** ++ * This function disables the controller's Global Interrupt in the AHB Config ++ * register. ++ * ++ * @param[in] _core_if Programming view of DWC_otg controller. ++ */ ++extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ) ++{ ++ gahbcfg_data_t ahbcfg = { .d32 = 0}; ++ ahbcfg.b.glblintrmsk = 1; /* Enable interrupts */ ++ dwc_modify_reg32(&_core_if->core_global_regs->gahbcfg, ahbcfg.d32, 0); ++} ++ ++/** ++ * This function initializes the commmon interrupts, used in both ++ * device and host modes. ++ * ++ * @param[in] _core_if Programming view of the DWC_otg controller ++ * ++ */ ++static void dwc_otg_enable_common_interrupts(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = ++ _core_if->core_global_regs; ++ gintmsk_data_t intr_mask = { .d32 = 0}; ++ /* Clear any pending OTG Interrupts */ ++ dwc_write_reg32( &global_regs->gotgint, 0xFFFFFFFF); ++ /* Clear any pending interrupts */ ++ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); ++ /* ++ * Enable the interrupts in the GINTMSK. ++ */ ++ intr_mask.b.modemismatch = 1; ++ intr_mask.b.otgintr = 1; ++ if (!_core_if->dma_enable) { ++ intr_mask.b.rxstsqlvl = 1; ++ } ++ intr_mask.b.conidstschng = 1; ++ intr_mask.b.wkupintr = 1; ++ intr_mask.b.disconnect = 1; ++ intr_mask.b.usbsuspend = 1; ++ intr_mask.b.sessreqintr = 1; ++ dwc_write_reg32( &global_regs->gintmsk, intr_mask.d32); ++} ++ ++/** ++ * Initializes the FSLSPClkSel field of the HCFG register depending on the PHY ++ * type. ++ */ ++static void init_fslspclksel(dwc_otg_core_if_t *_core_if) ++{ ++ uint32_t val; ++ hcfg_data_t hcfg; ++ ++ if (((_core_if->hwcfg2.b.hs_phy_type == 2) && ++ (_core_if->hwcfg2.b.fs_phy_type == 1) && ++ (_core_if->core_params->ulpi_fs_ls)) || ++ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) ++ { ++ /* Full speed PHY */ ++ val = DWC_HCFG_48_MHZ; ++ } else { ++ /* High speed PHY running at full speed or high speed */ ++ val = DWC_HCFG_30_60_MHZ; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing HCFG.FSLSPClkSel to 0x%1x\n", val); ++ hcfg.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hcfg); ++ hcfg.b.fslspclksel = val; ++ dwc_write_reg32(&_core_if->host_if->host_global_regs->hcfg, hcfg.d32); ++} ++ ++/** ++ * Initializes the DevSpd field of the DCFG register depending on the PHY type ++ * and the enumeration speed of the device. ++ */ ++static void init_devspd(dwc_otg_core_if_t *_core_if) ++{ ++ uint32_t val; ++ dcfg_data_t dcfg; ++ ++ if (((_core_if->hwcfg2.b.hs_phy_type == 2) && ++ (_core_if->hwcfg2.b.fs_phy_type == 1) && ++ (_core_if->core_params->ulpi_fs_ls)) || ++ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) ++ { ++ /* Full speed PHY */ ++ val = 0x3; ++ } else if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ /* High speed PHY running at full speed */ ++ val = 0x1; ++ } else { ++ /* High speed PHY running at high speed */ ++ val = 0x0; ++ } ++ ++ DWC_DEBUGPL(DBG_CIL, "Initializing DCFG.DevSpd to 0x%1x\n", val); ++ dcfg.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dcfg); ++ dcfg.b.devspd = val; ++ dwc_write_reg32(&_core_if->dev_if->dev_global_regs->dcfg, dcfg.d32); ++} ++ ++/** ++ * This function calculates the number of IN EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param _pcd the pcd structure. ++ */ ++static uint32_t calc_num_in_eps(dwc_otg_core_if_t * _core_if) ++{ ++ uint32_t num_in_eps = 0; ++ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; ++ uint32_t num_tx_fifos = _core_if->hwcfg4.b.num_in_eps; ++ int i; ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x1)) ++ num_in_eps++; ++ hwcfg1 >>= 2; ++ } ++ if (_core_if->hwcfg4.b.ded_fifo_en) { ++ num_in_eps = (num_in_eps > num_tx_fifos) ? num_tx_fifos : num_in_eps; ++ } ++ return num_in_eps; ++} ++ ++ ++/** ++ * This function calculates the number of OUT EPS ++ * using GHWCFG1 and GHWCFG2 registers values ++ * ++ * @param _pcd the pcd structure. ++ */ ++static uint32_t calc_num_out_eps(dwc_otg_core_if_t * _core_if) ++{ ++ uint32_t num_out_eps = 0; ++ uint32_t num_eps = _core_if->hwcfg2.b.num_dev_ep; ++ uint32_t hwcfg1 = _core_if->hwcfg1.d32 >> 2; ++ int i; ++ for (i = 0; i < num_eps; ++i) { ++ if (!(hwcfg1 & 0x2)) ++ num_out_eps++; ++ hwcfg1 >>= 2; ++ } ++ return num_out_eps; ++} ++/** ++ * This function initializes the DWC_otg controller registers and ++ * prepares the core for device mode or host mode operation. ++ * ++ * @param _core_if Programming view of the DWC_otg controller ++ * ++ */ ++void dwc_otg_core_init(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ int i = 0; ++ gahbcfg_data_t ahbcfg = { .d32 = 0}; ++ gusbcfg_data_t usbcfg = { .d32 = 0 }; ++ gi2cctl_data_t i2cctl = {.d32 = 0}; ++ ++ DWC_DEBUGPL(DBG_CILV, "dwc_otg_core_init(%p)\n",_core_if); ++ ++ /* Common Initialization */ ++ ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ DWC_DEBUGPL(DBG_CIL, "USB config register: 0x%08x\n", usbcfg.d32); ++ ++ /* Program the ULPI External VBUS bit if needed */ ++ //usbcfg.b.ulpi_ext_vbus_drv = 1; ++ //usbcfg.b.ulpi_ext_vbus_drv = 0; ++ usbcfg.b.ulpi_ext_vbus_drv = ++ (_core_if->core_params->phy_ulpi_ext_vbus == DWC_PHY_ULPI_EXTERNAL_VBUS) ? 1 : 0; ++ ++ /* Set external TS Dline pulsing */ ++ usbcfg.b.term_sel_dl_pulse = (_core_if->core_params->ts_dline == 1) ? 1 : 0; ++ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset the Controller */ ++ dwc_otg_core_reset( _core_if ); ++ ++ /* Initialize parameters from Hardware configuration registers. */ ++#if 0 ++ dev_if->num_eps = _core_if->hwcfg2.b.num_dev_ep; ++ dev_if->num_perio_eps = _core_if->hwcfg4.b.num_dev_perio_in_ep; ++#else ++ dev_if->num_in_eps = calc_num_in_eps(_core_if); ++ dev_if->num_out_eps = calc_num_out_eps(_core_if); ++#endif ++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n", ++ _core_if->hwcfg4.b.num_dev_perio_in_ep); ++ DWC_DEBUGPL(DBG_CIL, "Is power optimization enabled? %s\n", ++ _core_if->hwcfg4.b.power_optimiz ? "Yes" : "No"); ++ DWC_DEBUGPL(DBG_CIL, "vbus_valid filter enabled? %s\n", ++ _core_if->hwcfg4.b.vbus_valid_filt_en ? "Yes" : "No"); ++ DWC_DEBUGPL(DBG_CIL, "iddig filter enabled? %s\n", ++ _core_if->hwcfg4.b.iddig_filt_en ? "Yes" : "No"); ++ ++ DWC_DEBUGPL(DBG_CIL, "num_dev_perio_in_ep=%d\n",_core_if->hwcfg4.b.num_dev_perio_in_ep); ++ for (i=0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ dev_if->perio_tx_fifo_size[i] = ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Periodic Tx FIFO SZ #%d=0x%0x\n", i, ++ dev_if->perio_tx_fifo_size[i]); ++ } ++ for (i = 0; i < _core_if->hwcfg4.b.num_in_eps; i++) { ++ dev_if->tx_fifo_size[i] = ++ dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i]) >> 16; ++ DWC_DEBUGPL(DBG_CIL, "Tx FIFO SZ #%d=0x%0x\n", i, ++ dev_if->perio_tx_fifo_size[i]); ++ } ++ ++ _core_if->total_fifo_size = _core_if->hwcfg3.b.dfifo_depth; ++ _core_if->rx_fifo_size = dwc_read_reg32(&global_regs->grxfsiz); ++ _core_if->nperio_tx_fifo_size = dwc_read_reg32(&global_regs->gnptxfsiz) >> 16; ++ ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO SZ=%d\n", _core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO SZ=%d\n", _core_if->rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO SZ=%d\n", _core_if->nperio_tx_fifo_size); ++ ++ /* This programming sequence needs to happen in FS mode before any other ++ * programming occurs */ ++ if ((_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) && ++ (_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS)) { ++ /* If FS mode with FS PHY */ ++ ++ /* core_init() is now called on every switch so only call the ++ * following for the first time through. */ ++ if (!_core_if->phy_init_done) { ++ _core_if->phy_init_done = 1; ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY detected\n"); ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.physel = 1; ++ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset after a PHY select */ ++ dwc_otg_core_reset( _core_if ); ++ } ++ ++ /* Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also ++ * do this on HNP Dev/Host mode switches (done in dev_init and ++ * host_init). */ ++ if (dwc_otg_is_host_mode(_core_if)) { ++ DWC_DEBUGPL(DBG_CIL, "host mode\n"); ++ init_fslspclksel(_core_if); ++ } else { ++ DWC_DEBUGPL(DBG_CIL, "device mode\n"); ++ init_devspd(_core_if); ++ } ++ ++ if (_core_if->core_params->i2c_enable) { ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY Enabling I2c\n"); ++ /* Program GUSBCFG.OtgUtmifsSel to I2C */ ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.otgutmifssel = 1; ++ dwc_write_reg32 (&global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Program GI2CCTL.I2CEn */ ++ i2cctl.d32 = dwc_read_reg32(&global_regs->gi2cctl); ++ i2cctl.b.i2cdevaddr = 1; ++ i2cctl.b.i2cen = 0; ++ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); ++ i2cctl.b.i2cen = 1; ++ dwc_write_reg32 (&global_regs->gi2cctl, i2cctl.d32); ++ } ++ ++ } /* endif speed == DWC_SPEED_PARAM_FULL */ ++ else { ++ /* High speed PHY. */ ++ if (!_core_if->phy_init_done) { ++ _core_if->phy_init_done = 1; ++ DWC_DEBUGPL(DBG_CIL, "High spped PHY\n"); ++ /* HS PHY parameters. These parameters are preserved ++ * during soft reset so only program the first time. Do ++ * a soft reset immediately after setting phyif. */ ++ usbcfg.b.ulpi_utmi_sel = _core_if->core_params->phy_type; ++ if (usbcfg.b.ulpi_utmi_sel == 2) { // winder ++ DWC_DEBUGPL(DBG_CIL, "ULPI\n"); ++ /* ULPI interface */ ++ usbcfg.b.phyif = 0; ++ usbcfg.b.ddrsel = _core_if->core_params->phy_ulpi_ddr; ++ } else { ++ /* UTMI+ interface */ ++ if (_core_if->core_params->phy_utmi_width == 16) { ++ usbcfg.b.phyif = 1; ++ DWC_DEBUGPL(DBG_CIL, "UTMI+ 16\n"); ++ } else { ++ DWC_DEBUGPL(DBG_CIL, "UTMI+ 8\n"); ++ usbcfg.b.phyif = 0; ++ } ++ } ++ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Reset after setting the PHY parameters */ ++ dwc_otg_core_reset( _core_if ); ++ } ++ } ++ ++ if ((_core_if->hwcfg2.b.hs_phy_type == 2) && ++ (_core_if->hwcfg2.b.fs_phy_type == 1) && ++ (_core_if->core_params->ulpi_fs_ls)) ++ { ++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS\n"); ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 1; ++ usbcfg.b.ulpi_clk_sus_m = 1; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ } else { ++ DWC_DEBUGPL(DBG_CIL, "Setting ULPI FSLS=0\n"); ++ usbcfg.d32 = dwc_read_reg32(&global_regs->gusbcfg); ++ usbcfg.b.ulpi_fsls = 0; ++ usbcfg.b.ulpi_clk_sus_m = 0; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ } ++ ++ /* Program the GAHBCFG Register.*/ ++ switch (_core_if->hwcfg2.b.architecture){ ++ ++ case DWC_SLAVE_ONLY_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Slave Only Mode\n"); ++ ahbcfg.b.nptxfemplvl_txfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ ahbcfg.b.ptxfemplvl = DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY; ++ _core_if->dma_enable = 0; ++ break; ++ ++ case DWC_EXT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "External DMA Mode\n"); ++ ahbcfg.b.hburstlen = _core_if->core_params->dma_burst_size; ++ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); ++ break; ++ ++ case DWC_INT_DMA_ARCH: ++ DWC_DEBUGPL(DBG_CIL, "Internal DMA Mode\n"); ++ //ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR; ++ ahbcfg.b.hburstlen = DWC_GAHBCFG_INT_DMA_BURST_INCR4; ++ _core_if->dma_enable = (_core_if->core_params->dma_enable != 0); ++ break; ++ } ++ ahbcfg.b.dmaenable = _core_if->dma_enable; ++ dwc_write_reg32(&global_regs->gahbcfg, ahbcfg.d32); ++ _core_if->en_multiple_tx_fifo = _core_if->hwcfg4.b.ded_fifo_en; ++ ++ /* ++ * Program the GUSBCFG register. ++ */ ++ usbcfg.d32 = dwc_read_reg32( &global_regs->gusbcfg ); ++ ++ switch (_core_if->hwcfg2.b.op_mode) { ++ case DWC_MODE_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = (_core_if->core_params->otg_cap == ++ DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE); ++ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_SRP_ONLY_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_HNP_SRP_CAPABLE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_DEVICE: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ ++ case DWC_MODE_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = (_core_if->core_params->otg_cap != ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE); ++ break; ++ ++ case DWC_MODE_NO_SRP_CAPABLE_HOST: ++ usbcfg.b.hnpcap = 0; ++ usbcfg.b.srpcap = 0; ++ break; ++ } ++ ++ dwc_write_reg32( &global_regs->gusbcfg, usbcfg.d32); ++ ++ /* Enable common interrupts */ ++ dwc_otg_enable_common_interrupts( _core_if ); ++ ++ /* Do device or host intialization based on mode during PCD ++ * and HCD initialization */ ++ if (dwc_otg_is_host_mode( _core_if )) { ++ DWC_DEBUGPL(DBG_ANY, "Host Mode\n" ); ++ _core_if->op_state = A_HOST; ++ } else { ++ DWC_DEBUGPL(DBG_ANY, "Device Mode\n" ); ++ _core_if->op_state = B_PERIPHERAL; ++#ifdef DWC_DEVICE_ONLY ++ dwc_otg_core_dev_init( _core_if ); ++#endif ++ } ++} ++ ++ ++/** ++ * This function enables the Device mode interrupts. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if) ++{ ++ gintmsk_data_t intr_mask = { .d32 = 0}; ++ dwc_otg_core_global_regs_t * global_regs = _core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); ++ ++ /* Disable all interrupts. */ ++ dwc_write_reg32( &global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts */ ++ dwc_write_reg32( &global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts( _core_if ); ++ ++ /* Enable interrupts */ ++ intr_mask.b.usbreset = 1; ++ intr_mask.b.enumdone = 1; ++ //intr_mask.b.epmismatch = 1; ++ intr_mask.b.inepintr = 1; ++ intr_mask.b.outepintr = 1; ++ intr_mask.b.erlysuspend = 1; ++ if (_core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.epmismatch = 1; ++ } ++ ++ /** @todo NGS: Should this be a module parameter? */ ++ intr_mask.b.isooutdrop = 1; ++ intr_mask.b.eopframe = 1; ++ intr_mask.b.incomplisoin = 1; ++ intr_mask.b.incomplisoout = 1; ++ ++ dwc_modify_reg32( &global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ ++ DWC_DEBUGPL(DBG_CIL, "%s() gintmsk=%0x\n", __func__, ++ dwc_read_reg32( &global_regs->gintmsk)); ++} ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * device mode. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = ++ _core_if->core_global_regs; ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ dwc_otg_core_params_t *params = _core_if->core_params; ++ dcfg_data_t dcfg = {.d32 = 0}; ++ grstctl_t resetctl = { .d32=0 }; ++ int i; ++ uint32_t rx_fifo_size; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t txfifosize; ++ dthrctl_data_t dthrctl; ++ ++ fifosize_data_t ptxfifosize; ++ ++ /* Restart the Phy Clock */ ++ dwc_write_reg32(_core_if->pcgcctl, 0); ++ ++ /* Device configuration register */ ++ init_devspd(_core_if); ++ dcfg.d32 = dwc_read_reg32( &dev_if->dev_global_regs->dcfg); ++ dcfg.b.perfrint = DWC_DCFG_FRAME_INTERVAL_80; ++ dwc_write_reg32( &dev_if->dev_global_regs->dcfg, dcfg.d32 ); ++ ++ /* Configure data FIFO sizes */ ++ if ( _core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo ) { ++ ++ DWC_DEBUGPL(DBG_CIL, "Total FIFO Size=%d\n", _core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "Rx FIFO Size=%d\n", params->dev_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL, "NP Tx FIFO Size=%d\n", params->dev_nperio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ rx_fifo_size = params->dev_rx_fifo_size; ++ dwc_write_reg32( &global_regs->grxfsiz, rx_fifo_size ); ++ DWC_DEBUGPL(DBG_CIL, "new grxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->grxfsiz)); ++ ++ /** Set Periodic Tx FIFO Mask all bits 0 */ ++ _core_if->p_tx_msk = 0; ++ ++ /** Set Tx FIFO Mask all bits 0 */ ++ _core_if->tx_msk = 0; ++ if (_core_if->en_multiple_tx_fifo == 0) { ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ dwc_write_reg32( &global_regs->gnptxfsiz, nptxfifosize.d32 ); ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ ++ /**@todo NGS: Fix Periodic FIFO Sizing! */ ++ /* ++ * Periodic Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_perio_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz array run from 0 to 14. ++ */ ++ /** @todo Finish debug of this */ ++ ptxfifosize.b.startaddr = ++ nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ for (i = 0; i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { ++ ptxfifosize.b.depth = params->dev_perio_tx_fifo_size[i]; ++ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", ++ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); ++ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i],ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", ++ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); ++ ptxfifosize.b.startaddr += ptxfifosize.b.depth; ++ } ++ } else { ++ ++ /* ++ * Tx FIFOs These FIFOs are numbered from 1 to 15. ++ * Indexes of the FIFO size module parameters in the ++ * dev_tx_fifo_size array and the FIFO size registers in ++ * the dptxfsiz_dieptxf array run from 0 to 14. ++ */ ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL, "initial gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->dev_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->dev_rx_fifo_size; ++ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL, "new gnptxfsiz=%08x\n", ++ dwc_read_reg32(&global_regs->gnptxfsiz)); ++ txfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ for (i = 1;i < _core_if->hwcfg4.b.num_dev_perio_in_ep;i++) { ++ txfifosize.b.depth = params->dev_tx_fifo_size[i]; ++ DWC_DEBUGPL(DBG_CIL,"initial dptxfsiz_dieptxf[%d]=%08x\n", ++ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i])); ++ dwc_write_reg32(&global_regs->dptxfsiz_dieptxf[i - 1],txfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL,"new dptxfsiz_dieptxf[%d]=%08x\n", ++ i,dwc_read_reg32(&global_regs->dptxfsiz_dieptxf[i-1])); ++ txfifosize.b.startaddr += txfifosize.b.depth; ++ } ++ } ++ } ++ /* Flush the FIFOs */ ++ dwc_otg_flush_tx_fifo(_core_if, 0x10); /* all Tx FIFOs */ ++ dwc_otg_flush_rx_fifo(_core_if); ++ ++ /* Flush the Learning Queue. */ ++ resetctl.b.intknqflsh = 1; ++ dwc_write_reg32( &_core_if->core_global_regs->grstctl, resetctl.d32); ++ ++ /* Clear all pending Device Interrupts */ ++ dwc_write_reg32( &dev_if->dev_global_regs->diepmsk, 0 ); ++ dwc_write_reg32( &dev_if->dev_global_regs->doepmsk, 0 ); ++ dwc_write_reg32( &dev_if->dev_global_regs->daint, 0xFFFFFFFF ); ++ dwc_write_reg32( &dev_if->dev_global_regs->daintmsk, 0 ); ++ ++ for (i = 0; i <= dev_if->num_in_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[i]->diepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ dwc_write_reg32( &dev_if->in_ep_regs[i]->diepctl, depctl.d32); ++ ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->dieptsiz, 0); ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepdma, 0); ++ dwc_write_reg32(&dev_if->in_ep_regs[i]->diepint, 0xFF); ++ } ++ for (i = 0; i <= dev_if->num_out_eps; i++) { ++ depctl_data_t depctl; ++ depctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[i]->doepctl); ++ if (depctl.b.epena) { ++ depctl.d32 = 0; ++ depctl.b.epdis = 1; ++ depctl.b.snak = 1; ++ } else { ++ depctl.d32 = 0; ++ } ++ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepctl, depctl.d32); ++ ++ //dwc_write_reg32( &dev_if->in_ep_regs[i]->dieptsiz, 0); ++ dwc_write_reg32( &dev_if->out_ep_regs[i]->doeptsiz, 0); ++ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepdma, 0); ++ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepdma, 0); ++ //dwc_write_reg32( &dev_if->in_ep_regs[i]->diepint, 0xFF); ++ dwc_write_reg32( &dev_if->out_ep_regs[i]->doepint, 0xFF); ++ } ++ ++ if (_core_if->en_multiple_tx_fifo && _core_if->dma_enable) { ++ dev_if->non_iso_tx_thr_en = _core_if->core_params->thr_ctl & 0x1; ++ dev_if->iso_tx_thr_en = (_core_if->core_params->thr_ctl >> 1) & 0x1; ++ dev_if->rx_thr_en = (_core_if->core_params->thr_ctl >> 2) & 0x1; ++ dev_if->rx_thr_length = _core_if->core_params->rx_thr_length; ++ dev_if->tx_thr_length = _core_if->core_params->tx_thr_length; ++ dthrctl.d32 = 0; ++ dthrctl.b.non_iso_thr_en = dev_if->non_iso_tx_thr_en; ++ dthrctl.b.iso_thr_en = dev_if->iso_tx_thr_en; ++ dthrctl.b.tx_thr_len = dev_if->tx_thr_length; ++ dthrctl.b.rx_thr_en = dev_if->rx_thr_en; ++ dthrctl.b.rx_thr_len = dev_if->rx_thr_length; ++ dwc_write_reg32(&dev_if->dev_global_regs->dtknqr3_dthrctl,dthrctl.d32); ++ DWC_DEBUGPL(DBG_CIL, "Non ISO Tx Thr - %d\nISO Tx Thr - %d\n" ++ "Rx Thr - %d\nTx Thr Len - %d\nRx Thr Len - %d\n", ++ dthrctl.b.non_iso_thr_en, dthrctl.b.iso_thr_en, ++ dthrctl.b.rx_thr_en, dthrctl.b.tx_thr_len, ++ dthrctl.b.rx_thr_len); ++ } ++ dwc_otg_enable_device_interrupts( _core_if ); ++ { ++ diepmsk_data_t msk = {.d32 = 0}; ++ msk.b.txfifoundrn = 1; ++ dwc_modify_reg32(&dev_if->dev_global_regs->diepmsk, msk.d32,msk.d32); ++} ++} ++ ++/** ++ * This function enables the Host mode interrupts. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ ++ DWC_DEBUGPL(DBG_CIL, "%s()\n", __func__); ++ ++ /* Disable all interrupts. */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* Clear any pending interrupts. */ ++ dwc_write_reg32(&global_regs->gintsts, 0xFFFFFFFF); ++ ++ /* Enable the common interrupts */ ++ dwc_otg_enable_common_interrupts(_core_if); ++ ++ /* ++ * Enable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ ++ //dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++ //dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, intr_mask.d32); ++} ++ ++/** ++ * This function disables the Host Mode interrupts. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ */ ++void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = ++ _core_if->core_global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s()\n", __func__); ++ ++ /* ++ * Disable host mode interrupts without disturbing common ++ * interrupts. ++ */ ++ intr_mask.b.sofintr = 1; ++ intr_mask.b.portintr = 1; ++ intr_mask.b.hcintr = 1; ++ intr_mask.b.ptxfempty = 1; ++ intr_mask.b.nptxfempty = 1; ++ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); ++} ++ ++#if 0 ++/* currently not used, keep it here as if needed later */ ++static int phy_read(dwc_otg_core_if_t * _core_if, int addr) ++{ ++ u32 val; ++ int timeout = 10; ++ ++ dwc_write_reg32(&_core_if->core_global_regs->gpvndctl, ++ 0x02000000 | (addr << 16)); ++ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); ++ while (((val & 0x08000000) == 0) && (timeout--)) { ++ udelay(1000); ++ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); ++ } ++ val = dwc_read_reg32(&_core_if->core_global_regs->gpvndctl); ++ printk("%s: addr=%02x regval=%02x\n", __func__, addr, val & 0x000000ff); ++ ++ return 0; ++} ++#endif ++ ++/** ++ * This function initializes the DWC_otg controller registers for ++ * host mode. ++ * ++ * This function flushes the Tx and Rx FIFOs and it flushes any entries in the ++ * request queues. Host channels are reset to ensure that they are ready for ++ * performing transfers. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ * ++ */ ++void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = _core_if->host_if; ++ dwc_otg_core_params_t *params = _core_if->core_params; ++ hprt0_data_t hprt0 = {.d32 = 0}; ++ fifosize_data_t nptxfifosize; ++ fifosize_data_t ptxfifosize; ++ int i; ++ hcchar_data_t hcchar; ++ hcfg_data_t hcfg; ++ dwc_otg_hc_regs_t *hc_regs; ++ int num_channels; ++ gotgctl_data_t gotgctl = {.d32 = 0}; ++ ++ DWC_DEBUGPL(DBG_CILV,"%s(%p)\n", __func__, _core_if); ++ ++ /* Restart the Phy Clock */ ++ dwc_write_reg32(_core_if->pcgcctl, 0); ++ ++ /* Initialize Host Configuration Register */ ++ init_fslspclksel(_core_if); ++ if (_core_if->core_params->speed == DWC_SPEED_PARAM_FULL) { ++ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ hcfg.b.fslssupp = 1; ++ dwc_write_reg32(&host_if->host_global_regs->hcfg, hcfg.d32); ++ } ++ ++ /* Configure data FIFO sizes */ ++ if (_core_if->hwcfg2.b.dynamic_fifo && params->enable_dynamic_fifo) { ++ DWC_DEBUGPL(DBG_CIL,"Total FIFO Size=%d\n", _core_if->total_fifo_size); ++ DWC_DEBUGPL(DBG_CIL,"Rx FIFO Size=%d\n", params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL,"NP Tx FIFO Size=%d\n", params->host_nperio_tx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL,"P Tx FIFO Size=%d\n", params->host_perio_tx_fifo_size); ++ ++ /* Rx FIFO */ ++ DWC_DEBUGPL(DBG_CIL,"initial grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); ++ dwc_write_reg32(&global_regs->grxfsiz, params->host_rx_fifo_size); ++ DWC_DEBUGPL(DBG_CIL,"new grxfsiz=%08x\n", dwc_read_reg32(&global_regs->grxfsiz)); ++ ++ /* Non-periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL,"initial gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); ++ nptxfifosize.b.depth = params->host_nperio_tx_fifo_size; ++ nptxfifosize.b.startaddr = params->host_rx_fifo_size; ++ dwc_write_reg32(&global_regs->gnptxfsiz, nptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL,"new gnptxfsiz=%08x\n", dwc_read_reg32(&global_regs->gnptxfsiz)); ++ ++ /* Periodic Tx FIFO */ ++ DWC_DEBUGPL(DBG_CIL,"initial hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); ++ ptxfifosize.b.depth = params->host_perio_tx_fifo_size; ++ ptxfifosize.b.startaddr = nptxfifosize.b.startaddr + nptxfifosize.b.depth; ++ dwc_write_reg32(&global_regs->hptxfsiz, ptxfifosize.d32); ++ DWC_DEBUGPL(DBG_CIL,"new hptxfsiz=%08x\n", dwc_read_reg32(&global_regs->hptxfsiz)); ++ } ++ ++ /* Clear Host Set HNP Enable in the OTG Control Register */ ++ gotgctl.b.hstsethnpen = 1; ++ dwc_modify_reg32( &global_regs->gotgctl, gotgctl.d32, 0); ++ ++ /* Make sure the FIFOs are flushed. */ ++ dwc_otg_flush_tx_fifo(_core_if, 0x10 /* all Tx FIFOs */); ++ dwc_otg_flush_rx_fifo(_core_if); ++ ++ /* Flush out any leftover queued requests. */ ++ num_channels = _core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ hc_regs = _core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ } ++ ++ /* Halt all channels to put them into a known state. */ ++ for (i = 0; i < num_channels; i++) { ++ int count = 0; ++ hc_regs = _core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, "%s: Halt channel %d\n", __func__, i); ++ do { ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (++count > 200) { ++ DWC_ERROR("%s: Unable to clear halt on channel %d\n", ++ __func__, i); ++ break; ++ } ++ udelay(100); ++ } while (hcchar.b.chen); ++ } ++ ++ /* Turn on the vbus power. */ ++ DWC_PRINT("Init: Port Power? op_state=%d\n", _core_if->op_state); ++ if (_core_if->op_state == A_HOST){ ++ hprt0.d32 = dwc_otg_read_hprt0(_core_if); ++ DWC_PRINT("Init: Power Port (%d)\n", hprt0.b.prtpwr); ++ if (hprt0.b.prtpwr == 0 ) { ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(host_if->hprt0, hprt0.d32); ++ } ++ } ++ ++ dwc_otg_enable_host_interrupts( _core_if ); ++} ++ ++/** ++ * Prepares a host channel for transferring packets to/from a specific ++ * endpoint. The HCCHARn register is set up with the characteristics specified ++ * in _hc. Host channel interrupts that may need to be serviced while this ++ * transfer is in progress are enabled. ++ * ++ * @param _core_if Programming view of DWC_otg controller ++ * @param _hc Information needed to initialize the host channel ++ */ ++void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ uint32_t intr_enable; ++ hcintmsk_data_t hc_intr_mask; ++ gintmsk_data_t gintmsk = {.d32 = 0}; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ ++ uint8_t hc_num = _hc->hc_num; ++ dwc_otg_host_if_t *host_if = _core_if->host_if; ++ dwc_otg_hc_regs_t *hc_regs = host_if->hc_regs[hc_num]; ++ ++ /* Clear old interrupt conditions for this host channel. */ ++ hc_intr_mask.d32 = 0xFFFFFFFF; ++ hc_intr_mask.b.reserved = 0; ++ dwc_write_reg32(&hc_regs->hcint, hc_intr_mask.d32); ++ ++ /* Enable channel interrupts required for this transfer. */ ++ hc_intr_mask.d32 = 0; ++ hc_intr_mask.b.chhltd = 1; ++ if (_core_if->dma_enable) { ++ hc_intr_mask.b.ahberr = 1; ++ if (_hc->error_state && !_hc->do_split && ++ _hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ hc_intr_mask.b.ack = 1; ++ if (_hc->ep_is_in) { ++ hc_intr_mask.b.datatglerr = 1; ++ if (_hc->ep_type != DWC_OTG_EP_TYPE_INTR) { ++ hc_intr_mask.b.nak = 1; ++ } ++ } ++ } ++ } else { ++ switch (_hc->ep_type) { ++ case DWC_OTG_EP_TYPE_CONTROL: ++ case DWC_OTG_EP_TYPE_BULK: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ if (_hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } else { ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.nyet = 1; ++ if (_hc->do_ping) { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (_hc->do_split) { ++ hc_intr_mask.b.nak = 1; ++ if (_hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } ++ else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ ++ if (_hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ break; ++ case DWC_OTG_EP_TYPE_INTR: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.nak = 1; ++ hc_intr_mask.b.stall = 1; ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.datatglerr = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ ++ if (_hc->ep_is_in) { ++ hc_intr_mask.b.bblerr = 1; ++ } ++ if (_hc->error_state) { ++ hc_intr_mask.b.ack = 1; ++ } ++ if (_hc->do_split) { ++ if (_hc->complete_split) { ++ hc_intr_mask.b.nyet = 1; ++ } ++ else { ++ hc_intr_mask.b.ack = 1; ++ } ++ } ++ break; ++ case DWC_OTG_EP_TYPE_ISOC: ++ hc_intr_mask.b.xfercompl = 1; ++ hc_intr_mask.b.frmovrun = 1; ++ hc_intr_mask.b.ack = 1; ++ ++ if (_hc->ep_is_in) { ++ hc_intr_mask.b.xacterr = 1; ++ hc_intr_mask.b.bblerr = 1; ++ } ++ break; ++ } ++ } ++ dwc_write_reg32(&hc_regs->hcintmsk, hc_intr_mask.d32); ++ ++ /* Enable the top level host channel interrupt. */ ++ intr_enable = (1 << hc_num); ++ dwc_modify_reg32(&host_if->host_global_regs->haintmsk, 0, intr_enable); ++ ++ /* Make sure host channel interrupts are enabled. */ ++ gintmsk.b.hcintr = 1; ++ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, 0, gintmsk.d32); ++ ++ /* ++ * Program the HCCHARn register with the endpoint characteristics for ++ * the current transfer. ++ */ ++ hcchar.d32 = 0; ++ hcchar.b.devaddr = _hc->dev_addr; ++ hcchar.b.epnum = _hc->ep_num; ++ hcchar.b.epdir = _hc->ep_is_in; ++ hcchar.b.lspddev = (_hc->speed == DWC_OTG_EP_SPEED_LOW); ++ hcchar.b.eptype = _hc->ep_type; ++ hcchar.b.mps = _hc->max_packet; ++ ++ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcchar, hcchar.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Dev Addr: %d\n", hcchar.b.devaddr); ++ DWC_DEBUGPL(DBG_HCDV, " Ep Num: %d\n", hcchar.b.epnum); ++ DWC_DEBUGPL(DBG_HCDV, " Is In: %d\n", hcchar.b.epdir); ++ DWC_DEBUGPL(DBG_HCDV, " Is Low Speed: %d\n", hcchar.b.lspddev); ++ DWC_DEBUGPL(DBG_HCDV, " Ep Type: %d\n", hcchar.b.eptype); ++ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, " Multi Cnt: %d\n", hcchar.b.multicnt); ++ ++ /* ++ * Program the HCSPLIT register for SPLITs ++ */ ++ hcsplt.d32 = 0; ++ if (_hc->do_split) { ++ DWC_DEBUGPL(DBG_HCDV, "Programming HC %d with split --> %s\n", _hc->hc_num, ++ _hc->complete_split ? "CSPLIT" : "SSPLIT"); ++ hcsplt.b.compsplt = _hc->complete_split; ++ hcsplt.b.xactpos = _hc->xact_pos; ++ hcsplt.b.hubaddr = _hc->hub_addr; ++ hcsplt.b.prtaddr = _hc->port_addr; ++ DWC_DEBUGPL(DBG_HCDV, " comp split %d\n", _hc->complete_split); ++ DWC_DEBUGPL(DBG_HCDV, " xact pos %d\n", _hc->xact_pos); ++ DWC_DEBUGPL(DBG_HCDV, " hub addr %d\n", _hc->hub_addr); ++ DWC_DEBUGPL(DBG_HCDV, " port addr %d\n", _hc->port_addr); ++ DWC_DEBUGPL(DBG_HCDV, " is_in %d\n", _hc->ep_is_in); ++ DWC_DEBUGPL(DBG_HCDV, " Max Pkt: %d\n", hcchar.b.mps); ++ DWC_DEBUGPL(DBG_HCDV, " xferlen: %d\n", _hc->xfer_len); ++ } ++ dwc_write_reg32(&host_if->hc_regs[hc_num]->hcsplt, hcsplt.d32); ++ ++} ++ ++/** ++ * Attempts to halt a host channel. This function should only be called in ++ * Slave mode or to abort a transfer in either Slave mode or DMA mode. Under ++ * normal circumstances in DMA mode, the controller halts the channel when the ++ * transfer is complete or a condition occurs that requires application ++ * intervention. ++ * ++ * In slave mode, checks for a free request queue entry, then sets the Channel ++ * Enable and Channel Disable bits of the Host Channel Characteristics ++ * register of the specified channel to intiate the halt. If there is no free ++ * request queue entry, sets only the Channel Disable bit of the HCCHARn ++ * register to flush requests for this channel. In the latter case, sets a ++ * flag to indicate that the host channel needs to be halted when a request ++ * queue slot is open. ++ * ++ * In DMA mode, always sets the Channel Enable and Channel Disable bits of the ++ * HCCHARn register. The controller ensures there is space in the request ++ * queue before submitting the halt request. ++ * ++ * Some time may elapse before the core flushes any posted requests for this ++ * host channel and halts. The Channel Halted interrupt handler completes the ++ * deactivation of the host channel. ++ * ++ * @param _core_if Controller register interface. ++ * @param _hc Host channel to halt. ++ * @param _halt_status Reason for halting the channel. ++ */ ++void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, ++ dwc_hc_t *_hc, ++ dwc_otg_halt_status_e _halt_status) ++{ ++ gnptxsts_data_t nptxsts; ++ hptxsts_data_t hptxsts; ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_core_global_regs_t *global_regs; ++ dwc_otg_host_global_regs_t *host_global_regs; ++ ++ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ global_regs = _core_if->core_global_regs; ++ host_global_regs = _core_if->host_if->host_global_regs; ++ ++ WARN_ON(_halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS); ++ ++ if (_halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ _halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ /* ++ * Disable all channel interrupts except Ch Halted. The QTD ++ * and QH state associated with this transfer has been cleared ++ * (in the case of URB_DEQUEUE), so the channel needs to be ++ * shut down carefully to prevent crashes. ++ */ ++ hcintmsk_data_t hcintmsk; ++ hcintmsk.d32 = 0; ++ hcintmsk.b.chhltd = 1; ++ dwc_write_reg32(&hc_regs->hcintmsk, hcintmsk.d32); ++ ++ /* ++ * Make sure no other interrupts besides halt are currently ++ * pending. Handling another interrupt could cause a crash due ++ * to the QTD and QH state. ++ */ ++ dwc_write_reg32(&hc_regs->hcint, ~hcintmsk.d32); ++ ++ /* ++ * Make sure the halt status is set to URB_DEQUEUE or AHB_ERR ++ * even if the channel was already halted for some other ++ * reason. ++ */ ++ _hc->halt_status = _halt_status; ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen == 0) { ++ /* ++ * The channel is either already halted or it hasn't ++ * started yet. In DMA mode, the transfer may halt if ++ * it finishes normally or a condition occurs that ++ * requires driver intervention. Don't want to halt ++ * the channel again. In either Slave or DMA mode, ++ * it's possible that the transfer has been assigned ++ * to a channel, but not started yet when an URB is ++ * dequeued. Don't want to halt a channel that hasn't ++ * started yet. ++ */ ++ return; ++ } ++ } ++ ++ if (_hc->halt_pending) { ++ /* ++ * A halt has already been issued for this channel. This might ++ * happen when a transfer is aborted by a higher level in ++ * the stack. ++ */ ++#ifdef DEBUG ++ DWC_PRINT("*** %s: Channel %d, _hc->halt_pending already set ***\n", ++ __func__, _hc->hc_num); ++ ++/* dwc_otg_dump_global_registers(_core_if); */ ++/* dwc_otg_dump_host_registers(_core_if); */ ++#endif ++ return; ++ } ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 1; ++ ++ if (!_core_if->dma_enable) { ++ /* Check for space in the request queue to issue the halt. */ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ nptxsts.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ if (nptxsts.b.nptxqspcavail == 0) { ++ hcchar.b.chen = 0; ++ } ++ } else { ++ hptxsts.d32 = dwc_read_reg32(&host_global_regs->hptxsts); ++ if ((hptxsts.b.ptxqspcavail == 0) || (_core_if->queuing_high_bandwidth)) { ++ hcchar.b.chen = 0; ++ } ++ } ++ } ++ ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ _hc->halt_status = _halt_status; ++ ++ if (hcchar.b.chen) { ++ _hc->halt_pending = 1; ++ _hc->halt_on_queue = 0; ++ } else { ++ _hc->halt_on_queue = 1; ++ } ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hcchar: 0x%08x\n", hcchar.d32); ++ DWC_DEBUGPL(DBG_HCDV, " halt_pending: %d\n", _hc->halt_pending); ++ DWC_DEBUGPL(DBG_HCDV, " halt_on_queue: %d\n", _hc->halt_on_queue); ++ DWC_DEBUGPL(DBG_HCDV, " halt_status: %d\n", _hc->halt_status); ++ ++ return; ++} ++ ++/** ++ * Clears the transfer state for a host channel. This function is normally ++ * called after a transfer is done and the host channel is being released. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _hc Identifies the host channel to clean up. ++ */ ++void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ dwc_otg_hc_regs_t *hc_regs; ++ ++ _hc->xfer_started = 0; ++ ++ /* ++ * Clear channel interrupt enables and any unhandled channel interrupt ++ * conditions. ++ */ ++ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ dwc_write_reg32(&hc_regs->hcintmsk, 0); ++ dwc_write_reg32(&hc_regs->hcint, 0xFFFFFFFF); ++ ++#ifdef DEBUG ++ del_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); ++ { ++ hcchar_data_t hcchar; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, _hc->hc_num, hcchar.d32); ++ } ++ } ++#endif ++} ++ ++/** ++ * Sets the channel property that indicates in which frame a periodic transfer ++ * should occur. This is always set to the _next_ frame. This function has no ++ * effect on non-periodic transfers. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _hc Identifies the host channel to set up and its properties. ++ * @param _hcchar Current value of the HCCHAR register for the specified host ++ * channel. ++ */ ++static inline void hc_set_even_odd_frame(dwc_otg_core_if_t *_core_if, ++ dwc_hc_t *_hc, ++ hcchar_data_t *_hcchar) ++{ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hfnum_data_t hfnum; ++ hfnum.d32 = dwc_read_reg32(&_core_if->host_if->host_global_regs->hfnum); ++ /* 1 if _next_ frame is odd, 0 if it's even */ ++ _hcchar->b.oddfrm = (hfnum.b.frnum & 0x1) ? 0 : 1; ++#ifdef DEBUG ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR && _hc->do_split && !_hc->complete_split) { ++ switch (hfnum.b.frnum & 0x7) { ++ case 7: ++ _core_if->hfnum_7_samples++; ++ _core_if->hfnum_7_frrem_accum += hfnum.b.frrem; ++ break; ++ case 0: ++ _core_if->hfnum_0_samples++; ++ _core_if->hfnum_0_frrem_accum += hfnum.b.frrem; ++ break; ++ default: ++ _core_if->hfnum_other_samples++; ++ _core_if->hfnum_other_frrem_accum += hfnum.b.frrem; ++ break; ++ } ++ } ++#endif ++ } ++} ++ ++#ifdef DEBUG ++static void hc_xfer_timeout(unsigned long _ptr) ++{ ++ hc_xfer_info_t *xfer_info = (hc_xfer_info_t *)_ptr; ++ int hc_num = xfer_info->hc->hc_num; ++ DWC_WARN("%s: timeout on channel %d\n", __func__, hc_num); ++ DWC_WARN(" start_hcchar_val 0x%08x\n", xfer_info->core_if->start_hcchar_val[hc_num]); ++} ++#endif ++ ++/* ++ * This function does the setup for a data transfer for a host channel and ++ * starts the transfer. May be called in either Slave mode or DMA mode. In ++ * Slave mode, the caller must ensure that there is sufficient space in the ++ * request queue and Tx Data FIFO. ++ * ++ * For an OUT transfer in Slave mode, it loads a data packet into the ++ * appropriate FIFO. If necessary, additional data packets will be loaded in ++ * the Host ISR. ++ * ++ * For an IN transfer in Slave mode, a data packet is requested. The data ++ * packets are unloaded from the Rx FIFO in the Host ISR. If necessary, ++ * additional data packets are requested in the Host ISR. ++ * ++ * For a PING transfer in Slave mode, the Do Ping bit is set in the HCTSIZ ++ * register along with a packet count of 1 and the channel is enabled. This ++ * causes a single PING transaction to occur. Other fields in HCTSIZ are ++ * simply set to 0 since no data transfer occurs in this case. ++ * ++ * For a PING transfer in DMA mode, the HCTSIZ register is initialized with ++ * all the information required to perform the subsequent data transfer. In ++ * addition, the Do Ping bit is set in the HCTSIZ register. In this case, the ++ * controller performs the entire PING protocol, then starts the data ++ * transfer. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _hc Information needed to initialize the host channel. The xfer_len ++ * value may be reduced to accommodate the max widths of the XferSize and ++ * PktCnt fields in the HCTSIZn register. The multi_count value may be changed ++ * to reflect the final xfer_len value. ++ */ ++void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ uint16_t num_packets; ++ uint32_t max_hc_xfer_size = _core_if->core_params->max_transfer_size; ++ uint16_t max_hc_pkt_count = _core_if->core_params->max_packet_count; ++ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ ++ hctsiz.d32 = 0; ++ ++ if (_hc->do_ping) { ++ if (!_core_if->dma_enable) { ++ dwc_otg_hc_do_ping(_core_if, _hc); ++ _hc->xfer_started = 1; ++ return; ++ } else { ++ hctsiz.b.dopng = 1; ++ } ++ } ++ ++ if (_hc->do_split) { ++ num_packets = 1; ++ ++ if (_hc->complete_split && !_hc->ep_is_in) { ++ /* For CSPLIT OUT Transfer, set the size to 0 so the ++ * core doesn't expect any data written to the FIFO */ ++ _hc->xfer_len = 0; ++ } else if (_hc->ep_is_in || (_hc->xfer_len > _hc->max_packet)) { ++ _hc->xfer_len = _hc->max_packet; ++ } else if (!_hc->ep_is_in && (_hc->xfer_len > 188)) { ++ _hc->xfer_len = 188; ++ } ++ ++ hctsiz.b.xfersize = _hc->xfer_len; ++ } else { ++ /* ++ * Ensure that the transfer length and packet count will fit ++ * in the widths allocated for them in the HCTSIZn register. ++ */ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure the transfer size is no larger than one ++ * (micro)frame's worth of data. (A check was done ++ * when the periodic transfer was accepted to ensure ++ * that a (micro)frame's worth of data can be ++ * programmed into a channel.) ++ */ ++ uint32_t max_periodic_len = _hc->multi_count * _hc->max_packet; ++ if (_hc->xfer_len > max_periodic_len) { ++ _hc->xfer_len = max_periodic_len; ++ } else { ++ } ++ } else if (_hc->xfer_len > max_hc_xfer_size) { ++ /* Make sure that xfer_len is a multiple of max packet size. */ ++ _hc->xfer_len = max_hc_xfer_size - _hc->max_packet + 1; ++ } ++ ++ if (_hc->xfer_len > 0) { ++ num_packets = (_hc->xfer_len + _hc->max_packet - 1) / _hc->max_packet; ++ if (num_packets > max_hc_pkt_count) { ++ num_packets = max_hc_pkt_count; ++ _hc->xfer_len = num_packets * _hc->max_packet; ++ } ++ } else { ++ /* Need 1 packet for transfer length of 0. */ ++ num_packets = 1; ++ } ++ ++ if (_hc->ep_is_in) { ++ /* Always program an integral # of max packets for IN transfers. */ ++ _hc->xfer_len = num_packets * _hc->max_packet; ++ } ++ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * Make sure that the multi_count field matches the ++ * actual transfer length. ++ */ ++ _hc->multi_count = num_packets; ++ ++ } ++ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* Set up the initial PID for the transfer. */ ++ if (_hc->speed == DWC_OTG_EP_SPEED_HIGH) { ++ if (_hc->ep_is_in) { ++ if (_hc->multi_count == 1) { ++ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else if (_hc->multi_count == 2) { ++ _hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ } else { ++ _hc->data_pid_start = DWC_OTG_HC_PID_DATA2; ++ } ++ } else { ++ if (_hc->multi_count == 1) { ++ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } else { ++ _hc->data_pid_start = DWC_OTG_HC_PID_MDATA; ++ } ++ } ++ } else { ++ _hc->data_pid_start = DWC_OTG_HC_PID_DATA0; ++ } ++ } ++ ++ hctsiz.b.xfersize = _hc->xfer_len; ++ } ++ ++ _hc->start_pkt_count = num_packets; ++ hctsiz.b.pktcnt = num_packets; ++ hctsiz.b.pid = _hc->data_pid_start; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " Xfer Size: %d\n", hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " Num Pkts: %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " Start PID: %d\n", hctsiz.b.pid); ++ ++ if (_core_if->dma_enable) { ++#ifdef DEBUG ++if(((uint32_t)_hc->xfer_buff)%4) ++printk("dwc_otg_hc_start_transfer _hc->xfer_buff not 4 byte alignment\n"); ++#endif ++ dwc_write_reg32(&hc_regs->hcdma, (uint32_t)_hc->xfer_buff); ++ } ++ ++ /* Start the split */ ++ if (_hc->do_split) { ++ hcsplt_data_t hcsplt; ++ hcsplt.d32 = dwc_read_reg32 (&hc_regs->hcsplt); ++ hcsplt.b.spltena = 1; ++ dwc_write_reg32(&hc_regs->hcsplt, hcsplt.d32); ++ } ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.multicnt = _hc->multi_count; ++ hc_set_even_odd_frame(_core_if, _hc, &hcchar); ++#ifdef DEBUG ++ _core_if->start_hcchar_val[_hc->hc_num] = hcchar.d32; ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: chdis set, channel %d, hcchar 0x%08x\n", ++ __func__, _hc->hc_num, hcchar.d32); ++ } ++#endif ++ ++ /* Set host channel enable after all other setup is complete. */ ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ _hc->xfer_started = 1; ++ _hc->requests++; ++ ++ if (!_core_if->dma_enable && !_hc->ep_is_in && _hc->xfer_len > 0) { ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(_core_if, _hc); ++ } ++ ++#ifdef DEBUG ++ /* Start a timer for this transfer. */ ++ _core_if->hc_xfer_timer[_hc->hc_num].function = hc_xfer_timeout; ++ _core_if->hc_xfer_info[_hc->hc_num].core_if = _core_if; ++ _core_if->hc_xfer_info[_hc->hc_num].hc = _hc; ++ _core_if->hc_xfer_timer[_hc->hc_num].data = (unsigned long)(&_core_if->hc_xfer_info[_hc->hc_num]); ++ _core_if->hc_xfer_timer[_hc->hc_num].expires = jiffies + (HZ*10); ++ add_timer(&_core_if->hc_xfer_timer[_hc->hc_num]); ++#endif ++} ++ ++/** ++ * This function continues a data transfer that was started by previous call ++ * to <code>dwc_otg_hc_start_transfer</code>. The caller must ensure there is ++ * sufficient space in the request queue and Tx Data FIFO. This function ++ * should only be called in Slave mode. In DMA mode, the controller acts ++ * autonomously to complete transfers programmed to a host channel. ++ * ++ * For an OUT transfer, a new data packet is loaded into the appropriate FIFO ++ * if there is any data remaining to be queued. For an IN transfer, another ++ * data packet is always requested. For the SETUP phase of a control transfer, ++ * this function does nothing. ++ * ++ * @return 1 if a new request is queued, 0 if no more requests are required ++ * for this transfer. ++ */ ++int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); ++ ++ if (_hc->do_split) { ++ /* SPLITs always queue just once per channel */ ++ return 0; ++ } else if (_hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ /* SETUPs are queued only once since they can't be NAKed. */ ++ return 0; ++ } else if (_hc->ep_is_in) { ++ /* ++ * Always queue another request for other IN transfers. If ++ * back-to-back INs are issued and NAKs are received for both, ++ * the driver may still be processing the first NAK when the ++ * second NAK is received. When the interrupt handler clears ++ * the NAK interrupt for the first NAK, the second NAK will ++ * not be seen. So we can't depend on the NAK interrupt ++ * handler to requeue a NAKed request. Instead, IN requests ++ * are issued each time this function is called. When the ++ * transfer completes, the extra requests for the channel will ++ * be flushed. ++ */ ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(_core_if, _hc, &hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ DWC_DEBUGPL(DBG_HCDV, " IN xfer: hcchar = 0x%08x\n", hcchar.d32); ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ _hc->requests++; ++ return 1; ++ } else { ++ /* OUT transfers. */ ++ if (_hc->xfer_count < _hc->xfer_len) { ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ hcchar_data_t hcchar; ++ dwc_otg_hc_regs_t *hc_regs; ++ hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hc_set_even_odd_frame(_core_if, _hc, &hcchar); ++ } ++ ++ /* Load OUT packet into the appropriate Tx FIFO. */ ++ dwc_otg_hc_write_packet(_core_if, _hc); ++ _hc->requests++; ++ return 1; ++ } else { ++ return 0; ++ } ++ } ++} ++ ++/** ++ * Starts a PING transfer. This function should only be called in Slave mode. ++ * The Do Ping bit is set in the HCTSIZ register, then the channel is enabled. ++ */ ++void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ dwc_otg_hc_regs_t *hc_regs = _core_if->host_if->hc_regs[_hc->hc_num]; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s: Channel %d\n", __func__, _hc->hc_num); ++ ++ hctsiz.d32 = 0; ++ hctsiz.b.dopng = 1; ++ hctsiz.b.pktcnt = 1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.chen = 1; ++ hcchar.b.chdis = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++} ++ ++/* ++ * This function writes a packet into the Tx FIFO associated with the Host ++ * Channel. For a channel associated with a non-periodic EP, the non-periodic ++ * Tx FIFO is written. For a channel associated with a periodic EP, the ++ * periodic Tx FIFO is written. This function should only be called in Slave ++ * mode. ++ * ++ * Upon return the xfer_buff and xfer_count fields in _hc are incremented by ++ * then number of bytes written to the Tx FIFO. ++ */ ++void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ uint32_t i; ++ uint32_t remaining_count; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ ++ uint32_t *data_buff = (uint32_t *)(_hc->xfer_buff); ++ uint32_t *data_fifo = _core_if->data_fifo[_hc->hc_num]; ++ ++ remaining_count = _hc->xfer_len - _hc->xfer_count; ++ if (remaining_count > _hc->max_packet) { ++ byte_count = _hc->max_packet; ++ } else { ++ byte_count = remaining_count; ++ } ++ ++ dword_count = (byte_count + 3) / 4; ++ ++ if ((((unsigned long)data_buff) & 0x3) == 0) { ++ /* xfer_buff is DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ dwc_write_reg32(data_fifo, *data_buff); ++ } ++ } else { ++ /* xfer_buff is not DWORD aligned. */ ++ for (i = 0; i < dword_count; i++, data_buff++) { ++ dwc_write_reg32(data_fifo, get_unaligned(data_buff)); ++ } ++ } ++ ++ _hc->xfer_count += byte_count; ++ _hc->xfer_buff += byte_count; ++} ++ ++/** ++ * Gets the current USB frame number. This is the frame number from the last ++ * SOF packet. ++ */ ++uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if) ++{ ++ dsts_data_t dsts; ++ dsts.d32 = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->dsts); ++ ++ /* read current frame/microfreme number from DSTS register */ ++ return dsts.b.soffn; ++} ++ ++/** ++ * This function reads a setup packet from the Rx FIFO into the destination ++ * buffer. This function is called from the Rx Status Queue Level (RxStsQLvl) ++ * Interrupt routine when a SETUP packet has been received in Slave mode. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _dest Destination buffer for packet data. ++ */ ++void dwc_otg_read_setup_packet(dwc_otg_core_if_t *_core_if, uint32_t *_dest) ++{ ++ /* Get the 8 bytes of a setup transaction data */ ++ ++ /* Pop 2 DWORDS off the receive data FIFO into memory */ ++ _dest[0] = dwc_read_reg32(_core_if->data_fifo[0]); ++ _dest[1] = dwc_read_reg32(_core_if->data_fifo[0]); ++ //_dest[0] = dwc_read_datafifo32(_core_if->data_fifo[0]); ++ //_dest[1] = dwc_read_datafifo32(_core_if->data_fifo[0]); ++} ++ ++ ++/** ++ * This function enables EP0 OUT to receive SETUP packets and configures EP0 ++ * IN for transmitting packets. It is normally called when the ++ * "Enumeration Done" interrupt occurs. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP0 data. ++ */ ++void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ dsts_data_t dsts; ++ depctl_data_t diepctl; ++ depctl_data_t doepctl; ++ dctl_data_t dctl ={.d32=0}; ++ ++ /* Read the Device Status and Endpoint 0 Control registers */ ++ dsts.d32 = dwc_read_reg32(&dev_if->dev_global_regs->dsts); ++ diepctl.d32 = dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl); ++ doepctl.d32 = dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl); ++ ++ /* Set the MPS of the IN EP based on the enumeration speed */ ++ switch (dsts.b.enumspd) { ++ case DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ: ++ case DWC_DSTS_ENUMSPD_FS_PHY_48MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_64; ++ break; ++ case DWC_DSTS_ENUMSPD_LS_PHY_6MHZ: ++ diepctl.b.mps = DWC_DEP0CTL_MPS_8; ++ break; ++ } ++ ++ dwc_write_reg32(&dev_if->in_ep_regs[0]->diepctl, diepctl.d32); ++ ++ /* Enable OUT EP for receive */ ++ doepctl.b.epena = 1; ++ dwc_write_reg32(&dev_if->out_ep_regs[0]->doepctl, doepctl.d32); ++ ++#ifdef VERBOSE ++ DWC_DEBUGPL(DBG_PCDV,"doepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->out_ep_regs[0]->doepctl)); ++ DWC_DEBUGPL(DBG_PCDV,"diepctl0=%0x\n", ++ dwc_read_reg32(&dev_if->in_ep_regs[0]->diepctl)); ++#endif ++ dctl.b.cgnpinnak = 1; ++ dwc_modify_reg32(&dev_if->dev_global_regs->dctl, dctl.d32, dctl.d32); ++ DWC_DEBUGPL(DBG_PCDV,"dctl=%0x\n", ++ dwc_read_reg32(&dev_if->dev_global_regs->dctl)); ++} ++ ++/** ++ * This function activates an EP. The Device EP control register for ++ * the EP is configured as defined in the ep structure. Note: This ++ * function is not used for EP0. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to activate. ++ */ ++void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ depctl_data_t depctl; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32=0}; ++ ++ DWC_DEBUGPL(DBG_PCDV, "%s() EP%d-%s\n", __func__, _ep->num, ++ (_ep->is_in?"IN":"OUT")); ++ ++ /* Read DEPCTLn register */ ++ if (_ep->is_in == 1) { ++ addr = &dev_if->in_ep_regs[_ep->num]->diepctl; ++ daintmsk.ep.in = 1<<_ep->num; ++ } else { ++ addr = &dev_if->out_ep_regs[_ep->num]->doepctl; ++ daintmsk.ep.out = 1<<_ep->num; ++ } ++ ++ /* If the EP is already active don't change the EP Control ++ * register. */ ++ depctl.d32 = dwc_read_reg32(addr); ++ if (!depctl.b.usbactep) { ++ depctl.b.mps = _ep->maxpacket; ++ depctl.b.eptype = _ep->type; ++ depctl.b.txfnum = _ep->tx_fifo_num; ++ ++ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ depctl.b.setd0pid = 1; // ??? ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ depctl.b.usbactep = 1; ++ ++ dwc_write_reg32(addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCDV,"DEPCTL=%08x\n", dwc_read_reg32(addr)); ++ } ++ ++ ++ /* Enable the Interrupt for this EP */ ++ dwc_modify_reg32(&dev_if->dev_global_regs->daintmsk, ++ 0, daintmsk.d32); ++ DWC_DEBUGPL(DBG_PCDV,"DAINTMSK=%0x\n", ++ dwc_read_reg32(&dev_if->dev_global_regs->daintmsk)); ++ _ep->stall_clear_flag = 0; ++ return; ++} ++ ++/** ++ * This function deactivates an EP. This is done by clearing the USB Active ++ * EP bit in the Device EP control register. Note: This function is not used ++ * for EP0. EP0 cannot be deactivated. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to deactivate. ++ */ ++void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ depctl_data_t depctl ={.d32 = 0}; ++ volatile uint32_t *addr; ++ daint_data_t daintmsk = {.d32=0}; ++ ++ /* Read DEPCTLn register */ ++ if (_ep->is_in == 1) { ++ addr = &_core_if->dev_if->in_ep_regs[_ep->num]->diepctl; ++ daintmsk.ep.in = 1<<_ep->num; ++ } else { ++ addr = &_core_if->dev_if->out_ep_regs[_ep->num]->doepctl; ++ daintmsk.ep.out = 1<<_ep->num; ++ } ++ ++ depctl.b.usbactep = 0; ++ dwc_write_reg32(addr, depctl.d32); ++ ++ /* Disable the Interrupt for this EP */ ++ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->daintmsk, ++ daintmsk.d32, 0); ++ ++ return; ++} ++ ++/** ++ * This function does the setup for a data transfer for an EP and ++ * starts the transfer. For an IN transfer, the packets will be ++ * loaded into the appropriate Tx FIFO in the ISR. For OUT transfers, ++ * the packets are unloaded from the Rx FIFO in the ISR. the ISR. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to start the transfer on. ++ */ ++void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ /** @todo Refactor this funciton to check the transfer size ++ * count value does not execed the number bits in the Transfer ++ * count register. */ ++ depctl_data_t depctl; ++ deptsiz_data_t deptsiz; ++ gintmsk_data_t intr_mask = { .d32 = 0}; ++ ++#ifdef CHECK_PACKET_COUNTER_WIDTH ++ const uint32_t MAX_XFER_SIZE = ++ _core_if->core_params->max_transfer_size; ++ const uint32_t MAX_PKT_COUNT = ++ _core_if->core_params->max_packet_count; ++ uint32_t num_packets; ++ uint32_t transfer_len; ++ dwc_otg_dev_out_ep_regs_t *out_regs = ++ _core_if->dev_if->out_ep_regs[_ep->num]; ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ _core_if->dev_if->in_ep_regs[_ep->num]; ++ gnptxsts_data_t txstatus; ++ ++ int lvl = SET_DEBUG_LEVEL(DBG_PCD); ++ ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p\n", ++ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, ++ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); ++ ++ transfer_len = _ep->xfer_len - _ep->xfer_count; ++ if (transfer_len > MAX_XFER_SIZE) { ++ transfer_len = MAX_XFER_SIZE; ++ } ++ if (transfer_len == 0) { ++ num_packets = 1; ++ /* OUT EP to recieve Zero-length packet set transfer ++ * size to maxpacket size. */ ++ if (!_ep->is_in) { ++ transfer_len = _ep->maxpacket; ++ } ++ } else { ++ num_packets = ++ (transfer_len + _ep->maxpacket - 1) / _ep->maxpacket; ++ if (num_packets > MAX_PKT_COUNT) { ++ num_packets = MAX_PKT_COUNT; ++ } ++ } ++ DWC_DEBUGPL(DBG_PCD, "transfer_len=%d #pckt=%d\n", transfer_len, ++ num_packets); ++ ++ deptsiz.b.xfersize = transfer_len; ++ deptsiz.b.pktcnt = num_packets; ++ ++ /* IN endpoint */ ++ if (_ep->is_in == 1) { ++ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); ++ } else {/* OUT endpoint */ ++ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ /* IN endpoint */ ++ if (_ep->is_in == 1) { ++ txstatus.d32 = ++ dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); ++ if (txstatus.b.nptxqspcavail == 0) { ++ DWC_DEBUGPL(DBG_ANY, "TX Queue Full (0x%0x)\n", ++ txstatus.d32); ++ return; ++ } ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (_core_if->dma_enable) { ++ dwc_write_reg32(&in_regs->diepdma, (uint32_t) _ep->xfer_buff); ++ } else { ++ if (_core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32( &_core_if->core_global_regs->gintsts, ++ intr_mask.d32, 0); ++ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (_ep->xfer_len > 0 && ++ _ep->type != DWC_OTG_EP_TYPE_ISOC) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = (0x1 << _ep->num); ++ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> ++ dtknqr4_fifoemptymsk,0, fifoemptymsk); ++ } ++ } ++ } ++ } else { /* OUT endpoint */ ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ if (_core_if->dma_enable) { ++ dwc_write_reg32(&out_regs->doepdma,(uint32_t) _ep->xfer_buff); ++ } ++ } ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ dwc_read_reg32(&out_regs->doepctl), ++ dwc_read_reg32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), ++ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); ++ ++ SET_DEBUG_LEVEL(lvl); ++#endif ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s()\n", __func__); ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p\n", ++ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, ++ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff); ++ ++ /* IN endpoint */ ++ if (_ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[_ep->num]; ++ gnptxsts_data_t gtxstatus; ++ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); ++ if (_core_if->en_multiple_tx_fifo == 0 && ++ gtxstatus.b.nptxqspcavail == 0) { ++#ifdef DEBUG ++ DWC_PRINT("TX Queue Full (0x%0x)\n", gtxstatus.d32); ++#endif ++ //return; ++ MDELAY(100); //james ++ } ++ ++ depctl.d32 = dwc_read_reg32(&(in_regs->diepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(in_regs->dieptsiz)); ++ ++ /* Zero Length Packet? */ ++ if (_ep->xfer_len == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = _ep->xfer_len; ++ deptsiz.b.pktcnt = (_ep->xfer_len - 1 + _ep->maxpacket) / _ep->maxpacket; ++ } ++ ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (_core_if->dma_enable) { ++#if 1 // winder ++ dma_cache_wback_inv((unsigned long) _ep->xfer_buff, _ep->xfer_len); // winder ++ dwc_write_reg32 (&(in_regs->diepdma), ++ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder ++#else ++ dwc_write_reg32 (&(in_regs->diepdma), ++ (uint32_t)_ep->dma_addr); ++#endif ++ } else { ++ if (_ep->type != DWC_OTG_EP_TYPE_ISOC) { ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, ++ * or the Tx FIFO epmty interrupt in dedicated Tx FIFO mode, ++ * the data will be written into the fifo by the ISR. ++ */ ++ if (_core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32( &_core_if->core_global_regs->gintsts, ++ intr_mask.d32, 0); ++ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (_ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk = 1 << _ep->num; ++ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs-> ++ dtknqr4_fifoemptymsk,0,fifoemptymsk); ++ } ++ } ++ } ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ if (_core_if->dma_enable) { ++ depctl.d32 = dwc_read_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl); ++ depctl.b.nextep = _ep->num; ++ dwc_write_reg32 (&_core_if->dev_if->in_ep_regs[0]->diepctl, depctl.d32); ++ ++ } ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; ++ ++ depctl.d32 = dwc_read_reg32(&(out_regs->doepctl)); ++ deptsiz.d32 = dwc_read_reg32(&(out_regs->doeptsiz)); ++ ++ /* Program the transfer size and packet count as follows: ++ * ++ * pktcnt = N ++ * xfersize = N * maxpacket ++ */ ++ if (_ep->xfer_len == 0) { ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = _ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; ++ } ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ ++ DWC_DEBUGPL(DBG_PCDV, "ep%d xfersize=%d pktcnt=%d\n", ++ _ep->num, deptsiz.b.xfersize, deptsiz.b.pktcnt); ++ ++ if (_core_if->dma_enable) { ++#if 1 // winder ++ dwc_write_reg32 (&(out_regs->doepdma), ++ CPHYSADDR((uint32_t)_ep->xfer_buff)); // winder ++#else ++ dwc_write_reg32 (&(out_regs->doepdma), ++ (uint32_t)_ep->dma_addr); ++#endif ++ } ++ ++ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ /** @todo NGS: dpid is read-only. Use setd0pid ++ * or setd1pid. */ ++ if (_ep->even_odd_frame) { ++ depctl.b.setd1pid = 1; ++ } else { ++ depctl.b.setd0pid = 1; ++ } ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ ++ dwc_write_reg32(&out_regs->doepctl, depctl.d32); ++ ++ DWC_DEBUGPL(DBG_PCD, "DOEPCTL=%08x DOEPTSIZ=%08x\n", ++ dwc_read_reg32(&out_regs->doepctl), ++ dwc_read_reg32(&out_regs->doeptsiz)); ++ DWC_DEBUGPL(DBG_PCD, "DAINTMSK=%08x GINTMSK=%08x\n", ++ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk), ++ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); ++ } ++} ++ ++ ++/** ++ * This function does the setup for a data transfer for EP0 and starts ++ * the transfer. For an IN transfer, the packets will be loaded into ++ * the appropriate Tx FIFO in the ISR. For OUT transfers, the packets are ++ * unloaded from the Rx FIFO in the ISR. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP0 data. ++ */ ++void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ volatile depctl_data_t depctl; ++ volatile deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = { .d32 = 0}; ++ ++ DWC_DEBUGPL(DBG_PCD, "ep%d-%s xfer_len=%d xfer_cnt=%d " ++ "xfer_buff=%p start_xfer_buff=%p total_len=%d\n", ++ _ep->num, (_ep->is_in?"IN":"OUT"), _ep->xfer_len, ++ _ep->xfer_count, _ep->xfer_buff, _ep->start_xfer_buff, ++ _ep->total_len); ++ _ep->total_len = _ep->xfer_len; ++ ++ /* IN endpoint */ ++ if (_ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t * in_regs = _core_if->dev_if->in_ep_regs[0]; ++ gnptxsts_data_t gtxstatus; ++ gtxstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); ++ if (_core_if->en_multiple_tx_fifo == 0 && ++ gtxstatus.b.nptxqspcavail == 0) { ++#ifdef DEBUG ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ DWC_DEBUGPL(DBG_PCD,"DIEPCTL0=%0x\n", ++ dwc_read_reg32(&in_regs->diepctl)); ++ DWC_DEBUGPL(DBG_PCD, "DIEPTSIZ0=%0x (sz=%d, pcnt=%d)\n", ++ deptsiz.d32, deptsiz.b.xfersize,deptsiz.b.pktcnt); ++ DWC_PRINT("TX Queue or FIFO Full (0x%0x)\n", gtxstatus.d32); ++#endif /* */ ++ printk("TX Queue or FIFO Full!!!!\n"); // test-only ++ //return; ++ MDELAY(100); //james ++ } ++ ++ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ ++ /* Zero Length Packet? */ ++ if (_ep->xfer_len == 0) { ++ deptsiz.b.xfersize = 0; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ if (_ep->xfer_len > _ep->maxpacket) { ++ _ep->xfer_len = _ep->maxpacket; ++ deptsiz.b.xfersize = _ep->maxpacket; ++ } ++ else { ++ deptsiz.b.xfersize = _ep->xfer_len; ++ } ++ deptsiz.b.pktcnt = 1; ++ ++ } ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (_core_if->dma_enable) { ++ dwc_write_reg32(&(in_regs->diepdma), (uint32_t) _ep->dma_addr); ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!_core_if->dma_enable) { ++ if (_core_if->en_multiple_tx_fifo == 0) { ++ intr_mask.b.nptxfempty = 1; ++ dwc_modify_reg32(&_core_if->core_global_regs->gintsts, intr_mask.d32, 0); ++ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, intr_mask.d32, ++ intr_mask.d32); ++ } else { ++ /* Enable the Tx FIFO Empty Interrupt for this EP */ ++ if (_ep->xfer_len > 0) { ++ uint32_t fifoemptymsk = 0; ++ fifoemptymsk |= 1 << _ep->num; ++ dwc_modify_reg32(&_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk, ++ 0, fifoemptymsk); ++ } ++ ++ } ++ } ++ } else { ++ /* OUT endpoint */ ++ dwc_otg_dev_out_ep_regs_t * out_regs = _core_if->dev_if->out_ep_regs[_ep->num]; ++ ++ depctl.d32 = dwc_read_reg32(&out_regs->doepctl); ++ deptsiz.d32 = dwc_read_reg32(&out_regs->doeptsiz); ++ ++ /* Program the transfer size and packet count as follows: ++ * xfersize = N * (maxpacket + 4 - (maxpacket % 4)) ++ * pktcnt = N */ ++ if (_ep->xfer_len == 0) { ++ /* Zero Length Packet */ ++ deptsiz.b.xfersize = _ep->maxpacket; ++ deptsiz.b.pktcnt = 1; ++ } else { ++ deptsiz.b.pktcnt = (_ep->xfer_len + (_ep->maxpacket - 1)) / _ep->maxpacket; ++ deptsiz.b.xfersize = deptsiz.b.pktcnt * _ep->maxpacket; ++ } ++ ++ dwc_write_reg32(&out_regs->doeptsiz, deptsiz.d32); ++ DWC_DEBUGPL(DBG_PCDV, "len=%d xfersize=%d pktcnt=%d\n", ++ _ep->xfer_len, deptsiz.b.xfersize,deptsiz.b.pktcnt); ++ ++ if (_core_if->dma_enable) { ++ dwc_write_reg32(&(out_regs->doepdma), (uint32_t) _ep->dma_addr); ++ } ++ ++ /* EP enable */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32 (&(out_regs->doepctl), depctl.d32); ++ } ++} ++ ++/** ++ * This function continues control IN transfers started by ++ * dwc_otg_ep0_start_transfer, when the transfer does not fit in a ++ * single packet. NOTE: The DIEPCTL0/DOEPCTL0 registers only have one ++ * bit for the packet count. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP0 data. ++ */ ++void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ depctl_data_t depctl; ++ deptsiz0_data_t deptsiz; ++ gintmsk_data_t intr_mask = { .d32 = 0}; ++ ++ if (_ep->is_in == 1) { ++ dwc_otg_dev_in_ep_regs_t *in_regs = ++ _core_if->dev_if->in_ep_regs[0]; ++ gnptxsts_data_t tx_status = {.d32 = 0}; ++ ++ tx_status.d32 = dwc_read_reg32( &_core_if->core_global_regs->gnptxsts ); ++ /** @todo Should there be check for room in the Tx ++ * Status Queue. If not remove the code above this comment. */ ++ ++ depctl.d32 = dwc_read_reg32(&in_regs->diepctl); ++ deptsiz.d32 = dwc_read_reg32(&in_regs->dieptsiz); ++ ++ /* Program the transfer size and packet count ++ * as follows: xfersize = N * maxpacket + ++ * short_packet pktcnt = N + (short_packet ++ * exist ? 1 : 0) ++ */ ++ deptsiz.b.xfersize = (_ep->total_len - _ep->xfer_count) > _ep->maxpacket ? _ep->maxpacket : ++ (_ep->total_len - _ep->xfer_count); ++ deptsiz.b.pktcnt = 1; ++ _ep->xfer_len += deptsiz.b.xfersize; ++ ++ dwc_write_reg32(&in_regs->dieptsiz, deptsiz.d32); ++ DWC_DEBUGPL(DBG_PCDV, "IN len=%d xfersize=%d pktcnt=%d [%08x]\n", ++ _ep->xfer_len, ++ deptsiz.b.xfersize, deptsiz.b.pktcnt, deptsiz.d32); ++ ++ /* Write the DMA register */ ++ if (_core_if->hwcfg2.b.architecture == DWC_INT_DMA_ARCH) { ++ dwc_write_reg32 (&(in_regs->diepdma), ++ CPHYSADDR((uint32_t)_ep->dma_addr)); // winder ++ } ++ ++ /* EP enable, IN data in FIFO */ ++ depctl.b.cnak = 1; ++ depctl.b.epena = 1; ++ dwc_write_reg32(&in_regs->diepctl, depctl.d32); ++ ++ /** ++ * Enable the Non-Periodic Tx FIFO empty interrupt, the ++ * data will be written into the fifo by the ISR. ++ */ ++ if (!_core_if->dma_enable) { ++ /* First clear it from GINTSTS */ ++ intr_mask.b.nptxfempty = 1; ++ dwc_write_reg32( &_core_if->core_global_regs->gintsts, ++ intr_mask.d32 ); ++ ++ dwc_modify_reg32( &_core_if->core_global_regs->gintmsk, ++ intr_mask.d32, intr_mask.d32); ++ } ++ ++ } ++ ++} ++ ++#ifdef DEBUG ++void dump_msg(const u8 *buf, unsigned int length) ++{ ++ unsigned int start, num, i; ++ char line[52], *p; ++ ++ if (length >= 512) ++ return; ++ start = 0; ++ while (length > 0) { ++ num = min(length, 16u); ++ p = line; ++ for (i = 0; i < num; ++i) { ++ if (i == 8) ++ *p++ = ' '; ++ sprintf(p, " %02x", buf[i]); ++ p += 3; ++ } ++ *p = 0; ++ DWC_PRINT( "%6x: %s\n", start, line); ++ buf += num; ++ start += num; ++ length -= num; ++ } ++} ++#else ++static inline void dump_msg(const u8 *buf, unsigned int length) ++{ ++} ++#endif ++ ++/** ++ * This function writes a packet into the Tx FIFO associated with the ++ * EP. For non-periodic EPs the non-periodic Tx FIFO is written. For ++ * periodic EPs the periodic Tx FIFO associated with the EP is written ++ * with all packets for the next micro-frame. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to write packet for. ++ * @param _dma Indicates if DMA is being used. ++ */ ++void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma) ++{ ++ /** ++ * The buffer is padded to DWORD on a per packet basis in ++ * slave/dma mode if the MPS is not DWORD aligned. The last ++ * packet, if short, is also padded to a multiple of DWORD. ++ * ++ * ep->xfer_buff always starts DWORD aligned in memory and is a ++ * multiple of DWORD in length ++ * ++ * ep->xfer_len can be any number of bytes ++ * ++ * ep->xfer_count is a multiple of ep->maxpacket until the last ++ * packet ++ * ++ * FIFO access is DWORD */ ++ ++ uint32_t i; ++ uint32_t byte_count; ++ uint32_t dword_count; ++ uint32_t *fifo; ++ uint32_t *data_buff = (uint32_t *)_ep->xfer_buff; ++ ++ //DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p)\n", __func__, _core_if, _ep); ++ if (_ep->xfer_count >= _ep->xfer_len) { ++ DWC_WARN("%s() No data for EP%d!!!\n", __func__, _ep->num); ++ return; ++ } ++ ++ /* Find the byte length of the packet either short packet or MPS */ ++ if ((_ep->xfer_len - _ep->xfer_count) < _ep->maxpacket) { ++ byte_count = _ep->xfer_len - _ep->xfer_count; ++ } ++ else { ++ byte_count = _ep->maxpacket; ++ } ++ ++ /* Find the DWORD length, padded by extra bytes as neccessary if MPS ++ * is not a multiple of DWORD */ ++ dword_count = (byte_count + 3) / 4; ++ ++#ifdef VERBOSE ++ dump_msg(_ep->xfer_buff, byte_count); ++#endif ++ if (_ep->type == DWC_OTG_EP_TYPE_ISOC) { ++ /**@todo NGS Where are the Periodic Tx FIFO addresses ++ * intialized? What should this be? */ ++ fifo = _core_if->data_fifo[_ep->tx_fifo_num]; ++ } else { ++ fifo = _core_if->data_fifo[_ep->num]; ++ } ++ ++ DWC_DEBUGPL((DBG_PCDV|DBG_CILV), "fifo=%p buff=%p *p=%08x bc=%d\n", ++ fifo, data_buff, *data_buff, byte_count); ++ ++ ++ if (!_dma) { ++ for (i=0; i<dword_count; i++, data_buff++) { ++ dwc_write_reg32( fifo, *data_buff ); ++ } ++ } ++ ++ _ep->xfer_count += byte_count; ++ _ep->xfer_buff += byte_count; ++#if 1 // winder, why do we need this?? ++ _ep->dma_addr += byte_count; ++#endif ++} ++ ++/** ++ * Set the EP STALL. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to set the stall on. ++ */ ++void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, ++ (_ep->is_in?"IN":"OUT")); ++ ++ if (_ep->is_in == 1) { ++ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* set the disable and stall bits */ ++ if (depctl.b.epena) { ++ depctl.b.epdis = 1; ++ } ++ depctl.b.stall = 1; ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ ++ } else { ++ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* set the stall bit */ ++ depctl.b.stall = 1; ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ } ++ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); ++ return; ++} ++ ++/** ++ * Clear the EP STALL. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _ep The EP to clear stall from. ++ */ ++void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep) ++{ ++ depctl_data_t depctl; ++ volatile uint32_t *depctl_addr; ++ ++ DWC_DEBUGPL(DBG_PCD, "%s ep%d-%s\n", __func__, _ep->num, ++ (_ep->is_in?"IN":"OUT")); ++ ++ if (_ep->is_in == 1) { ++ depctl_addr = &(_core_if->dev_if->in_ep_regs[_ep->num]->diepctl); ++ } else { ++ depctl_addr = &(_core_if->dev_if->out_ep_regs[_ep->num]->doepctl); ++ } ++ ++ depctl.d32 = dwc_read_reg32(depctl_addr); ++ ++ /* clear the stall bits */ ++ depctl.b.stall = 0; ++ ++ /* ++ * USB Spec 9.4.5: For endpoints using data toggle, regardless ++ * of whether an endpoint has the Halt feature set, a ++ * ClearFeature(ENDPOINT_HALT) request always results in the ++ * data toggle being reinitialized to DATA0. ++ */ ++ if (_ep->type == DWC_OTG_EP_TYPE_INTR || ++ _ep->type == DWC_OTG_EP_TYPE_BULK) { ++ depctl.b.setd0pid = 1; /* DATA0 */ ++ } ++ ++ dwc_write_reg32(depctl_addr, depctl.d32); ++ DWC_DEBUGPL(DBG_PCD,"DEPCTL=%0x\n",dwc_read_reg32(depctl_addr)); ++ return; ++} ++ ++/** ++ * This function reads a packet from the Rx FIFO into the destination ++ * buffer. To read SETUP data use dwc_otg_read_setup_packet. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _dest Destination buffer for the packet. ++ * @param _bytes Number of bytes to copy to the destination. ++ */ ++void dwc_otg_read_packet(dwc_otg_core_if_t *_core_if, ++ uint8_t *_dest, ++ uint16_t _bytes) ++{ ++ int i; ++ int word_count = (_bytes + 3) / 4; ++ ++ volatile uint32_t *fifo = _core_if->data_fifo[0]; ++ uint32_t *data_buff = (uint32_t *)_dest; ++ ++ /** ++ * @todo Account for the case where _dest is not dword aligned. This ++ * requires reading data from the FIFO into a uint32_t temp buffer, ++ * then moving it into the data buffer. ++ */ ++ ++ DWC_DEBUGPL((DBG_PCDV | DBG_CILV), "%s(%p,%p,%d)\n", __func__, ++ _core_if, _dest, _bytes); ++ ++ for (i=0; i<word_count; i++, data_buff++) { ++ *data_buff = dwc_read_reg32(fifo); ++ } ++ ++ return; ++} ++ ++ ++#ifdef DEBUG ++/** ++ * This functions reads the device registers and prints them ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINT("Device Global Registers\n"); ++ addr=&_core_if->dev_if->dev_global_regs->dcfg; ++ DWC_PRINT("DCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->dctl; ++ DWC_PRINT("DCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->dsts; ++ DWC_PRINT("DSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->diepmsk; ++ DWC_PRINT("DIEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->doepmsk; ++ DWC_PRINT("DOEPMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->daint; ++ DWC_PRINT("DAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->dev_global_regs->dtknqr1; ++ DWC_PRINT("DTKNQR1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ if (_core_if->hwcfg2.b.dev_token_q_depth > 6) { ++ addr=&_core_if->dev_if->dev_global_regs->dtknqr2; ++ DWC_PRINT("DTKNQR2 @0x%08X : 0x%08X\n", ++ (uint32_t)addr,dwc_read_reg32(addr)); ++ } ++ ++ addr=&_core_if->dev_if->dev_global_regs->dvbusdis; ++ DWC_PRINT("DVBUSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ ++ addr=&_core_if->dev_if->dev_global_regs->dvbuspulse; ++ DWC_PRINT("DVBUSPULSE @0x%08X : 0x%08X\n", ++ (uint32_t)addr,dwc_read_reg32(addr)); ++ ++ if (_core_if->hwcfg2.b.dev_token_q_depth > 14) { ++ addr = &_core_if->dev_if->dev_global_regs->dtknqr3_dthrctl; ++ DWC_PRINT("DTKNQR3 @0x%08X : 0x%08X\n", ++ (uint32_t)addr, dwc_read_reg32(addr)); ++ } ++ ++ if (_core_if->hwcfg2.b.dev_token_q_depth > 22) { ++ addr = &_core_if->dev_if->dev_global_regs->dtknqr4_fifoemptymsk; ++ DWC_PRINT("DTKNQR4 @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ } ++ for (i = 0; i <= _core_if->dev_if->num_in_eps; i++) { ++ DWC_PRINT("Device IN EP %d Registers\n", i); ++ addr=&_core_if->dev_if->in_ep_regs[i]->diepctl; ++ DWC_PRINT("DIEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->in_ep_regs[i]->diepint; ++ DWC_PRINT("DIEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->in_ep_regs[i]->dieptsiz; ++ DWC_PRINT("DIETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->in_ep_regs[i]->diepdma; ++ DWC_PRINT("DIEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ ++addr = &_core_if->dev_if->in_ep_regs[i]->dtxfsts; ++ DWC_PRINT("DTXFSTS @0x%08X : 0x%08X\n", (uint32_t) addr, ++ dwc_read_reg32(addr)); ++ } ++ for (i = 0; i <= _core_if->dev_if->num_out_eps; i++) { ++ DWC_PRINT("Device OUT EP %d Registers\n", i); ++ addr=&_core_if->dev_if->out_ep_regs[i]->doepctl; ++ DWC_PRINT("DOEPCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->out_ep_regs[i]->doepfn; ++ DWC_PRINT("DOEPFN @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->out_ep_regs[i]->doepint; ++ DWC_PRINT("DOEPINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->out_ep_regs[i]->doeptsiz; ++ DWC_PRINT("DOETSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->dev_if->out_ep_regs[i]->doepdma; ++ DWC_PRINT("DOEPDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ } ++ return; ++} ++ ++/** ++ * This function reads the host registers and prints them ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINT("Host Global Registers\n"); ++ addr=&_core_if->host_if->host_global_regs->hcfg; ++ DWC_PRINT("HCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->host_global_regs->hfir; ++ DWC_PRINT("HFIR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->host_global_regs->hfnum; ++ DWC_PRINT("HFNUM @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->host_global_regs->hptxsts; ++ DWC_PRINT("HPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->host_global_regs->haint; ++ DWC_PRINT("HAINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->host_global_regs->haintmsk; ++ DWC_PRINT("HAINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=_core_if->host_if->hprt0; ++ DWC_PRINT("HPRT0 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ ++ for (i=0; i<_core_if->core_params->host_channels; i++) { ++ DWC_PRINT("Host Channel %d Specific Registers\n", i); ++ addr=&_core_if->host_if->hc_regs[i]->hcchar; ++ DWC_PRINT("HCCHAR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->hc_regs[i]->hcsplt; ++ DWC_PRINT("HCSPLT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->hc_regs[i]->hcint; ++ DWC_PRINT("HCINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->hc_regs[i]->hcintmsk; ++ DWC_PRINT("HCINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->hc_regs[i]->hctsiz; ++ DWC_PRINT("HCTSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->host_if->hc_regs[i]->hcdma; ++ DWC_PRINT("HCDMA @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ ++ } ++ return; ++} ++ ++/** ++ * This function reads the core global registers and prints them ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if) ++{ ++ int i; ++ volatile uint32_t *addr; ++ ++ DWC_PRINT("Core Global Registers\n"); ++ addr=&_core_if->core_global_regs->gotgctl; ++ DWC_PRINT("GOTGCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gotgint; ++ DWC_PRINT("GOTGINT @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gahbcfg; ++ DWC_PRINT("GAHBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gusbcfg; ++ DWC_PRINT("GUSBCFG @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->grstctl; ++ DWC_PRINT("GRSTCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gintsts; ++ DWC_PRINT("GINTSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gintmsk; ++ DWC_PRINT("GINTMSK @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->grxstsr; ++ DWC_PRINT("GRXSTSR @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ //addr=&_core_if->core_global_regs->grxstsp; ++ //DWC_PRINT("GRXSTSP @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->grxfsiz; ++ DWC_PRINT("GRXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gnptxfsiz; ++ DWC_PRINT("GNPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gnptxsts; ++ DWC_PRINT("GNPTXSTS @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gi2cctl; ++ DWC_PRINT("GI2CCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gpvndctl; ++ DWC_PRINT("GPVNDCTL @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->ggpio; ++ DWC_PRINT("GGPIO @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->guid; ++ DWC_PRINT("GUID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->gsnpsid; ++ DWC_PRINT("GSNPSID @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->ghwcfg1; ++ DWC_PRINT("GHWCFG1 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->ghwcfg2; ++ DWC_PRINT("GHWCFG2 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->ghwcfg3; ++ DWC_PRINT("GHWCFG3 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->ghwcfg4; ++ DWC_PRINT("GHWCFG4 @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ addr=&_core_if->core_global_regs->hptxfsiz; ++ DWC_PRINT("HPTXFSIZ @0x%08X : 0x%08X\n",(uint32_t)addr,dwc_read_reg32(addr)); ++ ++ for (i=0; i<_core_if->hwcfg4.b.num_dev_perio_in_ep; i++) { ++ addr=&_core_if->core_global_regs->dptxfsiz_dieptxf[i]; ++ DWC_PRINT("DPTXFSIZ[%d] @0x%08X : 0x%08X\n",i,(uint32_t)addr,dwc_read_reg32(addr)); ++ } ++ ++} ++#endif ++ ++/** ++ * Flush a Tx FIFO. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _num Tx FIFO to flush. ++ */ ++extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, ++ const int _num ) ++{ ++ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; ++ volatile grstctl_t greset = { .d32 = 0}; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "Flush Tx FIFO %d\n", _num); ++ ++ greset.b.txfflsh = 1; ++ greset.b.txfnum = _num; ++ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); ++ ++ do { ++ greset.d32 = dwc_read_reg32( &global_regs->grstctl); ++ if (++count > 10000){ ++ DWC_WARN("%s() HANG! GRSTCTL=%0x GNPTXSTS=0x%08x\n", ++ __func__, greset.d32, ++ dwc_read_reg32( &global_regs->gnptxsts)); ++ break; ++ } ++ ++ udelay(1); ++ } while (greset.b.txfflsh == 1); ++ /* Wait for 3 PHY Clocks*/ ++ UDELAY(1); ++} ++ ++/** ++ * Flush Rx FIFO. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ) ++{ ++ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; ++ volatile grstctl_t greset = { .d32 = 0}; ++ int count = 0; ++ ++ DWC_DEBUGPL((DBG_CIL|DBG_PCDV), "%s\n", __func__); ++ /* ++ * ++ */ ++ greset.b.rxfflsh = 1; ++ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); ++ ++ do { ++ greset.d32 = dwc_read_reg32( &global_regs->grstctl); ++ if (++count > 10000){ ++ DWC_WARN("%s() HANG! GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ break; ++ } ++ } while (greset.b.rxfflsh == 1); ++ /* Wait for 3 PHY Clocks*/ ++ UDELAY(1); ++} ++ ++/** ++ * Do core a soft reset of the core. Be careful with this because it ++ * resets all the internal state machines of the core. ++ */ ++ ++void dwc_otg_core_reset(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = _core_if->core_global_regs; ++ volatile grstctl_t greset = { .d32 = 0}; ++ int count = 0; ++ ++ DWC_DEBUGPL(DBG_CILV, "%s\n", __func__); ++ /* Wait for AHB master IDLE state. */ ++ do { ++ UDELAY(10); ++ greset.d32 = dwc_read_reg32( &global_regs->grstctl); ++ if (++count > 100000){ ++ DWC_WARN("%s() HANG! AHB Idle GRSTCTL=%0x %x\n", __func__, ++ greset.d32, greset.b.ahbidle); ++ return; ++ } ++ } while (greset.b.ahbidle == 0); ++ ++// winder add. ++#if 1 ++ /* Note: Actually, I don't exactly why we need to put delay here. */ ++ MDELAY(100); ++#endif ++ /* Core Soft Reset */ ++ count = 0; ++ greset.b.csftrst = 1; ++ dwc_write_reg32( &global_regs->grstctl, greset.d32 ); ++// winder add. ++#if 1 ++ /* Note: Actually, I don't exactly why we need to put delay here. */ ++ MDELAY(100); ++#endif ++ do { ++ greset.d32 = dwc_read_reg32( &global_regs->grstctl); ++ if (++count > 10000){ ++ DWC_WARN("%s() HANG! Soft Reset GRSTCTL=%0x\n", __func__, ++ greset.d32); ++ break; ++ } ++ udelay(1); ++ } while (greset.b.csftrst == 1); ++ /* Wait for 3 PHY Clocks*/ ++ //DWC_PRINT("100ms\n"); ++ MDELAY(100); ++} ++ ++ ++ ++/** ++ * Register HCD callbacks. The callbacks are used to start and stop ++ * the HCD for interrupt processing. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _cb the HCD callback structure. ++ * @param _p pointer to be passed to callback function (usb_hcd*). ++ */ ++extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, ++ dwc_otg_cil_callbacks_t *_cb, ++ void *_p) ++{ ++ _core_if->hcd_cb = _cb; ++ _cb->p = _p; ++} ++ ++/** ++ * Register PCD callbacks. The callbacks are used to start and stop ++ * the PCD for interrupt processing. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ * @param _cb the PCD callback structure. ++ * @param _p pointer to be passed to callback function (pcd*). ++ */ ++extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, ++ dwc_otg_cil_callbacks_t *_cb, ++ void *_p) ++{ ++ _core_if->pcd_cb = _cb; ++ _cb->p = _p; ++} ++ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_cil.h +@@ -0,0 +1,911 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 631780 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_CIL_H__) ++#define __DWC_CIL_H__ ++ ++#include "dwc_otg_plat.h" ++ ++#include "dwc_otg_regs.h" ++#ifdef DEBUG ++#include "linux/timer.h" ++#endif ++ ++/* the OTG capabilities. */ ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 ++/* the maximum speed of operation in host and device mode. */ ++#define DWC_SPEED_PARAM_HIGH 0 ++#define DWC_SPEED_PARAM_FULL 1 ++/* the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. */ ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 ++/* the type of PHY interface to use. */ ++#define DWC_PHY_TYPE_PARAM_FS 0 ++#define DWC_PHY_TYPE_PARAM_UTMI 1 ++#define DWC_PHY_TYPE_PARAM_ULPI 2 ++/* whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. */ ++#define DWC_PHY_ULPI_INTERNAL_VBUS 0 ++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 ++/* EP type. */ ++ ++/** ++ * @file ++ * This file contains the interface to the Core Interface Layer. ++ */ ++ ++/** ++ * The <code>dwc_ep</code> structure represents the state of a single ++ * endpoint when acting in device mode. It contains the data items ++ * needed for an endpoint to be activated and transfer packets. ++ */ ++typedef struct dwc_ep { ++ /** EP number used for register address lookup */ ++ uint8_t num; ++ /** EP direction 0 = OUT */ ++ unsigned is_in : 1; ++ /** EP active. */ ++ unsigned active : 1; ++ ++ /** Periodic Tx FIFO # for IN EPs For INTR EP set to 0 to use non-periodic Tx FIFO ++ If dedicated Tx FIFOs are enabled for all IN Eps - Tx FIFO # FOR IN EPs*/ ++ unsigned tx_fifo_num : 4; ++ /** EP type: 0 - Control, 1 - ISOC, 2 - BULK, 3 - INTR */ ++ unsigned type : 2; ++#define DWC_OTG_EP_TYPE_CONTROL 0 ++#define DWC_OTG_EP_TYPE_ISOC 1 ++#define DWC_OTG_EP_TYPE_BULK 2 ++#define DWC_OTG_EP_TYPE_INTR 3 ++ ++ /** DATA start PID for INTR and BULK EP */ ++ unsigned data_pid_start : 1; ++ /** Frame (even/odd) for ISOC EP */ ++ unsigned even_odd_frame : 1; ++ /** Max Packet bytes */ ++ unsigned maxpacket : 11; ++ ++ /** @name Transfer state */ ++ /** @{ */ ++ ++ /** ++ * Pointer to the beginning of the transfer buffer -- do not modify ++ * during transfer. ++ */ ++ ++ uint32_t dma_addr; ++ ++ uint8_t *start_xfer_buff; ++ /** pointer to the transfer buffer */ ++ uint8_t *xfer_buff; ++ /** Number of bytes to transfer */ ++ unsigned xfer_len : 19; ++ /** Number of bytes transferred. */ ++ unsigned xfer_count : 19; ++ /** Sent ZLP */ ++ unsigned sent_zlp : 1; ++ /** Total len for control transfer */ ++ unsigned total_len : 19; ++ ++ /** stall clear flag */ ++ unsigned stall_clear_flag : 1; ++ ++ /** @} */ ++} dwc_ep_t; ++ ++/* ++ * Reasons for halting a host channel. ++ */ ++typedef enum dwc_otg_halt_status { ++ DWC_OTG_HC_XFER_NO_HALT_STATUS, ++ DWC_OTG_HC_XFER_COMPLETE, ++ DWC_OTG_HC_XFER_URB_COMPLETE, ++ DWC_OTG_HC_XFER_ACK, ++ DWC_OTG_HC_XFER_NAK, ++ DWC_OTG_HC_XFER_NYET, ++ DWC_OTG_HC_XFER_STALL, ++ DWC_OTG_HC_XFER_XACT_ERR, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN, ++ DWC_OTG_HC_XFER_BABBLE_ERR, ++ DWC_OTG_HC_XFER_DATA_TOGGLE_ERR, ++ DWC_OTG_HC_XFER_AHB_ERR, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, ++ DWC_OTG_HC_XFER_URB_DEQUEUE ++} dwc_otg_halt_status_e; ++ ++/** ++ * Host channel descriptor. This structure represents the state of a single ++ * host channel when acting in host mode. It contains the data items needed to ++ * transfer packets to an endpoint via a host channel. ++ */ ++typedef struct dwc_hc { ++ /** Host channel number used for register address lookup */ ++ uint8_t hc_num; ++ ++ /** Device to access */ ++ unsigned dev_addr : 7; ++ ++ /** EP to access */ ++ unsigned ep_num : 4; ++ ++ /** EP direction. 0: OUT, 1: IN */ ++ unsigned ep_is_in : 1; ++ ++ /** ++ * EP speed. ++ * One of the following values: ++ * - DWC_OTG_EP_SPEED_LOW ++ * - DWC_OTG_EP_SPEED_FULL ++ * - DWC_OTG_EP_SPEED_HIGH ++ */ ++ unsigned speed : 2; ++#define DWC_OTG_EP_SPEED_LOW 0 ++#define DWC_OTG_EP_SPEED_FULL 1 ++#define DWC_OTG_EP_SPEED_HIGH 2 ++ ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - DWC_OTG_EP_TYPE_CONTROL: 0 ++ * - DWC_OTG_EP_TYPE_ISOC: 1 ++ * - DWC_OTG_EP_TYPE_BULK: 2 ++ * - DWC_OTG_EP_TYPE_INTR: 3 ++ */ ++ unsigned ep_type : 2; ++ ++ /** Max packet size in bytes */ ++ unsigned max_packet : 11; ++ ++ /** ++ * PID for initial transaction. ++ * 0: DATA0,<br> ++ * 1: DATA2,<br> ++ * 2: DATA1,<br> ++ * 3: MDATA (non-Control EP), ++ * SETUP (Control EP) ++ */ ++ unsigned data_pid_start : 2; ++#define DWC_OTG_HC_PID_DATA0 0 ++#define DWC_OTG_HC_PID_DATA2 1 ++#define DWC_OTG_HC_PID_DATA1 2 ++#define DWC_OTG_HC_PID_MDATA 3 ++#define DWC_OTG_HC_PID_SETUP 3 ++ ++ /** Number of periodic transactions per (micro)frame */ ++ unsigned multi_count: 2; ++ ++ /** @name Transfer State */ ++ /** @{ */ ++ ++ /** Pointer to the current transfer buffer position. */ ++ uint8_t *xfer_buff; ++ /** Total number of bytes to transfer. */ ++ uint32_t xfer_len; ++ /** Number of bytes transferred so far. */ ++ uint32_t xfer_count; ++ /** Packet count at start of transfer.*/ ++ uint16_t start_pkt_count; ++ ++ /** ++ * Flag to indicate whether the transfer has been started. Set to 1 if ++ * it has been started, 0 otherwise. ++ */ ++ uint8_t xfer_started; ++ ++ /** ++ * Set to 1 to indicate that a PING request should be issued on this ++ * channel. If 0, process normally. ++ */ ++ uint8_t do_ping; ++ ++ /** ++ * Set to 1 to indicate that the error count for this transaction is ++ * non-zero. Set to 0 if the error count is 0. ++ */ ++ uint8_t error_state; ++ ++ /** ++ * Set to 1 to indicate that this channel should be halted the next ++ * time a request is queued for the channel. This is necessary in ++ * slave mode if no request queue space is available when an attempt ++ * is made to halt the channel. ++ */ ++ uint8_t halt_on_queue; ++ ++ /** ++ * Set to 1 if the host channel has been halted, but the core is not ++ * finished flushing queued requests. Otherwise 0. ++ */ ++ uint8_t halt_pending; ++ ++ /** ++ * Reason for halting the host channel. ++ */ ++ dwc_otg_halt_status_e halt_status; ++ ++ /* ++ * Split settings for the host channel ++ */ ++ uint8_t do_split; /**< Enable split for the channel */ ++ uint8_t complete_split; /**< Enable complete split */ ++ uint8_t hub_addr; /**< Address of high speed hub */ ++ ++ uint8_t port_addr; /**< Port of the low/full speed device */ ++ /** Split transaction position ++ * One of the following values: ++ * - DWC_HCSPLIT_XACTPOS_MID ++ * - DWC_HCSPLIT_XACTPOS_BEGIN ++ * - DWC_HCSPLIT_XACTPOS_END ++ * - DWC_HCSPLIT_XACTPOS_ALL */ ++ uint8_t xact_pos; ++ ++ /** Set when the host channel does a short read. */ ++ uint8_t short_read; ++ ++ /** ++ * Number of requests issued for this channel since it was assigned to ++ * the current transfer (not counting PINGs). ++ */ ++ uint8_t requests; ++ ++ /** ++ * Queue Head for the transfer being processed by this channel. ++ */ ++ struct dwc_otg_qh *qh; ++ ++ /** @} */ ++ ++ /** Entry in list of host channels. */ ++ struct list_head hc_list_entry; ++} dwc_hc_t; ++ ++/** ++ * The following parameters may be specified when starting the module. These ++ * parameters define how the DWC_otg controller should be configured. ++ * Parameter values are passed to the CIL initialization function ++ * dwc_otg_cil_init. ++ */ ++ ++typedef struct dwc_otg_core_params ++{ ++ int32_t opt; ++//#define dwc_param_opt_default 1 ++ /** ++ * Specifies the OTG capabilities. The driver will automatically ++ * detect the value for this parameter if none is specified. ++ * 0 - HNP and SRP capable (default) ++ * 1 - SRP Only capable ++ * 2 - No HNP/SRP capable ++ */ ++ int32_t otg_cap; ++#define DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE 0 ++#define DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE 1 ++#define DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE 2 ++//#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE ++ /** ++ * Specifies whether to use slave or DMA mode for accessing the data ++ * FIFOs. The driver will automatically detect the value for this ++ * parameter if none is specified. ++ * 0 - Slave ++ * 1 - DMA (default, if available) ++ */ ++ int32_t dma_enable; ++//#define dwc_param_dma_enable_default 1 ++ /** The DMA Burst size (applicable only for External DMA ++ * Mode). 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ */ ++ int32_t dma_burst_size; /* Translate this to GAHBCFG values */ ++//#define dwc_param_dma_burst_size_default 32 ++ /** ++ * Specifies the maximum speed of operation in host and device mode. ++ * The actual speed depends on the speed of the attached device and ++ * the value of phy_type. The actual speed depends on the speed of the ++ * attached device. ++ * 0 - High Speed (default) ++ * 1 - Full Speed ++ */ ++ int32_t speed; ++//#define dwc_param_speed_default 0 ++#define DWC_SPEED_PARAM_HIGH 0 ++#define DWC_SPEED_PARAM_FULL 1 ++ ++ /** Specifies whether low power mode is supported when attached ++ * to a Full Speed or Low Speed device in host mode. ++ * 0 - Don't support low power mode (default) ++ * 1 - Support low power mode ++ */ ++ int32_t host_support_fs_ls_low_power; ++//#define dwc_param_host_support_fs_ls_low_power_default 0 ++ /** Specifies the PHY clock rate in low power mode when connected to a ++ * Low Speed device in host mode. This parameter is applicable only if ++ * HOST_SUPPORT_FS_LS_LOW_POWER is enabled. If PHY_TYPE is set to FS ++ * then defaults to 6 MHZ otherwise 48 MHZ. ++ * ++ * 0 - 48 MHz ++ * 1 - 6 MHz ++ */ ++ int32_t host_ls_low_power_phy_clk; ++//#define dwc_param_host_ls_low_power_phy_clk_default 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ 0 ++#define DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ 1 ++ /** ++ * 0 - Use cC FIFO size parameters ++ * 1 - Allow dynamic FIFO sizing (default) ++ */ ++ int32_t enable_dynamic_fifo; ++//#define dwc_param_enable_dynamic_fifo_default 1 ++ /** Total number of 4-byte words in the data FIFO memory. This ++ * memory includes the Rx FIFO, non-periodic Tx FIFO, and periodic ++ * Tx FIFOs. ++ * 32 to 32768 (default 8192) ++ * Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ */ ++ int32_t data_fifo_size; ++//#define dwc_param_data_fifo_size_default 8192 ++ /** Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1064) ++ */ ++ int32_t dev_rx_fifo_size; ++//#define dwc_param_dev_rx_fifo_size_default 1064 ++ /** Number of 4-byte words in the non-periodic Tx FIFO in device mode ++ * when dynamic FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t dev_nperio_tx_fifo_size; ++//#define dwc_param_dev_nperio_tx_fifo_size_default 1024 ++ /** Number of 4-byte words in each of the periodic Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++//#define dwc_param_dev_perio_tx_fifo_size_default 256 ++ /** Number of 4-byte words in the Rx FIFO in host mode when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_rx_fifo_size; ++//#define dwc_param_host_rx_fifo_size_default 1024 ++ /** Number of 4-byte words in the non-periodic Tx FIFO in host mode ++ * when Dynamic FIFO sizing is enabled in the core. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_nperio_tx_fifo_size; ++//#define dwc_param_host_nperio_tx_fifo_size_default 1024 ++ /** Number of 4-byte words in the host periodic Tx FIFO when dynamic ++ * FIFO sizing is enabled. ++ * 16 to 32768 (default 1024) ++ */ ++ int32_t host_perio_tx_fifo_size; ++//#define dwc_param_host_perio_tx_fifo_size_default 1024 ++ /** The maximum transfer size supported in bytes. ++ * 2047 to 65,535 (default 65,535) ++ */ ++ int32_t max_transfer_size; ++//#define dwc_param_max_transfer_size_default 65535 ++ /** The maximum number of packets in a transfer. ++ * 15 to 511 (default 511) ++ */ ++ int32_t max_packet_count; ++//#define dwc_param_max_packet_count_default 511 ++ /** The number of host channel registers to use. ++ * 1 to 16 (default 12) ++ * Note: The FPGA configuration supports a maximum of 12 host channels. ++ */ ++ int32_t host_channels; ++//#define dwc_param_host_channels_default 12 ++ /** The number of endpoints in addition to EP0 available for device ++ * mode operations. ++ * 1 to 15 (default 6 IN and OUT) ++ * Note: The FPGA configuration supports a maximum of 6 IN and OUT ++ * endpoints in addition to EP0. ++ */ ++ int32_t dev_endpoints; ++//#define dwc_param_dev_endpoints_default 6 ++ /** ++ * Specifies the type of PHY interface to use. By default, the driver ++ * will automatically detect the phy_type. ++ * ++ * 0 - Full Speed PHY ++ * 1 - UTMI+ (default) ++ * 2 - ULPI ++ */ ++ int32_t phy_type; ++#define DWC_PHY_TYPE_PARAM_FS 0 ++#define DWC_PHY_TYPE_PARAM_UTMI 1 ++#define DWC_PHY_TYPE_PARAM_ULPI 2 ++//#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI ++ /** ++ * Specifies the UTMI+ Data Width. This parameter is ++ * applicable for a PHY_TYPE of UTMI+ or ULPI. (For a ULPI ++ * PHY_TYPE, this parameter indicates the data width between ++ * the MAC and the ULPI Wrapper.) Also, this parameter is ++ * applicable only if the OTG_HSPHY_WIDTH cC parameter was set ++ * to "8 and 16 bits", meaning that the core has been ++ * configured to work at either data path width. ++ * ++ * 8 or 16 bits (default 16) ++ */ ++ int32_t phy_utmi_width; ++//#define dwc_param_phy_utmi_width_default 16 ++ /** ++ * Specifies whether the ULPI operates at double or single ++ * data rate. This parameter is only applicable if PHY_TYPE is ++ * ULPI. ++ * ++ * 0 - single data rate ULPI interface with 8 bit wide data ++ * bus (default) ++ * 1 - double data rate ULPI interface with 4 bit wide data ++ * bus ++ */ ++ int32_t phy_ulpi_ddr; ++//#define dwc_param_phy_ulpi_ddr_default 0 ++ /** ++ * Specifies whether to use the internal or external supply to ++ * drive the vbus with a ULPI phy. ++ */ ++ int32_t phy_ulpi_ext_vbus; ++#define DWC_PHY_ULPI_INTERNAL_VBUS 0 ++#define DWC_PHY_ULPI_EXTERNAL_VBUS 1 ++//#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS ++ /** ++ * Specifies whether to use the I2Cinterface for full speed PHY. This ++ * parameter is only applicable if PHY_TYPE is FS. ++ * 0 - No (default) ++ * 1 - Yes ++ */ ++ int32_t i2c_enable; ++//#define dwc_param_i2c_enable_default 0 ++ ++ int32_t ulpi_fs_ls; ++//#define dwc_param_ulpi_fs_ls_default 0 ++ ++ int32_t ts_dline; ++//#define dwc_param_ts_dline_default 0 ++ ++ /** ++ * Specifies whether dedicated transmit FIFOs are ++ * enabled for non periodic IN endpoints in device mode ++ * 0 - No ++ * 1 - Yes ++ */ ++ int32_t en_multiple_tx_fifo; ++#define dwc_param_en_multiple_tx_fifo_default 1 ++ ++ /** Number of 4-byte words in each of the Tx FIFOs in device ++ * mode when dynamic FIFO sizing is enabled. ++ * 4 to 768 (default 256) ++ */ ++ uint32_t dev_tx_fifo_size[MAX_TX_FIFOS]; ++#define dwc_param_dev_tx_fifo_size_default 256 ++ ++ /** Thresholding enable flag- ++ * bit 0 - enable non-ISO Tx thresholding ++ * bit 1 - enable ISO Tx thresholding ++ * bit 2 - enable Rx thresholding ++ */ ++ uint32_t thr_ctl; ++#define dwc_param_thr_ctl_default 0 ++ ++ /** Thresholding length for Tx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t tx_thr_length; ++#define dwc_param_tx_thr_length_default 64 ++ ++ /** Thresholding length for Rx ++ * FIFOs in 32 bit DWORDs ++ */ ++ uint32_t rx_thr_length; ++#define dwc_param_rx_thr_length_default 64 ++} dwc_otg_core_params_t; ++ ++#ifdef DEBUG ++struct dwc_otg_core_if; ++typedef struct hc_xfer_info ++{ ++ struct dwc_otg_core_if *core_if; ++ dwc_hc_t *hc; ++} hc_xfer_info_t; ++#endif ++ ++/** ++ * The <code>dwc_otg_core_if</code> structure contains information needed to manage ++ * the DWC_otg controller acting in either host or device mode. It ++ * represents the programming view of the controller as a whole. ++ */ ++typedef struct dwc_otg_core_if ++{ ++ /** Parameters that define how the core should be configured.*/ ++ dwc_otg_core_params_t *core_params; ++ ++ /** Core Global registers starting at offset 000h. */ ++ dwc_otg_core_global_regs_t *core_global_regs; ++ ++ /** Device-specific information */ ++ dwc_otg_dev_if_t *dev_if; ++ /** Host-specific information */ ++ dwc_otg_host_if_t *host_if; ++ ++ /* ++ * Set to 1 if the core PHY interface bits in USBCFG have been ++ * initialized. ++ */ ++ uint8_t phy_init_done; ++ ++ /* ++ * SRP Success flag, set by srp success interrupt in FS I2C mode ++ */ ++ uint8_t srp_success; ++ uint8_t srp_timer_started; ++ ++ /* Common configuration information */ ++ /** Power and Clock Gating Control Register */ ++ volatile uint32_t *pcgcctl; ++#define DWC_OTG_PCGCCTL_OFFSET 0xE00 ++ ++ /** Push/pop addresses for endpoints or host channels.*/ ++ uint32_t *data_fifo[MAX_EPS_CHANNELS]; ++#define DWC_OTG_DATA_FIFO_OFFSET 0x1000 ++#define DWC_OTG_DATA_FIFO_SIZE 0x1000 ++ ++ /** Total RAM for FIFOs (Bytes) */ ++ uint16_t total_fifo_size; ++ /** Size of Rx FIFO (Bytes) */ ++ uint16_t rx_fifo_size; ++ /** Size of Non-periodic Tx FIFO (Bytes) */ ++ uint16_t nperio_tx_fifo_size; ++ ++ /** 1 if DMA is enabled, 0 otherwise. */ ++ uint8_t dma_enable; ++ ++ /** 1 if dedicated Tx FIFOs are enabled, 0 otherwise. */ ++ uint8_t en_multiple_tx_fifo; ++ ++ /** Set to 1 if multiple packets of a high-bandwidth transfer is in ++ * process of being queued */ ++ uint8_t queuing_high_bandwidth; ++ ++ /** Hardware Configuration -- stored here for convenience.*/ ++ hwcfg1_data_t hwcfg1; ++ hwcfg2_data_t hwcfg2; ++ hwcfg3_data_t hwcfg3; ++ hwcfg4_data_t hwcfg4; ++ ++ /** The operational State, during transations ++ * (a_host>>a_peripherial and b_device=>b_host) this may not ++ * match the core but allows the software to determine ++ * transitions. ++ */ ++ uint8_t op_state; ++ ++ /** ++ * Set to 1 if the HCD needs to be restarted on a session request ++ * interrupt. This is required if no connector ID status change has ++ * occurred since the HCD was last disconnected. ++ */ ++ uint8_t restart_hcd_on_session_req; ++ ++ /** HCD callbacks */ ++ /** A-Device is a_host */ ++#define A_HOST (1) ++ /** A-Device is a_suspend */ ++#define A_SUSPEND (2) ++ /** A-Device is a_peripherial */ ++#define A_PERIPHERAL (3) ++ /** B-Device is operating as a Peripheral. */ ++#define B_PERIPHERAL (4) ++ /** B-Device is operating as a Host. */ ++#define B_HOST (5) ++ ++ /** HCD callbacks */ ++ struct dwc_otg_cil_callbacks *hcd_cb; ++ /** PCD callbacks */ ++ struct dwc_otg_cil_callbacks *pcd_cb; ++ ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t p_tx_msk; ++ /** Device mode Periodic Tx FIFO Mask */ ++ uint32_t tx_msk; ++ ++#ifdef DEBUG ++ uint32_t start_hcchar_val[MAX_EPS_CHANNELS]; ++ ++ hc_xfer_info_t hc_xfer_info[MAX_EPS_CHANNELS]; ++ struct timer_list hc_xfer_timer[MAX_EPS_CHANNELS]; ++ ++#if 1 // winder ++ uint32_t hfnum_7_samples; ++ uint32_t hfnum_7_frrem_accum; ++ uint32_t hfnum_0_samples; ++ uint32_t hfnum_0_frrem_accum; ++ uint32_t hfnum_other_samples; ++ uint32_t hfnum_other_frrem_accum; ++#else ++ uint32_t hfnum_7_samples; ++ uint64_t hfnum_7_frrem_accum; ++ uint32_t hfnum_0_samples; ++ uint64_t hfnum_0_frrem_accum; ++ uint32_t hfnum_other_samples; ++ uint64_t hfnum_other_frrem_accum; ++#endif ++ resource_size_t phys_addr; /* Added to support PLB DMA : phys-virt mapping */ ++#endif ++ ++} dwc_otg_core_if_t; ++ ++/* ++ * The following functions support initialization of the CIL driver component ++ * and the DWC_otg controller. ++ */ ++extern dwc_otg_core_if_t *dwc_otg_cil_init(const uint32_t *_reg_base_addr, ++ dwc_otg_core_params_t *_core_params); ++extern void dwc_otg_cil_remove(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_core_init(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_core_host_init(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_core_dev_init(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_enable_global_interrupts( dwc_otg_core_if_t *_core_if ); ++extern void dwc_otg_disable_global_interrupts( dwc_otg_core_if_t *_core_if ); ++ ++/** @name Device CIL Functions ++ * The following functions support managing the DWC_otg controller in device ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_wakeup(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_read_setup_packet (dwc_otg_core_if_t *_core_if, uint32_t *_dest); ++extern uint32_t dwc_otg_get_frame_number(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_ep0_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep_activate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep_deactivate(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep0_start_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep0_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep_write_packet(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep, int _dma); ++extern void dwc_otg_ep_set_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_ep_clear_stall(dwc_otg_core_if_t *_core_if, dwc_ep_t *_ep); ++extern void dwc_otg_enable_device_interrupts(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_dump_dev_registers(dwc_otg_core_if_t *_core_if); ++/**@}*/ ++ ++/** @name Host CIL Functions ++ * The following functions support managing the DWC_otg controller in host ++ * mode. ++ */ ++/**@{*/ ++extern void dwc_otg_hc_init(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern void dwc_otg_hc_halt(dwc_otg_core_if_t *_core_if, ++ dwc_hc_t *_hc, ++ dwc_otg_halt_status_e _halt_status); ++extern void dwc_otg_hc_cleanup(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern void dwc_otg_hc_start_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern int dwc_otg_hc_continue_transfer(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern void dwc_otg_hc_do_ping(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern void dwc_otg_hc_write_packet(dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc); ++extern void dwc_otg_enable_host_interrupts(dwc_otg_core_if_t *_core_if); ++extern void dwc_otg_disable_host_interrupts(dwc_otg_core_if_t *_core_if); ++ ++/** ++ * This function Reads HPRT0 in preparation to modify. It keeps the ++ * WC bits 0 so that if they are read as 1, they won't clear when you ++ * write it back ++ */ ++static inline uint32_t dwc_otg_read_hprt0(dwc_otg_core_if_t *_core_if) ++{ ++ hprt0_data_t hprt0; ++ hprt0.d32 = dwc_read_reg32(_core_if->host_if->hprt0); ++ hprt0.b.prtena = 0; ++ hprt0.b.prtconndet = 0; ++ hprt0.b.prtenchng = 0; ++ hprt0.b.prtovrcurrchng = 0; ++ return hprt0.d32; ++} ++ ++extern void dwc_otg_dump_host_registers(dwc_otg_core_if_t *_core_if); ++/**@}*/ ++ ++/** @name Common CIL Functions ++ * The following functions support managing the DWC_otg controller in either ++ * device or host mode. ++ */ ++/**@{*/ ++ ++extern void dwc_otg_read_packet(dwc_otg_core_if_t *core_if, ++ uint8_t *dest, ++ uint16_t bytes); ++ ++extern void dwc_otg_dump_global_registers(dwc_otg_core_if_t *_core_if); ++ ++extern void dwc_otg_flush_tx_fifo( dwc_otg_core_if_t *_core_if, ++ const int _num ); ++extern void dwc_otg_flush_rx_fifo( dwc_otg_core_if_t *_core_if ); ++extern void dwc_otg_core_reset( dwc_otg_core_if_t *_core_if ); ++ ++#define NP_TXFIFO_EMPTY -1 ++#define MAX_NP_TXREQUEST_Q_SLOTS 8 ++/** ++ * This function returns the endpoint number of the request at ++ * the top of non-periodic TX FIFO, or -1 if the request FIFO is ++ * empty. ++ */ ++static inline int dwc_otg_top_nptxfifo_epnum(dwc_otg_core_if_t *_core_if) { ++ gnptxsts_data_t txstatus = {.d32 = 0}; ++ ++ txstatus.d32 = dwc_read_reg32(&_core_if->core_global_regs->gnptxsts); ++ return (txstatus.b.nptxqspcavail == MAX_NP_TXREQUEST_Q_SLOTS ? ++ -1 : txstatus.b.nptxqtop_chnep); ++} ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_core_intr(dwc_otg_core_if_t *_core_if) { ++ return (dwc_read_reg32(&_core_if->core_global_regs->gintsts) & ++ dwc_read_reg32(&_core_if->core_global_regs->gintmsk)); ++} ++ ++/** ++ * This function returns the OTG Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_otg_intr (dwc_otg_core_if_t *_core_if) { ++ return (dwc_read_reg32 (&_core_if->core_global_regs->gotgint)); ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the IN endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_in_ep_intr(dwc_otg_core_if_t *_core_if) { ++ uint32_t v; ++ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & ++ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); ++ return (v & 0xffff); ++ ++} ++ ++/** ++ * This function reads the Device All Endpoints Interrupt register and ++ * returns the OUT endpoint interrupt bits. ++ */ ++static inline uint32_t dwc_otg_read_dev_all_out_ep_intr(dwc_otg_core_if_t *_core_if) { ++ uint32_t v; ++ v = dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daint) & ++ dwc_read_reg32(&_core_if->dev_if->dev_global_regs->daintmsk); ++ return ((v & 0xffff0000) >> 16); ++} ++ ++/** ++ * This function returns the Device IN EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_in_ep_intr(dwc_otg_core_if_t *_core_if, ++ dwc_ep_t *_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v, msk, emp; ++ msk = dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); ++ emp = dwc_read_reg32(&dev_if->dev_global_regs->dtknqr4_fifoemptymsk); ++ msk |= ((emp >> _ep->num) & 0x1) << 7; ++ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & msk; ++/* ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v; ++ v = dwc_read_reg32(&dev_if->in_ep_regs[_ep->num]->diepint) & ++ dwc_read_reg32(&dev_if->dev_global_regs->diepmsk); ++*/ ++ return v; ++} ++/** ++ * This function returns the Device OUT EP Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_dev_out_ep_intr(dwc_otg_core_if_t *_core_if, ++ dwc_ep_t *_ep) ++{ ++ dwc_otg_dev_if_t *dev_if = _core_if->dev_if; ++ uint32_t v; ++ v = dwc_read_reg32( &dev_if->out_ep_regs[_ep->num]->doepint) & ++ dwc_read_reg32(&dev_if->dev_global_regs->doepmsk); ++ return v; ++} ++ ++/** ++ * This function returns the Host All Channel Interrupt register ++ */ ++static inline uint32_t dwc_otg_read_host_all_channels_intr (dwc_otg_core_if_t *_core_if) ++{ ++ return (dwc_read_reg32 (&_core_if->host_if->host_global_regs->haint)); ++} ++ ++static inline uint32_t dwc_otg_read_host_channel_intr (dwc_otg_core_if_t *_core_if, dwc_hc_t *_hc) ++{ ++ return (dwc_read_reg32 (&_core_if->host_if->hc_regs[_hc->hc_num]->hcint)); ++} ++ ++ ++/** ++ * This function returns the mode of the operation, host or device. ++ * ++ * @return 0 - Device Mode, 1 - Host Mode ++ */ ++static inline uint32_t dwc_otg_mode(dwc_otg_core_if_t *_core_if) { ++ return (dwc_read_reg32( &_core_if->core_global_regs->gintsts ) & 0x1); ++} ++ ++static inline uint8_t dwc_otg_is_device_mode(dwc_otg_core_if_t *_core_if) ++{ ++ return (dwc_otg_mode(_core_if) != DWC_HOST_MODE); ++} ++static inline uint8_t dwc_otg_is_host_mode(dwc_otg_core_if_t *_core_if) ++{ ++ return (dwc_otg_mode(_core_if) == DWC_HOST_MODE); ++} ++ ++extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ); ++ ++ ++/**@}*/ ++ ++/** ++ * DWC_otg CIL callback structure. This structure allows the HCD and ++ * PCD to register functions used for starting and stopping the PCD ++ * and HCD for role change on for a DRD. ++ */ ++typedef struct dwc_otg_cil_callbacks ++{ ++ /** Start function for role change */ ++ int (*start) (void *_p); ++ /** Stop Function for role change */ ++ int (*stop) (void *_p); ++ /** Disconnect Function for role change */ ++ int (*disconnect) (void *_p); ++ /** Resume/Remote wakeup Function */ ++ int (*resume_wakeup) (void *_p); ++ /** Suspend function */ ++ int (*suspend) (void *_p); ++ /** Session Start (SRP) */ ++ int (*session_start) (void *_p); ++ /** Pointer passed to start() and stop() */ ++ void *p; ++} dwc_otg_cil_callbacks_t; ++ ++ ++ ++extern void dwc_otg_cil_register_pcd_callbacks( dwc_otg_core_if_t *_core_if, ++ dwc_otg_cil_callbacks_t *_cb, ++ void *_p); ++extern void dwc_otg_cil_register_hcd_callbacks( dwc_otg_core_if_t *_core_if, ++ dwc_otg_cil_callbacks_t *_cb, ++ void *_p); ++ ++ ++#endif +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_cil_ifx.h +@@ -0,0 +1,58 @@ ++/****************************************************************************** ++** ++** FILE NAME : dwc_otg_cil_ifx.h ++** PROJECT : Twinpass/Danube ++** MODULES : DWC OTG USB ++** ++** DATE : 07 Sep. 2007 ++** AUTHOR : Sung Winder ++** DESCRIPTION : Default param value. ++** COPYRIGHT : Copyright (c) 2007 ++** Infineon Technologies AG ++** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, ++** Hsin-chu City, 300 Taiwan. ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 12 April 2007 Sung Winder Initiate Version ++*******************************************************************************/ ++#if !defined(__DWC_OTG_CIL_IFX_H__) ++#define __DWC_OTG_CIL_IFX_H__ ++ ++/* ================ Default param value ================== */ ++#define dwc_param_opt_default 1 ++#define dwc_param_otg_cap_default DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE ++#define dwc_param_dma_enable_default 1 ++#define dwc_param_dma_burst_size_default 32 ++#define dwc_param_speed_default DWC_SPEED_PARAM_HIGH ++#define dwc_param_host_support_fs_ls_low_power_default 0 ++#define dwc_param_host_ls_low_power_phy_clk_default DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ ++#define dwc_param_enable_dynamic_fifo_default 1 ++#define dwc_param_data_fifo_size_default 2048 ++#define dwc_param_dev_rx_fifo_size_default 1024 ++#define dwc_param_dev_nperio_tx_fifo_size_default 1024 ++#define dwc_param_dev_perio_tx_fifo_size_default 768 ++#define dwc_param_host_rx_fifo_size_default 640 ++#define dwc_param_host_nperio_tx_fifo_size_default 640 ++#define dwc_param_host_perio_tx_fifo_size_default 768 ++#define dwc_param_max_transfer_size_default 65535 ++#define dwc_param_max_packet_count_default 511 ++#define dwc_param_host_channels_default 16 ++#define dwc_param_dev_endpoints_default 6 ++#define dwc_param_phy_type_default DWC_PHY_TYPE_PARAM_UTMI ++#define dwc_param_phy_utmi_width_default 16 ++#define dwc_param_phy_ulpi_ddr_default 0 ++#define dwc_param_phy_ulpi_ext_vbus_default DWC_PHY_ULPI_INTERNAL_VBUS ++#define dwc_param_i2c_enable_default 0 ++#define dwc_param_ulpi_fs_ls_default 0 ++#define dwc_param_ts_dline_default 0 ++ ++/* ======================================================= */ ++ ++#endif // __DWC_OTG_CIL_IFX_H__ ++ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_cil_intr.c +@@ -0,0 +1,708 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_cil_intr.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 553126 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * ++ * The Core Interface Layer provides basic services for accessing and ++ * managing the DWC_otg hardware. These services are used by both the ++ * Host Controller Driver and the Peripheral Controller Driver. ++ * ++ * This file contains the Common Interrupt handlers. ++ */ ++#include "dwc_otg_plat.h" ++#include "dwc_otg_regs.h" ++#include "dwc_otg_cil.h" ++ ++#ifdef DEBUG ++inline const char *op_state_str( dwc_otg_core_if_t *_core_if ) ++{ ++ return (_core_if->op_state==A_HOST?"a_host": ++ (_core_if->op_state==A_SUSPEND?"a_suspend": ++ (_core_if->op_state==A_PERIPHERAL?"a_peripheral": ++ (_core_if->op_state==B_PERIPHERAL?"b_peripheral": ++ (_core_if->op_state==B_HOST?"b_host": ++ "unknown"))))); ++} ++#endif ++ ++/** This function will log a debug message ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_mode_mismatch_intr (dwc_otg_core_if_t *_core_if) ++{ ++ gintsts_data_t gintsts; ++ DWC_WARN("Mode Mismatch Interrupt: currently in %s mode\n", ++ dwc_otg_mode(_core_if) ? "Host" : "Device"); ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.modemismatch = 1; ++ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++ ++/** Start the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_start( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->hcd_cb && _core_if->hcd_cb->start) { ++ _core_if->hcd_cb->start( _core_if->hcd_cb->p ); ++ } ++} ++/** Stop the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_stop( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->hcd_cb && _core_if->hcd_cb->stop) { ++ _core_if->hcd_cb->stop( _core_if->hcd_cb->p ); ++ } ++} ++/** Disconnect the HCD. Helper function for using the HCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_disconnect( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->hcd_cb && _core_if->hcd_cb->disconnect) { ++ _core_if->hcd_cb->disconnect( _core_if->hcd_cb->p ); ++ } ++} ++/** Inform the HCD the a New Session has begun. Helper function for ++ * using the HCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void hcd_session_start( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->hcd_cb && _core_if->hcd_cb->session_start) { ++ _core_if->hcd_cb->session_start( _core_if->hcd_cb->p ); ++ } ++} ++ ++/** Start the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_start( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->pcd_cb && _core_if->pcd_cb->start ) { ++ _core_if->pcd_cb->start( _core_if->pcd_cb->p ); ++ } ++} ++/** Stop the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_stop( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->pcd_cb && _core_if->pcd_cb->stop ) { ++ _core_if->pcd_cb->stop( _core_if->pcd_cb->p ); ++ } ++} ++/** Suspend the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_suspend( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->pcd_cb && _core_if->pcd_cb->suspend ) { ++ _core_if->pcd_cb->suspend( _core_if->pcd_cb->p ); ++ } ++} ++/** Resume the PCD. Helper function for using the PCD callbacks. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++static inline void pcd_resume( dwc_otg_core_if_t *_core_if ) ++{ ++ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup ) { ++ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); ++ } ++} ++ ++/** ++ * This function handles the OTG Interrupts. It reads the OTG ++ * Interrupt Register (GOTGINT) to determine what interrupt has ++ * occurred. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_otg_intr(dwc_otg_core_if_t *_core_if) ++{ ++ dwc_otg_core_global_regs_t *global_regs = ++ _core_if->core_global_regs; ++ gotgint_data_t gotgint; ++ gotgctl_data_t gotgctl; ++ gintmsk_data_t gintmsk; ++ ++ gotgint.d32 = dwc_read_reg32( &global_regs->gotgint); ++ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint.d32, ++ op_state_str(_core_if)); ++ //DWC_DEBUGPL(DBG_CIL, "gotgctl=%08x\n", gotgctl.d32 ); ++ ++ if (gotgint.b.sesenddet) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session End Detected++ (%s)\n", ++ op_state_str(_core_if)); ++ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); ++ ++ if (_core_if->op_state == B_HOST) { ++ pcd_start( _core_if ); ++ _core_if->op_state = B_PERIPHERAL; ++ } else { ++ /* If not B_HOST and Device HNP still set. HNP ++ * Did not succeed!*/ ++ if (gotgctl.b.devhnpen) { ++ DWC_DEBUGPL(DBG_ANY, "Session End Detected\n"); ++ DWC_ERROR( "Device Not Connected/Responding!\n" ); ++ } ++ ++ /* If Session End Detected the B-Cable has ++ * been disconnected. */ ++ /* Reset PCD and Gadget driver to a ++ * clean state. */ ++ pcd_stop(_core_if); ++ } ++ gotgctl.d32 = 0; ++ gotgctl.b.devhnpen = 1; ++ dwc_modify_reg32( &global_regs->gotgctl, ++ gotgctl.d32, 0); ++ } ++ if (gotgint.b.sesreqsucstschng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Session Reqeust Success Status Change++\n"); ++ gotgctl.d32 = dwc_read_reg32( &global_regs->gotgctl); ++ if (gotgctl.b.sesreqscs) { ++ if ((_core_if->core_params->phy_type == DWC_PHY_TYPE_PARAM_FS) && ++ (_core_if->core_params->i2c_enable)) { ++ _core_if->srp_success = 1; ++ } ++ else { ++ pcd_resume( _core_if ); ++ /* Clear Session Request */ ++ gotgctl.d32 = 0; ++ gotgctl.b.sesreq = 1; ++ dwc_modify_reg32( &global_regs->gotgctl, ++ gotgctl.d32, 0); ++ } ++ } ++ } ++ if (gotgint.b.hstnegsucstschng) { ++ /* Print statements during the HNP interrupt handling ++ * can cause it to fail.*/ ++ gotgctl.d32 = dwc_read_reg32(&global_regs->gotgctl); ++ if (gotgctl.b.hstnegscs) { ++ if (dwc_otg_is_host_mode(_core_if) ) { ++ _core_if->op_state = B_HOST; ++ /* ++ * Need to disable SOF interrupt immediately. ++ * When switching from device to host, the PCD ++ * interrupt handler won't handle the ++ * interrupt if host mode is already set. The ++ * HCD interrupt handler won't get called if ++ * the HCD state is HALT. This means that the ++ * interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, ++ gintmsk.d32, 0); ++ pcd_stop(_core_if); ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ hcd_start( _core_if ); ++ _core_if->op_state = B_HOST; ++ } ++ } else { ++ gotgctl.d32 = 0; ++ gotgctl.b.hnpreq = 1; ++ gotgctl.b.devhnpen = 1; ++ dwc_modify_reg32( &global_regs->gotgctl, ++ gotgctl.d32, 0); ++ DWC_DEBUGPL( DBG_ANY, "HNP Failed\n"); ++ DWC_ERROR( "Device Not Connected/Responding\n" ); ++ } ++ } ++ if (gotgint.b.hstnegdet) { ++ /* The disconnect interrupt is set at the same time as ++ * Host Negotiation Detected. During the mode ++ * switch all interrupts are cleared so the disconnect ++ * interrupt handler will not get executed. ++ */ ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Host Negotiation Detected++ (%s)\n", ++ (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); ++ if (dwc_otg_is_device_mode(_core_if)){ ++ DWC_DEBUGPL(DBG_ANY, "a_suspend->a_peripheral (%d)\n",_core_if->op_state); ++ hcd_disconnect( _core_if ); ++ pcd_start( _core_if ); ++ _core_if->op_state = A_PERIPHERAL; ++ } else { ++ /* ++ * Need to disable SOF interrupt immediately. When ++ * switching from device to host, the PCD interrupt ++ * handler won't handle the interrupt if host mode is ++ * already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that ++ * the interrupt does not get handled and Linux ++ * complains loudly. ++ */ ++ gintmsk.d32 = 0; ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, ++ gintmsk.d32, 0); ++ pcd_stop( _core_if ); ++ hcd_start( _core_if ); ++ _core_if->op_state = A_HOST; ++ } ++ } ++ if (gotgint.b.adevtoutchng) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "A-Device Timeout Change++\n"); ++ } ++ if (gotgint.b.debdone) { ++ DWC_DEBUGPL(DBG_ANY, " ++OTG Interrupt: " ++ "Debounce Done++\n"); ++ } ++ ++ /* Clear GOTGINT */ ++ dwc_write_reg32 (&_core_if->core_global_regs->gotgint, gotgint.d32); ++ ++ return 1; ++} ++ ++/** ++ * This function handles the Connector ID Status Change Interrupt. It ++ * reads the OTG Interrupt Register (GOTCTL) to determine whether this ++ * is a Device to Host Mode transition or a Host Mode to Device ++ * Transition. ++ * ++ * This only occurs when the cable is connected/removed from the PHY ++ * connector. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_conn_id_status_change_intr(dwc_otg_core_if_t *_core_if) ++{ ++ uint32_t count = 0; ++ ++ gintsts_data_t gintsts = { .d32 = 0 }; ++ gintmsk_data_t gintmsk = { .d32 = 0 }; ++ gotgctl_data_t gotgctl = { .d32 = 0 }; ++ ++ /* ++ * Need to disable SOF interrupt immediately. If switching from device ++ * to host, the PCD interrupt handler won't handle the interrupt if ++ * host mode is already set. The HCD interrupt handler won't get ++ * called if the HCD state is HALT. This means that the interrupt does ++ * not get handled and Linux complains loudly. ++ */ ++ gintmsk.b.sofintr = 1; ++ dwc_modify_reg32(&_core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ ++ DWC_DEBUGPL(DBG_CIL, " ++Connector ID Status Change Interrupt++ (%s)\n", ++ (dwc_otg_is_host_mode(_core_if)?"Host":"Device")); ++ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl=%0x\n", gotgctl.d32); ++ DWC_DEBUGPL(DBG_CIL, "gotgctl.b.conidsts=%d\n", gotgctl.b.conidsts); ++ ++ /* B-Device connector (Device Mode) */ ++ if (gotgctl.b.conidsts) { ++ /* Wait for switch to device mode. */ ++ while (!dwc_otg_is_device_mode(_core_if) ){ ++ DWC_PRINT("Waiting for Peripheral Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); ++ MDELAY(100); ++ if (++count > 10000) *(uint32_t*)NULL=0; ++ } ++ _core_if->op_state = B_PERIPHERAL; ++ dwc_otg_core_init(_core_if); ++ dwc_otg_enable_global_interrupts(_core_if); ++ pcd_start( _core_if ); ++ } else { ++ /* A-Device connector (Host Mode) */ ++ while (!dwc_otg_is_host_mode(_core_if) ) { ++ DWC_PRINT("Waiting for Host Mode, Mode=%s\n", ++ (dwc_otg_is_host_mode(_core_if)?"Host":"Peripheral")); ++ MDELAY(100); ++ if (++count > 10000) *(uint32_t*)NULL=0; ++ } ++ _core_if->op_state = A_HOST; ++ /* ++ * Initialize the Core for Host mode. ++ */ ++ dwc_otg_core_init(_core_if); ++ dwc_otg_enable_global_interrupts(_core_if); ++ hcd_start( _core_if ); ++ } ++ ++ /* Set flag and clear interrupt */ ++ gintsts.b.conidstschng = 1; ++ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device is initiating the Session ++ * Request Protocol to request the host to turn on bus power so a new ++ * session can begin. The handler responds by turning on bus power. If ++ * the DWC_otg controller is in low power mode, the handler brings the ++ * controller out of low power mode before turning on bus power. ++ * ++ * @param _core_if Programming view of DWC_otg controller. ++ */ ++int32_t dwc_otg_handle_session_req_intr( dwc_otg_core_if_t *_core_if ) ++{ ++#ifndef DWC_HOST_ONLY // winder ++ hprt0_data_t hprt0; ++#endif ++ gintsts_data_t gintsts; ++ ++#ifndef DWC_HOST_ONLY ++ DWC_DEBUGPL(DBG_ANY, "++Session Request Interrupt++\n"); ++ ++ if (dwc_otg_is_device_mode(_core_if) ) { ++ DWC_PRINT("SRP: Device mode\n"); ++ } else { ++ DWC_PRINT("SRP: Host mode\n"); ++ ++ /* Turn on the port power bit. */ ++ hprt0.d32 = dwc_otg_read_hprt0( _core_if ); ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Start the Connection timer. So a message can be displayed ++ * if connect does not occur within 10 seconds. */ ++ hcd_session_start( _core_if ); ++ } ++#endif ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.sessreqintr = 1; ++ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that the DWC_otg controller has detected a ++ * resume or remote wakeup sequence. If the DWC_otg controller is in ++ * low power mode, the handler must brings the controller out of low ++ * power mode. The controller automatically begins resume ++ * signaling. The handler schedules a time to stop resume signaling. ++ */ ++int32_t dwc_otg_handle_wakeup_detected_intr( dwc_otg_core_if_t *_core_if ) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "++Resume and Remote Wakeup Detected Interrupt++\n"); ++ ++ if (dwc_otg_is_device_mode(_core_if) ) { ++ dctl_data_t dctl = {.d32=0}; ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", ++ dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts)); ++#ifdef PARTIAL_POWER_DOWN ++ if (_core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32=0}; ++ ++ power.d32 = dwc_read_reg32( _core_if->pcgcctl ); ++ DWC_DEBUGPL(DBG_CIL, "PCGCCTL=%0x\n", power.d32); ++ ++ power.b.stoppclk = 0; ++ dwc_write_reg32( _core_if->pcgcctl, power.d32); ++ ++ power.b.pwrclmp = 0; ++ dwc_write_reg32( _core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 0; ++ dwc_write_reg32( _core_if->pcgcctl, power.d32); ++ } ++#endif ++ /* Clear the Remote Wakeup Signalling */ ++ dctl.b.rmtwkupsig = 1; ++ dwc_modify_reg32( &_core_if->dev_if->dev_global_regs->dctl, ++ dctl.d32, 0 ); ++ ++ if (_core_if->pcd_cb && _core_if->pcd_cb->resume_wakeup) { ++ _core_if->pcd_cb->resume_wakeup( _core_if->pcd_cb->p ); ++ } ++ ++ } else { ++ /* ++ * Clear the Resume after 70ms. (Need 20 ms minimum. Use 70 ms ++ * so that OPT tests pass with all PHYs). ++ */ ++ hprt0_data_t hprt0 = {.d32=0}; ++ pcgcctl_data_t pcgcctl = {.d32=0}; ++ /* Restart the Phy Clock */ ++ pcgcctl.b.stoppclk = 1; ++ dwc_modify_reg32(_core_if->pcgcctl, pcgcctl.d32, 0); ++ UDELAY(10); ++ ++ /* Now wait for 70 ms. */ ++ hprt0.d32 = dwc_otg_read_hprt0( _core_if ); ++ DWC_DEBUGPL(DBG_ANY,"Resume: HPRT0=%0x\n", hprt0.d32); ++ MDELAY(70); ++ hprt0.b.prtres = 0; /* Resume */ ++ dwc_write_reg32(_core_if->host_if->hprt0, hprt0.d32); ++ DWC_DEBUGPL(DBG_ANY,"Clear Resume: HPRT0=%0x\n", dwc_read_reg32(_core_if->host_if->hprt0)); ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.wkupintr = 1; ++ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** ++ * This interrupt indicates that a device has been disconnected from ++ * the root port. ++ */ ++int32_t dwc_otg_handle_disconnect_intr( dwc_otg_core_if_t *_core_if) ++{ ++ gintsts_data_t gintsts; ++ ++ DWC_DEBUGPL(DBG_ANY, "++Disconnect Detected Interrupt++ (%s) %s\n", ++ (dwc_otg_is_host_mode(_core_if)?"Host":"Device"), ++ op_state_str(_core_if)); ++ ++/** @todo Consolidate this if statement. */ ++#ifndef DWC_HOST_ONLY ++ if (_core_if->op_state == B_HOST) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ hcd_disconnect( _core_if ); ++ pcd_start( _core_if ); ++ _core_if->op_state = B_PERIPHERAL; ++ } else if (dwc_otg_is_device_mode(_core_if)) { ++ gotgctl_data_t gotgctl = { .d32 = 0 }; ++ gotgctl.d32 = dwc_read_reg32(&_core_if->core_global_regs->gotgctl); ++ if (gotgctl.b.hstsethnpen==1) { ++ /* Do nothing, if HNP in process the OTG ++ * interrupt "Host Negotiation Detected" ++ * interrupt will do the mode switch. ++ */ ++ } else if (gotgctl.b.devhnpen == 0) { ++ /* If in device mode Disconnect and stop the HCD, then ++ * start the PCD. */ ++ hcd_disconnect( _core_if ); ++ pcd_start( _core_if ); ++ _core_if->op_state = B_PERIPHERAL; ++ } else { ++ DWC_DEBUGPL(DBG_ANY,"!a_peripheral && !devhnpen\n"); ++ } ++ } else { ++ if (_core_if->op_state == A_HOST) { ++ /* A-Cable still connected but device disconnected. */ ++ hcd_disconnect( _core_if ); ++ } ++ } ++#endif ++/* Without OTG, we should use the disconnect function!? winder added.*/ ++#if 1 // NO OTG, so host only!! ++ hcd_disconnect( _core_if ); ++#endif ++ ++ gintsts.d32 = 0; ++ gintsts.b.disconnect = 1; ++ dwc_write_reg32 (&_core_if->core_global_regs->gintsts, gintsts.d32); ++ return 1; ++} ++/** ++ * This interrupt indicates that SUSPEND state has been detected on ++ * the USB. ++ * ++ * For HNP the USB Suspend interrupt signals the change from ++ * "a_peripheral" to "a_host". ++ * ++ * When power management is enabled the core will be put in low power ++ * mode. ++ */ ++int32_t dwc_otg_handle_usb_suspend_intr(dwc_otg_core_if_t *_core_if ) ++{ ++ dsts_data_t dsts; ++ gintsts_data_t gintsts; ++ ++ //805141:<IFTW-fchang>.removed DWC_DEBUGPL(DBG_ANY,"USB SUSPEND\n"); ++ ++ if (dwc_otg_is_device_mode( _core_if ) ) { ++ /* Check the Device status register to determine if the Suspend ++ * state is active. */ ++ dsts.d32 = dwc_read_reg32( &_core_if->dev_if->dev_global_regs->dsts); ++ DWC_DEBUGPL(DBG_PCD, "DSTS=0x%0x\n", dsts.d32); ++ DWC_DEBUGPL(DBG_PCD, "DSTS.Suspend Status=%d " ++ "HWCFG4.power Optimize=%d\n", ++ dsts.b.suspsts, _core_if->hwcfg4.b.power_optimiz); ++ ++ ++#ifdef PARTIAL_POWER_DOWN ++/** @todo Add a module parameter for power management. */ ++ ++ if (dsts.b.suspsts && _core_if->hwcfg4.b.power_optimiz) { ++ pcgcctl_data_t power = {.d32=0}; ++ DWC_DEBUGPL(DBG_CIL, "suspend\n"); ++ ++ power.b.pwrclmp = 1; ++ dwc_write_reg32( _core_if->pcgcctl, power.d32); ++ ++ power.b.rstpdwnmodule = 1; ++ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); ++ ++ power.b.stoppclk = 1; ++ dwc_modify_reg32( _core_if->pcgcctl, 0, power.d32); ++ ++ } else { ++ DWC_DEBUGPL(DBG_ANY,"disconnect?\n"); ++ } ++#endif ++ /* PCD callback for suspend. */ ++ pcd_suspend(_core_if); ++ } else { ++ if (_core_if->op_state == A_PERIPHERAL) { ++ DWC_DEBUGPL(DBG_ANY,"a_peripheral->a_host\n"); ++ /* Clear the a_peripheral flag, back to a_host. */ ++ pcd_stop( _core_if ); ++ hcd_start( _core_if ); ++ _core_if->op_state = A_HOST; ++ } ++ } ++ ++ /* Clear interrupt */ ++ gintsts.d32 = 0; ++ gintsts.b.usbsuspend = 1; ++ dwc_write_reg32( &_core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++ ++/** ++ * This function returns the Core Interrupt register. ++ */ ++static inline uint32_t dwc_otg_read_common_intr(dwc_otg_core_if_t *_core_if) ++{ ++ gintsts_data_t gintsts; ++ gintmsk_data_t gintmsk; ++ gintmsk_data_t gintmsk_common = {.d32=0}; ++ gintmsk_common.b.wkupintr = 1; ++ gintmsk_common.b.sessreqintr = 1; ++ gintmsk_common.b.conidstschng = 1; ++ gintmsk_common.b.otgintr = 1; ++ gintmsk_common.b.modemismatch = 1; ++ gintmsk_common.b.disconnect = 1; ++ gintmsk_common.b.usbsuspend = 1; ++ /** @todo: The port interrupt occurs while in device ++ * mode. Added code to CIL to clear the interrupt for now! ++ */ ++ gintmsk_common.b.portintr = 1; ++ ++ gintsts.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintsts); ++ gintmsk.d32 = dwc_read_reg32(&_core_if->core_global_regs->gintmsk); ++#ifdef DEBUG ++ /* if any common interrupts set */ ++ if (gintsts.d32 & gintmsk_common.d32) { ++ DWC_DEBUGPL(DBG_ANY, "gintsts=%08x gintmsk=%08x\n", ++ gintsts.d32, gintmsk.d32); ++ } ++#endif ++ ++ return ((gintsts.d32 & gintmsk.d32 ) & gintmsk_common.d32); ++ ++} ++ ++/** ++ * Common interrupt handler. ++ * ++ * The common interrupts are those that occur in both Host and Device mode. ++ * This handler handles the following interrupts: ++ * - Mode Mismatch Interrupt ++ * - Disconnect Interrupt ++ * - OTG Interrupt ++ * - Connector ID Status Change Interrupt ++ * - Session Request Interrupt. ++ * - Resume / Remote Wakeup Detected Interrupt. ++ * ++ */ ++extern int32_t dwc_otg_handle_common_intr( dwc_otg_core_if_t *_core_if ) ++{ ++ int retval = 0; ++ gintsts_data_t gintsts; ++ ++ gintsts.d32 = dwc_otg_read_common_intr(_core_if); ++ ++ if (gintsts.b.modemismatch) { ++ retval |= dwc_otg_handle_mode_mismatch_intr( _core_if ); ++ } ++ if (gintsts.b.otgintr) { ++ retval |= dwc_otg_handle_otg_intr( _core_if ); ++ } ++ if (gintsts.b.conidstschng) { ++ retval |= dwc_otg_handle_conn_id_status_change_intr( _core_if ); ++ } ++ if (gintsts.b.disconnect) { ++ retval |= dwc_otg_handle_disconnect_intr( _core_if ); ++ } ++ if (gintsts.b.sessreqintr) { ++ retval |= dwc_otg_handle_session_req_intr( _core_if ); ++ } ++ if (gintsts.b.wkupintr) { ++ retval |= dwc_otg_handle_wakeup_detected_intr( _core_if ); ++ } ++ if (gintsts.b.usbsuspend) { ++ retval |= dwc_otg_handle_usb_suspend_intr( _core_if ); ++ } ++ if (gintsts.b.portintr && dwc_otg_is_device_mode(_core_if)) { ++ /* The port interrupt occurs while in device mode with HPRT0 ++ * Port Enable/Disable. ++ */ ++ gintsts.d32 = 0; ++ gintsts.b.portintr = 1; ++ dwc_write_reg32(&_core_if->core_global_regs->gintsts, ++ gintsts.d32); ++ retval |= 1; ++ ++ } ++ return retval; ++} +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_driver.c +@@ -0,0 +1,1274 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 631780 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++/** @file ++ * The dwc_otg_driver module provides the initialization and cleanup entry ++ * points for the DWC_otg driver. This module will be dynamically installed ++ * after Linux is booted using the insmod command. When the module is ++ * installed, the dwc_otg_init function is called. When the module is ++ * removed (using rmmod), the dwc_otg_cleanup function is called. ++ * ++ * This module also defines a data structure for the dwc_otg_driver, which is ++ * used in conjunction with the standard ARM lm_device structure. These ++ * structures allow the OTG driver to comply with the standard Linux driver ++ * model in which devices and drivers are registered with a bus driver. This ++ * has the benefit that Linux can expose attributes of the driver and device ++ * in its special sysfs file system. Users can then read or write files in ++ * this file system to perform diagnostics on the driver components or the ++ * device. ++ */ ++ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/gpio.h> ++ ++#include <linux/device.h> ++#include <linux/platform_device.h> ++ ++#include <linux/errno.h> ++#include <linux/types.h> ++#include <linux/stat.h> /* permission constants */ ++#include <linux/irq.h> ++#include <asm/io.h> ++ ++#include "dwc_otg_plat.h" ++#include "dwc_otg_attr.h" ++#include "dwc_otg_driver.h" ++#include "dwc_otg_cil.h" ++#include "dwc_otg_cil_ifx.h" ++ ++// #include "dwc_otg_pcd.h" // device ++#include "dwc_otg_hcd.h" // host ++ ++#include "dwc_otg_ifx.h" // for Infineon platform specific. ++ ++#define DWC_DRIVER_VERSION "2.60a 22-NOV-2006" ++#define DWC_DRIVER_DESC "HS OTG USB Controller driver" ++ ++const char dwc_driver_name[] = "dwc_otg"; ++ ++static unsigned long dwc_iomem_base = IFX_USB_IOMEM_BASE; ++int dwc_irq = LTQ_USB_INT; ++//int dwc_irq = 54; ++//int dwc_irq = IFXMIPS_USB_OC_INT; ++ ++extern int ifx_usb_hc_init(unsigned long base_addr, int irq); ++extern void ifx_usb_hc_remove(void); ++ ++/*-------------------------------------------------------------------------*/ ++/* Encapsulate the module parameter settings */ ++ ++static dwc_otg_core_params_t dwc_otg_module_params = { ++ .opt = -1, ++ .otg_cap = -1, ++ .dma_enable = -1, ++ .dma_burst_size = -1, ++ .speed = -1, ++ .host_support_fs_ls_low_power = -1, ++ .host_ls_low_power_phy_clk = -1, ++ .enable_dynamic_fifo = -1, ++ .data_fifo_size = -1, ++ .dev_rx_fifo_size = -1, ++ .dev_nperio_tx_fifo_size = -1, ++ .dev_perio_tx_fifo_size = /* dev_perio_tx_fifo_size_1 */ {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 15 */ ++ .host_rx_fifo_size = -1, ++ .host_nperio_tx_fifo_size = -1, ++ .host_perio_tx_fifo_size = -1, ++ .max_transfer_size = -1, ++ .max_packet_count = -1, ++ .host_channels = -1, ++ .dev_endpoints = -1, ++ .phy_type = -1, ++ .phy_utmi_width = -1, ++ .phy_ulpi_ddr = -1, ++ .phy_ulpi_ext_vbus = -1, ++ .i2c_enable = -1, ++ .ulpi_fs_ls = -1, ++ .ts_dline = -1, ++ .en_multiple_tx_fifo = -1, ++ .dev_tx_fifo_size = { /* dev_tx_fifo_size */ ++ -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 ++ }, /* 15 */ ++ .thr_ctl = -1, ++ .tx_thr_length = -1, ++ .rx_thr_length = -1, ++}; ++ ++/** ++ * This function shows the Driver Version. ++ */ ++static ssize_t version_show(struct device_driver *dev, char *buf) ++{ ++ return snprintf(buf, sizeof(DWC_DRIVER_VERSION)+2,"%s\n", ++ DWC_DRIVER_VERSION); ++} ++static DRIVER_ATTR(version, S_IRUGO, version_show, NULL); ++ ++/** ++ * Global Debug Level Mask. ++ */ ++uint32_t g_dbg_lvl = 0xff; /* OFF */ ++ ++/** ++ * This function shows the driver Debug Level. ++ */ ++static ssize_t dbg_level_show(struct device_driver *_drv, char *_buf) ++{ ++ return sprintf(_buf, "0x%0x\n", g_dbg_lvl); ++} ++/** ++ * This function stores the driver Debug Level. ++ */ ++static ssize_t dbg_level_store(struct device_driver *_drv, const char *_buf, ++ size_t _count) ++{ ++ g_dbg_lvl = simple_strtoul(_buf, NULL, 16); ++ return _count; ++} ++static DRIVER_ATTR(debuglevel, S_IRUGO|S_IWUSR, dbg_level_show, dbg_level_store); ++ ++/** ++ * This function is called during module intialization to verify that ++ * the module parameters are in a valid state. ++ */ ++static int check_parameters(dwc_otg_core_if_t *core_if) ++{ ++ int i; ++ int retval = 0; ++ ++/* Checks if the parameter is outside of its valid range of values */ ++#define DWC_OTG_PARAM_TEST(_param_,_low_,_high_) \ ++ ((dwc_otg_module_params._param_ < (_low_)) || \ ++ (dwc_otg_module_params._param_ > (_high_))) ++ ++/* If the parameter has been set by the user, check that the parameter value is ++ * within the value range of values. If not, report a module error. */ ++#define DWC_OTG_PARAM_ERR(_param_,_low_,_high_,_string_) \ ++ do { \ ++ if (dwc_otg_module_params._param_ != -1) { \ ++ if (DWC_OTG_PARAM_TEST(_param_,(_low_),(_high_))) { \ ++ DWC_ERROR("`%d' invalid for parameter `%s'\n", \ ++ dwc_otg_module_params._param_, _string_); \ ++ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ ++ retval ++; \ ++ } \ ++ } \ ++ } while (0) ++ ++ DWC_OTG_PARAM_ERR(opt,0,1,"opt"); ++ DWC_OTG_PARAM_ERR(otg_cap,0,2,"otg_cap"); ++ DWC_OTG_PARAM_ERR(dma_enable,0,1,"dma_enable"); ++ DWC_OTG_PARAM_ERR(speed,0,1,"speed"); ++ DWC_OTG_PARAM_ERR(host_support_fs_ls_low_power,0,1,"host_support_fs_ls_low_power"); ++ DWC_OTG_PARAM_ERR(host_ls_low_power_phy_clk,0,1,"host_ls_low_power_phy_clk"); ++ DWC_OTG_PARAM_ERR(enable_dynamic_fifo,0,1,"enable_dynamic_fifo"); ++ DWC_OTG_PARAM_ERR(data_fifo_size,32,32768,"data_fifo_size"); ++ DWC_OTG_PARAM_ERR(dev_rx_fifo_size,16,32768,"dev_rx_fifo_size"); ++ DWC_OTG_PARAM_ERR(dev_nperio_tx_fifo_size,16,32768,"dev_nperio_tx_fifo_size"); ++ DWC_OTG_PARAM_ERR(host_rx_fifo_size,16,32768,"host_rx_fifo_size"); ++ DWC_OTG_PARAM_ERR(host_nperio_tx_fifo_size,16,32768,"host_nperio_tx_fifo_size"); ++ DWC_OTG_PARAM_ERR(host_perio_tx_fifo_size,16,32768,"host_perio_tx_fifo_size"); ++ DWC_OTG_PARAM_ERR(max_transfer_size,2047,524288,"max_transfer_size"); ++ DWC_OTG_PARAM_ERR(max_packet_count,15,511,"max_packet_count"); ++ DWC_OTG_PARAM_ERR(host_channels,1,16,"host_channels"); ++ DWC_OTG_PARAM_ERR(dev_endpoints,1,15,"dev_endpoints"); ++ DWC_OTG_PARAM_ERR(phy_type,0,2,"phy_type"); ++ DWC_OTG_PARAM_ERR(phy_ulpi_ddr,0,1,"phy_ulpi_ddr"); ++ DWC_OTG_PARAM_ERR(phy_ulpi_ext_vbus,0,1,"phy_ulpi_ext_vbus"); ++ DWC_OTG_PARAM_ERR(i2c_enable,0,1,"i2c_enable"); ++ DWC_OTG_PARAM_ERR(ulpi_fs_ls,0,1,"ulpi_fs_ls"); ++ DWC_OTG_PARAM_ERR(ts_dline,0,1,"ts_dline"); ++ ++ if (dwc_otg_module_params.dma_burst_size != -1) { ++ if (DWC_OTG_PARAM_TEST(dma_burst_size,1,1) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,4,4) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,8,8) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,16,16) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,32,32) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,64,64) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,128,128) && ++ DWC_OTG_PARAM_TEST(dma_burst_size,256,256)) ++ { ++ DWC_ERROR("`%d' invalid for parameter `dma_burst_size'\n", ++ dwc_otg_module_params.dma_burst_size); ++ dwc_otg_module_params.dma_burst_size = 32; ++ retval ++; ++ } ++ } ++ ++ if (dwc_otg_module_params.phy_utmi_width != -1) { ++ if (DWC_OTG_PARAM_TEST(phy_utmi_width,8,8) && ++ DWC_OTG_PARAM_TEST(phy_utmi_width,16,16)) ++ { ++ DWC_ERROR("`%d' invalid for parameter `phy_utmi_width'\n", ++ dwc_otg_module_params.phy_utmi_width); ++ //dwc_otg_module_params.phy_utmi_width = 16; ++ dwc_otg_module_params.phy_utmi_width = 8; ++ retval ++; ++ } ++ } ++ ++ for (i=0; i<15; i++) { ++ /** @todo should be like above */ ++ //DWC_OTG_PARAM_ERR(dev_perio_tx_fifo_size[i],4,768,"dev_perio_tx_fifo_size"); ++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] != -1) { ++ if (DWC_OTG_PARAM_TEST(dev_perio_tx_fifo_size[i],4,768)) { ++ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", ++ dwc_otg_module_params.dev_perio_tx_fifo_size[i], "dev_perio_tx_fifo_size", i); ++ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; ++ retval ++; ++ } ++ } ++ } ++ ++ DWC_OTG_PARAM_ERR(en_multiple_tx_fifo, 0, 1, "en_multiple_tx_fifo"); ++ for (i = 0; i < 15; i++) { ++ /** @todo should be like above */ ++ //DWC_OTG_PARAM_ERR(dev_tx_fifo_size[i],4,768,"dev_tx_fifo_size"); ++ if (dwc_otg_module_params.dev_tx_fifo_size[i] != -1) { ++ if (DWC_OTG_PARAM_TEST(dev_tx_fifo_size[i], 4, 768)) { ++ DWC_ERROR("`%d' invalid for parameter `%s_%d'\n", ++ dwc_otg_module_params.dev_tx_fifo_size[i], ++ "dev_tx_fifo_size", i); ++ dwc_otg_module_params.dev_tx_fifo_size[i] = ++ dwc_param_dev_tx_fifo_size_default; ++ retval++; ++ } ++ } ++ } ++ DWC_OTG_PARAM_ERR(thr_ctl, 0, 7, "thr_ctl"); ++ DWC_OTG_PARAM_ERR(tx_thr_length, 8, 128, "tx_thr_length"); ++ DWC_OTG_PARAM_ERR(rx_thr_length, 8, 128, "rx_thr_length"); ++ ++ /* At this point, all module parameters that have been set by the user ++ * are valid, and those that have not are left unset. Now set their ++ * default values and/or check the parameters against the hardware ++ * configurations of the OTG core. */ ++ ++ ++ ++/* This sets the parameter to the default value if it has not been set by the ++ * user */ ++#define DWC_OTG_PARAM_SET_DEFAULT(_param_) \ ++ ({ \ ++ int changed = 1; \ ++ if (dwc_otg_module_params._param_ == -1) { \ ++ changed = 0; \ ++ dwc_otg_module_params._param_ = dwc_param_##_param_##_default; \ ++ } \ ++ changed; \ ++ }) ++ ++/* This checks the macro agains the hardware configuration to see if it is ++ * valid. It is possible that the default value could be invalid. In this ++ * case, it will report a module error if the user touched the parameter. ++ * Otherwise it will adjust the value without any error. */ ++#define DWC_OTG_PARAM_CHECK_VALID(_param_,_str_,_is_valid_,_set_valid_) \ ++ ({ \ ++ int changed = DWC_OTG_PARAM_SET_DEFAULT(_param_); \ ++ int error = 0; \ ++ if (!(_is_valid_)) { \ ++ if (changed) { \ ++ DWC_ERROR("`%d' invalid for parameter `%s'. Check HW configuration.\n", dwc_otg_module_params._param_,_str_); \ ++ error = 1; \ ++ } \ ++ dwc_otg_module_params._param_ = (_set_valid_); \ ++ } \ ++ error; \ ++ }) ++ ++ /* OTG Cap */ ++ retval += DWC_OTG_PARAM_CHECK_VALID(otg_cap,"otg_cap", ++ ({ ++ int valid; ++ valid = 1; ++ switch (dwc_otg_module_params.otg_cap) { ++ case DWC_OTG_CAP_PARAM_HNP_SRP_CAPABLE: ++ if (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) valid = 0; ++ break; ++ case DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE: ++ if ((core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) && ++ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) && ++ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) && ++ (core_if->hwcfg2.b.op_mode != DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ++ { ++ valid = 0; ++ } ++ break; ++ case DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE: ++ /* always valid */ ++ break; ++ } ++ valid; ++ }), ++ (((core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG) || ++ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG) || ++ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE) || ++ (core_if->hwcfg2.b.op_mode == DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST)) ? ++ DWC_OTG_CAP_PARAM_SRP_ONLY_CAPABLE : ++ DWC_OTG_CAP_PARAM_NO_HNP_SRP_CAPABLE)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(dma_enable,"dma_enable", ++ ((dwc_otg_module_params.dma_enable == 1) && (core_if->hwcfg2.b.architecture == 0)) ? 0 : 1, ++ 0); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(opt,"opt", ++ 1, ++ 0); ++ ++ DWC_OTG_PARAM_SET_DEFAULT(dma_burst_size); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_support_fs_ls_low_power, ++ "host_support_fs_ls_low_power", ++ 1, 0); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(enable_dynamic_fifo, ++ "enable_dynamic_fifo", ++ ((dwc_otg_module_params.enable_dynamic_fifo == 0) || ++ (core_if->hwcfg2.b.dynamic_fifo == 1)), 0); ++ ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(data_fifo_size, ++ "data_fifo_size", ++ (dwc_otg_module_params.data_fifo_size <= core_if->hwcfg3.b.dfifo_depth), ++ core_if->hwcfg3.b.dfifo_depth); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(dev_rx_fifo_size, ++ "dev_rx_fifo_size", ++ (dwc_otg_module_params.dev_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), ++ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(dev_nperio_tx_fifo_size, ++ "dev_nperio_tx_fifo_size", ++ (dwc_otg_module_params.dev_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), ++ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_rx_fifo_size, ++ "host_rx_fifo_size", ++ (dwc_otg_module_params.host_rx_fifo_size <= dwc_read_reg32(&core_if->core_global_regs->grxfsiz)), ++ dwc_read_reg32(&core_if->core_global_regs->grxfsiz)); ++ ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_nperio_tx_fifo_size, ++ "host_nperio_tx_fifo_size", ++ (dwc_otg_module_params.host_nperio_tx_fifo_size <= (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)), ++ (dwc_read_reg32(&core_if->core_global_regs->gnptxfsiz) >> 16)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_perio_tx_fifo_size, ++ "host_perio_tx_fifo_size", ++ (dwc_otg_module_params.host_perio_tx_fifo_size <= ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))), ++ ((dwc_read_reg32(&core_if->core_global_regs->hptxfsiz) >> 16))); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(max_transfer_size, ++ "max_transfer_size", ++ (dwc_otg_module_params.max_transfer_size < (1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11))), ++ ((1 << (core_if->hwcfg3.b.xfer_size_cntr_width + 11)) - 1)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(max_packet_count, ++ "max_packet_count", ++ (dwc_otg_module_params.max_packet_count < (1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4))), ++ ((1 << (core_if->hwcfg3.b.packet_size_cntr_width + 4)) - 1)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_channels, ++ "host_channels", ++ (dwc_otg_module_params.host_channels <= (core_if->hwcfg2.b.num_host_chan + 1)), ++ (core_if->hwcfg2.b.num_host_chan + 1)); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(dev_endpoints, ++ "dev_endpoints", ++ (dwc_otg_module_params.dev_endpoints <= (core_if->hwcfg2.b.num_dev_ep)), ++ core_if->hwcfg2.b.num_dev_ep); ++ ++/* ++ * Define the following to disable the FS PHY Hardware checking. This is for ++ * internal testing only. ++ * ++ * #define NO_FS_PHY_HW_CHECKS ++ */ ++ ++#ifdef NO_FS_PHY_HW_CHECKS ++ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, ++ "phy_type", 1, 0); ++#else ++ retval += DWC_OTG_PARAM_CHECK_VALID(phy_type, ++ "phy_type", ++ ({ ++ int valid = 0; ++ if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_UTMI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 1) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) ++ { ++ valid = 1; ++ } ++ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_ULPI) && ++ ((core_if->hwcfg2.b.hs_phy_type == 2) || ++ (core_if->hwcfg2.b.hs_phy_type == 3))) ++ { ++ valid = 1; ++ } ++ else if ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) && ++ (core_if->hwcfg2.b.fs_phy_type == 1)) ++ { ++ valid = 1; ++ } ++ valid; ++ }), ++ ({ ++ int set = DWC_PHY_TYPE_PARAM_FS; ++ if (core_if->hwcfg2.b.hs_phy_type) { ++ if ((core_if->hwcfg2.b.hs_phy_type == 3) || ++ (core_if->hwcfg2.b.hs_phy_type == 1)) { ++ set = DWC_PHY_TYPE_PARAM_UTMI; ++ } ++ else { ++ set = DWC_PHY_TYPE_PARAM_ULPI; ++ } ++ } ++ set; ++ })); ++#endif ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(speed,"speed", ++ (dwc_otg_module_params.speed == 0) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1, ++ dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS ? 1 : 0); ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(host_ls_low_power_phy_clk, ++ "host_ls_low_power_phy_clk", ++ ((dwc_otg_module_params.host_ls_low_power_phy_clk == DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ) && (dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? 0 : 1), ++ ((dwc_otg_module_params.phy_type == DWC_PHY_TYPE_PARAM_FS) ? DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ : DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_48MHZ)); ++ ++ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ddr); ++ DWC_OTG_PARAM_SET_DEFAULT(phy_ulpi_ext_vbus); ++ DWC_OTG_PARAM_SET_DEFAULT(phy_utmi_width); ++ DWC_OTG_PARAM_SET_DEFAULT(ulpi_fs_ls); ++ DWC_OTG_PARAM_SET_DEFAULT(ts_dline); ++ ++#ifdef NO_FS_PHY_HW_CHECKS ++ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, ++ "i2c_enable", 1, 0); ++#else ++ retval += DWC_OTG_PARAM_CHECK_VALID(i2c_enable, ++ "i2c_enable", ++ (dwc_otg_module_params.i2c_enable == 1) && (core_if->hwcfg3.b.i2c == 0) ? 0 : 1, ++ 0); ++#endif ++ ++ for (i=0; i<16; i++) { ++ ++ int changed = 1; ++ int error = 0; ++ ++ if (dwc_otg_module_params.dev_perio_tx_fifo_size[i] == -1) { ++ changed = 0; ++ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_param_dev_perio_tx_fifo_size_default; ++ } ++ if (!(dwc_otg_module_params.dev_perio_tx_fifo_size[i] <= (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { ++ if (changed) { ++ DWC_ERROR("`%d' invalid for parameter `dev_perio_fifo_size_%d'. Check HW configuration.\n", dwc_otg_module_params.dev_perio_tx_fifo_size[i],i); ++ error = 1; ++ } ++ dwc_otg_module_params.dev_perio_tx_fifo_size[i] = dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); ++ } ++ retval += error; ++ } ++ ++ retval += DWC_OTG_PARAM_CHECK_VALID(en_multiple_tx_fifo, ++ "en_multiple_tx_fifo", ++ ((dwc_otg_module_params.en_multiple_tx_fifo == 1) && ++ (core_if->hwcfg4.b.ded_fifo_en == 0)) ? 0 : 1, 0); ++ ++ for (i = 0; i < 16; i++) { ++ int changed = 1; ++ int error = 0; ++ if (dwc_otg_module_params.dev_tx_fifo_size[i] == -1) { ++ changed = 0; ++ dwc_otg_module_params.dev_tx_fifo_size[i] = ++ dwc_param_dev_tx_fifo_size_default; ++ } ++ if (!(dwc_otg_module_params.dev_tx_fifo_size[i] <= ++ (dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i])))) { ++ if (changed) { ++ DWC_ERROR("%d' invalid for parameter `dev_perio_fifo_size_%d'." ++ "Check HW configuration.\n",dwc_otg_module_params.dev_tx_fifo_size[i],i); ++ error = 1; ++ } ++ dwc_otg_module_params.dev_tx_fifo_size[i] = ++ dwc_read_reg32(&core_if->core_global_regs->dptxfsiz_dieptxf[i]); ++ } ++ retval += error; ++ } ++ DWC_OTG_PARAM_SET_DEFAULT(thr_ctl); ++ DWC_OTG_PARAM_SET_DEFAULT(tx_thr_length); ++ DWC_OTG_PARAM_SET_DEFAULT(rx_thr_length); ++ return retval; ++} // check_parameters ++ ++ ++/** ++ * This function is the top level interrupt handler for the Common ++ * (Device and host modes) interrupts. ++ */ ++static irqreturn_t dwc_otg_common_irq(int _irq, void *_dev) ++{ ++ dwc_otg_device_t *otg_dev = _dev; ++ int32_t retval = IRQ_NONE; ++ ++ retval = dwc_otg_handle_common_intr( otg_dev->core_if ); ++ ++ mask_and_ack_ifx_irq (_irq); ++ ++ return IRQ_RETVAL(retval); ++} ++ ++ ++/** ++ * This function is called when a DWC_OTG device is unregistered with the ++ * dwc_otg_driver. This happens, for example, when the rmmod command is ++ * executed. The device may or may not be electrically present. If it is ++ * present, the driver stops device processing. Any resources used on behalf ++ * of this device are freed. ++ * ++ * @return ++ */ ++static int ++dwc_otg_driver_remove(struct platform_device *_dev) ++{ ++ //dwc_otg_device_t *otg_dev = dev_get_drvdata(&_dev->dev); ++ dwc_otg_device_t *otg_dev = platform_get_drvdata(_dev); ++ ++ DWC_DEBUGPL(DBG_ANY, "%s(%p)\n", __func__, _dev); ++ ++ if (otg_dev == NULL) { ++ /* Memory allocation for the dwc_otg_device failed. */ ++ return 0; ++ } ++ ++ /* ++ * Free the IRQ ++ */ ++ if (otg_dev->common_irq_installed) { ++ free_irq( otg_dev->irq, otg_dev ); ++ } ++ ++#ifndef DWC_DEVICE_ONLY ++ if (otg_dev->hcd != NULL) { ++ dwc_otg_hcd_remove(&_dev->dev); ++ } ++#endif ++ printk("after removehcd\n"); ++ ++// Note: Integrate HOST and DEVICE(Gadget) is not planned yet. ++#ifndef DWC_HOST_ONLY ++ if (otg_dev->pcd != NULL) { ++ dwc_otg_pcd_remove(otg_dev); ++ } ++#endif ++ if (otg_dev->core_if != NULL) { ++ dwc_otg_cil_remove( otg_dev->core_if ); ++ } ++ printk("after removecil\n"); ++ ++ /* ++ * Remove the device attributes ++ */ ++ dwc_otg_attr_remove(&_dev->dev); ++ printk("after removeattr\n"); ++ ++ /* ++ * Return the memory. ++ */ ++ if (otg_dev->base != NULL) { ++ iounmap(otg_dev->base); ++ } ++ if (otg_dev->phys_addr != 0) { ++ release_mem_region(otg_dev->phys_addr, otg_dev->base_len); ++ } ++ kfree(otg_dev); ++ ++ /* ++ * Clear the drvdata pointer. ++ */ ++ //dev_set_drvdata(&_dev->dev, 0); ++ platform_set_drvdata(_dev, 0); ++ return 0; ++} ++ ++/** ++ * This function is called when an DWC_OTG device is bound to a ++ * dwc_otg_driver. It creates the driver components required to ++ * control the device (CIL, HCD, and PCD) and it initializes the ++ * device. The driver components are stored in a dwc_otg_device ++ * structure. A reference to the dwc_otg_device is saved in the ++ * lm_device. This allows the driver to access the dwc_otg_device ++ * structure on subsequent calls to driver methods for this device. ++ * ++ * @return ++ */ ++static int __devinit ++dwc_otg_driver_probe(struct platform_device *_dev) ++{ ++ int retval = 0; ++ dwc_otg_device_t *dwc_otg_device; ++ int pin = (int)_dev->dev.platform_data; ++ int32_t snpsid; ++ struct resource *res; ++ gusbcfg_data_t usbcfg = {.d32 = 0}; ++ ++ // GPIOs ++ if(pin >= 0) ++ { ++ gpio_request(pin, "usb_power"); ++ gpio_direction_output(pin, 1); ++ gpio_set_value(pin, 1); ++ gpio_export(pin, 0); ++ } ++ dev_dbg(&_dev->dev, "dwc_otg_driver_probe (%p)\n", _dev); ++ ++ dwc_otg_device = kmalloc(sizeof(dwc_otg_device_t), GFP_KERNEL); ++ if (dwc_otg_device == 0) { ++ dev_err(&_dev->dev, "kmalloc of dwc_otg_device failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ memset(dwc_otg_device, 0, sizeof(*dwc_otg_device)); ++ dwc_otg_device->reg_offset = 0xFFFFFFFF; ++ ++ /* ++ * Retrieve the memory and IRQ resources. ++ */ ++ dwc_otg_device->irq = platform_get_irq(_dev, 0); ++ if (dwc_otg_device->irq == 0) { ++ dev_err(&_dev->dev, "no device irq\n"); ++ retval = -ENODEV; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "OTG - device irq: %d\n", dwc_otg_device->irq); ++ res = platform_get_resource(_dev, IORESOURCE_MEM, 0); ++ if (res == NULL) { ++ dev_err(&_dev->dev, "no CSR address\n"); ++ retval = -ENODEV; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "OTG - ioresource_mem start0x%08x: end:0x%08x\n", ++ (unsigned)res->start, (unsigned)res->end); ++ dwc_otg_device->phys_addr = res->start; ++ dwc_otg_device->base_len = res->end - res->start + 1; ++ if (request_mem_region(dwc_otg_device->phys_addr, dwc_otg_device->base_len, ++ dwc_driver_name) == NULL) { ++ dev_err(&_dev->dev, "request_mem_region failed\n"); ++ retval = -EBUSY; ++ goto fail; ++ } ++ ++ /* ++ * Map the DWC_otg Core memory into virtual address space. ++ */ ++ dwc_otg_device->base = ioremap_nocache(dwc_otg_device->phys_addr, dwc_otg_device->base_len); ++ if (dwc_otg_device->base == NULL) { ++ dev_err(&_dev->dev, "ioremap() failed\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ dev_dbg(&_dev->dev, "mapped base=0x%08x\n", (unsigned)dwc_otg_device->base); ++ ++ /* ++ * Attempt to ensure this device is really a DWC_otg Controller. ++ * Read and verify the SNPSID register contents. The value should be ++ * 0x45F42XXX, which corresponds to "OT2", as in "OTG version 2.XX". ++ */ ++ snpsid = dwc_read_reg32((uint32_t *)((uint8_t *)dwc_otg_device->base + 0x40)); ++ if ((snpsid & 0xFFFFF000) != 0x4F542000) { ++ dev_err(&_dev->dev, "Bad value for SNPSID: 0x%08x\n", snpsid); ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* ++ * Initialize driver data to point to the global DWC_otg ++ * Device structure. ++ */ ++ platform_set_drvdata(_dev, dwc_otg_device); ++ dev_dbg(&_dev->dev, "dwc_otg_device=0x%p\n", dwc_otg_device); ++ dwc_otg_device->core_if = dwc_otg_cil_init( dwc_otg_device->base, &dwc_otg_module_params); ++ if (dwc_otg_device->core_if == 0) { ++ dev_err(&_dev->dev, "CIL initialization failed!\n"); ++ retval = -ENOMEM; ++ goto fail; ++ } ++ ++ /* ++ * Validate parameter values. ++ */ ++ if (check_parameters(dwc_otg_device->core_if) != 0) { ++ retval = -EINVAL; ++ goto fail; ++ } ++ ++ /* Added for PLB DMA phys virt mapping */ ++ //dwc_otg_device->core_if->phys_addr = dwc_otg_device->phys_addr; ++ /* ++ * Create Device Attributes in sysfs ++ */ ++ dwc_otg_attr_create (&_dev->dev); ++ ++ /* ++ * Disable the global interrupt until all the interrupt ++ * handlers are installed. ++ */ ++ dwc_otg_disable_global_interrupts( dwc_otg_device->core_if ); ++ /* ++ * Install the interrupt handler for the common interrupts before ++ * enabling common interrupts in core_init below. ++ */ ++ DWC_DEBUGPL( DBG_CIL, "registering (common) handler for irq%d\n", dwc_otg_device->irq); ++ ++ retval = request_irq((unsigned int)dwc_otg_device->irq, dwc_otg_common_irq, ++ //SA_INTERRUPT|SA_SHIRQ, "dwc_otg", (void *)dwc_otg_device ); ++ IRQF_SHARED, "dwc_otg", (void *)dwc_otg_device ); ++ //IRQF_DISABLED, "dwc_otg", (void *)dwc_otg_device ); ++ if (retval != 0) { ++ DWC_ERROR("request of irq%d failed retval: %d\n", dwc_otg_device->irq, retval); ++ retval = -EBUSY; ++ goto fail; ++ } else { ++ dwc_otg_device->common_irq_installed = 1; ++ } ++ ++ /* ++ * Initialize the DWC_otg core. ++ */ ++ dwc_otg_core_init( dwc_otg_device->core_if ); ++ ++ ++#ifndef DWC_HOST_ONLY // otg device mode. (gadget.) ++ /* ++ * Initialize the PCD ++ */ ++ retval = dwc_otg_pcd_init(dwc_otg_device); ++ if (retval != 0) { ++ DWC_ERROR("dwc_otg_pcd_init failed\n"); ++ dwc_otg_device->pcd = NULL; ++ goto fail; ++ } ++#endif // DWC_HOST_ONLY ++ ++#ifndef DWC_DEVICE_ONLY // otg host mode. (HCD) ++ /* ++ * Initialize the HCD ++ */ ++#if 1 /*fscz*/ ++ /* force_host_mode */ ++ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); ++ usbcfg.b.force_host_mode = 1; ++ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); ++#endif ++ retval = dwc_otg_hcd_init(&_dev->dev, dwc_otg_device); ++ if (retval != 0) { ++ DWC_ERROR("dwc_otg_hcd_init failed\n"); ++ dwc_otg_device->hcd = NULL; ++ goto fail; ++ } ++#endif // DWC_DEVICE_ONLY ++ ++ /* ++ * Enable the global interrupt after all the interrupt ++ * handlers are installed. ++ */ ++ dwc_otg_enable_global_interrupts( dwc_otg_device->core_if ); ++#if 0 /*fscz*/ ++ usbcfg.d32 = dwc_read_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg); ++ usbcfg.b.force_host_mode = 0; ++ dwc_write_reg32(&dwc_otg_device->core_if->core_global_regs ->gusbcfg, usbcfg.d32); ++#endif ++ ++ ++ return 0; ++ ++fail: ++ dwc_otg_driver_remove(_dev); ++ return retval; ++} ++ ++/** ++ * This structure defines the methods to be called by a bus driver ++ * during the lifecycle of a device on that bus. Both drivers and ++ * devices are registered with a bus driver. The bus driver matches ++ * devices to drivers based on information in the device and driver ++ * structures. ++ * ++ * The probe function is called when the bus driver matches a device ++ * to this driver. The remove function is called when a device is ++ * unregistered with the bus driver. ++ */ ++struct platform_driver dwc_otg_driver = { ++ .probe = dwc_otg_driver_probe, ++ .remove = dwc_otg_driver_remove, ++// .suspend = dwc_otg_driver_suspend, ++// .resume = dwc_otg_driver_resume, ++ .driver = { ++ .name = dwc_driver_name, ++ .owner = THIS_MODULE, ++ }, ++}; ++EXPORT_SYMBOL(dwc_otg_driver); ++ ++/** ++ * This function is called when the dwc_otg_driver is installed with the ++ * insmod command. It registers the dwc_otg_driver structure with the ++ * appropriate bus driver. This will cause the dwc_otg_driver_probe function ++ * to be called. In addition, the bus driver will automatically expose ++ * attributes defined for the device and driver in the special sysfs file ++ * system. ++ * ++ * @return ++ */ ++static int __init dwc_otg_init(void) ++{ ++ int retval = 0; ++ ++ printk(KERN_INFO "%s: version %s\n", dwc_driver_name, DWC_DRIVER_VERSION); ++ ++ // ifxmips setup ++ retval = ifx_usb_hc_init(dwc_iomem_base, dwc_irq); ++ if (retval < 0) ++ { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ return retval; ++ } ++ dwc_otg_power_on(); // ifx only!! ++ ++ ++ retval = platform_driver_register(&dwc_otg_driver); ++ ++ if (retval < 0) { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ goto error1; ++ } ++ ++ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_version); ++ if (retval < 0) ++ { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ goto error2; ++ } ++ retval = driver_create_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ if (retval < 0) ++ { ++ printk(KERN_ERR "%s retval=%d\n", __func__, retval); ++ goto error3; ++ } ++ return retval; ++ ++ ++error3: ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++error2: ++ driver_unregister(&dwc_otg_driver.driver); ++error1: ++ ifx_usb_hc_remove(); ++ return retval; ++} ++module_init(dwc_otg_init); ++ ++/** ++ * This function is called when the driver is removed from the kernel ++ * with the rmmod command. The driver unregisters itself with its bus ++ * driver. ++ * ++ */ ++static void __exit dwc_otg_cleanup(void) ++{ ++ printk(KERN_DEBUG "dwc_otg_cleanup()\n"); ++ ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_debuglevel); ++ driver_remove_file(&dwc_otg_driver.driver, &driver_attr_version); ++ ++ platform_driver_unregister(&dwc_otg_driver); ++ ifx_usb_hc_remove(); ++ ++ printk(KERN_INFO "%s module removed\n", dwc_driver_name); ++} ++module_exit(dwc_otg_cleanup); ++ ++MODULE_DESCRIPTION(DWC_DRIVER_DESC); ++MODULE_AUTHOR("Synopsys Inc."); ++MODULE_LICENSE("GPL"); ++ ++module_param_named(otg_cap, dwc_otg_module_params.otg_cap, int, 0444); ++MODULE_PARM_DESC(otg_cap, "OTG Capabilities 0=HNP&SRP 1=SRP Only 2=None"); ++module_param_named(opt, dwc_otg_module_params.opt, int, 0444); ++MODULE_PARM_DESC(opt, "OPT Mode"); ++module_param_named(dma_enable, dwc_otg_module_params.dma_enable, int, 0444); ++MODULE_PARM_DESC(dma_enable, "DMA Mode 0=Slave 1=DMA enabled"); ++module_param_named(dma_burst_size, dwc_otg_module_params.dma_burst_size, int, 0444); ++MODULE_PARM_DESC(dma_burst_size, "DMA Burst Size 1, 4, 8, 16, 32, 64, 128, 256"); ++module_param_named(speed, dwc_otg_module_params.speed, int, 0444); ++MODULE_PARM_DESC(speed, "Speed 0=High Speed 1=Full Speed"); ++module_param_named(host_support_fs_ls_low_power, dwc_otg_module_params.host_support_fs_ls_low_power, int, 0444); ++MODULE_PARM_DESC(host_support_fs_ls_low_power, "Support Low Power w/FS or LS 0=Support 1=Don't Support"); ++module_param_named(host_ls_low_power_phy_clk, dwc_otg_module_params.host_ls_low_power_phy_clk, int, 0444); ++MODULE_PARM_DESC(host_ls_low_power_phy_clk, "Low Speed Low Power Clock 0=48Mhz 1=6Mhz"); ++module_param_named(enable_dynamic_fifo, dwc_otg_module_params.enable_dynamic_fifo, int, 0444); ++MODULE_PARM_DESC(enable_dynamic_fifo, "0=cC Setting 1=Allow Dynamic Sizing"); ++module_param_named(data_fifo_size, dwc_otg_module_params.data_fifo_size, int, 0444); ++MODULE_PARM_DESC(data_fifo_size, "Total number of words in the data FIFO memory 32-32768"); ++module_param_named(dev_rx_fifo_size, dwc_otg_module_params.dev_rx_fifo_size, int, 0444); ++MODULE_PARM_DESC(dev_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(dev_nperio_tx_fifo_size, dwc_otg_module_params.dev_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(dev_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(dev_perio_tx_fifo_size_1, dwc_otg_module_params.dev_perio_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_1, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_2, dwc_otg_module_params.dev_perio_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_2, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_3, dwc_otg_module_params.dev_perio_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_3, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_4, dwc_otg_module_params.dev_perio_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_4, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_5, dwc_otg_module_params.dev_perio_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_5, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_6, dwc_otg_module_params.dev_perio_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_6, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_7, dwc_otg_module_params.dev_perio_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_7, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_8, dwc_otg_module_params.dev_perio_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_8, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_9, dwc_otg_module_params.dev_perio_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_9, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_10, dwc_otg_module_params.dev_perio_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_10, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_11, dwc_otg_module_params.dev_perio_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_11, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_12, dwc_otg_module_params.dev_perio_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_12, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_13, dwc_otg_module_params.dev_perio_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_13, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_14, dwc_otg_module_params.dev_perio_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_14, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(dev_perio_tx_fifo_size_15, dwc_otg_module_params.dev_perio_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_perio_tx_fifo_size_15, "Number of words in the periodic Tx FIFO 4-768"); ++module_param_named(host_rx_fifo_size, dwc_otg_module_params.host_rx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_rx_fifo_size, "Number of words in the Rx FIFO 16-32768"); ++module_param_named(host_nperio_tx_fifo_size, dwc_otg_module_params.host_nperio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_nperio_tx_fifo_size, "Number of words in the non-periodic Tx FIFO 16-32768"); ++module_param_named(host_perio_tx_fifo_size, dwc_otg_module_params.host_perio_tx_fifo_size, int, 0444); ++MODULE_PARM_DESC(host_perio_tx_fifo_size, "Number of words in the host periodic Tx FIFO 16-32768"); ++module_param_named(max_transfer_size, dwc_otg_module_params.max_transfer_size, int, 0444); ++/** @todo Set the max to 512K, modify checks */ ++MODULE_PARM_DESC(max_transfer_size, "The maximum transfer size supported in bytes 2047-65535"); ++module_param_named(max_packet_count, dwc_otg_module_params.max_packet_count, int, 0444); ++MODULE_PARM_DESC(max_packet_count, "The maximum number of packets in a transfer 15-511"); ++module_param_named(host_channels, dwc_otg_module_params.host_channels, int, 0444); ++MODULE_PARM_DESC(host_channels, "The number of host channel registers to use 1-16"); ++module_param_named(dev_endpoints, dwc_otg_module_params.dev_endpoints, int, 0444); ++MODULE_PARM_DESC(dev_endpoints, "The number of endpoints in addition to EP0 available for device mode 1-15"); ++module_param_named(phy_type, dwc_otg_module_params.phy_type, int, 0444); ++MODULE_PARM_DESC(phy_type, "0=Reserved 1=UTMI+ 2=ULPI"); ++module_param_named(phy_utmi_width, dwc_otg_module_params.phy_utmi_width, int, 0444); ++MODULE_PARM_DESC(phy_utmi_width, "Specifies the UTMI+ Data Width 8 or 16 bits"); ++module_param_named(phy_ulpi_ddr, dwc_otg_module_params.phy_ulpi_ddr, int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ddr, "ULPI at double or single data rate 0=Single 1=Double"); ++module_param_named(phy_ulpi_ext_vbus, dwc_otg_module_params.phy_ulpi_ext_vbus, int, 0444); ++MODULE_PARM_DESC(phy_ulpi_ext_vbus, "ULPI PHY using internal or external vbus 0=Internal"); ++module_param_named(i2c_enable, dwc_otg_module_params.i2c_enable, int, 0444); ++MODULE_PARM_DESC(i2c_enable, "FS PHY Interface"); ++module_param_named(ulpi_fs_ls, dwc_otg_module_params.ulpi_fs_ls, int, 0444); ++MODULE_PARM_DESC(ulpi_fs_ls, "ULPI PHY FS/LS mode only"); ++module_param_named(ts_dline, dwc_otg_module_params.ts_dline, int, 0444); ++MODULE_PARM_DESC(ts_dline, "Term select Dline pulsing for all PHYs"); ++module_param_named(debug, g_dbg_lvl, int, 0444); ++MODULE_PARM_DESC(debug, "0"); ++module_param_named(en_multiple_tx_fifo, ++ dwc_otg_module_params.en_multiple_tx_fifo, int, 0444); ++MODULE_PARM_DESC(en_multiple_tx_fifo, ++ "Dedicated Non Periodic Tx FIFOs 0=disabled 1=enabled"); ++module_param_named(dev_tx_fifo_size_1, ++ dwc_otg_module_params.dev_tx_fifo_size[0], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_1, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_2, ++ dwc_otg_module_params.dev_tx_fifo_size[1], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_2, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_3, ++ dwc_otg_module_params.dev_tx_fifo_size[2], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_3, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_4, ++ dwc_otg_module_params.dev_tx_fifo_size[3], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_4, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_5, ++ dwc_otg_module_params.dev_tx_fifo_size[4], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_5, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_6, ++ dwc_otg_module_params.dev_tx_fifo_size[5], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_6, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_7, ++ dwc_otg_module_params.dev_tx_fifo_size[6], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_7, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_8, ++ dwc_otg_module_params.dev_tx_fifo_size[7], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_8, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_9, ++ dwc_otg_module_params.dev_tx_fifo_size[8], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_9, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_10, ++ dwc_otg_module_params.dev_tx_fifo_size[9], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_10, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_11, ++ dwc_otg_module_params.dev_tx_fifo_size[10], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_11, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_12, ++ dwc_otg_module_params.dev_tx_fifo_size[11], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_12, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_13, ++ dwc_otg_module_params.dev_tx_fifo_size[12], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_13, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_14, ++ dwc_otg_module_params.dev_tx_fifo_size[13], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_14, "Number of words in the Tx FIFO 4-768"); ++module_param_named(dev_tx_fifo_size_15, ++ dwc_otg_module_params.dev_tx_fifo_size[14], int, 0444); ++MODULE_PARM_DESC(dev_tx_fifo_size_15, "Number of words in the Tx FIFO 4-768"); ++module_param_named(thr_ctl, dwc_otg_module_params.thr_ctl, int, 0444); ++MODULE_PARM_DESC(thr_ctl, "Thresholding enable flag bit" ++ "0 - non ISO Tx thr., 1 - ISO Tx thr., 2 - Rx thr.- bit 0=disabled 1=enabled"); ++module_param_named(tx_thr_length, dwc_otg_module_params.tx_thr_length, int, 0444); ++MODULE_PARM_DESC(tx_thr_length, "Tx Threshold length in 32 bit DWORDs"); ++module_param_named(rx_thr_length, dwc_otg_module_params.rx_thr_length, int, 0444); ++MODULE_PARM_DESC(rx_thr_length, "Rx Threshold length in 32 bit DWORDs"); ++module_param_named (iomem_base, dwc_iomem_base, ulong, 0444); ++MODULE_PARM_DESC (dwc_iomem_base, "The base address of the DWC_OTG register."); ++module_param_named (irq, dwc_irq, int, 0444); ++MODULE_PARM_DESC (dwc_irq, "The interrupt number"); ++ ++/** @page "Module Parameters" ++ * ++ * The following parameters may be specified when starting the module. ++ * These parameters define how the DWC_otg controller should be ++ * configured. Parameter values are passed to the CIL initialization ++ * function dwc_otg_cil_init ++ * ++ * Example: <code>modprobe dwc_otg speed=1 otg_cap=1</code> ++ * ++ ++ <table> ++ <tr><td>Parameter Name</td><td>Meaning</td></tr> ++ ++ <tr> ++ <td>otg_cap</td> ++ <td>Specifies the OTG capabilities. The driver will automatically detect the ++ value for this parameter if none is specified. ++ - 0: HNP and SRP capable (default, if available) ++ - 1: SRP Only capable ++ - 2: No HNP/SRP capable ++ </td></tr> ++ ++ <tr> ++ <td>dma_enable</td> ++ <td>Specifies whether to use slave or DMA mode for accessing the data FIFOs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Slave ++ - 1: DMA (default, if available) ++ </td></tr> ++ ++ <tr> ++ <td>dma_burst_size</td> ++ <td>The DMA Burst size (applicable only for External DMA Mode). ++ - Values: 1, 4, 8 16, 32, 64, 128, 256 (default 32) ++ </td></tr> ++ ++ <tr> ++ <td>speed</td> ++ <td>Specifies the maximum speed of operation in host and device mode. The ++ actual speed depends on the speed of the attached device and the value of ++ phy_type. ++ - 0: High Speed (default) ++ - 1: Full Speed ++ </td></tr> ++ ++ <tr> ++ <td>host_support_fs_ls_low_power</td> ++ <td>Specifies whether low power mode is supported when attached to a Full ++ Speed or Low Speed device in host mode. ++ - 0: Don't support low power mode (default) ++ - 1: Support low power mode ++ </td></tr> ++ ++ <tr> ++ <td>host_ls_low_power_phy_clk</td> ++ <td>Specifies the PHY clock rate in low power mode when connected to a Low ++ Speed device in host mode. This parameter is applicable only if ++ HOST_SUPPORT_FS_LS_LOW_POWER is enabled. ++ - 0: 48 MHz (default) ++ - 1: 6 MHz ++ </td></tr> ++ ++ <tr> ++ <td>enable_dynamic_fifo</td> ++ <td> Specifies whether FIFOs may be resized by the driver software. ++ - 0: Use cC FIFO size parameters ++ - 1: Allow dynamic FIFO sizing (default) ++ </td></tr> ++ ++ <tr> ++ <td>data_fifo_size</td> ++ <td>Total number of 4-byte words in the data FIFO memory. This memory ++ includes the Rx FIFO, non-periodic Tx FIFO, and periodic Tx FIFOs. ++ - Values: 32 to 32768 (default 8192) ++ ++ Note: The total FIFO memory depth in the FPGA configuration is 8192. ++ </td></tr> ++ ++ <tr> ++ <td>dev_rx_fifo_size</td> ++ <td>Number of 4-byte words in the Rx FIFO in device mode when dynamic ++ FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1064) ++ </td></tr> ++ ++ <tr> ++ <td>dev_nperio_tx_fifo_size</td> ++ <td>Number of 4-byte words in the non-periodic Tx FIFO in device mode when ++ dynamic FIFO sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++ </td></tr> ++ ++ <tr> ++ <td>dev_perio_tx_fifo_size_n (n = 1 to 15)</td> ++ <td>Number of 4-byte words in each of the periodic Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++ </td></tr> ++ ++ <tr> ++ <td>host_rx_fifo_size</td> ++ <td>Number of 4-byte words in the Rx FIFO in host mode when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++ </td></tr> ++ ++ <tr> ++ <td>host_nperio_tx_fifo_size</td> ++ <td>Number of 4-byte words in the non-periodic Tx FIFO in host mode when ++ dynamic FIFO sizing is enabled in the core. ++ - Values: 16 to 32768 (default 1024) ++ </td></tr> ++ ++ <tr> ++ <td>host_perio_tx_fifo_size</td> ++ <td>Number of 4-byte words in the host periodic Tx FIFO when dynamic FIFO ++ sizing is enabled. ++ - Values: 16 to 32768 (default 1024) ++ </td></tr> ++ ++ <tr> ++ <td>max_transfer_size</td> ++ <td>The maximum transfer size supported in bytes. ++ - Values: 2047 to 65,535 (default 65,535) ++ </td></tr> ++ ++ <tr> ++ <td>max_packet_count</td> ++ <td>The maximum number of packets in a transfer. ++ - Values: 15 to 511 (default 511) ++ </td></tr> ++ ++ <tr> ++ <td>host_channels</td> ++ <td>The number of host channel registers to use. ++ - Values: 1 to 16 (default 12) ++ ++ Note: The FPGA configuration supports a maximum of 12 host channels. ++ </td></tr> ++ ++ <tr> ++ <td>dev_endpoints</td> ++ <td>The number of endpoints in addition to EP0 available for device mode ++ operations. ++ - Values: 1 to 15 (default 6 IN and OUT) ++ ++ Note: The FPGA configuration supports a maximum of 6 IN and OUT endpoints in ++ addition to EP0. ++ </td></tr> ++ ++ <tr> ++ <td>phy_type</td> ++ <td>Specifies the type of PHY interface to use. By default, the driver will ++ automatically detect the phy_type. ++ - 0: Full Speed ++ - 1: UTMI+ (default, if available) ++ - 2: ULPI ++ </td></tr> ++ ++ <tr> ++ <td>phy_utmi_width</td> ++ <td>Specifies the UTMI+ Data Width. This parameter is applicable for a ++ phy_type of UTMI+. Also, this parameter is applicable only if the ++ OTG_HSPHY_WIDTH cC parameter was set to "8 and 16 bits", meaning that the ++ core has been configured to work at either data path width. ++ - Values: 8 or 16 bits (default 16) ++ </td></tr> ++ ++ <tr> ++ <td>phy_ulpi_ddr</td> ++ <td>Specifies whether the ULPI operates at double or single data rate. This ++ parameter is only applicable if phy_type is ULPI. ++ - 0: single data rate ULPI interface with 8 bit wide data bus (default) ++ - 1: double data rate ULPI interface with 4 bit wide data bus ++ </td></tr> ++ ++ <tr> ++ <td>i2c_enable</td> ++ <td>Specifies whether to use the I2C interface for full speed PHY. This ++ parameter is only applicable if PHY_TYPE is FS. ++ - 0: Disabled (default) ++ - 1: Enabled ++ </td></tr> ++ ++ <tr> ++ <td>otg_en_multiple_tx_fifo</td> ++ <td>Specifies whether dedicatedto tx fifos are enabled for non periodic IN EPs. ++ The driver will automatically detect the value for this parameter if none is ++ specified. ++ - 0: Disabled ++ - 1: Enabled (default, if available) ++ </td></tr> ++ ++ <tr> ++ <td>dev_tx_fifo_size_n (n = 1 to 15)</td> ++ <td>Number of 4-byte words in each of the Tx FIFOs in device mode ++ when dynamic FIFO sizing is enabled. ++ - Values: 4 to 768 (default 256) ++ </td></tr> ++ ++*/ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_driver.h +@@ -0,0 +1,84 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_driver.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 510275 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_DRIVER_H__) ++#define __DWC_OTG_DRIVER_H__ ++ ++/** @file ++ * This file contains the interface to the Linux driver. ++ */ ++#include "dwc_otg_cil.h" ++ ++/* Type declarations */ ++struct dwc_otg_pcd; ++struct dwc_otg_hcd; ++ ++/** ++ * This structure is a wrapper that encapsulates the driver components used to ++ * manage a single DWC_otg controller. ++ */ ++typedef struct dwc_otg_device ++{ ++ /** Base address returned from ioremap() */ ++ void *base; ++ ++ /** Pointer to the core interface structure. */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Register offset for Diagnostic API.*/ ++ uint32_t reg_offset; ++ ++ /** Pointer to the PCD structure. */ ++ struct dwc_otg_pcd *pcd; ++ ++ /** Pointer to the HCD structure. */ ++ struct dwc_otg_hcd *hcd; ++ ++ /** Flag to indicate whether the common IRQ handler is installed. */ ++ uint8_t common_irq_installed; ++ ++ /** Interrupt request number. */ ++ unsigned int irq; ++ ++ /** Physical address of Control and Status registers, used by ++ * release_mem_region(). ++ */ ++ resource_size_t phys_addr; ++ ++ /** Length of memory region, used by release_mem_region(). */ ++ unsigned long base_len; ++} dwc_otg_device_t; ++ ++//#define dev_dbg(fake, format, arg...) printk(KERN_CRIT __FILE__ ":%d: " format "\n" , __LINE__, ## arg) ++ ++#endif +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_hcd.c +@@ -0,0 +1,2870 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 631780 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the implementation of the HCD. In Linux, the HCD ++ * implements the hc_driver API. ++ */ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++ ++#include <linux/device.h> ++ ++#include <linux/errno.h> ++#include <linux/list.h> ++#include <linux/interrupt.h> ++#include <linux/string.h> ++ ++#include <linux/dma-mapping.h> ++ ++#include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++#include <asm/irq.h> ++#include "dwc_otg_ifx.h" // for Infineon platform specific. ++extern atomic_t release_later; ++ ++static u64 dma_mask = DMA_BIT_MASK(32); ++ ++static const char dwc_otg_hcd_name [] = "dwc_otg_hcd"; ++static const struct hc_driver dwc_otg_hc_driver = ++{ ++ .description = dwc_otg_hcd_name, ++ .product_desc = "DWC OTG Controller", ++ .hcd_priv_size = sizeof(dwc_otg_hcd_t), ++ .irq = dwc_otg_hcd_irq, ++ .flags = HCD_MEMORY | HCD_USB2, ++ //.reset = ++ .start = dwc_otg_hcd_start, ++ //.suspend = ++ //.resume = ++ .stop = dwc_otg_hcd_stop, ++ .urb_enqueue = dwc_otg_hcd_urb_enqueue, ++ .urb_dequeue = dwc_otg_hcd_urb_dequeue, ++ .endpoint_disable = dwc_otg_hcd_endpoint_disable, ++ .get_frame_number = dwc_otg_hcd_get_frame_number, ++ .hub_status_data = dwc_otg_hcd_hub_status_data, ++ .hub_control = dwc_otg_hcd_hub_control, ++ //.hub_suspend = ++ //.hub_resume = ++}; ++ ++ ++/** ++ * Work queue function for starting the HCD when A-Cable is connected. ++ * The dwc_otg_hcd_start() must be called in a process context. ++ */ ++static void hcd_start_func(struct work_struct *work) ++{ ++ struct dwc_otg_hcd *priv = ++ container_of(work, struct dwc_otg_hcd, start_work); ++ struct usb_hcd *usb_hcd = (struct usb_hcd *)priv->_p; ++ DWC_DEBUGPL(DBG_HCDV, "%s() %p\n", __func__, usb_hcd); ++ if (usb_hcd) { ++ dwc_otg_hcd_start(usb_hcd); ++ } ++} ++ ++ ++/** ++ * HCD Callback function for starting the HCD when A-Cable is ++ * connected. ++ * ++ * @param _p void pointer to the <code>struct usb_hcd</code> ++ */ ++static int32_t dwc_otg_hcd_start_cb(void *_p) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_p); ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ hprt0_data_t hprt0; ++ if (core_if->op_state == B_HOST) { ++ /* ++ * Reset the port. During a HNP mode switch the reset ++ * needs to occur within 1ms and have a duration of at ++ * least 50ms. ++ */ ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ ((struct usb_hcd *)_p)->self.is_b_host = 1; ++ } else { ++ ((struct usb_hcd *)_p)->self.is_b_host = 0; ++ } ++ /* Need to start the HCD in a non-interrupt context. */ ++ INIT_WORK(&dwc_otg_hcd->start_work, hcd_start_func); ++ dwc_otg_hcd->_p = _p; ++ schedule_work(&dwc_otg_hcd->start_work); ++ return 1; ++} ++ ++ ++/** ++ * HCD Callback function for stopping the HCD. ++ * ++ * @param _p void pointer to the <code>struct usb_hcd</code> ++ */ ++static int32_t dwc_otg_hcd_stop_cb( void *_p ) ++{ ++ struct usb_hcd *usb_hcd = (struct usb_hcd *)_p; ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); ++ dwc_otg_hcd_stop( usb_hcd ); ++ return 1; ++} ++static void del_xfer_timers(dwc_otg_hcd_t *_hcd) ++{ ++#ifdef DEBUG ++ int i; ++ int num_channels = _hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ del_timer(&_hcd->core_if->hc_xfer_timer[i]); ++ } ++#endif /* */ ++} ++ ++static void del_timers(dwc_otg_hcd_t *_hcd) ++{ ++ del_xfer_timers(_hcd); ++ del_timer(&_hcd->conn_timer); ++} ++ ++/** ++ * Processes all the URBs in a single list of QHs. Completes them with ++ * -ETIMEDOUT and frees the QTD. ++ */ ++static void kill_urbs_in_qh_list(dwc_otg_hcd_t * _hcd, ++ struct list_head *_qh_list) ++{ ++ struct list_head *qh_item; ++ dwc_otg_qh_t *qh; ++ struct list_head *qtd_item; ++ dwc_otg_qtd_t *qtd; ++ ++ list_for_each(qh_item, _qh_list) { ++ qh = list_entry(qh_item, dwc_otg_qh_t, qh_list_entry); ++ for (qtd_item = qh->qtd_list.next; qtd_item != &qh->qtd_list; ++ qtd_item = qh->qtd_list.next) { ++ qtd = list_entry(qtd_item, dwc_otg_qtd_t, qtd_list_entry); ++ if (qtd->urb != NULL) { ++ dwc_otg_hcd_complete_urb(_hcd, qtd->urb,-ETIMEDOUT); ++ } ++ dwc_otg_hcd_qtd_remove_and_free(qtd); ++ } ++ } ++} ++ ++/** ++ * Responds with an error status of ETIMEDOUT to all URBs in the non-periodic ++ * and periodic schedules. The QTD associated with each URB is removed from ++ * the schedule and freed. This function may be called when a disconnect is ++ * detected or when the HCD is being stopped. ++ */ ++static void kill_all_urbs(dwc_otg_hcd_t *_hcd) ++{ ++ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_deferred); ++ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_inactive); ++ kill_urbs_in_qh_list(_hcd, &_hcd->non_periodic_sched_active); ++ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_inactive); ++ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_ready); ++ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_assigned); ++ kill_urbs_in_qh_list(_hcd, &_hcd->periodic_sched_queued); ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param _p void pointer to the <code>struct usb_hcd</code> ++ */ ++static int32_t dwc_otg_hcd_disconnect_cb( void *_p ) ++{ ++ gintsts_data_t intr; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); ++ ++ /* ++ * Set status flags for the hub driver. ++ */ ++ dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ dwc_otg_hcd->flags.b.port_connect_status = 0; ++ ++ /* ++ * Shutdown any transfers in process by clearing the Tx FIFO Empty ++ * interrupt mask and status bits and disabling subsequent host ++ * channel interrupts. ++ */ ++ intr.d32 = 0; ++ intr.b.nptxfempty = 1; ++ intr.b.ptxfempty = 1; ++ intr.b.hcintr = 1; ++ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, intr.d32, 0); ++ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintsts, intr.d32, 0); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* ++ * Turn off the vbus power only if the core has transitioned to device ++ * mode. If still in host mode, need to keep power on to detect a ++ * reconnection. ++ */ ++ if (dwc_otg_is_device_mode(dwc_otg_hcd->core_if)) { ++ if (dwc_otg_hcd->core_if->op_state != A_SUSPEND) { ++ hprt0_data_t hprt0 = { .d32=0 }; ++ DWC_PRINT("Disconnect: PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); ++ } ++ ++ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); ++ } ++ ++ /* Respond with an error status to all URBs in the schedule. */ ++ kill_all_urbs(dwc_otg_hcd); ++ ++ if (dwc_otg_is_host_mode(dwc_otg_hcd->core_if)) { ++ /* Clean up any host channels that were in use. */ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ ++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; ++ ++ if (!dwc_otg_hcd->core_if->dma_enable) { ++ /* Flush out any channel requests in slave mode. */ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (list_empty(&channel->hc_list_entry)) { ++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ hcchar.b.chen = 0; ++ hcchar.b.chdis = 1; ++ hcchar.b.epdir = 0; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ } ++ } ++ } ++ } ++ ++ for (i = 0; i < num_channels; i++) { ++ channel = dwc_otg_hcd->hc_ptr_array[i]; ++ if (list_empty(&channel->hc_list_entry)) { ++ hc_regs = dwc_otg_hcd->core_if->host_if->hc_regs[i]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ /* Halt the channel. */ ++ hcchar.b.chdis = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ } ++ ++ dwc_otg_hc_cleanup(dwc_otg_hcd->core_if, channel); ++ list_add_tail(&channel->hc_list_entry, ++ &dwc_otg_hcd->free_hc_list); ++ } ++ } ++ } ++ ++ /* A disconnect will end the session so the B-Device is no ++ * longer a B-host. */ ++ ((struct usb_hcd *)_p)->self.is_b_host = 0; ++ ++ return 1; ++} ++ ++/** ++ * Connection timeout function. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. ++ */ ++void dwc_otg_hcd_connect_timeout( unsigned long _ptr ) ++{ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%x)\n", __func__, (int)_ptr); ++ DWC_PRINT( "Connect Timeout\n"); ++ DWC_ERROR( "Device Not Connected/Responding\n" ); ++} ++ ++/** ++ * Start the connection timer. An OTG host is required to display a ++ * message if the device does not connect within 10 seconds. The ++ * timer is deleted if a port connect interrupt occurs before the ++ * timer expires. ++ */ ++static void dwc_otg_hcd_start_connect_timer( dwc_otg_hcd_t *_hcd) ++{ ++ init_timer( &_hcd->conn_timer ); ++ _hcd->conn_timer.function = dwc_otg_hcd_connect_timeout; ++ _hcd->conn_timer.data = (unsigned long)0; ++ _hcd->conn_timer.expires = jiffies + (HZ*10); ++ add_timer( &_hcd->conn_timer ); ++} ++ ++/** ++ * HCD Callback function for disconnect of the HCD. ++ * ++ * @param _p void pointer to the <code>struct usb_hcd</code> ++ */ ++static int32_t dwc_otg_hcd_session_start_cb( void *_p ) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_p); ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p)\n", __func__, _p); ++ dwc_otg_hcd_start_connect_timer( dwc_otg_hcd ); ++ return 1; ++} ++ ++/** ++ * HCD Callback structure for handling mode switching. ++ */ ++static dwc_otg_cil_callbacks_t hcd_cil_callbacks = { ++ .start = dwc_otg_hcd_start_cb, ++ .stop = dwc_otg_hcd_stop_cb, ++ .disconnect = dwc_otg_hcd_disconnect_cb, ++ .session_start = dwc_otg_hcd_session_start_cb, ++ .p = 0, ++}; ++ ++ ++/** ++ * Reset tasklet function ++ */ ++static void reset_tasklet_func (unsigned long data) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = (dwc_otg_hcd_t*)data; ++ dwc_otg_core_if_t *core_if = dwc_otg_hcd->core_if; ++ hprt0_data_t hprt0; ++ ++ DWC_DEBUGPL(DBG_HCDV, "USB RESET tasklet called\n"); ++ ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ mdelay (60); ++ ++ hprt0.b.prtrst = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ dwc_otg_hcd->flags.b.port_reset_change = 1; ++ ++ return; ++} ++ ++static struct tasklet_struct reset_tasklet = { ++ .next = NULL, ++ .state = 0, ++ .count = ATOMIC_INIT(0), ++ .func = reset_tasklet_func, ++ .data = 0, ++}; ++ ++/** ++ * Initializes the HCD. This function allocates memory for and initializes the ++ * static parts of the usb_hcd and dwc_otg_hcd structures. It also registers the ++ * USB bus with the core and calls the hc_driver->start() function. It returns ++ * a negative error on failure. ++ */ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd); ++ ++int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device) ++{ ++ struct usb_hcd *hcd = NULL; ++ dwc_otg_hcd_t *dwc_otg_hcd = NULL; ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ ++ int retval = 0; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD INIT\n"); ++ ++ /* ++ * Allocate memory for the base HCD plus the DWC OTG HCD. ++ * Initialize the base HCD. ++ */ ++ hcd = usb_create_hcd(&dwc_otg_hc_driver, _dev, dev_name(_dev)); ++ if (hcd == NULL) { ++ retval = -ENOMEM; ++ goto error1; ++ } ++ dev_set_drvdata(_dev, dwc_otg_device); /* fscz restore */ ++ hcd->regs = otg_dev->base; ++ hcd->rsrc_start = (int)otg_dev->base; ++ ++ hcd->self.otg_port = 1; ++ ++ /* Initialize the DWC OTG HCD. */ ++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(hcd); ++ dwc_otg_hcd->core_if = otg_dev->core_if; ++ otg_dev->hcd = dwc_otg_hcd; ++ ++ /* Register the HCD CIL Callbacks */ ++ dwc_otg_cil_register_hcd_callbacks(otg_dev->core_if, ++ &hcd_cil_callbacks, hcd); ++ ++ /* Initialize the non-periodic schedule. */ ++ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_inactive); ++ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_active); ++ INIT_LIST_HEAD(&dwc_otg_hcd->non_periodic_sched_deferred); ++ ++ /* Initialize the periodic schedule. */ ++ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_inactive); ++ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_ready); ++ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_assigned); ++ INIT_LIST_HEAD(&dwc_otg_hcd->periodic_sched_queued); ++ ++ /* ++ * Create a host channel descriptor for each host channel implemented ++ * in the controller. Initialize the channel descriptor array. ++ */ ++ INIT_LIST_HEAD(&dwc_otg_hcd->free_hc_list); ++ num_channels = dwc_otg_hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ channel = kmalloc(sizeof(dwc_hc_t), GFP_KERNEL); ++ if (channel == NULL) { ++ retval = -ENOMEM; ++ DWC_ERROR("%s: host channel allocation failed\n", __func__); ++ goto error2; ++ } ++ memset(channel, 0, sizeof(dwc_hc_t)); ++ channel->hc_num = i; ++ dwc_otg_hcd->hc_ptr_array[i] = channel; ++#ifdef DEBUG ++ init_timer(&dwc_otg_hcd->core_if->hc_xfer_timer[i]); ++#endif ++ ++ DWC_DEBUGPL(DBG_HCDV, "HCD Added channel #%d, hc=%p\n", i, channel); ++ } ++ ++ /* Initialize the Connection timeout timer. */ ++ init_timer( &dwc_otg_hcd->conn_timer ); ++ ++ /* Initialize reset tasklet. */ ++ reset_tasklet.data = (unsigned long) dwc_otg_hcd; ++ dwc_otg_hcd->reset_tasklet = &reset_tasklet; ++ ++ /* Set device flags indicating whether the HCD supports DMA. */ ++ if (otg_dev->core_if->dma_enable) { ++ DWC_PRINT("Using DMA mode\n"); ++ //_dev->dma_mask = (void *)~0; ++ //_dev->coherent_dma_mask = ~0; ++ _dev->dma_mask = &dma_mask; ++ _dev->coherent_dma_mask = DMA_BIT_MASK(32); ++ } else { ++ DWC_PRINT("Using Slave mode\n"); ++ _dev->dma_mask = (void *)0; ++ _dev->coherent_dma_mask = 0; ++ } ++ ++ init_hcd_usecs(dwc_otg_hcd); ++ /* ++ * Finish generic HCD initialization and start the HCD. This function ++ * allocates the DMA buffer pool, registers the USB bus, requests the ++ * IRQ line, and calls dwc_otg_hcd_start method. ++ */ ++ retval = usb_add_hcd(hcd, otg_dev->irq, IRQF_SHARED); ++ if (retval < 0) { ++ goto error2; ++ } ++ ++ /* ++ * Allocate space for storing data on status transactions. Normally no ++ * data is sent, but this space acts as a bit bucket. This must be ++ * done after usb_add_hcd since that function allocates the DMA buffer ++ * pool. ++ */ ++ if (otg_dev->core_if->dma_enable) { ++ dwc_otg_hcd->status_buf = ++ dma_alloc_coherent(_dev, ++ DWC_OTG_HCD_STATUS_BUF_SIZE, ++ &dwc_otg_hcd->status_buf_dma, ++ GFP_KERNEL | GFP_DMA); ++ } else { ++ dwc_otg_hcd->status_buf = kmalloc(DWC_OTG_HCD_STATUS_BUF_SIZE, ++ GFP_KERNEL); ++ } ++ if (dwc_otg_hcd->status_buf == NULL) { ++ retval = -ENOMEM; ++ DWC_ERROR("%s: status_buf allocation failed\n", __func__); ++ goto error3; ++ } ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Initialized HCD, bus=%s, usbbus=%d\n", ++ dev_name(_dev), hcd->self.busnum); ++ ++ return 0; ++ ++ /* Error conditions */ ++error3: ++ usb_remove_hcd(hcd); ++error2: ++ dwc_otg_hcd_free(hcd); ++ usb_put_hcd(hcd); ++error1: ++ return retval; ++} ++ ++/** ++ * Removes the HCD. ++ * Frees memory and resources associated with the HCD and deregisters the bus. ++ */ ++void dwc_otg_hcd_remove(struct device *_dev) ++{ ++ dwc_otg_device_t *otg_dev = dev_get_drvdata(_dev); ++ dwc_otg_hcd_t *dwc_otg_hcd = otg_dev->hcd; ++ struct usb_hcd *hcd = dwc_otg_hcd_to_hcd(dwc_otg_hcd); ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD REMOVE\n"); ++ ++ /* Turn off all interrupts */ ++ dwc_write_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gintmsk, 0); ++ dwc_modify_reg32 (&dwc_otg_hcd->core_if->core_global_regs->gahbcfg, 1, 0); ++ ++ usb_remove_hcd(hcd); ++ ++ dwc_otg_hcd_free(hcd); ++ ++ usb_put_hcd(hcd); ++ ++ return; ++} ++ ++ ++/* ========================================================================= ++ * Linux HC Driver Functions ++ * ========================================================================= */ ++ ++/** ++ * Initializes dynamic portions of the DWC_otg HCD state. ++ */ ++static void hcd_reinit(dwc_otg_hcd_t *_hcd) ++{ ++ struct list_head *item; ++ int num_channels; ++ int i; ++ dwc_hc_t *channel; ++ ++ _hcd->flags.d32 = 0; ++ ++ _hcd->non_periodic_qh_ptr = &_hcd->non_periodic_sched_active; ++ _hcd->available_host_channels = _hcd->core_if->core_params->host_channels; ++ ++ /* ++ * Put all channels in the free channel list and clean up channel ++ * states. ++ */ ++ item = _hcd->free_hc_list.next; ++ while (item != &_hcd->free_hc_list) { ++ list_del(item); ++ item = _hcd->free_hc_list.next; ++ } ++ num_channels = _hcd->core_if->core_params->host_channels; ++ for (i = 0; i < num_channels; i++) { ++ channel = _hcd->hc_ptr_array[i]; ++ list_add_tail(&channel->hc_list_entry, &_hcd->free_hc_list); ++ dwc_otg_hc_cleanup(_hcd->core_if, channel); ++ } ++ ++ /* Initialize the DWC core for host mode operation. */ ++ dwc_otg_core_host_init(_hcd->core_if); ++} ++ ++/** Initializes the DWC_otg controller and its root hub and prepares it for host ++ * mode operation. Activates the root port. Returns 0 on success and a negative ++ * error code on failure. */ ++int dwc_otg_hcd_start(struct usb_hcd *_hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ dwc_otg_core_if_t * core_if = dwc_otg_hcd->core_if; ++ struct usb_bus *bus; ++ ++ // int retval; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD START\n"); ++ ++ bus = hcd_to_bus(_hcd); ++ ++ /* Initialize the bus state. If the core is in Device Mode ++ * HALT the USB bus and return. */ ++ if (dwc_otg_is_device_mode (core_if)) { ++ _hcd->state = HC_STATE_HALT; ++ return 0; ++ } ++ _hcd->state = HC_STATE_RUNNING; ++ ++ /* Initialize and connect root hub if one is not already attached */ ++ if (bus->root_hub) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Has Root Hub\n"); ++ /* Inform the HUB driver to resume. */ ++ usb_hcd_resume_root_hub(_hcd); ++ } ++ else { ++#if 0 ++ struct usb_device *udev; ++ udev = usb_alloc_dev(NULL, bus, 0); ++ if (!udev) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); ++ return -ENODEV; ++ } ++ udev->speed = USB_SPEED_HIGH; ++ /* Not needed - VJ ++ if ((retval = usb_hcd_register_root_hub(udev, _hcd)) != 0) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error registering %d\n", retval); ++ return -ENODEV; ++ } ++ */ ++#else ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Error udev alloc\n"); ++#endif ++ } ++ ++ hcd_reinit(dwc_otg_hcd); ++ ++ return 0; ++} ++ ++static void qh_list_free(dwc_otg_hcd_t *_hcd, struct list_head *_qh_list) ++{ ++ struct list_head *item; ++ dwc_otg_qh_t *qh; ++ ++ if (_qh_list->next == NULL) { ++ /* The list hasn't been initialized yet. */ ++ return; ++ } ++ ++ /* Ensure there are no QTDs or URBs left. */ ++ kill_urbs_in_qh_list(_hcd, _qh_list); ++ ++ for (item = _qh_list->next; item != _qh_list; item = _qh_list->next) { ++ qh = list_entry(item, dwc_otg_qh_t, qh_list_entry); ++ dwc_otg_hcd_qh_remove_and_free(_hcd, qh); ++ } ++} ++ ++/** ++ * Halts the DWC_otg host mode operations in a clean manner. USB transfers are ++ * stopped. ++ */ ++void dwc_otg_hcd_stop(struct usb_hcd *_hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ hprt0_data_t hprt0 = { .d32=0 }; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD STOP\n"); ++ ++ /* Turn off all host-specific interrupts. */ ++ dwc_otg_disable_host_interrupts( dwc_otg_hcd->core_if ); ++ ++ /* ++ * The root hub should be disconnected before this function is called. ++ * The disconnect will clear the QTD lists (via ..._hcd_urb_dequeue) ++ * and the QH lists (via ..._hcd_endpoint_disable). ++ */ ++ ++ /* Turn off the vbus power */ ++ DWC_PRINT("PortPower off\n"); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(dwc_otg_hcd->core_if->host_if->hprt0, hprt0.d32); ++ ++ return; ++} ++ ++ ++/** Returns the current frame number. */ ++int dwc_otg_hcd_get_frame_number(struct usb_hcd *_hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); ++ hfnum_data_t hfnum; ++ ++ hfnum.d32 = dwc_read_reg32(&dwc_otg_hcd->core_if-> ++ host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD GET FRAME NUMBER %d\n", hfnum.b.frnum); ++#endif ++ return hfnum.b.frnum; ++} ++ ++/** ++ * Frees secondary storage associated with the dwc_otg_hcd structure contained ++ * in the struct usb_hcd field. ++ */ ++void dwc_otg_hcd_free(struct usb_hcd *_hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); ++ int i; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD FREE\n"); ++ ++ del_timers(dwc_otg_hcd); ++ ++ /* Free memory for QH/QTD lists */ ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_deferred); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->non_periodic_sched_active); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_inactive); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_ready); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_assigned); ++ qh_list_free(dwc_otg_hcd, &dwc_otg_hcd->periodic_sched_queued); ++ ++ /* Free memory for the host channels. */ ++ for (i = 0; i < MAX_EPS_CHANNELS; i++) { ++ dwc_hc_t *hc = dwc_otg_hcd->hc_ptr_array[i]; ++ if (hc != NULL) { ++ DWC_DEBUGPL(DBG_HCDV, "HCD Free channel #%i, hc=%p\n", i, hc); ++ kfree(hc); ++ } ++ } ++ ++ if (dwc_otg_hcd->core_if->dma_enable) { ++ if (dwc_otg_hcd->status_buf_dma) { ++ dma_free_coherent(_hcd->self.controller, ++ DWC_OTG_HCD_STATUS_BUF_SIZE, ++ dwc_otg_hcd->status_buf, ++ dwc_otg_hcd->status_buf_dma); ++ } ++ } else if (dwc_otg_hcd->status_buf != NULL) { ++ kfree(dwc_otg_hcd->status_buf); ++ } ++ ++ return; ++} ++ ++ ++#ifdef DEBUG ++static void dump_urb_info(struct urb *_urb, char* _fn_name) ++{ ++ DWC_PRINT("%s, urb %p\n", _fn_name, _urb); ++ DWC_PRINT(" Device address: %d\n", usb_pipedevice(_urb->pipe)); ++ DWC_PRINT(" Endpoint: %d, %s\n", usb_pipeendpoint(_urb->pipe), ++ (usb_pipein(_urb->pipe) ? "IN" : "OUT")); ++ DWC_PRINT(" Endpoint type: %s\n", ++ ({char *pipetype; ++ switch (usb_pipetype(_urb->pipe)) { ++ case PIPE_CONTROL: pipetype = "CONTROL"; break; ++ case PIPE_BULK: pipetype = "BULK"; break; ++ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; ++ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; ++ default: pipetype = "UNKNOWN"; break; ++ }; pipetype;})); ++ DWC_PRINT(" Speed: %s\n", ++ ({char *speed; ++ switch (_urb->dev->speed) { ++ case USB_SPEED_HIGH: speed = "HIGH"; break; ++ case USB_SPEED_FULL: speed = "FULL"; break; ++ case USB_SPEED_LOW: speed = "LOW"; break; ++ default: speed = "UNKNOWN"; break; ++ }; speed;})); ++ DWC_PRINT(" Max packet size: %d\n", ++ usb_maxpacket(_urb->dev, _urb->pipe, usb_pipeout(_urb->pipe))); ++ DWC_PRINT(" Data buffer length: %d\n", _urb->transfer_buffer_length); ++ DWC_PRINT(" Transfer buffer: %p, Transfer DMA: %p\n", ++ _urb->transfer_buffer, (void *)_urb->transfer_dma); ++ DWC_PRINT(" Setup buffer: %p, Setup DMA: %p\n", ++ _urb->setup_packet, (void *)_urb->setup_dma); ++ DWC_PRINT(" Interval: %d\n", _urb->interval); ++ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < _urb->number_of_packets; i++) { ++ DWC_PRINT(" ISO Desc %d:\n", i); ++ DWC_PRINT(" offset: %d, length %d\n", ++ _urb->iso_frame_desc[i].offset, ++ _urb->iso_frame_desc[i].length); ++ } ++ } ++} ++ ++static void dump_channel_info(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *qh) ++{ ++ if (qh->channel != NULL) { ++ dwc_hc_t *hc = qh->channel; ++ struct list_head *item; ++ dwc_otg_qh_t *qh_item; ++ int num_channels = _hcd->core_if->core_params->host_channels; ++ int i; ++ ++ dwc_otg_hc_regs_t *hc_regs; ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ ++ hc_regs = _hcd->core_if->host_if->hc_regs[hc->hc_num]; ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcsplt.d32 = dwc_read_reg32(&hc_regs->hcsplt); ++ hctsiz.d32 = dwc_read_reg32(&hc_regs->hctsiz); ++ hcdma = dwc_read_reg32(&hc_regs->hcdma); ++ ++ DWC_PRINT(" Assigned to channel %p:\n", hc); ++ DWC_PRINT(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); ++ DWC_PRINT(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); ++ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINT(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINT(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINT(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINT(" qh: %p\n", hc->qh); ++ DWC_PRINT(" NP inactive sched:\n"); ++ list_for_each(item, &_hcd->non_periodic_sched_inactive) { ++ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINT(" %p\n", qh_item); ++ } DWC_PRINT(" NP active sched:\n"); ++ list_for_each(item, &_hcd->non_periodic_sched_deferred) { ++ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINT(" %p\n", qh_item); ++ } DWC_PRINT(" NP deferred sched:\n"); ++ list_for_each(item, &_hcd->non_periodic_sched_active) { ++ qh_item = list_entry(item, dwc_otg_qh_t, qh_list_entry); ++ DWC_PRINT(" %p\n", qh_item); ++ } DWC_PRINT(" Channels: \n"); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = _hcd->hc_ptr_array[i]; ++ DWC_PRINT(" %2d: %p\n", i, hc); ++ } ++ } ++} ++#endif // DEBUG ++ ++/** Starts processing a USB transfer request specified by a USB Request Block ++ * (URB). mem_flags indicates the type of memory allocation to use while ++ * processing this URB. */ ++int dwc_otg_hcd_urb_enqueue(struct usb_hcd *_hcd, ++ struct urb *_urb, ++ gfp_t _mem_flags) ++{ ++ unsigned long flags; ++ int retval; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ dwc_otg_qtd_t *qtd; ++ ++ local_irq_save(flags); ++ retval = usb_hcd_link_urb_to_ep(_hcd, _urb); ++ if (retval) { ++ local_irq_restore(flags); ++ return retval; ++ } ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(_urb, "dwc_otg_hcd_urb_enqueue"); ++ } ++#endif // DEBUG ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* No longer connected. */ ++ local_irq_restore(flags); ++ return -ENODEV; ++ } ++ ++ qtd = dwc_otg_hcd_qtd_create (_urb); ++ if (qtd == NULL) { ++ local_irq_restore(flags); ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed creating QTD\n"); ++ return -ENOMEM; ++ } ++ ++ retval = dwc_otg_hcd_qtd_add (qtd, dwc_otg_hcd); ++ if (retval < 0) { ++ DWC_ERROR("DWC OTG HCD URB Enqueue failed adding QTD. " ++ "Error status %d\n", retval); ++ dwc_otg_hcd_qtd_free(qtd); ++ } ++ ++ local_irq_restore (flags); ++ return retval; ++} ++ ++/** Aborts/cancels a USB transfer request. Always returns 0 to indicate ++ * success. */ ++int dwc_otg_hcd_urb_dequeue(struct usb_hcd *_hcd, struct urb *_urb, int _status) ++{ ++ unsigned long flags; ++ dwc_otg_hcd_t *dwc_otg_hcd; ++ dwc_otg_qtd_t *urb_qtd; ++ dwc_otg_qh_t *qh; ++ int retval; ++ //struct usb_host_endpoint *_ep = NULL; ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Dequeue\n"); ++ ++ local_irq_save(flags); ++ ++ retval = usb_hcd_check_unlink_urb(_hcd, _urb, _status); ++ if (retval) { ++ local_irq_restore(flags); ++ return retval; ++ } ++ ++ dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); ++ urb_qtd = (dwc_otg_qtd_t *)_urb->hcpriv; ++ if (urb_qtd == NULL) { ++ printk("urb_qtd is NULL for _urb %08x\n",(unsigned)_urb); ++ goto done; ++ } ++ qh = (dwc_otg_qh_t *) urb_qtd->qtd_qh_ptr; ++ if (qh == NULL) { ++ goto done; ++ } ++ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ dump_urb_info(_urb, "dwc_otg_hcd_urb_dequeue"); ++ if (urb_qtd == qh->qtd_in_process) { ++ dump_channel_info(dwc_otg_hcd, qh); ++ } ++ } ++#endif // DEBUG ++ ++ if (urb_qtd == qh->qtd_in_process) { ++ /* The QTD is in process (it has been assigned to a channel). */ ++ ++ if (dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * If still connected (i.e. in host mode), halt the ++ * channel so it can be used for other transfers. If ++ * no longer connected, the host registers can't be ++ * written to halt the channel since the core is in ++ * device mode. ++ */ ++ dwc_otg_hc_halt(dwc_otg_hcd->core_if, qh->channel, ++ DWC_OTG_HC_XFER_URB_DEQUEUE); ++ } ++ } ++ ++ /* ++ * Free the QTD and clean up the associated QH. Leave the QH in the ++ * schedule if it has any remaining QTDs. ++ */ ++ dwc_otg_hcd_qtd_remove_and_free(urb_qtd); ++ if (urb_qtd == qh->qtd_in_process) { ++ dwc_otg_hcd_qh_deactivate(dwc_otg_hcd, qh, 0); ++ qh->channel = NULL; ++ qh->qtd_in_process = NULL; ++ } else if (list_empty(&qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(dwc_otg_hcd, qh); ++ } ++ ++done: ++ local_irq_restore(flags); ++ _urb->hcpriv = NULL; ++ ++ /* Higher layer software sets URB status. */ ++ usb_hcd_unlink_urb_from_ep(_hcd, _urb); ++ usb_hcd_giveback_urb(_hcd, _urb, _status); ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINT("Called usb_hcd_giveback_urb()\n"); ++ DWC_PRINT(" urb->status = %d\n", _urb->status); ++ } ++ ++ return 0; ++} ++ ++ ++/** Frees resources in the DWC_otg controller related to a given endpoint. Also ++ * clears state in the HCD related to the endpoint. Any URBs for the endpoint ++ * must already be dequeued. */ ++void dwc_otg_hcd_endpoint_disable(struct usb_hcd *_hcd, ++ struct usb_host_endpoint *_ep) ++ ++{ ++ dwc_otg_qh_t *qh; ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd(_hcd); ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD EP DISABLE: _bEndpointAddress=0x%02x, " ++ "endpoint=%d\n", _ep->desc.bEndpointAddress, ++ dwc_ep_addr_to_endpoint(_ep->desc.bEndpointAddress)); ++ ++ qh = (dwc_otg_qh_t *)(_ep->hcpriv); ++ if (qh != NULL) { ++#ifdef DEBUG ++ /** Check that the QTD list is really empty */ ++ if (!list_empty(&qh->qtd_list)) { ++ DWC_WARN("DWC OTG HCD EP DISABLE:" ++ " QTD List for this endpoint is not empty\n"); ++ } ++#endif // DEBUG ++ ++ dwc_otg_hcd_qh_remove_and_free(dwc_otg_hcd, qh); ++ _ep->hcpriv = NULL; ++ } ++ ++ return; ++} ++extern int dwc_irq; ++/** Handles host mode interrupts for the DWC_otg controller. Returns IRQ_NONE if ++ * there was no interrupt to handle. Returns IRQ_HANDLED if there was a valid ++ * interrupt. ++ * ++ * This function is called by the USB core when an interrupt occurs */ ++irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *_hcd) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ ++ mask_and_ack_ifx_irq (dwc_irq); ++ return IRQ_RETVAL(dwc_otg_hcd_handle_intr(dwc_otg_hcd)); ++} ++ ++/** Creates Status Change bitmap for the root hub and root port. The bitmap is ++ * returned in buf. Bit 0 is the status change indicator for the root hub. Bit 1 ++ * is the status change indicator for the single root port. Returns 1 if either ++ * change indicator is 1, otherwise returns 0. */ ++int dwc_otg_hcd_hub_status_data(struct usb_hcd *_hcd, char *_buf) ++{ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ ++ _buf[0] = 0; ++ _buf[0] |= (dwc_otg_hcd->flags.b.port_connect_status_change || ++ dwc_otg_hcd->flags.b.port_reset_change || ++ dwc_otg_hcd->flags.b.port_enable_change || ++ dwc_otg_hcd->flags.b.port_suspend_change || ++ dwc_otg_hcd->flags.b.port_over_current_change) << 1; ++ ++#ifdef DEBUG ++ if (_buf[0]) { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD HUB STATUS DATA:" ++ " Root port status changed\n"); ++ DWC_DEBUGPL(DBG_HCDV, " port_connect_status_change: %d\n", ++ dwc_otg_hcd->flags.b.port_connect_status_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_reset_change: %d\n", ++ dwc_otg_hcd->flags.b.port_reset_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_enable_change: %d\n", ++ dwc_otg_hcd->flags.b.port_enable_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_suspend_change: %d\n", ++ dwc_otg_hcd->flags.b.port_suspend_change); ++ DWC_DEBUGPL(DBG_HCDV, " port_over_current_change: %d\n", ++ dwc_otg_hcd->flags.b.port_over_current_change); ++ } ++#endif // DEBUG ++ return (_buf[0] != 0); ++} ++ ++#ifdef DWC_HS_ELECT_TST ++/* ++ * Quick and dirty hack to implement the HS Electrical Test ++ * SINGLE_STEP_GET_DEVICE_DESCRIPTOR feature. ++ * ++ * This code was copied from our userspace app "hset". It sends a ++ * Get Device Descriptor control sequence in two parts, first the ++ * Setup packet by itself, followed some time later by the In and ++ * Ack packets. Rather than trying to figure out how to add this ++ * functionality to the normal driver code, we just hijack the ++ * hardware, using these two function to drive the hardware ++ * directly. ++ */ ++ ++dwc_otg_core_global_regs_t *global_regs; ++dwc_otg_host_global_regs_t *hc_global_regs; ++dwc_otg_hc_regs_t *hc_regs; ++uint32_t *data_fifo; ++ ++static void do_setup(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ ++ /* Enable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* ++ * Send Setup packet (Get Device Descriptor) ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ //fprintf(stderr, "Channel already enabled 1, HCCHAR = %08x\n", hcchar.d32); ++ hcchar.b.chdis = 1; ++ // hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ MDELAY(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //if (hcchar.b.chen) { ++ // fprintf(stderr, "** Channel _still_ enabled 1, HCCHAR = %08x **\n", hcchar.d32); ++ //} ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_SETUP; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ /* Fill FIFO with Setup data for Get Device Descriptor */ ++ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); ++ dwc_write_reg32(data_fifo++, 0x01000680); ++ dwc_write_reg32(data_fifo++, 0x00080000); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "Waiting for HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ //fprintf(stderr, "Got HCINTR intr 1, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Disable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++} ++ ++static void do_in_ack(void) ++{ ++ gintsts_data_t gintsts; ++ hctsiz_data_t hctsiz; ++ hcchar_data_t hcchar; ++ haint_data_t haint; ++ hcint_data_t hcint; ++ host_grxsts_data_t grxsts; ++ ++ /* Enable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0001); ++ ++ /* Enable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x04a3); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* ++ * Receive Control In packet ++ */ ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ //fprintf(stderr, "Channel already enabled 2, HCCHAR = %08x\n", hcchar.d32); ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ MDELAY(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //if (hcchar.b.chen) { ++ // fprintf(stderr, "** Channel _still_ enabled 2, HCCHAR = %08x **\n", hcchar.d32); ++ //} ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 8; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 1; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "Waiting for RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ //fprintf(stderr, "Got RXSTSQLVL intr 1, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer */ ++ if (grxsts.b.bcnt > 0) { ++ int i; ++ int word_count = (grxsts.b.bcnt + 3) / 4; ++ ++ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); ++ ++ for (i = 0; i < word_count; i++) { ++ (void)dwc_read_reg32(data_fifo++); ++ } ++ } ++ ++ //fprintf(stderr, "Received %u bytes\n", (unsigned)grxsts.b.bcnt); ++ break; ++ ++ default: ++ //fprintf(stderr, "** Unexpected GRXSTS packet status 1 **\n"); ++ break; ++ } ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "Waiting for RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Wait for receive status queue interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.rxstsqlvl == 0); ++ ++ //fprintf(stderr, "Got RXSTSQLVL intr 2, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Read RXSTS */ ++ grxsts.d32 = dwc_read_reg32(&global_regs->grxstsp); ++ //fprintf(stderr, "GRXSTS: %08x\n", grxsts.d32); ++ ++ /* Clear RXSTSQLVL in GINTSTS */ ++ gintsts.d32 = 0; ++ gintsts.b.rxstsqlvl = 1; ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ break; ++ ++ default: ++ //fprintf(stderr, "** Unexpected GRXSTS packet status 2 **\n"); ++ break; ++ } ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "Waiting for HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ //fprintf(stderr, "Got HCINTR intr 2, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ // usleep(100000); ++ // mdelay(100); ++ MDELAY(1); ++ ++ /* ++ * Send handshake packet ++ */ ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Make sure channel is disabled */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ if (hcchar.b.chen) { ++ //fprintf(stderr, "Channel already enabled 3, HCCHAR = %08x\n", hcchar.d32); ++ hcchar.b.chdis = 1; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ //sleep(1); ++ MDELAY(1000); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //if (hcchar.b.chen) { ++ // fprintf(stderr, "** Channel _still_ enabled 3, HCCHAR = %08x **\n", hcchar.d32); ++ //} ++ } ++ ++ /* Set HCTSIZ */ ++ hctsiz.d32 = 0; ++ hctsiz.b.xfersize = 0; ++ hctsiz.b.pktcnt = 1; ++ hctsiz.b.pid = DWC_OTG_HC_PID_DATA1; ++ dwc_write_reg32(&hc_regs->hctsiz, hctsiz.d32); ++ ++ /* Set HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ hcchar.b.eptype = DWC_OTG_EP_TYPE_CONTROL; ++ hcchar.b.epdir = 0; ++ hcchar.b.epnum = 0; ++ hcchar.b.mps = 8; ++ hcchar.b.chen = 1; ++ dwc_write_reg32(&hc_regs->hcchar, hcchar.d32); ++ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "Waiting for HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Wait for host channel interrupt */ ++ do { ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ } while (gintsts.b.hcintr == 0); ++ ++ //fprintf(stderr, "Got HCINTR intr 3, GINTSTS = %08x\n", gintsts.d32); ++ ++ /* Disable HCINTs */ ++ dwc_write_reg32(&hc_regs->hcintmsk, 0x0000); ++ ++ /* Disable HAINTs */ ++ dwc_write_reg32(&hc_global_regs->haintmsk, 0x0000); ++ ++ /* Read HAINT */ ++ haint.d32 = dwc_read_reg32(&hc_global_regs->haint); ++ //fprintf(stderr, "HAINT: %08x\n", haint.d32); ++ ++ /* Read HCINT */ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ //fprintf(stderr, "HCINT: %08x\n", hcint.d32); ++ ++ /* Read HCCHAR */ ++ hcchar.d32 = dwc_read_reg32(&hc_regs->hcchar); ++ //fprintf(stderr, "HCCHAR: %08x\n", hcchar.d32); ++ ++ /* Clear HCINT */ ++ dwc_write_reg32(&hc_regs->hcint, hcint.d32); ++ ++ /* Clear HAINT */ ++ dwc_write_reg32(&hc_global_regs->haint, haint.d32); ++ ++ /* Clear GINTSTS */ ++ dwc_write_reg32(&global_regs->gintsts, gintsts.d32); ++ ++ /* Read GINTSTS */ ++ gintsts.d32 = dwc_read_reg32(&global_regs->gintsts); ++ //fprintf(stderr, "GINTSTS: %08x\n", gintsts.d32); ++} ++#endif /* DWC_HS_ELECT_TST */ ++ ++/** Handles hub class-specific requests.*/ ++int dwc_otg_hcd_hub_control(struct usb_hcd *_hcd, ++ u16 _typeReq, ++ u16 _wValue, ++ u16 _wIndex, ++ char *_buf, ++ u16 _wLength) ++{ ++ int retval = 0; ++ ++ dwc_otg_hcd_t *dwc_otg_hcd = hcd_to_dwc_otg_hcd (_hcd); ++ dwc_otg_core_if_t *core_if = hcd_to_dwc_otg_hcd (_hcd)->core_if; ++ struct usb_hub_descriptor *desc; ++ hprt0_data_t hprt0 = {.d32 = 0}; ++ ++ uint32_t port_status; ++ ++ switch (_typeReq) { ++ case ClearHubFeature: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearHubFeature 0x%x\n", _wValue); ++ switch (_wValue) { ++ case C_HUB_LOCAL_POWER: ++ case C_HUB_OVER_CURRENT: ++ /* Nothing required here */ ++ break; ++ default: ++ retval = -EINVAL; ++ DWC_ERROR ("DWC OTG HCD - " ++ "ClearHubFeature request %xh unknown\n", _wValue); ++ } ++ break; ++ case ClearPortFeature: ++ if (!_wIndex || _wIndex > 1) ++ goto error; ++ ++ switch (_wValue) { ++ case USB_PORT_FEAT_ENABLE: ++ DWC_DEBUGPL (DBG_ANY, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_ENABLE\n"); ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtena = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case USB_PORT_FEAT_SUSPEND: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_SUSPEND\n"); ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtres = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ /* Clear Resume bit */ ++ mdelay (100); ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case USB_PORT_FEAT_POWER: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtpwr = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case USB_PORT_FEAT_INDICATOR: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_INDICATOR\n"); ++ /* Port inidicator not supported */ ++ break; ++ case USB_PORT_FEAT_C_CONNECTION: ++ /* Clears drivers internal connect status change ++ * flag */ ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_CONNECTION\n"); ++ dwc_otg_hcd->flags.b.port_connect_status_change = 0; ++ break; ++ case USB_PORT_FEAT_C_RESET: ++ /* Clears the driver's internal Port Reset Change ++ * flag */ ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_RESET\n"); ++ dwc_otg_hcd->flags.b.port_reset_change = 0; ++ break; ++ case USB_PORT_FEAT_C_ENABLE: ++ /* Clears the driver's internal Port ++ * Enable/Disable Change flag */ ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_ENABLE\n"); ++ dwc_otg_hcd->flags.b.port_enable_change = 0; ++ break; ++ case USB_PORT_FEAT_C_SUSPEND: ++ /* Clears the driver's internal Port Suspend ++ * Change flag, which is set when resume signaling on ++ * the host port is complete */ ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_SUSPEND\n"); ++ dwc_otg_hcd->flags.b.port_suspend_change = 0; ++ break; ++ case USB_PORT_FEAT_C_OVER_CURRENT: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "ClearPortFeature USB_PORT_FEAT_C_OVER_CURRENT\n"); ++ dwc_otg_hcd->flags.b.port_over_current_change = 0; ++ break; ++ default: ++ retval = -EINVAL; ++ DWC_ERROR ("DWC OTG HCD - " ++ "ClearPortFeature request %xh " ++ "unknown or unsupported\n", _wValue); ++ } ++ break; ++ case GetHubDescriptor: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubDescriptor\n"); ++ desc = (struct usb_hub_descriptor *)_buf; ++ desc->bDescLength = 9; ++ desc->bDescriptorType = 0x29; ++ desc->bNbrPorts = 1; ++ desc->wHubCharacteristics = 0x08; ++ desc->bPwrOn2PwrGood = 1; ++ desc->bHubContrCurrent = 0; ++ desc->u.hs.DeviceRemovable[0] = 0; ++ desc->u.hs.DeviceRemovable[1] = 0xff; ++ break; ++ case GetHubStatus: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetHubStatus\n"); ++ memset (_buf, 0, 4); ++ break; ++ case GetPortStatus: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "GetPortStatus\n"); ++ ++ if (!_wIndex || _wIndex > 1) ++ goto error; ++ ++ port_status = 0; ++ ++ if (dwc_otg_hcd->flags.b.port_connect_status_change) ++ port_status |= (1 << USB_PORT_FEAT_C_CONNECTION); ++ ++ if (dwc_otg_hcd->flags.b.port_enable_change) ++ port_status |= (1 << USB_PORT_FEAT_C_ENABLE); ++ ++ if (dwc_otg_hcd->flags.b.port_suspend_change) ++ port_status |= (1 << USB_PORT_FEAT_C_SUSPEND); ++ ++ if (dwc_otg_hcd->flags.b.port_reset_change) ++ port_status |= (1 << USB_PORT_FEAT_C_RESET); ++ ++ if (dwc_otg_hcd->flags.b.port_over_current_change) { ++ DWC_ERROR("Device Not Supported\n"); ++ port_status |= (1 << USB_PORT_FEAT_C_OVER_CURRENT); ++ } ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ printk("DISCONNECTED PORT\n"); ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return 0's for the remainder of the port status ++ * since the port register can't be read if the core ++ * is in device mode. ++ */ ++#if 1 // winder. ++ *((u32 *) _buf) = cpu_to_le32(port_status); ++#else ++ *((__le32 *) _buf) = cpu_to_le32(port_status); ++#endif ++ break; ++ } ++ ++ hprt0.d32 = dwc_read_reg32(core_if->host_if->hprt0); ++ DWC_DEBUGPL(DBG_HCDV, " HPRT0: 0x%08x\n", hprt0.d32); ++ ++ if (hprt0.b.prtconnsts) ++ port_status |= (1 << USB_PORT_FEAT_CONNECTION); ++ ++ if (hprt0.b.prtena) ++ port_status |= (1 << USB_PORT_FEAT_ENABLE); ++ ++ if (hprt0.b.prtsusp) ++ port_status |= (1 << USB_PORT_FEAT_SUSPEND); ++ ++ if (hprt0.b.prtovrcurract) ++ port_status |= (1 << USB_PORT_FEAT_OVER_CURRENT); ++ ++ if (hprt0.b.prtrst) ++ port_status |= (1 << USB_PORT_FEAT_RESET); ++ ++ if (hprt0.b.prtpwr) ++ port_status |= (1 << USB_PORT_FEAT_POWER); ++ ++ if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) ++ port_status |= USB_PORT_STAT_HIGH_SPEED; ++ ++ else if (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) ++ port_status |= (1 << USB_PORT_FEAT_LOWSPEED); ++ ++ if (hprt0.b.prttstctl) ++ port_status |= (1 << USB_PORT_FEAT_TEST); ++ ++ /* USB_PORT_FEAT_INDICATOR unsupported always 0 */ ++#if 1 // winder. ++ *((u32 *) _buf) = cpu_to_le32(port_status); ++#else ++ *((__le32 *) _buf) = cpu_to_le32(port_status); ++#endif ++ ++ break; ++ case SetHubFeature: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetHubFeature\n"); ++ /* No HUB features supported */ ++ break; ++ case SetPortFeature: ++ if (_wValue != USB_PORT_FEAT_TEST && (!_wIndex || _wIndex > 1)) ++ goto error; ++ ++ if (!dwc_otg_hcd->flags.b.port_connect_status) { ++ /* ++ * The port is disconnected, which means the core is ++ * either in device mode or it soon will be. Just ++ * return without doing anything since the port ++ * register can't be written if the core is in device ++ * mode. ++ */ ++ break; ++ } ++ ++ switch (_wValue) { ++ case USB_PORT_FEAT_SUSPEND: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_SUSPEND\n"); ++ if (_hcd->self.otg_port == _wIndex ++ && _hcd->self.b_hnp_enable) { ++ gotgctl_data_t gotgctl = {.d32=0}; ++ gotgctl.b.hstsethnpen = 1; ++ dwc_modify_reg32(&core_if->core_global_regs-> ++ gotgctl, 0, gotgctl.d32); ++ core_if->op_state = A_SUSPEND; ++ } ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtsusp = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ //DWC_PRINT( "SUSPEND: HPRT0=%0x\n", hprt0.d32); ++ /* Suspend the Phy Clock */ ++ { ++ pcgcctl_data_t pcgcctl = {.d32=0}; ++ pcgcctl.b.stoppclk = 1; ++ dwc_write_reg32(core_if->pcgcctl, pcgcctl.d32); ++ } ++ ++ /* For HNP the bus must be suspended for at least 200ms.*/ ++ if (_hcd->self.b_hnp_enable) { ++ mdelay(200); ++ //DWC_PRINT( "SUSPEND: wait complete! (%d)\n", _hcd->state); ++ } ++ break; ++ case USB_PORT_FEAT_POWER: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_POWER\n"); ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtpwr = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ case USB_PORT_FEAT_RESET: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_RESET\n"); ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ /* TODO: Is this for OTG protocol?? ++ * We shoudl remove OTG totally for Danube system. ++ * But, in the future, maybe we need this. ++ */ ++#if 1 // winder ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++#else ++ /* When B-Host the Port reset bit is set in ++ * the Start HCD Callback function, so that ++ * the reset is started within 1ms of the HNP ++ * success interrupt. */ ++ if (!_hcd->self.is_b_host) { ++ hprt0.b.prtrst = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ } ++#endif ++ /* Clear reset bit in 10ms (FS/LS) or 50ms (HS) */ ++ MDELAY (60); ++ hprt0.b.prtrst = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ break; ++ ++#ifdef DWC_HS_ELECT_TST ++ case USB_PORT_FEAT_TEST: ++ { ++ uint32_t t; ++ gintmsk_data_t gintmsk; ++ ++ t = (_wIndex >> 8); /* MSB wIndex USB */ ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_TEST %d\n", t); ++ printk("USB_PORT_FEAT_TEST %d\n", t); ++ if (t < 6) { ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prttstctl = t; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ } else { ++ /* Setup global vars with reg addresses (quick and ++ * dirty hack, should be cleaned up) ++ */ ++ global_regs = core_if->core_global_regs; ++ hc_global_regs = core_if->host_if->host_global_regs; ++ hc_regs = (dwc_otg_hc_regs_t *)((char *)global_regs + 0x500); ++ data_fifo = (uint32_t *)((char *)global_regs + 0x1000); ++ ++ if (t == 6) { /* HS_HOST_PORT_SUSPEND_RESUME */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ mdelay(15000); ++ ++ /* Drive suspend on the root port */ ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtsusp = 1; ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* 15 second delay per the test spec */ ++ mdelay(15000); ++ ++ /* Drive resume on the root port */ ++ hprt0.d32 = dwc_otg_read_hprt0 (core_if); ++ hprt0.b.prtsusp = 0; ++ hprt0.b.prtres = 1; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ mdelay(100); ++ ++ /* Clear the resume bit */ ++ hprt0.b.prtres = 0; ++ dwc_write_reg32(core_if->host_if->hprt0, hprt0.d32); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 7) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR setup */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* 15 second delay per the test spec */ ++ mdelay(15000); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ mdelay(15000); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ } else if (t == 8) { /* SINGLE_STEP_GET_DEVICE_DESCRIPTOR execute */ ++ /* Save current interrupt mask */ ++ gintmsk.d32 = dwc_read_reg32(&global_regs->gintmsk); ++ ++ /* Disable all interrupts while we muck with ++ * the hardware directly ++ */ ++ dwc_write_reg32(&global_regs->gintmsk, 0); ++ ++ /* Send the Setup packet */ ++ do_setup(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ mdelay(15000); ++ ++ /* Send the In and Ack packets */ ++ do_in_ack(); ++ ++ /* 15 second delay so nothing else happens for awhile */ ++ mdelay(15000); ++ ++ /* Restore interrupts */ ++ dwc_write_reg32(&global_regs->gintmsk, gintmsk.d32); ++ } ++ } ++ break; ++ } ++#endif /* DWC_HS_ELECT_TST */ ++ ++ case USB_PORT_FEAT_INDICATOR: ++ DWC_DEBUGPL (DBG_HCD, "DWC OTG HCD HUB CONTROL - " ++ "SetPortFeature - USB_PORT_FEAT_INDICATOR\n"); ++ /* Not supported */ ++ break; ++ default: ++ retval = -EINVAL; ++ DWC_ERROR ("DWC OTG HCD - " ++ "SetPortFeature request %xh " ++ "unknown or unsupported\n", _wValue); ++ break; ++ } ++ break; ++ default: ++error: ++ retval = -EINVAL; ++ DWC_WARN ("DWC OTG HCD - " ++ "Unknown hub control request type or invalid typeReq: %xh wIndex: %xh wValue: %xh\n", ++ _typeReq, _wIndex, _wValue); ++ break; ++ } ++ ++ return retval; ++} ++ ++ ++/** ++ * Assigns transactions from a QTD to a free host channel and initializes the ++ * host channel to perform the transactions. The host channel is removed from ++ * the free list. ++ * ++ * @param _hcd The HCD state structure. ++ * @param _qh Transactions from the first QTD for this QH are selected and ++ * assigned to a free host channel. ++ */ ++static void assign_and_init_hc(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ dwc_hc_t *hc; ++ dwc_otg_qtd_t *qtd; ++ struct urb *urb; ++ ++ DWC_DEBUGPL(DBG_HCDV, "%s(%p,%p)\n", __func__, _hcd, _qh); ++ ++ hc = list_entry(_hcd->free_hc_list.next, dwc_hc_t, hc_list_entry); ++ ++ /* Remove the host channel from the free list. */ ++ list_del_init(&hc->hc_list_entry); ++ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); ++ urb = qtd->urb; ++ _qh->channel = hc; ++ _qh->qtd_in_process = qtd; ++ ++ /* ++ * Use usb_pipedevice to determine device address. This address is ++ * 0 before the SET_ADDRESS command and the correct address afterward. ++ */ ++ hc->dev_addr = usb_pipedevice(urb->pipe); ++ hc->ep_num = usb_pipeendpoint(urb->pipe); ++ ++ if (urb->dev->speed == USB_SPEED_LOW) { ++ hc->speed = DWC_OTG_EP_SPEED_LOW; ++ } else if (urb->dev->speed == USB_SPEED_FULL) { ++ hc->speed = DWC_OTG_EP_SPEED_FULL; ++ } else { ++ hc->speed = DWC_OTG_EP_SPEED_HIGH; ++ } ++ hc->max_packet = dwc_max_packet(_qh->maxp); ++ ++ hc->xfer_started = 0; ++ hc->halt_status = DWC_OTG_HC_XFER_NO_HALT_STATUS; ++ hc->error_state = (qtd->error_count > 0); ++ hc->halt_on_queue = 0; ++ hc->halt_pending = 0; ++ hc->requests = 0; ++ ++ /* ++ * The following values may be modified in the transfer type section ++ * below. The xfer_len value may be reduced when the transfer is ++ * started to accommodate the max widths of the XferSize and PktCnt ++ * fields in the HCTSIZn register. ++ */ ++ hc->do_ping = _qh->ping_state; ++ hc->ep_is_in = (usb_pipein(urb->pipe) != 0); ++ hc->data_pid_start = _qh->data_toggle; ++ hc->multi_count = 1; ++ ++ if (_hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma + urb->actual_length; ++ } else { ++ hc->xfer_buff = (uint8_t *)urb->transfer_buffer + urb->actual_length; ++ } ++ hc->xfer_len = urb->transfer_buffer_length - urb->actual_length; ++ hc->xfer_count = 0; ++ ++ /* ++ * Set the split attributes ++ */ ++ hc->do_split = 0; ++ if (_qh->do_split) { ++ hc->do_split = 1; ++ hc->xact_pos = qtd->isoc_split_pos; ++ hc->complete_split = qtd->complete_split; ++ hc->hub_addr = urb->dev->tt->hub->devnum; ++ hc->port_addr = urb->dev->ttport; ++ } ++ ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: ++ hc->ep_type = DWC_OTG_EP_TYPE_CONTROL; ++ switch (qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction\n"); ++ hc->do_ping = 0; ++ hc->ep_is_in = 0; ++ hc->data_pid_start = DWC_OTG_HC_PID_SETUP; ++ if (_hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *)(u32)urb->setup_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *)urb->setup_packet; ++ } ++ hc->xfer_len = 8; ++ break; ++ case DWC_OTG_CONTROL_DATA: ++ DWC_DEBUGPL(DBG_HCDV, " Control data transaction\n"); ++ hc->data_pid_start = qtd->data_toggle; ++ break; ++ case DWC_OTG_CONTROL_STATUS: ++ /* ++ * Direction is opposite of data direction or IN if no ++ * data. ++ */ ++ DWC_DEBUGPL(DBG_HCDV, " Control status transaction\n"); ++ if (urb->transfer_buffer_length == 0) { ++ hc->ep_is_in = 1; ++ } else { ++ hc->ep_is_in = (usb_pipein(urb->pipe) != USB_DIR_IN); ++ } ++ if (hc->ep_is_in) { ++ hc->do_ping = 0; ++ } ++ hc->data_pid_start = DWC_OTG_HC_PID_DATA1; ++ hc->xfer_len = 0; ++ if (_hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *)_hcd->status_buf_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *)_hcd->status_buf; ++ } ++ break; ++ } ++ break; ++ case PIPE_BULK: ++ hc->ep_type = DWC_OTG_EP_TYPE_BULK; ++ break; ++ case PIPE_INTERRUPT: ++ hc->ep_type = DWC_OTG_EP_TYPE_INTR; ++ break; ++ case PIPE_ISOCHRONOUS: ++ { ++ struct usb_iso_packet_descriptor *frame_desc; ++ frame_desc = &urb->iso_frame_desc[qtd->isoc_frame_index]; ++ hc->ep_type = DWC_OTG_EP_TYPE_ISOC; ++ if (_hcd->core_if->dma_enable) { ++ hc->xfer_buff = (uint8_t *)(u32)urb->transfer_dma; ++ } else { ++ hc->xfer_buff = (uint8_t *)urb->transfer_buffer; ++ } ++ hc->xfer_buff += frame_desc->offset + qtd->isoc_split_offset; ++ hc->xfer_len = frame_desc->length - qtd->isoc_split_offset; ++ ++ if (hc->xact_pos == DWC_HCSPLIT_XACTPOS_ALL) { ++ if (hc->xfer_len <= 188) { ++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ } ++ else { ++ hc->xact_pos = DWC_HCSPLIT_XACTPOS_BEGIN; ++ } ++ } ++ } ++ break; ++ } ++ ++ if (hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * This value may be modified when the transfer is started to ++ * reflect the actual transfer length. ++ */ ++ hc->multi_count = dwc_hb_mult(_qh->maxp); ++ } ++ ++ dwc_otg_hc_init(_hcd->core_if, hc); ++ hc->qh = _qh; ++} ++#define DEBUG_HOST_CHANNELS ++#ifdef DEBUG_HOST_CHANNELS ++static int last_sel_trans_num_per_scheduled = 0; ++module_param(last_sel_trans_num_per_scheduled, int, 0444); ++ ++static int last_sel_trans_num_nonper_scheduled = 0; ++module_param(last_sel_trans_num_nonper_scheduled, int, 0444); ++ ++static int last_sel_trans_num_avail_hc_at_start = 0; ++module_param(last_sel_trans_num_avail_hc_at_start, int, 0444); ++ ++static int last_sel_trans_num_avail_hc_at_end = 0; ++module_param(last_sel_trans_num_avail_hc_at_end, int, 0444); ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++/** ++ * This function selects transactions from the HCD transfer schedule and ++ * assigns them to available host channels. It is called from HCD interrupt ++ * handler functions. ++ * ++ * @param _hcd The HCD state structure. ++ * ++ * @return The types of new transactions that were assigned to host channels. ++ */ ++dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd) ++{ ++ struct list_head *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int num_channels; ++ unsigned long flags; ++ dwc_otg_transaction_type_e ret_val = DWC_OTG_TRANSACTION_NONE; ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, " Select Transactions\n"); ++#endif /* */ ++ ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled = 0; ++ last_sel_trans_num_nonper_scheduled = 0; ++ last_sel_trans_num_avail_hc_at_start = _hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ /* Process entries in the periodic ready list. */ ++ num_channels = _hcd->core_if->core_params->host_channels; ++ qh_ptr = _hcd->periodic_sched_ready.next; ++ while (qh_ptr != &_hcd->periodic_sched_ready ++ && !list_empty(&_hcd->free_hc_list)) { ++ ++ // Make sure we leave one channel for non periodic transactions. ++ local_irq_save(flags); ++ if (_hcd->available_host_channels <= 1) { ++ local_irq_restore(flags); ++ break; ++ } ++ _hcd->available_host_channels--; ++ local_irq_restore(flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_per_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ assign_and_init_hc(_hcd, qh); ++ ++ /* ++ * Move the QH from the periodic ready schedule to the ++ * periodic assigned schedule. ++ */ ++ qh_ptr = qh_ptr->next; ++ local_irq_save(flags); ++ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_assigned); ++ local_irq_restore(flags); ++ ret_val = DWC_OTG_TRANSACTION_PERIODIC; ++ } ++ ++ /* ++ * Process entries in the deferred portion of the non-periodic list. ++ * A NAK put them here and, at the right time, they need to be ++ * placed on the sched_inactive list. ++ */ ++ qh_ptr = _hcd->non_periodic_sched_deferred.next; ++ while (qh_ptr != &_hcd->non_periodic_sched_deferred) { ++ uint16_t frame_number = ++ dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); ++ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ qh_ptr = qh_ptr->next; ++ ++ if (dwc_frame_num_le(qh->sched_frame, frame_number)) { ++ // NAK did this ++ /* ++ * Move the QH from the non periodic deferred schedule to ++ * the non periodic inactive schedule. ++ */ ++ local_irq_save(flags); ++ list_move(&qh->qh_list_entry, ++ &_hcd->non_periodic_sched_inactive); ++ local_irq_restore(flags); ++ } ++ } ++ ++ /* ++ * Process entries in the inactive portion of the non-periodic ++ * schedule. Some free host channels may not be used if they are ++ * reserved for periodic transfers. ++ */ ++ qh_ptr = _hcd->non_periodic_sched_inactive.next; ++ num_channels = _hcd->core_if->core_params->host_channels; ++ while (qh_ptr != &_hcd->non_periodic_sched_inactive ++ && !list_empty(&_hcd->free_hc_list)) { ++ ++ local_irq_save(flags); ++ if (_hcd->available_host_channels < 1) { ++ local_irq_restore(flags); ++ break; ++ } ++ _hcd->available_host_channels--; ++ local_irq_restore(flags); ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_nonper_scheduled++; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ assign_and_init_hc(_hcd, qh); ++ ++ /* ++ * Move the QH from the non-periodic inactive schedule to the ++ * non-periodic active schedule. ++ */ ++ qh_ptr = qh_ptr->next; ++ local_irq_save(flags); ++ list_move(&qh->qh_list_entry, &_hcd->non_periodic_sched_active); ++ local_irq_restore(flags); ++ ++ if (ret_val == DWC_OTG_TRANSACTION_NONE) { ++ ret_val = DWC_OTG_TRANSACTION_NON_PERIODIC; ++ } else { ++ ret_val = DWC_OTG_TRANSACTION_ALL; ++ } ++ ++ } ++#ifdef DEBUG_HOST_CHANNELS ++ last_sel_trans_num_avail_hc_at_end = _hcd->available_host_channels; ++#endif /* DEBUG_HOST_CHANNELS */ ++ ++ return ret_val; ++} ++ ++/** ++ * Attempts to queue a single transaction request for a host channel ++ * associated with either a periodic or non-periodic transfer. This function ++ * assumes that there is space available in the appropriate request queue. For ++ * an OUT transfer or SETUP transaction in Slave mode, it checks whether space ++ * is available in the appropriate Tx FIFO. ++ * ++ * @param _hcd The HCD state structure. ++ * @param _hc Host channel descriptor associated with either a periodic or ++ * non-periodic transfer. ++ * @param _fifo_dwords_avail Number of DWORDs available in the periodic Tx ++ * FIFO for periodic transfers or the non-periodic Tx FIFO for non-periodic ++ * transfers. ++ * ++ * @return 1 if a request is queued and more requests may be needed to ++ * complete the transfer, 0 if no more requests are required for this ++ * transfer, -1 if there is insufficient space in the Tx FIFO. ++ */ ++static int queue_transaction(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ uint16_t _fifo_dwords_avail) ++{ ++ int retval; ++ ++ if (_hcd->core_if->dma_enable) { ++ if (!_hc->xfer_started) { ++ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); ++ _hc->qh->ping_state = 0; ++ } ++ retval = 0; ++ } else if (_hc->halt_pending) { ++ /* Don't queue a request if the channel has been halted. */ ++ retval = 0; ++ } else if (_hc->halt_on_queue) { ++ dwc_otg_hc_halt(_hcd->core_if, _hc, _hc->halt_status); ++ retval = 0; ++ } else if (_hc->do_ping) { ++ if (!_hc->xfer_started) { ++ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); ++ } ++ retval = 0; ++ } else if (!_hc->ep_is_in || ++ _hc->data_pid_start == DWC_OTG_HC_PID_SETUP) { ++ if ((_fifo_dwords_avail * 4) >= _hc->max_packet) { ++ if (!_hc->xfer_started) { ++ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); ++ retval = 1; ++ } else { ++ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); ++ } ++ } else { ++ retval = -1; ++ } ++ } else { ++ if (!_hc->xfer_started) { ++ dwc_otg_hc_start_transfer(_hcd->core_if, _hc); ++ retval = 1; ++ } else { ++ retval = dwc_otg_hc_continue_transfer(_hcd->core_if, _hc); ++ } ++ } ++ ++ return retval; ++} ++ ++/** ++ * Processes active non-periodic channels and queues transactions for these ++ * channels to the DWC_otg controller. After queueing transactions, the NP Tx ++ * FIFO Empty interrupt is enabled if there are more transactions to queue as ++ * NP Tx FIFO or request queue space becomes available. Otherwise, the NP Tx ++ * FIFO Empty interrupt is disabled. ++ */ ++static void process_non_periodic_channels(dwc_otg_hcd_t *_hcd) ++{ ++ gnptxsts_data_t tx_status; ++ struct list_head *orig_qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ int more_to_do = 0; ++ ++ dwc_otg_core_global_regs_t *global_regs = _hcd->core_if->core_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue non-periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ /* ++ * Keep track of the starting point. Skip over the start-of-list ++ * entry. ++ */ ++ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { ++ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; ++ } ++ orig_qh_ptr = _hcd->non_periodic_qh_ptr; ++ ++ /* ++ * Process once through the active list or until no more space is ++ * available in the request queue or the Tx FIFO. ++ */ ++ do { ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ if (!_hcd->core_if->dma_enable && tx_status.b.nptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = list_entry(_hcd->non_periodic_qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ status = queue_transaction(_hcd, qh->channel, tx_status.b.nptxfspcavail); ++ ++ if (status > 0) { ++ more_to_do = 1; ++ } else if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ ++ /* Advance to next QH, skipping start-of-list entry. */ ++ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; ++ if (_hcd->non_periodic_qh_ptr == &_hcd->non_periodic_sched_active) { ++ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; ++ } ++ ++ } while (_hcd->non_periodic_qh_ptr != orig_qh_ptr); ++ ++ if (!_hcd->core_if->dma_enable) { ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ intr_mask.b.nptxfempty = 1; ++ ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&global_regs->gnptxsts); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.nptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " NP Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.nptxfspcavail); ++#endif ++ if (more_to_do || no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the non-periodic ++ * Tx FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); ++ } ++ } ++} ++ ++/** ++ * Processes periodic channels for the next frame and queues transactions for ++ * these channels to the DWC_otg controller. After queueing transactions, the ++ * Periodic Tx FIFO Empty interrupt is enabled if there are more transactions ++ * to queue as Periodic Tx FIFO or request queue space becomes available. ++ * Otherwise, the Periodic Tx FIFO Empty interrupt is disabled. ++ */ ++static void process_periodic_channels(dwc_otg_hcd_t *_hcd) ++{ ++ hptxsts_data_t tx_status; ++ struct list_head *qh_ptr; ++ dwc_otg_qh_t *qh; ++ int status; ++ int no_queue_space = 0; ++ int no_fifo_space = 0; ++ ++ dwc_otg_host_global_regs_t *host_regs; ++ host_regs = _hcd->core_if->host_if->host_global_regs; ++ ++ DWC_DEBUGPL(DBG_HCDV, "Queue periodic transactions\n"); ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (before queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (before queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ ++ qh_ptr = _hcd->periodic_sched_assigned.next; ++ while (qh_ptr != &_hcd->periodic_sched_assigned) { ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ if (tx_status.b.ptxqspcavail == 0) { ++ no_queue_space = 1; ++ break; ++ } ++ ++ qh = list_entry(qh_ptr, dwc_otg_qh_t, qh_list_entry); ++ ++ /* ++ * Set a flag if we're queuing high-bandwidth in slave mode. ++ * The flag prevents any halts to get into the request queue in ++ * the middle of multiple high-bandwidth packets getting queued. ++ */ ++ if ((!_hcd->core_if->dma_enable) && ++ (qh->channel->multi_count > 1)) ++ { ++ _hcd->core_if->queuing_high_bandwidth = 1; ++ } ++ ++ status = queue_transaction(_hcd, qh->channel, tx_status.b.ptxfspcavail); ++ if (status < 0) { ++ no_fifo_space = 1; ++ break; ++ } ++ ++ /* ++ * In Slave mode, stay on the current transfer until there is ++ * nothing more to do or the high-bandwidth request count is ++ * reached. In DMA mode, only need to queue one request. The ++ * controller automatically handles multiple packets for ++ * high-bandwidth transfers. ++ */ ++ if (_hcd->core_if->dma_enable || ++ (status == 0 || ++ qh->channel->requests == qh->channel->multi_count)) { ++ qh_ptr = qh_ptr->next; ++ /* ++ * Move the QH from the periodic assigned schedule to ++ * the periodic queued schedule. ++ */ ++ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_queued); ++ ++ /* done queuing high bandwidth */ ++ _hcd->core_if->queuing_high_bandwidth = 0; ++ } ++ } ++ ++ if (!_hcd->core_if->dma_enable) { ++ dwc_otg_core_global_regs_t *global_regs; ++ gintmsk_data_t intr_mask = {.d32 = 0}; ++ ++ global_regs = _hcd->core_if->core_global_regs; ++ intr_mask.b.ptxfempty = 1; ++#ifdef DEBUG ++ tx_status.d32 = dwc_read_reg32(&host_regs->hptxsts); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx Req Queue Space Avail (after queue): %d\n", ++ tx_status.b.ptxqspcavail); ++ DWC_DEBUGPL(DBG_HCDV, " P Tx FIFO Space Avail (after queue): %d\n", ++ tx_status.b.ptxfspcavail); ++#endif ++ if (!(list_empty(&_hcd->periodic_sched_assigned)) || ++ no_queue_space || no_fifo_space) { ++ /* ++ * May need to queue more transactions as the request ++ * queue or Tx FIFO empties. Enable the periodic Tx ++ * FIFO empty interrupt. (Always use the half-empty ++ * level to ensure that new requests are loaded as ++ * soon as possible.) ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, 0, intr_mask.d32); ++ } else { ++ /* ++ * Disable the Tx FIFO empty interrupt since there are ++ * no more transactions that need to be queued right ++ * now. This function is called from interrupt ++ * handlers to queue more transactions as transfer ++ * states change. ++ */ ++ dwc_modify_reg32(&global_regs->gintmsk, intr_mask.d32, 0); ++ } ++ } ++} ++ ++/** ++ * This function processes the currently active host channels and queues ++ * transactions for these channels to the DWC_otg controller. It is called ++ * from HCD interrupt handler functions. ++ * ++ * @param _hcd The HCD state structure. ++ * @param _tr_type The type(s) of transactions to queue (non-periodic, ++ * periodic, or both). ++ */ ++void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, ++ dwc_otg_transaction_type_e _tr_type) ++{ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "Queue Transactions\n"); ++#endif ++ /* Process host channels associated with periodic transfers. */ ++ if ((_tr_type == DWC_OTG_TRANSACTION_PERIODIC || ++ _tr_type == DWC_OTG_TRANSACTION_ALL) && ++ !list_empty(&_hcd->periodic_sched_assigned)) { ++ ++ process_periodic_channels(_hcd); ++ } ++ ++ /* Process host channels associated with non-periodic transfers. */ ++ if ((_tr_type == DWC_OTG_TRANSACTION_NON_PERIODIC || ++ _tr_type == DWC_OTG_TRANSACTION_ALL)) { ++ if (!list_empty(&_hcd->non_periodic_sched_active)) { ++ process_non_periodic_channels(_hcd); ++ } else { ++ /* ++ * Ensure NP Tx FIFO empty interrupt is disabled when ++ * there are no non-periodic transfers to process. ++ */ ++ gintmsk_data_t gintmsk = {.d32 = 0}; ++ gintmsk.b.nptxfempty = 1; ++ dwc_modify_reg32(&_hcd->core_if->core_global_regs->gintmsk, gintmsk.d32, 0); ++ } ++ } ++} ++ ++/** ++ * Sets the final status of an URB and returns it to the device driver. Any ++ * required cleanup of the URB is performed. ++ */ ++void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t * _hcd, struct urb *_urb, ++ int _status) ++ __releases(_hcd->lock) ++__acquires(_hcd->lock) ++{ ++#ifdef DEBUG ++ if (CHK_DEBUG_LEVEL(DBG_HCDV | DBG_HCD_URB)) { ++ DWC_PRINT("%s: urb %p, device %d, ep %d %s, status=%d\n", ++ __func__, _urb, usb_pipedevice(_urb->pipe), ++ usb_pipeendpoint(_urb->pipe), ++ usb_pipein(_urb->pipe) ? "IN" : "OUT", _status); ++ if (usb_pipetype(_urb->pipe) == PIPE_ISOCHRONOUS) { ++ int i; ++ for (i = 0; i < _urb->number_of_packets; i++) { ++ DWC_PRINT(" ISO Desc %d status: %d\n", ++ i, _urb->iso_frame_desc[i].status); ++ } ++ } ++ } ++#endif ++ ++ _urb->status = _status; ++ _urb->hcpriv = NULL; ++ usb_hcd_unlink_urb_from_ep(dwc_otg_hcd_to_hcd(_hcd), _urb); ++ spin_unlock(&_hcd->lock); ++ usb_hcd_giveback_urb(dwc_otg_hcd_to_hcd(_hcd), _urb, _status); ++ spin_lock(&_hcd->lock); ++} ++ ++/* ++ * Returns the Queue Head for an URB. ++ */ ++dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb) ++{ ++ struct usb_host_endpoint *ep = dwc_urb_to_endpoint(_urb); ++ return (dwc_otg_qh_t *)ep->hcpriv; ++} ++ ++#ifdef DEBUG ++void dwc_print_setup_data (uint8_t *setup) ++{ ++ int i; ++ if (CHK_DEBUG_LEVEL(DBG_HCD)){ ++ DWC_PRINT("Setup Data = MSB "); ++ for (i=7; i>=0; i--) DWC_PRINT ("%02x ", setup[i]); ++ DWC_PRINT("\n"); ++ DWC_PRINT(" bmRequestType Tranfer = %s\n", (setup[0]&0x80) ? "Device-to-Host" : "Host-to-Device"); ++ DWC_PRINT(" bmRequestType Type = "); ++ switch ((setup[0]&0x60) >> 5) { ++ case 0: DWC_PRINT("Standard\n"); break; ++ case 1: DWC_PRINT("Class\n"); break; ++ case 2: DWC_PRINT("Vendor\n"); break; ++ case 3: DWC_PRINT("Reserved\n"); break; ++ } ++ DWC_PRINT(" bmRequestType Recipient = "); ++ switch (setup[0]&0x1f) { ++ case 0: DWC_PRINT("Device\n"); break; ++ case 1: DWC_PRINT("Interface\n"); break; ++ case 2: DWC_PRINT("Endpoint\n"); break; ++ case 3: DWC_PRINT("Other\n"); break; ++ default: DWC_PRINT("Reserved\n"); break; ++ } ++ DWC_PRINT(" bRequest = 0x%0x\n", setup[1]); ++ DWC_PRINT(" wValue = 0x%0x\n", *((uint16_t *)&setup[2])); ++ DWC_PRINT(" wIndex = 0x%0x\n", *((uint16_t *)&setup[4])); ++ DWC_PRINT(" wLength = 0x%0x\n\n", *((uint16_t *)&setup[6])); ++ } ++} ++#endif ++ ++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd) { ++#ifdef DEBUG ++#if 0 ++ DWC_PRINT("Frame remaining at SOF:\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->frrem_samples, _hcd->frrem_accum, ++ (_hcd->frrem_samples > 0) ? ++ _hcd->frrem_accum/_hcd->frrem_samples : 0); ++ ++ DWC_PRINT("\n"); ++ DWC_PRINT("Frame remaining at start_transfer (uframe 7):\n"); ++ DWC_PRINT(" samples %u, accum %u, avg %u\n", ++ _hcd->core_if->hfnum_7_samples, _hcd->core_if->hfnum_7_frrem_accum, ++ (_hcd->core_if->hfnum_7_samples > 0) ? ++ _hcd->core_if->hfnum_7_frrem_accum/_hcd->core_if->hfnum_7_samples : 0); ++ DWC_PRINT("Frame remaining at start_transfer (uframe 0):\n"); ++ DWC_PRINT(" samples %u, accum %u, avg %u\n", ++ _hcd->core_if->hfnum_0_samples, _hcd->core_if->hfnum_0_frrem_accum, ++ (_hcd->core_if->hfnum_0_samples > 0) ? ++ _hcd->core_if->hfnum_0_frrem_accum/_hcd->core_if->hfnum_0_samples : 0); ++ DWC_PRINT("Frame remaining at start_transfer (uframe 1-6):\n"); ++ DWC_PRINT(" samples %u, accum %u, avg %u\n", ++ _hcd->core_if->hfnum_other_samples, _hcd->core_if->hfnum_other_frrem_accum, ++ (_hcd->core_if->hfnum_other_samples > 0) ? ++ _hcd->core_if->hfnum_other_frrem_accum/_hcd->core_if->hfnum_other_samples : 0); ++ ++ DWC_PRINT("\n"); ++ DWC_PRINT("Frame remaining at sample point A (uframe 7):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_7_samples_a, _hcd->hfnum_7_frrem_accum_a, ++ (_hcd->hfnum_7_samples_a > 0) ? ++ _hcd->hfnum_7_frrem_accum_a/_hcd->hfnum_7_samples_a : 0); ++ DWC_PRINT("Frame remaining at sample point A (uframe 0):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_0_samples_a, _hcd->hfnum_0_frrem_accum_a, ++ (_hcd->hfnum_0_samples_a > 0) ? ++ _hcd->hfnum_0_frrem_accum_a/_hcd->hfnum_0_samples_a : 0); ++ DWC_PRINT("Frame remaining at sample point A (uframe 1-6):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_other_samples_a, _hcd->hfnum_other_frrem_accum_a, ++ (_hcd->hfnum_other_samples_a > 0) ? ++ _hcd->hfnum_other_frrem_accum_a/_hcd->hfnum_other_samples_a : 0); ++ ++ DWC_PRINT("\n"); ++ DWC_PRINT("Frame remaining at sample point B (uframe 7):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_7_samples_b, _hcd->hfnum_7_frrem_accum_b, ++ (_hcd->hfnum_7_samples_b > 0) ? ++ _hcd->hfnum_7_frrem_accum_b/_hcd->hfnum_7_samples_b : 0); ++ DWC_PRINT("Frame remaining at sample point B (uframe 0):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_0_samples_b, _hcd->hfnum_0_frrem_accum_b, ++ (_hcd->hfnum_0_samples_b > 0) ? ++ _hcd->hfnum_0_frrem_accum_b/_hcd->hfnum_0_samples_b : 0); ++ DWC_PRINT("Frame remaining at sample point B (uframe 1-6):\n"); ++ DWC_PRINT(" samples %u, accum %llu, avg %llu\n", ++ _hcd->hfnum_other_samples_b, _hcd->hfnum_other_frrem_accum_b, ++ (_hcd->hfnum_other_samples_b > 0) ? ++ _hcd->hfnum_other_frrem_accum_b/_hcd->hfnum_other_samples_b : 0); ++#endif ++#endif ++} ++ ++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd) ++{ ++#ifdef DEBUG ++ int num_channels; ++ int i; ++ gnptxsts_data_t np_tx_status; ++ hptxsts_data_t p_tx_status; ++ ++ num_channels = _hcd->core_if->core_params->host_channels; ++ DWC_PRINT("\n"); ++ DWC_PRINT("************************************************************\n"); ++ DWC_PRINT("HCD State:\n"); ++ DWC_PRINT(" Num channels: %d\n", num_channels); ++ for (i = 0; i < num_channels; i++) { ++ dwc_hc_t *hc = _hcd->hc_ptr_array[i]; ++ DWC_PRINT(" Channel %d:\n", i); ++ DWC_PRINT(" dev_addr: %d, ep_num: %d, ep_is_in: %d\n", ++ hc->dev_addr, hc->ep_num, hc->ep_is_in); ++ DWC_PRINT(" speed: %d\n", hc->speed); ++ DWC_PRINT(" ep_type: %d\n", hc->ep_type); ++ DWC_PRINT(" max_packet: %d\n", hc->max_packet); ++ DWC_PRINT(" data_pid_start: %d\n", hc->data_pid_start); ++ DWC_PRINT(" multi_count: %d\n", hc->multi_count); ++ DWC_PRINT(" xfer_started: %d\n", hc->xfer_started); ++ DWC_PRINT(" xfer_buff: %p\n", hc->xfer_buff); ++ DWC_PRINT(" xfer_len: %d\n", hc->xfer_len); ++ DWC_PRINT(" xfer_count: %d\n", hc->xfer_count); ++ DWC_PRINT(" halt_on_queue: %d\n", hc->halt_on_queue); ++ DWC_PRINT(" halt_pending: %d\n", hc->halt_pending); ++ DWC_PRINT(" halt_status: %d\n", hc->halt_status); ++ DWC_PRINT(" do_split: %d\n", hc->do_split); ++ DWC_PRINT(" complete_split: %d\n", hc->complete_split); ++ DWC_PRINT(" hub_addr: %d\n", hc->hub_addr); ++ DWC_PRINT(" port_addr: %d\n", hc->port_addr); ++ DWC_PRINT(" xact_pos: %d\n", hc->xact_pos); ++ DWC_PRINT(" requests: %d\n", hc->requests); ++ DWC_PRINT(" qh: %p\n", hc->qh); ++ if (hc->xfer_started) { ++ hfnum_data_t hfnum; ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); ++ hcchar.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcchar); ++ hctsiz.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hctsiz); ++ hcint.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&_hcd->core_if->host_if->hc_regs[i]->hcintmsk); ++ DWC_PRINT(" hfnum: 0x%08x\n", hfnum.d32); ++ DWC_PRINT(" hcchar: 0x%08x\n", hcchar.d32); ++ DWC_PRINT(" hctsiz: 0x%08x\n", hctsiz.d32); ++ DWC_PRINT(" hcint: 0x%08x\n", hcint.d32); ++ DWC_PRINT(" hcintmsk: 0x%08x\n", hcintmsk.d32); ++ } ++ if (hc->xfer_started && (hc->qh != NULL) && (hc->qh->qtd_in_process != NULL)) { ++ dwc_otg_qtd_t *qtd; ++ struct urb *urb; ++ qtd = hc->qh->qtd_in_process; ++ urb = qtd->urb; ++ DWC_PRINT(" URB Info:\n"); ++ DWC_PRINT(" qtd: %p, urb: %p\n", qtd, urb); ++ if (urb != NULL) { ++ DWC_PRINT(" Dev: %d, EP: %d %s\n", ++ usb_pipedevice(urb->pipe), usb_pipeendpoint(urb->pipe), ++ usb_pipein(urb->pipe) ? "IN" : "OUT"); ++ DWC_PRINT(" Max packet size: %d\n", ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); ++ DWC_PRINT(" transfer_buffer: %p\n", urb->transfer_buffer); ++ DWC_PRINT(" transfer_dma: %p\n", (void *)urb->transfer_dma); ++ DWC_PRINT(" transfer_buffer_length: %d\n", urb->transfer_buffer_length); ++ DWC_PRINT(" actual_length: %d\n", urb->actual_length); ++ } ++ } ++ } ++ //DWC_PRINT(" non_periodic_channels: %d\n", _hcd->non_periodic_channels); ++ //DWC_PRINT(" periodic_channels: %d\n", _hcd->periodic_channels); ++ DWC_PRINT(" available_channels: %d\n", _hcd->available_host_channels); ++ DWC_PRINT(" periodic_usecs: %d\n", _hcd->periodic_usecs); ++ np_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->core_global_regs->gnptxsts); ++ DWC_PRINT(" NP Tx Req Queue Space Avail: %d\n", np_tx_status.b.nptxqspcavail); ++ DWC_PRINT(" NP Tx FIFO Space Avail: %d\n", np_tx_status.b.nptxfspcavail); ++ p_tx_status.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hptxsts); ++ DWC_PRINT(" P Tx Req Queue Space Avail: %d\n", p_tx_status.b.ptxqspcavail); ++ DWC_PRINT(" P Tx FIFO Space Avail: %d\n", p_tx_status.b.ptxfspcavail); ++ dwc_otg_hcd_dump_frrem(_hcd); ++ dwc_otg_dump_global_registers(_hcd->core_if); ++ dwc_otg_dump_host_registers(_hcd->core_if); ++ DWC_PRINT("************************************************************\n"); ++ DWC_PRINT("\n"); ++#endif ++} ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_hcd.h +@@ -0,0 +1,676 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 537387 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++#if !defined(__DWC_HCD_H__) ++#define __DWC_HCD_H__ ++ ++#include <linux/list.h> ++#include <linux/usb.h> ++#include <linux/usb/hcd.h> ++ ++struct lm_device; ++struct dwc_otg_device; ++ ++#include "dwc_otg_cil.h" ++//#include "dwc_otg_ifx.h" // winder ++ ++ ++/** ++ * @file ++ * ++ * This file contains the structures, constants, and interfaces for ++ * the Host Contoller Driver (HCD). ++ * ++ * The Host Controller Driver (HCD) is responsible for translating requests ++ * from the USB Driver into the appropriate actions on the DWC_otg controller. ++ * It isolates the USBD from the specifics of the controller by providing an ++ * API to the USBD. ++ */ ++ ++/** ++ * Phases for control transfers. ++ */ ++typedef enum dwc_otg_control_phase { ++ DWC_OTG_CONTROL_SETUP, ++ DWC_OTG_CONTROL_DATA, ++ DWC_OTG_CONTROL_STATUS ++} dwc_otg_control_phase_e; ++ ++/** Transaction types. */ ++typedef enum dwc_otg_transaction_type { ++ DWC_OTG_TRANSACTION_NONE, ++ DWC_OTG_TRANSACTION_PERIODIC, ++ DWC_OTG_TRANSACTION_NON_PERIODIC, ++ DWC_OTG_TRANSACTION_ALL ++} dwc_otg_transaction_type_e; ++ ++/** ++ * A Queue Transfer Descriptor (QTD) holds the state of a bulk, control, ++ * interrupt, or isochronous transfer. A single QTD is created for each URB ++ * (of one of these types) submitted to the HCD. The transfer associated with ++ * a QTD may require one or multiple transactions. ++ * ++ * A QTD is linked to a Queue Head, which is entered in either the ++ * non-periodic or periodic schedule for execution. When a QTD is chosen for ++ * execution, some or all of its transactions may be executed. After ++ * execution, the state of the QTD is updated. The QTD may be retired if all ++ * its transactions are complete or if an error occurred. Otherwise, it ++ * remains in the schedule so more transactions can be executed later. ++ */ ++struct dwc_otg_qh; ++typedef struct dwc_otg_qtd { ++ /** ++ * Determines the PID of the next data packet for the data phase of ++ * control transfers. Ignored for other transfer types.<br> ++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Current phase for control transfers (Setup, Data, or Status). */ ++ dwc_otg_control_phase_e control_phase; ++ ++ /** Keep track of the current split type ++ * for FS/LS endpoints on a HS Hub */ ++ uint8_t complete_split; ++ ++ /** How many bytes transferred during SSPLIT OUT */ ++ uint32_t ssplit_out_xfer_count; ++ ++ /** ++ * Holds the number of bus errors that have occurred for a transaction ++ * within this transfer. ++ */ ++ uint8_t error_count; ++ ++ /** ++ * Index of the next frame descriptor for an isochronous transfer. A ++ * frame descriptor describes the buffer position and length of the ++ * data to be transferred in the next scheduled (micro)frame of an ++ * isochronous transfer. It also holds status for that transaction. ++ * The frame index starts at 0. ++ */ ++ int isoc_frame_index; ++ ++ /** Position of the ISOC split on full/low speed */ ++ uint8_t isoc_split_pos; ++ ++ /** Position of the ISOC split in the buffer for the current frame */ ++ uint16_t isoc_split_offset; ++ ++ /** URB for this transfer */ ++ struct urb *urb; ++ ++ /** This list of QTDs */ ++ struct list_head qtd_list_entry; ++ ++ /* Field to track the qh pointer */ ++ struct dwc_otg_qh *qtd_qh_ptr; ++} dwc_otg_qtd_t; ++ ++/** ++ * A Queue Head (QH) holds the static characteristics of an endpoint and ++ * maintains a list of transfers (QTDs) for that endpoint. A QH structure may ++ * be entered in either the non-periodic or periodic schedule. ++ */ ++typedef struct dwc_otg_qh { ++ /** ++ * Endpoint type. ++ * One of the following values: ++ * - USB_ENDPOINT_XFER_CONTROL ++ * - USB_ENDPOINT_XFER_ISOC ++ * - USB_ENDPOINT_XFER_BULK ++ * - USB_ENDPOINT_XFER_INT ++ */ ++ uint8_t ep_type; ++ uint8_t ep_is_in; ++ ++ /** wMaxPacketSize Field of Endpoint Descriptor. */ ++ uint16_t maxp; ++ ++ /** ++ * Determines the PID of the next data packet for non-control ++ * transfers. Ignored for control transfers.<br> ++ * One of the following values: ++ * - DWC_OTG_HC_PID_DATA0 ++ * - DWC_OTG_HC_PID_DATA1 ++ */ ++ uint8_t data_toggle; ++ ++ /** Ping state if 1. */ ++ uint8_t ping_state; ++ ++ /** ++ * List of QTDs for this QH. ++ */ ++ struct list_head qtd_list; ++ ++ /** Host channel currently processing transfers for this QH. */ ++ dwc_hc_t *channel; ++ ++ /** QTD currently assigned to a host channel for this QH. */ ++ dwc_otg_qtd_t *qtd_in_process; ++ ++ /** Full/low speed endpoint on high-speed hub requires split. */ ++ uint8_t do_split; ++ ++ /** @name Periodic schedule information */ ++ /** @{ */ ++ ++ /** Bandwidth in microseconds per (micro)frame. */ ++ uint8_t usecs; ++ ++ /** Interval between transfers in (micro)frames. */ ++ uint16_t interval; ++ ++ /** ++ * (micro)frame to initialize a periodic transfer. The transfer ++ * executes in the following (micro)frame. ++ */ ++ uint16_t sched_frame; ++ ++ /** (micro)frame at which last start split was initialized. */ ++ uint16_t start_split_frame; ++ ++ /** @} */ ++ ++ uint16_t speed; ++ uint16_t frame_usecs[8]; ++ /** Entry for QH in either the periodic or non-periodic schedule. */ ++ struct list_head qh_list_entry; ++} dwc_otg_qh_t; ++ ++/** ++ * This structure holds the state of the HCD, including the non-periodic and ++ * periodic schedules. ++ */ ++typedef struct dwc_otg_hcd { ++ spinlock_t lock; ++ ++ /** DWC OTG Core Interface Layer */ ++ dwc_otg_core_if_t *core_if; ++ ++ /** Internal DWC HCD Flags */ ++ volatile union dwc_otg_hcd_internal_flags { ++ uint32_t d32; ++ struct { ++ unsigned port_connect_status_change : 1; ++ unsigned port_connect_status : 1; ++ unsigned port_reset_change : 1; ++ unsigned port_enable_change : 1; ++ unsigned port_suspend_change : 1; ++ unsigned port_over_current_change : 1; ++ unsigned reserved : 27; ++ } b; ++ } flags; ++ ++ /** ++ * Inactive items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are not ++ * currently assigned to a host channel. ++ */ ++ struct list_head non_periodic_sched_inactive; ++ ++ /** ++ * Deferred items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are not ++ * currently assigned to a host channel. ++ * When we get an NAK, the QH goes here. ++ */ ++ struct list_head non_periodic_sched_deferred; ++ ++ /** ++ * Active items in the non-periodic schedule. This is a list of ++ * Queue Heads. Transfers associated with these Queue Heads are ++ * currently assigned to a host channel. ++ */ ++ struct list_head non_periodic_sched_active; ++ ++ /** ++ * Pointer to the next Queue Head to process in the active ++ * non-periodic schedule. ++ */ ++ struct list_head *non_periodic_qh_ptr; ++ ++ /** ++ * Inactive items in the periodic schedule. This is a list of QHs for ++ * periodic transfers that are _not_ scheduled for the next frame. ++ * Each QH in the list has an interval counter that determines when it ++ * needs to be scheduled for execution. This scheduling mechanism ++ * allows only a simple calculation for periodic bandwidth used (i.e. ++ * must assume that all periodic transfers may need to execute in the ++ * same frame). However, it greatly simplifies scheduling and should ++ * be sufficient for the vast majority of OTG hosts, which need to ++ * connect to a small number of peripherals at one time. ++ * ++ * Items move from this list to periodic_sched_ready when the QH ++ * interval counter is 0 at SOF. ++ */ ++ struct list_head periodic_sched_inactive; ++ ++ /** ++ * List of periodic QHs that are ready for execution in the next ++ * frame, but have not yet been assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_assigned as host ++ * channels become available during the current frame. ++ */ ++ struct list_head periodic_sched_ready; ++ ++ /** ++ * List of periodic QHs to be executed in the next frame that are ++ * assigned to host channels. ++ * ++ * Items move from this list to periodic_sched_queued as the ++ * transactions for the QH are queued to the DWC_otg controller. ++ */ ++ struct list_head periodic_sched_assigned; ++ ++ /** ++ * List of periodic QHs that have been queued for execution. ++ * ++ * Items move from this list to either periodic_sched_inactive or ++ * periodic_sched_ready when the channel associated with the transfer ++ * is released. If the interval for the QH is 1, the item moves to ++ * periodic_sched_ready because it must be rescheduled for the next ++ * frame. Otherwise, the item moves to periodic_sched_inactive. ++ */ ++ struct list_head periodic_sched_queued; ++ ++ /** ++ * Total bandwidth claimed so far for periodic transfers. This value ++ * is in microseconds per (micro)frame. The assumption is that all ++ * periodic transfers may occur in the same (micro)frame. ++ */ ++ uint16_t periodic_usecs; ++ ++ /** ++ * Total bandwidth claimed so far for all periodic transfers ++ * in a frame. ++ * This will include a mixture of HS and FS transfers. ++ * Units are microseconds per (micro)frame. ++ * We have a budget per frame and have to schedule ++ * transactions accordingly. ++ * Watch out for the fact that things are actually scheduled for the ++ * "next frame". ++ */ ++ uint16_t frame_usecs[8]; ++ ++ /** ++ * Frame number read from the core at SOF. The value ranges from 0 to ++ * DWC_HFNUM_MAX_FRNUM. ++ */ ++ uint16_t frame_number; ++ ++ /** ++ * Free host channels in the controller. This is a list of ++ * dwc_hc_t items. ++ */ ++ struct list_head free_hc_list; ++ ++ /** ++ * Number of available host channels. ++ */ ++ int available_host_channels; ++ ++ /** ++ * Array of pointers to the host channel descriptors. Allows accessing ++ * a host channel descriptor given the host channel number. This is ++ * useful in interrupt handlers. ++ */ ++ dwc_hc_t *hc_ptr_array[MAX_EPS_CHANNELS]; ++ ++ /** ++ * Buffer to use for any data received during the status phase of a ++ * control transfer. Normally no data is transferred during the status ++ * phase. This buffer is used as a bit bucket. ++ */ ++ uint8_t *status_buf; ++ ++ /** ++ * DMA address for status_buf. ++ */ ++ dma_addr_t status_buf_dma; ++#define DWC_OTG_HCD_STATUS_BUF_SIZE 64 ++ ++ /** ++ * Structure to allow starting the HCD in a non-interrupt context ++ * during an OTG role change. ++ */ ++ struct work_struct start_work; ++ struct usb_hcd *_p; ++ ++ /** ++ * Connection timer. An OTG host must display a message if the device ++ * does not connect. Started when the VBus power is turned on via ++ * sysfs attribute "buspower". ++ */ ++ struct timer_list conn_timer; ++ ++ /* Tasket to do a reset */ ++ struct tasklet_struct *reset_tasklet; ++ ++#ifdef DEBUG ++ uint32_t frrem_samples; ++ uint64_t frrem_accum; ++ ++ uint32_t hfnum_7_samples_a; ++ uint64_t hfnum_7_frrem_accum_a; ++ uint32_t hfnum_0_samples_a; ++ uint64_t hfnum_0_frrem_accum_a; ++ uint32_t hfnum_other_samples_a; ++ uint64_t hfnum_other_frrem_accum_a; ++ ++ uint32_t hfnum_7_samples_b; ++ uint64_t hfnum_7_frrem_accum_b; ++ uint32_t hfnum_0_samples_b; ++ uint64_t hfnum_0_frrem_accum_b; ++ uint32_t hfnum_other_samples_b; ++ uint64_t hfnum_other_frrem_accum_b; ++#endif ++ ++} dwc_otg_hcd_t; ++ ++/** Gets the dwc_otg_hcd from a struct usb_hcd */ ++static inline dwc_otg_hcd_t *hcd_to_dwc_otg_hcd(struct usb_hcd *hcd) ++{ ++ return (dwc_otg_hcd_t *)(hcd->hcd_priv); ++} ++ ++/** Gets the struct usb_hcd that contains a dwc_otg_hcd_t. */ ++static inline struct usb_hcd *dwc_otg_hcd_to_hcd(dwc_otg_hcd_t *dwc_otg_hcd) ++{ ++ return container_of((void *)dwc_otg_hcd, struct usb_hcd, hcd_priv); ++} ++ ++/** @name HCD Create/Destroy Functions */ ++/** @{ */ ++extern int __devinit dwc_otg_hcd_init(struct device *_dev, dwc_otg_device_t * dwc_otg_device); ++extern void dwc_otg_hcd_remove(struct device *_dev); ++/** @} */ ++ ++/** @name Linux HC Driver API Functions */ ++/** @{ */ ++ ++extern int dwc_otg_hcd_start(struct usb_hcd *hcd); ++extern void dwc_otg_hcd_stop(struct usb_hcd *hcd); ++extern int dwc_otg_hcd_get_frame_number(struct usb_hcd *hcd); ++extern void dwc_otg_hcd_free(struct usb_hcd *hcd); ++ ++extern int dwc_otg_hcd_urb_enqueue(struct usb_hcd *hcd, ++ struct urb *urb, ++ gfp_t mem_flags); ++extern int dwc_otg_hcd_urb_dequeue(struct usb_hcd *hcd, ++ struct urb *urb, ++ int status); ++extern irqreturn_t dwc_otg_hcd_irq(struct usb_hcd *hcd); ++ ++extern void dwc_otg_hcd_endpoint_disable(struct usb_hcd *hcd, ++ struct usb_host_endpoint *ep); ++ ++extern int dwc_otg_hcd_hub_status_data(struct usb_hcd *hcd, ++ char *buf); ++extern int dwc_otg_hcd_hub_control(struct usb_hcd *hcd, ++ u16 typeReq, ++ u16 wValue, ++ u16 wIndex, ++ char *buf, ++ u16 wLength); ++ ++/** @} */ ++ ++/** @name Transaction Execution Functions */ ++/** @{ */ ++extern dwc_otg_transaction_type_e dwc_otg_hcd_select_transactions(dwc_otg_hcd_t *_hcd); ++extern void dwc_otg_hcd_queue_transactions(dwc_otg_hcd_t *_hcd, ++ dwc_otg_transaction_type_e _tr_type); ++extern void dwc_otg_hcd_complete_urb(dwc_otg_hcd_t *_hcd, struct urb *_urb, ++ int _status); ++/** @} */ ++ ++/** @name Interrupt Handler Functions */ ++/** @{ */ ++extern int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_incomplete_periodic_intr(dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_conn_id_status_change_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_disconnect_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num); ++extern int32_t dwc_otg_hcd_handle_session_req_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++extern int32_t dwc_otg_hcd_handle_wakeup_detected_intr (dwc_otg_hcd_t *_dwc_otg_hcd); ++/** @} */ ++ ++ ++/** @name Schedule Queue Functions */ ++/** @{ */ ++ ++/* Implemented in dwc_otg_hcd_queue.c */ ++extern dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb); ++extern void dwc_otg_hcd_qh_init (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb); ++extern void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh); ++extern int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); ++extern void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh); ++extern void dwc_otg_hcd_qh_deactivate (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_csplit); ++extern int dwc_otg_hcd_qh_deferr (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int delay); ++ ++/** Remove and free a QH */ ++static inline void dwc_otg_hcd_qh_remove_and_free (dwc_otg_hcd_t *_hcd, ++ dwc_otg_qh_t *_qh) ++{ ++ dwc_otg_hcd_qh_remove (_hcd, _qh); ++ dwc_otg_hcd_qh_free (_qh); ++} ++ ++/** Allocates memory for a QH structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qh_t *dwc_otg_hcd_qh_alloc (void) ++{ ++#ifdef _SC_BUILD_ ++ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_ATOMIC); ++#else ++ return (dwc_otg_qh_t *) kmalloc (sizeof(dwc_otg_qh_t), GFP_KERNEL); ++#endif ++} ++ ++extern dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *urb); ++extern void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *qtd, struct urb *urb); ++extern int dwc_otg_hcd_qtd_add (dwc_otg_qtd_t *qtd, dwc_otg_hcd_t *dwc_otg_hcd); ++ ++/** Allocates memory for a QTD structure. ++ * @return Returns the memory allocate or NULL on error. */ ++static inline dwc_otg_qtd_t *dwc_otg_hcd_qtd_alloc (void) ++{ ++#ifdef _SC_BUILD_ ++ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_ATOMIC); ++#else ++ return (dwc_otg_qtd_t *) kmalloc (sizeof(dwc_otg_qtd_t), GFP_KERNEL); ++#endif ++} ++ ++/** Frees the memory for a QTD structure. QTD should already be removed from ++ * list. ++ * @param[in] _qtd QTD to free.*/ ++static inline void dwc_otg_hcd_qtd_free (dwc_otg_qtd_t *_qtd) ++{ ++ kfree (_qtd); ++} ++ ++/** Removes a QTD from list. ++ * @param[in] _qtd QTD to remove from list. */ ++static inline void dwc_otg_hcd_qtd_remove (dwc_otg_qtd_t *_qtd) ++{ ++ unsigned long flags; ++ local_irq_save (flags); ++ list_del (&_qtd->qtd_list_entry); ++ local_irq_restore (flags); ++} ++ ++/** Remove and free a QTD */ ++static inline void dwc_otg_hcd_qtd_remove_and_free (dwc_otg_qtd_t *_qtd) ++{ ++ dwc_otg_hcd_qtd_remove (_qtd); ++ dwc_otg_hcd_qtd_free (_qtd); ++} ++ ++/** @} */ ++ ++ ++/** @name Internal Functions */ ++/** @{ */ ++dwc_otg_qh_t *dwc_urb_to_qh(struct urb *_urb); ++void dwc_otg_hcd_dump_frrem(dwc_otg_hcd_t *_hcd); ++void dwc_otg_hcd_dump_state(dwc_otg_hcd_t *_hcd); ++/** @} */ ++ ++ ++/** Gets the usb_host_endpoint associated with an URB. */ ++static inline struct usb_host_endpoint *dwc_urb_to_endpoint(struct urb *_urb) ++{ ++ struct usb_device *dev = _urb->dev; ++ int ep_num = usb_pipeendpoint(_urb->pipe); ++ if (usb_pipein(_urb->pipe)) ++ return dev->ep_in[ep_num]; ++ else ++ return dev->ep_out[ep_num]; ++} ++ ++/** ++ * Gets the endpoint number from a _bEndpointAddress argument. The endpoint is ++ * qualified with its direction (possible 32 endpoints per device). ++ */ ++#define dwc_ep_addr_to_endpoint(_bEndpointAddress_) \ ++ ((_bEndpointAddress_ & USB_ENDPOINT_NUMBER_MASK) | \ ++ ((_bEndpointAddress_ & USB_DIR_IN) != 0) << 4) ++ ++/** Gets the QH that contains the list_head */ ++#define dwc_list_to_qh(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qh_t,qh_list_entry)) ++ ++/** Gets the QTD that contains the list_head */ ++#define dwc_list_to_qtd(_list_head_ptr_) (container_of(_list_head_ptr_,dwc_otg_qtd_t,qtd_list_entry)) ++ ++/** Check if QH is non-periodic */ ++#define dwc_qh_is_non_per(_qh_ptr_) ((_qh_ptr_->ep_type == USB_ENDPOINT_XFER_BULK) || \ ++ (_qh_ptr_->ep_type == USB_ENDPOINT_XFER_CONTROL)) ++ ++/** High bandwidth multiplier as encoded in highspeed endpoint descriptors */ ++#define dwc_hb_mult(wMaxPacketSize) (1 + (((wMaxPacketSize) >> 11) & 0x03)) ++ ++/** Packet size for any kind of endpoint descriptor */ ++#define dwc_max_packet(wMaxPacketSize) ((wMaxPacketSize) & 0x07ff) ++ ++/** ++ * Returns true if _frame1 is less than or equal to _frame2. The comparison is ++ * done modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the ++ * frame number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_le(uint16_t _frame1, uint16_t _frame2) ++{ ++ return ((_frame2 - _frame1) & DWC_HFNUM_MAX_FRNUM) <= ++ (DWC_HFNUM_MAX_FRNUM >> 1); ++} ++ ++/** ++ * Returns true if _frame1 is greater than _frame2. The comparison is done ++ * modulo DWC_HFNUM_MAX_FRNUM. This accounts for the rollover of the frame ++ * number when the max frame number is reached. ++ */ ++static inline int dwc_frame_num_gt(uint16_t _frame1, uint16_t _frame2) ++{ ++ return (_frame1 != _frame2) && ++ (((_frame1 - _frame2) & DWC_HFNUM_MAX_FRNUM) < ++ (DWC_HFNUM_MAX_FRNUM >> 1)); ++} ++ ++/** ++ * Increments _frame by the amount specified by _inc. The addition is done ++ * modulo DWC_HFNUM_MAX_FRNUM. Returns the incremented value. ++ */ ++static inline uint16_t dwc_frame_num_inc(uint16_t _frame, uint16_t _inc) ++{ ++ return (_frame + _inc) & DWC_HFNUM_MAX_FRNUM; ++} ++ ++static inline uint16_t dwc_full_frame_num (uint16_t _frame) ++{ ++ return ((_frame) & DWC_HFNUM_MAX_FRNUM) >> 3; ++} ++ ++static inline uint16_t dwc_micro_frame_num (uint16_t _frame) ++{ ++ return (_frame) & 0x7; ++} ++ ++#ifdef DEBUG ++/** ++ * Macro to sample the remaining PHY clocks left in the current frame. This ++ * may be used during debugging to determine the average time it takes to ++ * execute sections of code. There are two possible sample points, "a" and ++ * "b", so the _letter argument must be one of these values. ++ * ++ * To dump the average sample times, read the "hcd_frrem" sysfs attribute. For ++ * example, "cat /sys/devices/lm0/hcd_frrem". ++ */ ++#define dwc_sample_frrem(_hcd, _qh, _letter) \ ++{ \ ++ hfnum_data_t hfnum; \ ++ dwc_otg_qtd_t *qtd; \ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); \ ++ if (usb_pipeint(qtd->urb->pipe) && _qh->start_split_frame != 0 && !qtd->complete_split) { \ ++ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); \ ++ switch (hfnum.b.frnum & 0x7) { \ ++ case 7: \ ++ _hcd->hfnum_7_samples_##_letter++; \ ++ _hcd->hfnum_7_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ case 0: \ ++ _hcd->hfnum_0_samples_##_letter++; \ ++ _hcd->hfnum_0_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ default: \ ++ _hcd->hfnum_other_samples_##_letter++; \ ++ _hcd->hfnum_other_frrem_accum_##_letter += hfnum.b.frrem; \ ++ break; \ ++ } \ ++ } \ ++} ++#else // DEBUG ++#define dwc_sample_frrem(_hcd, _qh, _letter) ++#endif // DEBUG ++#endif // __DWC_HCD_H__ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_hcd_intr.c +@@ -0,0 +1,1841 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_intr.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 553126 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++#include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++const int erratum_usb09_patched = 0; ++const int deferral_on = 1; ++const int nak_deferral_delay = 8; ++const int nyet_deferral_delay = 1; ++/** @file ++ * This file contains the implementation of the HCD Interrupt handlers. ++ */ ++ ++/** This function handles interrupts for the HCD. */ ++int32_t dwc_otg_hcd_handle_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ int retval = 0; ++ ++ dwc_otg_core_if_t *core_if = _dwc_otg_hcd->core_if; ++ gintsts_data_t gintsts; ++#ifdef DEBUG ++ dwc_otg_core_global_regs_t *global_regs = core_if->core_global_regs; ++#endif ++ ++ /* Check if HOST Mode */ ++ if (dwc_otg_is_host_mode(core_if)) { ++ gintsts.d32 = dwc_otg_read_core_intr(core_if); ++ if (!gintsts.d32) { ++ return 0; ++ } ++ ++#ifdef DEBUG ++ /* Don't print debug message in the interrupt handler on SOF */ ++# ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++# endif ++ DWC_DEBUGPL (DBG_HCD, "\n"); ++#endif ++ ++#ifdef DEBUG ++# ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++# endif ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Interrupt Detected gintsts&gintmsk=0x%08x\n", gintsts.d32); ++#endif ++ ++ if (gintsts.b.sofintr) { ++ retval |= dwc_otg_hcd_handle_sof_intr (_dwc_otg_hcd); ++ } ++ if (gintsts.b.rxstsqlvl) { ++ retval |= dwc_otg_hcd_handle_rx_status_q_level_intr (_dwc_otg_hcd); ++ } ++ if (gintsts.b.nptxfempty) { ++ retval |= dwc_otg_hcd_handle_np_tx_fifo_empty_intr (_dwc_otg_hcd); ++ } ++ if (gintsts.b.i2cintr) { ++ /** @todo Implement i2cintr handler. */ ++ } ++ if (gintsts.b.portintr) { ++ retval |= dwc_otg_hcd_handle_port_intr (_dwc_otg_hcd); ++ } ++ if (gintsts.b.hcintr) { ++ retval |= dwc_otg_hcd_handle_hc_intr (_dwc_otg_hcd); ++ } ++ if (gintsts.b.ptxfempty) { ++ retval |= dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (_dwc_otg_hcd); ++ } ++#ifdef DEBUG ++# ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++# endif ++ { ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD Finished Servicing Interrupts\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintsts=0x%08x\n", ++ dwc_read_reg32(&global_regs->gintsts)); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD gintmsk=0x%08x\n", ++ dwc_read_reg32(&global_regs->gintmsk)); ++ } ++#endif ++ ++#ifdef DEBUG ++# ifndef DEBUG_SOF ++ if (gintsts.d32 != DWC_SOF_INTR_MASK) ++# endif ++ DWC_DEBUGPL (DBG_HCD, "\n"); ++#endif ++ ++ } ++ ++ return retval; ++} ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++#warning Compiling code to track missed SOFs ++#define FRAME_NUM_ARRAY_SIZE 1000 ++/** ++ * This function is for debug only. ++ */ ++static inline void track_missed_sofs(uint16_t _curr_frame_number) { ++ static uint16_t frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static uint16_t last_frame_num_array[FRAME_NUM_ARRAY_SIZE]; ++ static int frame_num_idx = 0; ++ static uint16_t last_frame_num = DWC_HFNUM_MAX_FRNUM; ++ static int dumped_frame_num_array = 0; ++ ++ if (frame_num_idx < FRAME_NUM_ARRAY_SIZE) { ++ if ((((last_frame_num + 1) & DWC_HFNUM_MAX_FRNUM) != _curr_frame_number)) { ++ frame_num_array[frame_num_idx] = _curr_frame_number; ++ last_frame_num_array[frame_num_idx++] = last_frame_num; ++ } ++ } else if (!dumped_frame_num_array) { ++ int i; ++ printk(KERN_EMERG USB_DWC "Frame Last Frame\n"); ++ printk(KERN_EMERG USB_DWC "----- ----------\n"); ++ for (i = 0; i < FRAME_NUM_ARRAY_SIZE; i++) { ++ printk(KERN_EMERG USB_DWC "0x%04x 0x%04x\n", ++ frame_num_array[i], last_frame_num_array[i]); ++ } ++ dumped_frame_num_array = 1; ++ } ++ last_frame_num = _curr_frame_number; ++} ++#endif ++ ++/** ++ * Handles the start-of-frame interrupt in host mode. Non-periodic ++ * transactions may be queued to the DWC_otg controller for the current ++ * (micro)frame. Periodic transactions may be queued to the controller for the ++ * next (micro)frame. ++ */ ++int32_t dwc_otg_hcd_handle_sof_intr (dwc_otg_hcd_t *_hcd) ++{ ++ hfnum_data_t hfnum; ++ struct list_head *qh_entry; ++ dwc_otg_qh_t *qh; ++ dwc_otg_transaction_type_e tr_type; ++ gintsts_data_t gintsts = {.d32 = 0}; ++ ++ hfnum.d32 = dwc_read_reg32(&_hcd->core_if->host_if->host_global_regs->hfnum); ++ ++#ifdef DEBUG_SOF ++ DWC_DEBUGPL(DBG_HCD, "--Start of Frame Interrupt--\n"); ++#endif ++ ++ _hcd->frame_number = hfnum.b.frnum; ++ ++#ifdef DEBUG ++ _hcd->frrem_accum += hfnum.b.frrem; ++ _hcd->frrem_samples++; ++#endif ++ ++#ifdef DWC_TRACK_MISSED_SOFS ++ track_missed_sofs(_hcd->frame_number); ++#endif ++ ++ /* Determine whether any periodic QHs should be executed. */ ++ qh_entry = _hcd->periodic_sched_inactive.next; ++ while (qh_entry != &_hcd->periodic_sched_inactive) { ++ qh = list_entry(qh_entry, dwc_otg_qh_t, qh_list_entry); ++ qh_entry = qh_entry->next; ++ if (dwc_frame_num_le(qh->sched_frame, _hcd->frame_number)) { ++ /* ++ * Move QH to the ready list to be executed next ++ * (micro)frame. ++ */ ++ list_move(&qh->qh_list_entry, &_hcd->periodic_sched_ready); ++ } ++ } ++ ++ tr_type = dwc_otg_hcd_select_transactions(_hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(_hcd, tr_type); ++ } ++ ++ /* Clear interrupt */ ++ gintsts.b.sofintr = 1; ++ dwc_write_reg32(&_hcd->core_if->core_global_regs->gintsts, gintsts.d32); ++ ++ return 1; ++} ++ ++/** Handles the Rx Status Queue Level Interrupt, which indicates that there is at ++ * least one packet in the Rx FIFO. The packets are moved from the FIFO to ++ * memory if the DWC_otg controller is operating in Slave mode. */ ++int32_t dwc_otg_hcd_handle_rx_status_q_level_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ host_grxsts_data_t grxsts; ++ dwc_hc_t *hc = NULL; ++ ++ DWC_DEBUGPL(DBG_HCD, "--RxStsQ Level Interrupt--\n"); ++ ++ grxsts.d32 = dwc_read_reg32(&_dwc_otg_hcd->core_if->core_global_regs->grxstsp); ++ ++ hc = _dwc_otg_hcd->hc_ptr_array[grxsts.b.chnum]; ++ ++ /* Packet Status */ ++ DWC_DEBUGPL(DBG_HCDV, " Ch num = %d\n", grxsts.b.chnum); ++ DWC_DEBUGPL(DBG_HCDV, " Count = %d\n", grxsts.b.bcnt); ++ DWC_DEBUGPL(DBG_HCDV, " DPID = %d, hc.dpid = %d\n", grxsts.b.dpid, hc->data_pid_start); ++ DWC_DEBUGPL(DBG_HCDV, " PStatus = %d\n", grxsts.b.pktsts); ++ ++ switch (grxsts.b.pktsts) { ++ case DWC_GRXSTS_PKTSTS_IN: ++ /* Read the data into the host buffer. */ ++ if (grxsts.b.bcnt > 0) { ++ dwc_otg_read_packet(_dwc_otg_hcd->core_if, ++ hc->xfer_buff, ++ grxsts.b.bcnt); ++ ++ /* Update the HC fields for the next packet received. */ ++ hc->xfer_count += grxsts.b.bcnt; ++ hc->xfer_buff += grxsts.b.bcnt; ++ } ++ ++ case DWC_GRXSTS_PKTSTS_IN_XFER_COMP: ++ case DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR: ++ case DWC_GRXSTS_PKTSTS_CH_HALTED: ++ /* Handled in interrupt, just ignore data */ ++ break; ++ default: ++ DWC_ERROR ("RX_STS_Q Interrupt: Unknown status %d\n", grxsts.b.pktsts); ++ break; ++ } ++ ++ return 1; ++} ++ ++/** This interrupt occurs when the non-periodic Tx FIFO is half-empty. More ++ * data packets may be written to the FIFO for OUT transfers. More requests ++ * may be written to the non-periodic request queue for IN transfers. This ++ * interrupt is enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_np_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Non-Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_NON_PERIODIC); ++ return 1; ++} ++ ++/** This interrupt occurs when the periodic Tx FIFO is half-empty. More data ++ * packets may be written to the FIFO for OUT transfers. More requests may be ++ * written to the periodic request queue for IN transfers. This interrupt is ++ * enabled only in Slave mode. */ ++int32_t dwc_otg_hcd_handle_perio_tx_fifo_empty_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Periodic TxFIFO Empty Interrupt--\n"); ++ dwc_otg_hcd_queue_transactions(_dwc_otg_hcd, ++ DWC_OTG_TRANSACTION_PERIODIC); ++ return 1; ++} ++ ++/** There are multiple conditions that can cause a port interrupt. This function ++ * determines which interrupt conditions have occurred and handles them ++ * appropriately. */ ++int32_t dwc_otg_hcd_handle_port_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ int retval = 0; ++ hprt0_data_t hprt0; ++ hprt0_data_t hprt0_modify; ++ ++ hprt0.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); ++ hprt0_modify.d32 = dwc_read_reg32(_dwc_otg_hcd->core_if->host_if->hprt0); ++ ++ /* Clear appropriate bits in HPRT0 to clear the interrupt bit in ++ * GINTSTS */ ++ ++ hprt0_modify.b.prtena = 0; ++ hprt0_modify.b.prtconndet = 0; ++ hprt0_modify.b.prtenchng = 0; ++ hprt0_modify.b.prtovrcurrchng = 0; ++ ++ /* Port Connect Detected ++ * Set flag and clear if detected */ ++ if (hprt0.b.prtconndet) { ++ DWC_DEBUGPL(DBG_HCD, "--Port Interrupt HPRT0=0x%08x " ++ "Port Connect Detected--\n", hprt0.d32); ++ _dwc_otg_hcd->flags.b.port_connect_status_change = 1; ++ _dwc_otg_hcd->flags.b.port_connect_status = 1; ++ hprt0_modify.b.prtconndet = 1; ++ ++ /* B-Device has connected, Delete the connection timer. */ ++ del_timer( &_dwc_otg_hcd->conn_timer ); ++ ++ /* The Hub driver asserts a reset when it sees port connect ++ * status change flag */ ++ retval |= 1; ++ } ++ ++ /* Port Enable Changed ++ * Clear if detected - Set internal flag if disabled */ ++ if (hprt0.b.prtenchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Enable Changed--\n", hprt0.d32); ++ hprt0_modify.b.prtenchng = 1; ++ if (hprt0.b.prtena == 1) { ++ int do_reset = 0; ++ dwc_otg_core_params_t *params = _dwc_otg_hcd->core_if->core_params; ++ dwc_otg_core_global_regs_t *global_regs = _dwc_otg_hcd->core_if->core_global_regs; ++ dwc_otg_host_if_t *host_if = _dwc_otg_hcd->core_if->host_if; ++ ++ /* Check if we need to adjust the PHY clock speed for ++ * low power and adjust it */ ++ if (params->host_support_fs_ls_low_power) ++ { ++ gusbcfg_data_t usbcfg; ++ ++ usbcfg.d32 = dwc_read_reg32 (&global_regs->gusbcfg); ++ ++ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) || ++ (hprt0.b.prtspd == DWC_HPRT0_PRTSPD_FULL_SPEED)) ++ { ++ /* ++ * Low power ++ */ ++ hcfg_data_t hcfg; ++ if (usbcfg.b.phylpwrclksel == 0) { ++ /* Set PHY low power clock select for FS/LS devices */ ++ usbcfg.b.phylpwrclksel = 1; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ do_reset = 1; ++ } ++ ++ hcfg.d32 = dwc_read_reg32(&host_if->host_global_regs->hcfg); ++ ++ if ((hprt0.b.prtspd == DWC_HPRT0_PRTSPD_LOW_SPEED) && ++ (params->host_ls_low_power_phy_clk == ++ DWC_HOST_LS_LOW_POWER_PHY_CLK_PARAM_6MHZ)) ++ { ++ /* 6 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 6 MHz (Low Power)\n"); ++ if (hcfg.b.fslspclksel != DWC_HCFG_6_MHZ) { ++ hcfg.b.fslspclksel = DWC_HCFG_6_MHZ; ++ dwc_write_reg32(&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } ++ else { ++ /* 48 MHZ */ ++ DWC_DEBUGPL(DBG_CIL, "FS_PHY programming HCFG to 48 MHz ()\n"); ++ if (hcfg.b.fslspclksel != DWC_HCFG_48_MHZ) { ++ hcfg.b.fslspclksel = DWC_HCFG_48_MHZ; ++ dwc_write_reg32(&host_if->host_global_regs->hcfg, ++ hcfg.d32); ++ do_reset = 1; ++ } ++ } ++ } ++ else { ++ /* ++ * Not low power ++ */ ++ if (usbcfg.b.phylpwrclksel == 1) { ++ usbcfg.b.phylpwrclksel = 0; ++ dwc_write_reg32(&global_regs->gusbcfg, usbcfg.d32); ++ do_reset = 1; ++ } ++ } ++ ++ if (do_reset) { ++ tasklet_schedule(_dwc_otg_hcd->reset_tasklet); ++ } ++ } ++ ++ if (!do_reset) { ++ /* Port has been enabled set the reset change flag */ ++ _dwc_otg_hcd->flags.b.port_reset_change = 1; ++ } ++ ++ } else { ++ _dwc_otg_hcd->flags.b.port_enable_change = 1; ++ } ++ retval |= 1; ++ } ++ ++ /** Overcurrent Change Interrupt */ ++ if (hprt0.b.prtovrcurrchng) { ++ DWC_DEBUGPL(DBG_HCD, " --Port Interrupt HPRT0=0x%08x " ++ "Port Overcurrent Changed--\n", hprt0.d32); ++ _dwc_otg_hcd->flags.b.port_over_current_change = 1; ++ hprt0_modify.b.prtovrcurrchng = 1; ++ retval |= 1; ++ } ++ ++ /* Clear Port Interrupts */ ++ dwc_write_reg32(_dwc_otg_hcd->core_if->host_if->hprt0, hprt0_modify.d32); ++ ++ return retval; ++} ++ ++ ++/** This interrupt indicates that one or more host channels has a pending ++ * interrupt. There are multiple conditions that can cause each host channel ++ * interrupt. This function determines which conditions have occurred for each ++ * host channel interrupt and handles them appropriately. */ ++int32_t dwc_otg_hcd_handle_hc_intr (dwc_otg_hcd_t *_dwc_otg_hcd) ++{ ++ int i; ++ int retval = 0; ++ haint_data_t haint; ++ ++ /* Clear appropriate bits in HCINTn to clear the interrupt bit in ++ * GINTSTS */ ++ ++ haint.d32 = dwc_otg_read_host_all_channels_intr(_dwc_otg_hcd->core_if); ++ ++ for (i=0; i<_dwc_otg_hcd->core_if->core_params->host_channels; i++) { ++ if (haint.b2.chint & (1 << i)) { ++ retval |= dwc_otg_hcd_handle_hc_n_intr (_dwc_otg_hcd, i); ++ } ++ } ++ ++ return retval; ++} ++ ++/* Macro used to clear one channel interrupt */ ++#define clear_hc_int(_hc_regs_,_intr_) \ ++do { \ ++ hcint_data_t hcint_clear = {.d32 = 0}; \ ++ hcint_clear.b._intr_ = 1; \ ++ dwc_write_reg32(&((_hc_regs_)->hcint), hcint_clear.d32); \ ++} while (0) ++ ++/* ++ * Macro used to disable one channel interrupt. Channel interrupts are ++ * disabled when the channel is halted or released by the interrupt handler. ++ * There is no need to handle further interrupts of that type until the ++ * channel is re-assigned. In fact, subsequent handling may cause crashes ++ * because the channel structures are cleaned up when the channel is released. ++ */ ++#define disable_hc_int(_hc_regs_,_intr_) \ ++do { \ ++ hcintmsk_data_t hcintmsk = {.d32 = 0}; \ ++ hcintmsk.b._intr_ = 1; \ ++ dwc_modify_reg32(&((_hc_regs_)->hcintmsk), hcintmsk.d32, 0); \ ++} while (0) ++ ++/** ++ * Gets the actual length of a transfer after the transfer halts. _halt_status ++ * holds the reason for the halt. ++ * ++ * For IN transfers where _halt_status is DWC_OTG_HC_XFER_COMPLETE, ++ * *_short_read is set to 1 upon return if less than the requested ++ * number of bytes were transferred. Otherwise, *_short_read is set to 0 upon ++ * return. _short_read may also be NULL on entry, in which case it remains ++ * unchanged. ++ */ ++static uint32_t get_actual_xfer_length(dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status, ++ int *_short_read) ++{ ++ hctsiz_data_t hctsiz; ++ uint32_t length; ++ ++ if (_short_read != NULL) { ++ *_short_read = 0; ++ } ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ ++ if (_halt_status == DWC_OTG_HC_XFER_COMPLETE) { ++ if (_hc->ep_is_in) { ++ length = _hc->xfer_len - hctsiz.b.xfersize; ++ if (_short_read != NULL) { ++ *_short_read = (hctsiz.b.xfersize != 0); ++ } ++ } else if (_hc->qh->do_split) { ++ length = _qtd->ssplit_out_xfer_count; ++ } else { ++ length = _hc->xfer_len; ++ } ++ } else { ++ /* ++ * Must use the hctsiz.pktcnt field to determine how much data ++ * has been transferred. This field reflects the number of ++ * packets that have been transferred via the USB. This is ++ * always an integral number of packets if the transfer was ++ * halted before its normal completion. (Can't use the ++ * hctsiz.xfersize field because that reflects the number of ++ * bytes transferred via the AHB, not the USB). ++ */ ++ length = (_hc->start_pkt_count - hctsiz.b.pktcnt) * _hc->max_packet; ++ } ++ ++ return length; ++} ++ ++/** ++ * Updates the state of the URB after a Transfer Complete interrupt on the ++ * host channel. Updates the actual_length field of the URB based on the ++ * number of bytes transferred via the host channel. Sets the URB status ++ * if the data transfer is finished. ++ * ++ * @return 1 if the data transfer specified by the URB is completely finished, ++ * 0 otherwise. ++ */ ++static int update_urb_state_xfer_comp(dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t * _hc_regs, struct urb *_urb, ++ dwc_otg_qtd_t * _qtd, int *status) ++{ ++ int xfer_done = 0; ++ int short_read = 0; ++ ++ _urb->actual_length += get_actual_xfer_length(_hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_COMPLETE, ++ &short_read); ++ ++ if (short_read || (_urb->actual_length == _urb->transfer_buffer_length)) { ++ xfer_done = 1; ++ if (short_read && (_urb->transfer_flags & URB_SHORT_NOT_OK)) { ++ *status = -EREMOTEIO; ++ } else { ++ *status = 0; ++ } ++ } ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " hc->xfer_len %d\n", _hc->xfer_len); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.xfersize %d\n", hctsiz.b.xfersize); ++ DWC_DEBUGPL(DBG_HCDV, " urb->transfer_buffer_length %d\n", ++ _urb->transfer_buffer_length); ++ DWC_DEBUGPL(DBG_HCDV, " urb->actual_length %d\n", _urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " short_read %d, xfer_done %d\n", ++ short_read, xfer_done); ++ } ++#endif ++ ++ return xfer_done; ++} ++ ++/* ++ * Save the starting data toggle for the next transfer. The data toggle is ++ * saved in the QH for non-control transfers and it's saved in the QTD for ++ * control transfers. ++ */ ++static void save_data_toggle(dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd) ++{ ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ ++ if (_hc->ep_type != DWC_OTG_EP_TYPE_CONTROL) { ++ dwc_otg_qh_t *qh = _hc->qh; ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ qh->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } else { ++ if (hctsiz.b.pid == DWC_HCTSIZ_DATA0) { ++ _qtd->data_toggle = DWC_OTG_HC_PID_DATA0; ++ } else { ++ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ } ++ } ++} ++ ++/** ++ * Frees the first QTD in the QH's list if free_qtd is 1. For non-periodic ++ * QHs, removes the QH from the active non-periodic schedule. If any QTDs are ++ * still linked to the QH, the QH is added to the end of the inactive ++ * non-periodic schedule. For periodic QHs, removes the QH from the periodic ++ * schedule if no more QTDs are linked to the QH. ++ */ ++static void deactivate_qh(dwc_otg_hcd_t *_hcd, ++ dwc_otg_qh_t *_qh, ++ int free_qtd) ++{ ++ int continue_split = 0; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s(%p,%p,%d)\n", __func__, _hcd, _qh, free_qtd); ++ ++ qtd = list_entry(_qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); ++ ++ if (qtd->complete_split) { ++ continue_split = 1; ++ } ++ else if ((qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_MID) || ++ (qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_END)) ++ { ++ continue_split = 1; ++ } ++ ++ if (free_qtd) { ++ /* ++ * Note that this was previously a call to ++ * dwc_otg_hcd_qtd_remove_and_free(qtd), which frees the qtd. ++ * However, that call frees the qtd memory, and we continue in the ++ * interrupt logic to access it many more times, including writing ++ * to it. With slub debugging on, it is clear that we were writing ++ * to memory we had freed. ++ * Call this instead, and now I have moved the freeing of the memory to ++ * the end of processing this interrupt. ++ */ ++ //dwc_otg_hcd_qtd_remove_and_free(qtd); ++ dwc_otg_hcd_qtd_remove(qtd); ++ ++ continue_split = 0; ++ } ++ ++ _qh->channel = NULL; ++ _qh->qtd_in_process = NULL; ++ dwc_otg_hcd_qh_deactivate(_hcd, _qh, continue_split); ++} ++ ++/** ++ * Updates the state of an Isochronous URB when the transfer is stopped for ++ * any reason. The fields of the current entry in the frame descriptor array ++ * are set based on the transfer state and the input _halt_status. Completes ++ * the Isochronous URB if all the URB frames have been completed. ++ * ++ * @return DWC_OTG_HC_XFER_COMPLETE if there are more frames remaining to be ++ * transferred in the URB. Otherwise return DWC_OTG_HC_XFER_URB_COMPLETE. ++ */ ++static dwc_otg_halt_status_e ++update_isoc_urb_state(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status) ++{ ++ struct urb *urb = _qtd->urb; ++ dwc_otg_halt_status_e ret_val = _halt_status; ++ struct usb_iso_packet_descriptor *frame_desc; ++ ++ frame_desc = &urb->iso_frame_desc[_qtd->isoc_frame_index]; ++ switch (_halt_status) { ++ case DWC_OTG_HC_XFER_COMPLETE: ++ frame_desc->status = 0; ++ frame_desc->actual_length = ++ get_actual_xfer_length(_hc, _hc_regs, _qtd, ++ _halt_status, NULL); ++ break; ++ case DWC_OTG_HC_XFER_FRAME_OVERRUN: ++ urb->error_count++; ++ if (_hc->ep_is_in) { ++ frame_desc->status = -ENOSR; ++ } else { ++ frame_desc->status = -ECOMM; ++ } ++ frame_desc->actual_length = 0; ++ break; ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ urb->error_count++; ++ frame_desc->status = -EOVERFLOW; ++ /* Don't need to update actual_length in this case. */ ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ urb->error_count++; ++ frame_desc->status = -EPROTO; ++ frame_desc->actual_length = ++ get_actual_xfer_length(_hc, _hc_regs, _qtd, ++ _halt_status, NULL); ++ default: ++ DWC_ERROR("%s: Unhandled _halt_status (%d)\n", __func__, ++ _halt_status); ++ BUG(); ++ break; ++ } ++ ++ if (++_qtd->isoc_frame_index == urb->number_of_packets) { ++ /* ++ * urb->status is not used for isoc transfers. ++ * The individual frame_desc statuses are used instead. ++ */ ++ dwc_otg_hcd_complete_urb(_hcd, urb, 0); ++ ret_val = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ ret_val = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ return ret_val; ++} ++ ++/** ++ * Releases a host channel for use by other transfers. Attempts to select and ++ * queue more transactions since at least one host channel is available. ++ * ++ * @param _hcd The HCD state structure. ++ * @param _hc The host channel to release. ++ * @param _qtd The QTD associated with the host channel. This QTD may be freed ++ * if the transfer is complete or an error has occurred. ++ * @param _halt_status Reason the channel is being released. This status ++ * determines the actions taken by this function. ++ */ ++static void release_channel(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status, ++ int *must_free) ++{ ++ dwc_otg_transaction_type_e tr_type; ++ int free_qtd; ++ dwc_otg_qh_t * _qh; ++ int deact = 1; ++ int retry_delay = 1; ++ unsigned long flags; ++ ++ DWC_DEBUGPL(DBG_HCDV, " %s: channel %d, halt_status %d\n", __func__, ++ _hc->hc_num, _halt_status); ++ ++ switch (_halt_status) { ++ case DWC_OTG_HC_XFER_NYET: ++ case DWC_OTG_HC_XFER_NAK: ++ if (_halt_status == DWC_OTG_HC_XFER_NYET) { ++ retry_delay = nyet_deferral_delay; ++ } else { ++ retry_delay = nak_deferral_delay; ++ } ++ free_qtd = 0; ++ if (deferral_on && _hc->do_split) { ++ _qh = _hc->qh; ++ if (_qh) { ++ deact = dwc_otg_hcd_qh_deferr(_hcd, _qh , retry_delay); ++ } ++ } ++ break; ++ case DWC_OTG_HC_XFER_URB_COMPLETE: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_AHB_ERR: ++ case DWC_OTG_HC_XFER_STALL: ++ case DWC_OTG_HC_XFER_BABBLE_ERR: ++ free_qtd = 1; ++ break; ++ case DWC_OTG_HC_XFER_XACT_ERR: ++ if (_qtd->error_count >= 3) { ++ DWC_DEBUGPL(DBG_HCDV, " Complete URB with transaction error\n"); ++ free_qtd = 1; ++ //_qtd->urb->status = -EPROTO; ++ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPROTO); ++ } else { ++ free_qtd = 0; ++ } ++ break; ++ case DWC_OTG_HC_XFER_URB_DEQUEUE: ++ /* ++ * The QTD has already been removed and the QH has been ++ * deactivated. Don't want to do anything except release the ++ * host channel and try to queue more transfers. ++ */ ++ goto cleanup; ++ case DWC_OTG_HC_XFER_NO_HALT_STATUS: ++ DWC_ERROR("%s: No halt_status, channel %d\n", __func__, _hc->hc_num); ++ free_qtd = 0; ++ break; ++ default: ++ free_qtd = 0; ++ break; ++ } ++ if (free_qtd) { ++ /* Only change must_free to true (do not set to zero here -- it is ++ * pre-initialized to zero). ++ */ ++ *must_free = 1; ++ } ++ if (deact) { ++ deactivate_qh(_hcd, _hc->qh, free_qtd); ++ } ++ cleanup: ++ /* ++ * Release the host channel for use by other transfers. The cleanup ++ * function clears the channel interrupt enables and conditions, so ++ * there's no need to clear the Channel Halted interrupt separately. ++ */ ++ dwc_otg_hc_cleanup(_hcd->core_if, _hc); ++ list_add_tail(&_hc->hc_list_entry, &_hcd->free_hc_list); ++ ++ local_irq_save(flags); ++ _hcd->available_host_channels++; ++ local_irq_restore(flags); ++ /* Try to queue more transfers now that there's a free channel, */ ++ /* unless erratum_usb09_patched is set */ ++ if (!erratum_usb09_patched) { ++ tr_type = dwc_otg_hcd_select_transactions(_hcd); ++ if (tr_type != DWC_OTG_TRANSACTION_NONE) { ++ dwc_otg_hcd_queue_transactions(_hcd, tr_type); ++ } ++ } ++} ++ ++/** ++ * Halts a host channel. If the channel cannot be halted immediately because ++ * the request queue is full, this function ensures that the FIFO empty ++ * interrupt for the appropriate queue is enabled so that the halt request can ++ * be queued when there is space in the request queue. ++ * ++ * This function may also be called in DMA mode. In that case, the channel is ++ * simply released since the core always halts the channel automatically in ++ * DMA mode. ++ */ ++static void halt_channel(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status, int *must_free) ++{ ++ if (_hcd->core_if->dma_enable) { ++ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); ++ return; ++ } ++ ++ /* Slave mode processing... */ ++ dwc_otg_hc_halt(_hcd->core_if, _hc, _halt_status); ++ ++ if (_hc->halt_on_queue) { ++ gintmsk_data_t gintmsk = {.d32 = 0}; ++ dwc_otg_core_global_regs_t *global_regs; ++ global_regs = _hcd->core_if->core_global_regs; ++ ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_CONTROL || ++ _hc->ep_type == DWC_OTG_EP_TYPE_BULK) { ++ /* ++ * Make sure the Non-periodic Tx FIFO empty interrupt ++ * is enabled so that the non-periodic schedule will ++ * be processed. ++ */ ++ gintmsk.b.nptxfempty = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } else { ++ /* ++ * Move the QH from the periodic queued schedule to ++ * the periodic assigned schedule. This allows the ++ * halt to be queued when the periodic schedule is ++ * processed. ++ */ ++ list_move(&_hc->qh->qh_list_entry, ++ &_hcd->periodic_sched_assigned); ++ ++ /* ++ * Make sure the Periodic Tx FIFO Empty interrupt is ++ * enabled so that the periodic schedule will be ++ * processed. ++ */ ++ gintmsk.b.ptxfempty = 1; ++ dwc_modify_reg32(&global_regs->gintmsk, 0, gintmsk.d32); ++ } ++ } ++} ++ ++/** ++ * Performs common cleanup for non-periodic transfers after a Transfer ++ * Complete interrupt. This function should be called after any endpoint type ++ * specific handling is finished to release the host channel. ++ */ ++static void complete_non_periodic_xfer(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status, int *must_free) ++{ ++ hcint_data_t hcint; ++ ++ _qtd->error_count = 0; ++ ++ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); ++ if (hcint.b.nyet) { ++ /* ++ * Got a NYET on the last transaction of the transfer. This ++ * means that the endpoint should be in the PING state at the ++ * beginning of the next transfer. ++ */ ++ _hc->qh->ping_state = 1; ++ clear_hc_int(_hc_regs,nyet); ++ } ++ ++ /* ++ * Always halt and release the host channel to make it available for ++ * more transfers. There may still be more phases for a control ++ * transfer or more data packets for a bulk transfer at this point, ++ * but the host channel is still halted. A channel will be reassigned ++ * to the transfer when the non-periodic schedule is processed after ++ * the channel is released. This allows transactions to be queued ++ * properly via dwc_otg_hcd_queue_transactions, which also enables the ++ * Tx FIFO Empty interrupt if necessary. ++ */ ++ if (_hc->ep_is_in) { ++ /* ++ * IN transfers in Slave mode require an explicit disable to ++ * halt the channel. (In DMA mode, this call simply releases ++ * the channel.) ++ */ ++ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); ++ } else { ++ /* ++ * The channel is automatically disabled by the core for OUT ++ * transfers in Slave mode. ++ */ ++ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); ++ } ++} ++ ++/** ++ * Performs common cleanup for periodic transfers after a Transfer Complete ++ * interrupt. This function should be called after any endpoint type specific ++ * handling is finished to release the host channel. ++ */ ++static void complete_periodic_xfer(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status, int *must_free) ++{ ++ hctsiz_data_t hctsiz; ++ _qtd->error_count = 0; ++ ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ if (!_hc->ep_is_in || hctsiz.b.pktcnt == 0) { ++ /* Core halts channel in these cases. */ ++ release_channel(_hcd, _hc, _qtd, _halt_status, must_free); ++ } else { ++ /* Flush any outstanding requests from the Tx queue. */ ++ halt_channel(_hcd, _hc, _qtd, _halt_status, must_free); ++ } ++} ++ ++/** ++ * Handles a host channel Transfer Complete interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xfercomp_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, int *must_free) ++{ ++ int urb_xfer_done; ++ dwc_otg_halt_status_e halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ struct urb *urb = _qtd->urb; ++ int pipe_type = usb_pipetype(urb->pipe); ++ int status = -EINPROGRESS; ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Transfer Complete--\n", _hc->hc_num); ++ ++ /* ++ * Handle xfer complete on CSPLIT. ++ */ ++ if (_hc->qh->do_split) { ++ _qtd->complete_split = 0; ++ } ++ ++ /* Update the QTD and URB states. */ ++ switch (pipe_type) { ++ case PIPE_CONTROL: ++ switch (_qtd->control_phase) { ++ case DWC_OTG_CONTROL_SETUP: ++ if (urb->transfer_buffer_length > 0) { ++ _qtd->control_phase = DWC_OTG_CONTROL_DATA; ++ } else { ++ _qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ } ++ DWC_DEBUGPL(DBG_HCDV, " Control setup transaction done\n"); ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ case DWC_OTG_CONTROL_DATA: { ++ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs,urb, _qtd, &status); ++ if (urb_xfer_done) { ++ _qtd->control_phase = DWC_OTG_CONTROL_STATUS; ++ DWC_DEBUGPL(DBG_HCDV, " Control data transfer done\n"); ++ } else { ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ } ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ break; ++ } ++ case DWC_OTG_CONTROL_STATUS: ++ DWC_DEBUGPL(DBG_HCDV, " Control transfer complete\n"); ++ if (status == -EINPROGRESS) { ++ status = 0; ++ } ++ dwc_otg_hcd_complete_urb(_hcd, urb, status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ break; ++ } ++ ++ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, ++ halt_status, must_free); ++ break; ++ case PIPE_BULK: ++ DWC_DEBUGPL(DBG_HCDV, " Bulk transfer complete\n"); ++ urb_xfer_done = update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); ++ if (urb_xfer_done) { ++ dwc_otg_hcd_complete_urb(_hcd, urb, status); ++ halt_status = DWC_OTG_HC_XFER_URB_COMPLETE; ++ } else { ++ halt_status = DWC_OTG_HC_XFER_COMPLETE; ++ } ++ ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ complete_non_periodic_xfer(_hcd, _hc, _hc_regs, _qtd,halt_status, must_free); ++ break; ++ case PIPE_INTERRUPT: ++ DWC_DEBUGPL(DBG_HCDV, " Interrupt transfer complete\n"); ++ update_urb_state_xfer_comp(_hc, _hc_regs, urb, _qtd, &status); ++ ++ /* ++ * Interrupt URB is done on the first transfer complete ++ * interrupt. ++ */ ++ dwc_otg_hcd_complete_urb(_hcd, urb, status); ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_URB_COMPLETE, must_free); ++ break; ++ case PIPE_ISOCHRONOUS: ++ DWC_DEBUGPL(DBG_HCDV, " Isochronous transfer complete\n"); ++ if (_qtd->isoc_split_pos == DWC_HCSPLIT_XACTPOS_ALL) ++ { ++ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_COMPLETE); ++ } ++ complete_periodic_xfer(_hcd, _hc, _hc_regs, _qtd, halt_status, must_free); ++ break; ++ } ++ ++ disable_hc_int(_hc_regs,xfercompl); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel STALL interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_stall_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, int *must_free) ++{ ++ struct urb *urb = _qtd->urb; ++ int pipe_type = usb_pipetype(urb->pipe); ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "STALL Received--\n", _hc->hc_num); ++ ++ if (pipe_type == PIPE_CONTROL) { ++ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); ++ } ++ ++ if (pipe_type == PIPE_BULK || pipe_type == PIPE_INTERRUPT) { ++ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EPIPE); ++ /* ++ * USB protocol requires resetting the data toggle for bulk ++ * and interrupt endpoints when a CLEAR_FEATURE(ENDPOINT_HALT) ++ * setup command is issued to the endpoint. Anticipate the ++ * CLEAR_FEATURE command since a STALL has occurred and reset ++ * the data toggle now. ++ */ ++ _hc->qh->data_toggle = 0; ++ } ++ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_STALL, must_free); ++ disable_hc_int(_hc_regs,stall); ++ ++ return 1; ++} ++ ++/* ++ * Updates the state of the URB when a transfer has been stopped due to an ++ * abnormal condition before the transfer completes. Modifies the ++ * actual_length field of the URB to reflect the number of bytes that have ++ * actually been transferred via the host channel. ++ */ ++static void update_urb_state_xfer_intr(dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ struct urb *_urb, ++ dwc_otg_qtd_t *_qtd, ++ dwc_otg_halt_status_e _halt_status) ++{ ++ uint32_t bytes_transferred = get_actual_xfer_length(_hc, _hc_regs, _qtd, ++ _halt_status, NULL); ++ _urb->actual_length += bytes_transferred; ++ ++#ifdef DEBUG ++ { ++ hctsiz_data_t hctsiz; ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ DWC_DEBUGPL(DBG_HCDV, "DWC_otg: %s: %s, channel %d\n", ++ __func__, (_hc->ep_is_in ? "IN" : "OUT"), _hc->hc_num); ++ DWC_DEBUGPL(DBG_HCDV, " _hc->start_pkt_count %d\n", _hc->start_pkt_count); ++ DWC_DEBUGPL(DBG_HCDV, " hctsiz.pktcnt %d\n", hctsiz.b.pktcnt); ++ DWC_DEBUGPL(DBG_HCDV, " _hc->max_packet %d\n", _hc->max_packet); ++ DWC_DEBUGPL(DBG_HCDV, " bytes_transferred %d\n", bytes_transferred); ++ DWC_DEBUGPL(DBG_HCDV, " _urb->actual_length %d\n", _urb->actual_length); ++ DWC_DEBUGPL(DBG_HCDV, " _urb->transfer_buffer_length %d\n", ++ _urb->transfer_buffer_length); ++ } ++#endif ++} ++ ++/** ++ * Handles a host channel NAK interrupt. This handler may be called in either ++ * DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nak_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "NAK Received--\n", _hc->hc_num); ++ ++ /* ++ * Handle NAK for IN/OUT SSPLIT/CSPLIT transfers, bulk, control, and ++ * interrupt. Re-start the SSPLIT transfer. ++ */ ++ if (_hc->do_split) { ++ if (_hc->complete_split) { ++ _qtd->error_count = 0; ++ } ++ _qtd->complete_split = 0; ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); ++ goto handle_nak_done; ++ } ++ ++ switch (usb_pipetype(_qtd->urb->pipe)) { ++ case PIPE_CONTROL: ++ case PIPE_BULK: ++ if (_hcd->core_if->dma_enable && _hc->ep_is_in) { ++ /* ++ * NAK interrupts are enabled on bulk/control IN ++ * transfers in DMA mode for the sole purpose of ++ * resetting the error count after a transaction error ++ * occurs. The core will continue transferring data. ++ */ ++ _qtd->error_count = 0; ++ goto handle_nak_done; ++ } ++ ++ /* ++ * NAK interrupts normally occur during OUT transfers in DMA ++ * or Slave mode. For IN transfers, more requests will be ++ * queued as request queue space is available. ++ */ ++ _qtd->error_count = 0; ++ ++ if (!_hc->qh->ping_state) { ++ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, ++ _qtd, DWC_OTG_HC_XFER_NAK); ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ if (_qtd->urb->dev->speed == USB_SPEED_HIGH) { ++ _hc->qh->ping_state = 1; ++ } ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will ++ * start/continue. ++ */ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); ++ break; ++ case PIPE_INTERRUPT: ++ _qtd->error_count = 0; ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NAK, must_free); ++ break; ++ case PIPE_ISOCHRONOUS: ++ /* Should never get called for isochronous transfers. */ ++ BUG(); ++ break; ++ } ++ ++ handle_nak_done: ++ disable_hc_int(_hc_regs,nak); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel ACK interrupt. This interrupt is enabled when ++ * performing the PING protocol in Slave mode, when errors occur during ++ * either Slave mode or DMA mode, and during Start Split transactions. ++ */ ++static int32_t handle_hc_ack_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "ACK Received--\n", _hc->hc_num); ++ ++ if (_hc->do_split) { ++ /* ++ * Handle ACK on SSPLIT. ++ * ACK should not occur in CSPLIT. ++ */ ++ if ((!_hc->ep_is_in) && (_hc->data_pid_start != DWC_OTG_HC_PID_SETUP)) { ++ _qtd->ssplit_out_xfer_count = _hc->xfer_len; ++ } ++ if (!(_hc->ep_type == DWC_OTG_EP_TYPE_ISOC && !_hc->ep_is_in)) { ++ /* Don't need complete for isochronous out transfers. */ ++ _qtd->complete_split = 1; ++ } ++ ++ /* ISOC OUT */ ++ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && !_hc->ep_is_in) { ++ switch (_hc->xact_pos) { ++ case DWC_HCSPLIT_XACTPOS_ALL: ++ break; ++ case DWC_HCSPLIT_XACTPOS_END: ++ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ _qtd->isoc_split_offset = 0; ++ break; ++ case DWC_HCSPLIT_XACTPOS_BEGIN: ++ case DWC_HCSPLIT_XACTPOS_MID: ++ /* ++ * For BEGIN or MID, calculate the length for ++ * the next microframe to determine the correct ++ * SSPLIT token, either MID or END. ++ */ ++ do { ++ struct usb_iso_packet_descriptor *frame_desc; ++ ++ frame_desc = &_qtd->urb->iso_frame_desc[_qtd->isoc_frame_index]; ++ _qtd->isoc_split_offset += 188; ++ ++ if ((frame_desc->length - _qtd->isoc_split_offset) <= 188) { ++ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_END; ++ } ++ else { ++ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_MID; ++ } ++ ++ } while(0); ++ break; ++ } ++ } else { ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); ++ } ++ } else { ++ _qtd->error_count = 0; ++ ++ if (_hc->qh->ping_state) { ++ _hc->qh->ping_state = 0; ++ /* ++ * Halt the channel so the transfer can be re-started ++ * from the appropriate point. This only happens in ++ * Slave mode. In DMA mode, the ping_state is cleared ++ * when the transfer is started because the core ++ * automatically executes the PING, then the transfer. ++ */ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_ACK, must_free); ++ } else { ++ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ } ++ } ++ ++ /* ++ * If the ACK occurred when _not_ in the PING state, let the channel ++ * continue transferring data after clearing the error count. ++ */ ++ ++ disable_hc_int(_hc_regs,ack); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel NYET interrupt. This interrupt should only occur on ++ * Bulk and Control OUT endpoints and for complete split transactions. If a ++ * NYET occurs at the same time as a Transfer Complete interrupt, it is ++ * handled in the xfercomp interrupt handler, not here. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_nyet_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "NYET Received--\n", _hc->hc_num); ++ ++ /* ++ * NYET on CSPLIT ++ * re-do the CSPLIT immediately on non-periodic ++ */ ++ if ((_hc->do_split) && (_hc->complete_split)) { ++ if ((_hc->ep_type == DWC_OTG_EP_TYPE_INTR) || ++ (_hc->ep_type == DWC_OTG_EP_TYPE_ISOC)) { ++ int frnum = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); ++ ++ if (dwc_full_frame_num(frnum) != ++ dwc_full_frame_num(_hc->qh->sched_frame)) { ++ /* ++ * No longer in the same full speed frame. ++ * Treat this as a transaction error. ++ */ ++#if 0 ++ /** @todo Fix system performance so this can ++ * be treated as an error. Right now complete ++ * splits cannot be scheduled precisely enough ++ * due to other system activity, so this error ++ * occurs regularly in Slave mode. ++ */ ++ _qtd->error_count++; ++#endif ++ _qtd->complete_split = 0; ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); ++ /** @todo add support for isoc release */ ++ goto handle_nyet_done; ++ } ++ } ++ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); ++ goto handle_nyet_done; ++ } ++ ++ _hc->qh->ping_state = 1; ++ _qtd->error_count = 0; ++ ++ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, _qtd, ++ DWC_OTG_HC_XFER_NYET); ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ ++ /* ++ * Halt the channel and re-start the transfer so the PING ++ * protocol will start. ++ */ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_NYET, must_free); ++ ++handle_nyet_done: ++ disable_hc_int(_hc_regs,nyet); ++ clear_hc_int(_hc_regs, nyet); ++ return 1; ++} ++ ++/** ++ * Handles a host channel babble interrupt. This handler may be called in ++ * either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_babble_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Babble Error--\n", _hc->hc_num); ++ if (_hc->ep_type != DWC_OTG_EP_TYPE_ISOC) { ++ dwc_otg_hcd_complete_urb(_hcd, _qtd->urb, -EOVERFLOW); ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_BABBLE_ERR, must_free); ++ } else { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_BABBLE_ERR); ++ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); ++ } ++ disable_hc_int(_hc_regs,bblerr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel AHB error interrupt. This handler is only called in ++ * DMA mode. ++ */ ++static int32_t handle_hc_ahberr_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t *_hc, ++ dwc_otg_hc_regs_t *_hc_regs, ++ dwc_otg_qtd_t *_qtd) ++{ ++ hcchar_data_t hcchar; ++ hcsplt_data_t hcsplt; ++ hctsiz_data_t hctsiz; ++ uint32_t hcdma; ++ struct urb *urb = _qtd->urb; ++ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "AHB Error--\n", _hc->hc_num); ++ ++ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); ++ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ hcdma = dwc_read_reg32(&_hc_regs->hcdma); ++ ++ DWC_ERROR("AHB ERROR, Channel %d\n", _hc->hc_num); ++ DWC_ERROR(" hcchar 0x%08x, hcsplt 0x%08x\n", hcchar.d32, hcsplt.d32); ++ DWC_ERROR(" hctsiz 0x%08x, hcdma 0x%08x\n", hctsiz.d32, hcdma); ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD URB Enqueue\n"); ++ DWC_ERROR(" Device address: %d\n", usb_pipedevice(urb->pipe)); ++ DWC_ERROR(" Endpoint: %d, %s\n", usb_pipeendpoint(urb->pipe), ++ (usb_pipein(urb->pipe) ? "IN" : "OUT")); ++ DWC_ERROR(" Endpoint type: %s\n", ++ ({char *pipetype; ++ switch (usb_pipetype(urb->pipe)) { ++ case PIPE_CONTROL: pipetype = "CONTROL"; break; ++ case PIPE_BULK: pipetype = "BULK"; break; ++ case PIPE_INTERRUPT: pipetype = "INTERRUPT"; break; ++ case PIPE_ISOCHRONOUS: pipetype = "ISOCHRONOUS"; break; ++ default: pipetype = "UNKNOWN"; break; ++ }; pipetype;})); ++ DWC_ERROR(" Speed: %s\n", ++ ({char *speed; ++ switch (urb->dev->speed) { ++ case USB_SPEED_HIGH: speed = "HIGH"; break; ++ case USB_SPEED_FULL: speed = "FULL"; break; ++ case USB_SPEED_LOW: speed = "LOW"; break; ++ default: speed = "UNKNOWN"; break; ++ }; speed;})); ++ DWC_ERROR(" Max packet size: %d\n", ++ usb_maxpacket(urb->dev, urb->pipe, usb_pipeout(urb->pipe))); ++ DWC_ERROR(" Data buffer length: %d\n", urb->transfer_buffer_length); ++ DWC_ERROR(" Transfer buffer: %p, Transfer DMA: %p\n", ++ urb->transfer_buffer, (void *)(u32)urb->transfer_dma); ++ DWC_ERROR(" Setup buffer: %p, Setup DMA: %p\n", ++ urb->setup_packet, (void *)(u32)urb->setup_dma); ++ DWC_ERROR(" Interval: %d\n", urb->interval); ++ ++ dwc_otg_hcd_complete_urb(_hcd, urb, -EIO); ++ ++ /* ++ * Force a channel halt. Don't call halt_channel because that won't ++ * write to the HCCHARn register in DMA mode to force the halt. ++ */ ++ dwc_otg_hc_halt(_hcd->core_if, _hc, DWC_OTG_HC_XFER_AHB_ERR); ++ ++ disable_hc_int(_hc_regs,ahberr); ++ return 1; ++} ++ ++/** ++ * Handles a host channel transaction error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_xacterr_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Transaction Error--\n", _hc->hc_num); ++ ++ switch (usb_pipetype(_qtd->urb->pipe)) { ++ case PIPE_CONTROL: ++ case PIPE_BULK: ++ _qtd->error_count++; ++ if (!_hc->qh->ping_state) { ++ update_urb_state_xfer_intr(_hc, _hc_regs, _qtd->urb, ++ _qtd, DWC_OTG_HC_XFER_XACT_ERR); ++ save_data_toggle(_hc, _hc_regs, _qtd); ++ if (!_hc->ep_is_in && _qtd->urb->dev->speed == USB_SPEED_HIGH) { ++ _hc->qh->ping_state = 1; ++ } ++ } ++ ++ /* ++ * Halt the channel so the transfer can be re-started from ++ * the appropriate point or the PING protocol will start. ++ */ ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); ++ break; ++ case PIPE_INTERRUPT: ++ _qtd->error_count++; ++ if ((_hc->do_split) && (_hc->complete_split)) { ++ _qtd->complete_split = 0; ++ } ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_XACT_ERR, must_free); ++ break; ++ case PIPE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_XACT_ERR); ++ ++ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); ++ } ++ break; ++ } ++ ++ ++ disable_hc_int(_hc_regs,xacterr); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel frame overrun interrupt. This handler may be called ++ * in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_frmovrun_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Frame Overrun--\n", _hc->hc_num); ++ ++ switch (usb_pipetype(_qtd->urb->pipe)) { ++ case PIPE_CONTROL: ++ case PIPE_BULK: ++ break; ++ case PIPE_INTERRUPT: ++ halt_channel(_hcd, _hc, _qtd, DWC_OTG_HC_XFER_FRAME_OVERRUN, must_free); ++ break; ++ case PIPE_ISOCHRONOUS: ++ { ++ dwc_otg_halt_status_e halt_status; ++ halt_status = update_isoc_urb_state(_hcd, _hc, _hc_regs, _qtd, ++ DWC_OTG_HC_XFER_FRAME_OVERRUN); ++ ++ halt_channel(_hcd, _hc, _qtd, halt_status, must_free); ++ } ++ break; ++ } ++ ++ disable_hc_int(_hc_regs,frmovrun); ++ ++ return 1; ++} ++ ++/** ++ * Handles a host channel data toggle error interrupt. This handler may be ++ * called in either DMA mode or Slave mode. ++ */ ++static int32_t handle_hc_datatglerr_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Data Toggle Error--\n", _hc->hc_num); ++ ++ if (_hc->ep_is_in) { ++ _qtd->error_count = 0; ++ } else { ++ DWC_ERROR("Data Toggle Error on OUT transfer," ++ "channel %d\n", _hc->hc_num); ++ } ++ ++ disable_hc_int(_hc_regs,datatglerr); ++ ++ return 1; ++} ++ ++#ifdef DEBUG ++/** ++ * This function is for debug only. It checks that a valid halt status is set ++ * and that HCCHARn.chdis is clear. If there's a problem, corrective action is ++ * taken and a warning is issued. ++ * @return 1 if halt status is ok, 0 otherwise. ++ */ ++static inline int halt_status_ok(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ hcchar_data_t hcchar; ++ hctsiz_data_t hctsiz; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ hcsplt_data_t hcsplt; ++ ++ if (_hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS) { ++ /* ++ * This code is here only as a check. This condition should ++ * never happen. Ignore the halt if it does occur. ++ */ ++ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); ++ hctsiz.d32 = dwc_read_reg32(&_hc_regs->hctsiz); ++ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); ++ hcsplt.d32 = dwc_read_reg32(&_hc_regs->hcsplt); ++ DWC_WARN("%s: _hc->halt_status == DWC_OTG_HC_XFER_NO_HALT_STATUS, " ++ "channel %d, hcchar 0x%08x, hctsiz 0x%08x, " ++ "hcint 0x%08x, hcintmsk 0x%08x, " ++ "hcsplt 0x%08x, qtd->complete_split %d\n", ++ __func__, _hc->hc_num, hcchar.d32, hctsiz.d32, ++ hcint.d32, hcintmsk.d32, ++ hcsplt.d32, _qtd->complete_split); ++ ++ DWC_WARN("%s: no halt status, channel %d, ignoring interrupt\n", ++ __func__, _hc->hc_num); ++ DWC_WARN("\n"); ++ clear_hc_int(_hc_regs,chhltd); ++ return 0; ++ } ++ ++ /* ++ * This code is here only as a check. hcchar.chdis should ++ * never be set when the halt interrupt occurs. Halt the ++ * channel again if it does occur. ++ */ ++ hcchar.d32 = dwc_read_reg32(&_hc_regs->hcchar); ++ if (hcchar.b.chdis) { ++ DWC_WARN("%s: hcchar.chdis set unexpectedly, " ++ "hcchar 0x%08x, trying to halt again\n", ++ __func__, hcchar.d32); ++ clear_hc_int(_hc_regs,chhltd); ++ _hc->halt_pending = 0; ++ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ return 0; ++ } ++ ++ return 1; ++} ++#endif ++ ++/** ++ * Handles a host Channel Halted interrupt in DMA mode. This handler ++ * determines the reason the channel halted and proceeds accordingly. ++ */ ++static void handle_hc_chhltd_intr_dma(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ ++ if (_hc->halt_status == DWC_OTG_HC_XFER_URB_DEQUEUE || ++ _hc->halt_status == DWC_OTG_HC_XFER_AHB_ERR) { ++ /* ++ * Just release the channel. A dequeue can happen on a ++ * transfer timeout. In the case of an AHB Error, the channel ++ * was forced to halt because there's no way to gracefully ++ * recover. ++ */ ++ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ return; ++ } ++ ++ /* Read the HCINTn register to determine the cause for the halt. */ ++ hcint.d32 = dwc_read_reg32(&_hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&_hc_regs->hcintmsk); ++ ++ if (hcint.b.xfercomp) { ++ /** @todo This is here because of a possible hardware bug. Spec ++ * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT ++ * interrupt w/ACK bit set should occur, but I only see the ++ * XFERCOMP bit, even with it masked out. This is a workaround ++ * for that behavior. Should fix this when hardware is fixed. ++ */ ++ if ((_hc->ep_type == DWC_OTG_EP_TYPE_ISOC) && (!_hc->ep_is_in)) { ++ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } ++ handle_hc_xfercomp_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.stall) { ++ handle_hc_stall_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.xacterr) { ++ /* ++ * Must handle xacterr before nak or ack. Could get a xacterr ++ * at the same time as either of these on a BULK/CONTROL OUT ++ * that started with a PING. The xacterr takes precedence. ++ */ ++ handle_hc_xacterr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.nyet) { ++ /* ++ * Must handle nyet before nak or ack. Could get a nyet at the ++ * same time as either of those on a BULK/CONTROL OUT that ++ * started with a PING. The nyet takes precedence. ++ */ ++ handle_hc_nyet_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.bblerr) { ++ handle_hc_babble_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.frmovrun) { ++ handle_hc_frmovrun_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.datatglerr) { ++ handle_hc_datatglerr_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ _hc->qh->data_toggle = 0; ++ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ } else if (hcint.b.nak && !hcintmsk.b.nak) { ++ /* ++ * If nak is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the nak is handled by ++ * the nak interrupt handler, not here. Handle nak here for ++ * BULK/CONTROL OUT transfers, which halt on a NAK to allow ++ * rewinding the buffer pointer. ++ */ ++ handle_hc_nak_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else if (hcint.b.ack && !hcintmsk.b.ack) { ++ /* ++ * If ack is not masked, it's because a non-split IN transfer ++ * is in an error state. In that case, the ack is handled by ++ * the ack interrupt handler, not here. Handle ack here for ++ * split transfers. Start splits halt on ACK. ++ */ ++ handle_hc_ack_intr(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else { ++ if (_hc->ep_type == DWC_OTG_EP_TYPE_INTR || ++ _hc->ep_type == DWC_OTG_EP_TYPE_ISOC) { ++ /* ++ * A periodic transfer halted with no other channel ++ * interrupts set. Assume it was halted by the core ++ * because it could not be completed in its scheduled ++ * (micro)frame. ++ */ ++#ifdef DEBUG ++ DWC_PRINT("%s: Halt channel %d (assume incomplete periodic transfer)\n", ++ __func__, _hc->hc_num); ++#endif /* */ ++ halt_channel(_hcd, _hc, _qtd, ++ DWC_OTG_HC_XFER_PERIODIC_INCOMPLETE, must_free); ++ } else { ++#ifdef DEBUG ++ DWC_ERROR("%s: Channel %d, DMA Mode -- ChHltd set, but reason " ++ "for halting is unknown, nyet %d, hcint 0x%08x, intsts 0x%08x\n", ++ __func__, _hc->hc_num, hcint.b.nyet, hcint.d32, ++ dwc_read_reg32(&_hcd->core_if->core_global_regs->gintsts)); ++#endif ++ halt_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ } ++ } ++} ++ ++/** ++ * Handles a host channel Channel Halted interrupt. ++ * ++ * In slave mode, this handler is called only when the driver specifically ++ * requests a halt. This occurs during handling other host channel interrupts ++ * (e.g. nak, xacterr, stall, nyet, etc.). ++ * ++ * In DMA mode, this is the interrupt that occurs when the core has finished ++ * processing a transfer on a channel. Other host channel interrupts (except ++ * ahberr) are disabled in DMA mode. ++ */ ++static int32_t handle_hc_chhltd_intr(dwc_otg_hcd_t *_hcd, ++ dwc_hc_t * _hc, dwc_otg_hc_regs_t * _hc_regs, dwc_otg_qtd_t * _qtd, int *must_free) ++{ ++ DWC_DEBUGPL(DBG_HCD, "--Host Channel %d Interrupt: " ++ "Channel Halted--\n", _hc->hc_num); ++ ++ if (_hcd->core_if->dma_enable) { ++ handle_hc_chhltd_intr_dma(_hcd, _hc, _hc_regs, _qtd, must_free); ++ } else { ++#ifdef DEBUG ++ if (!halt_status_ok(_hcd, _hc, _hc_regs, _qtd, must_free)) { ++ return 1; ++ } ++#endif /* */ ++ release_channel(_hcd, _hc, _qtd, _hc->halt_status, must_free); ++ } ++ ++ return 1; ++} ++ ++/** Handles interrupt for a specific Host Channel */ ++int32_t dwc_otg_hcd_handle_hc_n_intr (dwc_otg_hcd_t *_dwc_otg_hcd, uint32_t _num) ++{ ++ int must_free = 0; ++ int retval = 0; ++ hcint_data_t hcint; ++ hcintmsk_data_t hcintmsk; ++ dwc_hc_t *hc; ++ dwc_otg_hc_regs_t *hc_regs; ++ dwc_otg_qtd_t *qtd; ++ ++ DWC_DEBUGPL(DBG_HCDV, "--Host Channel Interrupt--, Channel %d\n", _num); ++ ++ hc = _dwc_otg_hcd->hc_ptr_array[_num]; ++ hc_regs = _dwc_otg_hcd->core_if->host_if->hc_regs[_num]; ++ qtd = list_entry(hc->qh->qtd_list.next, dwc_otg_qtd_t, qtd_list_entry); ++ ++ hcint.d32 = dwc_read_reg32(&hc_regs->hcint); ++ hcintmsk.d32 = dwc_read_reg32(&hc_regs->hcintmsk); ++ DWC_DEBUGPL(DBG_HCDV, " hcint 0x%08x, hcintmsk 0x%08x, hcint&hcintmsk 0x%08x\n", ++ hcint.d32, hcintmsk.d32, (hcint.d32 & hcintmsk.d32)); ++ hcint.d32 = hcint.d32 & hcintmsk.d32; ++ ++ if (!_dwc_otg_hcd->core_if->dma_enable) { ++ if ((hcint.b.chhltd) && (hcint.d32 != 0x2)) { ++ hcint.b.chhltd = 0; ++ } ++ } ++ ++ if (hcint.b.xfercomp) { ++ retval |= handle_hc_xfercomp_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ /* ++ * If NYET occurred at same time as Xfer Complete, the NYET is ++ * handled by the Xfer Complete interrupt handler. Don't want ++ * to call the NYET interrupt handler in this case. ++ */ ++ hcint.b.nyet = 0; ++ } ++ if (hcint.b.chhltd) { ++ retval |= handle_hc_chhltd_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.ahberr) { ++ retval |= handle_hc_ahberr_intr(_dwc_otg_hcd, hc, hc_regs, qtd); ++ } ++ if (hcint.b.stall) { ++ retval |= handle_hc_stall_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.nak) { ++ retval |= handle_hc_nak_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.ack) { ++ retval |= handle_hc_ack_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.nyet) { ++ retval |= handle_hc_nyet_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.xacterr) { ++ retval |= handle_hc_xacterr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.bblerr) { ++ retval |= handle_hc_babble_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.frmovrun) { ++ retval |= handle_hc_frmovrun_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ if (hcint.b.datatglerr) { ++ retval |= handle_hc_datatglerr_intr(_dwc_otg_hcd, hc, hc_regs, qtd, &must_free); ++ } ++ ++ /* ++ * Logic to free the qtd here, at the end of the hc intr ++ * processing, if the handling of this interrupt determined ++ * that it needs to be freed. ++ */ ++ if (must_free) { ++ /* Free the qtd here now that we are done using it. */ ++ dwc_otg_hcd_qtd_free(qtd); ++ } ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_hcd_queue.c +@@ -0,0 +1,794 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_hcd_queue.c $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 537387 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++#ifndef DWC_DEVICE_ONLY ++ ++/** ++ * @file ++ * ++ * This file contains the functions to manage Queue Heads and Queue ++ * Transfer Descriptors. ++ */ ++#include <linux/kernel.h> ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/init.h> ++#include <linux/device.h> ++#include <linux/errno.h> ++#include <linux/list.h> ++#include <linux/interrupt.h> ++#include <linux/string.h> ++ ++#include "dwc_otg_driver.h" ++#include "dwc_otg_hcd.h" ++#include "dwc_otg_regs.h" ++ ++/** ++ * This function allocates and initializes a QH. ++ * ++ * @param _hcd The HCD state structure for the DWC OTG controller. ++ * @param[in] _urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. ++ * ++ * @return Returns pointer to the newly allocated QH, or NULL on error. */ ++dwc_otg_qh_t *dwc_otg_hcd_qh_create (dwc_otg_hcd_t *_hcd, struct urb *_urb) ++{ ++ dwc_otg_qh_t *qh; ++ ++ /* Allocate memory */ ++ /** @todo add memflags argument */ ++ qh = dwc_otg_hcd_qh_alloc (); ++ if (qh == NULL) { ++ return NULL; ++ } ++ ++ dwc_otg_hcd_qh_init (_hcd, qh, _urb); ++ return qh; ++} ++ ++/** Free each QTD in the QH's QTD-list then free the QH. QH should already be ++ * removed from a list. QTD list should already be empty if called from URB ++ * Dequeue. ++ * ++ * @param[in] _qh The QH to free. ++ */ ++void dwc_otg_hcd_qh_free (dwc_otg_qh_t *_qh) ++{ ++ dwc_otg_qtd_t *qtd; ++ struct list_head *pos; ++ unsigned long flags; ++ ++ /* Free each QTD in the QTD list */ ++ local_irq_save (flags); ++ for (pos = _qh->qtd_list.next; ++ pos != &_qh->qtd_list; ++ pos = _qh->qtd_list.next) ++ { ++ list_del (pos); ++ qtd = dwc_list_to_qtd (pos); ++ dwc_otg_hcd_qtd_free (qtd); ++ } ++ local_irq_restore (flags); ++ ++ kfree (_qh); ++ return; ++} ++ ++/** Initializes a QH structure. ++ * ++ * @param[in] _hcd The HCD state structure for the DWC OTG controller. ++ * @param[in] _qh The QH to init. ++ * @param[in] _urb Holds the information about the device/endpoint that we need ++ * to initialize the QH. */ ++#define SCHEDULE_SLOP 10 ++void dwc_otg_hcd_qh_init(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, struct urb *_urb) ++{ ++ memset (_qh, 0, sizeof (dwc_otg_qh_t)); ++ ++ /* Initialize QH */ ++ switch (usb_pipetype(_urb->pipe)) { ++ case PIPE_CONTROL: ++ _qh->ep_type = USB_ENDPOINT_XFER_CONTROL; ++ break; ++ case PIPE_BULK: ++ _qh->ep_type = USB_ENDPOINT_XFER_BULK; ++ break; ++ case PIPE_ISOCHRONOUS: ++ _qh->ep_type = USB_ENDPOINT_XFER_ISOC; ++ break; ++ case PIPE_INTERRUPT: ++ _qh->ep_type = USB_ENDPOINT_XFER_INT; ++ break; ++ } ++ ++ _qh->ep_is_in = usb_pipein(_urb->pipe) ? 1 : 0; ++ ++ _qh->data_toggle = DWC_OTG_HC_PID_DATA0; ++ _qh->maxp = usb_maxpacket(_urb->dev, _urb->pipe, !(usb_pipein(_urb->pipe))); ++ INIT_LIST_HEAD(&_qh->qtd_list); ++ INIT_LIST_HEAD(&_qh->qh_list_entry); ++ _qh->channel = NULL; ++ ++ /* FS/LS Enpoint on HS Hub ++ * NOT virtual root hub */ ++ _qh->do_split = 0; ++ _qh->speed = _urb->dev->speed; ++ if (((_urb->dev->speed == USB_SPEED_LOW) || ++ (_urb->dev->speed == USB_SPEED_FULL)) && ++ (_urb->dev->tt) && (_urb->dev->tt->hub) && (_urb->dev->tt->hub->devnum != 1)) { ++ DWC_DEBUGPL(DBG_HCD, "QH init: EP %d: TT found at hub addr %d, for port %d\n", ++ usb_pipeendpoint(_urb->pipe), _urb->dev->tt->hub->devnum, ++ _urb->dev->ttport); ++ _qh->do_split = 1; ++ } ++ ++ if (_qh->ep_type == USB_ENDPOINT_XFER_INT || ++ _qh->ep_type == USB_ENDPOINT_XFER_ISOC) { ++ /* Compute scheduling parameters once and save them. */ ++ hprt0_data_t hprt; ++ ++ /** @todo Account for split transfers in the bus time. */ ++ int bytecount = dwc_hb_mult(_qh->maxp) * dwc_max_packet(_qh->maxp); ++ _qh->usecs = NS_TO_US(usb_calc_bus_time(_urb->dev->speed, ++ usb_pipein(_urb->pipe), ++ (_qh->ep_type == USB_ENDPOINT_XFER_ISOC),bytecount)); ++ ++ /* Start in a slightly future (micro)frame. */ ++ _qh->sched_frame = dwc_frame_num_inc(_hcd->frame_number, SCHEDULE_SLOP); ++ _qh->interval = _urb->interval; ++#if 0 ++ /* Increase interrupt polling rate for debugging. */ ++ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { ++ _qh->interval = 8; ++ } ++#endif ++ hprt.d32 = dwc_read_reg32(_hcd->core_if->host_if->hprt0); ++ if ((hprt.b.prtspd == DWC_HPRT0_PRTSPD_HIGH_SPEED) && ++ ((_urb->dev->speed == USB_SPEED_LOW) || ++ (_urb->dev->speed == USB_SPEED_FULL))) ++ { ++ _qh->interval *= 8; ++ _qh->sched_frame |= 0x7; ++ _qh->start_split_frame = _qh->sched_frame; ++ } ++ } ++ ++ DWC_DEBUGPL(DBG_HCD, "DWC OTG HCD QH Initialized\n"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - qh = %p\n", _qh); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Device Address = %d\n", ++ _urb->dev->devnum); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Endpoint %d, %s\n", ++ usb_pipeendpoint(_urb->pipe), ++ usb_pipein(_urb->pipe) == USB_DIR_IN ? "IN" : "OUT"); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Speed = %s\n", ++ ({ char *speed; switch (_urb->dev->speed) { ++ case USB_SPEED_LOW: speed = "low"; break; ++ case USB_SPEED_FULL: speed = "full"; break; ++ case USB_SPEED_HIGH: speed = "high"; break; ++ default: speed = "?"; break; ++ }; speed;})); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - Type = %s\n", ++ ({ char *type; switch (_qh->ep_type) { ++ case USB_ENDPOINT_XFER_ISOC: type = "isochronous"; break; ++ case USB_ENDPOINT_XFER_INT: type = "interrupt"; break; ++ case USB_ENDPOINT_XFER_CONTROL: type = "control"; break; ++ case USB_ENDPOINT_XFER_BULK: type = "bulk"; break; ++ default: type = "?"; break; ++ }; type;})); ++#ifdef DEBUG ++ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - usecs = %d\n", ++ _qh->usecs); ++ DWC_DEBUGPL(DBG_HCDV, "DWC OTG HCD QH - interval = %d\n", ++ _qh->interval); ++ } ++#endif ++ ++ return; ++} ++ ++/** ++ * Microframe scheduler ++ * track the total use in hcd->frame_usecs ++ * keep each qh use in qh->frame_usecs ++ * when surrendering the qh then donate the time back ++ */ ++const unsigned short max_uframe_usecs[]={ 100, 100, 100, 100, 100, 100, 30, 0 }; ++ ++/* ++ * called from dwc_otg_hcd.c:dwc_otg_hcd_init ++ */ ++int init_hcd_usecs(dwc_otg_hcd_t *_hcd) ++{ ++ int i; ++ for (i=0; i<8; i++) { ++ _hcd->frame_usecs[i] = max_uframe_usecs[i]; ++ } ++ return 0; ++} ++ ++static int find_single_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++ while (done == 0) { ++ /* At the start _hcd->frame_usecs[i] = max_uframe_usecs[i]; */ ++ if (utime <= _hcd->frame_usecs[i]) { ++ _hcd->frame_usecs[i] -= utime; ++ _qh->frame_usecs[i] += utime; ++ t_left -= utime; ++ ret = i; ++ done = 1; ++ return ret; ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++} ++ ++/* ++ * use this for FS apps that can span multiple uframes ++ */ ++static int find_multi_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int i; ++ int j; ++ unsigned short utime; ++ int t_left; ++ int ret; ++ int done; ++ unsigned short xtime; ++ ++ ret = -1; ++ utime = _qh->usecs; ++ t_left = utime; ++ i = 0; ++ done = 0; ++loop: ++ while (done == 0) { ++ if(_hcd->frame_usecs[i] <= 0) { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ goto loop; ++ } ++ ++ /* ++ * we need n consequtive slots ++ * so use j as a start slot j plus j+1 must be enough time (for now) ++ */ ++ xtime= _hcd->frame_usecs[i]; ++ for (j = i+1 ; j < 8 ; j++ ) { ++ /* ++ * if we add this frame remaining time to xtime we may ++ * be OK, if not we need to test j for a complete frame ++ */ ++ if ((xtime+_hcd->frame_usecs[j]) < utime) { ++ if (_hcd->frame_usecs[j] < max_uframe_usecs[j]) { ++ j = 8; ++ ret = -1; ++ continue; ++ } ++ } ++ if (xtime >= utime) { ++ ret = i; ++ j = 8; /* stop loop with a good value ret */ ++ continue; ++ } ++ /* add the frame time to x time */ ++ xtime += _hcd->frame_usecs[j]; ++ /* we must have a fully available next frame or break */ ++ if ((xtime < utime) ++ && (_hcd->frame_usecs[j] == max_uframe_usecs[j])) { ++ ret = -1; ++ j = 8; /* stop loop with a bad value ret */ ++ continue; ++ } ++ } ++ if (ret >= 0) { ++ t_left = utime; ++ for (j = i; (t_left>0) && (j < 8); j++ ) { ++ t_left -= _hcd->frame_usecs[j]; ++ if ( t_left <= 0 ) { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j] + t_left; ++ _hcd->frame_usecs[j]= -t_left; ++ ret = i; ++ done = 1; ++ } else { ++ _qh->frame_usecs[j] += _hcd->frame_usecs[j]; ++ _hcd->frame_usecs[j] = 0; ++ } ++ } ++ } else { ++ i++; ++ if (i == 8) { ++ done = 1; ++ ret = -1; ++ } ++ } ++ } ++ return ret; ++} ++ ++static int find_uframe(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ int ret; ++ ret = -1; ++ ++ if (_qh->speed == USB_SPEED_HIGH) { ++ /* if this is a hs transaction we need a full frame */ ++ ret = find_single_uframe(_hcd, _qh); ++ } else { ++ /* if this is a fs transaction we may need a sequence of frames */ ++ ret = find_multi_uframe(_hcd, _qh); ++ } ++ return ret; ++} ++ ++/** ++ * Checks that the max transfer size allowed in a host channel is large enough ++ * to handle the maximum data transfer in a single (micro)frame for a periodic ++ * transfer. ++ * ++ * @param _hcd The HCD state structure for the DWC OTG controller. ++ * @param _qh QH for a periodic endpoint. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int check_max_xfer_size(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ int status; ++ uint32_t max_xfer_size; ++ uint32_t max_channel_xfer_size; ++ ++ status = 0; ++ ++ max_xfer_size = dwc_max_packet(_qh->maxp) * dwc_hb_mult(_qh->maxp); ++ max_channel_xfer_size = _hcd->core_if->core_params->max_transfer_size; ++ ++ if (max_xfer_size > max_channel_xfer_size) { ++ DWC_NOTICE("%s: Periodic xfer length %d > " ++ "max xfer length for channel %d\n", ++ __func__, max_xfer_size, max_channel_xfer_size); ++ status = -ENOSPC; ++ } ++ ++ return status; ++} ++ ++/** ++ * Schedules an interrupt or isochronous transfer in the periodic schedule. ++ * ++ * @param _hcd The HCD state structure for the DWC OTG controller. ++ * @param _qh QH for the periodic transfer. The QH should already contain the ++ * scheduling information. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++static int schedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ int status = 0; ++ ++ int frame; ++ status = find_uframe(_hcd, _qh); ++ frame = -1; ++ if (status == 0) { ++ frame = 7; ++ } else { ++ if (status > 0 ) ++ frame = status-1; ++ } ++ ++ /* Set the new frame up */ ++ if (frame > -1) { ++ _qh->sched_frame &= ~0x7; ++ _qh->sched_frame |= (frame & 7); ++ } ++ ++ if (status != -1 ) ++ status = 0; ++ if (status) { ++ DWC_NOTICE("%s: Insufficient periodic bandwidth for " ++ "periodic transfer.\n", __func__); ++ return status; ++ } ++ ++ status = check_max_xfer_size(_hcd, _qh); ++ if (status) { ++ DWC_NOTICE("%s: Channel max transfer size too small " ++ "for periodic transfer.\n", __func__); ++ return status; ++ } ++ ++ /* Always start in the inactive schedule. */ ++ list_add_tail(&_qh->qh_list_entry, &_hcd->periodic_sched_inactive); ++ ++ ++ /* Update claimed usecs per (micro)frame. */ ++ _hcd->periodic_usecs += _qh->usecs; ++ ++ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated += _qh->usecs / _qh->interval; ++ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs++; ++ DWC_DEBUGPL(DBG_HCD, "Scheduled intr: qh %p, usecs %d, period %d\n", ++ _qh, _qh->usecs, _qh->interval); ++ } else { ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs++; ++ DWC_DEBUGPL(DBG_HCD, "Scheduled isoc: qh %p, usecs %d, period %d\n", ++ _qh, _qh->usecs, _qh->interval); ++ } ++ ++ return status; ++} ++ ++/** ++ * This function adds a QH to either the non periodic or periodic schedule if ++ * it is not already in the schedule. If the QH is already in the schedule, no ++ * action is taken. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_add (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ unsigned long flags; ++ int status = 0; ++ ++ local_irq_save(flags); ++ ++ if (!list_empty(&_qh->qh_list_entry)) { ++ /* QH already in a schedule. */ ++ goto done; ++ } ++ ++ /* Add the new QH to the appropriate schedule */ ++ if (dwc_qh_is_non_per(_qh)) { ++ /* Always start in the inactive schedule. */ ++ list_add_tail(&_qh->qh_list_entry, &_hcd->non_periodic_sched_inactive); ++ } else { ++ status = schedule_periodic(_hcd, _qh); ++ } ++ ++ done: ++ local_irq_restore(flags); ++ ++ return status; ++} ++ ++/** ++ * This function adds a QH to the non periodic deferred schedule. ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qh_add_deferred(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh) ++{ ++ unsigned long flags; ++ local_irq_save(flags); ++ if (!list_empty(&_qh->qh_list_entry)) { ++ /* QH already in a schedule. */ ++ goto done; ++ } ++ ++ /* Add the new QH to the non periodic deferred schedule */ ++ if (dwc_qh_is_non_per(_qh)) { ++ list_add_tail(&_qh->qh_list_entry, ++ &_hcd->non_periodic_sched_deferred); ++ } ++done: ++ local_irq_restore(flags); ++ return 0; ++} ++ ++/** ++ * Removes an interrupt or isochronous transfer from the periodic schedule. ++ * ++ * @param _hcd The HCD state structure for the DWC OTG controller. ++ * @param _qh QH for the periodic transfer. ++ */ ++static void deschedule_periodic(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ int i; ++ list_del_init(&_qh->qh_list_entry); ++ ++ ++ /* Update claimed usecs per (micro)frame. */ ++ _hcd->periodic_usecs -= _qh->usecs; ++ ++ for (i = 0; i < 8; i++) { ++ _hcd->frame_usecs[i] += _qh->frame_usecs[i]; ++ _qh->frame_usecs[i] = 0; ++ } ++ /* Update average periodic bandwidth claimed and # periodic reqs for usbfs. */ ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_allocated -= _qh->usecs / _qh->interval; ++ ++ if (_qh->ep_type == USB_ENDPOINT_XFER_INT) { ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_int_reqs--; ++ DWC_DEBUGPL(DBG_HCD, "Descheduled intr: qh %p, usecs %d, period %d\n", ++ _qh, _qh->usecs, _qh->interval); ++ } else { ++ hcd_to_bus(dwc_otg_hcd_to_hcd(_hcd))->bandwidth_isoc_reqs--; ++ DWC_DEBUGPL(DBG_HCD, "Descheduled isoc: qh %p, usecs %d, period %d\n", ++ _qh, _qh->usecs, _qh->interval); ++ } ++} ++ ++/** ++ * Removes a QH from either the non-periodic or periodic schedule. Memory is ++ * not freed. ++ * ++ * @param[in] _hcd The HCD state structure. ++ * @param[in] _qh QH to remove from schedule. */ ++void dwc_otg_hcd_qh_remove (dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh) ++{ ++ unsigned long flags; ++ ++ local_irq_save(flags); ++ ++ if (list_empty(&_qh->qh_list_entry)) { ++ /* QH is not in a schedule. */ ++ goto done; ++ } ++ ++ if (dwc_qh_is_non_per(_qh)) { ++ if (_hcd->non_periodic_qh_ptr == &_qh->qh_list_entry) { ++ _hcd->non_periodic_qh_ptr = _hcd->non_periodic_qh_ptr->next; ++ } ++ list_del_init(&_qh->qh_list_entry); ++ } else { ++ deschedule_periodic(_hcd, _qh); ++ } ++ ++ done: ++ local_irq_restore(flags); ++} ++ ++/** ++ * Defers a QH. For non-periodic QHs, removes the QH from the active ++ * non-periodic schedule. The QH is added to the deferred non-periodic ++ * schedule if any QTDs are still attached to the QH. ++ */ ++int dwc_otg_hcd_qh_deferr(dwc_otg_hcd_t * _hcd, dwc_otg_qh_t * _qh, int delay) ++{ ++ int deact = 1; ++ unsigned long flags; ++ local_irq_save(flags); ++ if (dwc_qh_is_non_per(_qh)) { ++ _qh->sched_frame = ++ dwc_frame_num_inc(_hcd->frame_number, ++ delay); ++ _qh->channel = NULL; ++ _qh->qtd_in_process = NULL; ++ deact = 0; ++ dwc_otg_hcd_qh_remove(_hcd, _qh); ++ if (!list_empty(&_qh->qtd_list)) { ++ /* Add back to deferred non-periodic schedule. */ ++ dwc_otg_hcd_qh_add_deferred(_hcd, _qh); ++ } ++ } ++ local_irq_restore(flags); ++ return deact; ++} ++ ++/** ++ * Deactivates a QH. For non-periodic QHs, removes the QH from the active ++ * non-periodic schedule. The QH is added to the inactive non-periodic ++ * schedule if any QTDs are still attached to the QH. ++ * ++ * For periodic QHs, the QH is removed from the periodic queued schedule. If ++ * there are any QTDs still attached to the QH, the QH is added to either the ++ * periodic inactive schedule or the periodic ready schedule and its next ++ * scheduled frame is calculated. The QH is placed in the ready schedule if ++ * the scheduled frame has been reached already. Otherwise it's placed in the ++ * inactive schedule. If there are no QTDs attached to the QH, the QH is ++ * completely removed from the periodic schedule. ++ */ ++void dwc_otg_hcd_qh_deactivate(dwc_otg_hcd_t *_hcd, dwc_otg_qh_t *_qh, int sched_next_periodic_split) ++{ ++ unsigned long flags; ++ local_irq_save(flags); ++ ++ if (dwc_qh_is_non_per(_qh)) { ++ dwc_otg_hcd_qh_remove(_hcd, _qh); ++ if (!list_empty(&_qh->qtd_list)) { ++ /* Add back to inactive non-periodic schedule. */ ++ dwc_otg_hcd_qh_add(_hcd, _qh); ++ } ++ } else { ++ uint16_t frame_number = dwc_otg_hcd_get_frame_number(dwc_otg_hcd_to_hcd(_hcd)); ++ ++ if (_qh->do_split) { ++ /* Schedule the next continuing periodic split transfer */ ++ if (sched_next_periodic_split) { ++ ++ _qh->sched_frame = frame_number; ++ if (dwc_frame_num_le(frame_number, ++ dwc_frame_num_inc(_qh->start_split_frame, 1))) { ++ /* ++ * Allow one frame to elapse after start ++ * split microframe before scheduling ++ * complete split, but DONT if we are ++ * doing the next start split in the ++ * same frame for an ISOC out. ++ */ ++ if ((_qh->ep_type != USB_ENDPOINT_XFER_ISOC) || (_qh->ep_is_in != 0)) { ++ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, 1); ++ } ++ } ++ } else { ++ _qh->sched_frame = dwc_frame_num_inc(_qh->start_split_frame, ++ _qh->interval); ++ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { ++ _qh->sched_frame = frame_number; ++ } ++ _qh->sched_frame |= 0x7; ++ _qh->start_split_frame = _qh->sched_frame; ++ } ++ } else { ++ _qh->sched_frame = dwc_frame_num_inc(_qh->sched_frame, _qh->interval); ++ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { ++ _qh->sched_frame = frame_number; ++ } ++ } ++ ++ if (list_empty(&_qh->qtd_list)) { ++ dwc_otg_hcd_qh_remove(_hcd, _qh); ++ } else { ++ /* ++ * Remove from periodic_sched_queued and move to ++ * appropriate queue. ++ */ ++ if (dwc_frame_num_le(_qh->sched_frame, frame_number)) { ++ list_move(&_qh->qh_list_entry, ++ &_hcd->periodic_sched_ready); ++ } else { ++ list_move(&_qh->qh_list_entry, ++ &_hcd->periodic_sched_inactive); ++ } ++ } ++ } ++ ++ local_irq_restore(flags); ++} ++ ++/** ++ * This function allocates and initializes a QTD. ++ * ++ * @param[in] _urb The URB to create a QTD from. Each URB-QTD pair will end up ++ * pointing to each other so each pair should have a unique correlation. ++ * ++ * @return Returns pointer to the newly allocated QTD, or NULL on error. */ ++dwc_otg_qtd_t *dwc_otg_hcd_qtd_create (struct urb *_urb) ++{ ++ dwc_otg_qtd_t *qtd; ++ ++ qtd = dwc_otg_hcd_qtd_alloc (); ++ if (qtd == NULL) { ++ return NULL; ++ } ++ ++ dwc_otg_hcd_qtd_init (qtd, _urb); ++ return qtd; ++} ++ ++/** ++ * Initializes a QTD structure. ++ * ++ * @param[in] _qtd The QTD to initialize. ++ * @param[in] _urb The URB to use for initialization. */ ++void dwc_otg_hcd_qtd_init (dwc_otg_qtd_t *_qtd, struct urb *_urb) ++{ ++ memset (_qtd, 0, sizeof (dwc_otg_qtd_t)); ++ _qtd->urb = _urb; ++ if (usb_pipecontrol(_urb->pipe)) { ++ /* ++ * The only time the QTD data toggle is used is on the data ++ * phase of control transfers. This phase always starts with ++ * DATA1. ++ */ ++ _qtd->data_toggle = DWC_OTG_HC_PID_DATA1; ++ _qtd->control_phase = DWC_OTG_CONTROL_SETUP; ++ } ++ ++ /* start split */ ++ _qtd->complete_split = 0; ++ _qtd->isoc_split_pos = DWC_HCSPLIT_XACTPOS_ALL; ++ _qtd->isoc_split_offset = 0; ++ ++ /* Store the qtd ptr in the urb to reference what QTD. */ ++ _urb->hcpriv = _qtd; ++ return; ++} ++ ++/** ++ * This function adds a QTD to the QTD-list of a QH. It will find the correct ++ * QH to place the QTD into. If it does not find a QH, then it will create a ++ * new QH. If the QH to which the QTD is added is not currently scheduled, it ++ * is placed into the proper schedule based on its EP type. ++ * ++ * @param[in] _qtd The QTD to add ++ * @param[in] _dwc_otg_hcd The DWC HCD structure ++ * ++ * @return 0 if successful, negative error code otherwise. ++ */ ++int dwc_otg_hcd_qtd_add(dwc_otg_qtd_t * _qtd, dwc_otg_hcd_t * _dwc_otg_hcd) ++{ ++ struct usb_host_endpoint *ep; ++ dwc_otg_qh_t *qh; ++ unsigned long flags; ++ int retval = 0; ++ struct urb *urb = _qtd->urb; ++ ++ local_irq_save(flags); ++ ++ /* ++ * Get the QH which holds the QTD-list to insert to. Create QH if it ++ * doesn't exist. ++ */ ++ ep = dwc_urb_to_endpoint(urb); ++ qh = (dwc_otg_qh_t *)ep->hcpriv; ++ if (qh == NULL) { ++ qh = dwc_otg_hcd_qh_create (_dwc_otg_hcd, urb); ++ if (qh == NULL) { ++ retval = -1; ++ goto done; ++ } ++ ep->hcpriv = qh; ++ } ++ ++ _qtd->qtd_qh_ptr = qh; ++ retval = dwc_otg_hcd_qh_add(_dwc_otg_hcd, qh); ++ if (retval == 0) { ++ list_add_tail(&_qtd->qtd_list_entry, &qh->qtd_list); ++ } ++ ++ done: ++ local_irq_restore(flags); ++ return retval; ++} ++ ++#endif /* DWC_DEVICE_ONLY */ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_ifx.c +@@ -0,0 +1,100 @@ ++/****************************************************************************** ++** ++** FILE NAME : dwc_otg_ifx.c ++** PROJECT : Twinpass/Danube ++** MODULES : DWC OTG USB ++** ++** DATE : 12 Auguest 2007 ++** AUTHOR : Sung Winder ++** DESCRIPTION : Platform specific initialization. ++** COPYRIGHT : Copyright (c) 2007 ++** Infineon Technologies AG ++** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, ++** Hsin-chu City, 300 Taiwan. ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 12 Auguest 2007 Sung Winder Initiate Version ++*******************************************************************************/ ++#include "dwc_otg_ifx.h" ++ ++#include <linux/platform_device.h> ++#include <linux/kernel.h> ++#include <linux/ioport.h> ++#include <linux/gpio.h> ++ ++#include <asm/io.h> ++//#include <asm/mach-ifxmips/ifxmips.h> ++#include <lantiq_soc.h> ++ ++#define IFXMIPS_GPIO_BASE_ADDR (0xBE100B00) ++ ++#define IFXMIPS_GPIO_P0_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0010)) ++#define IFXMIPS_GPIO_P1_OUT ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0040)) ++#define IFXMIPS_GPIO_P0_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0014)) ++#define IFXMIPS_GPIO_P1_IN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0044)) ++#define IFXMIPS_GPIO_P0_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0018)) ++#define IFXMIPS_GPIO_P1_DIR ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0048)) ++#define IFXMIPS_GPIO_P0_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x001C)) ++#define IFXMIPS_GPIO_P1_ALTSEL0 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x004C)) ++#define IFXMIPS_GPIO_P0_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0020)) ++#define IFXMIPS_GPIO_P1_ALTSEL1 ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0050)) ++#define IFXMIPS_GPIO_P0_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0024)) ++#define IFXMIPS_GPIO_P1_OD ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0054)) ++#define IFXMIPS_GPIO_P0_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0028)) ++#define IFXMIPS_GPIO_P1_STOFF ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0058)) ++#define IFXMIPS_GPIO_P0_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x002C)) ++#define IFXMIPS_GPIO_P1_PUDSEL ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x005C)) ++#define IFXMIPS_GPIO_P0_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0030)) ++#define IFXMIPS_GPIO_P1_PUDEN ((u32 *)(IFXMIPS_GPIO_BASE_ADDR + 0x0060)) ++ ++ ++#define writel ltq_w32 ++#define readl ltq_r32 ++void dwc_otg_power_on (void) ++{ ++ // clear power ++ writel(readl(DANUBE_PMU_PWDCR) | 0x41, DANUBE_PMU_PWDCR); ++ // set clock gating ++ writel(readl(DANUBE_CGU_IFCCR) | 0x30, DANUBE_CGU_IFCCR); ++ // set power ++ writel(readl(DANUBE_PMU_PWDCR) & ~0x1, DANUBE_PMU_PWDCR); ++ writel(readl(DANUBE_PMU_PWDCR) & ~0x40, DANUBE_PMU_PWDCR); ++ writel(readl(DANUBE_PMU_PWDCR) & ~0x8000, DANUBE_PMU_PWDCR); ++ ++#if 1//defined (DWC_HOST_ONLY) ++ // make the hardware be a host controller (default) ++ //clear_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); ++ writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_HDSEL_BIT), DANUBE_RCU_UBSCFG); ++ ++ //#elif defined (DWC_DEVICE_ONLY) ++ /* set the controller to the device mode */ ++ // set_bit (DANUBE_USBCFG_HDSEL_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); ++#else ++#error "For Danube/Twinpass, it should be HOST or Device Only." ++#endif ++ ++ // set the HC's byte-order to big-endian ++ //set_bit (DANUBE_USBCFG_HOST_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); ++ writel(readl(DANUBE_RCU_UBSCFG) | (1<<DANUBE_USBCFG_HOST_END_BIT), DANUBE_RCU_UBSCFG); ++ //clear_bit (DANUBE_USBCFG_SLV_END_BIT, (volatile unsigned long *)DANUBE_RCU_UBSCFG); ++ writel(readl(DANUBE_RCU_UBSCFG) & ~(1<<DANUBE_USBCFG_SLV_END_BIT), DANUBE_RCU_UBSCFG); ++ //writel(0x400, DANUBE_RCU_UBSCFG); ++ ++ // PHY configurations. ++ writel (0x14014, (volatile unsigned long *)0xbe10103c); ++} ++ ++int ifx_usb_hc_init(unsigned long base_addr, int irq) ++{ ++ return 0; ++} ++ ++void ifx_usb_hc_remove(void) ++{ ++} +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_ifx.h +@@ -0,0 +1,85 @@ ++/****************************************************************************** ++** ++** FILE NAME : dwc_otg_ifx.h ++** PROJECT : Twinpass/Danube ++** MODULES : DWC OTG USB ++** ++** DATE : 12 April 2007 ++** AUTHOR : Sung Winder ++** DESCRIPTION : Platform specific initialization. ++** COPYRIGHT : Copyright (c) 2007 ++** Infineon Technologies AG ++** 2F, No.2, Li-Hsin Rd., Hsinchu Science Park, ++** Hsin-chu City, 300 Taiwan. ++** ++** This program is free software; you can redistribute it and/or modify ++** it under the terms of the GNU General Public License as published by ++** the Free Software Foundation; either version 2 of the License, or ++** (at your option) any later version. ++** ++** HISTORY ++** $Date $Author $Comment ++** 12 April 2007 Sung Winder Initiate Version ++*******************************************************************************/ ++#if !defined(__DWC_OTG_IFX_H__) ++#define __DWC_OTG_IFX_H__ ++ ++#include <linux/irq.h> ++#include <irq.h> ++ ++// 20070316, winder added. ++#ifndef SZ_256K ++#define SZ_256K 0x00040000 ++#endif ++ ++extern void dwc_otg_power_on (void); ++ ++/* FIXME: The current Linux-2.6 do not have these header files, but anyway, we need these. */ ++// #include <asm/danube/danube.h> ++// #include <asm/ifx/irq.h> ++ ++/* winder, I used the Danube parameter as default. * ++ * We could change this through module param. */ ++#define IFX_USB_IOMEM_BASE 0x1e101000 ++#define IFX_USB_IOMEM_SIZE SZ_256K ++#define IFX_USB_IRQ LTQ_USB_INT ++ ++/** ++ * This function is called to set correct clock gating and power. ++ * For Twinpass/Danube board. ++ */ ++#ifndef DANUBE_RCU_BASE_ADDR ++#define DANUBE_RCU_BASE_ADDR (0xBF203000) ++#endif ++ ++#ifndef DANUBE_CGU ++#define DANUBE_CGU (0xBF103000) ++#endif ++#ifndef DANUBE_CGU_IFCCR ++/***CGU Interface Clock Control Register***/ ++#define DANUBE_CGU_IFCCR ((volatile u32*)(DANUBE_CGU+ 0x0018)) ++#endif ++ ++#ifndef DANUBE_PMU ++#define DANUBE_PMU (KSEG1+0x1F102000) ++#endif ++#ifndef DANUBE_PMU_PWDCR ++/* PMU Power down Control Register */ ++#define DANUBE_PMU_PWDCR ((volatile u32*)(DANUBE_PMU+0x001C)) ++#endif ++ ++ ++#define DANUBE_RCU_UBSCFG ((volatile u32*)(DANUBE_RCU_BASE_ADDR + 0x18)) ++#define DANUBE_USBCFG_HDSEL_BIT 11 // 0:host, 1:device ++#define DANUBE_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end ++#define DANUBE_USBCFG_SLV_END_BIT 9 // 0:little_end, 1:big_end ++ ++extern void ltq_mask_and_ack_irq(struct irq_data *d); ++ ++static void inline mask_and_ack_ifx_irq(int x) ++{ ++ struct irq_data d; ++ d.irq = x; ++ ltq_mask_and_ack_irq(&d); ++} ++#endif //__DWC_OTG_IFX_H__ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_plat.h +@@ -0,0 +1,269 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/platform/dwc_otg_plat.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 510301 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#if !defined(__DWC_OTG_PLAT_H__) ++#define __DWC_OTG_PLAT_H__ ++ ++#include <linux/types.h> ++#include <linux/slab.h> ++#include <linux/list.h> ++#include <linux/delay.h> ++#include <asm/io.h> ++ ++/** ++ * @file ++ * ++ * This file contains the Platform Specific constants, interfaces ++ * (functions and macros) for Linux. ++ * ++ */ ++/*#if !defined(__LINUX__) ++#error "The contents of this file is Linux specific!!!" ++#endif ++*/ ++#include <lantiq_soc.h> ++#define writel ltq_w32 ++#define readl ltq_r32 ++ ++/** ++ * Reads the content of a register. ++ * ++ * @param _reg address of register to read. ++ * @return contents of the register. ++ * ++ ++ * Usage:<br> ++ * <code>uint32_t dev_ctl = dwc_read_reg32(&dev_regs->dctl);</code> ++ */ ++static __inline__ uint32_t dwc_read_reg32( volatile uint32_t *_reg) ++{ ++ return readl(_reg); ++}; ++ ++/** ++ * Writes a register with a 32 bit value. ++ * ++ * @param _reg address of register to read. ++ * @param _value to write to _reg. ++ * ++ * Usage:<br> ++ * <code>dwc_write_reg32(&dev_regs->dctl, 0); </code> ++ */ ++static __inline__ void dwc_write_reg32( volatile uint32_t *_reg, const uint32_t _value) ++{ ++ writel( _value, _reg ); ++}; ++ ++/** ++ * This function modifies bit values in a register. Using the ++ * algorithm: (reg_contents & ~clear_mask) | set_mask. ++ * ++ * @param _reg address of register to read. ++ * @param _clear_mask bit mask to be cleared. ++ * @param _set_mask bit mask to be set. ++ * ++ * Usage:<br> ++ * <code> // Clear the SOF Interrupt Mask bit and <br> ++ * // set the OTG Interrupt mask bit, leaving all others as they were. ++ * dwc_modify_reg32(&dev_regs->gintmsk, DWC_SOF_INT, DWC_OTG_INT);</code> ++ */ ++static __inline__ ++ void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask) ++{ ++ writel( (readl(_reg) & ~_clear_mask) | _set_mask, _reg ); ++}; ++ ++ ++/** ++ * Wrapper for the OS micro-second delay function. ++ * @param[in] _usecs Microseconds of delay ++ */ ++static __inline__ void UDELAY( const uint32_t _usecs ) ++{ ++ udelay( _usecs ); ++} ++ ++/** ++ * Wrapper for the OS milli-second delay function. ++ * @param[in] _msecs milliseconds of delay ++ */ ++static __inline__ void MDELAY( const uint32_t _msecs ) ++{ ++ mdelay( _msecs ); ++} ++ ++/** ++ * Wrapper for the Linux spin_lock. On the ARM (Integrator) ++ * spin_lock() is a nop. ++ * ++ * @param _lock Pointer to the spinlock. ++ */ ++static __inline__ void SPIN_LOCK( spinlock_t *_lock ) ++{ ++ spin_lock(_lock); ++} ++ ++/** ++ * Wrapper for the Linux spin_unlock. On the ARM (Integrator) ++ * spin_lock() is a nop. ++ * ++ * @param _lock Pointer to the spinlock. ++ */ ++static __inline__ void SPIN_UNLOCK( spinlock_t *_lock ) ++{ ++ spin_unlock(_lock); ++} ++ ++/** ++ * Wrapper (macro) for the Linux spin_lock_irqsave. On the ARM ++ * (Integrator) spin_lock() is a nop. ++ * ++ * @param _l Pointer to the spinlock. ++ * @param _f unsigned long for irq flags storage. ++ */ ++#define SPIN_LOCK_IRQSAVE( _l, _f ) { \ ++ spin_lock_irqsave(_l,_f); \ ++ } ++ ++/** ++ * Wrapper (macro) for the Linux spin_unlock_irqrestore. On the ARM ++ * (Integrator) spin_lock() is a nop. ++ * ++ * @param _l Pointer to the spinlock. ++ * @param _f unsigned long for irq flags storage. ++ */ ++#define SPIN_UNLOCK_IRQRESTORE( _l,_f ) {\ ++ spin_unlock_irqrestore(_l,_f); \ ++ } ++ ++ ++/* ++ * Debugging support vanishes in non-debug builds. ++ */ ++ ++ ++/** ++ * The Debug Level bit-mask variable. ++ */ ++extern uint32_t g_dbg_lvl; ++/** ++ * Set the Debug Level variable. ++ */ ++static inline uint32_t SET_DEBUG_LEVEL( const uint32_t _new ) ++{ ++ uint32_t old = g_dbg_lvl; ++ g_dbg_lvl = _new; ++ return old; ++} ++ ++/** When debug level has the DBG_CIL bit set, display CIL Debug messages. */ ++#define DBG_CIL (0x2) ++/** When debug level has the DBG_CILV bit set, display CIL Verbose debug ++ * messages */ ++#define DBG_CILV (0x20) ++/** When debug level has the DBG_PCD bit set, display PCD (Device) debug ++ * messages */ ++#define DBG_PCD (0x4) ++/** When debug level has the DBG_PCDV set, display PCD (Device) Verbose debug ++ * messages */ ++#define DBG_PCDV (0x40) ++/** When debug level has the DBG_HCD bit set, display Host debug messages */ ++#define DBG_HCD (0x8) ++/** When debug level has the DBG_HCDV bit set, display Verbose Host debug ++ * messages */ ++#define DBG_HCDV (0x80) ++/** When debug level has the DBG_HCD_URB bit set, display enqueued URBs in host ++ * mode. */ ++#define DBG_HCD_URB (0x800) ++ ++/** When debug level has any bit set, display debug messages */ ++#define DBG_ANY (0xFF) ++ ++/** All debug messages off */ ++#define DBG_OFF 0 ++ ++/** Prefix string for DWC_DEBUG print macros. */ ++#define USB_DWC "DWC_otg: " ++ ++/** ++ * Print a debug message when the Global debug level variable contains ++ * the bit defined in <code>lvl</code>. ++ * ++ * @param[in] lvl - Debug level, use one of the DBG_ constants above. ++ * @param[in] x - like printf ++ * ++ * Example:<p> ++ * <code> ++ * DWC_DEBUGPL( DBG_ANY, "%s(%p)\n", __func__, _reg_base_addr); ++ * </code> ++ * <br> ++ * results in:<br> ++ * <code> ++ * usb-DWC_otg: dwc_otg_cil_init(ca867000) ++ * </code> ++ */ ++#ifdef DEBUG ++ ++# define DWC_DEBUGPL(lvl, x...) do{ if ((lvl)&g_dbg_lvl)printk( KERN_DEBUG USB_DWC x ); }while(0) ++# define DWC_DEBUGP(x...) DWC_DEBUGPL(DBG_ANY, x ) ++ ++# define CHK_DEBUG_LEVEL(level) ((level) & g_dbg_lvl) ++ ++#else ++ ++# define DWC_DEBUGPL(lvl, x...) do{}while(0) ++# define DWC_DEBUGP(x...) ++ ++# define CHK_DEBUG_LEVEL(level) (0) ++ ++#endif /*DEBUG*/ ++ ++/** ++ * Print an Error message. ++ */ ++#define DWC_ERROR(x...) printk( KERN_ERR USB_DWC x ) ++/** ++ * Print a Warning message. ++ */ ++#define DWC_WARN(x...) printk( KERN_WARNING USB_DWC x ) ++/** ++ * Print a notice (normal but significant message). ++ */ ++#define DWC_NOTICE(x...) printk( KERN_NOTICE USB_DWC x ) ++/** ++ * Basic message printing. ++ */ ++#define DWC_PRINT(x...) printk( KERN_INFO USB_DWC x ) ++ ++#endif ++ +--- /dev/null ++++ b/drivers/usb/dwc_otg/dwc_otg_regs.h +@@ -0,0 +1,1797 @@ ++/* ========================================================================== ++ * $File: //dwh/usb_iip/dev/software/otg_ipmate/linux/drivers/dwc_otg_regs.h $ ++ * $Revision: 1.1.1.1 $ ++ * $Date: 2009-04-17 06:15:34 $ ++ * $Change: 631780 $ ++ * ++ * Synopsys HS OTG Linux Software Driver and documentation (hereinafter, ++ * "Software") is an Unsupported proprietary work of Synopsys, Inc. unless ++ * otherwise expressly agreed to in writing between Synopsys and you. ++ * ++ * The Software IS NOT an item of Licensed Software or Licensed Product under ++ * any End User Software License Agreement or Agreement for Licensed Product ++ * with Synopsys or any supplement thereto. You are permitted to use and ++ * redistribute this Software in source and binary forms, with or without ++ * modification, provided that redistributions of source code must retain this ++ * notice. You may not view, use, disclose, copy or distribute this file or ++ * any information contained herein except pursuant to this license grant from ++ * Synopsys. If you do not agree with this notice, including the disclaimer ++ * below, then you are not authorized to use the Software. ++ * ++ * THIS SOFTWARE IS BEING DISTRIBUTED BY SYNOPSYS SOLELY ON AN "AS IS" BASIS ++ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE ++ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ++ * ARE HEREBY DISCLAIMED. IN NO EVENT SHALL SYNOPSYS BE LIABLE FOR ANY DIRECT, ++ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ++ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR ++ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER ++ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT ++ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY ++ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH ++ * DAMAGE. ++ * ========================================================================== */ ++ ++#ifndef __DWC_OTG_REGS_H__ ++#define __DWC_OTG_REGS_H__ ++ ++/** ++ * @file ++ * ++ * This file contains the data structures for accessing the DWC_otg core registers. ++ * ++ * The application interfaces with the HS OTG core by reading from and ++ * writing to the Control and Status Register (CSR) space through the ++ * AHB Slave interface. These registers are 32 bits wide, and the ++ * addresses are 32-bit-block aligned. ++ * CSRs are classified as follows: ++ * - Core Global Registers ++ * - Device Mode Registers ++ * - Device Global Registers ++ * - Device Endpoint Specific Registers ++ * - Host Mode Registers ++ * - Host Global Registers ++ * - Host Port CSRs ++ * - Host Channel Specific Registers ++ * ++ * Only the Core Global registers can be accessed in both Device and ++ * Host modes. When the HS OTG core is operating in one mode, either ++ * Device or Host, the application must not access registers from the ++ * other mode. When the core switches from one mode to another, the ++ * registers in the new mode of operation must be reprogrammed as they ++ * would be after a power-on reset. ++ */ ++ ++/****************************************************************************/ ++/** DWC_otg Core registers . ++ * The dwc_otg_core_global_regs structure defines the size ++ * and relative field offsets for the Core Global registers. ++ */ ++typedef struct dwc_otg_core_global_regs ++{ ++ /** OTG Control and Status Register. <i>Offset: 000h</i> */ ++ volatile uint32_t gotgctl; ++ /** OTG Interrupt Register. <i>Offset: 004h</i> */ ++ volatile uint32_t gotgint; ++ /**Core AHB Configuration Register. <i>Offset: 008h</i> */ ++ volatile uint32_t gahbcfg; ++#define DWC_GLBINTRMASK 0x0001 ++#define DWC_DMAENABLE 0x0020 ++#define DWC_NPTXEMPTYLVL_EMPTY 0x0080 ++#define DWC_NPTXEMPTYLVL_HALFEMPTY 0x0000 ++#define DWC_PTXEMPTYLVL_EMPTY 0x0100 ++#define DWC_PTXEMPTYLVL_HALFEMPTY 0x0000 ++ ++ ++ /**Core USB Configuration Register. <i>Offset: 00Ch</i> */ ++ volatile uint32_t gusbcfg; ++ /**Core Reset Register. <i>Offset: 010h</i> */ ++ volatile uint32_t grstctl; ++ /**Core Interrupt Register. <i>Offset: 014h</i> */ ++ volatile uint32_t gintsts; ++ /**Core Interrupt Mask Register. <i>Offset: 018h</i> */ ++ volatile uint32_t gintmsk; ++ /**Receive Status Queue Read Register (Read Only). <i>Offset: 01Ch</i> */ ++ volatile uint32_t grxstsr; ++ /**Receive Status Queue Read & POP Register (Read Only). <i>Offset: 020h</i>*/ ++ volatile uint32_t grxstsp; ++ /**Receive FIFO Size Register. <i>Offset: 024h</i> */ ++ volatile uint32_t grxfsiz; ++ /**Non Periodic Transmit FIFO Size Register. <i>Offset: 028h</i> */ ++ volatile uint32_t gnptxfsiz; ++ /**Non Periodic Transmit FIFO/Queue Status Register (Read ++ * Only). <i>Offset: 02Ch</i> */ ++ volatile uint32_t gnptxsts; ++ /**I2C Access Register. <i>Offset: 030h</i> */ ++ volatile uint32_t gi2cctl; ++ /**PHY Vendor Control Register. <i>Offset: 034h</i> */ ++ volatile uint32_t gpvndctl; ++ /**General Purpose Input/Output Register. <i>Offset: 038h</i> */ ++ volatile uint32_t ggpio; ++ /**User ID Register. <i>Offset: 03Ch</i> */ ++ volatile uint32_t guid; ++ /**Synopsys ID Register (Read Only). <i>Offset: 040h</i> */ ++ volatile uint32_t gsnpsid; ++ /**User HW Config1 Register (Read Only). <i>Offset: 044h</i> */ ++ volatile uint32_t ghwcfg1; ++ /**User HW Config2 Register (Read Only). <i>Offset: 048h</i> */ ++ volatile uint32_t ghwcfg2; ++#define DWC_SLAVE_ONLY_ARCH 0 ++#define DWC_EXT_DMA_ARCH 1 ++#define DWC_INT_DMA_ARCH 2 ++ ++#define DWC_MODE_HNP_SRP_CAPABLE 0 ++#define DWC_MODE_SRP_ONLY_CAPABLE 1 ++#define DWC_MODE_NO_HNP_SRP_CAPABLE 2 ++#define DWC_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_MODE_NO_SRP_CAPABLE_HOST 6 ++ ++ /**User HW Config3 Register (Read Only). <i>Offset: 04Ch</i> */ ++ volatile uint32_t ghwcfg3; ++ /**User HW Config4 Register (Read Only). <i>Offset: 050h</i>*/ ++ volatile uint32_t ghwcfg4; ++ /** Reserved <i>Offset: 054h-0FFh</i> */ ++ uint32_t reserved[43]; ++ /** Host Periodic Transmit FIFO Size Register. <i>Offset: 100h</i> */ ++ volatile uint32_t hptxfsiz; ++ /** Device Periodic Transmit FIFO#n Register if dedicated fifos are disabled, ++ otherwise Device Transmit FIFO#n Register. ++ * <i>Offset: 104h + (FIFO_Number-1)*04h, 1 <= FIFO Number <= 15 (1<=n<=15).</i> */ ++ //volatile uint32_t dptxfsiz[15]; ++ volatile uint32_t dptxfsiz_dieptxf[15]; ++} dwc_otg_core_global_regs_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Control ++ * and Status Register (GOTGCTL). Set the bits using the bit ++ * fields then write the <i>d32</i> value to the register. ++ */ ++typedef union gotgctl_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ unsigned reserved31_21 : 11; ++ unsigned currmod : 1; ++ unsigned bsesvld : 1; ++ unsigned asesvld : 1; ++ unsigned reserved17 : 1; ++ unsigned conidsts : 1; ++ unsigned reserved15_12 : 4; ++ unsigned devhnpen : 1; ++ unsigned hstsethnpen : 1; ++ unsigned hnpreq : 1; ++ unsigned hstnegscs : 1; ++ unsigned reserved7_2 : 6; ++ unsigned sesreq : 1; ++ unsigned sesreqscs : 1; ++ } b; ++} gotgctl_data_t; ++ ++/** ++ * This union represents the bit fields of the Core OTG Interrupt Register ++ * (GOTGINT). Set/clear the bits using the bit fields then write the <i>d32</i> ++ * value to the register. ++ */ ++typedef union gotgint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ /** Current Mode */ ++ unsigned reserved31_20 : 12; ++ /** Debounce Done */ ++ unsigned debdone : 1; ++ /** A-Device Timeout Change */ ++ unsigned adevtoutchng : 1; ++ /** Host Negotiation Detected */ ++ unsigned hstnegdet : 1; ++ unsigned reserver16_10 : 7; ++ /** Host Negotiation Success Status Change */ ++ unsigned hstnegsucstschng : 1; ++ /** Session Request Success Status Change */ ++ unsigned sesreqsucstschng : 1; ++ unsigned reserved3_7 : 5; ++ /** Session End Detected */ ++ unsigned sesenddet : 1; ++ /** Current Mode */ ++ unsigned reserved1_0 : 2; ++ } b; ++} gotgint_data_t; ++ ++ ++/** ++ * This union represents the bit fields of the Core AHB Configuration ++ * Register (GAHBCFG). Set/clear the bits using the bit fields then ++ * write the <i>d32</i> value to the register. ++ */ ++typedef union gahbcfg_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++#define DWC_GAHBCFG_TXFEMPTYLVL_EMPTY 1 ++#define DWC_GAHBCFG_TXFEMPTYLVL_HALFEMPTY 0 ++ unsigned reserved9_31 : 23; ++ unsigned ptxfemplvl : 1; ++ unsigned nptxfemplvl_txfemplvl : 1; ++#define DWC_GAHBCFG_DMAENABLE 1 ++ unsigned reserved : 1; ++ unsigned dmaenable : 1; ++#define DWC_GAHBCFG_INT_DMA_BURST_SINGLE 0 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR 1 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR4 3 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR8 5 ++#define DWC_GAHBCFG_INT_DMA_BURST_INCR16 7 ++ unsigned hburstlen : 4; ++ unsigned glblintrmsk : 1; ++#define DWC_GAHBCFG_GLBINT_ENABLE 1 ++ ++ } b; ++} gahbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core USB Configuration ++ * Register (GUSBCFG). Set the bits using the bit fields then write ++ * the <i>d32</i> value to the register. ++ */ ++typedef union gusbcfg_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ unsigned corrupt_tx_packet: 1; /*fscz*/ ++ unsigned force_device_mode: 1; ++ unsigned force_host_mode: 1; ++ unsigned reserved23_28 : 6; ++ unsigned term_sel_dl_pulse : 1; ++ unsigned ulpi_int_vbus_indicator : 1; ++ unsigned ulpi_ext_vbus_drv : 1; ++ unsigned ulpi_clk_sus_m : 1; ++ unsigned ulpi_auto_res : 1; ++ unsigned ulpi_fsls : 1; ++ unsigned otgutmifssel : 1; ++ unsigned phylpwrclksel : 1; ++ unsigned nptxfrwnden : 1; ++ unsigned usbtrdtim : 4; ++ unsigned hnpcap : 1; ++ unsigned srpcap : 1; ++ unsigned ddrsel : 1; ++ unsigned physel : 1; ++ unsigned fsintf : 1; ++ unsigned ulpi_utmi_sel : 1; ++ unsigned phyif : 1; ++ unsigned toutcal : 3; ++ } b; ++} gusbcfg_data_t; ++ ++/** ++ * This union represents the bit fields of the Core Reset Register ++ * (GRSTCTL). Set/clear the bits using the bit fields then write the ++ * <i>d32</i> value to the register. ++ */ ++typedef union grstctl_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ /** AHB Master Idle. Indicates the AHB Master State ++ * Machine is in IDLE condition. */ ++ unsigned ahbidle : 1; ++ /** DMA Request Signal. Indicated DMA request is in ++ * probress. Used for debug purpose. */ ++ unsigned dmareq : 1; ++ /** Reserved */ ++ unsigned reserved29_11 : 19; ++ /** TxFIFO Number (TxFNum) (Device and Host). ++ * ++ * This is the FIFO number which needs to be flushed, ++ * using the TxFIFO Flush bit. This field should not ++ * be changed until the TxFIFO Flush bit is cleared by ++ * the core. ++ * - 0x0 : Non Periodic TxFIFO Flush ++ * - 0x1 : Periodic TxFIFO #1 Flush in device mode ++ * or Periodic TxFIFO in host mode ++ * - 0x2 : Periodic TxFIFO #2 Flush in device mode. ++ * - ... ++ * - 0xF : Periodic TxFIFO #15 Flush in device mode ++ * - 0x10: Flush all the Transmit NonPeriodic and ++ * Transmit Periodic FIFOs in the core ++ */ ++ unsigned txfnum : 5; ++ /** TxFIFO Flush (TxFFlsh) (Device and Host). ++ * ++ * This bit is used to selectively flush a single or ++ * all transmit FIFOs. The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. <p>The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is writing into the TxFIFO nor the MAC ++ * is reading the data out of the FIFO. <p>The ++ * application should wait until the core clears this ++ * bit, before performing any operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned txfflsh : 1; ++ /** RxFIFO Flush (RxFFlsh) (Device and Host) ++ * ++ * The application can flush the entire Receive FIFO ++ * using this bit. <p>The application must first ++ * ensure that the core is not in the middle of a ++ * transaction. <p>The application should write into ++ * this bit, only after making sure that neither the ++ * DMA engine is reading from the RxFIFO nor the MAC ++ * is writing the data in to the FIFO. <p>The ++ * application should wait until the bit is cleared ++ * before performing any other operations. This bit ++ * will takes 8 clocks (slowest of PHY or AHB clock) ++ * to clear. ++ */ ++ unsigned rxfflsh : 1; ++ /** In Token Sequence Learning Queue Flush ++ * (INTknQFlsh) (Device Only) ++ */ ++ unsigned intknqflsh : 1; ++ /** Host Frame Counter Reset (Host Only)<br> ++ * ++ * The application can reset the (micro)frame number ++ * counter inside the core, using this bit. When the ++ * (micro)frame counter is reset, the subsequent SOF ++ * sent out by the core, will have a (micro)frame ++ * number of 0. ++ */ ++ unsigned hstfrm : 1; ++ /** Hclk Soft Reset ++ * ++ * The application uses this bit to reset the control logic in ++ * the AHB clock domain. Only AHB clock domain pipelines are ++ * reset. ++ */ ++ unsigned hsftrst : 1; ++ /** Core Soft Reset (CSftRst) (Device and Host) ++ * ++ * The application can flush the control logic in the ++ * entire core using this bit. This bit resets the ++ * pipelines in the AHB Clock domain as well as the ++ * PHY Clock domain. ++ * ++ * The state machines are reset to an IDLE state, the ++ * control bits in the CSRs are cleared, all the ++ * transmit FIFOs and the receive FIFO are flushed. ++ * ++ * The status mask bits that control the generation of ++ * the interrupt, are cleared, to clear the ++ * interrupt. The interrupt status bits are not ++ * cleared, so the application can get the status of ++ * any events that occurred in the core after it has ++ * set this bit. ++ * ++ * Any transactions on the AHB are terminated as soon ++ * as possible following the protocol. Any ++ * transactions on the USB are terminated immediately. ++ * ++ * The configuration settings in the CSRs are ++ * unchanged, so the software doesn't have to ++ * reprogram these registers (Device ++ * Configuration/Host Configuration/Core System ++ * Configuration/Core PHY Configuration). ++ * ++ * The application can write to this bit, any time it ++ * wants to reset the core. This is a self clearing ++ * bit and the core clears this bit after all the ++ * necessary logic is reset in the core, which may ++ * take several clocks, depending on the current state ++ * of the core. ++ */ ++ unsigned csftrst : 1; ++ } b; ++} grstctl_t; ++ ++ ++/** ++ * This union represents the bit fields of the Core Interrupt Mask ++ * Register (GINTMSK). Set/clear the bits using the bit fields then ++ * write the <i>d32</i> value to the register. ++ */ ++typedef union gintmsk_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct ++ { ++ unsigned wkupintr : 1; ++ unsigned sessreqintr : 1; ++ unsigned disconnect : 1; ++ unsigned conidstschng : 1; ++ unsigned reserved27 : 1; ++ unsigned ptxfempty : 1; ++ unsigned hcintr : 1; ++ unsigned portintr : 1; ++ unsigned reserved22_23 : 2; ++ unsigned incomplisoout : 1; ++ unsigned incomplisoin : 1; ++ unsigned outepintr : 1; ++ unsigned inepintr : 1; ++ unsigned epmismatch : 1; ++ unsigned reserved16 : 1; ++ unsigned eopframe : 1; ++ unsigned isooutdrop : 1; ++ unsigned enumdone : 1; ++ unsigned usbreset : 1; ++ unsigned usbsuspend : 1; ++ unsigned erlysuspend : 1; ++ unsigned i2cintr : 1; ++ unsigned reserved8 : 1; ++ unsigned goutnakeff : 1; ++ unsigned ginnakeff : 1; ++ unsigned nptxfempty : 1; ++ unsigned rxstsqlvl : 1; ++ unsigned sofintr : 1; ++ unsigned otgintr : 1; ++ unsigned modemismatch : 1; ++ unsigned reserved0 : 1; ++ } b; ++} gintmsk_data_t; ++/** ++ * This union represents the bit fields of the Core Interrupt Register ++ * (GINTSTS). Set/clear the bits using the bit fields then write the ++ * <i>d32</i> value to the register. ++ */ ++typedef union gintsts_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++#define DWC_SOF_INTR_MASK 0x0008 ++ /** register bits */ ++ struct ++ { ++#define DWC_HOST_MODE 1 ++ unsigned wkupintr : 1; ++ unsigned sessreqintr : 1; ++ unsigned disconnect : 1; ++ unsigned conidstschng : 1; ++ unsigned reserved27 : 1; ++ unsigned ptxfempty : 1; ++ unsigned hcintr : 1; ++ unsigned portintr : 1; ++ unsigned reserved22_23 : 2; ++ unsigned incomplisoout : 1; ++ unsigned incomplisoin : 1; ++ unsigned outepintr : 1; ++ unsigned inepint: 1; ++ unsigned epmismatch : 1; ++ unsigned intokenrx : 1; ++ unsigned eopframe : 1; ++ unsigned isooutdrop : 1; ++ unsigned enumdone : 1; ++ unsigned usbreset : 1; ++ unsigned usbsuspend : 1; ++ unsigned erlysuspend : 1; ++ unsigned i2cintr : 1; ++ unsigned reserved8 : 1; ++ unsigned goutnakeff : 1; ++ unsigned ginnakeff : 1; ++ unsigned nptxfempty : 1; ++ unsigned rxstsqlvl : 1; ++ unsigned sofintr : 1; ++ unsigned otgintr : 1; ++ unsigned modemismatch : 1; ++ unsigned curmode : 1; ++ } b; ++} gintsts_data_t; ++ ++ ++/** ++ * This union represents the bit fields in the Device Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> ++ * element then read out the bits using the <i>b</i>it elements. ++ */ ++typedef union device_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 7; ++ unsigned fn : 4; ++#define DWC_STS_DATA_UPDT 0x2 // OUT Data Packet ++#define DWC_STS_XFER_COMP 0x3 // OUT Data Transfer Complete ++ ++#define DWC_DSTS_GOUT_NAK 0x1 // Global OUT NAK ++#define DWC_DSTS_SETUP_COMP 0x4 // Setup Phase Complete ++#define DWC_DSTS_SETUP_UPDT 0x6 // SETUP Packet ++ unsigned pktsts : 4; ++ unsigned dpid : 2; ++ unsigned bcnt : 11; ++ unsigned epnum : 4; ++ } b; ++} device_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Receive Status Read and ++ * Pop Registers (GRXSTSR, GRXSTSP) Read the register into the <i>d32</i> ++ * element then read out the bits using the <i>b</i>it elements. ++ */ ++typedef union host_grxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved31_21 : 11; ++#define DWC_GRXSTS_PKTSTS_IN 0x2 ++#define DWC_GRXSTS_PKTSTS_IN_XFER_COMP 0x3 ++#define DWC_GRXSTS_PKTSTS_DATA_TOGGLE_ERR 0x5 ++#define DWC_GRXSTS_PKTSTS_CH_HALTED 0x7 ++ unsigned pktsts : 4; ++ unsigned dpid : 2; ++ unsigned bcnt : 11; ++ unsigned chnum : 4; ++ } b; ++} host_grxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the FIFO Size Registers (HPTXFSIZ, ++ * GNPTXFSIZ, DPTXFSIZn). Read the register into the <i>d32</i> element then ++ * read out the bits using the <i>b</i>it elements. ++ */ ++typedef union fifosize_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned depth : 16; ++ unsigned startaddr : 16; ++ } b; ++} fifosize_data_t; ++ ++/** ++ * This union represents the bit fields in the Non-Periodic Transmit ++ * FIFO/Queue Status Register (GNPTXSTS). Read the register into the ++ * <i>d32</i> element then read out the bits using the <i>b</i>it ++ * elements. ++ */ ++typedef union gnptxsts_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 1; ++ /** Top of the Non-Periodic Transmit Request Queue ++ * - bits 30:27 - Channel/EP Number ++ * - bits 26:25 - Token Type ++ * - bit 24 - Terminate (Last entry for the selected ++ * channel/EP) ++ * - 2'b00 - IN/OUT ++ * - 2'b01 - Zero Length OUT ++ * - 2'b10 - PING/Complete Split ++ * - 2'b11 - Channel Halt ++ ++ */ ++ unsigned nptxqtop_chnep : 4; ++ unsigned nptxqtop_token : 2; ++ unsigned nptxqtop_terminate : 1; ++ unsigned nptxqspcavail : 8; ++ unsigned nptxfspcavail : 16; ++ } b; ++} gnptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Transmit ++ * FIFO Status Register (DTXFSTS). Read the register into the ++ * <i>d32</i> element then read out the bits using the <i>b</i>it ++ * elements. ++ */ ++typedef union dtxfsts_data /* fscz */ //* ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 16; ++ unsigned txfspcavail : 16; ++ } b; ++} dtxfsts_data_t; ++ ++/** ++ * This union represents the bit fields in the I2C Control Register ++ * (I2CCTL). Read the register into the <i>d32</i> element then read out the ++ * bits using the <i>b</i>it elements. ++ */ ++typedef union gi2cctl_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned bsydne : 1; ++ unsigned rw : 1; ++ unsigned reserved : 2; ++ unsigned i2cdevaddr : 2; ++ unsigned i2csuspctl : 1; ++ unsigned ack : 1; ++ unsigned i2cen : 1; ++ unsigned addr : 7; ++ unsigned regaddr : 8; ++ unsigned rwdata : 8; ++ } b; ++} gi2cctl_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config1 ++ * Register. Read the register into the <i>d32</i> element then read ++ * out the bits using the <i>b</i>it elements. ++ */ ++typedef union hwcfg1_data { ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned ep_dir15 : 2; ++ unsigned ep_dir14 : 2; ++ unsigned ep_dir13 : 2; ++ unsigned ep_dir12 : 2; ++ unsigned ep_dir11 : 2; ++ unsigned ep_dir10 : 2; ++ unsigned ep_dir9 : 2; ++ unsigned ep_dir8 : 2; ++ unsigned ep_dir7 : 2; ++ unsigned ep_dir6 : 2; ++ unsigned ep_dir5 : 2; ++ unsigned ep_dir4 : 2; ++ unsigned ep_dir3 : 2; ++ unsigned ep_dir2 : 2; ++ unsigned ep_dir1 : 2; ++ unsigned ep_dir0 : 2; ++ } b; ++} hwcfg1_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config2 ++ * Register. Read the register into the <i>d32</i> element then read ++ * out the bits using the <i>b</i>it elements. ++ */ ++typedef union hwcfg2_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG2 */ ++ unsigned reserved31 : 1; ++ unsigned dev_token_q_depth : 5; ++ unsigned host_perio_tx_q_depth : 2; ++ unsigned nonperio_tx_q_depth : 2; ++ unsigned rx_status_q_depth : 2; ++ unsigned dynamic_fifo : 1; ++ unsigned perio_ep_supported : 1; ++ unsigned num_host_chan : 4; ++ unsigned num_dev_ep : 4; ++ unsigned fs_phy_type : 2; ++#define DWC_HWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI 1 ++#define DWC_HWCFG2_HS_PHY_TYPE_ULPI 2 ++#define DWC_HWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 ++ unsigned hs_phy_type : 2; ++ unsigned point2point : 1; ++ unsigned architecture : 2; ++#define DWC_HWCFG2_OP_MODE_HNP_SRP_CAPABLE_OTG 0 ++#define DWC_HWCFG2_OP_MODE_SRP_ONLY_CAPABLE_OTG 1 ++#define DWC_HWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE_OTG 2 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 ++#define DWC_HWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 ++#define DWC_HWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 ++ unsigned op_mode : 3; ++ } b; ++} hwcfg2_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config3 ++ * Register. Read the register into the <i>d32</i> element then read ++ * out the bits using the <i>b</i>it elements. ++ */ ++typedef union hwcfg3_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /* GHWCFG3 */ ++ unsigned dfifo_depth : 16; ++ unsigned reserved15_13 : 3; ++ unsigned ahb_phy_clock_synch : 1; ++ unsigned synch_reset_type : 1; ++ unsigned optional_features : 1; ++ unsigned vendor_ctrl_if : 1; ++ unsigned i2c : 1; ++ unsigned otg_func : 1; ++ unsigned packet_size_cntr_width : 3; ++ unsigned xfer_size_cntr_width : 4; ++ } b; ++} hwcfg3_data_t; ++ ++/** ++ * This union represents the bit fields in the User HW Config4 ++ * Register. Read the register into the <i>d32</i> element then read ++ * out the bits using the <i>b</i>it elements. ++ */ ++typedef union hwcfg4_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++unsigned reserved31_30 : 2; /* fscz */ ++ unsigned num_in_eps : 4; ++ unsigned ded_fifo_en : 1; ++ ++ unsigned session_end_filt_en : 1; ++ unsigned b_valid_filt_en : 1; ++ unsigned a_valid_filt_en : 1; ++ unsigned vbus_valid_filt_en : 1; ++ unsigned iddig_filt_en : 1; ++ unsigned num_dev_mode_ctrl_ep : 4; ++ unsigned utmi_phy_data_width : 2; ++ unsigned min_ahb_freq : 9; ++ unsigned power_optimiz : 1; ++ unsigned num_dev_perio_in_ep : 4; ++ } b; ++} hwcfg4_data_t; ++ ++//////////////////////////////////////////// ++// Device Registers ++/** ++ * Device Global Registers. <i>Offsets 800h-BFFh</i> ++ * ++ * The following structures define the size and relative field offsets ++ * for the Device Mode Registers. ++ * ++ * <i>These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown.</i> ++ */ ++typedef struct dwc_otg_dev_global_regs ++{ ++ /** Device Configuration Register. <i>Offset 800h</i> */ ++ volatile uint32_t dcfg; ++ /** Device Control Register. <i>Offset: 804h</i> */ ++ volatile uint32_t dctl; ++ /** Device Status Register (Read Only). <i>Offset: 808h</i> */ ++ volatile uint32_t dsts; ++ /** Reserved. <i>Offset: 80Ch</i> */ ++ uint32_t unused; ++ /** Device IN Endpoint Common Interrupt Mask ++ * Register. <i>Offset: 810h</i> */ ++ volatile uint32_t diepmsk; ++ /** Device OUT Endpoint Common Interrupt Mask ++ * Register. <i>Offset: 814h</i> */ ++ volatile uint32_t doepmsk; ++ /** Device All Endpoints Interrupt Register. <i>Offset: 818h</i> */ ++ volatile uint32_t daint; ++ /** Device All Endpoints Interrupt Mask Register. <i>Offset: ++ * 81Ch</i> */ ++ volatile uint32_t daintmsk; ++ /** Device IN Token Queue Read Register-1 (Read Only). ++ * <i>Offset: 820h</i> */ ++ volatile uint32_t dtknqr1; ++ /** Device IN Token Queue Read Register-2 (Read Only). ++ * <i>Offset: 824h</i> */ ++ volatile uint32_t dtknqr2; ++ /** Device VBUS discharge Register. <i>Offset: 828h</i> */ ++ volatile uint32_t dvbusdis; ++ /** Device VBUS Pulse Register. <i>Offset: 82Ch</i> */ ++ volatile uint32_t dvbuspulse; ++ /** Device IN Token Queue Read Register-3 (Read Only). ++ * Device Thresholding control register (Read/Write) ++ * <i>Offset: 830h</i> */ ++ volatile uint32_t dtknqr3_dthrctl; ++ /** Device IN Token Queue Read Register-4 (Read Only). / ++ * Device IN EPs empty Inr. Mask Register (Read/Write) ++ * <i>Offset: 834h</i> */ ++ volatile uint32_t dtknqr4_fifoemptymsk; ++} dwc_otg_device_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device Configuration ++ * Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. Write the ++ * <i>d32</i> member to the dcfg register. ++ */ ++typedef union dcfg_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved31_23 : 9; ++ /** In Endpoint Mis-match count */ ++ unsigned epmscnt : 5; ++ unsigned reserved13_17 : 5; ++ /** Periodic Frame Interval */ ++#define DWC_DCFG_FRAME_INTERVAL_80 0 ++#define DWC_DCFG_FRAME_INTERVAL_85 1 ++#define DWC_DCFG_FRAME_INTERVAL_90 2 ++#define DWC_DCFG_FRAME_INTERVAL_95 3 ++ unsigned perfrint : 2; ++ /** Device Addresses */ ++ unsigned devaddr : 7; ++ unsigned reserved3 : 1; ++ /** Non Zero Length Status OUT Handshake */ ++#define DWC_DCFG_SEND_STALL 1 ++ unsigned nzstsouthshk : 1; ++ /** Device Speed */ ++ unsigned devspd : 2; ++ } b; ++} dcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Control ++ * Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. ++ */ ++typedef union dctl_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 20; ++ /** Power-On Programming Done */ ++ unsigned pwronprgdone : 1; ++ /** Clear Global OUT NAK */ ++ unsigned cgoutnak : 1; ++ /** Set Global OUT NAK */ ++ unsigned sgoutnak : 1; ++ /** Clear Global Non-Periodic IN NAK */ ++ unsigned cgnpinnak : 1; ++ /** Set Global Non-Periodic IN NAK */ ++ unsigned sgnpinnak : 1; ++ /** Test Control */ ++ unsigned tstctl : 3; ++ /** Global OUT NAK Status */ ++ unsigned goutnaksts : 1; ++ /** Global Non-Periodic IN NAK Status */ ++ unsigned gnpinnaksts : 1; ++ /** Soft Disconnect */ ++ unsigned sftdiscon : 1; ++ /** Remote Wakeup */ ++ unsigned rmtwkupsig : 1; ++ } b; ++} dctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device Status ++ * Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. ++ */ ++typedef union dsts_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved22_31 : 10; ++ /** Frame or Microframe Number of the received SOF */ ++ unsigned soffn : 14; ++ unsigned reserved4_7: 4; ++ /** Erratic Error */ ++ unsigned errticerr : 1; ++ /** Enumerated Speed */ ++#define DWC_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0 ++#define DWC_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1 ++#define DWC_DSTS_ENUMSPD_LS_PHY_6MHZ 2 ++#define DWC_DSTS_ENUMSPD_FS_PHY_48MHZ 3 ++ unsigned enumspd : 2; ++ /** Suspend Status */ ++ unsigned suspsts : 1; ++ } b; ++} dsts_data_t; ++ ++ ++/** ++ * This union represents the bit fields in the Device IN EP Interrupt ++ * Register and the Device IN EP Common Mask Register. ++ * ++ * - Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. ++ */ ++typedef union diepint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved07_31 : 23; ++ unsigned txfifoundrn : 1; ++ /** IN Endpoint HAK Effective mask */ ++ unsigned emptyintr : 1; ++ /** IN Endpoint NAK Effective mask */ ++ unsigned inepnakeff : 1; ++ /** IN Token Received with EP mismatch mask */ ++ unsigned intknepmis : 1; ++ /** IN Token received with TxF Empty mask */ ++ unsigned intktxfemp : 1; ++ /** TimeOUT Handshake mask (non-ISOC EPs) */ ++ unsigned timeout : 1; ++ /** AHB Error mask */ ++ unsigned ahberr : 1; ++ /** Endpoint disable mask */ ++ unsigned epdisabled : 1; ++ /** Transfer complete mask */ ++ unsigned xfercompl : 1; ++ } b; ++} diepint_data_t; ++/** ++ * This union represents the bit fields in the Device IN EP Common ++ * Interrupt Mask Register. ++ */ ++typedef union diepint_data diepmsk_data_t; ++ ++/** ++ * This union represents the bit fields in the Device OUT EP Interrupt ++ * Registerand Device OUT EP Common Interrupt Mask Register. ++ * ++ * - Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. ++ */ ++typedef union doepint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved04_31 : 27; ++ /** OUT Token Received when Endpoint Disabled */ ++ unsigned outtknepdis : 1; ++ /** Setup Phase Done (contorl EPs) */ ++ unsigned setup : 1; ++ /** AHB Error */ ++ unsigned ahberr : 1; ++ /** Endpoint disable */ ++ unsigned epdisabled : 1; ++ /** Transfer complete */ ++ unsigned xfercompl : 1; ++ } b; ++} doepint_data_t; ++/** ++ * This union represents the bit fields in the Device OUT EP Common ++ * Interrupt Mask Register. ++ */ ++typedef union doepint_data doepmsk_data_t; ++ ++ ++/** ++ * This union represents the bit fields in the Device All EP Interrupt ++ * and Mask Registers. ++ * - Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. ++ */ ++typedef union daint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** OUT Endpoint bits */ ++ unsigned out : 16; ++ /** IN Endpoint bits */ ++ unsigned in : 16; ++ } ep; ++ struct { ++ /** OUT Endpoint bits */ ++ unsigned outep15 : 1; ++ unsigned outep14 : 1; ++ unsigned outep13 : 1; ++ unsigned outep12 : 1; ++ unsigned outep11 : 1; ++ unsigned outep10 : 1; ++ unsigned outep9 : 1; ++ unsigned outep8 : 1; ++ unsigned outep7 : 1; ++ unsigned outep6 : 1; ++ unsigned outep5 : 1; ++ unsigned outep4 : 1; ++ unsigned outep3 : 1; ++ unsigned outep2 : 1; ++ unsigned outep1 : 1; ++ unsigned outep0 : 1; ++ /** IN Endpoint bits */ ++ unsigned inep15 : 1; ++ unsigned inep14 : 1; ++ unsigned inep13 : 1; ++ unsigned inep12 : 1; ++ unsigned inep11 : 1; ++ unsigned inep10 : 1; ++ unsigned inep9 : 1; ++ unsigned inep8 : 1; ++ unsigned inep7 : 1; ++ unsigned inep6 : 1; ++ unsigned inep5 : 1; ++ unsigned inep4 : 1; ++ unsigned inep3 : 1; ++ unsigned inep2 : 1; ++ unsigned inep1 : 1; ++ unsigned inep0 : 1; ++ } b; ++} daint_data_t; ++ ++/** ++ * This union represents the bit fields in the Device IN Token Queue ++ * Read Registers. ++ * - Read the register into the <i>d32</i> member. ++ * - READ-ONLY Register ++ */ ++typedef union dtknq1_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** EP Numbers of IN Tokens 0 ... 4 */ ++ unsigned epnums0_5 : 24; ++ /** write pointer has wrapped. */ ++ unsigned wrap_bit : 1; ++ /** Reserved */ ++ unsigned reserved05_06 : 2; ++ /** In Token Queue Write Pointer */ ++ unsigned intknwptr : 5; ++ }b; ++} dtknq1_data_t; ++ ++/** ++ * This union represents Threshold control Register ++ * - Read and write the register into the <i>d32</i> member. ++ * - READ-WRITABLE Register ++ */ ++typedef union dthrctl_data //* /*fscz */ ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Reserved */ ++ unsigned reserved26_31 : 6; ++ /** Rx Thr. Length */ ++ unsigned rx_thr_len : 9; ++ /** Rx Thr. Enable */ ++ unsigned rx_thr_en : 1; ++ /** Reserved */ ++ unsigned reserved11_15 : 5; ++ /** Tx Thr. Length */ ++ unsigned tx_thr_len : 9; ++ /** ISO Tx Thr. Enable */ ++ unsigned iso_thr_en : 1; ++ /** non ISO Tx Thr. Enable */ ++ unsigned non_iso_thr_en : 1; ++ ++ }b; ++} dthrctl_data_t; ++ ++/** ++ * Device Logical IN Endpoint-Specific Registers. <i>Offsets ++ * 900h-AFCh</i> ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * <i>These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown.</i> ++ */ ++typedef struct dwc_otg_dev_in_ep_regs ++{ ++ /** Device IN Endpoint Control Register. <i>Offset:900h + ++ * (ep_num * 20h) + 00h</i> */ ++ volatile uint32_t diepctl; ++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 04h</i> */ ++ uint32_t reserved04; ++ /** Device IN Endpoint Interrupt Register. <i>Offset:900h + ++ * (ep_num * 20h) + 08h</i> */ ++ volatile uint32_t diepint; ++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 0Ch</i> */ ++ uint32_t reserved0C; ++ /** Device IN Endpoint Transfer Size ++ * Register. <i>Offset:900h + (ep_num * 20h) + 10h</i> */ ++ volatile uint32_t dieptsiz; ++ /** Device IN Endpoint DMA Address Register. <i>Offset:900h + ++ * (ep_num * 20h) + 14h</i> */ ++ volatile uint32_t diepdma; ++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 18h - 900h + ++ * (ep_num * 20h) + 1Ch</i>*/ ++ volatile uint32_t dtxfsts; ++ /** Reserved. <i>Offset:900h + (ep_num * 20h) + 1Ch - 900h + ++ * (ep_num * 20h) + 1Ch</i>*/ ++ uint32_t reserved18; ++} dwc_otg_dev_in_ep_regs_t; ++ ++/** ++ * Device Logical OUT Endpoint-Specific Registers. <i>Offsets: ++ * B00h-CFCh</i> ++ * ++ * There will be one set of endpoint registers per logical endpoint ++ * implemented. ++ * ++ * <i>These registers are visible only in Device mode and must not be ++ * accessed in Host mode, as the results are unknown.</i> ++ */ ++typedef struct dwc_otg_dev_out_ep_regs ++{ ++ /** Device OUT Endpoint Control Register. <i>Offset:B00h + ++ * (ep_num * 20h) + 00h</i> */ ++ volatile uint32_t doepctl; ++ /** Device OUT Endpoint Frame number Register. <i>Offset: ++ * B00h + (ep_num * 20h) + 04h</i> */ ++ volatile uint32_t doepfn; ++ /** Device OUT Endpoint Interrupt Register. <i>Offset:B00h + ++ * (ep_num * 20h) + 08h</i> */ ++ volatile uint32_t doepint; ++ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 0Ch</i> */ ++ uint32_t reserved0C; ++ /** Device OUT Endpoint Transfer Size Register. <i>Offset: ++ * B00h + (ep_num * 20h) + 10h</i> */ ++ volatile uint32_t doeptsiz; ++ /** Device OUT Endpoint DMA Address Register. <i>Offset:B00h ++ * + (ep_num * 20h) + 14h</i> */ ++ volatile uint32_t doepdma; ++ /** Reserved. <i>Offset:B00h + (ep_num * 20h) + 18h - B00h + ++ * (ep_num * 20h) + 1Ch</i> */ ++ uint32_t unused[2]; ++} dwc_otg_dev_out_ep_regs_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Control ++ * Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. ++ */ ++typedef union depctl_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Endpoint Enable */ ++ unsigned epena : 1; ++ /** Endpoint Disable */ ++ unsigned epdis : 1; ++ /** Set DATA1 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA1 Set Odd ++ * (micro)frame (SetOddFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to odd (micro) frame. ++ */ ++ unsigned setd1pid : 1; ++ /** Set DATA0 PID (INTR/Bulk IN and OUT endpoints) ++ * Writing to this field sets the Endpoint DPID (DPID) ++ * field in this register to DATA0. Set Even ++ * (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints) ++ * Writing to this field sets the Even/Odd ++ * (micro)frame (EO_FrNum) field to even (micro) ++ * frame. ++ */ ++ unsigned setd0pid : 1; ++ /** Set NAK */ ++ unsigned snak : 1; ++ /** Clear NAK */ ++ unsigned cnak : 1; ++ /** Tx Fifo Number ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned txfnum : 4; ++ /** Stall Handshake */ ++ unsigned stall : 1; ++ /** Snoop Mode ++ * OUT EPn/OUT EP0 ++ * IN EPn/IN EP0 - reserved */ ++ unsigned snp : 1; ++ /** Endpoint Type ++ * 2'b00: Control ++ * 2'b01: Isochronous ++ * 2'b10: Bulk ++ * 2'b11: Interrupt */ ++ unsigned eptype : 2; ++ /** NAK Status */ ++ unsigned naksts : 1; ++ /** Endpoint DPID (INTR/Bulk IN and OUT endpoints) ++ * This field contains the PID of the packet going to ++ * be received or transmitted on this endpoint. The ++ * application should program the PID of the first ++ * packet going to be received or transmitted on this ++ * endpoint , after the endpoint is ++ * activated. Application use the SetD1PID and ++ * SetD0PID fields of this register to program either ++ * D0 or D1 PID. ++ * ++ * The encoding for this field is ++ * - 0: D0 ++ * - 1: D1 ++ */ ++ unsigned dpid : 1; ++ /** USB Active Endpoint */ ++ unsigned usbactep : 1; ++ /** Next Endpoint ++ * IN EPn/IN EP0 ++ * OUT EPn/OUT EP0 - reserved */ ++ unsigned nextep : 4; ++ /** Maximum Packet Size ++ * IN/OUT EPn ++ * IN/OUT EP0 - 2 bits ++ * 2'b00: 64 Bytes ++ * 2'b01: 32 ++ * 2'b10: 16 ++ * 2'b11: 8 */ ++#define DWC_DEP0CTL_MPS_64 0 ++#define DWC_DEP0CTL_MPS_32 1 ++#define DWC_DEP0CTL_MPS_16 2 ++#define DWC_DEP0CTL_MPS_8 3 ++ unsigned mps : 11; ++ } b; ++} depctl_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP Transfer ++ * Size Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. ++ */ ++typedef union deptsiz_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 1; ++ /** Multi Count - Periodic IN endpoints */ ++ unsigned mc : 2; ++ /** Packet Count */ ++ unsigned pktcnt : 10; ++ /** Transfer size */ ++ unsigned xfersize : 19; ++ } b; ++} deptsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Device EP 0 Transfer ++ * Size Register. Read the register into the <i>d32</i> member then ++ * set/clear the bits using the <i>b</i>it elements. ++ */ ++typedef union deptsiz0_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved31 : 1; ++ /**Setup Packet Count (DOEPTSIZ0 Only) */ ++ unsigned supcnt : 2; ++ /** Reserved */ ++ unsigned reserved28_20 : 9; ++ /** Packet Count */ ++ unsigned pktcnt : 1; ++ /** Reserved */ ++ unsigned reserved18_7 : 12; ++ /** Transfer size */ ++ unsigned xfersize : 7; ++ } b; ++} deptsiz0_data_t; ++ ++ ++/** Maximum number of Periodic FIFOs */ ++#define MAX_PERIO_FIFOS 15 ++/** Maximum number of TX FIFOs */ ++#define MAX_TX_FIFOS 15 ++/** Maximum number of Endpoints/HostChannels */ ++#define MAX_EPS_CHANNELS 16 ++//#define MAX_EPS_CHANNELS 4 ++ ++/** ++ * The dwc_otg_dev_if structure contains information needed to manage ++ * the DWC_otg controller acting in device mode. It represents the ++ * programming view of the device-specific aspects of the controller. ++ */ ++typedef struct dwc_otg_dev_if { ++ /** Pointer to device Global registers. ++ * Device Global Registers starting at offset 800h ++ */ ++ dwc_otg_device_global_regs_t *dev_global_regs; ++#define DWC_DEV_GLOBAL_REG_OFFSET 0x800 ++ ++ /** ++ * Device Logical IN Endpoint-Specific Registers 900h-AFCh ++ */ ++ dwc_otg_dev_in_ep_regs_t *in_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_IN_EP_REG_OFFSET 0x900 ++#define DWC_EP_REG_OFFSET 0x20 ++ ++ /** Device Logical OUT Endpoint-Specific Registers B00h-CFCh */ ++ dwc_otg_dev_out_ep_regs_t *out_ep_regs[MAX_EPS_CHANNELS]; ++#define DWC_DEV_OUT_EP_REG_OFFSET 0xB00 ++ ++ /* Device configuration information*/ ++ uint8_t speed; /**< Device Speed 0: Unknown, 1: LS, 2:FS, 3: HS */ ++ //uint8_t num_eps; /**< Number of EPs range: 0-16 (includes EP0) */ ++ //uint8_t num_perio_eps; /**< # of Periodic EP range: 0-15 */ ++ /*fscz */ ++ uint8_t num_in_eps; /**< Number # of Tx EP range: 0-15 exept ep0 */ ++ uint8_t num_out_eps; /**< Number # of Rx EP range: 0-15 exept ep 0*/ ++ ++ /** Size of periodic FIFOs (Bytes) */ ++ uint16_t perio_tx_fifo_size[MAX_PERIO_FIFOS]; ++ ++ /** Size of Tx FIFOs (Bytes) */ ++ uint16_t tx_fifo_size[MAX_TX_FIFOS]; ++ ++ /** Thresholding enable flags and length varaiables **/ ++ uint16_t rx_thr_en; ++ uint16_t iso_tx_thr_en; ++ uint16_t non_iso_tx_thr_en; ++ ++ uint16_t rx_thr_length; ++ uint16_t tx_thr_length; ++} dwc_otg_dev_if_t; ++ ++/** ++ * This union represents the bit fields in the Power and Clock Gating Control ++ * Register. Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. ++ */ ++typedef union pcgcctl_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned reserved31_05 : 27; ++ /** PHY Suspended */ ++ unsigned physuspended : 1; ++ /** Reset Power Down Modules */ ++ unsigned rstpdwnmodule : 1; ++ /** Power Clamp */ ++ unsigned pwrclmp : 1; ++ /** Gate Hclk */ ++ unsigned gatehclk : 1; ++ /** Stop Pclk */ ++ unsigned stoppclk : 1; ++ } b; ++} pcgcctl_data_t; ++ ++///////////////////////////////////////////////// ++// Host Mode Register Structures ++// ++/** ++ * The Host Global Registers structure defines the size and relative ++ * field offsets for the Host Mode Global Registers. Host Global ++ * Registers offsets 400h-7FFh. ++*/ ++typedef struct dwc_otg_host_global_regs ++{ ++ /** Host Configuration Register. <i>Offset: 400h</i> */ ++ volatile uint32_t hcfg; ++ /** Host Frame Interval Register. <i>Offset: 404h</i> */ ++ volatile uint32_t hfir; ++ /** Host Frame Number / Frame Remaining Register. <i>Offset: 408h</i> */ ++ volatile uint32_t hfnum; ++ /** Reserved. <i>Offset: 40Ch</i> */ ++ uint32_t reserved40C; ++ /** Host Periodic Transmit FIFO/ Queue Status Register. <i>Offset: 410h</i> */ ++ volatile uint32_t hptxsts; ++ /** Host All Channels Interrupt Register. <i>Offset: 414h</i> */ ++ volatile uint32_t haint; ++ /** Host All Channels Interrupt Mask Register. <i>Offset: 418h</i> */ ++ volatile uint32_t haintmsk; ++} dwc_otg_host_global_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Configuration Register. ++ * Read the register into the <i>d32</i> member then set/clear the bits using ++ * the <i>b</i>it elements. Write the <i>d32</i> member to the hcfg register. ++ */ ++typedef union hcfg_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Reserved */ ++ //unsigned reserved31_03 : 29; ++ /** FS/LS Only Support */ ++ unsigned fslssupp : 1; ++ /** FS/LS Phy Clock Select */ ++#define DWC_HCFG_30_60_MHZ 0 ++#define DWC_HCFG_48_MHZ 1 ++#define DWC_HCFG_6_MHZ 2 ++ unsigned fslspclksel : 2; ++ } b; ++} hcfg_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfir_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned reserved : 16; ++ unsigned frint : 16; ++ } b; ++} hfir_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Frame Remaing/Number ++ * Register. ++ */ ++typedef union hfnum_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned frrem : 16; ++#define DWC_HFNUM_MAX_FRNUM 0x3FFF ++ unsigned frnum : 16; ++ } b; ++} hfnum_data_t; ++ ++typedef union hptxsts_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Top of the Periodic Transmit Request Queue ++ * - bit 24 - Terminate (last entry for the selected channel) ++ * - bits 26:25 - Token Type ++ * - 2'b00 - Zero length ++ * - 2'b01 - Ping ++ * - 2'b10 - Disable ++ * - bits 30:27 - Channel Number ++ * - bit 31 - Odd/even microframe ++ */ ++ unsigned ptxqtop_odd : 1; ++ unsigned ptxqtop_chnum : 4; ++ unsigned ptxqtop_token : 2; ++ unsigned ptxqtop_terminate : 1; ++ unsigned ptxqspcavail : 8; ++ unsigned ptxfspcavail : 16; ++ } b; ++} hptxsts_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Port Control and Status ++ * Register. Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the ++ * hprt0 register. ++ */ ++typedef union hprt0_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved19_31 : 13; ++#define DWC_HPRT0_PRTSPD_HIGH_SPEED 0 ++#define DWC_HPRT0_PRTSPD_FULL_SPEED 1 ++#define DWC_HPRT0_PRTSPD_LOW_SPEED 2 ++ unsigned prtspd : 2; ++ unsigned prttstctl : 4; ++ unsigned prtpwr : 1; ++ unsigned prtlnsts : 2; ++ unsigned reserved9 : 1; ++ unsigned prtrst : 1; ++ unsigned prtsusp : 1; ++ unsigned prtres : 1; ++ unsigned prtovrcurrchng : 1; ++ unsigned prtovrcurract : 1; ++ unsigned prtenchng : 1; ++ unsigned prtena : 1; ++ unsigned prtconndet : 1; ++ unsigned prtconnsts : 1; ++ } b; ++} hprt0_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 16; ++ unsigned ch15 : 1; ++ unsigned ch14 : 1; ++ unsigned ch13 : 1; ++ unsigned ch12 : 1; ++ unsigned ch11 : 1; ++ unsigned ch10 : 1; ++ unsigned ch9 : 1; ++ unsigned ch8 : 1; ++ unsigned ch7 : 1; ++ unsigned ch6 : 1; ++ unsigned ch5 : 1; ++ unsigned ch4 : 1; ++ unsigned ch3 : 1; ++ unsigned ch2 : 1; ++ unsigned ch1 : 1; ++ unsigned ch0 : 1; ++ } b; ++ struct { ++ unsigned reserved : 16; ++ unsigned chint : 16; ++ } b2; ++} haint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union haintmsk_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ unsigned reserved : 16; ++ unsigned ch15 : 1; ++ unsigned ch14 : 1; ++ unsigned ch13 : 1; ++ unsigned ch12 : 1; ++ unsigned ch11 : 1; ++ unsigned ch10 : 1; ++ unsigned ch9 : 1; ++ unsigned ch8 : 1; ++ unsigned ch7 : 1; ++ unsigned ch6 : 1; ++ unsigned ch5 : 1; ++ unsigned ch4 : 1; ++ unsigned ch3 : 1; ++ unsigned ch2 : 1; ++ unsigned ch1 : 1; ++ unsigned ch0 : 1; ++ } b; ++ struct { ++ unsigned reserved : 16; ++ unsigned chint : 16; ++ } b2; ++} haintmsk_data_t; ++ ++/** ++ * Host Channel Specific Registers. <i>500h-5FCh</i> ++ */ ++typedef struct dwc_otg_hc_regs ++{ ++ /** Host Channel 0 Characteristic Register. <i>Offset: 500h + (chan_num * 20h) + 00h</i> */ ++ volatile uint32_t hcchar; ++ /** Host Channel 0 Split Control Register. <i>Offset: 500h + (chan_num * 20h) + 04h</i> */ ++ volatile uint32_t hcsplt; ++ /** Host Channel 0 Interrupt Register. <i>Offset: 500h + (chan_num * 20h) + 08h</i> */ ++ volatile uint32_t hcint; ++ /** Host Channel 0 Interrupt Mask Register. <i>Offset: 500h + (chan_num * 20h) + 0Ch</i> */ ++ volatile uint32_t hcintmsk; ++ /** Host Channel 0 Transfer Size Register. <i>Offset: 500h + (chan_num * 20h) + 10h</i> */ ++ volatile uint32_t hctsiz; ++ /** Host Channel 0 DMA Address Register. <i>Offset: 500h + (chan_num * 20h) + 14h</i> */ ++ volatile uint32_t hcdma; ++ /** Reserved. <i>Offset: 500h + (chan_num * 20h) + 18h - 500h + (chan_num * 20h) + 1Ch</i> */ ++ uint32_t reserved[2]; ++} dwc_otg_hc_regs_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Characteristics ++ * Register. Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the ++ * hcchar register. ++ */ ++typedef union hcchar_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Channel enable */ ++ unsigned chen : 1; ++ /** Channel disable */ ++ unsigned chdis : 1; ++ /** ++ * Frame to transmit periodic transaction. ++ * 0: even, 1: odd ++ */ ++ unsigned oddfrm : 1; ++ /** Device address */ ++ unsigned devaddr : 7; ++ /** Packets per frame for periodic transfers. 0 is reserved. */ ++ unsigned multicnt : 2; ++ /** 0: Control, 1: Isoc, 2: Bulk, 3: Intr */ ++ unsigned eptype : 2; ++ /** 0: Full/high speed device, 1: Low speed device */ ++ unsigned lspddev : 1; ++ unsigned reserved : 1; ++ /** 0: OUT, 1: IN */ ++ unsigned epdir : 1; ++ /** Endpoint number */ ++ unsigned epnum : 4; ++ /** Maximum packet size in bytes */ ++ unsigned mps : 11; ++ } b; ++} hcchar_data_t; ++ ++typedef union hcsplt_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Split Enble */ ++ unsigned spltena : 1; ++ /** Reserved */ ++ unsigned reserved : 14; ++ /** Do Complete Split */ ++ unsigned compsplt : 1; ++ /** Transaction Position */ ++#define DWC_HCSPLIT_XACTPOS_MID 0 ++#define DWC_HCSPLIT_XACTPOS_END 1 ++#define DWC_HCSPLIT_XACTPOS_BEGIN 2 ++#define DWC_HCSPLIT_XACTPOS_ALL 3 ++ unsigned xactpos : 2; ++ /** Hub Address */ ++ unsigned hubaddr : 7; ++ /** Port Address */ ++ unsigned prtaddr : 7; ++ } b; ++} hcsplt_data_t; ++ ++ ++/** ++ * This union represents the bit fields in the Host All Interrupt ++ * Register. ++ */ ++typedef union hcint_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ /** register bits */ ++ struct { ++ /** Reserved */ ++ unsigned reserved : 21; ++ /** Data Toggle Error */ ++ unsigned datatglerr : 1; ++ /** Frame Overrun */ ++ unsigned frmovrun : 1; ++ /** Babble Error */ ++ unsigned bblerr : 1; ++ /** Transaction Err */ ++ unsigned xacterr : 1; ++ /** NYET Response Received */ ++ unsigned nyet : 1; ++ /** ACK Response Received */ ++ unsigned ack : 1; ++ /** NAK Response Received */ ++ unsigned nak : 1; ++ /** STALL Response Received */ ++ unsigned stall : 1; ++ /** AHB Error */ ++ unsigned ahberr : 1; ++ /** Channel Halted */ ++ unsigned chhltd : 1; ++ /** Transfer Complete */ ++ unsigned xfercomp : 1; ++ } b; ++} hcint_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Transfer Size ++ * Register. Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the ++ * hcchar register. ++ */ ++typedef union hctsiz_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ /** Do PING protocol when 1 */ ++ unsigned dopng : 1; ++ /** ++ * Packet ID for next data packet ++ * 0: DATA0 ++ * 1: DATA2 ++ * 2: DATA1 ++ * 3: MDATA (non-Control), SETUP (Control) ++ */ ++#define DWC_HCTSIZ_DATA0 0 ++#define DWC_HCTSIZ_DATA1 2 ++#define DWC_HCTSIZ_DATA2 1 ++#define DWC_HCTSIZ_MDATA 3 ++#define DWC_HCTSIZ_SETUP 3 ++ unsigned pid : 2; ++ /** Data packets to transfer */ ++ unsigned pktcnt : 10; ++ /** Total transfer size in bytes */ ++ unsigned xfersize : 19; ++ } b; ++} hctsiz_data_t; ++ ++/** ++ * This union represents the bit fields in the Host Channel Interrupt Mask ++ * Register. Read the register into the <i>d32</i> member then set/clear the ++ * bits using the <i>b</i>it elements. Write the <i>d32</i> member to the ++ * hcintmsk register. ++ */ ++typedef union hcintmsk_data ++{ ++ /** raw register data */ ++ uint32_t d32; ++ ++ /** register bits */ ++ struct { ++ unsigned reserved : 21; ++ unsigned datatglerr : 1; ++ unsigned frmovrun : 1; ++ unsigned bblerr : 1; ++ unsigned xacterr : 1; ++ unsigned nyet : 1; ++ unsigned ack : 1; ++ unsigned nak : 1; ++ unsigned stall : 1; ++ unsigned ahberr : 1; ++ unsigned chhltd : 1; ++ unsigned xfercompl : 1; ++ } b; ++} hcintmsk_data_t; ++ ++/** OTG Host Interface Structure. ++ * ++ * The OTG Host Interface Structure structure contains information ++ * needed to manage the DWC_otg controller acting in host mode. It ++ * represents the programming view of the host-specific aspects of the ++ * controller. ++ */ ++typedef struct dwc_otg_host_if { ++ /** Host Global Registers starting at offset 400h.*/ ++ dwc_otg_host_global_regs_t *host_global_regs; ++#define DWC_OTG_HOST_GLOBAL_REG_OFFSET 0x400 ++ ++ /** Host Port 0 Control and Status Register */ ++ volatile uint32_t *hprt0; ++#define DWC_OTG_HOST_PORT_REGS_OFFSET 0x440 ++ ++ ++ /** Host Channel Specific Registers at offsets 500h-5FCh. */ ++ dwc_otg_hc_regs_t *hc_regs[MAX_EPS_CHANNELS]; ++#define DWC_OTG_HOST_CHAN_REGS_OFFSET 0x500 ++#define DWC_OTG_CHAN_REGS_OFFSET 0x20 ++ ++ ++ /* Host configuration information */ ++ /** Number of Host Channels (range: 1-16) */ ++ uint8_t num_host_channels; ++ /** Periodic EPs supported (0: no, 1: yes) */ ++ uint8_t perio_eps_supported; ++ /** Periodic Tx FIFO Size (Only 1 host periodic Tx FIFO) */ ++ uint16_t perio_tx_fifo_size; ++ ++} dwc_otg_host_if_t; ++ ++#endif diff --git a/target/linux/lantiq/patches/0019-MIPS-lantiq-adds-VPE-extensions.patch b/target/linux/lantiq/patches/0019-MIPS-lantiq-adds-VPE-extensions.patch new file mode 100644 index 0000000000..1bd4c5b4e8 --- /dev/null +++ b/target/linux/lantiq/patches/0019-MIPS-lantiq-adds-VPE-extensions.patch @@ -0,0 +1,1198 @@ +From c6c810d83f0d95f54c3a6b338d219cec7ccef4c9 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 20:30:40 +0200 +Subject: [PATCH 19/24] MIPS: lantiq: adds VPE extensions + +--- + arch/mips/Kconfig | 22 +++ + arch/mips/include/asm/mipsmtregs.h | 54 +++++++ + arch/mips/kernel/Makefile | 3 +- + arch/mips/kernel/mips-mt.c | 97 +++++++++++-- + arch/mips/kernel/mtsched_proc.c | 279 ++++++++++++++++++++++++++++++++++++ + arch/mips/kernel/perf_proc.c | 191 ++++++++++++++++++++++++ + arch/mips/kernel/proc.c | 17 +++ + arch/mips/kernel/smtc.c | 7 + + arch/mips/kernel/vpe.c | 250 ++++++++++++++++++++++++++++++++- + 9 files changed, 905 insertions(+), 15 deletions(-) + create mode 100644 arch/mips/kernel/mtsched_proc.c + create mode 100644 arch/mips/kernel/perf_proc.c + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1915,6 +1915,28 @@ config MIPS_VPE_LOADER + Includes a loader for loading an elf relocatable object + onto another VPE and running it. + ++config IFX_VPE_EXT ++ bool "IFX APRP Extensions" ++ depends on MIPS_VPE_LOADER ++ default y ++ help ++ IFX included extensions in APRP ++ ++config PERFCTRS ++ bool "34K Performance counters" ++ depends on MIPS_MT && PROC_FS ++ default n ++ help ++ 34K Performance counter through /proc ++ ++config MTSCHED ++ bool "Support mtsched priority configuration for TCs" ++ depends on MIPS_MT && PROC_FS ++ default y ++ help ++ Support for mtsched priority configuration for TCs through ++ /proc/mips/mtsched ++ + config MIPS_MT_SMTC_IM_BACKSTOP + bool "Use per-TC register bits as backstop for inhibited IM bits" + depends on MIPS_MT_SMTC +--- a/arch/mips/include/asm/mipsmtregs.h ++++ b/arch/mips/include/asm/mipsmtregs.h +@@ -28,14 +28,34 @@ + #define read_c0_vpeconf0() __read_32bit_c0_register($1, 2) + #define write_c0_vpeconf0(val) __write_32bit_c0_register($1, 2, val) + ++#define read_c0_vpeconf1() __read_32bit_c0_register($1, 3) ++#define write_c0_vpeconf1(val) __write_32bit_c0_register($1, 3, val) ++ ++#define read_c0_vpeschedule() __read_32bit_c0_register($1, 5) ++#define write_c0_vpeschedule(val) __write_32bit_c0_register($1, 5, val) ++ ++#define read_c0_vpeschefback() __read_32bit_c0_register($1, 6) ++#define write_c0_vpeschefback(val) __write_32bit_c0_register($1, 6, val) ++ ++#define read_c0_vpeopt() __read_32bit_c0_register($1, 7) ++#define write_c0_vpeopt(val) __write_32bit_c0_register($1, 7, val) ++ + #define read_c0_tcstatus() __read_32bit_c0_register($2, 1) + #define write_c0_tcstatus(val) __write_32bit_c0_register($2, 1, val) + + #define read_c0_tcbind() __read_32bit_c0_register($2, 2) ++#define write_c0_tcbind(val) __write_32bit_c0_register($2, 2, val) + + #define read_c0_tccontext() __read_32bit_c0_register($2, 5) + #define write_c0_tccontext(val) __write_32bit_c0_register($2, 5, val) + ++#define read_c0_tcschedule() __read_32bit_c0_register($2, 6) ++#define write_c0_tcschedule(val) __write_32bit_c0_register($2, 6, val) ++ ++#define read_c0_tcschefback() __read_32bit_c0_register($2, 7) ++#define write_c0_tcschefback(val) __write_32bit_c0_register($2, 7, val) ++ ++ + #else /* Assembly */ + /* + * Macros for use in assembly language code +@@ -74,6 +94,8 @@ + #define MVPCONTROL_STLB_SHIFT 2 + #define MVPCONTROL_STLB (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT) + ++#define MVPCONTROL_CPA_SHIFT 3 ++#define MVPCONTROL_CPA (_ULCAST_(1) << MVPCONTROL_CPA_SHIFT) + + /* MVPConf0 fields */ + #define MVPCONF0_PTC_SHIFT 0 +@@ -84,6 +106,8 @@ + #define MVPCONF0_TCA ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT) + #define MVPCONF0_PTLBE_SHIFT 16 + #define MVPCONF0_PTLBE (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT) ++#define MVPCONF0_PCP_SHIFT 27 ++#define MVPCONF0_PCP (_ULCAST_(1) << MVPCONF0_PCP_SHIFT) + #define MVPCONF0_TLBS_SHIFT 29 + #define MVPCONF0_TLBS (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT) + #define MVPCONF0_M_SHIFT 31 +@@ -121,9 +145,25 @@ + #define VPECONF0_VPA (_ULCAST_(1) << VPECONF0_VPA_SHIFT) + #define VPECONF0_MVP_SHIFT 1 + #define VPECONF0_MVP (_ULCAST_(1) << VPECONF0_MVP_SHIFT) ++#define VPECONF0_ICS_SHIFT 16 ++#define VPECONF0_ICS (_ULCAST_(1) << VPECONF0_ICS_SHIFT) ++#define VPECONF0_DCS_SHIFT 17 ++#define VPECONF0_DCS (_ULCAST_(1) << VPECONF0_DCS_SHIFT) + #define VPECONF0_XTC_SHIFT 21 + #define VPECONF0_XTC (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT) + ++/* VPEOpt fields */ ++#define VPEOPT_DWX_SHIFT 0 ++#define VPEOPT_IWX_SHIFT 8 ++#define VPEOPT_IWX0 ( _ULCAST_(0x1) << VPEOPT_IWX_SHIFT) ++#define VPEOPT_IWX1 ( _ULCAST_(0x2) << VPEOPT_IWX_SHIFT) ++#define VPEOPT_IWX2 ( _ULCAST_(0x4) << VPEOPT_IWX_SHIFT) ++#define VPEOPT_IWX3 ( _ULCAST_(0x8) << VPEOPT_IWX_SHIFT) ++#define VPEOPT_DWX0 ( _ULCAST_(0x1) << VPEOPT_DWX_SHIFT) ++#define VPEOPT_DWX1 ( _ULCAST_(0x2) << VPEOPT_DWX_SHIFT) ++#define VPEOPT_DWX2 ( _ULCAST_(0x4) << VPEOPT_DWX_SHIFT) ++#define VPEOPT_DWX3 ( _ULCAST_(0x8) << VPEOPT_DWX_SHIFT) ++ + /* TCStatus fields (per TC) */ + #define TCSTATUS_TASID (_ULCAST_(0xff)) + #define TCSTATUS_IXMT_SHIFT 10 +@@ -350,6 +390,14 @@ do { \ + #define write_vpe_c0_vpecontrol(val) mttc0(1, 1, val) + #define read_vpe_c0_vpeconf0() mftc0(1, 2) + #define write_vpe_c0_vpeconf0(val) mttc0(1, 2, val) ++#define read_vpe_c0_vpeschedule() mftc0(1, 5) ++#define write_vpe_c0_vpeschedule(val) mttc0(1, 5, val) ++#define read_vpe_c0_vpeschefback() mftc0(1, 6) ++#define write_vpe_c0_vpeschefback(val) mttc0(1, 6, val) ++#define read_vpe_c0_vpeopt() mftc0(1, 7) ++#define write_vpe_c0_vpeopt(val) mttc0(1, 7, val) ++#define read_vpe_c0_wired() mftc0(6, 0) ++#define write_vpe_c0_wired(val) mttc0(6, 0, val) + #define read_vpe_c0_count() mftc0(9, 0) + #define write_vpe_c0_count(val) mttc0(9, 0, val) + #define read_vpe_c0_status() mftc0(12, 0) +@@ -381,6 +429,12 @@ do { \ + #define write_tc_c0_tchalt(val) mttc0(2, 4, val) + #define read_tc_c0_tccontext() mftc0(2, 5) + #define write_tc_c0_tccontext(val) mttc0(2, 5, val) ++#define read_tc_c0_tcschedule() mftc0(2, 6) ++#define write_tc_c0_tcschedule(val) mttc0(2, 6, val) ++#define read_tc_c0_tcschefback() mftc0(2, 7) ++#define write_tc_c0_tcschefback(val) mttc0(2, 7, val) ++#define read_tc_c0_entryhi() mftc0(10, 0) ++#define write_tc_c0_entryhi(val) mttc0(10, 0, val) + + /* GPR */ + #define read_tc_gpr_sp() mftgpr(29) +--- a/arch/mips/kernel/Makefile ++++ b/arch/mips/kernel/Makefile +@@ -86,7 +86,8 @@ obj-$(CONFIG_MIPS32_O32) += binfmt_elfo3 + + obj-$(CONFIG_KGDB) += kgdb.o + obj-$(CONFIG_PROC_FS) += proc.o +- ++obj-$(CONFIG_MTSCHED) += mtsched_proc.o ++obj-$(CONFIG_PERFCTRS) += perf_proc.o + obj-$(CONFIG_64BIT) += cpu-bugs64.o + + obj-$(CONFIG_I8253) += i8253.o +--- a/arch/mips/kernel/mips-mt.c ++++ b/arch/mips/kernel/mips-mt.c +@@ -21,26 +21,96 @@ + #include <asm/cacheflush.h> + + int vpelimit; +- + static int __init maxvpes(char *str) + { + get_option(&str, &vpelimit); +- + return 1; + } +- + __setup("maxvpes=", maxvpes); + + int tclimit; +- + static int __init maxtcs(char *str) + { + get_option(&str, &tclimit); ++ return 1; ++} ++__setup("maxtcs=", maxtcs); + ++#ifdef CONFIG_IFX_VPE_EXT ++int stlb; ++static int __init istlbshared(char *str) ++{ ++ get_option(&str, &stlb); + return 1; + } ++__setup("vpe_tlb_shared=", istlbshared); + +-__setup("maxtcs=", maxtcs); ++int vpe0_wired; ++static int __init vpe0wired(char *str) ++{ ++ get_option(&str, &vpe0_wired); ++ return 1; ++} ++__setup("vpe0_wired_tlb_entries=", vpe0wired); ++ ++int vpe1_wired; ++static int __init vpe1wired(char *str) ++{ ++ get_option(&str, &vpe1_wired); ++ return 1; ++} ++__setup("vpe1_wired_tlb_entries=", vpe1wired); ++ ++#ifdef CONFIG_MIPS_MT_SMTC ++extern int nostlb; ++#endif ++void configure_tlb(void) ++{ ++ int vpeflags, tcflags, tlbsiz; ++ unsigned int config1val; ++ vpeflags = dvpe(); ++ tcflags = dmt(); ++ write_c0_vpeconf0((read_c0_vpeconf0() | VPECONF0_MVP)); ++ write_c0_mvpcontrol((read_c0_mvpcontrol() | MVPCONTROL_VPC)); ++ mips_ihb(); ++ //printk("stlb = %d, vpe0_wired = %d vpe1_wired=%d\n", stlb,vpe0_wired, vpe1_wired); ++ if (stlb) { ++ if (!(read_c0_mvpconf0() & MVPCONF0_TLBS)) { ++ emt(tcflags); ++ evpe(vpeflags); ++ return; ++ } ++ ++ write_c0_mvpcontrol(read_c0_mvpcontrol() | MVPCONTROL_STLB); ++ write_c0_wired(vpe0_wired + vpe1_wired); ++ if (((read_vpe_c0_config() & MIPS_CONF_MT) >> 7) == 1) { ++ config1val = read_vpe_c0_config1(); ++ tlbsiz = (((config1val >> 25) & 0x3f) + 1); ++ if (tlbsiz > 64) ++ tlbsiz = 64; ++ cpu_data[0].tlbsize = tlbsiz; ++ current_cpu_data.tlbsize = tlbsiz; ++ } ++ ++ } ++ else { ++ write_c0_mvpcontrol(read_c0_mvpcontrol() & ~MVPCONTROL_STLB); ++ write_c0_wired(vpe0_wired); ++ } ++ ++ ehb(); ++ write_c0_mvpcontrol((read_c0_mvpcontrol() & ~MVPCONTROL_VPC)); ++ ehb(); ++ local_flush_tlb_all(); ++ ++ printk("Wired TLB entries for Linux read_c0_wired() = %d\n", read_c0_wired()); ++#ifdef CONFIG_MIPS_MT_SMTC ++ nostlb = !stlb; ++#endif ++ emt(tcflags); ++ evpe(vpeflags); ++} ++#endif + + /* + * Dump new MIPS MT state for the core. Does not leave TCs halted. +@@ -78,18 +148,18 @@ void mips_mt_regdump(unsigned long mvpct + if ((read_tc_c0_tcbind() & TCBIND_CURVPE) == i) { + printk(" VPE %d\n", i); + printk(" VPEControl : %08lx\n", +- read_vpe_c0_vpecontrol()); ++ read_vpe_c0_vpecontrol()); + printk(" VPEConf0 : %08lx\n", +- read_vpe_c0_vpeconf0()); ++ read_vpe_c0_vpeconf0()); + printk(" VPE%d.Status : %08lx\n", +- i, read_vpe_c0_status()); ++ i, read_vpe_c0_status()); + printk(" VPE%d.EPC : %08lx %pS\n", +- i, read_vpe_c0_epc(), +- (void *) read_vpe_c0_epc()); ++ i, read_vpe_c0_epc(), ++ (void *) read_vpe_c0_epc()); + printk(" VPE%d.Cause : %08lx\n", +- i, read_vpe_c0_cause()); ++ i, read_vpe_c0_cause()); + printk(" VPE%d.Config7 : %08lx\n", +- i, read_vpe_c0_config7()); ++ i, read_vpe_c0_config7()); + break; /* Next VPE */ + } + } +@@ -287,6 +357,9 @@ void mips_mt_set_cpuoptions(void) + printk("Mapped %ld ITC cells starting at 0x%08x\n", + ((itcblkgrn & 0x7fe00000) >> 20), itc_base); + } ++#ifdef CONFIG_IFX_VPE_EXT ++ configure_tlb(); ++#endif + } + + /* +--- /dev/null ++++ b/arch/mips/kernel/mtsched_proc.c +@@ -0,0 +1,279 @@ ++/* ++ * /proc hooks for MIPS MT scheduling policy management for 34K cores ++ * ++ * This program is free software; you can distribute it and/or modify it ++ * under the terms of the GNU General Public License (Version 2) as ++ * published by the Free Software Foundation. ++ * ++ * This program is distributed in the hope it will be useful, but WITHOUT ++ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or ++ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License ++ * for more details. ++ * ++ * You should have received a copy of the GNU General Public License along ++ * with this program; if not, write to the Free Software Foundation, Inc., ++ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA. ++ * ++ * Copyright (C) 2006 Mips Technologies, Inc ++ */ ++ ++#include <linux/kernel.h> ++ ++#include <asm/cpu.h> ++#include <asm/processor.h> ++#include <asm/system.h> ++#include <asm/mipsregs.h> ++#include <asm/mipsmtregs.h> ++#include <asm/uaccess.h> ++#include <linux/proc_fs.h> ++ ++static struct proc_dir_entry *mtsched_proc; ++ ++#ifndef CONFIG_MIPS_MT_SMTC ++#define NTCS 2 ++#else ++#define NTCS NR_CPUS ++#endif ++#define NVPES 2 ++ ++int lastvpe = 1; ++int lasttc = 8; ++ ++static int proc_read_mtsched(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int totalen = 0; ++ int len; ++ ++ int i; ++ int vpe; ++ int mytc; ++ unsigned long flags; ++ unsigned int mtflags; ++ unsigned int haltstate; ++ unsigned int vpes_checked[NVPES]; ++ unsigned int vpeschedule[NVPES]; ++ unsigned int vpeschefback[NVPES]; ++ unsigned int tcschedule[NTCS]; ++ unsigned int tcschefback[NTCS]; ++ ++ /* Dump the state of the MIPS MT scheduling policy manager */ ++ /* Inititalize control state */ ++ for(i = 0; i < NVPES; i++) { ++ vpes_checked[i] = 0; ++ vpeschedule[i] = 0; ++ vpeschefback[i] = 0; ++ } ++ for(i = 0; i < NTCS; i++) { ++ tcschedule[i] = 0; ++ tcschefback[i] = 0; ++ } ++ ++ /* Disable interrupts and multithreaded issue */ ++ local_irq_save(flags); ++ mtflags = dvpe(); ++ ++ /* Then go through the TCs, halt 'em, and extract the values */ ++ mytc = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; ++ for(i = 0; i < NTCS; i++) { ++ if(i == mytc) { ++ /* No need to halt ourselves! */ ++ tcschedule[i] = read_c0_tcschedule(); ++ tcschefback[i] = read_c0_tcschefback(); ++ /* If VPE bound to TC hasn't been checked, do it */ ++ vpe = read_c0_tcbind() & TCBIND_CURVPE; ++ if(!vpes_checked[vpe]) { ++ vpeschedule[vpe] = read_c0_vpeschedule(); ++ vpeschefback[vpe] = read_c0_vpeschefback(); ++ vpes_checked[vpe] = 1; ++ } ++ } else { ++ settc(i); ++ haltstate = read_tc_c0_tchalt(); ++ write_tc_c0_tchalt(TCHALT_H); ++ mips_ihb(); ++ tcschedule[i] = read_tc_c0_tcschedule(); ++ tcschefback[i] = read_tc_c0_tcschefback(); ++ /* If VPE bound to TC hasn't been checked, do it */ ++ vpe = read_tc_c0_tcbind() & TCBIND_CURVPE; ++ if(!vpes_checked[vpe]) { ++ vpeschedule[vpe] = read_vpe_c0_vpeschedule(); ++ vpeschefback[vpe] = read_vpe_c0_vpeschefback(); ++ vpes_checked[vpe] = 1; ++ } ++ if(!haltstate) write_tc_c0_tchalt(0); ++ } ++ } ++ /* Re-enable MT and interrupts */ ++ evpe(mtflags); ++ local_irq_restore(flags); ++ ++ for(vpe=0; vpe < NVPES; vpe++) { ++ len = sprintf(page, "VPE[%d].VPEschedule = 0x%08x\n", ++ vpe, vpeschedule[vpe]); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "VPE[%d].VPEschefback = 0x%08x\n", ++ vpe, vpeschefback[vpe]); ++ totalen += len; ++ page += len; ++ } ++ for(i=0; i < NTCS; i++) { ++ len = sprintf(page, "TC[%d].TCschedule = 0x%08x\n", ++ i, tcschedule[i]); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "TC[%d].TCschefback = 0x%08x\n", ++ i, tcschefback[i]); ++ totalen += len; ++ page += len; ++ } ++ return totalen; ++} ++ ++/* ++ * Write to perf counter registers based on text input ++ */ ++ ++#define TXTBUFSZ 100 ++ ++static int proc_write_mtsched(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ int len = 0; ++ char mybuf[TXTBUFSZ]; ++ /* At most, we will set up 9 TCs and 2 VPEs, 11 entries in all */ ++ char entity[1]; //, entity1[1]; ++ int number[1]; ++ unsigned long value[1]; ++ int nparsed = 0 , index = 0; ++ unsigned long flags; ++ unsigned int mtflags; ++ unsigned int haltstate; ++ unsigned int tcbindval; ++ ++ if(count >= TXTBUFSZ) len = TXTBUFSZ-1; ++ else len = count; ++ memset(mybuf,0,TXTBUFSZ); ++ if(copy_from_user(mybuf, buffer, len)) return -EFAULT; ++ ++ nparsed = sscanf(mybuf, "%c%d %lx", ++ &entity[0] ,&number[0], &value[0]); ++ ++ /* ++ * Having acquired the inputs, which might have ++ * generated exceptions and preemptions, ++ * program the registers. ++ */ ++ /* Disable interrupts and multithreaded issue */ ++ local_irq_save(flags); ++ mtflags = dvpe(); ++ ++ if(entity[index] == 't' ) { ++ /* Set TCSchedule or TCScheFBack of specified TC */ ++ if(number[index] > NTCS) goto skip; ++ /* If it's our own TC, do it direct */ ++ if(number[index] == ++ ((read_c0_tcbind() & TCBIND_CURTC) ++ >> TCBIND_CURTC_SHIFT)) { ++ if(entity[index] == 't') ++ write_c0_tcschedule(value[index]); ++ else ++ write_c0_tcschefback(value[index]); ++ } else { ++ /* Otherwise, we do it via MTTR */ ++ settc(number[index]); ++ haltstate = read_tc_c0_tchalt(); ++ write_tc_c0_tchalt(TCHALT_H); ++ mips_ihb(); ++ if(entity[index] == 't') ++ write_tc_c0_tcschedule(value[index]); ++ else ++ write_tc_c0_tcschefback(value[index]); ++ mips_ihb(); ++ if(!haltstate) write_tc_c0_tchalt(0); ++ } ++ } else if(entity[index] == 'v') { ++ /* Set VPESchedule of specified VPE */ ++ if(number[index] > NVPES) goto skip; ++ tcbindval = read_c0_tcbind(); ++ /* Are we doing this to our current VPE? */ ++ if((tcbindval & TCBIND_CURVPE) == number[index]) { ++ /* Then life is simple */ ++ write_c0_vpeschedule(value[index]); ++ } else { ++ /* ++ * Bind ourselves to the other VPE long enough ++ * to program the bind value. ++ */ ++ write_c0_tcbind((tcbindval & ~TCBIND_CURVPE) ++ | number[index]); ++ mips_ihb(); ++ write_c0_vpeschedule(value[index]); ++ mips_ihb(); ++ /* Restore previous binding */ ++ write_c0_tcbind(tcbindval); ++ mips_ihb(); ++ } ++ } ++ ++ else if(entity[index] == 'r') { ++ unsigned int vpes_checked[2], vpe ,i , mytc; ++ vpes_checked[0] = vpes_checked[1] = 0; ++ ++ /* Then go through the TCs, halt 'em, and extract the values */ ++ mytc = (read_c0_tcbind() & TCBIND_CURTC) >> TCBIND_CURTC_SHIFT; ++ ++ for(i = 0; i < NTCS; i++) { ++ if(i == mytc) { ++ /* No need to halt ourselves! */ ++ write_c0_vpeschefback(0); ++ write_c0_tcschefback(0); ++ } else { ++ settc(i); ++ haltstate = read_tc_c0_tchalt(); ++ write_tc_c0_tchalt(TCHALT_H); ++ mips_ihb(); ++ write_tc_c0_tcschefback(0); ++ /* If VPE bound to TC hasn't been checked, do it */ ++ vpe = read_tc_c0_tcbind() & TCBIND_CURVPE; ++ if(!vpes_checked[vpe]) { ++ write_vpe_c0_vpeschefback(0); ++ vpes_checked[vpe] = 1; ++ } ++ if(!haltstate) write_tc_c0_tchalt(0); ++ } ++ } ++ } ++ else { ++ printk ("\n Usage : <t/v><0/1> <Hex Value>\n Example : t0 0x01\n"); ++ } ++ ++skip: ++ /* Re-enable MT and interrupts */ ++ evpe(mtflags); ++ local_irq_restore(flags); ++ return (len); ++} ++ ++static int __init init_mtsched_proc(void) ++{ ++ extern struct proc_dir_entry *get_mips_proc_dir(void); ++ struct proc_dir_entry *mips_proc_dir; ++ ++ if (!cpu_has_mipsmt) { ++ printk("mtsched: not a MIPS MT capable processor\n"); ++ return -ENODEV; ++ } ++ ++ mips_proc_dir = get_mips_proc_dir(); ++ ++ mtsched_proc = create_proc_entry("mtsched", 0644, mips_proc_dir); ++ mtsched_proc->read_proc = proc_read_mtsched; ++ mtsched_proc->write_proc = proc_write_mtsched; ++ ++ return 0; ++} ++ ++/* Automagically create the entry */ ++module_init(init_mtsched_proc); +--- /dev/null ++++ b/arch/mips/kernel/perf_proc.c +@@ -0,0 +1,191 @@ ++/* ++ * /proc hooks for CPU performance counter support for SMTC kernel ++ * (and ultimately others) ++ * Copyright (C) 2006 Mips Technologies, Inc ++ */ ++ ++#include <linux/kernel.h> ++ ++#include <asm/cpu.h> ++#include <asm/processor.h> ++#include <asm/system.h> ++#include <asm/mipsregs.h> ++#include <asm/uaccess.h> ++#include <linux/proc_fs.h> ++ ++/* ++ * /proc diagnostic and statistics hooks ++ */ ++ ++ ++/* Internal software-extended event counters */ ++ ++static unsigned long long extencount[4] = {0,0,0,0}; ++ ++static struct proc_dir_entry *perf_proc; ++ ++static int proc_read_perf(char *page, char **start, off_t off, ++ int count, int *eof, void *data) ++{ ++ int totalen = 0; ++ int len; ++ ++ len = sprintf(page, "PerfCnt[0].Ctl : 0x%08x\n", read_c0_perfctrl0()); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[0].Cnt : %Lu\n", ++ extencount[0] + (unsigned long long)((unsigned)read_c0_perfcntr0())); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[1].Ctl : 0x%08x\n", read_c0_perfctrl1()); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[1].Cnt : %Lu\n", ++ extencount[1] + (unsigned long long)((unsigned)read_c0_perfcntr1())); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[2].Ctl : 0x%08x\n", read_c0_perfctrl2()); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[2].Cnt : %Lu\n", ++ extencount[2] + (unsigned long long)((unsigned)read_c0_perfcntr2())); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[3].Ctl : 0x%08x\n", read_c0_perfctrl3()); ++ totalen += len; ++ page += len; ++ len = sprintf(page, "PerfCnt[3].Cnt : %Lu\n", ++ extencount[3] + (unsigned long long)((unsigned)read_c0_perfcntr3())); ++ totalen += len; ++ page += len; ++ ++ return totalen; ++} ++ ++/* ++ * Write to perf counter registers based on text input ++ */ ++ ++#define TXTBUFSZ 100 ++ ++static int proc_write_perf(struct file *file, const char *buffer, ++ unsigned long count, void *data) ++{ ++ int len; ++ int nparsed; ++ int index; ++ char mybuf[TXTBUFSZ]; ++ ++ int which[4]; ++ unsigned long control[4]; ++ long long ctrdata[4]; ++ ++ if(count >= TXTBUFSZ) len = TXTBUFSZ-1; ++ else len = count; ++ memset(mybuf,0,TXTBUFSZ); ++ if(copy_from_user(mybuf, buffer, len)) return -EFAULT; ++ ++ nparsed = sscanf(mybuf, ++ "%d %lx %Ld %d %lx %Ld %d %lx %Ld %d %lx %Ld", ++ &which[0], &control[0], &ctrdata[0], ++ &which[1], &control[1], &ctrdata[1], ++ &which[2], &control[2], &ctrdata[2], ++ &which[3], &control[3], &ctrdata[3]); ++ ++ for(index = 0; nparsed >= 3; index++) { ++ switch (which[index]) { ++ case 0: ++ write_c0_perfctrl0(control[index]); ++ if(ctrdata[index] != -1) { ++ extencount[0] = (unsigned long long)ctrdata[index]; ++ write_c0_perfcntr0((unsigned long)0); ++ } ++ break; ++ case 1: ++ write_c0_perfctrl1(control[index]); ++ if(ctrdata[index] != -1) { ++ extencount[1] = (unsigned long long)ctrdata[index]; ++ write_c0_perfcntr1((unsigned long)0); ++ } ++ break; ++ case 2: ++ write_c0_perfctrl2(control[index]); ++ if(ctrdata[index] != -1) { ++ extencount[2] = (unsigned long long)ctrdata[index]; ++ write_c0_perfcntr2((unsigned long)0); ++ } ++ break; ++ case 3: ++ write_c0_perfctrl3(control[index]); ++ if(ctrdata[index] != -1) { ++ extencount[3] = (unsigned long long)ctrdata[index]; ++ write_c0_perfcntr3((unsigned long)0); ++ } ++ break; ++ } ++ nparsed -= 3; ++ } ++ return (len); ++} ++ ++extern int (*perf_irq)(void); ++ ++/* ++ * Invoked when timer interrupt vector picks up a perf counter overflow ++ */ ++ ++static int perf_proc_irq(void) ++{ ++ unsigned long snapshot; ++ ++ /* ++ * It would be nice to do this as a loop, but we don't have ++ * indirect access to CP0 registers. ++ */ ++ snapshot = read_c0_perfcntr0(); ++ if ((long)snapshot < 0) { ++ extencount[0] += ++ (unsigned long long)((unsigned)read_c0_perfcntr0()); ++ write_c0_perfcntr0(0); ++ } ++ snapshot = read_c0_perfcntr1(); ++ if ((long)snapshot < 0) { ++ extencount[1] += ++ (unsigned long long)((unsigned)read_c0_perfcntr1()); ++ write_c0_perfcntr1(0); ++ } ++ snapshot = read_c0_perfcntr2(); ++ if ((long)snapshot < 0) { ++ extencount[2] += ++ (unsigned long long)((unsigned)read_c0_perfcntr2()); ++ write_c0_perfcntr2(0); ++ } ++ snapshot = read_c0_perfcntr3(); ++ if ((long)snapshot < 0) { ++ extencount[3] += ++ (unsigned long long)((unsigned)read_c0_perfcntr3()); ++ write_c0_perfcntr3(0); ++ } ++ return 0; ++} ++ ++static int __init init_perf_proc(void) ++{ ++ extern struct proc_dir_entry *get_mips_proc_dir(void); ++ ++ struct proc_dir_entry *mips_proc_dir = get_mips_proc_dir(); ++ ++ write_c0_perfcntr0(0); ++ write_c0_perfcntr1(0); ++ write_c0_perfcntr2(0); ++ write_c0_perfcntr3(0); ++ perf_proc = create_proc_entry("perf", 0644, mips_proc_dir); ++ perf_proc->read_proc = proc_read_perf; ++ perf_proc->write_proc = proc_write_perf; ++ perf_irq = perf_proc_irq; ++ ++ return 0; ++} ++ ++/* Automagically create the entry */ ++module_init(init_perf_proc); +--- a/arch/mips/kernel/proc.c ++++ b/arch/mips/kernel/proc.c +@@ -7,6 +7,7 @@ + #include <linux/kernel.h> + #include <linux/sched.h> + #include <linux/seq_file.h> ++#include <linux/proc_fs.h> + #include <asm/bootinfo.h> + #include <asm/cpu.h> + #include <asm/cpu-features.h> +@@ -110,3 +111,19 @@ const struct seq_operations cpuinfo_op = + .stop = c_stop, + .show = show_cpuinfo, + }; ++ ++/* ++ * Support for MIPS/local /proc hooks in /proc/mips/ ++ */ ++ ++static struct proc_dir_entry *mips_proc = NULL; ++ ++struct proc_dir_entry *get_mips_proc_dir(void) ++{ ++ /* ++ * This ought not to be preemptable. ++ */ ++ if(mips_proc == NULL) ++ mips_proc = proc_mkdir("mips", NULL); ++ return(mips_proc); ++} +--- a/arch/mips/kernel/smtc.c ++++ b/arch/mips/kernel/smtc.c +@@ -1334,6 +1334,13 @@ void smtc_get_new_mmu_context(struct mm_ + asid = asid_cache(cpu); + + do { ++#ifdef CONFIG_IFX_VPE_EXT ++ /* If TLB is shared between AP and RP (AP is running SMTC), ++ leave out max ASID i.e., ASID_MASK for RP ++ */ ++ if (!nostlb && ((asid & ASID_MASK) == (ASID_MASK - 1))) ++ asid++; ++#endif + if (!((asid += ASID_INC) & ASID_MASK) ) { + if (cpu_has_vtag_icache) + flush_icache_all(); +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -76,6 +76,58 @@ static struct kspd_notifications kspd_ev + static int kspd_events_reqd; + #endif + ++#ifdef CONFIG_IFX_VPE_EXT ++static int is_sdepgm; ++extern int stlb; ++extern int vpe0_wired; ++extern int vpe1_wired; ++unsigned int vpe1_load_addr; ++ ++static int __init load_address(char *str) ++{ ++ get_option(&str, &vpe1_load_addr); ++ return 1; ++} ++__setup("vpe1_load_addr=", load_address); ++ ++#include <asm/mipsmtregs.h> ++#define write_vpe_c0_wired(val) mttc0(6, 0, val) ++ ++#ifndef COMMAND_LINE_SIZE ++# define COMMAND_LINE_SIZE 512 ++#endif ++ ++char command_line[COMMAND_LINE_SIZE * 2]; ++ ++static unsigned int vpe1_mem; ++static int __init vpe1mem(char *str) ++{ ++ vpe1_mem = memparse(str, &str); ++ return 1; ++} ++__setup("vpe1_mem=", vpe1mem); ++ ++uint32_t vpe1_wdog_ctr; ++static int __init wdog_ctr(char *str) ++{ ++ get_option(&str, &vpe1_wdog_ctr); ++ return 1; ++} ++ ++__setup("vpe1_wdog_ctr_addr=", wdog_ctr); ++EXPORT_SYMBOL(vpe1_wdog_ctr); ++ ++uint32_t vpe1_wdog_timeout; ++static int __init wdog_timeout(char *str) ++{ ++ get_option(&str, &vpe1_wdog_timeout); ++ return 1; ++} ++ ++__setup("vpe1_wdog_timeout=", wdog_timeout); ++EXPORT_SYMBOL(vpe1_wdog_timeout); ++ ++#endif + /* grab the likely amount of memory we will need. */ + #ifdef CONFIG_MIPS_VPE_LOADER_TOM + #define P_SIZE (2 * 1024 * 1024) +@@ -268,6 +320,13 @@ static void *alloc_progmem(unsigned long + void *addr; + + #ifdef CONFIG_MIPS_VPE_LOADER_TOM ++#ifdef CONFIG_IFX_VPE_EXT ++ if (vpe1_load_addr) { ++ memset((void *)vpe1_load_addr, 0, len); ++ return (void *)vpe1_load_addr; ++ } ++#endif ++ + /* + * This means you must tell Linux to use less memory than you + * physically have, for example by passing a mem= boot argument. +@@ -746,6 +805,12 @@ static int vpe_run(struct vpe * v) + } + + /* Write the address we want it to start running from in the TCPC register. */ ++#if defined(CONFIG_IFX_VPE_EXT) && 0 ++ if (stlb) ++ write_vpe_c0_wired(vpe0_wired + vpe1_wired); ++ else ++ write_vpe_c0_wired(vpe1_wired); ++#endif + write_tc_c0_tcrestart((unsigned long)v->__start); + write_tc_c0_tccontext((unsigned long)0); + +@@ -759,6 +824,20 @@ static int vpe_run(struct vpe * v) + + write_tc_c0_tchalt(read_tc_c0_tchalt() & ~TCHALT_H); + ++#if defined(CONFIG_IFX_VPE_EXT) && 0 ++ /* ++ * $a2 & $a3 are used to pass command line parameters to VPE1. $a2 ++ * points to the start of the command line string and $a3 points to ++ * the end of the string. This convention is identical to the Linux ++ * kernel boot parameter passing mechanism. Please note that $a3 is ++ * used to pass physical memory size or 0 in SDE tool kit. So, if you ++ * are passing comand line parameters through $a2 & $a3 SDE programs ++ * don't work as desired. ++ */ ++ mttgpr(6, command_line); ++ mttgpr(7, (command_line + strlen(command_line))); ++ if (is_sdepgm) ++#endif + /* + * The sde-kit passes 'memsize' to __start in $a3, so set something + * here... Or set $a3 to zero and define DFLT_STACK_SIZE and +@@ -833,6 +912,9 @@ static int find_vpe_symbols(struct vpe * + if ( (v->__start == 0) || (v->shared_ptr == NULL)) + return -1; + ++#ifdef CONFIG_IFX_VPE_EXT ++ is_sdepgm = 1; ++#endif + return 0; + } + +@@ -994,6 +1076,15 @@ static int vpe_elfload(struct vpe * v) + (unsigned long)v->load_addr + v->len); + + if ((find_vpe_symbols(v, sechdrs, symindex, strtab, &mod)) < 0) { ++#ifdef CONFIG_IFX_VPE_EXT ++ if (vpe1_load_addr) { ++ /* Conversion to KSEG1 is required ??? */ ++ v->__start = KSEG1ADDR(vpe1_load_addr); ++ is_sdepgm = 0; ++ return 0; ++ } ++#endif ++ + if (v->__start == 0) { + printk(KERN_WARNING "VPE loader: program does not contain " + "a __start symbol\n"); +@@ -1064,6 +1155,9 @@ static int vpe_open(struct inode *inode, + struct vpe_notifications *not; + struct vpe *v; + int ret; ++#ifdef CONFIG_IFX_VPE_EXT ++ int progsize; ++#endif + + if (minor != iminor(inode)) { + /* assume only 1 device at the moment. */ +@@ -1089,7 +1183,12 @@ static int vpe_open(struct inode *inode, + release_progmem(v->load_addr); + cleanup_tc(get_tc(tclimit)); + } +- ++#ifdef CONFIG_IFX_VPE_EXT ++ progsize = (vpe1_mem != 0) ? vpe1_mem : P_SIZE; ++ //printk("progsize = %x\n", progsize); ++ v->pbuffer = vmalloc(progsize); ++ v->plen = progsize; ++#else + /* this of-course trashes what was there before... */ + v->pbuffer = vmalloc(P_SIZE); + if (!v->pbuffer) { +@@ -1097,11 +1196,14 @@ static int vpe_open(struct inode *inode, + return -ENOMEM; + } + v->plen = P_SIZE; ++#endif + v->load_addr = NULL; + v->len = 0; + ++#if 0 + v->uid = filp->f_cred->fsuid; + v->gid = filp->f_cred->fsgid; ++#endif + + #ifdef CONFIG_MIPS_APSP_KSPD + /* get kspd to tell us when a syscall_exit happens */ +@@ -1349,6 +1451,133 @@ static void kspd_sp_exit( int sp_id) + cleanup_tc(get_tc(sp_id)); + } + #endif ++#ifdef CONFIG_IFX_VPE_EXT ++int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags) ++{ ++ enum vpe_state state; ++ struct vpe *v = get_vpe(tclimit); ++ struct vpe_notifications *not; ++ ++ if (tcmask || flags) { ++ printk(KERN_WARNING "Currently tcmask and flags should be 0.\ ++ other values not supported\n"); ++ return -1; ++ } ++ ++ state = xchg(&v->state, VPE_STATE_INUSE); ++ if (state != VPE_STATE_UNUSED) { ++ vpe_stop(v); ++ ++ list_for_each_entry(not, &v->notify, list) { ++ not->stop(tclimit); ++ } ++ } ++ ++ v->__start = (unsigned long)sw_start_addr; ++ is_sdepgm = 0; ++ ++ if (!vpe_run(v)) { ++ printk(KERN_DEBUG "VPE loader: VPE1 running successfully\n"); ++ return 0; ++ } ++ return -1; ++} ++ ++EXPORT_SYMBOL(vpe1_sw_start); ++ ++int32_t vpe1_sw_stop(uint32_t flags) ++{ ++ struct vpe *v = get_vpe(tclimit); ++ ++ if (!vpe_free(v)) { ++ printk(KERN_DEBUG "RP Stopped\n"); ++ return 0; ++ } ++ else ++ return -1; ++} ++ ++EXPORT_SYMBOL(vpe1_sw_stop); ++ ++uint32_t vpe1_get_load_addr (uint32_t flags) ++{ ++ return vpe1_load_addr; ++} ++ ++EXPORT_SYMBOL(vpe1_get_load_addr); ++ ++uint32_t vpe1_get_max_mem (uint32_t flags) ++{ ++ if (!vpe1_mem) ++ return P_SIZE; ++ else ++ return vpe1_mem; ++} ++ ++EXPORT_SYMBOL(vpe1_get_max_mem); ++ ++void* vpe1_get_cmdline_argument(void) ++{ ++ return saved_command_line; ++} ++ ++EXPORT_SYMBOL(vpe1_get_cmdline_argument); ++ ++int32_t vpe1_set_boot_param(char *field, char *value, char flags) ++{ ++ char *ptr, string[64]; ++ int start_off, end_off; ++ if (!field) ++ return -1; ++ strcpy(string, field); ++ if (value) { ++ strcat(string, "="); ++ strcat(string, value); ++ strcat(command_line, " "); ++ strcat(command_line, string); ++ } ++ else { ++ ptr = strstr(command_line, string); ++ if (ptr) { ++ start_off = ptr - command_line; ++ ptr += strlen(string); ++ while ((*ptr != ' ') && (*ptr != '\0')) ++ ptr++; ++ end_off = ptr - command_line; ++ command_line[start_off] = '\0'; ++ strcat (command_line, command_line+end_off); ++ } ++ } ++ return 0; ++} ++ ++EXPORT_SYMBOL(vpe1_set_boot_param); ++ ++int32_t vpe1_get_boot_param(char *field, char **value, char flags) ++{ ++ char *ptr, string[64]; ++ int i = 0; ++ if (!field) ++ return -1; ++ if ((ptr = strstr(command_line, field))) { ++ ptr += strlen(field) + 1; /* including = */ ++ while ((*ptr != ' ') && (*ptr != '\0')) ++ string[i++] = *ptr++; ++ string[i] = '\0'; ++ *value = kmalloc((strlen(string) + 1), GFP_KERNEL); ++ if (*value != NULL) ++ strcpy(*value, string); ++ } ++ else ++ *value = NULL; ++ ++ return 0; ++} ++ ++EXPORT_SYMBOL(vpe1_get_boot_param); ++ ++extern void configure_tlb(void); ++#endif + + static ssize_t store_kill(struct device *dev, struct device_attribute *attr, + const char *buf, size_t len) +@@ -1430,6 +1659,18 @@ static int __init vpe_module_init(void) + printk("VPE loader: not a MIPS MT capable processor\n"); + return -ENODEV; + } ++#ifdef CONFIG_IFX_VPE_EXT ++#ifndef CONFIG_MIPS_MT_SMTC ++ configure_tlb(); ++#endif ++#endif ++ ++#ifndef CONFIG_MIPS_MT_SMTC ++ if (!vpelimit) ++ vpelimit = 1; ++ if (!tclimit) ++ tclimit = 1; ++#endif + + if (vpelimit == 0) { + printk(KERN_WARNING "No VPEs reserved for AP/SP, not " +@@ -1474,10 +1715,12 @@ static int __init vpe_module_init(void) + mtflags = dmt(); + vpflags = dvpe(); + ++ back_to_back_c0_hazard(); ++ + /* Put MVPE's into 'configuration state' */ + set_c0_mvpcontrol(MVPCONTROL_VPC); + +- /* dump_mtregs(); */ ++ dump_mtregs(); + + val = read_c0_mvpconf0(); + hw_tcs = (val & MVPCONF0_PTC) + 1; +@@ -1489,6 +1732,7 @@ static int __init vpe_module_init(void) + * reschedule send IPIs or similar we might hang. + */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); ++ back_to_back_c0_hazard(); + evpe(vpflags); + emt(mtflags); + local_irq_restore(flags); +@@ -1514,6 +1758,7 @@ static int __init vpe_module_init(void) + } + + v->ntcs = hw_tcs - tclimit; ++ write_tc_c0_tcbind((read_tc_c0_tcbind() & ~TCBIND_CURVPE) | 1); + + /* add the tc to the list of this vpe's tc's. */ + list_add(&t->tc, &v->tc); +@@ -1582,6 +1827,7 @@ static int __init vpe_module_init(void) + out_reenable: + /* release config state */ + clear_c0_mvpcontrol(MVPCONTROL_VPC); ++ back_to_back_c0_hazard(); + + evpe(vpflags); + emt(mtflags); diff --git a/target/linux/lantiq/patches/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch b/target/linux/lantiq/patches/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch new file mode 100644 index 0000000000..9173a5de09 --- /dev/null +++ b/target/linux/lantiq/patches/0020-MIPS-lantiq-adds-falcon-VPE-softdog.patch @@ -0,0 +1,177 @@ +From e3c377986855f820513edf2924a022a39c363908 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 21:29:14 +0200 +Subject: [PATCH 20/24] MIPS: lantiq: adds falcon VPE softdog + +--- + arch/mips/include/asm/mach-lantiq/falcon/vpe.h | 44 ++++++++++ + arch/mips/lantiq/falcon/softdog_vpe.c | 109 ++++++++++++++++++++++++ + 2 files changed, 153 insertions(+), 0 deletions(-) + create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/vpe.h + create mode 100644 arch/mips/lantiq/falcon/softdog_vpe.c + +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/vpe.h +@@ -0,0 +1,44 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License as published by ++ * the Free Software Foundation; either version 2 of the License, or ++ * (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA. ++ * ++ * Copyright (C) 2005 infineon ++ * Copyright (C) 2007 John Crispin <blogic@openwrt.org> ++ * ++ */ ++#ifndef _IFXMIPS_VPE_H__ ++#define _IFXMIPS_VPE_H__ ++ ++/* For the explanation of the APIs please refer the section "MT APRP Kernel ++ * Programming" in AR9 SW Architecture Specification ++ */ ++int32_t vpe1_sw_start(void* sw_start_addr, uint32_t tcmask, uint32_t flags); ++int32_t vpe1_sw_stop(uint32_t flags); ++uint32_t vpe1_get_load_addr (uint32_t flags); ++uint32_t vpe1_get_max_mem (uint32_t flags); ++ ++int32_t vpe1_set_boot_param(char *field, char *value, char flags); ++int32_t vpe1_get_boot_param(char *field, char **value, char flags); ++ ++/* Watchdog APIs */ ++extern unsigned long vpe1_wdog_ctr; ++extern unsigned long vpe1_wdog_timeout; ++ ++unsigned long vpe1_sw_wdog_start(unsigned long); ++unsigned long vpe1_sw_wdog_stop(unsigned long); ++ ++typedef int (*VPE_SW_WDOG_RESET)(unsigned long wdog_cleared_ok_count); ++int32_t vpe1_sw_wdog_register_reset_handler(VPE_SW_WDOG_RESET reset_fn); ++ ++#endif +--- /dev/null ++++ b/arch/mips/lantiq/falcon/softdog_vpe.c +@@ -0,0 +1,109 @@ ++/* ++** ============================================================================= ++** FILE NAME : softdog_vpe.c ++** MODULES : LXDB ++** DATE : 24-03-2008 ++** AUTHOR : LXDB Team ++** DESCRIPTION : This header file contains the code for the watchdog ++** implentation on vpe1 side. ++** REFERENCES : ++** COPYRIGHT : Copyright (c) 2008 ++** Am Campeon 1-12, 85579 Neubiberg, Germany ++** Any use of this software is subject to the conclusion of a respective ++** License agreement. Without such a License agreement no rights to the ++** software are granted ++** ++** HISTORY : ++** $Date $Author $Comment ++** 24-03-2008 LXDB Initial version ++** ============================================================================ ++*/ ++ ++#include <linux/module.h> ++#include <linux/moduleparam.h> ++#include <linux/types.h> ++#include <linux/timer.h> ++#include <linux/reboot.h> ++#include <linux/init.h> ++#include <linux/jiffies.h> ++ ++#include <falcon/vpe.h> ++ ++static unsigned long last_wdog_value; ++static unsigned long vpe1_wdog_cleared; ++ ++static unsigned long vpe1_wdog_dead; ++static void watchdog_vpe0_fire(unsigned long); /* Called when vpe0 timer expires */ ++static void keep_alive_vpe0(unsigned long); ++VPE_SW_WDOG_RESET reset_local_fn; ++ ++ ++static struct timer_list watchdog_vpe0_ticktock = ++ TIMER_INITIALIZER(watchdog_vpe0_fire, 0, 0); ++ ++static void watchdog_vpe0_fire (unsigned long flags) ++{ ++ volatile unsigned long *wdog_ctr_value; ++ wdog_ctr_value = (void*)vpe1_wdog_ctr; ++ if (*wdog_ctr_value == last_wdog_value) { /* VPE1 watchdog expiry handling */ ++ vpe1_sw_wdog_stop(flags); ++ vpe1_wdog_dead++; ++ printk(KERN_DEBUG "VPE1 watchdog reset handler called\n"); ++ /* Call the reset handler function */ ++ reset_local_fn(flags); ++ } else { /* Everything is OK on vpe1 side. Continue. */ ++ last_wdog_value = *wdog_ctr_value; ++ vpe1_wdog_cleared++; ++ keep_alive_vpe0(flags); ++ } ++} ++ ++int32_t vpe1_sw_wdog_register_reset_handler (VPE_SW_WDOG_RESET reset_fn) ++{ ++ reset_local_fn = (VPE_SW_WDOG_RESET)reset_fn; ++ return 0; ++} ++ ++static void keep_alive_vpe0(unsigned long flags) ++{ ++ mod_timer(&watchdog_vpe0_ticktock, jiffies+ vpe1_wdog_timeout ); ++} ++ ++unsigned long vpe1_sw_wdog_start(unsigned long flags) ++{ ++ volatile unsigned long *wdog_ctr_value; ++ wdog_ctr_value = (void*)vpe1_wdog_ctr; ++ *wdog_ctr_value = 0; ++ last_wdog_value = 0; ++ keep_alive_vpe0(flags); ++ return 0; ++} ++ ++unsigned long vpe1_sw_wdog_stop(unsigned long flags) ++{ ++ del_timer(&watchdog_vpe0_ticktock); ++ return 0; ++} ++ ++static int __init watchdog_vpe1_init(void) ++{ ++ /* Nothing to be done here */ ++ return 0; ++} ++ ++static void __exit watchdog_vpe1_exit(void) ++{ ++ unsigned long flags=0; ++ vpe1_sw_wdog_stop(flags); ++} ++ ++module_init(watchdog_vpe1_init); ++module_exit(watchdog_vpe1_exit); ++ ++EXPORT_SYMBOL(vpe1_sw_wdog_register_reset_handler); ++EXPORT_SYMBOL(vpe1_sw_wdog_start); ++EXPORT_SYMBOL(vpe1_sw_wdog_stop); ++ ++MODULE_AUTHOR("LXDB"); ++MODULE_DESCRIPTION("Software Watchdog For VPE1"); ++MODULE_LICENSE("GPL"); +--- a/arch/mips/lantiq/falcon/Makefile ++++ b/arch/mips/lantiq/falcon/Makefile +@@ -1,2 +1,2 @@ +-obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o ++obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o softdog_vpe.o + obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o diff --git a/target/linux/lantiq/patches/0021-MIPS-lantiq-adds-cache-split.patch b/target/linux/lantiq/patches/0021-MIPS-lantiq-adds-cache-split.patch new file mode 100644 index 0000000000..640d1e2acf --- /dev/null +++ b/target/linux/lantiq/patches/0021-MIPS-lantiq-adds-cache-split.patch @@ -0,0 +1,345 @@ +From 0f85e79f6f01f50cb703866a555085a9c65bad2f Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 20:31:54 +0200 +Subject: [PATCH 21/24] MIPS: lantiq: adds cache split + +--- + arch/mips/Kconfig | 22 ++++++ + arch/mips/kernel/vpe.c | 66 ++++++++++++++++++ + arch/mips/mm/c-r4k.c | 172 ++++++++++++++++++++++++++++++++++++++++++++++++ + 3 files changed, 260 insertions(+), 0 deletions(-) + +--- a/arch/mips/Kconfig ++++ b/arch/mips/Kconfig +@@ -1922,6 +1922,28 @@ config IFX_VPE_EXT + help + IFX included extensions in APRP + ++config IFX_VPE_CACHE_SPLIT ++ bool "IFX Cache Split Ways" ++ depends on IFX_VPE_EXT ++ help ++ IFX extension for reserving (splitting) cache ways among VPEs. You must ++ give kernel command line arguments vpe_icache_shared=0 or ++ vpe_dcache_shared=0 to enable splitting of icache or dcache ++ respectively. Then you can specify which cache ways should be ++ assigned to which VPE. There are total 8 cache ways, 4 each ++ for dcache and icache: dcache_way0, dcache_way1,dcache_way2, ++ dcache_way3 and icache_way0,icache_way1, icache_way2,icache_way3. ++ ++ For example, if you specify vpe_icache_shared=0 and icache_way2=1, ++ then the 3rd icache way will be assigned to VPE0 and denied in VPE1. ++ ++ For icache, software is required to make at least one cache way available ++ for a VPE at all times i.e., one can't assign all the icache ways to one ++ VPE. ++ ++ By default, vpe_dcache_shared and vpe_icache_shared are set to 1 ++ (i.e., both icache and dcache are shared among VPEs) ++ + config PERFCTRS + bool "34K Performance counters" + depends on MIPS_MT && PROC_FS +--- a/arch/mips/kernel/vpe.c ++++ b/arch/mips/kernel/vpe.c +@@ -128,6 +128,13 @@ __setup("vpe1_wdog_timeout=", wdog_timeo + EXPORT_SYMBOL(vpe1_wdog_timeout); + + #endif ++ ++#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */ ++extern int vpe_icache_shared,vpe_dcache_shared; ++extern int icache_way0,icache_way1,icache_way2,icache_way3; ++extern int dcache_way0,dcache_way1,dcache_way2,dcache_way3; ++#endif ++ + /* grab the likely amount of memory we will need. */ + #ifdef CONFIG_MIPS_VPE_LOADER_TOM + #define P_SIZE (2 * 1024 * 1024) +@@ -866,6 +873,65 @@ static int vpe_run(struct vpe * v) + /* enable this VPE */ + write_vpe_c0_vpeconf0(read_vpe_c0_vpeconf0() | VPECONF0_VPA); + ++#ifdef CONFIG_IFX_VPE_CACHE_SPLIT ++ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ) { ++ ++ /* PCP bit must be 1 to split the cache */ ++ if(read_c0_mvpconf0() & MVPCONF0_PCP) { ++ ++ if ( !vpe_icache_shared ){ ++ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_ICS); ++ ++ /* ++ * If any cache way is 1, then that way is denied ++ * in VPE1. Otherwise assign that way to VPE1. ++ */ ++ if (!icache_way0) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX0 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX0 ); ++ if (!icache_way1) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX1 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX1 ); ++ if (!icache_way2) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX2 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX2 ); ++ if (!icache_way3) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_IWX3 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_IWX3 ); ++ } ++ ++ if ( !vpe_dcache_shared ) { ++ write_vpe_c0_vpeconf0((read_vpe_c0_vpeconf0()) & ~VPECONF0_DCS); ++ ++ /* ++ * If any cache way is 1, then that way is denied ++ * in VPE1. Otherwise assign that way to VPE1. ++ */ ++ if (!dcache_way0) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX0 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX0 ); ++ if (!dcache_way1) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX1 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX1 ); ++ if (!dcache_way2) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX2 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX2 ); ++ if (!dcache_way3) ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() | VPEOPT_DWX3 ); ++ else ++ write_vpe_c0_vpeopt(read_vpe_c0_vpeopt() & ~VPEOPT_DWX3 ); ++ } ++ } ++ } ++#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */ ++ + /* clear out any left overs from a previous program */ + write_vpe_c0_status(0); + write_vpe_c0_cause(0); +--- a/arch/mips/mm/c-r4k.c ++++ b/arch/mips/mm/c-r4k.c +@@ -1350,6 +1350,106 @@ static int __init setcoherentio(char *st + __setup("coherentio", setcoherentio); + #endif + ++#ifdef CONFIG_IFX_VPE_CACHE_SPLIT /* Code for splitting the cache ways among VPEs. */ ++ ++#include <asm/mipsmtregs.h> ++ ++/* ++ * By default, vpe_icache_shared and vpe_dcache_shared ++ * values are 1 i.e., both icache and dcache are shared ++ * among the VPEs. ++ */ ++ ++int vpe_icache_shared = 1; ++static int __init vpe_icache_shared_val(char *str) ++{ ++ get_option(&str, &vpe_icache_shared); ++ return 1; ++} ++__setup("vpe_icache_shared=", vpe_icache_shared_val); ++EXPORT_SYMBOL(vpe_icache_shared); ++ ++int vpe_dcache_shared = 1; ++static int __init vpe_dcache_shared_val(char *str) ++{ ++ get_option(&str, &vpe_dcache_shared); ++ return 1; ++} ++__setup("vpe_dcache_shared=", vpe_dcache_shared_val); ++EXPORT_SYMBOL(vpe_dcache_shared); ++ ++/* ++ * Software is required to make atleast one icache ++ * way available for a VPE at all times i.e., one ++ * can't assign all the icache ways to one VPE. ++ */ ++ ++int icache_way0 = 0; ++static int __init icache_way0_val(char *str) ++{ ++ get_option(&str, &icache_way0); ++ return 1; ++} ++__setup("icache_way0=", icache_way0_val); ++ ++int icache_way1 = 0; ++static int __init icache_way1_val(char *str) ++{ ++ get_option(&str, &icache_way1); ++ return 1; ++} ++__setup("icache_way1=", icache_way1_val); ++ ++int icache_way2 = 0; ++static int __init icache_way2_val(char *str) ++{ ++ get_option(&str, &icache_way2); ++ return 1; ++} ++__setup("icache_way2=", icache_way2_val); ++ ++int icache_way3 = 0; ++static int __init icache_way3_val(char *str) ++{ ++ get_option(&str, &icache_way3); ++ return 1; ++} ++__setup("icache_way3=", icache_way3_val); ++ ++int dcache_way0 = 0; ++static int __init dcache_way0_val(char *str) ++{ ++ get_option(&str, &dcache_way0); ++ return 1; ++} ++__setup("dcache_way0=", dcache_way0_val); ++ ++int dcache_way1 = 0; ++static int __init dcache_way1_val(char *str) ++{ ++ get_option(&str, &dcache_way1); ++ return 1; ++} ++__setup("dcache_way1=", dcache_way1_val); ++ ++int dcache_way2 = 0; ++static int __init dcache_way2_val(char *str) ++{ ++ get_option(&str, &dcache_way2); ++ return 1; ++} ++__setup("dcache_way2=", dcache_way2_val); ++ ++int dcache_way3 = 0; ++static int __init dcache_way3_val(char *str) ++{ ++ get_option(&str, &dcache_way3); ++ return 1; ++} ++__setup("dcache_way3=", dcache_way3_val); ++ ++#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */ ++ + void __cpuinit r4k_cache_init(void) + { + extern void build_clear_page(void); +@@ -1369,6 +1469,78 @@ void __cpuinit r4k_cache_init(void) + break; + } + ++#ifdef CONFIG_IFX_VPE_CACHE_SPLIT ++ /* ++ * We split the cache ways appropriately among the VPEs ++ * based on cache ways values we received as command line ++ * arguments ++ */ ++ if ( (!vpe_icache_shared) || (!vpe_dcache_shared) ){ ++ ++ /* PCP bit must be 1 to split the cache */ ++ if(read_c0_mvpconf0() & MVPCONF0_PCP) { ++ ++ /* Set CPA bit which enables us to modify VPEOpt register */ ++ write_c0_mvpcontrol((read_c0_mvpcontrol()) | MVPCONTROL_CPA); ++ ++ if ( !vpe_icache_shared ){ ++ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_ICS); ++ /* ++ * If any cache way is 1, then that way is denied ++ * in VPE0. Otherwise assign that way to VPE0. ++ */ ++ printk(KERN_DEBUG "icache is split\n"); ++ printk(KERN_DEBUG "icache_way0=%d icache_way1=%d icache_way2=%d icache_way3=%d\n", ++ icache_way0, icache_way1,icache_way2, icache_way3); ++ if (icache_way0) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX0 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX0 ); ++ if (icache_way1) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX1 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX1 ); ++ if (icache_way2) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX2 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX2 ); ++ if (icache_way3) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_IWX3 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_IWX3 ); ++ } ++ ++ if ( !vpe_dcache_shared ) { ++ /* ++ * If any cache way is 1, then that way is denied ++ * in VPE0. Otherwise assign that way to VPE0. ++ */ ++ printk(KERN_DEBUG "dcache is split\n"); ++ printk(KERN_DEBUG "dcache_way0=%d dcache_way1=%d dcache_way2=%d dcache_way3=%d\n", ++ dcache_way0, dcache_way1, dcache_way2, dcache_way3); ++ write_c0_vpeconf0((read_c0_vpeconf0()) & ~VPECONF0_DCS); ++ if (dcache_way0) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX0 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX0 ); ++ if (dcache_way1) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX1 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX1 ); ++ if (dcache_way2) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX2 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX2 ); ++ if (dcache_way3) ++ write_c0_vpeopt(read_c0_vpeopt() | VPEOPT_DWX3 ); ++ else ++ write_c0_vpeopt(read_c0_vpeopt() & ~VPEOPT_DWX3 ); ++ } ++ } ++ } ++ ++#endif /* endif CONFIG_IFX_VPE_CACHE_SPLIT */ ++ + probe_pcache(); + setup_scache(); + +--- a/arch/mips/lantiq/setup.c ++++ b/arch/mips/lantiq/setup.c +@@ -18,10 +18,11 @@ + #include "devices.h" + #include "prom.h" + ++/* assume 16M as default incase uboot fails to pass proper ramsize */ ++unsigned long physical_memsize = 16L; ++ + void __init plat_mem_setup(void) + { +- /* assume 16M as default incase uboot fails to pass proper ramsize */ +- unsigned long memsize = 16; + char **envp = (char **) KSEG1ADDR(fw_arg2); + + ioport_resource.start = IOPORT_RESOURCE_START; +@@ -35,13 +36,13 @@ void __init plat_mem_setup(void) + char *e = (char *)KSEG1ADDR(*envp); + if (!strncmp(e, "memsize=", 8)) { + e += 8; +- if (strict_strtoul(e, 0, &memsize)) ++ if (strict_strtoul(e, 0, &physical_memsize)) + pr_warn("bad memsize specified\n"); + } + envp++; + } +- memsize *= 1024 * 1024; +- add_memory_region(0x00000000, memsize, BOOT_MEM_RAM); ++ physical_memsize *= 1024 * 1024; ++ add_memory_region(0x00000000, physical_memsize, BOOT_MEM_RAM); + } + + static int __init diff --git a/target/linux/lantiq/patches/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch b/target/linux/lantiq/patches/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch new file mode 100644 index 0000000000..c80731e83b --- /dev/null +++ b/target/linux/lantiq/patches/0022-MIPS-lantiq-adds-udp-in-kernel-redirect.patch @@ -0,0 +1,363 @@ +From 14ff975c660696fa636e8d6b58d0abed0ddc72ce Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 29 Sep 2011 20:29:54 +0200 +Subject: [PATCH 22/24] MIPS: lantiq: adds udp in-kernel redirect + +--- + include/linux/udp_redirect.h | 57 +++++++++++++ + net/Kconfig | 6 ++ + net/ipv4/Makefile | 3 + + net/ipv4/udp.c | 28 ++++++- + net/ipv4/udp_redirect_symb.c | 186 ++++++++++++++++++++++++++++++++++++++++++ + 5 files changed, 276 insertions(+), 4 deletions(-) + create mode 100644 include/linux/udp_redirect.h + create mode 100644 net/ipv4/udp_redirect_symb.c + +--- /dev/null ++++ b/include/linux/udp_redirect.h +@@ -0,0 +1,57 @@ ++#ifndef _UDP_REDIRECT_H ++#define _UDP_REDIRECT_H ++ ++/****************************************************************************** ++ ++ Copyright (c) 2006 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ ++******************************************************************************/ ++ ++/* ============================= */ ++/* Includes */ ++/* ============================= */ ++#ifndef _LINUX_TYPES_H ++#include <linux/types.h> ++#endif ++ ++ ++/* ============================= */ ++/* Definitions */ ++/* ============================= */ ++#define UDP_REDIRECT_MAGIC (void*)0x55445052L ++ ++ ++/* ============================= */ ++/* Global variable declaration */ ++/* ============================= */ ++extern int (*udp_do_redirect_fn)(struct sock *sk, struct sk_buff *skb); ++extern int (*udpredirect_getfrag_fn)(void *p, char * to, ++ int offset, int fraglen, int odd, ++ struct sk_buff *skb); ++/* ============================= */ ++/* Global function declaration */ ++/* ============================= */ ++ ++extern int udpredirect_getfrag(void *p, char * to, int offset, ++ int fraglen, int odd, struct sk_buff *skb); ++#endif +--- a/net/Kconfig ++++ b/net/Kconfig +@@ -72,6 +72,12 @@ config INET + + Short answer: say Y. + ++config IFX_UDP_REDIRECT ++ bool "IFX Kernel Packet Interface for UDP redirection" ++ help ++ You can say Y here if you want to use hooks from kernel for ++ UDP redirection. ++ + if INET + source "net/ipv4/Kconfig" + source "net/ipv6/Kconfig" +--- a/net/ipv4/Makefile ++++ b/net/ipv4/Makefile +@@ -14,6 +14,9 @@ obj-y := route.o inetpeer.o protocol + inet_fragment.o ping.o + + obj-$(CONFIG_SYSCTL) += sysctl_net_ipv4.o ++ifneq ($(CONFIG_IFX_UDP_REDIRECT),) ++obj-$(CONFIG_IFX_UDP_REDIRECT) += udp_redirect_symb.o ++endif + obj-$(CONFIG_PROC_FS) += proc.o + obj-$(CONFIG_IP_MULTIPLE_TABLES) += fib_rules.o + obj-$(CONFIG_IP_MROUTE) += ipmr.o +--- a/net/ipv4/udp.c ++++ b/net/ipv4/udp.c +@@ -108,6 +108,10 @@ + #include <trace/events/udp.h> + #include "udp_impl.h" + ++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE) ++#include <linux/udp_redirect.h> ++#endif ++ + struct udp_table udp_table __read_mostly; + EXPORT_SYMBOL(udp_table); + +@@ -803,7 +807,7 @@ int udp_sendmsg(struct kiocb *iocb, stru + u8 tos; + int err, is_udplite = IS_UDPLITE(sk); + int corkreq = up->corkflag || msg->msg_flags&MSG_MORE; +- int (*getfrag)(void *, char *, int, int, int, struct sk_buff *); ++ int (*getfrag)(void *, char *, int, int, int, struct sk_buff *) = NULL; + struct sk_buff *skb; + struct ip_options_data opt_copy; + +@@ -820,7 +824,13 @@ int udp_sendmsg(struct kiocb *iocb, stru + ipc.opt = NULL; + ipc.tx_flags = 0; + +- getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag; ++/* UDPREDIRECT */ ++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE) ++ if(udpredirect_getfrag_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC) ++ getfrag = udpredirect_getfrag_fn; ++ else ++#endif /* IFX_UDP_REDIRECT */ ++ getfrag = is_udplite ? udplite_getfrag : ip_generic_getfrag; + + fl4 = &inet->cork.fl.u.ip4; + if (up->pending) { +@@ -1621,6 +1631,7 @@ int __udp4_lib_rcv(struct sk_buff *skb, + struct rtable *rt = skb_rtable(skb); + __be32 saddr, daddr; + struct net *net = dev_net(skb->dev); ++ int ret = 0; + + /* + * Validate the packet. +@@ -1653,7 +1664,16 @@ int __udp4_lib_rcv(struct sk_buff *skb, + sk = __udp4_lib_lookup_skb(skb, uh->source, uh->dest, udptable); + + if (sk != NULL) { +- int ret = udp_queue_rcv_skb(sk, skb); ++ /* UDPREDIRECT */ ++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE) ++ if(udp_do_redirect_fn && sk->sk_user_data == UDP_REDIRECT_MAGIC) ++ { ++ udp_do_redirect_fn(sk,skb); ++ kfree_skb(skb); ++ return(0); ++ } ++#endif ++ ret = udp_queue_rcv_skb(sk, skb); + sock_put(sk); + + /* a return value > 0 means to resubmit the input, but +@@ -1950,7 +1970,7 @@ struct proto udp_prot = { + .clear_sk = sk_prot_clear_portaddr_nulls, + }; + EXPORT_SYMBOL(udp_prot); +- ++EXPORT_SYMBOL(udp_rcv); + /* ------------------------------------------------------------------------ */ + #ifdef CONFIG_PROC_FS + +--- /dev/null ++++ b/net/ipv4/udp_redirect_symb.c +@@ -0,0 +1,186 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2006 ++ Infineon Technologies AG ++ Am Campeon 1-12; 81726 Munich, Germany ++ ++ THE DELIVERY OF THIS SOFTWARE AS WELL AS THE HEREBY GRANTED NON-EXCLUSIVE, ++ WORLDWIDE LICENSE TO USE, COPY, MODIFY, DISTRIBUTE AND SUBLICENSE THIS ++ SOFTWARE IS FREE OF CHARGE. ++ ++ THE LICENSED SOFTWARE IS PROVIDED "AS IS" AND INFINEON EXPRESSLY DISCLAIMS ++ ALL REPRESENTATIONS AND WARRANTIES, WHETHER EXPRESS OR IMPLIED, INCLUDING ++ WITHOUT LIMITATION, WARRANTIES OR REPRESENTATIONS OF WORKMANSHIP, ++ MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, DURABILITY, THAT THE ++ OPERATING OF THE LICENSED SOFTWARE WILL BE ERROR FREE OR FREE OF ANY THIRD ++ PARTY CLAIMS, INCLUDING WITHOUT LIMITATION CLAIMS OF THIRD PARTY INTELLECTUAL ++ PROPERTY INFRINGEMENT. ++ ++ EXCEPT FOR ANY LIABILITY DUE TO WILFUL ACTS OR GROSS NEGLIGENCE AND EXCEPT ++ FOR ANY PERSONAL INJURY INFINEON SHALL IN NO EVENT BE LIABLE FOR ANY CLAIM ++ OR DAMAGES OF ANY KIND, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ++ ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER ++ DEALINGS IN THE SOFTWARE. ++ ++******************************************************************************/ ++#if defined(CONFIG_IFX_UDP_REDIRECT) || defined(CONFIG_IFX_UDP_REDIRECT_MODULE) ++/* ============================= */ ++/* Includes */ ++/* ============================= */ ++#include <net/checksum.h> ++#include <net/udp.h> ++#include <linux/module.h> ++#include <linux/skbuff.h> ++#include <linux/udp_redirect.h> ++ ++/* ============================= */ ++/* Global variable definition */ ++/* ============================= */ ++int (*udpredirect_getfrag_fn) (void *p, char * to, int offset, ++ int fraglen, int odd, struct sk_buff *skb) = NULL; ++int (*udp_do_redirect_fn)(struct sock *sk, struct sk_buff *skb) = NULL; ++ ++/* ============================= */ ++/* Local type definitions */ ++/* ============================= */ ++struct udpfakehdr ++{ ++ struct udphdr uh; ++ u32 saddr; ++ u32 daddr; ++ struct iovec *iov; ++ u32 wcheck; ++}; ++ ++/* ============================= */ ++/* Local function declaration */ ++/* ============================= */ ++static int udpredirect_csum_partial_copy_fromiovecend(unsigned char *kdata, ++ struct iovec *iov, int offset, unsigned int len, __wsum *csump); ++ ++static int udpredirect_memcpy_fromiovecend(unsigned char *kdata, struct iovec *iov, int offset, ++ int len); ++ ++/* ============================= */ ++/* Global function definition */ ++/* ============================= */ ++ ++/* ++ Copy of udp_getfrag() from udp.c ++ This function exists because no copy_from_user() is needed for udpredirect. ++*/ ++ ++int ++udpredirect_getfrag(void *from, char *to, int offset, int len, int odd, struct sk_buff *skb) ++{ ++ struct iovec *iov = from; ++ ++ if (skb->ip_summed == CHECKSUM_PARTIAL) { ++ if (udpredirect_memcpy_fromiovecend(to, iov, offset, len) < 0) ++ return -EFAULT; ++ } else { ++ __wsum csum = 0; ++ if (udpredirect_csum_partial_copy_fromiovecend(to, iov, offset, len, &csum) < 0) ++ return -EFAULT; ++ skb->csum = csum_block_add(skb->csum, csum, odd); ++ } ++ return 0; ++} ++ ++static int udpredirect_memcpy_fromiovecend(unsigned char *kdata, struct iovec *iov, int offset, ++ int len) ++{ ++ /* Skip over the finished iovecs */ ++ while (offset >= iov->iov_len) { ++ offset -= iov->iov_len; ++ iov++; ++ } ++ ++ while (len > 0) { ++ u8 __user *base = iov->iov_base + offset; ++ int copy = min_t(unsigned int, len, iov->iov_len - offset); ++ ++ offset = 0; ++ memcpy(kdata, base, copy); ++ len -= copy; ++ kdata += copy; ++ iov++; ++ } ++ ++ return 0; ++} ++ ++/* ++ Copy of csum_partial_copy_fromiovecend() from iovec.c ++ This function exists because no copy_from_user() is needed for udpredirect. ++*/ ++ ++int udpredirect_csum_partial_copy_fromiovecend(unsigned char *kdata, struct iovec *iov, ++ int offset, unsigned int len, __wsum *csump) ++{ ++ __wsum csum = *csump; ++ int partial_cnt = 0, err = 0; ++ ++ /* Skip over the finished iovecs */ ++ while (offset >= iov->iov_len) { ++ offset -= iov->iov_len; ++ iov++; ++ } ++ ++ while (len > 0) { ++ u8 __user *base = iov->iov_base + offset; ++ int copy = min_t(unsigned int, len, iov->iov_len - offset); ++ ++ offset = 0; ++ ++ /* There is a remnant from previous iov. */ ++ if (partial_cnt) { ++ int par_len = 4 - partial_cnt; ++ ++ /* iov component is too short ... */ ++ if (par_len > copy) { ++ memcpy(kdata, base, copy); ++ kdata += copy; ++ base += copy; ++ partial_cnt += copy; ++ len -= copy; ++ iov++; ++ if (len) ++ continue; ++ *csump = csum_partial(kdata - partial_cnt, ++ partial_cnt, csum); ++ goto out; ++ } ++ memcpy(kdata, base, par_len); ++ csum = csum_partial(kdata - partial_cnt, 4, csum); ++ kdata += par_len; ++ base += par_len; ++ copy -= par_len; ++ len -= par_len; ++ partial_cnt = 0; ++ } ++ ++ if (len > copy) { ++ partial_cnt = copy % 4; ++ if (partial_cnt) { ++ copy -= partial_cnt; ++ memcpy(kdata + copy, base + copy, partial_cnt); ++ } ++ } ++ ++ if (copy) { ++ csum = csum_partial_copy_nocheck(base, kdata, copy, csum); ++ } ++ len -= copy + partial_cnt; ++ kdata += copy + partial_cnt; ++ iov++; ++ } ++ *csump = csum; ++out: ++ return err; ++} ++ ++EXPORT_SYMBOL(udpredirect_getfrag); ++EXPORT_SYMBOL(udp_do_redirect_fn); ++EXPORT_SYMBOL(udpredirect_getfrag_fn); ++#endif /* CONFIG_IFX_UDP_REDIRECT* */ diff --git a/target/linux/lantiq/patches/0023-MIPS-lantiq-adds-basic-vr9-support.patch b/target/linux/lantiq/patches/0023-MIPS-lantiq-adds-basic-vr9-support.patch new file mode 100644 index 0000000000..bb7422cf90 --- /dev/null +++ b/target/linux/lantiq/patches/0023-MIPS-lantiq-adds-basic-vr9-support.patch @@ -0,0 +1,262 @@ +From 780a64cd52209fad15c7133f950b2b2d6b9b59e2 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 27 Aug 2011 21:44:32 +0200 +Subject: [PATCH 23/24] MIPS: lantiq: adds basic vr9 support + +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + + arch/mips/lantiq/Kconfig | 9 ++ + arch/mips/lantiq/Platform | 1 + + arch/mips/lantiq/machtypes.h | 3 + + arch/mips/lantiq/xway/Kconfig | 12 +++ + arch/mips/lantiq/xway/Makefile | 2 + + arch/mips/lantiq/xway/clk-vr9.c | 78 ++++++++++++++++++++ + arch/mips/lantiq/xway/mach-fritz.c | 74 +++++++++++++++++++ + arch/mips/lantiq/xway/prom-vr9.c | 55 ++++++++++++++ + arch/mips/pci/Makefile | 2 +- + 10 files changed, 237 insertions(+), 1 deletions(-) + create mode 100644 arch/mips/lantiq/xway/clk-vr9.c + create mode 100644 arch/mips/lantiq/xway/mach-fritz.c + create mode 100644 arch/mips/lantiq/xway/prom-vr9.c + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -21,6 +21,7 @@ + #define SOC_ID_ARX188 0x16C + #define SOC_ID_ARX168 0x16D + #define SOC_ID_ARX182 0x16F ++#define SOC_ID_VRX288 0x1C0 + + /* SoC Types */ + #define SOC_TYPE_DANUBE 0x01 +@@ -91,6 +92,7 @@ + + /* ETOP - ethernet */ + #define LTQ_ETOP_BASE_ADDR 0x1E180000 ++#define LTQ_ETOP_BASE_ADDR_VR9 0x1E200000 + #define LTQ_ETOP_SIZE 0x40000 + + /* GBIT - gigabit switch */ +--- a/arch/mips/lantiq/Kconfig ++++ b/arch/mips/lantiq/Kconfig +@@ -1,5 +1,8 @@ + if LANTIQ + ++config LANTIQ_PCIE ++ bool ++ + config SOC_TYPE_XWAY + bool + default n +@@ -17,6 +20,12 @@ config SOC_XWAY + select SOC_TYPE_XWAY + select HW_HAS_PCI + ++config SOC_VR9 ++ bool "VR9" ++ select SOC_TYPE_XWAY ++ select HW_HAS_PCI ++ select LANTIQ_PCIE ++ + config SOC_FALCON + bool "FALCON" + endchoice +--- a/arch/mips/lantiq/Platform ++++ b/arch/mips/lantiq/Platform +@@ -6,4 +6,5 @@ platform-$(CONFIG_LANTIQ) += lantiq/ + cflags-$(CONFIG_LANTIQ) += -I$(srctree)/arch/mips/include/asm/mach-lantiq + load-$(CONFIG_LANTIQ) = 0xffffffff80002000 + cflags-$(CONFIG_SOC_TYPE_XWAY) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway ++cflags-$(CONFIG_SOC_TYPE_VR9) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/xway + cflags-$(CONFIG_SOC_FALCON) += -I$(srctree)/arch/mips/include/asm/mach-lantiq/falcon +--- a/arch/mips/lantiq/machtypes.h ++++ b/arch/mips/lantiq/machtypes.h +@@ -20,6 +20,9 @@ enum lantiq_mach_type { + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ + LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ ++ ++ /* FRITZ!BOX */ ++ LANTIQ_MACH_FRITZ3370, /* FRITZ!BOX 3370 vdsl cpe */ + }; + + #endif +--- a/arch/mips/lantiq/xway/Kconfig ++++ b/arch/mips/lantiq/xway/Kconfig +@@ -21,3 +21,15 @@ config LANTIQ_MACH_EASY50601 + endmenu + + endif ++ ++if SOC_VR9 ++ ++menu "MIPS Machine" ++ ++config LANTIQ_MACH_FRITZ3370 ++ bool "Fritz!Box 3370" ++ default y ++ ++endmenu ++ ++endif +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -2,6 +2,8 @@ obj-y := sysctrl.o reset.o gpio.o gpio_s + + obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o + obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o ++obj-$(CONFIG_SOC_VR9) += clk-vr9.o prom-vr9.o + + obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o + obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o ++obj-$(CONFIG_LANTIQ_MACH_FRITZ3370) += mach-fritz.o +--- /dev/null ++++ b/arch/mips/lantiq/xway/clk-vr9.c +@@ -0,0 +1,78 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/io.h> ++#include <linux/module.h> ++#include <linux/init.h> ++#include <linux/clk.h> ++ ++#include <asm/time.h> ++#include <asm/irq.h> ++#include <asm/div64.h> ++ ++#include <lantiq_soc.h> ++ ++#define CLOCK_62_5M 62500000 ++#define CLOCK_83_5M 83500000 ++#define CLOCK_125M 125000000 ++#define CLOCK_200M 200000000 ++#define CLOCK_250M 250000000 ++#define CLOCK_300M 300000000 ++#define CLOCK_98_304M 98304000 ++#define CLOCK_150M 150000000 ++#define CLOCK_196_608M 196608000 ++#define CLOCK_600M 600000000 ++#define CLOCK_500M 500000000 ++#define CLOCK_393M 393215332 ++#define CLOCK_166M 166666666 ++ ++#define LTQ_CGU_SYS 0x0c ++#define LTQ_CGU_IF_CLK 0x24 ++ ++unsigned int ltq_get_cpu_hz(void) ++{ ++ int clks[] = { ++ CLOCK_600M, CLOCK_500M, CLOCK_393M, CLOCK_333M, CLOCK_125M, ++ CLOCK_125M, CLOCK_196_608M, CLOCK_166M, CLOCK_125M, CLOCK_125M }; ++ int val = (ltq_cgu_r32(LTQ_CGU_SYS) >> 4) & 0xf; ++ ++ if (val > 9) ++ panic("bad cpu speed\n"); ++ if (val == 2) ++ panic("missing workaround\n"); ++ //cgu_get_pll1_fosc(); //CLOCK_393M; ++ return clks[val]; ++} ++EXPORT_SYMBOL(ltq_get_cpu_hz); ++ ++unsigned int ltq_get_fpi_hz(void) ++{ ++ int clks[] = { ++ CLOCK_62_5M, CLOCK_62_5M, CLOCK_83_5M, CLOCK_125M, CLOCK_125M, ++ CLOCK_125M, CLOCK_167M, CLOCK_200M, CLOCK_250M, CLOCK_300M, ++ CLOCK_62_5M, CLOCK_98_304M, CLOCK_150M, CLOCK_196_608M }; ++ int val = ((ltq_cgu_r32(LTQ_CGU_IF_CLK) >> 25) & 0xf); ++ ++ if (val > 13) ++ panic("bad fpi speed\n"); ++ ++ return clks[val]; ++} ++EXPORT_SYMBOL(ltq_get_fpi_hz); ++ ++unsigned int ltq_get_io_region_clock(void) ++{ ++ return ltq_get_fpi_hz() / 2; ++} ++EXPORT_SYMBOL(ltq_get_io_region_clock); ++ ++unsigned int ltq_get_fpi_bus_clock(int fpi) ++{ ++ return ltq_get_fpi_hz(); ++} ++EXPORT_SYMBOL(ltq_get_fpi_bus_clock); +--- /dev/null ++++ b/arch/mips/lantiq/xway/prom-vr9.c +@@ -0,0 +1,55 @@ ++/* ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ * Copyright (C) 2010 John Crispin <blogic@openwrt.org> ++ */ ++ ++#include <linux/module.h> ++#include <linux/clk.h> ++#include <asm/bootinfo.h> ++#include <asm/time.h> ++ ++#include <lantiq_soc.h> ++ ++#include "devices.h" ++#include "../prom.h" ++ ++#define SOC_VRX288 "VRX288" ++ ++#define PART_SHIFT 12 ++#define PART_MASK 0x0FFFFFFF ++#define REV_SHIFT 28 ++#define REV_MASK 0xF0000000 ++ ++void __init ltq_soc_detect(struct ltq_soc_info *i) ++{ ++ i->partnum = (ltq_r32(LTQ_MPS_CHIPID) & PART_MASK) >> PART_SHIFT; ++ i->rev = (ltq_r32(LTQ_MPS_CHIPID) & REV_MASK) >> REV_SHIFT; ++ sprintf(i->rev_type, "1.%d", i->rev); ++ switch (i->partnum) { ++ case SOC_ID_VRX288: ++ i->name = SOC_VRX288; ++ i->type = SOC_TYPE_VR9; ++ break; ++ ++ default: ++ unreachable(); ++ break; ++ } ++ printk("%08X\n", i->partnum); ++} ++ ++void __init ltq_soc_setup(void) ++{ ++ /* ++ reg = IFX_REG_R32(IFX_XBAR_ALWAYS_LAST); ++ reg &= ~ IFX_XBAR_FPI_BURST_EN; ++ IFX_REG_W32(reg, IFX_XBAR_ALWAYS_LAST); ++ */ ++ ++ ltq_register_asc(1); ++ ltq_register_gpio(); ++ ltq_register_wdt(); ++} +--- a/arch/mips/pci/Makefile ++++ b/arch/mips/pci/Makefile +@@ -41,7 +41,7 @@ obj-$(CONFIG_SIBYTE_SB1250) += fixup-sb1 + obj-$(CONFIG_SIBYTE_BCM112X) += fixup-sb1250.o pci-sb1250.o + obj-$(CONFIG_SIBYTE_BCM1x80) += pci-bcm1480.o pci-bcm1480ht.o + obj-$(CONFIG_SNI_RM) += fixup-sni.o ops-sni.o +-obj-$(CONFIG_SOC_XWAY) += pci-lantiq.o ops-lantiq.o ++obj-$(CONFIG_LANTIQ) += pci-lantiq.o ops-lantiq.o + obj-$(CONFIG_TANBAC_TB0219) += fixup-tb0219.o + obj-$(CONFIG_TANBAC_TB0226) += fixup-tb0226.o + obj-$(CONFIG_TANBAC_TB0287) += fixup-tb0287.o diff --git a/target/linux/lantiq/patches/0024-MIPS-lantiq-fixes-STP-based-gpios.patch b/target/linux/lantiq/patches/0024-MIPS-lantiq-fixes-STP-based-gpios.patch new file mode 100644 index 0000000000..04f84e0b51 --- /dev/null +++ b/target/linux/lantiq/patches/0024-MIPS-lantiq-fixes-STP-based-gpios.patch @@ -0,0 +1,36 @@ +From 2dfa2b3e50c5ac49052233d15fa427a9b9136df8 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 27 Oct 2011 20:06:05 +0200 +Subject: [PATCH 10/22] MIPS: lantiq: fixes STP based gpios + +The STP engine has 3 groups of 8 pins. Only the first was activated by default. + +Signed-off-by: Matti Laakso <malaakso@elisanet.fi> +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/lantiq/xway/gpio_stp.c | 7 +++++-- + 1 files changed, 5 insertions(+), 2 deletions(-) + +--- a/arch/mips/lantiq/xway/gpio_stp.c ++++ b/arch/mips/lantiq/xway/gpio_stp.c +@@ -35,6 +35,8 @@ + #define LTQ_STP_ADSL_SRC (3 << 24) + + #define LTQ_STP_GROUP0 (1 << 0) ++#define LTQ_STP_GROUP1 (1 << 1) ++#define LTQ_STP_GROUP2 (1 << 2) + + #define LTQ_STP_RISING 0 + #define LTQ_STP_FALLING (1 << 26) +@@ -93,8 +95,9 @@ static int ltq_stp_hw_init(void) + /* rising or falling edge */ + ltq_stp_w32_mask(LTQ_STP_EDGE_MASK, LTQ_STP_FALLING, LTQ_STP_CON0); + +- /* per default stp 15-0 are set */ +- ltq_stp_w32_mask(0, LTQ_STP_GROUP0, LTQ_STP_CON1); ++ /* enable all three led groups */ ++ ltq_stp_w32_mask(0, LTQ_STP_GROUP0 | LTQ_STP_GROUP1 | LTQ_STP_GROUP2, ++ LTQ_STP_CON1); + + /* stp are update periodically by the FPI bus */ + ltq_stp_w32_mask(LTQ_STP_UPD_MASK, LTQ_STP_UPD_FPI, LTQ_STP_CON1); diff --git a/target/linux/lantiq/patches/0025-MIPS-lantiq-activate-pull-up-resistors-when-gpio-is-.patch b/target/linux/lantiq/patches/0025-MIPS-lantiq-activate-pull-up-resistors-when-gpio-is-.patch new file mode 100644 index 0000000000..f8146f78c7 --- /dev/null +++ b/target/linux/lantiq/patches/0025-MIPS-lantiq-activate-pull-up-resistors-when-gpio-is-.patch @@ -0,0 +1,43 @@ +From 6efd9a5f303c4561eee14ae429b8c0fafa6c5a83 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Thu, 27 Oct 2011 20:06:30 +0200 +Subject: [PATCH 11/22] MIPS: lantiq: activate pull up resistors when gpio is + a input + +The register that enables a gpios internal pullups was not set. + +Signed-off-by: Matti Laakso <malaakso@elisanet.fi> +Signed-off-by: John Crispin <blogic@openwrt.org> +--- + arch/mips/lantiq/xway/gpio.c | 6 ++++++ + 1 files changed, 6 insertions(+), 0 deletions(-) + +--- a/arch/mips/lantiq/xway/gpio.c ++++ b/arch/mips/lantiq/xway/gpio.c +@@ -21,6 +21,8 @@ + #define LTQ_GPIO_ALTSEL0 0x0C + #define LTQ_GPIO_ALTSEL1 0x10 + #define LTQ_GPIO_OD 0x14 ++#define LTQ_GPIO_PUDSEL 0x1C ++#define LTQ_GPIO_PUDEN 0x20 + + #define PINS_PER_PORT 16 + #define MAX_PORTS 3 +@@ -106,6 +108,8 @@ static int ltq_gpio_direction_input(stru + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); + + return 0; + } +@@ -117,6 +121,8 @@ static int ltq_gpio_direction_output(str + + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); + ltq_gpio_set(chip, offset, value); + + return 0; diff --git a/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch b/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch new file mode 100644 index 0000000000..e96d9b70d6 --- /dev/null +++ b/target/linux/lantiq/patches/0026-MIPS-lantiq-adds-GPIO3-support-on-AR9.patch @@ -0,0 +1,199 @@ +From 92b24777385cd8388e0fa8b9f1d24e5bc4466641 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 13 Aug 2011 13:59:50 +0200 +Subject: [PATCH 12/22] MIPS: lantiq: make GPIO3 work on AR9 + +There are 3 16bit and 1 8bit gpio ports on AR9. The gpio driver needs a hack +at 2 places to make the different register layout of the GPIO3 work properly +with the driver. Before only GPIO0-2 were supported. As the GPIO number scheme +clashes with the new size, we also move the other gpio chips to new offsets. + +Signed-off-by: John Crispin <blogic@openwrt.org> +Signed-off-by: Thomas Langer <thomas.langer@lantiq.com> +--- + .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 2 + + arch/mips/lantiq/xway/devices.c | 3 + + arch/mips/lantiq/xway/gpio.c | 62 ++++++++++++++++---- + arch/mips/lantiq/xway/gpio_ebu.c | 3 +- + arch/mips/lantiq/xway/gpio_stp.c | 3 +- + 5 files changed, 57 insertions(+), 16 deletions(-) + +--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h ++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h +@@ -113,7 +113,9 @@ + #define LTQ_GPIO0_BASE_ADDR 0x1E100B10 + #define LTQ_GPIO1_BASE_ADDR 0x1E100B40 + #define LTQ_GPIO2_BASE_ADDR 0x1E100B70 ++#define LTQ_GPIO3_BASE_ADDR 0x1E100BA0 + #define LTQ_GPIO_SIZE 0x30 ++#define LTQ_GPIO3_SIZE 0x10 + + /* SSC */ + #define LTQ_SSC_BASE_ADDR 0x1e100800 +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -34,6 +34,7 @@ static struct resource ltq_gpio_resource + MEM_RES("gpio0", LTQ_GPIO0_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio1", LTQ_GPIO1_BASE_ADDR, LTQ_GPIO_SIZE), + MEM_RES("gpio2", LTQ_GPIO2_BASE_ADDR, LTQ_GPIO_SIZE), ++ MEM_RES("gpio3", LTQ_GPIO3_BASE_ADDR, LTQ_GPIO3_SIZE), + }; + + void __init ltq_register_gpio(void) +@@ -47,6 +48,8 @@ void __init ltq_register_gpio(void) + if (ltq_is_ar9() || ltq_is_vr9()) { + platform_device_register_simple("ltq_gpio", 2, + <q_gpio_resource[2], 1); ++ platform_device_register_simple("ltq_gpio", 3, ++ <q_gpio_resource[3], 1); + } + } + +--- a/arch/mips/lantiq/xway/gpio.c ++++ b/arch/mips/lantiq/xway/gpio.c +@@ -23,9 +23,15 @@ + #define LTQ_GPIO_OD 0x14 + #define LTQ_GPIO_PUDSEL 0x1C + #define LTQ_GPIO_PUDEN 0x20 ++#define LTQ_GPIO3_OD 0x24 ++#define LTQ_GPIO3_ALTSEL1 0x24 + ++/* PORT3 only has 8 pins and its register layout ++ is slightly different */ + #define PINS_PER_PORT 16 +-#define MAX_PORTS 3 ++#define PINS_PORT3 8 ++#define MAX_PORTS 4 ++#define MAX_PIN 56 + + #define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p))) + #define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r) +@@ -55,7 +61,7 @@ int ltq_gpio_request(unsigned int pin, u + { + int id = 0; + +- if (pin >= (MAX_PORTS * PINS_PER_PORT)) ++ if (pin >= MAX_PIN) + return -EINVAL; + if (gpio_request(pin, name)) { + pr_err("failed to setup lantiq gpio: %s\n", name); +@@ -75,12 +81,21 @@ int ltq_gpio_request(unsigned int pin, u + else + ltq_gpio_clearbit(ltq_gpio_port[id].membase, + LTQ_GPIO_ALTSEL0, pin); +- if (alt1) +- ltq_gpio_setbit(ltq_gpio_port[id].membase, +- LTQ_GPIO_ALTSEL1, pin); +- else +- ltq_gpio_clearbit(ltq_gpio_port[id].membase, +- LTQ_GPIO_ALTSEL1, pin); ++ if (id == 3) { ++ if (alt1) ++ ltq_gpio_setbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, pin); ++ else ++ ltq_gpio_clearbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, pin); ++ } else { ++ if (alt1) ++ ltq_gpio_setbit(ltq_gpio_port[id].membase, ++ LTQ_GPIO_ALTSEL1, pin); ++ else ++ ltq_gpio_clearbit(ltq_gpio_port[id].membase, ++ LTQ_GPIO_ALTSEL1, pin); ++ } + return 0; + } + EXPORT_SYMBOL(ltq_gpio_request); +@@ -106,7 +121,11 @@ static int ltq_gpio_direction_input(stru + { + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + +- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ if (chip->ngpio == PINS_PORT3) ++ ltq_gpio_clearbit(ltq_gpio_port[0].membase, ++ LTQ_GPIO3_OD, offset); ++ else ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); +@@ -119,7 +138,10 @@ static int ltq_gpio_direction_output(str + { + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + +- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); ++ if (chip->ngpio == PINS_PORT3) ++ ltq_gpio_setbit(ltq_gpio_port[0].membase, LTQ_GPIO3_OD, offset); ++ else ++ ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset); + ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDSEL, offset); + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_PUDEN, offset); +@@ -133,7 +155,11 @@ static int ltq_gpio_req(struct gpio_chip + struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip); + + ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset); +- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); ++ if (chip->ngpio == PINS_PORT3) ++ ltq_gpio_clearbit(ltq_gpio_port[1].membase, ++ LTQ_GPIO3_ALTSEL1, offset); ++ else ++ ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset); + return 0; + } + +@@ -146,6 +172,15 @@ static int ltq_gpio_probe(struct platfor + pdev->id); + return -EINVAL; + } ++ ++ /* dirty hack - The registers of port3 are not mapped linearly. ++ Port 3 may only load if Port 1/2 are mapped */ ++ if ((pdev->id == 3) && (!ltq_gpio_port[1].membase || !ltq_gpio_port[2].membase)) { ++ dev_err(&pdev->dev, ++ "ports 1/2 need to be loaded before port 3 works\n"); ++ return -ENOMEM; ++ } ++ + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (!res) { + dev_err(&pdev->dev, "failed to get memory for gpio port %d\n", +@@ -175,7 +210,10 @@ static int ltq_gpio_probe(struct platfor + ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set; + ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req; + ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id; +- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; ++ if (pdev->id == 3) ++ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PORT3; ++ else ++ ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT; + platform_set_drvdata(pdev, <q_gpio_port[pdev->id]); + return gpiochip_add(<q_gpio_port[pdev->id].chip); + } +--- a/arch/mips/lantiq/xway/gpio_ebu.c ++++ b/arch/mips/lantiq/xway/gpio_ebu.c +@@ -61,9 +61,8 @@ static struct gpio_chip ltq_ebu_chip = { + .label = "ltq_ebu", + .direction_output = ltq_ebu_direction_output, + .set = ltq_ebu_set, +- .base = 72, ++ .base = 100, + .ngpio = 16, +- .can_sleep = 1, + .owner = THIS_MODULE, + }; + +--- a/arch/mips/lantiq/xway/gpio_stp.c ++++ b/arch/mips/lantiq/xway/gpio_stp.c +@@ -72,9 +72,8 @@ static struct gpio_chip ltq_stp_chip = { + .label = "ltq_stp", + .direction_output = ltq_stp_direction_output, + .set = ltq_stp_set, +- .base = 48, ++ .base = 200, + .ngpio = 24, +- .can_sleep = 1, + .owner = THIS_MODULE, + }; + diff --git a/target/linux/lantiq/patches/100-falcon_bsp_header.patch b/target/linux/lantiq/patches/100-falcon_bsp_header.patch new file mode 100644 index 0000000000..4e8ce08365 --- /dev/null +++ b/target/linux/lantiq/patches/100-falcon_bsp_header.patch @@ -0,0 +1,13678 @@ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h +@@ -0,0 +1,376 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _gpon_reg_base_h ++#define _gpon_reg_base_h ++ ++/** \addtogroup GPON_BASE ++ @{ ++*/ ++ ++#ifndef KSEG1 ++#define KSEG1 0xA0000000 ++#endif ++ ++/** address range for ebu ++ 0x18000000--0x180000FF */ ++#define GPON_EBU_BASE (KSEG1 | 0x18000000) ++#define GPON_EBU_END (KSEG1 | 0x180000FF) ++#define GPON_EBU_SIZE 0x00000100 ++/** address range for gpearb ++ 0x1D400100--0x1D4001FF */ ++#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100) ++#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF) ++#define GPON_GPEARB_SIZE 0x00000100 ++/** address range for tmu ++ 0x1D404000--0x1D404FFF */ ++#define GPON_TMU_BASE (KSEG1 | 0x1D404000) ++#define GPON_TMU_END (KSEG1 | 0x1D404FFF) ++#define GPON_TMU_SIZE 0x00001000 ++/** address range for iqm ++ 0x1D410000--0x1D41FFFF */ ++#define GPON_IQM_BASE (KSEG1 | 0x1D410000) ++#define GPON_IQM_END (KSEG1 | 0x1D41FFFF) ++#define GPON_IQM_SIZE 0x00010000 ++/** address range for octrlg ++ 0x1D420000--0x1D42FFFF */ ++#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000) ++#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF) ++#define GPON_OCTRLG_SIZE 0x00010000 ++/** address range for octrll0 ++ 0x1D440000--0x1D4400FF */ ++#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000) ++#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF) ++#define GPON_OCTRLL0_SIZE 0x00000100 ++/** address range for octrll1 ++ 0x1D440100--0x1D4401FF */ ++#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100) ++#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF) ++#define GPON_OCTRLL1_SIZE 0x00000100 ++/** address range for octrll2 ++ 0x1D440200--0x1D4402FF */ ++#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200) ++#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF) ++#define GPON_OCTRLL2_SIZE 0x00000100 ++/** address range for octrll3 ++ 0x1D440300--0x1D4403FF */ ++#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300) ++#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF) ++#define GPON_OCTRLL3_SIZE 0x00000100 ++/** address range for octrlc ++ 0x1D441000--0x1D4410FF */ ++#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000) ++#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF) ++#define GPON_OCTRLC_SIZE 0x00000100 ++/** address range for ictrlg ++ 0x1D450000--0x1D45FFFF */ ++#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000) ++#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF) ++#define GPON_ICTRLG_SIZE 0x00010000 ++/** address range for ictrll0 ++ 0x1D460000--0x1D4601FF */ ++#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000) ++#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF) ++#define GPON_ICTRLL0_SIZE 0x00000200 ++/** address range for ictrll1 ++ 0x1D460200--0x1D4603FF */ ++#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200) ++#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF) ++#define GPON_ICTRLL1_SIZE 0x00000200 ++/** address range for ictrll2 ++ 0x1D460400--0x1D4605FF */ ++#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400) ++#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF) ++#define GPON_ICTRLL2_SIZE 0x00000200 ++/** address range for ictrll3 ++ 0x1D460600--0x1D4607FF */ ++#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600) ++#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF) ++#define GPON_ICTRLL3_SIZE 0x00000200 ++/** address range for ictrlc0 ++ 0x1D461000--0x1D4610FF */ ++#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000) ++#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF) ++#define GPON_ICTRLC0_SIZE 0x00000100 ++/** address range for ictrlc1 ++ 0x1D461100--0x1D4611FF */ ++#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100) ++#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF) ++#define GPON_ICTRLC1_SIZE 0x00000100 ++/** address range for fsqm ++ 0x1D500000--0x1D5FFFFF */ ++#define GPON_FSQM_BASE (KSEG1 | 0x1D500000) ++#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF) ++#define GPON_FSQM_SIZE 0x00100000 ++/** address range for pctrl ++ 0x1D600000--0x1D6001FF */ ++#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000) ++#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF) ++#define GPON_PCTRL_SIZE 0x00000200 ++/** address range for link0 ++ 0x1D600200--0x1D6002FF */ ++#define GPON_LINK0_BASE (KSEG1 | 0x1D600200) ++#define GPON_LINK0_END (KSEG1 | 0x1D6002FF) ++#define GPON_LINK0_SIZE 0x00000100 ++/** address range for link1 ++ 0x1D600300--0x1D6003FF */ ++#define GPON_LINK1_BASE (KSEG1 | 0x1D600300) ++#define GPON_LINK1_END (KSEG1 | 0x1D6003FF) ++#define GPON_LINK1_SIZE 0x00000100 ++/** address range for link2 ++ 0x1D600400--0x1D6004FF */ ++#define GPON_LINK2_BASE (KSEG1 | 0x1D600400) ++#define GPON_LINK2_END (KSEG1 | 0x1D6004FF) ++#define GPON_LINK2_SIZE 0x00000100 ++/** address range for disp ++ 0x1D600500--0x1D6005FF */ ++#define GPON_DISP_BASE (KSEG1 | 0x1D600500) ++#define GPON_DISP_END (KSEG1 | 0x1D6005FF) ++#define GPON_DISP_SIZE 0x00000100 ++/** address range for merge ++ 0x1D600600--0x1D6006FF */ ++#define GPON_MERGE_BASE (KSEG1 | 0x1D600600) ++#define GPON_MERGE_END (KSEG1 | 0x1D6006FF) ++#define GPON_MERGE_SIZE 0x00000100 ++/** address range for tbm ++ 0x1D600700--0x1D6007FF */ ++#define GPON_TBM_BASE (KSEG1 | 0x1D600700) ++#define GPON_TBM_END (KSEG1 | 0x1D6007FF) ++#define GPON_TBM_SIZE 0x00000100 ++/** address range for pe0 ++ 0x1D610000--0x1D61FFFF */ ++#define GPON_PE0_BASE (KSEG1 | 0x1D610000) ++#define GPON_PE0_END (KSEG1 | 0x1D61FFFF) ++#define GPON_PE0_SIZE 0x00010000 ++/** address range for pe1 ++ 0x1D620000--0x1D62FFFF */ ++#define GPON_PE1_BASE (KSEG1 | 0x1D620000) ++#define GPON_PE1_END (KSEG1 | 0x1D62FFFF) ++#define GPON_PE1_SIZE 0x00010000 ++/** address range for pe2 ++ 0x1D630000--0x1D63FFFF */ ++#define GPON_PE2_BASE (KSEG1 | 0x1D630000) ++#define GPON_PE2_END (KSEG1 | 0x1D63FFFF) ++#define GPON_PE2_SIZE 0x00010000 ++/** address range for pe3 ++ 0x1D640000--0x1D64FFFF */ ++#define GPON_PE3_BASE (KSEG1 | 0x1D640000) ++#define GPON_PE3_END (KSEG1 | 0x1D64FFFF) ++#define GPON_PE3_SIZE 0x00010000 ++/** address range for pe4 ++ 0x1D650000--0x1D65FFFF */ ++#define GPON_PE4_BASE (KSEG1 | 0x1D650000) ++#define GPON_PE4_END (KSEG1 | 0x1D65FFFF) ++#define GPON_PE4_SIZE 0x00010000 ++/** address range for pe5 ++ 0x1D660000--0x1D66FFFF */ ++#define GPON_PE5_BASE (KSEG1 | 0x1D660000) ++#define GPON_PE5_END (KSEG1 | 0x1D66FFFF) ++#define GPON_PE5_SIZE 0x00010000 ++/** address range for sys_gpe ++ 0x1D700000--0x1D7000FF */ ++#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000) ++#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF) ++#define GPON_SYS_GPE_SIZE 0x00000100 ++/** address range for eim ++ 0x1D800000--0x1D800FFF */ ++#define GPON_EIM_BASE (KSEG1 | 0x1D800000) ++#define GPON_EIM_END (KSEG1 | 0x1D800FFF) ++#define GPON_EIM_SIZE 0x00001000 ++/** address range for sxgmii ++ 0x1D808800--0x1D8088FF */ ++#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800) ++#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF) ++#define GPON_SXGMII_SIZE 0x00000100 ++/** address range for sgmii ++ 0x1D808C00--0x1D808CFF */ ++#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00) ++#define GPON_SGMII_END (KSEG1 | 0x1D808CFF) ++#define GPON_SGMII_SIZE 0x00000100 ++/** address range for gpio0 ++ 0x1D810000--0x1D81007F */ ++#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000) ++#define GPON_GPIO0_END (KSEG1 | 0x1D81007F) ++#define GPON_GPIO0_SIZE 0x00000080 ++/** address range for gpio2 ++ 0x1D810100--0x1D81017F */ ++#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100) ++#define GPON_GPIO2_END (KSEG1 | 0x1D81017F) ++#define GPON_GPIO2_SIZE 0x00000080 ++/** address range for sys_eth ++ 0x1DB00000--0x1DB000FF */ ++#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000) ++#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF) ++#define GPON_SYS_ETH_SIZE 0x00000100 ++/** address range for padctrl0 ++ 0x1DB01000--0x1DB010FF */ ++#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000) ++#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF) ++#define GPON_PADCTRL0_SIZE 0x00000100 ++/** address range for padctrl2 ++ 0x1DB02000--0x1DB020FF */ ++#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000) ++#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF) ++#define GPON_PADCTRL2_SIZE 0x00000100 ++/** address range for gtc ++ 0x1DC05000--0x1DC052D4 */ ++#define GPON_GTC_BASE (KSEG1 | 0x1DC05000) ++#define GPON_GTC_END (KSEG1 | 0x1DC052D4) ++#define GPON_GTC_SIZE 0x000002D5 ++/** address range for pma ++ 0x1DD00000--0x1DD003FF */ ++#define GPON_PMA_BASE (KSEG1 | 0x1DD00000) ++#define GPON_PMA_END (KSEG1 | 0x1DD003FF) ++#define GPON_PMA_SIZE 0x00000400 ++/** address range for fcsic ++ 0x1DD00600--0x1DD0061F */ ++#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600) ++#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F) ++#define GPON_FCSIC_SIZE 0x00000020 ++/** address range for pma_int200 ++ 0x1DD00700--0x1DD0070F */ ++#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700) ++#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F) ++#define GPON_PMA_INT200_SIZE 0x00000010 ++/** address range for pma_inttx ++ 0x1DD00720--0x1DD0072F */ ++#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720) ++#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F) ++#define GPON_PMA_INTTX_SIZE 0x00000010 ++/** address range for pma_intrx ++ 0x1DD00740--0x1DD0074F */ ++#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740) ++#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F) ++#define GPON_PMA_INTRX_SIZE 0x00000010 ++/** address range for gtc_pma ++ 0x1DEFFF00--0x1DEFFFFF */ ++#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00) ++#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF) ++#define GPON_GTC_PMA_SIZE 0x00000100 ++/** address range for sys ++ 0x1DF00000--0x1DF000FF */ ++#define GPON_SYS_BASE (KSEG1 | 0x1DF00000) ++#define GPON_SYS_END (KSEG1 | 0x1DF000FF) ++#define GPON_SYS_SIZE 0x00000100 ++/** address range for asc1 ++ 0x1E100B00--0x1E100BFF */ ++#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00) ++#define GPON_ASC1_END (KSEG1 | 0x1E100BFF) ++#define GPON_ASC1_SIZE 0x00000100 ++/** address range for asc0 ++ 0x1E100C00--0x1E100CFF */ ++#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00) ++#define GPON_ASC0_END (KSEG1 | 0x1E100CFF) ++#define GPON_ASC0_SIZE 0x00000100 ++/** address range for i2c ++ 0x1E200000--0x1E20FFFF */ ++#define GPON_I2C_BASE (KSEG1 | 0x1E200000) ++#define GPON_I2C_END (KSEG1 | 0x1E20FFFF) ++#define GPON_I2C_SIZE 0x00010000 ++/** address range for gpio1 ++ 0x1E800100--0x1E80017F */ ++#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100) ++#define GPON_GPIO1_END (KSEG1 | 0x1E80017F) ++#define GPON_GPIO1_SIZE 0x00000080 ++/** address range for gpio3 ++ 0x1E800200--0x1E80027F */ ++#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200) ++#define GPON_GPIO3_END (KSEG1 | 0x1E80027F) ++#define GPON_GPIO3_SIZE 0x00000080 ++/** address range for gpio4 ++ 0x1E800300--0x1E80037F */ ++#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300) ++#define GPON_GPIO4_END (KSEG1 | 0x1E80037F) ++#define GPON_GPIO4_SIZE 0x00000080 ++/** address range for padctrl1 ++ 0x1E800400--0x1E8004FF */ ++#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400) ++#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF) ++#define GPON_PADCTRL1_SIZE 0x00000100 ++/** address range for padctrl3 ++ 0x1E800500--0x1E8005FF */ ++#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500) ++#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF) ++#define GPON_PADCTRL3_SIZE 0x00000100 ++/** address range for padctrl4 ++ 0x1E800600--0x1E8006FF */ ++#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600) ++#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF) ++#define GPON_PADCTRL4_SIZE 0x00000100 ++/** address range for status ++ 0x1E802000--0x1E80207F */ ++#define GPON_STATUS_BASE (KSEG1 | 0x1E802000) ++#define GPON_STATUS_END (KSEG1 | 0x1E80207F) ++#define GPON_STATUS_SIZE 0x00000080 ++/** address range for dcdc_1v0 ++ 0x1E803000--0x1E8033FF */ ++#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000) ++#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF) ++#define GPON_DCDC_1V0_SIZE 0x00000400 ++/** address range for dcdc_ddr ++ 0x1E804000--0x1E8043FF */ ++#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000) ++#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF) ++#define GPON_DCDC_DDR_SIZE 0x00000400 ++/** address range for dcdc_apd ++ 0x1E805000--0x1E8053FF */ ++#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000) ++#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF) ++#define GPON_DCDC_APD_SIZE 0x00000400 ++/** address range for sys1 ++ 0x1EF00000--0x1EF000FF */ ++#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000) ++#define GPON_SYS1_END (KSEG1 | 0x1EF000FF) ++#define GPON_SYS1_SIZE 0x00000100 ++/** address range for sbs0ctrl ++ 0x1F080000--0x1F0801FF */ ++#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000) ++#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF) ++#define GPON_SBS0CTRL_SIZE 0x00000200 ++/** address range for sbs0red ++ 0x1F080200--0x1F08027F */ ++#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200) ++#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F) ++#define GPON_SBS0RED_SIZE 0x00000080 ++/** address range for sbs0ram ++ 0x1F200000--0x1F32FFFF */ ++#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000) ++#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF) ++#define GPON_SBS0RAM_SIZE 0x00130000 ++/** address range for ddrdb ++ 0x1F701000--0x1F701FFF */ ++#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000) ++#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF) ++#define GPON_DDRDB_SIZE 0x00001000 ++/** address range for sbiu ++ 0x1F880000--0x1F8800FF */ ++#define GPON_SBIU_BASE (KSEG1 | 0x1F880000) ++#define GPON_SBIU_END (KSEG1 | 0x1F8800FF) ++#define GPON_SBIU_SIZE 0x00000100 ++/** address range for icu0 ++ 0x1F880200--0x1F8802DF */ ++#define GPON_ICU0_BASE (KSEG1 | 0x1F880200) ++#define GPON_ICU0_END (KSEG1 | 0x1F8802DF) ++#define GPON_ICU0_SIZE 0x000000E0 ++/** address range for icu1 ++ 0x1F880300--0x1F8803DF */ ++#define GPON_ICU1_BASE (KSEG1 | 0x1F880300) ++#define GPON_ICU1_END (KSEG1 | 0x1F8803DF) ++#define GPON_ICU1_SIZE 0x000000E0 ++/** address range for wdt ++ 0x1F8803F0--0x1F8803FF */ ++#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0) ++#define GPON_WDT_END (KSEG1 | 0x1F8803FF) ++#define GPON_WDT_SIZE 0x00000010 ++ ++/*! @} */ /* GPON_BASE */ ++ ++#endif /* _gpon_reg_base_h */ ++ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h +@@ -0,0 +1,830 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _i2c_reg_h ++#define _i2c_reg_h ++ ++/** \addtogroup I2C_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define i2c_r32(reg) reg_r32(&i2c->reg) ++#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) ++#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) ++#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx) ++#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx) ++#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx) ++#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx) ++ ++ ++/** I2C register structure */ ++struct gpon_reg_i2c ++{ ++ /** I2C Kernel Clock Control Register */ ++ unsigned int clc; /* 0x00000000 */ ++ /** Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /** I2C Identification Register */ ++ unsigned int id; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /** I2C RUN Control Register ++ This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */ ++ unsigned int run_ctrl; /* 0x00000010 */ ++ /** I2C End Data Control Register ++ This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */ ++ unsigned int endd_ctrl; /* 0x00000014 */ ++ /** I2C Fractional Divider Configuration Register ++ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */ ++ unsigned int fdiv_cfg; /* 0x00000018 */ ++ /** I2C Fractional Divider (highspeed mode) Configuration Register ++ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */ ++ unsigned int fdiv_high_cfg; /* 0x0000001C */ ++ /** I2C Address Configuration Register */ ++ unsigned int addr_cfg; /* 0x00000020 */ ++ /** I2C Bus Status Register ++ This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */ ++ unsigned int bus_stat; /* 0x00000024 */ ++ /** I2C FIFO Configuration Register */ ++ unsigned int fifo_cfg; /* 0x00000028 */ ++ /** I2C Maximum Received Packet Size Register */ ++ unsigned int mrps_ctrl; /* 0x0000002C */ ++ /** I2C Received Packet Size Status Register */ ++ unsigned int rps_stat; /* 0x00000030 */ ++ /** I2C Transmit Packet Size Register */ ++ unsigned int tps_ctrl; /* 0x00000034 */ ++ /** I2C Filled FIFO Stages Status Register */ ++ unsigned int ffs_stat; /* 0x00000038 */ ++ /** Reserved */ ++ unsigned int res_2; /* 0x0000003C */ ++ /** I2C Timing Configuration Register */ ++ unsigned int tim_cfg; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_3[7]; /* 0x00000044 */ ++ /** I2C Error Interrupt Request Source Mask Register */ ++ unsigned int err_irqsm; /* 0x00000060 */ ++ /** I2C Error Interrupt Request Source Status Register */ ++ unsigned int err_irqss; /* 0x00000064 */ ++ /** I2C Error Interrupt Request Source Clear Register */ ++ unsigned int err_irqsc; /* 0x00000068 */ ++ /** Reserved */ ++ unsigned int res_4; /* 0x0000006C */ ++ /** I2C Protocol Interrupt Request Source Mask Register */ ++ unsigned int p_irqsm; /* 0x00000070 */ ++ /** I2C Protocol Interrupt Request Source Status Register */ ++ unsigned int p_irqss; /* 0x00000074 */ ++ /** I2C Protocol Interrupt Request Source Clear Register */ ++ unsigned int p_irqsc; /* 0x00000078 */ ++ /** Reserved */ ++ unsigned int res_5; /* 0x0000007C */ ++ /** I2C Raw Interrupt Status Register */ ++ unsigned int ris; /* 0x00000080 */ ++ /** I2C Interrupt Mask Control Register */ ++ unsigned int imsc; /* 0x00000084 */ ++ /** I2C Masked Interrupt Status Register */ ++ unsigned int mis; /* 0x00000088 */ ++ /** I2C Interrupt Clear Register */ ++ unsigned int icr; /* 0x0000008C */ ++ /** I2C Interrupt Set Register */ ++ unsigned int isr; /* 0x00000090 */ ++ /** I2C DMA Enable Register */ ++ unsigned int dmae; /* 0x00000094 */ ++ /** Reserved */ ++ unsigned int res_6[8154]; /* 0x00000098 */ ++ /** I2C Transmit Data Register */ ++ unsigned int txd; /* 0x00008000 */ ++ /** Reserved */ ++ unsigned int res_7[4095]; /* 0x00008004 */ ++ /** I2C Receive Data Register */ ++ unsigned int rxd; /* 0x0000C000 */ ++ /** Reserved */ ++ unsigned int res_8[4095]; /* 0x0000C004 */ ++}; ++ ++ ++/* Fields of "I2C Kernel Clock Control Register" */ ++/** Clock Divider for Optional Run Mode (AHB peripherals) ++ Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */ ++#define I2C_CLC_ORMC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_CLC_ORMC_OFFSET 16 ++/** Clock Divider for Normal Run Mode ++ Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */ ++#define I2C_CLC_RMC_MASK 0x0000FF00 ++/** field offset */ ++#define I2C_CLC_RMC_OFFSET 8 ++/** Fast Shut-Off Enable Bit */ ++#define I2C_CLC_FSOE 0x00000020 ++/* Disable ++#define I2C_CLC_FSOE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_FSOE_EN 0x00000020 ++/** Suspend Bit Write Enable for OCDS */ ++#define I2C_CLC_SBWE 0x00000010 ++/* Disable ++#define I2C_CLC_SBWE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_SBWE_EN 0x00000010 ++/** Disable External Request Disable */ ++#define I2C_CLC_EDIS 0x00000008 ++/* Enable ++#define I2C_CLC_EDIS_EN 0x00000000 */ ++/** Disable */ ++#define I2C_CLC_EDIS_DIS 0x00000008 ++/** Suspend Enable Bit for OCDS */ ++#define I2C_CLC_SPEN 0x00000004 ++/* Disable ++#define I2C_CLC_SPEN_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_CLC_SPEN_EN 0x00000004 ++/** Disable Status Bit ++ Bit DISS can be modified only by writing to bit DISR */ ++#define I2C_CLC_DISS 0x00000002 ++/* Enable ++#define I2C_CLC_DISS_EN 0x00000000 */ ++/** Disable */ ++#define I2C_CLC_DISS_DIS 0x00000002 ++/** Disable Request Bit */ ++#define I2C_CLC_DISR 0x00000001 ++/* Module disable not requested ++#define I2C_CLC_DISR_OFF 0x00000000 */ ++/** Module disable requested */ ++#define I2C_CLC_DISR_ON 0x00000001 ++ ++/* Fields of "I2C Identification Register" */ ++/** Module ID */ ++#define I2C_ID_ID_MASK 0x0000FF00 ++/** field offset */ ++#define I2C_ID_ID_OFFSET 8 ++/** Revision */ ++#define I2C_ID_REV_MASK 0x000000FF ++/** field offset */ ++#define I2C_ID_REV_OFFSET 0 ++ ++/* Fields of "I2C RUN Control Register" */ ++/** Enabling I2C Interface ++ Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */ ++#define I2C_RUN_CTRL_RUN 0x00000001 ++/* Disable ++#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_RUN_CTRL_RUN_EN 0x00000001 ++ ++/* Fields of "I2C End Data Control Register" */ ++/** Set End of Transmission ++ Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */ ++#define I2C_ENDD_CTRL_SETEND 0x00000002 ++/* No-Operation ++#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */ ++/** Master Receives Bytes */ ++#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002 ++/** Set Restart Condition */ ++#define I2C_ENDD_CTRL_SETRSC 0x00000001 ++/* No-Operation ++#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */ ++/** Master Restart */ ++#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001 ++ ++/* Fields of "I2C Fractional Divider Configuration Register" */ ++/** Decrement Value of fractional divider */ ++#define I2C_FDIV_CFG_INC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_FDIV_CFG_INC_OFFSET 16 ++/** Increment Value of fractional divider */ ++#define I2C_FDIV_CFG_DEC_MASK 0x000007FF ++/** field offset */ ++#define I2C_FDIV_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */ ++/** Decrement Value of fractional divider */ ++#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000 ++/** field offset */ ++#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 ++/** Increment Value of fractional divider */ ++#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF ++/** field offset */ ++#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 ++ ++/* Fields of "I2C Address Configuration Register" */ ++/** Stop on Packet End ++ If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */ ++#define I2C_ADDR_CFG_SOPE 0x00200000 ++/* Disable ++#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_SOPE_EN 0x00200000 ++/** Stop on Not Acknowledge ++ After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */ ++#define I2C_ADDR_CFG_SONA 0x00100000 ++/* Disable ++#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_SONA_EN 0x00100000 ++/** Master Enable */ ++#define I2C_ADDR_CFG_MnS 0x00080000 ++/* Disable ++#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_MnS_EN 0x00080000 ++/** Master Code Enable */ ++#define I2C_ADDR_CFG_MCE 0x00040000 ++/* Disable ++#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_MCE_EN 0x00040000 ++/** General Call Enable */ ++#define I2C_ADDR_CFG_GCE 0x00020000 ++/* Disable ++#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ADDR_CFG_GCE_EN 0x00020000 ++/** Ten Bit Address Mode */ ++#define I2C_ADDR_CFG_TBAM 0x00010000 ++/* 7-bit address mode enabled. ++#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */ ++/** 10-bit address mode enabled. */ ++#define I2C_ADDR_CFG_TBAM_10bit 0x00010000 ++/** I2C Bus device address ++ This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */ ++#define I2C_ADDR_CFG_ADR_MASK 0x000003FF ++/** field offset */ ++#define I2C_ADDR_CFG_ADR_OFFSET 0 ++ ++/* Fields of "I2C Bus Status Register" */ ++/** Read / not Write */ ++#define I2C_BUS_STAT_RNW 0x00000004 ++/* Write to I2C Bus. ++#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */ ++/** Read from I2C Bus. */ ++#define I2C_BUS_STAT_RNW_READ 0x00000004 ++/** Bus Status */ ++#define I2C_BUS_STAT_BS_MASK 0x00000003 ++/** field offset */ ++#define I2C_BUS_STAT_BS_OFFSET 0 ++/** I2C Bus is free. */ ++#define I2C_BUS_STAT_BS_FREE 0x00000000 ++/** A start condition has been detected on the bus (bus busy). */ ++#define I2C_BUS_STAT_BS_SC 0x00000001 ++/** The device is working as master and has claimed the control on the I2C-bus (busy master). */ ++#define I2C_BUS_STAT_BS_BM 0x00000002 ++/** A remote master has accessed this device as slave. */ ++#define I2C_BUS_STAT_BS_RM 0x00000003 ++ ++/* Fields of "I2C FIFO Configuration Register" */ ++/** TX FIFO Flow Control */ ++#define I2C_FIFO_CFG_TXFC 0x00020000 ++/* TX FIFO not as Flow Controller ++#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */ ++/** RX FIFO Flow Control */ ++#define I2C_FIFO_CFG_RXFC 0x00010000 ++/* RX FIFO not as Flow Controller ++#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */ ++/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ ++#define I2C_FIFO_CFG_TXFA_MASK 0x00003000 ++/** field offset */ ++#define I2C_FIFO_CFG_TXFA_OFFSET 12 ++/** Byte aligned (character alignment) */ ++#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000 ++/** Half word aligned (character alignment of two characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000 ++/** Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 ++/** Double word aligned (character alignment of eight */ ++#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000 ++/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ ++#define I2C_FIFO_CFG_RXFA_MASK 0x00000300 ++/** field offset */ ++#define I2C_FIFO_CFG_RXFA_OFFSET 8 ++/** Byte aligned (character alignment) */ ++#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000 ++/** Half word aligned (character alignment of two characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100 ++/** Word aligned (character alignment of four characters) */ ++#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 ++/** Double word aligned (character alignment of eight */ ++#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300 ++/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ ++#define I2C_FIFO_CFG_TXBS_MASK 0x00000030 ++/** field offset */ ++#define I2C_FIFO_CFG_TXBS_OFFSET 4 ++/** 1 word */ ++#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 ++/** 2 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010 ++/** 4 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020 ++/** 8 words */ ++#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030 ++/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ ++#define I2C_FIFO_CFG_RXBS_MASK 0x00000003 ++/** field offset */ ++#define I2C_FIFO_CFG_RXBS_OFFSET 0 ++/** 1 word */ ++#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 ++/** 2 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001 ++/** 4 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002 ++/** 8 words */ ++#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003 ++ ++/* Fields of "I2C Maximum Received Packet Size Register" */ ++/** MRPS */ ++#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_MRPS_CTRL_MRPS_OFFSET 0 ++ ++/* Fields of "I2C Received Packet Size Status Register" */ ++/** RPS */ ++#define I2C_RPS_STAT_RPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_RPS_STAT_RPS_OFFSET 0 ++ ++/* Fields of "I2C Transmit Packet Size Register" */ ++/** TPS */ ++#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF ++/** field offset */ ++#define I2C_TPS_CTRL_TPS_OFFSET 0 ++ ++/* Fields of "I2C Filled FIFO Stages Status Register" */ ++/** FFS */ ++#define I2C_FFS_STAT_FFS_MASK 0x0000000F ++/** field offset */ ++#define I2C_FFS_STAT_FFS_OFFSET 0 ++ ++/* Fields of "I2C Timing Configuration Register" */ ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000 ++/** field offset */ ++#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16 ++/** Enable Fast Mode SCL Low period timing */ ++#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000 ++/* Disable ++#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000 ++/** SCL Delay Stages for Hold Time Start (Restart) Bit. ++ The actual delay is calculated as the value of this field + 2 */ ++#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00 ++/** field offset */ ++#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9 ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0 ++/** field offset */ ++#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6 ++/** SDA Delay Stages for Start/Stop bit in High Speed Mode ++ The actual delay is calculated as the value of this field + 3 */ ++#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F ++/** field offset */ ++#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0 ++ ++/* Fields of "I2C Error Interrupt Request Source Mask Register" */ ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_TXF_OFL 0x00000008 ++/* Disable ++#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_TXF_UFL 0x00000004 ++/* Disable ++#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_RXF_OFL 0x00000002 ++/* Disable ++#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002 ++/** Enables the corresponding error interrupt. */ ++#define I2C_ERR_IRQSM_RXF_UFL 0x00000001 ++/* Disable ++#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001 ++ ++/* Fields of "I2C Error Interrupt Request Source Status Register" */ ++/** TXF_OFL */ ++#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 ++/* Nothing ++#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008 ++/** TXF_UFL */ ++#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 ++/* Nothing ++#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004 ++/** RXF_OFL */ ++#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 ++/* Nothing ++#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002 ++/** RXF_UFL */ ++#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 ++/* Nothing ++#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001 ++ ++/* Fields of "I2C Error Interrupt Request Source Clear Register" */ ++/** TXF_OFL */ ++#define I2C_ERR_IRQSC_TXF_OFL 0x00000008 ++/* No-Operation ++#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008 ++/** TXF_UFL */ ++#define I2C_ERR_IRQSC_TXF_UFL 0x00000004 ++/* No-Operation ++#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004 ++/** RXF_OFL */ ++#define I2C_ERR_IRQSC_RXF_OFL 0x00000002 ++/* No-Operation ++#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002 ++/** RXF_UFL */ ++#define I2C_ERR_IRQSC_RXF_UFL 0x00000001 ++/* No-Operation ++#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */ ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_RX 0x00000040 ++/* Disable ++#define I2C_P_IRQSM_RX_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_RX_EN 0x00000040 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_TX_END 0x00000020 ++/* Disable ++#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_TX_END_EN 0x00000020 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_NACK 0x00000010 ++/* Disable ++#define I2C_P_IRQSM_NACK_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_NACK_EN 0x00000010 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_AL 0x00000008 ++/* Disable ++#define I2C_P_IRQSM_AL_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_AL_EN 0x00000008 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_MC 0x00000004 ++/* Disable ++#define I2C_P_IRQSM_MC_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_MC_EN 0x00000004 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_GC 0x00000002 ++/* Disable ++#define I2C_P_IRQSM_GC_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_GC_EN 0x00000002 ++/** Enables the corresponding interrupt. */ ++#define I2C_P_IRQSM_AM 0x00000001 ++/* Disable ++#define I2C_P_IRQSM_AM_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_P_IRQSM_AM_EN 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ ++/** RX */ ++#define I2C_P_IRQSS_RX 0x00000040 ++/* Nothing ++#define I2C_P_IRQSS_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_RX_INTOCC 0x00000040 ++/** TX_END */ ++#define I2C_P_IRQSS_TX_END 0x00000020 ++/* Nothing ++#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020 ++/** NACK */ ++#define I2C_P_IRQSS_NACK 0x00000010 ++/* Nothing ++#define I2C_P_IRQSS_NACK_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_NACK_INTOCC 0x00000010 ++/** AL */ ++#define I2C_P_IRQSS_AL 0x00000008 ++/* Nothing ++#define I2C_P_IRQSS_AL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_AL_INTOCC 0x00000008 ++/** MC */ ++#define I2C_P_IRQSS_MC 0x00000004 ++/* Nothing ++#define I2C_P_IRQSS_MC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_MC_INTOCC 0x00000004 ++/** GC */ ++#define I2C_P_IRQSS_GC 0x00000002 ++/* Nothing ++#define I2C_P_IRQSS_GC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_GC_INTOCC 0x00000002 ++/** AM */ ++#define I2C_P_IRQSS_AM 0x00000001 ++/* Nothing ++#define I2C_P_IRQSS_AM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_P_IRQSS_AM_INTOCC 0x00000001 ++ ++/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */ ++/** RX */ ++#define I2C_P_IRQSC_RX 0x00000040 ++/* No-Operation ++#define I2C_P_IRQSC_RX_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_RX_CLR 0x00000040 ++/** TX_END */ ++#define I2C_P_IRQSC_TX_END 0x00000020 ++/* No-Operation ++#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_TX_END_CLR 0x00000020 ++/** NACK */ ++#define I2C_P_IRQSC_NACK 0x00000010 ++/* No-Operation ++#define I2C_P_IRQSC_NACK_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_NACK_CLR 0x00000010 ++/** AL */ ++#define I2C_P_IRQSC_AL 0x00000008 ++/* No-Operation ++#define I2C_P_IRQSC_AL_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_AL_CLR 0x00000008 ++/** MC */ ++#define I2C_P_IRQSC_MC 0x00000004 ++/* No-Operation ++#define I2C_P_IRQSC_MC_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_MC_CLR 0x00000004 ++/** GC */ ++#define I2C_P_IRQSC_GC 0x00000002 ++/* No-Operation ++#define I2C_P_IRQSC_GC_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_GC_CLR 0x00000002 ++/** AM */ ++#define I2C_P_IRQSC_AM 0x00000001 ++/* No-Operation ++#define I2C_P_IRQSC_AM_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_P_IRQSC_AM_CLR 0x00000001 ++ ++/* Fields of "I2C Raw Interrupt Status Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_RIS_I2C_P_INT 0x00000020 ++/* Nothing ++#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_RIS_I2C_ERR_INT 0x00000010 ++/* Nothing ++#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 ++/** BREQ_INT */ ++#define I2C_RIS_BREQ_INT 0x00000008 ++/* Nothing ++#define I2C_RIS_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_BREQ_INT_INTOCC 0x00000008 ++/** LBREQ_INT */ ++#define I2C_RIS_LBREQ_INT 0x00000004 ++/* Nothing ++#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004 ++/** SREQ_INT */ ++#define I2C_RIS_SREQ_INT 0x00000002 ++/* Nothing ++#define I2C_RIS_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_SREQ_INT_INTOCC 0x00000002 ++/** LSREQ_INT */ ++#define I2C_RIS_LSREQ_INT 0x00000001 ++/* Nothing ++#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001 ++ ++/* Fields of "I2C Interrupt Mask Control Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_IMSC_I2C_P_INT 0x00000020 ++/* Disable ++#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_I2C_P_INT_EN 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_IMSC_I2C_ERR_INT 0x00000010 ++/* Disable ++#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 ++/** BREQ_INT */ ++#define I2C_IMSC_BREQ_INT 0x00000008 ++/* Disable ++#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_BREQ_INT_EN 0x00000008 ++/** LBREQ_INT */ ++#define I2C_IMSC_LBREQ_INT 0x00000004 ++/* Disable ++#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_LBREQ_INT_EN 0x00000004 ++/** SREQ_INT */ ++#define I2C_IMSC_SREQ_INT 0x00000002 ++/* Disable ++#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_SREQ_INT_EN 0x00000002 ++/** LSREQ_INT */ ++#define I2C_IMSC_LSREQ_INT 0x00000001 ++/* Disable ++#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_IMSC_LSREQ_INT_EN 0x00000001 ++ ++/* Fields of "I2C Masked Interrupt Status Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_MIS_I2C_P_INT 0x00000020 ++/* Nothing ++#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_MIS_I2C_ERR_INT 0x00000010 ++/* Nothing ++#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010 ++/** BREQ_INT */ ++#define I2C_MIS_BREQ_INT 0x00000008 ++/* Nothing ++#define I2C_MIS_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_BREQ_INT_INTOCC 0x00000008 ++/** LBREQ_INT */ ++#define I2C_MIS_LBREQ_INT 0x00000004 ++/* Nothing ++#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004 ++/** SREQ_INT */ ++#define I2C_MIS_SREQ_INT 0x00000002 ++/* Nothing ++#define I2C_MIS_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_SREQ_INT_INTOCC 0x00000002 ++/** LSREQ_INT */ ++#define I2C_MIS_LSREQ_INT 0x00000001 ++/* Nothing ++#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001 ++ ++/* Fields of "I2C Interrupt Clear Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_ICR_I2C_P_INT 0x00000020 ++/* No-Operation ++#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_I2C_P_INT_CLR 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_ICR_I2C_ERR_INT 0x00000010 ++/* No-Operation ++#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010 ++/** BREQ_INT */ ++#define I2C_ICR_BREQ_INT 0x00000008 ++/* No-Operation ++#define I2C_ICR_BREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_BREQ_INT_CLR 0x00000008 ++/** LBREQ_INT */ ++#define I2C_ICR_LBREQ_INT 0x00000004 ++/* No-Operation ++#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_LBREQ_INT_CLR 0x00000004 ++/** SREQ_INT */ ++#define I2C_ICR_SREQ_INT 0x00000002 ++/* No-Operation ++#define I2C_ICR_SREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_SREQ_INT_CLR 0x00000002 ++/** LSREQ_INT */ ++#define I2C_ICR_LSREQ_INT 0x00000001 ++/* No-Operation ++#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */ ++/** Clear */ ++#define I2C_ICR_LSREQ_INT_CLR 0x00000001 ++ ++/* Fields of "I2C Interrupt Set Register" */ ++/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ ++#define I2C_ISR_I2C_P_INT 0x00000020 ++/* No-Operation ++#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_I2C_P_INT_SET 0x00000020 ++/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ ++#define I2C_ISR_I2C_ERR_INT 0x00000010 ++/* No-Operation ++#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_I2C_ERR_INT_SET 0x00000010 ++/** BREQ_INT */ ++#define I2C_ISR_BREQ_INT 0x00000008 ++/* No-Operation ++#define I2C_ISR_BREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_BREQ_INT_SET 0x00000008 ++/** LBREQ_INT */ ++#define I2C_ISR_LBREQ_INT 0x00000004 ++/* No-Operation ++#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_LBREQ_INT_SET 0x00000004 ++/** SREQ_INT */ ++#define I2C_ISR_SREQ_INT 0x00000002 ++/* No-Operation ++#define I2C_ISR_SREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_SREQ_INT_SET 0x00000002 ++/** LSREQ_INT */ ++#define I2C_ISR_LSREQ_INT 0x00000001 ++/* No-Operation ++#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */ ++/** Set */ ++#define I2C_ISR_LSREQ_INT_SET 0x00000001 ++ ++/* Fields of "I2C DMA Enable Register" */ ++/** BREQ_INT */ ++#define I2C_DMAE_BREQ_INT 0x00000008 ++/* Disable ++#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_BREQ_INT_EN 0x00000008 ++/** LBREQ_INT */ ++#define I2C_DMAE_LBREQ_INT 0x00000004 ++/* Disable ++#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_LBREQ_INT_EN 0x00000004 ++/** SREQ_INT */ ++#define I2C_DMAE_SREQ_INT 0x00000002 ++/* Disable ++#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_SREQ_INT_EN 0x00000002 ++/** LSREQ_INT */ ++#define I2C_DMAE_LSREQ_INT 0x00000001 ++/* Disable ++#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define I2C_DMAE_LSREQ_INT_EN 0x00000001 ++ ++/* Fields of "I2C Transmit Data Register" */ ++/** Characters to be transmitted */ ++#define I2C_TXD_TXD_MASK 0xFFFFFFFF ++/** field offset */ ++#define I2C_TXD_TXD_OFFSET 0 ++ ++/* Fields of "I2C Receive Data Register" */ ++/** Received characters */ ++#define I2C_RXD_RXD_MASK 0xFFFFFFFF ++/** field offset */ ++#define I2C_RXD_RXD_OFFSET 0 ++ ++/*! @} */ /* I2C_REGISTER */ ++ ++#endif /* _i2c_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h +@@ -0,0 +1,4324 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _icu0_reg_h ++#define _icu0_reg_h ++ ++/** \addtogroup ICU0_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define icu0_r32(reg) reg_r32(&icu0->reg) ++#define icu0_w32(val, reg) reg_w32(val, &icu0->reg) ++#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg) ++#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx) ++#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx) ++#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx) ++#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx) ++ ++ ++/** ICU0 register structure */ ++struct gpon_reg_icu0 ++{ ++ /** IM0 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im0_isr; /* 0x00000000 */ ++ /** Reserved */ ++ unsigned int res_0; /* 0x00000004 */ ++ /** IM0 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im0_ier; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_1; /* 0x0000000C */ ++ /** IM0 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */ ++ unsigned int im0_iosr; /* 0x00000010 */ ++ /** Reserved */ ++ unsigned int res_2; /* 0x00000014 */ ++ /** IM0 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im0_irsr; /* 0x00000018 */ ++ /** Reserved */ ++ unsigned int res_3; /* 0x0000001C */ ++ /** IM0 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im0_imr; /* 0x00000020 */ ++ /** Reserved */ ++ unsigned int res_4; /* 0x00000024 */ ++ /** IM1 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im1_isr; /* 0x00000028 */ ++ /** Reserved */ ++ unsigned int res_5; /* 0x0000002C */ ++ /** IM1 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im1_ier; /* 0x00000030 */ ++ /** Reserved */ ++ unsigned int res_6; /* 0x00000034 */ ++ /** IM1 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */ ++ unsigned int im1_iosr; /* 0x00000038 */ ++ /** Reserved */ ++ unsigned int res_7; /* 0x0000003C */ ++ /** IM1 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im1_irsr; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_8; /* 0x00000044 */ ++ /** IM1 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im1_imr; /* 0x00000048 */ ++ /** Reserved */ ++ unsigned int res_9; /* 0x0000004C */ ++ /** IM2 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im2_isr; /* 0x00000050 */ ++ /** Reserved */ ++ unsigned int res_10; /* 0x00000054 */ ++ /** IM2 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im2_ier; /* 0x00000058 */ ++ /** Reserved */ ++ unsigned int res_11; /* 0x0000005C */ ++ /** IM2 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */ ++ unsigned int im2_iosr; /* 0x00000060 */ ++ /** Reserved */ ++ unsigned int res_12; /* 0x00000064 */ ++ /** IM2 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im2_irsr; /* 0x00000068 */ ++ /** Reserved */ ++ unsigned int res_13; /* 0x0000006C */ ++ /** IM2 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im2_imr; /* 0x00000070 */ ++ /** Reserved */ ++ unsigned int res_14; /* 0x00000074 */ ++ /** IM3 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im3_isr; /* 0x00000078 */ ++ /** Reserved */ ++ unsigned int res_15; /* 0x0000007C */ ++ /** IM3 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im3_ier; /* 0x00000080 */ ++ /** Reserved */ ++ unsigned int res_16; /* 0x00000084 */ ++ /** IM3 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */ ++ unsigned int im3_iosr; /* 0x00000088 */ ++ /** Reserved */ ++ unsigned int res_17; /* 0x0000008C */ ++ /** IM3 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im3_irsr; /* 0x00000090 */ ++ /** Reserved */ ++ unsigned int res_18; /* 0x00000094 */ ++ /** IM3 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im3_imr; /* 0x00000098 */ ++ /** Reserved */ ++ unsigned int res_19; /* 0x0000009C */ ++ /** IM4 Interrupt Status Register ++ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ ++ unsigned int im4_isr; /* 0x000000A0 */ ++ /** Reserved */ ++ unsigned int res_20; /* 0x000000A4 */ ++ /** IM4 Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int im4_ier; /* 0x000000A8 */ ++ /** Reserved */ ++ unsigned int res_21; /* 0x000000AC */ ++ /** IM4 Interrupt Output Status Register ++ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */ ++ unsigned int im4_iosr; /* 0x000000B0 */ ++ /** Reserved */ ++ unsigned int res_22; /* 0x000000B4 */ ++ /** IM4 Interrupt Request Set Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int im4_irsr; /* 0x000000B8 */ ++ /** Reserved */ ++ unsigned int res_23; /* 0x000000BC */ ++ /** IM4 Interrupt Mode Register ++ This register shows the type of interrupt for each bit. */ ++ unsigned int im4_imr; /* 0x000000C0 */ ++ /** Reserved */ ++ unsigned int res_24; /* 0x000000C4 */ ++ /** ICU Interrupt Vector Register (5 bit variant) ++ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ ++ unsigned int icu_ivec; /* 0x000000C8 */ ++ /** Reserved */ ++ unsigned int res_25; /* 0x000000CC */ ++ /** ICU Interrupt Vector Register (6 bit variant) ++ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ ++ unsigned int icu_ivec_6; /* 0x000000D0 */ ++ /** Reserved */ ++ unsigned int res_26[3]; /* 0x000000D4 */ ++}; ++ ++ ++/* Fields of "IM0 Interrupt Status Register" */ ++/** PCM Transmit Crash Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000 ++/** PCM Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_TX 0x40000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000 ++/** PCM Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_PCM_RX 0x20000000 ++/* Nothing ++#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SHA1_HASH 0x10000000 ++/* Nothing ++#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_AES_AES 0x08000000 ++/* Nothing ++#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000 ++/** SSC Frame Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_F 0x00020000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000 ++/** SSC Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_E 0x00010000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000 ++/** SSC Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_R 0x00008000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000 ++/** SSC Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM0_ISR_SSC0_T 0x00004000 ++/* Nothing ++#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000 ++/** I2C Peripheral Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000 ++/** I2C Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000 ++/** I2C Burst Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400 ++/** I2C Single Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200 ++/** I2C Last Single Data Transfer Request ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100 ++/* Nothing ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002 ++/** HOST IF Event Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM0_ISR_HOST_EIR 0x00000001 ++/* Nothing ++#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001 ++ ++/* Fields of "IM0 Interrupt Enable Register" */ ++/** PCM Transmit Crash Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000 ++/** PCM Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_TX 0x40000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_TX_EN 0x40000000 ++/** PCM Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_PCM_RX 0x20000000 ++/* Disable ++#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_PCM_RX_EN 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SHA1_HASH 0x10000000 ++/* Disable ++#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_AES_AES 0x08000000 ++/* Disable ++#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_AES_AES_EN 0x08000000 ++/** SSC Frame Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_F 0x00020000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_F_EN 0x00020000 ++/** SSC Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_E 0x00010000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_E_EN 0x00010000 ++/** SSC Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_R 0x00008000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_R_EN 0x00008000 ++/** SSC Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_SSC0_T 0x00004000 ++/* Disable ++#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_SSC0_T_EN 0x00004000 ++/** I2C Peripheral Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000 ++/* Disable ++#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000 ++/** I2C Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000 ++/* Disable ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000 ++/** I2C Burst Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800 ++/* Disable ++#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400 ++/* Disable ++#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400 ++/** I2C Single Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200 ++/* Disable ++#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100 ++/* Disable ++#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002 ++/* Disable ++#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002 ++/** HOST IF Event Interrupt ++ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IER_HOST_EIR 0x00000001 ++/* Disable ++#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001 ++ ++/* Fields of "IM0 Interrupt Output Status Register" */ ++/** PCM Transmit Crash Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000 ++/** PCM Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_TX 0x40000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000 ++/** PCM Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_PCM_RX 0x20000000 ++/* Nothing ++#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000 ++/* Nothing ++#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_AES_AES 0x08000000 ++/* Nothing ++#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000 ++/** SSC Frame Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_F 0x00020000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000 ++/** SSC Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_E 0x00010000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000 ++/** SSC Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_R 0x00008000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000 ++/** SSC Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_SSC0_T 0x00004000 ++/* Nothing ++#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000 ++/** I2C Peripheral Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000 ++/** I2C Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000 ++/** I2C Burst Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400 ++/** I2C Single Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100 ++/* Nothing ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002 ++/** HOST IF Event Interrupt ++ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IOSR_HOST_EIR 0x00000001 ++/* Nothing ++#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001 ++ ++/* Fields of "IM0 Interrupt Request Set Register" */ ++/** PCM Transmit Crash Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000 ++/** PCM Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_TX 0x40000000 ++/** PCM Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_PCM_RX 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_AES_AES 0x08000000 ++/** SSC Frame Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_F 0x00020000 ++/** SSC Error Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_E 0x00010000 ++/** SSC Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_R 0x00008000 ++/** SSC Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_SSC0_T 0x00004000 ++/** I2C Peripheral Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000 ++/** I2C Error Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000 ++/** I2C Burst Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400 ++/** I2C Single Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002 ++/** HOST IF Event Interrupt ++ Software control for the corresponding bit in the IM0_ISR register. */ ++#define ICU0_IM0_IRSR_HOST_EIR 0x00000001 ++ ++/* Fields of "IM0 Interrupt Mode Register" */ ++/** PCM Transmit Crash Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000 ++/** PCM Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_TX 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000 ++/** PCM Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_PCM_RX 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000 ++/** Secure Hash Algorithm Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SHA1_HASH 0x10000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000 ++/** Advanced Encryption Standard Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_AES_AES 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000 ++/** SSC Frame Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_F 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000 ++/** SSC Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_E 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000 ++/** SSC Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_R 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000 ++/** SSC Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_SSC0_T 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000 ++/** I2C Peripheral Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000 ++/** I2C Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000 ++/** I2C Burst Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800 ++/** I2C Last Burst Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400 ++/** I2C Single Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200 ++/** I2C Last Single Data Transfer Request ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100 ++/** HOST IF Mailbox1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010 ++/** HOST IF Mailbox1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008 ++/** HOST IF Mailbox0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004 ++/** HOST IF Mailbox0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002 ++/** HOST IF Event Interrupt ++ Type of interrupt. */ ++#define ICU0_IM0_IMR_HOST_EIR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001 ++ ++/* Fields of "IM1 Interrupt Status Register" */ ++/** Crossbar Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000 ++/* Nothing ++#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000 ++/** DDR Controller Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_DDR 0x40000000 ++/* Nothing ++#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_DDR_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_BCU0 0x20000000 ++/* Nothing ++#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000 ++/** SBIU interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SBIU0 0x08000000 ++/* Nothing ++#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000 ++/** Watchdog Prewarning Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_WDT_PIR 0x02000000 ++/* Nothing ++#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000 ++/** Watchdog Access Error Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_WDT_AEIR 0x01000000 ++/* Nothing ++#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000 ++/** SYS GPE Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SYS_GPE 0x00200000 ++/* Nothing ++#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000 ++/** SYS1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_SYS1 0x00100000 ++/* Nothing ++#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_RX 0x00020000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_TX 0x00010000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_PMA_200M 0x00008000 ++/* Nothing ++#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000 ++/** Time of Day ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_TOD 0x00004000 ++/* Nothing ++#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_TOD_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSC_ROOT 0x00002000 ++/* Nothing ++#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000 ++/** FSC Timer Interrupt 1 ++ Delayed version of FSCROOT. This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000 ++/* Nothing ++#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000 ++/** FSC Timer Interrupt 0 ++ Delayed version of FSCROOT. This bit is a direct interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800 ++/* Nothing ++#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_FSC_BKP 0x00000400 ++/* Nothing ++#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400 ++/** External Interrupt from GPIO P4 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P4 0x00000100 ++/* Nothing ++#define ICU0_IM1_ISR_P4_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P4_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P4_INTOCC 0x00000100 ++/** External Interrupt from GPIO P3 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P3 0x00000080 ++/* Nothing ++#define ICU0_IM1_ISR_P3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P3_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P3_INTOCC 0x00000080 ++/** External Interrupt from GPIO P2 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P2 0x00000040 ++/* Nothing ++#define ICU0_IM1_ISR_P2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P2_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P2_INTOCC 0x00000040 ++/** External Interrupt from GPIO P1 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P1 0x00000020 ++/* Nothing ++#define ICU0_IM1_ISR_P1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P1_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P1_INTOCC 0x00000020 ++/** External Interrupt from GPIO P0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_P0 0x00000010 ++/* Nothing ++#define ICU0_IM1_ISR_P0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_P0_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_P0_INTOCC 0x00000010 ++/** EBU Serial Flash Busy ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002 ++/** EBU Serial Flash Command Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001 ++/* Nothing ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001 ++ ++/* Fields of "IM1 Interrupt Enable Register" */ ++/** Crossbar Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_XBAR_ERROR 0x80000000 ++/* Disable ++#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000 ++/** DDR Controller Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_DDR 0x40000000 ++/* Disable ++#define ICU0_IM1_IER_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_DDR_EN 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_BCU0 0x20000000 ++/* Disable ++#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_BCU0_EN 0x20000000 ++/** SBIU interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SBIU0 0x08000000 ++/* Disable ++#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SBIU0_EN 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_WDT_PIR 0x02000000 ++/* Disable ++#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000 ++/** Watchdog Access Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_WDT_AEIR 0x01000000 ++/* Disable ++#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000 ++/** SYS GPE Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SYS_GPE 0x00200000 ++/* Disable ++#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000 ++/** SYS1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_SYS1 0x00100000 ++/* Disable ++#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_SYS1_EN 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_RX 0x00020000 ++/* Disable ++#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_RX_EN 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_TX 0x00010000 ++/* Disable ++#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_TX_EN 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_PMA_200M 0x00008000 ++/* Disable ++#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_PMA_200M_EN 0x00008000 ++/** Time of Day ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_TOD 0x00004000 ++/* Disable ++#define ICU0_IM1_IER_TOD_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_TOD_EN 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSC_ROOT 0x00002000 ++/* Disable ++#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000 ++/** FSC Timer Interrupt 1 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSCT_CMP1 0x00001000 ++/* Disable ++#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000 ++/** FSC Timer Interrupt 0 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSCT_CMP0 0x00000800 ++/* Disable ++#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_FSC_BKP 0x00000400 ++/* Disable ++#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400 ++/** External Interrupt from GPIO P4 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P4 0x00000100 ++/* Disable ++#define ICU0_IM1_IER_P4_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P4_EN 0x00000100 ++/** External Interrupt from GPIO P3 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P3 0x00000080 ++/* Disable ++#define ICU0_IM1_IER_P3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P3_EN 0x00000080 ++/** External Interrupt from GPIO P2 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P2 0x00000040 ++/* Disable ++#define ICU0_IM1_IER_P2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P2_EN 0x00000040 ++/** External Interrupt from GPIO P1 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P1 0x00000020 ++/* Disable ++#define ICU0_IM1_IER_P1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P1_EN 0x00000020 ++/** External Interrupt from GPIO P0 ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_P0 0x00000010 ++/* Disable ++#define ICU0_IM1_IER_P0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_P0_EN 0x00000010 ++/** EBU Serial Flash Busy ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002 ++/** EBU Serial Flash Command Error ++ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001 ++/* Disable ++#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001 ++ ++/* Fields of "IM1 Interrupt Output Status Register" */ ++/** Crossbar Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000 ++/* Nothing ++#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000 ++/** DDR Controller Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_DDR 0x40000000 ++/* Nothing ++#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_BCU0 0x20000000 ++/* Nothing ++#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000 ++/** SBIU interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SBIU0 0x08000000 ++/* Nothing ++#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_WDT_PIR 0x02000000 ++/* Nothing ++#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000 ++/** Watchdog Access Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000 ++/* Nothing ++#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000 ++/** SYS GPE Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SYS_GPE 0x00200000 ++/* Nothing ++#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000 ++/** SYS1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_SYS1 0x00100000 ++/* Nothing ++#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_RX 0x00020000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_TX 0x00010000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_PMA_200M 0x00008000 ++/* Nothing ++#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000 ++/** Time of Day ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_TOD 0x00004000 ++/* Nothing ++#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000 ++/* Nothing ++#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000 ++/** FSC Timer Interrupt 1 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000 ++/* Nothing ++#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000 ++/** FSC Timer Interrupt 0 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800 ++/* Nothing ++#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_FSC_BKP 0x00000400 ++/* Nothing ++#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400 ++/** External Interrupt from GPIO P4 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P4 0x00000100 ++/* Nothing ++#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100 ++/** External Interrupt from GPIO P3 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P3 0x00000080 ++/* Nothing ++#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080 ++/** External Interrupt from GPIO P2 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P2 0x00000040 ++/* Nothing ++#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040 ++/** External Interrupt from GPIO P1 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P1 0x00000020 ++/* Nothing ++#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020 ++/** External Interrupt from GPIO P0 ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_P0 0x00000010 ++/* Nothing ++#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010 ++/** EBU Serial Flash Busy ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002 ++/** EBU Serial Flash Command Error ++ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001 ++/* Nothing ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001 ++ ++/* Fields of "IM1 Interrupt Request Set Register" */ ++/** Crossbar Error Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000 ++/** DDR Controller Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_DDR 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_BCU0 0x20000000 ++/** SBIU interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SBIU0 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_WDT_PIR 0x02000000 ++/** Watchdog Access Error Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000 ++/** SYS GPE Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SYS_GPE 0x00200000 ++/** SYS1 Interrupt ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_SYS1 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_RX 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_TX 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_PMA_200M 0x00008000 ++/** Time of Day ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_TOD 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000 ++/** FSC Timer Interrupt 1 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000 ++/** FSC Timer Interrupt 0 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_FSC_BKP 0x00000400 ++/** External Interrupt from GPIO P4 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P4 0x00000100 ++/** External Interrupt from GPIO P3 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P3 0x00000080 ++/** External Interrupt from GPIO P2 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P2 0x00000040 ++/** External Interrupt from GPIO P1 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P1 0x00000020 ++/** External Interrupt from GPIO P0 ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_P0 0x00000010 ++/** EBU Serial Flash Busy ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002 ++/** EBU Serial Flash Command Error ++ Software control for the corresponding bit in the IM1_ISR register. */ ++#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001 ++ ++/* Fields of "IM1 Interrupt Mode Register" */ ++/** Crossbar Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000 ++/** DDR Controller Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_DDR 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_DDR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_DDR_DIR 0x40000000 ++/** FPI Bus Control Unit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_BCU0 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_BCU0_DIR 0x20000000 ++/** SBIU interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SBIU0 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000 ++/** Watchdog Prewarning Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_WDT_PIR 0x02000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000 ++/** Watchdog Access Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_WDT_AEIR 0x01000000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000 ++/** SYS GPE Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SYS_GPE 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000 ++/** SYS1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_SYS1 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_SYS1_DIR 0x00100000 ++/** PMA Interrupt from IntNode of the RX Clk Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_RX 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000 ++/** PMA Interrupt from IntNode of the TX Clk Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_TX 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000 ++/** PMA Interrupt from IntNode of the 200MHz Domain ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_PMA_200M 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000 ++/** Time of Day ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_TOD 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_TOD_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_TOD_DIR 0x00004000 ++/** 8kHz root interrupt derived from GPON interface ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSC_ROOT 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000 ++/** FSC Timer Interrupt 1 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000 ++/** FSC Timer Interrupt 0 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800 ++/** 8kHz backup interrupt derived from core-PLL ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_FSC_BKP 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400 ++/** External Interrupt from GPIO P4 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P4 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P4_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P4_DIR 0x00000100 ++/** External Interrupt from GPIO P3 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P3 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P3_DIR 0x00000080 ++/** External Interrupt from GPIO P2 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P2 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P2_DIR 0x00000040 ++/** External Interrupt from GPIO P1 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P1 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P1_DIR 0x00000020 ++/** External Interrupt from GPIO P0 ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_P0 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_P0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_P0_DIR 0x00000010 ++/** EBU Serial Flash Busy ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004 ++/** EBU Serial Flash Command Overwrite Error ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002 ++/** EBU Serial Flash Command Error ++ Type of interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001 ++ ++/* Fields of "IM2 Interrupt Status Register" */ ++/** EIM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_EIM 0x80000000 ++/* Nothing ++#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_EIM_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000 ++/** GTC Upstream Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_GTC_US 0x40000000 ++/* Nothing ++#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000 ++/** GTC Downstream Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_GTC_DS 0x20000000 ++/* Nothing ++#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000 ++/** TBM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_TBM 0x00400000 ++/* Nothing ++#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_TBM_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000 ++/** Dispatcher Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_DISP 0x00200000 ++/* Nothing ++#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_DISP_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000 ++/** CONFIG Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_CONFIG 0x00100000 ++/* Nothing ++#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000 ++/** CONFIG Break Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000 ++/* Nothing ++#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000 ++/** OCTRLC Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLC 0x00040000 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000 ++/** ICTRLC 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC1 0x00020000 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000 ++/** ICTRLC 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC0 0x00010000 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000 ++/** LINK 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_LINK1 0x00004000 ++/* Nothing ++#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000 ++/** TMU Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_TMU 0x00001000 ++/* Nothing ++#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_TMU_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000 ++/** FSQM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_FSQM 0x00000800 ++/* Nothing ++#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800 ++/** IQM Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_IQM 0x00000400 ++/* Nothing ++#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_IQM_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400 ++/** OCTRLG Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLG 0x00000200 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200 ++/** OCTRLL 3 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL3 0x00000080 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080 ++/** OCTRLL 2 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL2 0x00000040 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040 ++/** OCTRLL 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL1 0x00000020 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020 ++/** OCTRLL 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL0 0x00000010 ++/* Nothing ++#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010 ++/** ICTRLL 3 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL3 0x00000008 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008 ++/** ICTRLL 2 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL2 0x00000004 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004 ++/** ICTRLL 1 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL1 0x00000002 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002 ++/** ICTRLL 0 Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL0 0x00000001 ++/* Nothing ++#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001 ++ ++/* Fields of "IM2 Interrupt Enable Register" */ ++/** EIM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_EIM 0x80000000 ++/* Disable ++#define ICU0_IM2_IER_EIM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_EIM_EN 0x80000000 ++/** GTC Upstream Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_GTC_US 0x40000000 ++/* Disable ++#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_GTC_US_EN 0x40000000 ++/** GTC Downstream Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_GTC_DS 0x20000000 ++/* Disable ++#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_GTC_DS_EN 0x20000000 ++/** TBM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_TBM 0x00400000 ++/* Disable ++#define ICU0_IM2_IER_TBM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_TBM_EN 0x00400000 ++/** Dispatcher Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_DISP 0x00200000 ++/* Disable ++#define ICU0_IM2_IER_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_DISP_EN 0x00200000 ++/** CONFIG Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_CONFIG 0x00100000 ++/* Disable ++#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_CONFIG_EN 0x00100000 ++/** CONFIG Break Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000 ++/* Disable ++#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000 ++/** OCTRLC Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLC 0x00040000 ++/* Disable ++#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLC_EN 0x00040000 ++/** ICTRLC 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLC1 0x00020000 ++/* Disable ++#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000 ++/** ICTRLC 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLC0 0x00010000 ++/* Disable ++#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000 ++/** LINK 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_LINK1 0x00004000 ++/* Disable ++#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_LINK1_EN 0x00004000 ++/** TMU Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_TMU 0x00001000 ++/* Disable ++#define ICU0_IM2_IER_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_TMU_EN 0x00001000 ++/** FSQM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_FSQM 0x00000800 ++/* Disable ++#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_FSQM_EN 0x00000800 ++/** IQM Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_IQM 0x00000400 ++/* Disable ++#define ICU0_IM2_IER_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_IQM_EN 0x00000400 ++/** OCTRLG Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLG 0x00000200 ++/* Disable ++#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLG_EN 0x00000200 ++/** OCTRLL 3 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL3 0x00000080 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080 ++/** OCTRLL 2 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL2 0x00000040 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040 ++/** OCTRLL 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL1 0x00000020 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020 ++/** OCTRLL 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_OCTRLL0 0x00000010 ++/* Disable ++#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010 ++/** ICTRLL 3 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL3 0x00000008 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008 ++/** ICTRLL 2 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL2 0x00000004 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004 ++/** ICTRLL 1 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL1 0x00000002 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002 ++/** ICTRLL 0 Interrupt ++ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IER_ICTRLL0 0x00000001 ++/* Disable ++#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001 ++ ++/* Fields of "IM2 Interrupt Output Status Register" */ ++/** EIM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_EIM 0x80000000 ++/* Nothing ++#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000 ++/** GTC Upstream Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_GTC_US 0x40000000 ++/* Nothing ++#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000 ++/** GTC Downstream Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_GTC_DS 0x20000000 ++/* Nothing ++#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000 ++/** TBM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_TBM 0x00400000 ++/* Nothing ++#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000 ++/** Dispatcher Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_DISP 0x00200000 ++/* Nothing ++#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000 ++/** CONFIG Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_CONFIG 0x00100000 ++/* Nothing ++#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000 ++/** CONFIG Break Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000 ++/* Nothing ++#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000 ++/** OCTRLC Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLC 0x00040000 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000 ++/** ICTRLC 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLC1 0x00020000 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000 ++/** ICTRLC 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLC0 0x00010000 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000 ++/** LINK 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_LINK1 0x00004000 ++/* Nothing ++#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000 ++/** TMU Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_TMU 0x00001000 ++/* Nothing ++#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000 ++/** FSQM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_FSQM 0x00000800 ++/* Nothing ++#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800 ++/** IQM Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_IQM 0x00000400 ++/* Nothing ++#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400 ++/** OCTRLG Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLG 0x00000200 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200 ++/** OCTRLL 3 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL3 0x00000080 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080 ++/** OCTRLL 2 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL2 0x00000040 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040 ++/** OCTRLL 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL1 0x00000020 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020 ++/** OCTRLL 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_OCTRLL0 0x00000010 ++/* Nothing ++#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010 ++/** ICTRLL 3 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL3 0x00000008 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008 ++/** ICTRLL 2 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL2 0x00000004 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004 ++/** ICTRLL 1 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL1 0x00000002 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002 ++/** ICTRLL 0 Interrupt ++ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IOSR_ICTRLL0 0x00000001 ++/* Nothing ++#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001 ++ ++/* Fields of "IM2 Interrupt Request Set Register" */ ++/** EIM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_EIM 0x80000000 ++/** GTC Upstream Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_GTC_US 0x40000000 ++/** GTC Downstream Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_GTC_DS 0x20000000 ++/** TBM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_TBM 0x00400000 ++/** Dispatcher Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_DISP 0x00200000 ++/** CONFIG Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_CONFIG 0x00100000 ++/** CONFIG Break Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000 ++/** OCTRLC Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLC 0x00040000 ++/** ICTRLC 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLC1 0x00020000 ++/** ICTRLC 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLC0 0x00010000 ++/** LINK 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_LINK1 0x00004000 ++/** TMU Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_TMU 0x00001000 ++/** FSQM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_FSQM 0x00000800 ++/** IQM Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_IQM 0x00000400 ++/** OCTRLG Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLG 0x00000200 ++/** OCTRLL 3 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL3 0x00000080 ++/** OCTRLL 2 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL2 0x00000040 ++/** OCTRLL 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL1 0x00000020 ++/** OCTRLL 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_OCTRLL0 0x00000010 ++/** ICTRLL 3 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL3 0x00000008 ++/** ICTRLL 2 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL2 0x00000004 ++/** ICTRLL 1 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL1 0x00000002 ++/** ICTRLL 0 Interrupt ++ Software control for the corresponding bit in the IM2_ISR register. */ ++#define ICU0_IM2_IRSR_ICTRLL0 0x00000001 ++ ++/* Fields of "IM2 Interrupt Mode Register" */ ++/** EIM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_EIM 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_EIM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_EIM_DIR 0x80000000 ++/** GTC Upstream Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_GTC_US 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000 ++/** GTC Downstream Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_GTC_DS 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000 ++/** TBM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_TBM 0x00400000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_TBM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_TBM_DIR 0x00400000 ++/** Dispatcher Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_DISP 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_DISP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_DISP_DIR 0x00200000 ++/** CONFIG Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_CONFIG 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000 ++/** CONFIG Break Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000 ++/** OCTRLC Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLC 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000 ++/** ICTRLC 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC1 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000 ++/** ICTRLC 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC0 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000 ++/** LINK 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_LINK1 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_LINK1_DIR 0x00004000 ++/** TMU Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_TMU 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_TMU_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_TMU_DIR 0x00001000 ++/** FSQM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_FSQM 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_FSQM_DIR 0x00000800 ++/** IQM Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_IQM 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_IQM_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_IQM_DIR 0x00000400 ++/** OCTRLG Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLG 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200 ++/** OCTRLL 3 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL3 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080 ++/** OCTRLL 2 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL2 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040 ++/** OCTRLL 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL1 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020 ++/** OCTRLL 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL0 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010 ++/** ICTRLL 3 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL3 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008 ++/** ICTRLL 2 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL2 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004 ++/** ICTRLL 1 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL1 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002 ++/** ICTRLL 0 Interrupt ++ Type of interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL0 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001 ++ ++/* Fields of "IM3 Interrupt Status Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000 ++/* Nothing ++#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000 ++/* Nothing ++#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_SFC 0x00008000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_MS 0x00004000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABST 0x00001000 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_TB 0x00000800 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800 ++/** ASC1 Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_E 0x00000400 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400 ++/** ASC1 Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_R 0x00000200 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200 ++/** ASC1 Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC1_T 0x00000100 ++/* Nothing ++#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_SFC 0x00000080 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_MS 0x00000040 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABST 0x00000010 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_TB 0x00000008 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008 ++/** ASC0 Error Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_E 0x00000004 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004 ++/** ASC0 Receive Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_R 0x00000002 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002 ++/** ASC0 Transmit Interrupt ++ This bit is a direct interrupt. */ ++#define ICU0_IM3_ISR_ASC0_T 0x00000001 ++/* Nothing ++#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001 ++ ++/* Fields of "IM3 Interrupt Enable Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1GP 0x80000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1RX 0x40000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_1TX 0x20000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2GP 0x10000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2RX 0x08000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_DFEV0_2TX 0x04000000 ++/* Disable ++#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC3B 0x00200000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC3A 0x00100000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC2B 0x00080000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC2A 0x00040000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC1B 0x00020000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_GPTC_TC1A 0x00010000 ++/* Disable ++#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_SFC 0x00008000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_MS 0x00004000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_ABDET 0x00002000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_ABST 0x00001000 ++/* Disable ++#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_TB 0x00000800 ++/* Disable ++#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800 ++/** ASC1 Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_E 0x00000400 ++/* Disable ++#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_E_EN 0x00000400 ++/** ASC1 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_R 0x00000200 ++/* Disable ++#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_R_EN 0x00000200 ++/** ASC1 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC1_T 0x00000100 ++/* Disable ++#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC1_T_EN 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_SFC 0x00000080 ++/* Disable ++#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_MS 0x00000040 ++/* Disable ++#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_ABDET 0x00000020 ++/* Disable ++#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_ABST 0x00000010 ++/* Disable ++#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_TB 0x00000008 ++/* Disable ++#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008 ++/** ASC0 Error Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_E 0x00000004 ++/* Disable ++#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_E_EN 0x00000004 ++/** ASC0 Receive Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_R 0x00000002 ++/* Disable ++#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_R_EN 0x00000002 ++/** ASC0 Transmit Interrupt ++ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IER_ASC0_T 0x00000001 ++/* Disable ++#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM3_IER_ASC0_T_EN 0x00000001 ++ ++/* Fields of "IM3 Interrupt Output Status Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000 ++/* Nothing ++#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000 ++/* Nothing ++#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_MS 0x00004000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_TB 0x00000800 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800 ++/** ASC1 Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_E 0x00000400 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400 ++/** ASC1 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_R 0x00000200 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200 ++/** ASC1 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC1_T 0x00000100 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_MS 0x00000040 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_TB 0x00000008 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008 ++/** ASC0 Error Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_E 0x00000004 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004 ++/** ASC0 Receive Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_R 0x00000002 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002 ++/** ASC0 Transmit Interrupt ++ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IOSR_ASC0_T 0x00000001 ++/* Nothing ++#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001 ++ ++/* Fields of "IM3 Interrupt Request Set Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_MS 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_TB 0x00000800 ++/** ASC1 Error Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_E 0x00000400 ++/** ASC1 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_R 0x00000200 ++/** ASC1 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC1_T 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_MS 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_TB 0x00000008 ++/** ASC0 Error Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_E 0x00000004 ++/** ASC0 Receive Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_R 0x00000002 ++/** ASC0 Transmit Interrupt ++ Software control for the corresponding bit in the IM3_ISR register. */ ++#define ICU0_IM3_IRSR_ASC0_T 0x00000001 ++ ++/* Fields of "IM3 Interrupt Mode Register" */ ++/** DFEV0, Channel 0 General Purpose Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000 ++/** DFEV0, Channel 0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000 ++/** DFEV0, Channel 0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000 ++/** DFEV0, Channel 1 General Purpose Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000 ++/** DFEV0, Channel 1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000 ++/** DFEV0, Channel 1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000 ++/** GPTC Timer/Counter 3B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000 ++/** GPTC Timer/Counter 3A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000 ++/** GPTC Timer/Counter 2B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000 ++/** GPTC Timer/Counter 2A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000 ++/** GPTC Timer/Counter 1B Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000 ++/** GPTC Timer/Counter 1A Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000 ++/** ASC1 Soft Flow Control Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_SFC 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000 ++/** ASC1 Modem Status Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_MS 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000 ++/** ASC1 Autobaud Detection Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000 ++/** ASC1 Autobaud Start Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABST 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000 ++/** ASC1 Transmit Buffer Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_TB 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800 ++/** ASC1 Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_E 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400 ++/** ASC1 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_R 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200 ++/** ASC1 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC1_T 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100 ++/** ASC0 Soft Flow Control Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_SFC 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080 ++/** ASC1 Modem Status Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_MS 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040 ++/** ASC0 Autobaud Detection Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020 ++/** ASC0 Autobaud Start Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABST 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010 ++/** ASC0 Transmit Buffer Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_TB 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008 ++/** ASC0 Error Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_E 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004 ++/** ASC0 Receive Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_R 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002 ++/** ASC0 Transmit Interrupt ++ Type of interrupt. */ ++#define ICU0_IM3_IMR_ASC0_T 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001 ++ ++/* Fields of "IM4 Interrupt Status Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_ERL 0x40000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_VPE0_EXL 0x20000000 ++/* Nothing ++#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR8 0x00400000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR7 0x00200000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR6 0x00100000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR5 0x00080000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR4 0x00040000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR3 0x00020000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR2 0x00010000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR1 0x00008000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR0 0x00004000 ++/* Nothing ++#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000 ++/** TMU Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_TMU_ERR 0x00001000 ++/* Nothing ++#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000 ++/** FSQM Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_FSQM_ERR 0x00000800 ++/* Nothing ++#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800 ++/** IQM Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_IQM_ERR 0x00000400 ++/* Nothing ++#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400 ++/** OCTRLG Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200 ++/** ICTRLG Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100 ++/** OCTRLL 3 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080 ++/** OCTRLL 2 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040 ++/** OCTRLL 1 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020 ++/** OCTRLL 0 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010 ++/* Nothing ++#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010 ++/** ICTRLL 3 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008 ++/** ICTRLL 2 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004 ++/** ICTRLL 1 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002 ++/** ICTRLL 0 Error ++ This bit is an indirect interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001 ++/* Nothing ++#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001 ++ ++/* Fields of "IM4 Interrupt Enable Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_ERL 0x40000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_VPE0_EXL 0x20000000 ++/* Disable ++#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR8 0x00400000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR7 0x00200000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR6 0x00100000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR5 0x00080000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR4 0x00040000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR3 0x00020000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR2 0x00010000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR1 0x00008000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_MPS_IR0 0x00004000 ++/* Disable ++#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000 ++/** TMU Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_TMU_ERR 0x00001000 ++/* Disable ++#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000 ++/** FSQM Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_FSQM_ERR 0x00000800 ++/* Disable ++#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800 ++/** IQM Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_IQM_ERR 0x00000400 ++/* Disable ++#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400 ++/** OCTRLG Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200 ++/* Disable ++#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200 ++/** ICTRLG Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100 ++/* Disable ++#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100 ++/** OCTRLL 3 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080 ++/** OCTRLL 2 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040 ++/** OCTRLL 1 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020 ++/** OCTRLL 0 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010 ++/* Disable ++#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010 ++/** ICTRLL 3 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008 ++/** ICTRLL 2 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004 ++/** ICTRLL 1 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002 ++/** ICTRLL 0 Error ++ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001 ++/* Disable ++#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */ ++/** Enable */ ++#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001 ++ ++/* Fields of "IM4 Interrupt Output Status Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000 ++/* Nothing ++#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR8 0x00400000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR7 0x00200000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR6 0x00100000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR5 0x00080000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR4 0x00040000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR3 0x00020000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR2 0x00010000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR1 0x00008000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_MPS_IR0 0x00004000 ++/* Nothing ++#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000 ++/** TMU Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_TMU_ERR 0x00001000 ++/* Nothing ++#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000 ++/** FSQM Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800 ++/* Nothing ++#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800 ++/** IQM Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_IQM_ERR 0x00000400 ++/* Nothing ++#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400 ++/** OCTRLG Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200 ++/** ICTRLG Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100 ++/** OCTRLL 3 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080 ++/** OCTRLL 2 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040 ++/** OCTRLL 1 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020 ++/** OCTRLL 0 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010 ++/* Nothing ++#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010 ++/** ICTRLL 3 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008 ++/** ICTRLL 2 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004 ++/** ICTRLL 1 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002 ++/** ICTRLL 0 Error ++ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001 ++/* Nothing ++#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */ ++/** Read: Interrupt occurred. */ ++#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001 ++ ++/* Fields of "IM4 Interrupt Request Set Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR8 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR7 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR6 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR5 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR4 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR3 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR2 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR1 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_MPS_IR0 0x00004000 ++/** TMU Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_TMU_ERR 0x00001000 ++/** FSQM Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800 ++/** IQM Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_IQM_ERR 0x00000400 ++/** OCTRLG Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200 ++/** ICTRLG Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100 ++/** OCTRLL 3 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080 ++/** OCTRLL 2 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040 ++/** OCTRLL 1 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020 ++/** OCTRLL 0 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010 ++/** ICTRLL 3 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008 ++/** ICTRLL 2 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004 ++/** ICTRLL 1 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002 ++/** ICTRLL 0 Error ++ Software control for the corresponding bit in the IM4_ISR register. */ ++#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001 ++ ++/* Fields of "IM4 Interrupt Mode Register" */ ++/** VPE0 Performance Monitoring Counter Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000 ++/** VPE0 Error Level Flag Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_ERL 0x40000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000 ++/** VPE0 Exception Level Flag Interrupt ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_VPE0_EXL 0x20000000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000 ++/** MPS Bin. Sem Interrupt to VPE0 ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR8 0x00400000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000 ++/** MPS Global Interrupt to VPE0 ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR7 0x00200000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000 ++/** MPS Status Interrupt #6 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR6 0x00100000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000 ++/** MPS Status Interrupt #5 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR5 0x00080000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000 ++/** MPS Status Interrupt #4 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR4 0x00040000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000 ++/** MPS Status Interrupt #3 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR3 0x00020000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000 ++/** MPS Status Interrupt #2 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR2 0x00010000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000 ++/** MPS Status Interrupt #1 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR1 0x00008000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000 ++/** MPS Status Interrupt #0 (VPE1 to VPE0) ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR0 0x00004000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000 ++/** TMU Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_TMU_ERR 0x00001000 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000 ++/** FSQM Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_FSQM_ERR 0x00000800 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800 ++/** IQM Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_IQM_ERR 0x00000400 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400 ++/** OCTRLG Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200 ++/** ICTRLG Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100 ++/** OCTRLL 3 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080 ++/** OCTRLL 2 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040 ++/** OCTRLL 1 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020 ++/** OCTRLL 0 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010 ++/** ICTRLL 3 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008 ++/** ICTRLL 2 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004 ++/** ICTRLL 1 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002 ++/** ICTRLL 0 Error ++ Type of interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001 ++/* Indirect Interrupt. ++#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */ ++/** Direct Interrupt. */ ++#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001 ++ ++/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */ ++/** IM4 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000 ++/** IM3 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000 ++/** IM2 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00 ++/** IM1 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0 ++/** field offset */ ++#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0 ++/** IM0 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F ++/** field offset */ ++#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0 ++/** Interrupt pending at bit 31 or no pending interrupt */ ++#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F ++ ++/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */ ++/** IM4 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000 ++/** IM3 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000 ++/** IM2 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000 ++/** IM1 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0 ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0 ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800 ++/** IM0 Interrupt Vector Value ++ Returns the highest priority pending interrupt vector. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F ++/** field offset */ ++#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0 ++/** No pending interrupt */ ++#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000 ++/** Interrupt pending at bit 0. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001 ++/** Interrupt pending at bit 1. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002 ++/** Interrupt pending at bit 30. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F ++/** Interrupt pending at bit 31. */ ++#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020 ++ ++/*! @} */ /* ICU0_REGISTER */ ++ ++#endif /* _icu0_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h +@@ -0,0 +1,529 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _status_reg_h ++#define _status_reg_h ++ ++/** \addtogroup STATUS_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define status_r32(reg) reg_r32(&status->reg) ++#define status_w32(val, reg) reg_w32(val, &status->reg) ++#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg) ++#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx) ++#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx) ++#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx) ++#define status_adr_table(reg, idx) adr_table(status->reg, idx) ++ ++ ++/** STATUS register structure */ ++struct gpon_reg_status ++{ ++ /** Reserved */ ++ unsigned int res_0[3]; /* 0x00000000 */ ++ /** Chip Identification Register */ ++ unsigned int chipid; /* 0x0000000C */ ++ /** Chip Location Register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int chiploc; /* 0x00000010 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red0; /* 0x00000014 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red1; /* 0x00000018 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red2; /* 0x0000001C */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red3; /* 0x00000020 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red4; /* 0x00000024 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red5; /* 0x00000028 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red6; /* 0x0000002C */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red7; /* 0x00000030 */ ++ /** Redundancy register ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int red8; /* 0x00000034 */ ++ /** SPARE fuse register 0 ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int fuse0; /* 0x00000038 */ ++ /** Fuses for Analog modules ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int analog; /* 0x0000003C */ ++ /** Configuration fuses for drivers and pll ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int config; /* 0x00000040 */ ++ /** SPARE fuse register 1 ++ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ ++ unsigned int fuse1; /* 0x00000044 */ ++ /** Configuration for sbs0 rambist */ ++ unsigned int mbcfg; /* 0x00000048 */ ++ /** sbs0 bist result and debug data */ ++ unsigned int mbdata; /* 0x0000004C */ ++ /** Reserved */ ++ unsigned int res_1[12]; /* 0x00000050 */ ++}; ++ ++ ++/* Fields of "Chip Identification Register" */ ++/** Chip Version Number ++ Version number */ ++#define STATUS_CHIPID_VERSION_MASK 0xF0000000 ++/** field offset */ ++#define STATUS_CHIPID_VERSION_OFFSET 28 ++/** Part Number, Constant Part ++ The Part Number is fixed to 016Bhex. */ ++#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000 ++/** field offset */ ++#define STATUS_CHIPID_PARTNR_OFFSET 12 ++/** Manufacturer ID ++ The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */ ++#define STATUS_CHIPID_MANID_MASK 0x00000FFE ++/** field offset */ ++#define STATUS_CHIPID_MANID_OFFSET 1 ++/** Constant bit ++ The value of bit field CONST1 is fixed to 1hex */ ++#define STATUS_CHIPID_CONST1 0x00000001 ++ ++/* Fields of "Chip Location Register" */ ++/** Chip Lot ID */ ++#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000 ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16 ++/** Chip X Coordinate */ ++#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00 ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPX_OFFSET 8 ++/** Chip Y Coordinate */ ++#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF ++/** field offset */ ++#define STATUS_CHIPLOC_CHIPY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED0_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED1_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED2_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED3_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED4_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED5_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED6_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED7_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "Redundancy register" */ ++/** Redundancy ++ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ ++#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF ++/** field offset */ ++#define STATUS_RED8_REDUNDANCY_OFFSET 0 ++ ++/* Fields of "SPARE fuse register 0" */ ++/** Soft fuse control ++ Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */ ++#define STATUS_FUSE0_SFC 0x80000000 ++/* Not selected ++#define STATUS_FUSE0_SFC_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_FUSE0_SFC_SEL 0x80000000 ++/** Soft control MBCFG ++ Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */ ++#define STATUS_FUSE0_SC_MBCFG 0x40000000 ++/* Not selected ++#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000 ++/** spare fuse0 ++ eFuses not assigned to hw/sw, can be used for future applications */ ++#define STATUS_FUSE0_F0_MASK 0x3C000000 ++/** field offset */ ++#define STATUS_FUSE0_F0_OFFSET 26 ++/** VCALMM20 Voltage Reference ++ Voltage Reference for calibration via R and constant current (20 uA) */ ++#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM20_OFFSET 20 ++/** VCALMM100 Voltage Reference ++ Voltage Reference for calibration via R and constant current (100 uA) */ ++#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM100_OFFSET 14 ++/** VCALMM400 Voltage Reference ++ Voltage Reference for calibration via R and constant current (400 uA) */ ++#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00 ++/** field offset */ ++#define STATUS_FUSE0_VCALMM400_OFFSET 8 ++/** RCALMM R error correction ++ The resistance deviation from ideal R (1000 Ohm) */ ++#define STATUS_FUSE0_RCALMM_MASK 0x000000FF ++/** field offset */ ++#define STATUS_FUSE0_RCALMM_OFFSET 0 ++ ++/* Fields of "Fuses for Analog modules" */ ++/** reserved Analog eFuses ++ Reserved Register contains information stored in eFuses needed for the analog modules */ ++#define STATUS_ANALOG_A0_MASK 0xFF000000 ++/** field offset */ ++#define STATUS_ANALOG_A0_OFFSET 24 ++/** Absolut Temperature ++ Temperature ERROR */ ++#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000 ++/** field offset */ ++#define STATUS_ANALOG_TEMPMM_OFFSET 18 ++/** Bias Voltage Generation ++ temperature dependency */ ++#define STATUS_ANALOG_TBGP_MASK 0x00038000 ++/** field offset */ ++#define STATUS_ANALOG_TBGP_OFFSET 15 ++/** Bias Voltage Generation ++ voltage dependency */ ++#define STATUS_ANALOG_VBGP_MASK 0x00007000 ++/** field offset */ ++#define STATUS_ANALOG_VBGP_OFFSET 12 ++/** Bias Current Generation */ ++#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00 ++/** field offset */ ++#define STATUS_ANALOG_IREFBGP_OFFSET 8 ++/** Drive DAC Gain */ ++#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0 ++/** field offset */ ++#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4 ++/** BIAS DAC Gain */ ++#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F ++/** field offset */ ++#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0 ++ ++/* Fields of "Configuration fuses for drivers and pll" */ ++/** ddr PU driver ++ ddr pullup driver strength adjustment */ ++#define STATUS_CONFIG_DDRPU_MASK 0xC0000000 ++/** field offset */ ++#define STATUS_CONFIG_DDRPU_OFFSET 30 ++/** ddr PD driver ++ ddr pulldown driver strength adjustment */ ++#define STATUS_CONFIG_DDRPD_MASK 0x30000000 ++/** field offset */ ++#define STATUS_CONFIG_DDRPD_OFFSET 28 ++/** Authentification Unit enable ++ This bit can only be set via eFuse and enables the authentification unit. */ ++#define STATUS_CONFIG_SHA1EN 0x08000000 ++/* Not selected ++#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_SHA1EN_SEL 0x08000000 ++/** Encryption Unit enable ++ This bit can only be set via eFuse and enables the encryption unit. */ ++#define STATUS_CONFIG_AESEN 0x04000000 ++/* Not selected ++#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_AESEN_SEL 0x04000000 ++/** Subversion Number ++ The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */ ++#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000 ++/** field offset */ ++#define STATUS_CONFIG_SUBVERS_OFFSET 22 ++/** PLL settings ++ PLL settings for infrastructure block */ ++#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000 ++/** field offset */ ++#define STATUS_CONFIG_PLLINFRA_OFFSET 12 ++/** GPE frequency selection ++ Scaling down the GPE frequency for debugging purpose */ ++#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00 ++/** field offset */ ++#define STATUS_CONFIG_GPEFREQ_OFFSET 10 ++/** RM enable ++ Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */ ++#define STATUS_CONFIG_RME 0x00000200 ++/* Not selected ++#define STATUS_CONFIG_RME_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_RME_SEL 0x00000200 ++/** RM settings ++ Read Marging Settings for all VIRAGE Memories except GPE */ ++#define STATUS_CONFIG_RM_MASK 0x000001E0 ++/** field offset */ ++#define STATUS_CONFIG_RM_OFFSET 5 ++/** RM enable for GPE Memories ++ Activates the Read Margin Settings defined in the RM Field */ ++#define STATUS_CONFIG_RMEGPE 0x00000010 ++/* Not selected ++#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */ ++/** Selected */ ++#define STATUS_CONFIG_RMEGPE_SEL 0x00000010 ++/** RM settings for GPE Memories ++ Read Marging Settings for VIRAGE Memories in GPE module */ ++#define STATUS_CONFIG_RMGPE_MASK 0x0000000F ++/** field offset */ ++#define STATUS_CONFIG_RMGPE_OFFSET 0 ++ ++/* Fields of "SPARE fuse register 1" */ ++/** spare fuse1 ++ eFuses not assigned to hw/sw, can be used for future applications */ ++#define STATUS_FUSE1_F1_MASK 0xFFF00000 ++/** field offset */ ++#define STATUS_FUSE1_F1_OFFSET 20 ++/** DCDC DDR OFFSET ++ offset error sense path */ ++#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000 ++/** field offset */ ++#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16 ++/** DCDC DDR GAIN ++ gain error sense path */ ++#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00 ++/** field offset */ ++#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10 ++/** DCDC APD OFFSET ++ offset error sense path */ ++#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0 ++/** field offset */ ++#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6 ++/** DCDC APD GAIN ++ gain error sense path */ ++#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F ++/** field offset */ ++#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0 ++ ++/* Fields of "Configuration for sbs0 rambist" */ ++/** Disable asc monitoring during boot-up ++ Bit is used to avoid asc output for reducing pattern count on testsystem */ ++#define STATUS_MBCFG_ASC_DBGDIS 0x01000000 ++/* Disable ++#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000 ++/** Descrambling Enable/Disable ++ Enables Address and Data Descrambling for internal Memory Test */ ++#define STATUS_MBCFG_DSC 0x00800000 ++/* Disable ++#define STATUS_MBCFG_DSC_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_DSC_EN 0x00800000 ++/** Enable repair mode ++ When bit is set redundancy repair mode is activated */ ++#define STATUS_MBCFG_REPAIR 0x00400000 ++/* Disable ++#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_REPAIR_EN 0x00400000 ++/** DEBUG Mode */ ++#define STATUS_MBCFG_DBG 0x00200000 ++/* Disable ++#define STATUS_MBCFG_DBG_DIS 0x00000000 */ ++/** Enable */ ++#define STATUS_MBCFG_DBG_EN 0x00200000 ++/** Retention Time ++ Length oft the Retention Time */ ++#define STATUS_MBCFG_RTIME_MASK 0x001C0000 ++/** field offset */ ++#define STATUS_MBCFG_RTIME_OFFSET 18 ++/** retention mode is switched off */ ++#define STATUS_MBCFG_RTIME_RET0 0x00000000 ++/** Retention time 50 ms */ ++#define STATUS_MBCFG_RTIME_RET50 0x00040000 ++/** Retention time 60 ms */ ++#define STATUS_MBCFG_RTIME_RET60 0x00080000 ++/** Retention time 70 ms */ ++#define STATUS_MBCFG_RTIME_RET70 0x000C0000 ++/** Retention time 80 ms */ ++#define STATUS_MBCFG_RTIME_RET80 0x00100000 ++/** Retention time 90 ms */ ++#define STATUS_MBCFG_RTIME_RET90 0x00140000 ++/** Retention time 1000 ms */ ++#define STATUS_MBCFG_RTIME_RET1000 0x00180000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_5_MASK 0x00038000 ++/** field offset */ ++#define STATUS_MBCFG_TID_5_OFFSET 15 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_5_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_5_MARCH 0x00008000 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_5_CHCK 0x00010000 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_5_HAM 0x00018000 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_5_ADEC 0x00020000 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000 ++/** Reserved */ ++#define STATUS_MBCFG_TID_5_RES 0x00030000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_4_MASK 0x00007000 ++/** field offset */ ++#define STATUS_MBCFG_TID_4_OFFSET 12 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_4_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_4_MARCH 0x00001000 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_4_CHCK 0x00002000 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_4_HAM 0x00003000 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_4_ADEC 0x00004000 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000 ++/** Reserved */ ++#define STATUS_MBCFG_TID_4_RES 0x00006000 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_3_MASK 0x00000E00 ++/** field offset */ ++#define STATUS_MBCFG_TID_3_OFFSET 9 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_3_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_3_MARCH 0x00000200 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_3_CHCK 0x00000400 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_3_HAM 0x00000600 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_3_ADEC 0x00000800 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00 ++/** Reserved */ ++#define STATUS_MBCFG_TID_3_RES 0x00000C00 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_2_MASK 0x000001C0 ++/** field offset */ ++#define STATUS_MBCFG_TID_2_OFFSET 6 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_2_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_2_MARCH 0x00000040 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_2_CHCK 0x00000080 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_2_HAM 0x000000C0 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_2_ADEC 0x00000100 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140 ++/** Reserved */ ++#define STATUS_MBCFG_TID_2_RES 0x00000180 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_1_MASK 0x00000038 ++/** field offset */ ++#define STATUS_MBCFG_TID_1_OFFSET 3 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_1_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_1_MARCH 0x00000008 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_1_CHCK 0x00000010 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_1_HAM 0x00000018 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_1_ADEC 0x00000020 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028 ++/** Reserved */ ++#define STATUS_MBCFG_TID_1_RES 0x00000030 ++/** Test ID ++ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ ++#define STATUS_MBCFG_TID_0_MASK 0x00000007 ++/** field offset */ ++#define STATUS_MBCFG_TID_0_OFFSET 0 ++/** No test is performed */ ++#define STATUS_MBCFG_TID_0_NONE 0x00000000 ++/** March test */ ++#define STATUS_MBCFG_TID_0_MARCH 0x00000001 ++/** Checkerboard test */ ++#define STATUS_MBCFG_TID_0_CHCK 0x00000002 ++/** Hammer test */ ++#define STATUS_MBCFG_TID_0_HAM 0x00000003 ++/** Address decoder test */ ++#define STATUS_MBCFG_TID_0_ADEC 0x00000004 ++/** Write mask byte test */ ++#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005 ++/** Reserved */ ++#define STATUS_MBCFG_TID_0_RES 0x00000006 ++ ++/* Fields of "sbs0 bist result and debug data" */ ++/** BIST result and debug data ++ Stores additional debug information */ ++#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8 ++/** field offset */ ++#define STATUS_MBDATA_DATA_OFFSET 3 ++/** MBIST NOGO ++ The BIST failed and cannot be repaired due to many failure locations */ ++#define STATUS_MBDATA_MBNOGO 0x00000004 ++/** MBIST FAILED ++ The BIST failed but can be repaired */ ++#define STATUS_MBDATA_MBFAIL 0x00000002 ++/** MBIST PASSED ++ The BIST passed without any Failures */ ++#define STATUS_MBDATA_MBPASS 0x00000001 ++ ++/*! @} */ /* STATUS_REGISTER */ ++ ++#endif /* _status_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h +@@ -0,0 +1,2008 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys1_reg_h ++#define _sys1_reg_h ++ ++/** \addtogroup SYS1_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys1_r32(reg) reg_r32(&sys1->reg) ++#define sys1_w32(val, reg) reg_w32(val, &sys1->reg) ++#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg) ++#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx) ++#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx) ++#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx) ++#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx) ++ ++ ++/** SYS1 register structure */ ++struct gpon_reg_sys1 ++{ ++ /** Clock Status Register */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[4]; /* 0x00000030 */ ++ /** CPU0 Clock Control Register ++ Clock control register for CPU0 */ ++ unsigned int cpu0cc; /* 0x00000040 */ ++ /** Reserved */ ++ unsigned int res_2[7]; /* 0x00000044 */ ++ /** CPU0 Reset Source Register ++ Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */ ++ unsigned int cpu0rs; /* 0x00000060 */ ++ /** Reserved */ ++ unsigned int res_3[7]; /* 0x00000064 */ ++ /** CPU0 Wakeup Configuration Register ++ Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */ ++ unsigned int cpu0wcfg; /* 0x00000080 */ ++ /** Reserved */ ++ unsigned int res_4[7]; /* 0x00000084 */ ++ /** Bootmode Control Register ++ Reflects the bootmode for the CPU and provides means to manipulate it. */ ++ unsigned int bmc; /* 0x000000A0 */ ++ /** Reserved */ ++ unsigned int res_5[3]; /* 0x000000A4 */ ++ /** Sleep Configuration Register */ ++ unsigned int scfg; /* 0x000000B0 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** CLKO Pad Control Register ++ Controls the behaviour of the CLKO pad/ball. */ ++ unsigned int clkoc; /* 0x000000B8 */ ++ /** Infrastructure Control Register ++ Controls the behaviour of the components of the infrastructure block. */ ++ unsigned int infrac; /* 0x000000BC */ ++ /** HRST_OUT_N Control Register ++ Controls the behaviour of the HRST_OUT_N pin. */ ++ unsigned int hrstoutc; /* 0x000000C0 */ ++ /** EBU Clock Control Register ++ Clock control register for the EBU. */ ++ unsigned int ebucc; /* 0x000000C4 */ ++ /** Reserved */ ++ unsigned int res_6[2]; /* 0x000000C8 */ ++ /** NMI Status Register ++ The Test NMI source is the GPTC counter 1A overflow bit. */ ++ unsigned int nmis; /* 0x000000D0 */ ++ /** NMI Set Register */ ++ unsigned int nmiset; /* 0x000000D4 */ ++ /** NMI Clear Register */ ++ unsigned int nmiclr; /* 0x000000D8 */ ++ /** NMI Test Configuration Register */ ++ unsigned int nmitcfg; /* 0x000000DC */ ++ /** NMI VPE1 Control Register */ ++ unsigned int nmivpe1c; /* 0x000000E0 */ ++ /** Reserved */ ++ unsigned int res_7[3]; /* 0x000000E4 */ ++ /** IRN Capture Register ++ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */ ++ unsigned int irncr; /* 0x000000F0 */ ++ /** IRN Interrupt Control Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int irnicr; /* 0x000000F4 */ ++ /** IRN Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int irnen; /* 0x000000F8 */ ++ /** Reserved */ ++ unsigned int res_8; /* 0x000000FC */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** STATUS Clock Enable ++ Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */ ++#define CLKS_STATUS 0x80000000 ++/* Disable ++#define CLKS_STATUS_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_STATUS_EN 0x80000000 ++/** SHA1 Clock Enable ++ Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKS_SHA1 0x40000000 ++/* Disable ++#define CLKS_SHA1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_SHA1_EN 0x40000000 ++/** AES Clock Enable ++ Shows the clock enable bit for the AES domain. This domain contains the AES block. */ ++#define CLKS_AES 0x20000000 ++/* Disable ++#define CLKS_AES_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_AES_EN 0x20000000 ++/** PCM Clock Enable ++ Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */ ++#define CLKS_PCM 0x10000000 ++/* Disable ++#define CLKS_PCM_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PCM_EN 0x10000000 ++/** FSCT Clock Enable ++ Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */ ++#define CLKS_FSCT 0x08000000 ++/* Disable ++#define CLKS_FSCT_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_FSCT_EN 0x08000000 ++/** GPTC Clock Enable ++ Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */ ++#define CLKS_GPTC 0x04000000 ++/* Disable ++#define CLKS_GPTC_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_GPTC_EN 0x04000000 ++/** MPS Clock Enable ++ Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */ ++#define CLKS_MPS 0x02000000 ++/* Disable ++#define CLKS_MPS_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_MPS_EN 0x02000000 ++/** DFEV0 Clock Enable ++ Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKS_DFEV0 0x01000000 ++/* Disable ++#define CLKS_DFEV0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DFEV0_EN 0x01000000 ++/** PADCTRL4 Clock Enable ++ Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKS_PADCTRL4 0x00400000 ++/* Disable ++#define CLKS_PADCTRL4_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL4_EN 0x00400000 ++/** PADCTRL3 Clock Enable ++ Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKS_PADCTRL3 0x00200000 ++/* Disable ++#define CLKS_PADCTRL3_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL3_EN 0x00200000 ++/** PADCTRL1 Clock Enable ++ Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKS_PADCTRL1 0x00100000 ++/* Disable ++#define CLKS_PADCTRL1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_PADCTRL1_EN 0x00100000 ++/** P4 Clock Enable ++ Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKS_P4 0x00040000 ++/* Disable ++#define CLKS_P4_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P4_EN 0x00040000 ++/** P3 Clock Enable ++ Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKS_P3 0x00020000 ++/* Disable ++#define CLKS_P3_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P3_EN 0x00020000 ++/** P1 Clock Enable ++ Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKS_P1 0x00010000 ++/* Disable ++#define CLKS_P1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_P1_EN 0x00010000 ++/** HOST Clock Enable ++ Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */ ++#define CLKS_HOST 0x00008000 ++/* Disable ++#define CLKS_HOST_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_HOST_EN 0x00008000 ++/** I2C Clock Enable ++ Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */ ++#define CLKS_I2C 0x00004000 ++/* Disable ++#define CLKS_I2C_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_I2C_EN 0x00004000 ++/** SSC0 Clock Enable ++ Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKS_SSC0 0x00002000 ++/* Disable ++#define CLKS_SSC0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_SSC0_EN 0x00002000 ++/** ASC0 Clock Enable ++ Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKS_ASC0 0x00001000 ++/* Disable ++#define CLKS_ASC0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_ASC0_EN 0x00001000 ++/** ASC1 Clock Enable ++ Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKS_ASC1 0x00000800 ++/* Disable ++#define CLKS_ASC1_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_ASC1_EN 0x00000800 ++/** DCDCAPD Clock Enable ++ Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKS_DCDCAPD 0x00000400 ++/* Disable ++#define CLKS_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDCAPD_EN 0x00000400 ++/** DCDCDDR Clock Enable ++ Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKS_DCDCDDR 0x00000200 ++/* Disable ++#define CLKS_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDCDDR_EN 0x00000200 ++/** DCDC1V0 Clock Enable ++ Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKS_DCDC1V0 0x00000100 ++/* Disable ++#define CLKS_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DCDC1V0_EN 0x00000100 ++/** TRC2MEM Clock Enable ++ Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKS_TRC2MEM 0x00000040 ++/* Disable ++#define CLKS_TRC2MEM_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_TRC2MEM_EN 0x00000040 ++/** DDR Clock Enable ++ Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */ ++#define CLKS_DDR 0x00000020 ++/* Disable ++#define CLKS_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_DDR_EN 0x00000020 ++/** EBU Clock Enable ++ Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */ ++#define CLKS_EBU 0x00000010 ++/* Disable ++#define CLKS_EBU_DIS 0x00000000 */ ++/** Enable */ ++#define CLKS_EBU_EN 0x00000010 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable STATUS ++ Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ ++#define CLKEN_STATUS 0x80000000 ++/* No-Operation ++#define CLKEN_STATUS_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_STATUS_SET 0x80000000 ++/** Set Clock Enable SHA1 ++ Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKEN_SHA1 0x40000000 ++/* No-Operation ++#define CLKEN_SHA1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_SHA1_SET 0x40000000 ++/** Set Clock Enable AES ++ Sets the clock enable bit of the AES domain. This domain contains the AES block. */ ++#define CLKEN_AES 0x20000000 ++/* No-Operation ++#define CLKEN_AES_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_AES_SET 0x20000000 ++/** Set Clock Enable PCM ++ Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ ++#define CLKEN_PCM 0x10000000 ++/* No-Operation ++#define CLKEN_PCM_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PCM_SET 0x10000000 ++/** Set Clock Enable FSCT ++ Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ ++#define CLKEN_FSCT 0x08000000 ++/* No-Operation ++#define CLKEN_FSCT_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_FSCT_SET 0x08000000 ++/** Set Clock Enable GPTC ++ Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ ++#define CLKEN_GPTC 0x04000000 ++/* No-Operation ++#define CLKEN_GPTC_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_GPTC_SET 0x04000000 ++/** Set Clock Enable MPS ++ Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */ ++#define CLKEN_MPS 0x02000000 ++/* No-Operation ++#define CLKEN_MPS_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_MPS_SET 0x02000000 ++/** Set Clock Enable DFEV0 ++ Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKEN_DFEV0 0x01000000 ++/* No-Operation ++#define CLKEN_DFEV0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DFEV0_SET 0x01000000 ++/** Set Clock Enable PADCTRL4 ++ Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKEN_PADCTRL4 0x00400000 ++/* No-Operation ++#define CLKEN_PADCTRL4_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL4_SET 0x00400000 ++/** Set Clock Enable PADCTRL3 ++ Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKEN_PADCTRL3 0x00200000 ++/* No-Operation ++#define CLKEN_PADCTRL3_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL3_SET 0x00200000 ++/** Set Clock Enable PADCTRL1 ++ Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKEN_PADCTRL1 0x00100000 ++/* No-Operation ++#define CLKEN_PADCTRL1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_PADCTRL1_SET 0x00100000 ++/** Set Clock Enable P4 ++ Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKEN_P4 0x00040000 ++/* No-Operation ++#define CLKEN_P4_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P4_SET 0x00040000 ++/** Set Clock Enable P3 ++ Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKEN_P3 0x00020000 ++/* No-Operation ++#define CLKEN_P3_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P3_SET 0x00020000 ++/** Set Clock Enable P1 ++ Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKEN_P1 0x00010000 ++/* No-Operation ++#define CLKEN_P1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_P1_SET 0x00010000 ++/** Set Clock Enable HOST ++ Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ ++#define CLKEN_HOST 0x00008000 ++/* No-Operation ++#define CLKEN_HOST_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_HOST_SET 0x00008000 ++/** Set Clock Enable I2C ++ Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ ++#define CLKEN_I2C 0x00004000 ++/* No-Operation ++#define CLKEN_I2C_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_I2C_SET 0x00004000 ++/** Set Clock Enable SSC0 ++ Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKEN_SSC0 0x00002000 ++/* No-Operation ++#define CLKEN_SSC0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_SSC0_SET 0x00002000 ++/** Set Clock Enable ASC0 ++ Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKEN_ASC0 0x00001000 ++/* No-Operation ++#define CLKEN_ASC0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_ASC0_SET 0x00001000 ++/** Set Clock Enable ASC1 ++ Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKEN_ASC1 0x00000800 ++/* No-Operation ++#define CLKEN_ASC1_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_ASC1_SET 0x00000800 ++/** Set Clock Enable DCDCAPD ++ Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKEN_DCDCAPD 0x00000400 ++/* No-Operation ++#define CLKEN_DCDCAPD_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDCAPD_SET 0x00000400 ++/** Set Clock Enable DCDCDDR ++ Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKEN_DCDCDDR 0x00000200 ++/* No-Operation ++#define CLKEN_DCDCDDR_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDCDDR_SET 0x00000200 ++/** Set Clock Enable DCDC1V0 ++ Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKEN_DCDC1V0 0x00000100 ++/* No-Operation ++#define CLKEN_DCDC1V0_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DCDC1V0_SET 0x00000100 ++/** Set Clock Enable TRC2MEM ++ Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKEN_TRC2MEM 0x00000040 ++/* No-Operation ++#define CLKEN_TRC2MEM_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_TRC2MEM_SET 0x00000040 ++/** Set Clock Enable DDR ++ Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ ++#define CLKEN_DDR 0x00000020 ++/* No-Operation ++#define CLKEN_DDR_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_DDR_SET 0x00000020 ++/** Set Clock Enable EBU ++ Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ ++#define CLKEN_EBU 0x00000010 ++/* No-Operation ++#define CLKEN_EBU_NOP 0x00000000 */ ++/** Set */ ++#define CLKEN_EBU_SET 0x00000010 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable STATUS ++ Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ ++#define CLKCLR_STATUS 0x80000000 ++/* No-Operation ++#define CLKCLR_STATUS_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_STATUS_CLR 0x80000000 ++/** Clear Clock Enable SHA1 ++ Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ ++#define CLKCLR_SHA1 0x40000000 ++/* No-Operation ++#define CLKCLR_SHA1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_SHA1_CLR 0x40000000 ++/** Clear Clock Enable AES ++ Clears the clock enable bit of the AES domain. This domain contains the AES block. */ ++#define CLKCLR_AES 0x20000000 ++/* No-Operation ++#define CLKCLR_AES_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_AES_CLR 0x20000000 ++/** Clear Clock Enable PCM ++ Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ ++#define CLKCLR_PCM 0x10000000 ++/* No-Operation ++#define CLKCLR_PCM_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PCM_CLR 0x10000000 ++/** Clear Clock Enable FSCT ++ Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ ++#define CLKCLR_FSCT 0x08000000 ++/* No-Operation ++#define CLKCLR_FSCT_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_FSCT_CLR 0x08000000 ++/** Clear Clock Enable GPTC ++ Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ ++#define CLKCLR_GPTC 0x04000000 ++/* No-Operation ++#define CLKCLR_GPTC_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_GPTC_CLR 0x04000000 ++/** Clear Clock Enable MPS ++ Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */ ++#define CLKCLR_MPS 0x02000000 ++/* No-Operation ++#define CLKCLR_MPS_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_MPS_CLR 0x02000000 ++/** Clear Clock Enable DFEV0 ++ Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define CLKCLR_DFEV0 0x01000000 ++/* No-Operation ++#define CLKCLR_DFEV0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DFEV0_CLR 0x01000000 ++/** Clear Clock Enable PADCTRL4 ++ Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define CLKCLR_PADCTRL4 0x00400000 ++/* No-Operation ++#define CLKCLR_PADCTRL4_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL4_CLR 0x00400000 ++/** Clear Clock Enable PADCTRL3 ++ Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define CLKCLR_PADCTRL3 0x00200000 ++/* No-Operation ++#define CLKCLR_PADCTRL3_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL3_CLR 0x00200000 ++/** Clear Clock Enable PADCTRL1 ++ Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define CLKCLR_PADCTRL1 0x00100000 ++/* No-Operation ++#define CLKCLR_PADCTRL1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_PADCTRL1_CLR 0x00100000 ++/** Clear Clock Enable P4 ++ Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define CLKCLR_P4 0x00040000 ++/* No-Operation ++#define CLKCLR_P4_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P4_CLR 0x00040000 ++/** Clear Clock Enable P3 ++ Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define CLKCLR_P3 0x00020000 ++/* No-Operation ++#define CLKCLR_P3_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P3_CLR 0x00020000 ++/** Clear Clock Enable P1 ++ Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define CLKCLR_P1 0x00010000 ++/* No-Operation ++#define CLKCLR_P1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_P1_CLR 0x00010000 ++/** Clear Clock Enable HOST ++ Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ ++#define CLKCLR_HOST 0x00008000 ++/* No-Operation ++#define CLKCLR_HOST_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_HOST_CLR 0x00008000 ++/** Clear Clock Enable I2C ++ Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ ++#define CLKCLR_I2C 0x00004000 ++/* No-Operation ++#define CLKCLR_I2C_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_I2C_CLR 0x00004000 ++/** Clear Clock Enable SSC0 ++ Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define CLKCLR_SSC0 0x00002000 ++/* No-Operation ++#define CLKCLR_SSC0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_SSC0_CLR 0x00002000 ++/** Clear Clock Enable ASC0 ++ Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define CLKCLR_ASC0 0x00001000 ++/* No-Operation ++#define CLKCLR_ASC0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_ASC0_CLR 0x00001000 ++/** Clear Clock Enable ASC1 ++ Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ ++#define CLKCLR_ASC1 0x00000800 ++/* No-Operation ++#define CLKCLR_ASC1_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_ASC1_CLR 0x00000800 ++/** Clear Clock Enable DCDCAPD ++ Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define CLKCLR_DCDCAPD 0x00000400 ++/* No-Operation ++#define CLKCLR_DCDCAPD_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDCAPD_CLR 0x00000400 ++/** Clear Clock Enable DCDCDDR ++ Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define CLKCLR_DCDCDDR 0x00000200 ++/* No-Operation ++#define CLKCLR_DCDCDDR_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDCDDR_CLR 0x00000200 ++/** Clear Clock Enable DCDC1V0 ++ Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define CLKCLR_DCDC1V0 0x00000100 ++/* No-Operation ++#define CLKCLR_DCDC1V0_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DCDC1V0_CLR 0x00000100 ++/** Clear Clock Enable TRC2MEM ++ Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define CLKCLR_TRC2MEM 0x00000040 ++/* No-Operation ++#define CLKCLR_TRC2MEM_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_TRC2MEM_CLR 0x00000040 ++/** Clear Clock Enable DDR ++ Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ ++#define CLKCLR_DDR 0x00000020 ++/* No-Operation ++#define CLKCLR_DDR_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_DDR_CLR 0x00000020 ++/** Clear Clock Enable EBU ++ Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ ++#define CLKCLR_EBU 0x00000010 ++/* No-Operation ++#define CLKCLR_EBU_NOP 0x00000000 */ ++/** Clear */ ++#define CLKCLR_EBU_CLR 0x00000010 ++ ++/* Fields of "Activation Status Register" */ ++/** STATUS Status ++ Shows the activation status of the STATUS domain. This domain contains the STATUS block. */ ++#define ACTS_STATUS 0x80000000 ++/* The block is inactive. ++#define ACTS_STATUS_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_STATUS_ACT 0x80000000 ++/** SHA1 Status ++ Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */ ++#define ACTS_SHA1 0x40000000 ++/* The block is inactive. ++#define ACTS_SHA1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_SHA1_ACT 0x40000000 ++/** AES Status ++ Shows the activation status of the AES domain. This domain contains the AES block. */ ++#define ACTS_AES 0x20000000 ++/* The block is inactive. ++#define ACTS_AES_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_AES_ACT 0x20000000 ++/** PCM Status ++ Shows the activation status of the PCM domain. This domain contains the PCM interface block. */ ++#define ACTS_PCM 0x10000000 ++/* The block is inactive. ++#define ACTS_PCM_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PCM_ACT 0x10000000 ++/** FSCT Status ++ Shows the activation status of the FSCT domain. This domain contains the FSCT block. */ ++#define ACTS_FSCT 0x08000000 ++/* The block is inactive. ++#define ACTS_FSCT_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_FSCT_ACT 0x08000000 ++/** GPTC Status ++ Shows the activation status of the GPTC domain. This domain contains the GPTC block. */ ++#define ACTS_GPTC 0x04000000 ++/* The block is inactive. ++#define ACTS_GPTC_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_GPTC_ACT 0x04000000 ++/** MPS Status ++ Shows the activation status of the MPS domain. This domain contains the MPS block. */ ++#define ACTS_MPS 0x02000000 ++/* The block is inactive. ++#define ACTS_MPS_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_MPS_ACT 0x02000000 ++/** DFEV0 Status ++ Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define ACTS_DFEV0 0x01000000 ++/* The block is inactive. ++#define ACTS_DFEV0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DFEV0_ACT 0x01000000 ++/** PADCTRL4 Status ++ Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define ACTS_PADCTRL4 0x00400000 ++/* The block is inactive. ++#define ACTS_PADCTRL4_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL4_ACT 0x00400000 ++/** PADCTRL3 Status ++ Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define ACTS_PADCTRL3 0x00200000 ++/* The block is inactive. ++#define ACTS_PADCTRL3_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL3_ACT 0x00200000 ++/** PADCTRL1 Status ++ Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define ACTS_PADCTRL1 0x00100000 ++/* The block is inactive. ++#define ACTS_PADCTRL1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_PADCTRL1_ACT 0x00100000 ++/** P4 Status ++ Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define ACTS_P4 0x00040000 ++/* The block is inactive. ++#define ACTS_P4_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P4_ACT 0x00040000 ++/** P3 Status ++ Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define ACTS_P3 0x00020000 ++/* The block is inactive. ++#define ACTS_P3_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P3_ACT 0x00020000 ++/** P1 Status ++ Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define ACTS_P1 0x00010000 ++/* The block is inactive. ++#define ACTS_P1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_P1_ACT 0x00010000 ++/** HOST Status ++ Shows the activation status of the HOST domain. This domain contains the HOST interface block. */ ++#define ACTS_HOST 0x00008000 ++/* The block is inactive. ++#define ACTS_HOST_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_HOST_ACT 0x00008000 ++/** I2C Status ++ Shows the activation status of the I2C domain. This domain contains the I2C interface block. */ ++#define ACTS_I2C 0x00004000 ++/* The block is inactive. ++#define ACTS_I2C_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_I2C_ACT 0x00004000 ++/** SSC0 Status ++ Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define ACTS_SSC0 0x00002000 ++/* The block is inactive. ++#define ACTS_SSC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_SSC0_ACT 0x00002000 ++/** ASC0 Status ++ Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define ACTS_ASC0 0x00001000 ++/* The block is inactive. ++#define ACTS_ASC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_ASC0_ACT 0x00001000 ++/** ASC1 Status ++ Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */ ++#define ACTS_ASC1 0x00000800 ++/* The block is inactive. ++#define ACTS_ASC1_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_ASC1_ACT 0x00000800 ++/** DCDCAPD Status ++ Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define ACTS_DCDCAPD 0x00000400 ++/* The block is inactive. ++#define ACTS_DCDCAPD_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDCAPD_ACT 0x00000400 ++/** DCDCDDR Status ++ Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define ACTS_DCDCDDR 0x00000200 ++/* The block is inactive. ++#define ACTS_DCDCDDR_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDCDDR_ACT 0x00000200 ++/** DCDC1V0 Status ++ Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define ACTS_DCDC1V0 0x00000100 ++/* The block is inactive. ++#define ACTS_DCDC1V0_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DCDC1V0_ACT 0x00000100 ++/** TRC2MEM Status ++ Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define ACTS_TRC2MEM 0x00000040 ++/* The block is inactive. ++#define ACTS_TRC2MEM_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_TRC2MEM_ACT 0x00000040 ++/** DDR Status ++ Shows the activation status of the DDR domain. This domain contains the DDR interface block. */ ++#define ACTS_DDR 0x00000020 ++/* The block is inactive. ++#define ACTS_DDR_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_DDR_ACT 0x00000020 ++/** EBU Status ++ Shows the activation status of the EBU domain. This domain contains the EBU interface block. */ ++#define ACTS_EBU 0x00000010 ++/* The block is inactive. ++#define ACTS_EBU_INACT 0x00000000 */ ++/** The block is active. */ ++#define ACTS_EBU_ACT 0x00000010 ++ ++/* Fields of "Activation Register" */ ++/** Activate STATUS ++ Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */ ++#define ACT_STATUS 0x80000000 ++/* No-Operation ++#define ACT_STATUS_NOP 0x00000000 */ ++/** Set */ ++#define ACT_STATUS_SET 0x80000000 ++/** Activate SHA1 ++ Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ ++#define ACT_SHA1 0x40000000 ++/* No-Operation ++#define ACT_SHA1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_SHA1_SET 0x40000000 ++/** Activate AES ++ Sets the activation flag of the AES domain. This domain contains the AES block. */ ++#define ACT_AES 0x20000000 ++/* No-Operation ++#define ACT_AES_NOP 0x00000000 */ ++/** Set */ ++#define ACT_AES_SET 0x20000000 ++/** Activate PCM ++ Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */ ++#define ACT_PCM 0x10000000 ++/* No-Operation ++#define ACT_PCM_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PCM_SET 0x10000000 ++/** Activate FSCT ++ Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */ ++#define ACT_FSCT 0x08000000 ++/* No-Operation ++#define ACT_FSCT_NOP 0x00000000 */ ++/** Set */ ++#define ACT_FSCT_SET 0x08000000 ++/** Activate GPTC ++ Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */ ++#define ACT_GPTC 0x04000000 ++/* No-Operation ++#define ACT_GPTC_NOP 0x00000000 */ ++/** Set */ ++#define ACT_GPTC_SET 0x04000000 ++/** Activate MPS ++ Sets the activation flag of the MPS domain. This domain contains the MPS block. */ ++#define ACT_MPS 0x02000000 ++/* No-Operation ++#define ACT_MPS_NOP 0x00000000 */ ++/** Set */ ++#define ACT_MPS_SET 0x02000000 ++/** Activate DFEV0 ++ Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define ACT_DFEV0 0x01000000 ++/* No-Operation ++#define ACT_DFEV0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DFEV0_SET 0x01000000 ++/** Activate PADCTRL4 ++ Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define ACT_PADCTRL4 0x00400000 ++/* No-Operation ++#define ACT_PADCTRL4_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL4_SET 0x00400000 ++/** Activate PADCTRL3 ++ Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define ACT_PADCTRL3 0x00200000 ++/* No-Operation ++#define ACT_PADCTRL3_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL3_SET 0x00200000 ++/** Activate PADCTRL1 ++ Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define ACT_PADCTRL1 0x00100000 ++/* No-Operation ++#define ACT_PADCTRL1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_PADCTRL1_SET 0x00100000 ++/** Activate P4 ++ Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define ACT_P4 0x00040000 ++/* No-Operation ++#define ACT_P4_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P4_SET 0x00040000 ++/** Activate P3 ++ Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define ACT_P3 0x00020000 ++/* No-Operation ++#define ACT_P3_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P3_SET 0x00020000 ++/** Activate P1 ++ Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define ACT_P1 0x00010000 ++/* No-Operation ++#define ACT_P1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_P1_SET 0x00010000 ++/** Activate HOST ++ Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */ ++#define ACT_HOST 0x00008000 ++/* No-Operation ++#define ACT_HOST_NOP 0x00000000 */ ++/** Set */ ++#define ACT_HOST_SET 0x00008000 ++/** Activate I2C ++ Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */ ++#define ACT_I2C 0x00004000 ++/* No-Operation ++#define ACT_I2C_NOP 0x00000000 */ ++/** Set */ ++#define ACT_I2C_SET 0x00004000 ++/** Activate SSC0 ++ Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define ACT_SSC0 0x00002000 ++/* No-Operation ++#define ACT_SSC0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_SSC0_SET 0x00002000 ++/** Activate ASC0 ++ Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define ACT_ASC0 0x00001000 ++/* No-Operation ++#define ACT_ASC0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_ASC0_SET 0x00001000 ++/** Activate ASC1 ++ Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ ++#define ACT_ASC1 0x00000800 ++/* No-Operation ++#define ACT_ASC1_NOP 0x00000000 */ ++/** Set */ ++#define ACT_ASC1_SET 0x00000800 ++/** Activate DCDCAPD ++ Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define ACT_DCDCAPD 0x00000400 ++/* No-Operation ++#define ACT_DCDCAPD_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDCAPD_SET 0x00000400 ++/** Activate DCDCDDR ++ Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define ACT_DCDCDDR 0x00000200 ++/* No-Operation ++#define ACT_DCDCDDR_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDCDDR_SET 0x00000200 ++/** Activate DCDC1V0 ++ Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define ACT_DCDC1V0 0x00000100 ++/* No-Operation ++#define ACT_DCDC1V0_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DCDC1V0_SET 0x00000100 ++/** Activate TRC2MEM ++ Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define ACT_TRC2MEM 0x00000040 ++/* No-Operation ++#define ACT_TRC2MEM_NOP 0x00000000 */ ++/** Set */ ++#define ACT_TRC2MEM_SET 0x00000040 ++/** Activate DDR ++ Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */ ++#define ACT_DDR 0x00000020 ++/* No-Operation ++#define ACT_DDR_NOP 0x00000000 */ ++/** Set */ ++#define ACT_DDR_SET 0x00000020 ++/** Activate EBU ++ Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */ ++#define ACT_EBU 0x00000010 ++/* No-Operation ++#define ACT_EBU_NOP 0x00000000 */ ++/** Set */ ++#define ACT_EBU_SET 0x00000010 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate STATUS ++ Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */ ++#define DEACT_STATUS 0x80000000 ++/* No-Operation ++#define DEACT_STATUS_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_STATUS_CLR 0x80000000 ++/** Deactivate SHA1 ++ Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ ++#define DEACT_SHA1 0x40000000 ++/* No-Operation ++#define DEACT_SHA1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_SHA1_CLR 0x40000000 ++/** Deactivate AES ++ Clears the activation flag of the AES domain. This domain contains the AES block. */ ++#define DEACT_AES 0x20000000 ++/* No-Operation ++#define DEACT_AES_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_AES_CLR 0x20000000 ++/** Deactivate PCM ++ Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */ ++#define DEACT_PCM 0x10000000 ++/* No-Operation ++#define DEACT_PCM_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PCM_CLR 0x10000000 ++/** Deactivate FSCT ++ Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */ ++#define DEACT_FSCT 0x08000000 ++/* No-Operation ++#define DEACT_FSCT_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_FSCT_CLR 0x08000000 ++/** Deactivate GPTC ++ Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */ ++#define DEACT_GPTC 0x04000000 ++/* No-Operation ++#define DEACT_GPTC_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_GPTC_CLR 0x04000000 ++/** Deactivate MPS ++ Clears the activation flag of the MPS domain. This domain contains the MPS block. */ ++#define DEACT_MPS 0x02000000 ++/* No-Operation ++#define DEACT_MPS_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_MPS_CLR 0x02000000 ++/** Deactivate DFEV0 ++ Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define DEACT_DFEV0 0x01000000 ++/* No-Operation ++#define DEACT_DFEV0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DFEV0_CLR 0x01000000 ++/** Deactivate PADCTRL4 ++ Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define DEACT_PADCTRL4 0x00400000 ++/* No-Operation ++#define DEACT_PADCTRL4_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL4_CLR 0x00400000 ++/** Deactivate PADCTRL3 ++ Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define DEACT_PADCTRL3 0x00200000 ++/* No-Operation ++#define DEACT_PADCTRL3_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL3_CLR 0x00200000 ++/** Deactivate PADCTRL1 ++ Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define DEACT_PADCTRL1 0x00100000 ++/* No-Operation ++#define DEACT_PADCTRL1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_PADCTRL1_CLR 0x00100000 ++/** Deactivate P4 ++ Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define DEACT_P4 0x00040000 ++/* No-Operation ++#define DEACT_P4_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P4_CLR 0x00040000 ++/** Deactivate P3 ++ Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define DEACT_P3 0x00020000 ++/* No-Operation ++#define DEACT_P3_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P3_CLR 0x00020000 ++/** Deactivate P1 ++ Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define DEACT_P1 0x00010000 ++/* No-Operation ++#define DEACT_P1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_P1_CLR 0x00010000 ++/** Deactivate HOST ++ Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */ ++#define DEACT_HOST 0x00008000 ++/* No-Operation ++#define DEACT_HOST_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_HOST_CLR 0x00008000 ++/** Deactivate I2C ++ Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */ ++#define DEACT_I2C 0x00004000 ++/* No-Operation ++#define DEACT_I2C_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_I2C_CLR 0x00004000 ++/** Deactivate SSC0 ++ Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define DEACT_SSC0 0x00002000 ++/* No-Operation ++#define DEACT_SSC0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_SSC0_CLR 0x00002000 ++/** Deactivate ASC0 ++ Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define DEACT_ASC0 0x00001000 ++/* No-Operation ++#define DEACT_ASC0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_ASC0_CLR 0x00001000 ++/** Deactivate ASC1 ++ Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ ++#define DEACT_ASC1 0x00000800 ++/* No-Operation ++#define DEACT_ASC1_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_ASC1_CLR 0x00000800 ++/** Deactivate DCDCAPD ++ Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define DEACT_DCDCAPD 0x00000400 ++/* No-Operation ++#define DEACT_DCDCAPD_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDCAPD_CLR 0x00000400 ++/** Deactivate DCDCDDR ++ Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define DEACT_DCDCDDR 0x00000200 ++/* No-Operation ++#define DEACT_DCDCDDR_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDCDDR_CLR 0x00000200 ++/** Deactivate DCDC1V0 ++ Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define DEACT_DCDC1V0 0x00000100 ++/* No-Operation ++#define DEACT_DCDC1V0_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DCDC1V0_CLR 0x00000100 ++/** Deactivate TRC2MEM ++ Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define DEACT_TRC2MEM 0x00000040 ++/* No-Operation ++#define DEACT_TRC2MEM_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_TRC2MEM_CLR 0x00000040 ++/** Deactivate DDR ++ Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */ ++#define DEACT_DDR 0x00000020 ++/* No-Operation ++#define DEACT_DDR_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_DDR_CLR 0x00000020 ++/** Deactivate EBU ++ Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */ ++#define DEACT_EBU 0x00000010 ++/* No-Operation ++#define DEACT_EBU_NOP 0x00000000 */ ++/** Clear */ ++#define DEACT_EBU_CLR 0x00000010 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot STATUS ++ Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */ ++#define RBT_STATUS 0x80000000 ++/* No-Operation ++#define RBT_STATUS_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_STATUS_TRIG 0x80000000 ++/** Reboot SHA1 ++ Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */ ++#define RBT_SHA1 0x40000000 ++/* No-Operation ++#define RBT_SHA1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_SHA1_TRIG 0x40000000 ++/** Reboot AES ++ Triggers a reboot of the AES domain. This domain contains the AES block. */ ++#define RBT_AES 0x20000000 ++/* No-Operation ++#define RBT_AES_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_AES_TRIG 0x20000000 ++/** Reboot PCM ++ Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */ ++#define RBT_PCM 0x10000000 ++/* No-Operation ++#define RBT_PCM_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PCM_TRIG 0x10000000 ++/** Reboot FSCT ++ Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */ ++#define RBT_FSCT 0x08000000 ++/* No-Operation ++#define RBT_FSCT_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_FSCT_TRIG 0x08000000 ++/** Reboot GPTC ++ Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */ ++#define RBT_GPTC 0x04000000 ++/* No-Operation ++#define RBT_GPTC_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_GPTC_TRIG 0x04000000 ++/** Reboot MPS ++ Triggers a reboot of the MPS domain. This domain contains the MPS block. */ ++#define RBT_MPS 0x02000000 ++/* No-Operation ++#define RBT_MPS_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_MPS_TRIG 0x02000000 ++/** Reboot DFEV0 ++ Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */ ++#define RBT_DFEV0 0x01000000 ++/* No-Operation ++#define RBT_DFEV0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DFEV0_TRIG 0x01000000 ++/** Reboot PADCTRL4 ++ Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ ++#define RBT_PADCTRL4 0x00400000 ++/* No-Operation ++#define RBT_PADCTRL4_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL4_TRIG 0x00400000 ++/** Reboot PADCTRL3 ++ Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ ++#define RBT_PADCTRL3 0x00200000 ++/* No-Operation ++#define RBT_PADCTRL3_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL3_TRIG 0x00200000 ++/** Reboot PADCTRL1 ++ Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ ++#define RBT_PADCTRL1 0x00100000 ++/* No-Operation ++#define RBT_PADCTRL1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_PADCTRL1_TRIG 0x00100000 ++/** Reboot P4 ++ Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */ ++#define RBT_P4 0x00040000 ++/* No-Operation ++#define RBT_P4_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P4_TRIG 0x00040000 ++/** Reboot P3 ++ Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */ ++#define RBT_P3 0x00020000 ++/* No-Operation ++#define RBT_P3_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P3_TRIG 0x00020000 ++/** Reboot P1 ++ Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */ ++#define RBT_P1 0x00010000 ++/* No-Operation ++#define RBT_P1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_P1_TRIG 0x00010000 ++/** Reboot HOST ++ Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */ ++#define RBT_HOST 0x00008000 ++/* No-Operation ++#define RBT_HOST_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_HOST_TRIG 0x00008000 ++/** Reboot I2C ++ Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */ ++#define RBT_I2C 0x00004000 ++/* No-Operation ++#define RBT_I2C_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_I2C_TRIG 0x00004000 ++/** Reboot SSC0 ++ Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */ ++#define RBT_SSC0 0x00002000 ++/* No-Operation ++#define RBT_SSC0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_SSC0_TRIG 0x00002000 ++/** Reboot ASC0 ++ Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */ ++#define RBT_ASC0 0x00001000 ++/* No-Operation ++#define RBT_ASC0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_ASC0_TRIG 0x00001000 ++/** Reboot ASC1 ++ Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */ ++#define RBT_ASC1 0x00000800 ++/* No-Operation ++#define RBT_ASC1_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_ASC1_TRIG 0x00000800 ++/** Reboot DCDCAPD ++ Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ ++#define RBT_DCDCAPD 0x00000400 ++/* No-Operation ++#define RBT_DCDCAPD_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDCAPD_TRIG 0x00000400 ++/** Reboot DCDCDDR ++ Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ ++#define RBT_DCDCDDR 0x00000200 ++/* No-Operation ++#define RBT_DCDCDDR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDCDDR_TRIG 0x00000200 ++/** Reboot DCDC1V0 ++ Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ ++#define RBT_DCDC1V0 0x00000100 ++/* No-Operation ++#define RBT_DCDC1V0_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DCDC1V0_TRIG 0x00000100 ++/** Reboot TRC2MEM ++ Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */ ++#define RBT_TRC2MEM 0x00000040 ++/* No-Operation ++#define RBT_TRC2MEM_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_TRC2MEM_TRIG 0x00000040 ++/** Reboot DDR ++ Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */ ++#define RBT_DDR 0x00000020 ++/* No-Operation ++#define RBT_DDR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_DDR_TRIG 0x00000020 ++/** Reboot EBU ++ Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */ ++#define RBT_EBU 0x00000010 ++/* No-Operation ++#define RBT_EBU_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_EBU_TRIG 0x00000010 ++/** Reboot XBAR ++ Triggers a reboot of the XBAR. */ ++#define RBT_XBAR 0x00000002 ++/* No-Operation ++#define RBT_XBAR_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_XBAR_TRIG 0x00000002 ++/** Reboot CPU ++ Triggers a reboot of the CPU. */ ++#define RBT_CPU 0x00000001 ++/* No-Operation ++#define RBT_CPU_NOP 0x00000000 */ ++/** Trigger */ ++#define RBT_CPU_TRIG 0x00000001 ++ ++/* Fields of "CPU0 Clock Control Register" */ ++/** CPU Clock Divider ++ Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */ ++#define CPU0CC_CPUDIV 0x00000001 ++/* Frequency set to the nominal value. ++#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */ ++/** Frequency set to half of its nominal value. */ ++#define CPU0CC_CPUDIV_SELFHALF 0x00000001 ++ ++/* Fields of "CPU0 Reset Source Register" */ ++/** Software Reboot Request Occurred ++ This bit can be acknowledged by a write operation. */ ++#define CPU0RS_SWRRO 0x00000004 ++/* Nothing ++#define CPU0RS_SWRRO_NULL 0x00000000 */ ++/** Write: Acknowledge the event. */ ++#define CPU0RS_SWRRO_EVACK 0x00000004 ++/** Read: Event occurred. */ ++#define CPU0RS_SWRRO_EVOCC 0x00000004 ++/** Hardware Reset Source ++ Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */ ++#define CPU0RS_HWRS_MASK 0x00000003 ++/** field offset */ ++#define CPU0RS_HWRS_OFFSET 0 ++/** Power-on reset. */ ++#define CPU0RS_HWRS_POR 0x00000000 ++/** RST pin. */ ++#define CPU0RS_HWRS_RST 0x00000001 ++/** Watchdog reset request. */ ++#define CPU0RS_HWRS_WDT 0x00000002 ++ ++/* Fields of "CPU0 Wakeup Configuration Register" */ ++/** Wakeup Request Source Yield Resume 15 ++ Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR15 0x80000000 ++/* Not selected ++#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR15_SEL 0x80000000 ++/** Wakeup Request Source Yield Resume 14 ++ Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR14 0x40000000 ++/* Not selected ++#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR14_SEL 0x40000000 ++/** Wakeup Request Source Yield Resume 13 ++ Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR13 0x20000000 ++/* Not selected ++#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR13_SEL 0x20000000 ++/** Wakeup Request Source Yield Resume 12 ++ Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR12 0x10000000 ++/* Not selected ++#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR12_SEL 0x10000000 ++/** Wakeup Request Source Yield Resume 11 ++ Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR11 0x08000000 ++/* Not selected ++#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR11_SEL 0x08000000 ++/** Wakeup Request Source Yield Resume 10 ++ Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR10 0x04000000 ++/* Not selected ++#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR10_SEL 0x04000000 ++/** Wakeup Request Source Yield Resume 9 ++ Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR9 0x02000000 ++/* Not selected ++#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR9_SEL 0x02000000 ++/** Wakeup Request Source Yield Resume 8 ++ Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR8 0x01000000 ++/* Not selected ++#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR8_SEL 0x01000000 ++/** Wakeup Request Source Yield Resume 7 ++ Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR7 0x00800000 ++/* Not selected ++#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR7_SEL 0x00800000 ++/** Wakeup Request Source Yield Resume 6 ++ Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR6 0x00400000 ++/* Not selected ++#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR6_SEL 0x00400000 ++/** Wakeup Request Source Yield Resume 5 ++ Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR5 0x00200000 ++/* Not selected ++#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR5_SEL 0x00200000 ++/** Wakeup Request Source Yield Resume 4 ++ Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR4 0x00100000 ++/* Not selected ++#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR4_SEL 0x00100000 ++/** Wakeup Request Source Yield Resume 3 ++ Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR3 0x00080000 ++/* Not selected ++#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR3_SEL 0x00080000 ++/** Wakeup Request Source Yield Resume 2 ++ Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR2 0x00040000 ++/* Not selected ++#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR2_SEL 0x00040000 ++/** Wakeup Request Source Yield Resume 1 ++ Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR1 0x00020000 ++/* Not selected ++#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR1_SEL 0x00020000 ++/** Wakeup Request Source Yield Resume 0 ++ Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSYR0 0x00010000 ++/* Not selected ++#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSYR0_SEL 0x00010000 ++/** Wakeup Request Source Debug ++ Select signal EJ_DINT as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSDBG 0x00000100 ++/* Not selected ++#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSDBG_SEL 0x00000100 ++/** Wakeup Request Source ICU of VPE1 ++ Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSICUVPE1 0x00000002 ++/* Not selected ++#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002 ++/** Wakeup Request Source ICU of VPE0 ++ Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */ ++#define CPU0WCFG_WRSICUVPE0 0x00000001 ++/* Not selected ++#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */ ++/** Selected */ ++#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001 ++ ++/* Fields of "Bootmode Control Register" */ ++/** Software Bootmode Select ++ Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */ ++#define BMC_BMSW 0x80000000 ++/* Disable ++#define BMC_BMSW_DIS 0x00000000 */ ++/** Enable */ ++#define BMC_BMSW_EN 0x80000000 ++/** Bootmode ++ Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */ ++#define BMC_BM_MASK 0x0000007F ++/** field offset */ ++#define BMC_BM_OFFSET 0 ++ ++/* Fields of "Sleep Configuration Register" */ ++/** Enable XBAR Clockoff When All XBAR masters Clockoff ++ Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */ ++#define SCFG_XBAR 0x00010000 ++/* Disable ++#define SCFG_XBAR_DIS 0x00000000 */ ++/** Enable */ ++#define SCFG_XBAR_EN 0x00010000 ++/** CPU0 Clockoff On Sleep ++ Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */ ++#define SCFG_CPU0 0x00000001 ++/* Disable ++#define SCFG_CPU0_DIS 0x00000000 */ ++/** Enable */ ++#define SCFG_CPU0_EN 0x00000001 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down STATUS ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_STATUS 0x80000000 ++/* Disable ++#define PDCFG_STATUS_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_STATUS_EN 0x80000000 ++/** Enable Power Down SHA1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_SHA1 0x40000000 ++/* Disable ++#define PDCFG_SHA1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_SHA1_EN 0x40000000 ++/** Enable Power Down AES ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_AES 0x20000000 ++/* Disable ++#define PDCFG_AES_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_AES_EN 0x20000000 ++/** Enable Power Down PCM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PCM 0x10000000 ++/* Disable ++#define PDCFG_PCM_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PCM_EN 0x10000000 ++/** Enable Power Down FSCT ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_FSCT 0x08000000 ++/* Disable ++#define PDCFG_FSCT_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_FSCT_EN 0x08000000 ++/** Enable Power Down GPTC ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_GPTC 0x04000000 ++/* Disable ++#define PDCFG_GPTC_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_GPTC_EN 0x04000000 ++/** Enable Power Down MPS ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_MPS 0x02000000 ++/* Disable ++#define PDCFG_MPS_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_MPS_EN 0x02000000 ++/** Enable Power Down DFEV0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DFEV0 0x01000000 ++/* Disable ++#define PDCFG_DFEV0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DFEV0_EN 0x01000000 ++/** Enable Power Down PADCTRL4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL4 0x00400000 ++/* Disable ++#define PDCFG_PADCTRL4_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL4_EN 0x00400000 ++/** Enable Power Down PADCTRL3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL3 0x00200000 ++/* Disable ++#define PDCFG_PADCTRL3_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL3_EN 0x00200000 ++/** Enable Power Down PADCTRL1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_PADCTRL1 0x00100000 ++/* Disable ++#define PDCFG_PADCTRL1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_PADCTRL1_EN 0x00100000 ++/** Enable Power Down P4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P4 0x00040000 ++/* Disable ++#define PDCFG_P4_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P4_EN 0x00040000 ++/** Enable Power Down P3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P3 0x00020000 ++/* Disable ++#define PDCFG_P3_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P3_EN 0x00020000 ++/** Enable Power Down P1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_P1 0x00010000 ++/* Disable ++#define PDCFG_P1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_P1_EN 0x00010000 ++/** Enable Power Down HOST ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_HOST 0x00008000 ++/* Disable ++#define PDCFG_HOST_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_HOST_EN 0x00008000 ++/** Enable Power Down I2C ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_I2C 0x00004000 ++/* Disable ++#define PDCFG_I2C_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_I2C_EN 0x00004000 ++/** Enable Power Down SSC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_SSC0 0x00002000 ++/* Disable ++#define PDCFG_SSC0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_SSC0_EN 0x00002000 ++/** Enable Power Down ASC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_ASC0 0x00001000 ++/* Disable ++#define PDCFG_ASC0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_ASC0_EN 0x00001000 ++/** Enable Power Down ASC1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_ASC1 0x00000800 ++/* Disable ++#define PDCFG_ASC1_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_ASC1_EN 0x00000800 ++/** Enable Power Down DCDCAPD ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDCAPD 0x00000400 ++/* Disable ++#define PDCFG_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDCAPD_EN 0x00000400 ++/** Enable Power Down DCDCDDR ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDCDDR 0x00000200 ++/* Disable ++#define PDCFG_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDCDDR_EN 0x00000200 ++/** Enable Power Down DCDC1V0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DCDC1V0 0x00000100 ++/* Disable ++#define PDCFG_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DCDC1V0_EN 0x00000100 ++/** Enable Power Down TRC2MEM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_TRC2MEM 0x00000040 ++/* Disable ++#define PDCFG_TRC2MEM_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_TRC2MEM_EN 0x00000040 ++/** Enable Power Down DDR ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_DDR 0x00000020 ++/* Disable ++#define PDCFG_DDR_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_DDR_EN 0x00000020 ++/** Enable Power Down EBU ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define PDCFG_EBU 0x00000010 ++/* Disable ++#define PDCFG_EBU_DIS 0x00000000 */ ++/** Enable */ ++#define PDCFG_EBU_EN 0x00000010 ++ ++/* Fields of "CLKO Pad Control Register" */ ++/** Ethernet Reference Clock CLKO Select ++ Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */ ++#define CLKOC_ETHREF 0x00000002 ++/* Not selected ++#define CLKOC_ETHREF_NSEL 0x00000000 */ ++/** Selected */ ++#define CLKOC_ETHREF_SEL 0x00000002 ++/** Output Enable ++ Enables the output driver of the CLKO pad. */ ++#define CLKOC_OEN 0x00000001 ++/* Disable ++#define CLKOC_OEN_DIS 0x00000000 */ ++/** Enable */ ++#define CLKOC_OEN_EN 0x00000001 ++ ++/* Fields of "Infrastructure Control Register" */ ++/** General Purpose Control ++ Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */ ++#define INFRAC_GP_MASK 0x1F000000 ++/** field offset */ ++#define INFRAC_GP_OFFSET 24 ++/** CMOS2CML Ethernet Control ++ CMOS2CML Ethernet Control. */ ++#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000 ++/** field offset */ ++#define INFRAC_CMOS2CML_GPON_OFFSET 12 ++/** CMOS2CML Ethernet Control ++ CMOS2CML Ethernet Control. */ ++#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00 ++/** field offset */ ++#define INFRAC_CMOS2CML_ETH_OFFSET 8 ++/** Dying Gasp Enable ++ Enables the dying gasp detector. */ ++#define INFRAC_DGASPEN 0x00000040 ++/* Disable ++#define INFRAC_DGASPEN_DIS 0x00000000 */ ++/** Enable */ ++#define INFRAC_DGASPEN_EN 0x00000040 ++/** Dying Gasp Hysteresis Control ++ Dying Gasp Hysteresis Control. */ ++#define INFRAC_DGASPHYS_MASK 0x00000030 ++/** field offset */ ++#define INFRAC_DGASPHYS_OFFSET 4 ++/** Linear Regulator 1.5V Enable ++ Enables 1.5V linear regulator. */ ++#define INFRAC_LIN1V5EN 0x00000008 ++/* Disable ++#define INFRAC_LIN1V5EN_DIS 0x00000000 */ ++/** Enable */ ++#define INFRAC_LIN1V5EN_EN 0x00000008 ++/** Linear Regulator 1.5V Control ++ Linear regulator 1.5V control. */ ++#define INFRAC_LIN1V5C_MASK 0x00000007 ++/** field offset */ ++#define INFRAC_LIN1V5C_OFFSET 0 ++ ++/* Fields of "HRST_OUT_N Control Register" */ ++/** HRST_OUT_N Pin Value ++ Controls the value of the HRST_OUT_N pin. */ ++#define HRSTOUTC_VALUE 0x00000001 ++ ++/* Fields of "EBU Clock Control Register" */ ++/** EBU Clock Divider ++ Via this bit the frequency of the clock of the EBU can be selected. */ ++#define EBUCC_EBUDIV 0x00000001 ++/* Frequency set to 50MHz. ++#define EBUCC_EBUDIV_SELF50 0x00000000 */ ++/** Frequency set to 100MHz. */ ++#define EBUCC_EBUDIV_SELF100 0x00000001 ++ ++/* Fields of "NMI Status Register" */ ++/** NMI Status Flag TEST ++ Shows whether the event NMI TEST occurred. */ ++#define NMIS_TEST 0x00000100 ++/* Nothing ++#define NMIS_TEST_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_TEST_EVOCC 0x00000100 ++/** NMI Status Flag DGASP ++ Shows whether the event NMI DGASP occurred. */ ++#define NMIS_DGASP 0x00000004 ++/* Nothing ++#define NMIS_DGASP_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_DGASP_EVOCC 0x00000004 ++/** NMI Status Flag HOST ++ Shows whether the event NMI HOST occurred. */ ++#define NMIS_HOST 0x00000002 ++/* Nothing ++#define NMIS_HOST_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_HOST_EVOCC 0x00000002 ++/** NMI Status Flag PIN ++ Shows whether the event NMI PIN occurred. */ ++#define NMIS_PIN 0x00000001 ++/* Nothing ++#define NMIS_PIN_NULL 0x00000000 */ ++/** Read: Event occurred. */ ++#define NMIS_PIN_EVOCC 0x00000001 ++ ++/* Fields of "NMI Set Register" */ ++/** Set NMI Status Flag TEST ++ Sets the corresponding NMI status flag. */ ++#define NMISET_TEST 0x00000100 ++/* Nothing ++#define NMISET_TEST_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_TEST_SET 0x00000100 ++/** Set NMI Status Flag DGASP ++ Sets the corresponding NMI status flag. */ ++#define NMISET_DGASP 0x00000004 ++/* Nothing ++#define NMISET_DGASP_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_DGASP_SET 0x00000004 ++/** Set NMI Status Flag HOST ++ Sets the corresponding NMI status flag. */ ++#define NMISET_HOST 0x00000002 ++/* Nothing ++#define NMISET_HOST_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_HOST_SET 0x00000002 ++/** Set NMI Status Flag PIN ++ Sets the corresponding NMI status flag. */ ++#define NMISET_PIN 0x00000001 ++/* Nothing ++#define NMISET_PIN_NULL 0x00000000 */ ++/** Set */ ++#define NMISET_PIN_SET 0x00000001 ++ ++/* Fields of "NMI Clear Register" */ ++/** Clear NMI Status Flag TEST ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_TEST 0x00000100 ++/* Nothing ++#define NMICLR_TEST_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_TEST_CLR 0x00000100 ++/** Clear NMI Status Flag DGASP ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_DGASP 0x00000004 ++/* Nothing ++#define NMICLR_DGASP_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_DGASP_CLR 0x00000004 ++/** Clear NMI Status Flag HOST ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_HOST 0x00000002 ++/* Nothing ++#define NMICLR_HOST_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_HOST_CLR 0x00000002 ++/** Clear NMI Status Flag PIN ++ Clears the corresponding NMI status flag. */ ++#define NMICLR_PIN 0x00000001 ++/* Nothing ++#define NMICLR_PIN_NULL 0x00000000 */ ++/** Clear */ ++#define NMICLR_PIN_CLR 0x00000001 ++ ++/* Fields of "NMI Test Configuration Register" */ ++/** Enable NMI Test Feature ++ Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */ ++#define NMITCFG_TEN 0x00000100 ++/* Disable ++#define NMITCFG_TEN_DIS 0x00000000 */ ++/** Enable */ ++#define NMITCFG_TEN_EN 0x00000100 ++ ++/* Fields of "NMI VPE1 Control Register" */ ++/** NMI VPE1 State ++ Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */ ++#define NMIVPE1C_NMI 0x00000001 ++/* False ++#define NMIVPE1C_NMI_FALSE 0x00000000 */ ++/** True */ ++#define NMIVPE1C_NMI_TRUE 0x00000001 ++ ++/* Fields of "IRN Capture Register" */ ++/** DCDCAPD Alarm ++ The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDCAPD 0x00400000 ++/* Nothing ++#define IRNCR_DCDCAPD_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDCAPD_INTACK 0x00400000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDCAPD_INTOCC 0x00400000 ++/** DCDCDDR Alarm ++ The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDCDDR 0x00200000 ++/* Nothing ++#define IRNCR_DCDCDDR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDCDDR_INTACK 0x00200000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDCDDR_INTOCC 0x00200000 ++/** DCDC1V0 Alarm ++ The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_DCDC1V0 0x00100000 ++/* Nothing ++#define IRNCR_DCDC1V0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_DCDC1V0_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_DCDC1V0_INTOCC 0x00100000 ++/** SIF0 wakeup request ++ SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define IRNCR_SIF0 0x00010000 ++/* Nothing ++#define IRNCR_SIF0_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define IRNCR_SIF0_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define IRNCR_SIF0_INTOCC 0x00010000 ++ ++/* Fields of "IRN Interrupt Control Register" */ ++/** DCDCAPD Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDCAPD 0x00400000 ++/** DCDCDDR Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDCDDR 0x00200000 ++/** DCDC1V0 Alarm ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_DCDC1V0 0x00100000 ++/** SIF0 wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCR register. */ ++#define IRNICR_SIF0 0x00010000 ++ ++/* Fields of "IRN Interrupt Enable Register" */ ++/** DCDCAPD Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDCAPD 0x00400000 ++/* Disable ++#define IRNEN_DCDCAPD_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDCAPD_EN 0x00400000 ++/** DCDCDDR Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDCDDR 0x00200000 ++/* Disable ++#define IRNEN_DCDCDDR_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDCDDR_EN 0x00200000 ++/** DCDC1V0 Alarm ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_DCDC1V0 0x00100000 ++/* Disable ++#define IRNEN_DCDC1V0_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_DCDC1V0_EN 0x00100000 ++/** SIF0 wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCR register. */ ++#define IRNEN_SIF0 0x00010000 ++/* Disable ++#define IRNEN_SIF0_DIS 0x00000000 */ ++/** Enable */ ++#define IRNEN_SIF0_EN 0x00010000 ++ ++/*! @} */ /* SYS1_REGISTER */ ++ ++#endif /* _sys1_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h +@@ -0,0 +1,1132 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys_eth_reg_h ++#define _sys_eth_reg_h ++ ++/** \addtogroup SYS_ETH_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys_eth_r32(reg) reg_r32(&sys_eth->reg) ++#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg) ++#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg) ++#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx) ++#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx) ++#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx) ++#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx) ++ ++ ++/** SYS_ETH register structure */ ++struct gpon_reg_sys_eth ++{ ++ /** Clock Status Register */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[32]; /* 0x00000030 */ ++ /** External PHY Control Register */ ++ unsigned int extphyc; /* 0x000000B0 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** Datarate Control Register ++ Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */ ++ unsigned int drc; /* 0x000000B8 */ ++ /** GMAC Multiplexer Control Register ++ Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */ ++ unsigned int gmuxc; /* 0x000000BC */ ++ /** Datarate Status Register ++ Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */ ++ unsigned int drs; /* 0x000000C0 */ ++ /** SGMII Control Register */ ++ unsigned int sgmiic; /* 0x000000C4 */ ++ /** Reserved */ ++ unsigned int res_2[14]; /* 0x000000C8 */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** GPHY1MII2 Clock Enable ++ Shows the clock enable bit for GPHY1MII2. */ ++#define SYS_ETH_CLKS_GPHY1MII2 0x02000000 ++/* Disable ++#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000 ++/** GPHY0MII2 Clock Enable ++ Shows the clock enable bit for GPHY0MII2. */ ++#define SYS_ETH_CLKS_GPHY0MII2 0x01000000 ++/* Disable ++#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000 ++/** PADCTRL2 Clock Enable ++ Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKS_PADCTRL2 0x00200000 ++/* Disable ++#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000 ++/** PADCTRL0 Clock Enable ++ Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKS_PADCTRL0 0x00100000 ++/* Disable ++#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000 ++/** P2 Clock Enable ++ Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKS_P2 0x00020000 ++/* Disable ++#define SYS_ETH_CLKS_P2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_P2_EN 0x00020000 ++/** P0 Clock Enable ++ Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKS_P0 0x00010000 ++/* Disable ++#define SYS_ETH_CLKS_P0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_P0_EN 0x00010000 ++/** xMII Clock Enable ++ Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKS_xMII 0x00000800 ++/* Disable ++#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_xMII_EN 0x00000800 ++/** SGMII Clock Enable ++ Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_SGMII 0x00000400 ++/* Disable ++#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_SGMII_EN 0x00000400 ++/** GPHY1 Clock Enable ++ Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_GPHY1 0x00000200 ++/* Disable ++#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY1_EN 0x00000200 ++/** GPHY0 Clock Enable ++ Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKS_GPHY0 0x00000100 ++/* Disable ++#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GPHY0_EN 0x00000100 ++/** MDIO Clock Enable ++ Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKS_MDIO 0x00000080 ++/* Disable ++#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_MDIO_EN 0x00000080 ++/** GMAC3 Clock Enable ++ Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKS_GMAC3 0x00000008 ++/* Disable ++#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC3_EN 0x00000008 ++/** GMAC2 Clock Enable ++ Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKS_GMAC2 0x00000004 ++/* Disable ++#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC2_EN 0x00000004 ++/** GMAC1 Clock Enable ++ Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKS_GMAC1 0x00000002 ++/* Disable ++#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC1_EN 0x00000002 ++/** GMAC0 Clock Enable ++ Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKS_GMAC0 0x00000001 ++/* Disable ++#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_CLKS_GMAC0_EN 0x00000001 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable GPHY1MII2 ++ Sets the clock enable bit of the GPHY1MII2. */ ++#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000 ++/** Set Clock Enable GPHY0MII2 ++ Sets the clock enable bit of the GPHY0MII2. */ ++#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000 ++/** Set Clock Enable PADCTRL2 ++ Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKEN_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000 ++/** Set Clock Enable PADCTRL0 ++ Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKEN_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000 ++/** Set Clock Enable P2 ++ Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKEN_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_P2_SET 0x00020000 ++/** Set Clock Enable P0 ++ Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKEN_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_P0_SET 0x00010000 ++/** Set Clock Enable xMII ++ Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKEN_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_xMII_SET 0x00000800 ++/** Set Clock Enable SGMII ++ Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_SGMII_SET 0x00000400 ++/** Set Clock Enable GPHY1 ++ Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200 ++/** Set Clock Enable GPHY0 ++ Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKEN_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100 ++/** Set Clock Enable MDIO ++ Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKEN_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_MDIO_SET 0x00000080 ++/** Set Clock Enable GMAC3 ++ Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKEN_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008 ++/** Set Clock Enable GMAC2 ++ Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKEN_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004 ++/** Set Clock Enable GMAC1 ++ Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKEN_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002 ++/** Set Clock Enable GMAC0 ++ Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKEN_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable GPHY1MII2 ++ Clears the clock enable bit of the GPHY1MII2. */ ++#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000 ++/** Clear Clock Enable GPHY0MII2 ++ Clears the clock enable bit of the GPHY0MII2. */ ++#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000 ++/** Clear Clock Enable PADCTRL2 ++ Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000 ++/** Clear Clock Enable PADCTRL0 ++ Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000 ++/** Clear Clock Enable P2 ++ Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_CLKCLR_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_P2_CLR 0x00020000 ++/** Clear Clock Enable P0 ++ Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_CLKCLR_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_P0_CLR 0x00010000 ++/** Clear Clock Enable xMII ++ Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_CLKCLR_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800 ++/** Clear Clock Enable SGMII ++ Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400 ++/** Clear Clock Enable GPHY1 ++ Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200 ++/** Clear Clock Enable GPHY0 ++ Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_CLKCLR_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100 ++/** Clear Clock Enable MDIO ++ Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_CLKCLR_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080 ++/** Clear Clock Enable GMAC3 ++ Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_CLKCLR_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008 ++/** Clear Clock Enable GMAC2 ++ Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_CLKCLR_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004 ++/** Clear Clock Enable GMAC1 ++ Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_CLKCLR_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002 ++/** Clear Clock Enable GMAC0 ++ Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_CLKCLR_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001 ++ ++/* Fields of "Activation Status Register" */ ++/** PADCTRL2 Status ++ Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_ACTS_PADCTRL2 0x00200000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000 ++/** PADCTRL0 Status ++ Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_ACTS_PADCTRL0 0x00100000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000 ++/** P2 Status ++ Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_ACTS_P2 0x00020000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_P2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_P2_ACT 0x00020000 ++/** P0 Status ++ Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_ACTS_P0 0x00010000 ++/* The block is inactive. ++#define SYS_ETH_ACTS_P0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_P0_ACT 0x00010000 ++/** xMII Status ++ Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_ACTS_xMII 0x00000800 ++/* The block is inactive. ++#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_xMII_ACT 0x00000800 ++/** SGMII Status ++ Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_SGMII 0x00000400 ++/* The block is inactive. ++#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_SGMII_ACT 0x00000400 ++/** GPHY1 Status ++ Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_GPHY1 0x00000200 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200 ++/** GPHY0 Status ++ Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACTS_GPHY0 0x00000100 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100 ++/** MDIO Status ++ Shows the activation status of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_ACTS_MDIO 0x00000080 ++/* The block is inactive. ++#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_MDIO_ACT 0x00000080 ++/** GMAC3 Status ++ Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_ACTS_GMAC3 0x00000008 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008 ++/** GMAC2 Status ++ Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_ACTS_GMAC2 0x00000004 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004 ++/** GMAC1 Status ++ Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_ACTS_GMAC1 0x00000002 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002 ++/** GMAC0 Status ++ Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_ACTS_GMAC0 0x00000001 ++/* The block is inactive. ++#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001 ++ ++/* Fields of "Activation Register" */ ++/** Activate PADCTRL2 ++ Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_ACT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000 ++/** Activate PADCTRL0 ++ Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_ACT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000 ++/** Activate P2 ++ Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_ACT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_ACT_P2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_P2_SET 0x00020000 ++/** Activate P0 ++ Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_ACT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_ACT_P0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_P0_SET 0x00010000 ++/** Activate xMII ++ Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_ACT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_ACT_xMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_xMII_SET 0x00000800 ++/** Activate SGMII ++ Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_SGMII_SET 0x00000400 ++/** Activate GPHY1 ++ Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GPHY1_SET 0x00000200 ++/** Activate GPHY0 ++ Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_ACT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GPHY0_SET 0x00000100 ++/** Activate MDIO ++ Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_ACT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_MDIO_SET 0x00000080 ++/** Activate GMAC3 ++ Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_ACT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC3_SET 0x00000008 ++/** Activate GMAC2 ++ Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_ACT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC2_SET 0x00000004 ++/** Activate GMAC1 ++ Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_ACT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC1_SET 0x00000002 ++/** Activate GMAC0 ++ Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_ACT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_ETH_ACT_GMAC0_SET 0x00000001 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate PADCTRL2 ++ Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_DEACT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000 ++/** Deactivate PADCTRL0 ++ Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_DEACT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000 ++/** Deactivate P2 ++ Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_DEACT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_DEACT_P2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_P2_CLR 0x00020000 ++/** Deactivate P0 ++ Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_DEACT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_DEACT_P0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_P0_CLR 0x00010000 ++/** Deactivate xMII ++ Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_DEACT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_xMII_CLR 0x00000800 ++/** Deactivate SGMII ++ Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_SGMII_CLR 0x00000400 ++/** Deactivate GPHY1 ++ Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200 ++/** Deactivate GPHY0 ++ Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_DEACT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100 ++/** Deactivate MDIO ++ Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_DEACT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_MDIO_CLR 0x00000080 ++/** Deactivate GMAC3 ++ Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_DEACT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008 ++/** Deactivate GMAC2 ++ Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_DEACT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004 ++/** Deactivate GMAC1 ++ Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_DEACT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002 ++/** Deactivate GMAC0 ++ Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_DEACT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot PADCTRL2 ++ Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ ++#define SYS_ETH_RBT_PADCTRL2 0x00200000 ++/* No-Operation ++#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000 ++/** Reboot PADCTRL0 ++ Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ ++#define SYS_ETH_RBT_PADCTRL0 0x00100000 ++/* No-Operation ++#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000 ++/** Reboot P2 ++ Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */ ++#define SYS_ETH_RBT_P2 0x00020000 ++/* No-Operation ++#define SYS_ETH_RBT_P2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_P2_TRIG 0x00020000 ++/** Reboot P0 ++ Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */ ++#define SYS_ETH_RBT_P0 0x00010000 ++/* No-Operation ++#define SYS_ETH_RBT_P0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_P0_TRIG 0x00010000 ++/** Reboot xMII ++ Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ ++#define SYS_ETH_RBT_xMII 0x00000800 ++/* No-Operation ++#define SYS_ETH_RBT_xMII_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_xMII_TRIG 0x00000800 ++/** Reboot SGMII ++ Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_SGMII 0x00000400 ++/* No-Operation ++#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_SGMII_TRIG 0x00000400 ++/** Reboot GPHY1 ++ Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_GPHY1 0x00000200 ++/* No-Operation ++#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200 ++/** Reboot GPHY0 ++ Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ ++#define SYS_ETH_RBT_GPHY0 0x00000100 ++/* No-Operation ++#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100 ++/** Reboot MDIO ++ Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */ ++#define SYS_ETH_RBT_MDIO 0x00000080 ++/* No-Operation ++#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_MDIO_TRIG 0x00000080 ++/** Reboot GMAC3 ++ Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */ ++#define SYS_ETH_RBT_GMAC3 0x00000008 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008 ++/** Reboot GMAC2 ++ Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */ ++#define SYS_ETH_RBT_GMAC2 0x00000004 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004 ++/** Reboot GMAC1 ++ Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */ ++#define SYS_ETH_RBT_GMAC1 0x00000002 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002 ++/** Reboot GMAC0 ++ Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */ ++#define SYS_ETH_RBT_GMAC0 0x00000001 ++/* No-Operation ++#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001 ++ ++/* Fields of "External PHY Control Register" */ ++/** PHY_CLKO Output Enable ++ Enables the output driver of the PHY_CLKO pin. */ ++#define SYS_ETH_EXTPHYC_CLKEN 0x80000000 ++/* Disable ++#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000 ++/** PHY_CLKO Frequency Select ++ Selects the frequency of the PHY_CLKO pin. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0 ++/** 25 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001 ++/** 125 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002 ++/** 50 MHz. */ ++#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down PADCTRL2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_PADCTRL2 0x00200000 ++/* Disable ++#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000 ++/** Enable Power Down PADCTRL0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_PADCTRL0 0x00100000 ++/* Disable ++#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000 ++/** Enable Power Down P2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_P2 0x00020000 ++/* Disable ++#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_P2_EN 0x00020000 ++/** Enable Power Down P0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_P0 0x00010000 ++/* Disable ++#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_P0_EN 0x00010000 ++/** Enable Power Down xMII ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_xMII 0x00000800 ++/* Disable ++#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_xMII_EN 0x00000800 ++/** Enable Power Down SGMII ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_SGMII 0x00000400 ++/* Disable ++#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_SGMII_EN 0x00000400 ++/** Enable Power Down GPHY1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GPHY1 0x00000200 ++/* Disable ++#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200 ++/** Enable Power Down GPHY0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GPHY0 0x00000100 ++/* Disable ++#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100 ++/** Enable Power Down MDIO ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_MDIO 0x00000080 ++/* Disable ++#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_MDIO_EN 0x00000080 ++/** Enable Power Down GMAC3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC3 0x00000008 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008 ++/** Enable Power Down GMAC2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC2 0x00000004 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004 ++/** Enable Power Down GMAC1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC1 0x00000002 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002 ++/** Enable Power Down GMAC0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_ETH_PDCFG_GMAC0 0x00000001 ++/* Disable ++#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001 ++ ++/* Fields of "Datarate Control Register" */ ++/** MDC Clockrate ++ Selects the clockrate of the MDIO interface. */ ++#define SYS_ETH_DRC_MDC_MASK 0x30000000 ++/** field offset */ ++#define SYS_ETH_DRC_MDC_OFFSET 28 ++/** 312.5/128 = appr. 2.44 MHz. */ ++#define SYS_ETH_DRC_MDC_F2M44 0x00000000 ++/** 312.5/64 = appr. 4.88 MHz. */ ++#define SYS_ETH_DRC_MDC_F4M88 0x10000000 ++/** 312.5/32 = appr. 9.77 MHz. */ ++#define SYS_ETH_DRC_MDC_F9M77 0x20000000 ++/** 312.5/16 = appr. 19.5 MHz. */ ++#define SYS_ETH_DRC_MDC_F19M5 0x30000000 ++/** xMII1 Datarate ++ Selects the datarate of the xMII1 interface. */ ++#define SYS_ETH_DRC_xMII1_MASK 0x07000000 ++/** field offset */ ++#define SYS_ETH_DRC_xMII1_OFFSET 24 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR100 0x01000000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR1000 0x02000000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRC_xMII1_DR200 0x05000000 ++/** xMII0 Datarate ++ Selects the datarate of the xMII0 interface. */ ++#define SYS_ETH_DRC_xMII0_MASK 0x00700000 ++/** field offset */ ++#define SYS_ETH_DRC_xMII0_OFFSET 20 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR100 0x00100000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR1000 0x00200000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRC_xMII0_DR200 0x00500000 ++/** SGMII Datarate ++ Selects the datarate of the SGMII interface. */ ++#define SYS_ETH_DRC_SGMII_MASK 0x00070000 ++/** field offset */ ++#define SYS_ETH_DRC_SGMII_OFFSET 16 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR100 0x00010000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR1000 0x00020000 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRC_SGMII_DR2500 0x00040000 ++/** GPHY1_MII2 Datarate ++ Shows the datarate of the GPHY1_MII2 interface. */ ++#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000 ++/** GPHY1_GMII Datarate ++ Shows the datarate of the GPHY1_GMII interface. */ ++#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200 ++/** GPHY0_MII2 Datarate ++ Shows the datarate of the GPHY0_MII2 interface. */ ++#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010 ++/** GPHY0_GMII Datarate ++ Shows the datarate of the GPHY0_GMII interface. */ ++#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002 ++ ++/* Fields of "GMAC Multiplexer Control Register" */ ++/** GMAC 3 MUX setting ++ Selects the physical layer to be connected to GMAC3 */ ++#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC3_OFFSET 12 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000 ++/** GMAC 2 MUX setting ++ Selects the physical layer to be connected to GMAC2 */ ++#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC2_OFFSET 8 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600 ++/** GMAC 1 MUX setting ++ Selects the physical layer to be connected to GMAC1 */ ++#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC1_OFFSET 4 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060 ++/** GMAC 0 MUX setting ++ Selects the physical layer to be connected to GMAC0 */ ++#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_GMUXC_GMAC0_OFFSET 0 ++/** GMAC connects to GPHY0_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000 ++/** GMAC connects to GPHY0_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001 ++/** GMAC connects to GPHY1_GMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002 ++/** GMAC connects to GPHY1_MII2 interface */ ++#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003 ++/** GMAC connects to SGMII interface */ ++#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004 ++/** GMAC connects to xMII0 interface */ ++#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005 ++/** GMAC connects to xMII1 interface */ ++#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006 ++ ++/* Fields of "Datarate Status Register" */ ++/** GMAC 3 datarate ++ Shows the datarate of GMAC3 */ ++#define SYS_ETH_DRS_GMAC3_MASK 0x00007000 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC3_OFFSET 12 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR100 0x00001000 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC3_DR200 0x00005000 ++/** GMAC 2 datarate ++ Shows the datarate of GMAC2 */ ++#define SYS_ETH_DRS_GMAC2_MASK 0x00000700 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC2_OFFSET 8 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR100 0x00000100 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC2_DR200 0x00000500 ++/** GMAC 1 datarate ++ Shows the datarate of GMAC1 */ ++#define SYS_ETH_DRS_GMAC1_MASK 0x00000070 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC1_OFFSET 4 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR100 0x00000010 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC1_DR200 0x00000050 ++/** GMAC 0 datarate ++ Shows the datarate of GMAC0 */ ++#define SYS_ETH_DRS_GMAC0_MASK 0x00000007 ++/** field offset */ ++#define SYS_ETH_DRS_GMAC0_OFFSET 0 ++/** 10 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR10 0x00000000 ++/** 100 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR100 0x00000001 ++/** 1000 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002 ++/** 2500 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004 ++/** 200 MBit/s. */ ++#define SYS_ETH_DRS_GMAC0_DR200 0x00000005 ++ ++/* Fields of "SGMII Control Register" */ ++/** Auto Negotiation Protocol ++ Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */ ++#define SYS_ETH_SGMIIC_ANP 0x00000002 ++/* TBX Mode (IEEE 802.3 Clause 37 ANEG) ++#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */ ++/** SGMII Mode (Cisco Aneg) */ ++#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002 ++/** Auto Negotiation MAC/PHY ++ Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */ ++#define SYS_ETH_SGMIIC_ANMP 0x00000001 ++/* MAC Mode ++#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */ ++/** PHY Mode */ ++#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001 ++ ++/*! @} */ /* SYS_ETH_REGISTER */ ++ ++#endif /* _sys_eth_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h +@@ -0,0 +1,2829 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _sys_gpe_reg_h ++#define _sys_gpe_reg_h ++ ++/** \addtogroup SYS_GPE_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg) ++#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg) ++#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg) ++#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx) ++#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx) ++#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx) ++#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx) ++ ++ ++/** SYS_GPE register structure */ ++struct gpon_reg_sys_gpe ++{ ++ /** Clock Status Register ++ The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */ ++ unsigned int clks; /* 0x00000000 */ ++ /** Clock Enable Register ++ Via this register the clocks for the domains can be enabled. */ ++ unsigned int clken; /* 0x00000004 */ ++ /** Clock Clear Register ++ Via this register the clocks for the domains can be disabled. */ ++ unsigned int clkclr; /* 0x00000008 */ ++ /** Reserved */ ++ unsigned int res_0[5]; /* 0x0000000C */ ++ /** Activation Status Register */ ++ unsigned int acts; /* 0x00000020 */ ++ /** Activation Register ++ Via this register the domains can be activated. */ ++ unsigned int act; /* 0x00000024 */ ++ /** Deactivation Register ++ Via this register the domains can be deactivated. */ ++ unsigned int deact; /* 0x00000028 */ ++ /** Reboot Trigger Register ++ Via this register the domains can be rebooted (sent through reset). */ ++ unsigned int rbt; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[33]; /* 0x00000030 */ ++ /** Power Down Configuration Register ++ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ ++ unsigned int pdcfg; /* 0x000000B4 */ ++ /** Sleep Source Configuration Register ++ All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */ ++ unsigned int sscfg; /* 0x000000B8 */ ++ /** Sleep Source Timer Register */ ++ unsigned int sst; /* 0x000000BC */ ++ /** Sleep Destination Status Register ++ Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */ ++ unsigned int sds; /* 0x000000C0 */ ++ /** Sleep Destination Set Register ++ Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */ ++ unsigned int sdset; /* 0x000000C4 */ ++ /** Sleep Destination Clear Register ++ Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */ ++ unsigned int sdclr; /* 0x000000C8 */ ++ /** Reserved */ ++ unsigned int res_2[9]; /* 0x000000CC */ ++ /** IRNCS Capture Register ++ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */ ++ unsigned int irncscr; /* 0x000000F0 */ ++ /** IRNCS Interrupt Control Register ++ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ ++ unsigned int irncsicr; /* 0x000000F4 */ ++ /** IRNCS Interrupt Enable Register ++ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */ ++ unsigned int irncsen; /* 0x000000F8 */ ++ /** Reserved */ ++ unsigned int res_3; /* 0x000000FC */ ++}; ++ ++ ++/* Fields of "Clock Status Register" */ ++/** COP7 Clock Enable ++ Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKS_COP7 0x80000000 ++/* Disable ++#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP7_EN 0x80000000 ++/** COP6 Clock Enable ++ Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKS_COP6 0x40000000 ++/* Disable ++#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP6_EN 0x40000000 ++/** COP5 Clock Enable ++ Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKS_COP5 0x20000000 ++/* Disable ++#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP5_EN 0x20000000 ++/** COP4 Clock Enable ++ Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKS_COP4 0x10000000 ++/* Disable ++#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP4_EN 0x10000000 ++/** COP3 Clock Enable ++ Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKS_COP3 0x08000000 ++/* Disable ++#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP3_EN 0x08000000 ++/** COP2 Clock Enable ++ Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKS_COP2 0x04000000 ++/* Disable ++#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP2_EN 0x04000000 ++/** COP1 Clock Enable ++ Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKS_COP1 0x02000000 ++/* Disable ++#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP1_EN 0x02000000 ++/** COP0 Clock Enable ++ Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKS_COP0 0x01000000 ++/* Disable ++#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_COP0_EN 0x01000000 ++/** PE5 Clock Enable ++ Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKS_PE5 0x00200000 ++/* Disable ++#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE5_EN 0x00200000 ++/** PE4 Clock Enable ++ Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKS_PE4 0x00100000 ++/* Disable ++#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE4_EN 0x00100000 ++/** PE3 Clock Enable ++ Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKS_PE3 0x00080000 ++/* Disable ++#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE3_EN 0x00080000 ++/** PE2 Clock Enable ++ Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKS_PE2 0x00040000 ++/* Disable ++#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE2_EN 0x00040000 ++/** PE1 Clock Enable ++ Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKS_PE1 0x00020000 ++/* Disable ++#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE1_EN 0x00020000 ++/** PE0 Clock Enable ++ Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKS_PE0 0x00010000 ++/* Disable ++#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_PE0_EN 0x00010000 ++/** ARB Clock Enable ++ Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKS_ARB 0x00002000 ++/* Disable ++#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_ARB_EN 0x00002000 ++/** FSQM Clock Enable ++ Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKS_FSQM 0x00001000 ++/* Disable ++#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_FSQM_EN 0x00001000 ++/** TMU Clock Enable ++ Shows the clock enable bit for the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKS_TMU 0x00000800 ++/* Disable ++#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_TMU_EN 0x00000800 ++/** MRG Clock Enable ++ Shows the clock enable bit for the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKS_MRG 0x00000400 ++/* Disable ++#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_MRG_EN 0x00000400 ++/** DISP Clock Enable ++ Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKS_DISP 0x00000200 ++/* Disable ++#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_DISP_EN 0x00000200 ++/** IQM Clock Enable ++ Shows the clock enable bit for the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKS_IQM 0x00000100 ++/* Disable ++#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_IQM_EN 0x00000100 ++/** CPUE Clock Enable ++ Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKS_CPUE 0x00000080 ++/* Disable ++#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_CPUE_EN 0x00000080 ++/** CPUI Clock Enable ++ Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKS_CPUI 0x00000040 ++/* Disable ++#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_CPUI_EN 0x00000040 ++/** GPONE Clock Enable ++ Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKS_GPONE 0x00000020 ++/* Disable ++#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_GPONE_EN 0x00000020 ++/** GPONI Clock Enable ++ Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKS_GPONI 0x00000010 ++/* Disable ++#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_GPONI_EN 0x00000010 ++/** LAN3 Clock Enable ++ Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKS_LAN3 0x00000008 ++/* Disable ++#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN3_EN 0x00000008 ++/** LAN2 Clock Enable ++ Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKS_LAN2 0x00000004 ++/* Disable ++#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN2_EN 0x00000004 ++/** LAN1 Clock Enable ++ Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKS_LAN1 0x00000002 ++/* Disable ++#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN1_EN 0x00000002 ++/** LAN0 Clock Enable ++ Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKS_LAN0 0x00000001 ++/* Disable ++#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_CLKS_LAN0_EN 0x00000001 ++ ++/* Fields of "Clock Enable Register" */ ++/** Set Clock Enable COP7 ++ Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKEN_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP7_SET 0x80000000 ++/** Set Clock Enable COP6 ++ Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKEN_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP6_SET 0x40000000 ++/** Set Clock Enable COP5 ++ Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKEN_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP5_SET 0x20000000 ++/** Set Clock Enable COP4 ++ Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKEN_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP4_SET 0x10000000 ++/** Set Clock Enable COP3 ++ Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKEN_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP3_SET 0x08000000 ++/** Set Clock Enable COP2 ++ Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKEN_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP2_SET 0x04000000 ++/** Set Clock Enable COP1 ++ Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKEN_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP1_SET 0x02000000 ++/** Set Clock Enable COP0 ++ Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKEN_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_COP0_SET 0x01000000 ++/** Set Clock Enable PE5 ++ Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKEN_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE5_SET 0x00200000 ++/** Set Clock Enable PE4 ++ Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKEN_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE4_SET 0x00100000 ++/** Set Clock Enable PE3 ++ Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKEN_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE3_SET 0x00080000 ++/** Set Clock Enable PE2 ++ Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKEN_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE2_SET 0x00040000 ++/** Set Clock Enable PE1 ++ Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKEN_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE1_SET 0x00020000 ++/** Set Clock Enable PE0 ++ Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKEN_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_PE0_SET 0x00010000 ++/** Set Clock Enable ARB ++ Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKEN_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_ARB_SET 0x00002000 ++/** Set Clock Enable FSQM ++ Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKEN_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_FSQM_SET 0x00001000 ++/** Set Clock Enable TMU ++ Sets the clock enable bit of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKEN_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_TMU_SET 0x00000800 ++/** Set Clock Enable MRG ++ Sets the clock enable bit of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKEN_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_MRG_SET 0x00000400 ++/** Set Clock Enable DISP ++ Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKEN_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_DISP_SET 0x00000200 ++/** Set Clock Enable IQM ++ Sets the clock enable bit of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKEN_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_IQM_SET 0x00000100 ++/** Set Clock Enable CPUE ++ Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKEN_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_CPUE_SET 0x00000080 ++/** Set Clock Enable CPUI ++ Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKEN_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_CPUI_SET 0x00000040 ++/** Set Clock Enable GPONE ++ Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKEN_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_GPONE_SET 0x00000020 ++/** Set Clock Enable GPONI ++ Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKEN_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_GPONI_SET 0x00000010 ++/** Set Clock Enable LAN3 ++ Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKEN_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN3_SET 0x00000008 ++/** Set Clock Enable LAN2 ++ Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKEN_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN2_SET 0x00000004 ++/** Set Clock Enable LAN1 ++ Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKEN_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN1_SET 0x00000002 ++/** Set Clock Enable LAN0 ++ Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKEN_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_CLKEN_LAN0_SET 0x00000001 ++ ++/* Fields of "Clock Clear Register" */ ++/** Clear Clock Enable COP7 ++ Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000 ++/** Clear Clock Enable COP6 ++ Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000 ++/** Clear Clock Enable COP5 ++ Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000 ++/** Clear Clock Enable COP4 ++ Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000 ++/** Clear Clock Enable COP3 ++ Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000 ++/** Clear Clock Enable COP2 ++ Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000 ++/** Clear Clock Enable COP1 ++ Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000 ++/** Clear Clock Enable COP0 ++ Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_CLKCLR_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000 ++/** Clear Clock Enable PE5 ++ Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000 ++/** Clear Clock Enable PE4 ++ Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000 ++/** Clear Clock Enable PE3 ++ Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000 ++/** Clear Clock Enable PE2 ++ Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000 ++/** Clear Clock Enable PE1 ++ Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000 ++/** Clear Clock Enable PE0 ++ Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_CLKCLR_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000 ++/** Clear Clock Enable ARB ++ Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_CLKCLR_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000 ++/** Clear Clock Enable FSQM ++ Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_CLKCLR_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000 ++/** Clear Clock Enable TMU ++ Clears the clock enable bit of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_CLKCLR_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800 ++/** Clear Clock Enable MRG ++ Clears the clock enable bit of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_CLKCLR_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400 ++/** Clear Clock Enable DISP ++ Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_CLKCLR_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200 ++/** Clear Clock Enable IQM ++ Clears the clock enable bit of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_CLKCLR_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100 ++/** Clear Clock Enable CPUE ++ Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_CLKCLR_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080 ++/** Clear Clock Enable CPUI ++ Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_CLKCLR_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040 ++/** Clear Clock Enable GPONE ++ Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_CLKCLR_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020 ++/** Clear Clock Enable GPONI ++ Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_CLKCLR_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010 ++/** Clear Clock Enable LAN3 ++ Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_CLKCLR_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008 ++/** Clear Clock Enable LAN2 ++ Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_CLKCLR_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004 ++/** Clear Clock Enable LAN1 ++ Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_CLKCLR_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002 ++/** Clear Clock Enable LAN0 ++ Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_CLKCLR_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001 ++ ++/* Fields of "Activation Status Register" */ ++/** COP7 Status ++ Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_ACTS_COP7 0x80000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP7_ACT 0x80000000 ++/** COP6 Status ++ Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_ACTS_COP6 0x40000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP6_ACT 0x40000000 ++/** COP5 Status ++ Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_ACTS_COP5 0x20000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP5_ACT 0x20000000 ++/** COP4 Status ++ Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_ACTS_COP4 0x10000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP4_ACT 0x10000000 ++/** COP3 Status ++ Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_ACTS_COP3 0x08000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP3_ACT 0x08000000 ++/** COP2 Status ++ Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_ACTS_COP2 0x04000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP2_ACT 0x04000000 ++/** COP1 Status ++ Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_ACTS_COP1 0x02000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP1_ACT 0x02000000 ++/** COP0 Status ++ Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_ACTS_COP0 0x01000000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_COP0_ACT 0x01000000 ++/** PE5 Status ++ Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_ACTS_PE5 0x00200000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE5_ACT 0x00200000 ++/** PE4 Status ++ Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_ACTS_PE4 0x00100000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE4_ACT 0x00100000 ++/** PE3 Status ++ Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_ACTS_PE3 0x00080000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE3_ACT 0x00080000 ++/** PE2 Status ++ Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_ACTS_PE2 0x00040000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE2_ACT 0x00040000 ++/** PE1 Status ++ Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_ACTS_PE1 0x00020000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE1_ACT 0x00020000 ++/** PE0 Status ++ Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_ACTS_PE0 0x00010000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_PE0_ACT 0x00010000 ++/** ARB Status ++ Shows the activation status of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_ACTS_ARB 0x00002000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_ARB_ACT 0x00002000 ++/** FSQM Status ++ Shows the activation status of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_ACTS_FSQM 0x00001000 ++/* The block is inactive. ++#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_FSQM_ACT 0x00001000 ++/** TMU Status ++ Shows the activation status of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_ACTS_TMU 0x00000800 ++/* The block is inactive. ++#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_TMU_ACT 0x00000800 ++/** MRG Status ++ Shows the activation status of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_ACTS_MRG 0x00000400 ++/* The block is inactive. ++#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_MRG_ACT 0x00000400 ++/** DISP Status ++ Shows the activation status of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_ACTS_DISP 0x00000200 ++/* The block is inactive. ++#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_DISP_ACT 0x00000200 ++/** IQM Status ++ Shows the activation status of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_ACTS_IQM 0x00000100 ++/* The block is inactive. ++#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_IQM_ACT 0x00000100 ++/** CPUE Status ++ Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_ACTS_CPUE 0x00000080 ++/* The block is inactive. ++#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_CPUE_ACT 0x00000080 ++/** CPUI Status ++ Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_ACTS_CPUI 0x00000040 ++/* The block is inactive. ++#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_CPUI_ACT 0x00000040 ++/** GPONE Status ++ Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_ACTS_GPONE 0x00000020 ++/* The block is inactive. ++#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_GPONE_ACT 0x00000020 ++/** GPONI Status ++ Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_ACTS_GPONI 0x00000010 ++/* The block is inactive. ++#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_GPONI_ACT 0x00000010 ++/** LAN3 Status ++ Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_ACTS_LAN3 0x00000008 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN3_ACT 0x00000008 ++/** LAN2 Status ++ Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_ACTS_LAN2 0x00000004 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN2_ACT 0x00000004 ++/** LAN1 Status ++ Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_ACTS_LAN1 0x00000002 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN1_ACT 0x00000002 ++/** LAN0 Status ++ Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_ACTS_LAN0 0x00000001 ++/* The block is inactive. ++#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */ ++/** The block is active. */ ++#define SYS_GPE_ACTS_LAN0_ACT 0x00000001 ++ ++/* Fields of "Activation Register" */ ++/** Activate COP7 ++ Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_ACT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP7_SET 0x80000000 ++/** Activate COP6 ++ Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_ACT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP6_SET 0x40000000 ++/** Activate COP5 ++ Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_ACT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP5_SET 0x20000000 ++/** Activate COP4 ++ Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_ACT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP4_SET 0x10000000 ++/** Activate COP3 ++ Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_ACT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP3_SET 0x08000000 ++/** Activate COP2 ++ Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_ACT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP2_SET 0x04000000 ++/** Activate COP1 ++ Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_ACT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP1_SET 0x02000000 ++/** Activate COP0 ++ Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_ACT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_ACT_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_COP0_SET 0x01000000 ++/** Activate PE5 ++ Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_ACT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_ACT_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE5_SET 0x00200000 ++/** Activate PE4 ++ Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_ACT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_ACT_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE4_SET 0x00100000 ++/** Activate PE3 ++ Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_ACT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_ACT_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE3_SET 0x00080000 ++/** Activate PE2 ++ Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_ACT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_ACT_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE2_SET 0x00040000 ++/** Activate PE1 ++ Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_ACT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_ACT_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE1_SET 0x00020000 ++/** Activate PE0 ++ Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_ACT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_ACT_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_PE0_SET 0x00010000 ++/** Activate ARB ++ Sets the activation flag of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_ACT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_ACT_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_ARB_SET 0x00002000 ++/** Activate FSQM ++ Sets the activation flag of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_ACT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_FSQM_SET 0x00001000 ++/** Activate TMU ++ Sets the activation flag of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_ACT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_ACT_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_TMU_SET 0x00000800 ++/** Activate MRG ++ Sets the activation flag of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_ACT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_ACT_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_MRG_SET 0x00000400 ++/** Activate DISP ++ Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_ACT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_ACT_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_DISP_SET 0x00000200 ++/** Activate IQM ++ Sets the activation flag of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_ACT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_ACT_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_IQM_SET 0x00000100 ++/** Activate CPUE ++ Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_ACT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_CPUE_SET 0x00000080 ++/** Activate CPUI ++ Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_ACT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_CPUI_SET 0x00000040 ++/** Activate GPONE ++ Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_ACT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_GPONE_SET 0x00000020 ++/** Activate GPONI ++ Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_ACT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_GPONI_SET 0x00000010 ++/** Activate LAN3 ++ Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_ACT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN3_SET 0x00000008 ++/** Activate LAN2 ++ Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_ACT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN2_SET 0x00000004 ++/** Activate LAN1 ++ Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_ACT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN1_SET 0x00000002 ++/** Activate LAN0 ++ Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_ACT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_ACT_LAN0_SET 0x00000001 ++ ++/* Fields of "Deactivation Register" */ ++/** Deactivate COP7 ++ Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_DEACT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP7_CLR 0x80000000 ++/** Deactivate COP6 ++ Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_DEACT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP6_CLR 0x40000000 ++/** Deactivate COP5 ++ Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_DEACT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP5_CLR 0x20000000 ++/** Deactivate COP4 ++ Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_DEACT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP4_CLR 0x10000000 ++/** Deactivate COP3 ++ Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_DEACT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP3_CLR 0x08000000 ++/** Deactivate COP2 ++ Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_DEACT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP2_CLR 0x04000000 ++/** Deactivate COP1 ++ Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_DEACT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP1_CLR 0x02000000 ++/** Deactivate COP0 ++ Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_DEACT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_COP0_CLR 0x01000000 ++/** Deactivate PE5 ++ Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_DEACT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE5_CLR 0x00200000 ++/** Deactivate PE4 ++ Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_DEACT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE4_CLR 0x00100000 ++/** Deactivate PE3 ++ Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_DEACT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE3_CLR 0x00080000 ++/** Deactivate PE2 ++ Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_DEACT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE2_CLR 0x00040000 ++/** Deactivate PE1 ++ Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_DEACT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE1_CLR 0x00020000 ++/** Deactivate PE0 ++ Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_DEACT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_PE0_CLR 0x00010000 ++/** Deactivate ARB ++ Clears the activation flag of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_DEACT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_ARB_CLR 0x00002000 ++/** Deactivate FSQM ++ Clears the activation flag of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_DEACT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_FSQM_CLR 0x00001000 ++/** Deactivate TMU ++ Clears the activation flag of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_DEACT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_TMU_CLR 0x00000800 ++/** Deactivate MRG ++ Clears the activation flag of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_DEACT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_MRG_CLR 0x00000400 ++/** Deactivate DISP ++ Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_DEACT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_DISP_CLR 0x00000200 ++/** Deactivate IQM ++ Clears the activation flag of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_DEACT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_IQM_CLR 0x00000100 ++/** Deactivate CPUE ++ Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_DEACT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_CPUE_CLR 0x00000080 ++/** Deactivate CPUI ++ Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_DEACT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_CPUI_CLR 0x00000040 ++/** Deactivate GPONE ++ Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_DEACT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_GPONE_CLR 0x00000020 ++/** Deactivate GPONI ++ Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_DEACT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_GPONI_CLR 0x00000010 ++/** Deactivate LAN3 ++ Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_DEACT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN3_CLR 0x00000008 ++/** Deactivate LAN2 ++ Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_DEACT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN2_CLR 0x00000004 ++/** Deactivate LAN1 ++ Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_DEACT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN1_CLR 0x00000002 ++/** Deactivate LAN0 ++ Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_DEACT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_DEACT_LAN0_CLR 0x00000001 ++ ++/* Fields of "Reboot Trigger Register" */ ++/** Reboot COP7 ++ Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_RBT_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP7_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP7_TRIG 0x80000000 ++/** Reboot COP6 ++ Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_RBT_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP6_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP6_TRIG 0x40000000 ++/** Reboot COP5 ++ Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_RBT_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP5_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP5_TRIG 0x20000000 ++/** Reboot COP4 ++ Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_RBT_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP4_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP4_TRIG 0x10000000 ++/** Reboot COP3 ++ Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_RBT_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP3_TRIG 0x08000000 ++/** Reboot COP2 ++ Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_RBT_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP2_TRIG 0x04000000 ++/** Reboot COP1 ++ Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_RBT_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP1_TRIG 0x02000000 ++/** Reboot COP0 ++ Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_RBT_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_RBT_COP0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_COP0_TRIG 0x01000000 ++/** Reboot PE5 ++ Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_RBT_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_RBT_PE5_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE5_TRIG 0x00200000 ++/** Reboot PE4 ++ Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_RBT_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_RBT_PE4_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE4_TRIG 0x00100000 ++/** Reboot PE3 ++ Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_RBT_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_RBT_PE3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE3_TRIG 0x00080000 ++/** Reboot PE2 ++ Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_RBT_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_RBT_PE2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE2_TRIG 0x00040000 ++/** Reboot PE1 ++ Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_RBT_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_RBT_PE1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE1_TRIG 0x00020000 ++/** Reboot PE0 ++ Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_RBT_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_RBT_PE0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_PE0_TRIG 0x00010000 ++/** Reboot ARB ++ Triggers a reboot of the ARB domain. This domain contains the Arbiter. */ ++#define SYS_GPE_RBT_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_RBT_ARB_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_ARB_TRIG 0x00002000 ++/** Reboot FSQM ++ Triggers a reboot of the FSQM domain. This domain contains the FSQM. */ ++#define SYS_GPE_RBT_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_FSQM_TRIG 0x00001000 ++/** Reboot TMU ++ Triggers a reboot of the TMU domain. This domain contains the TMU. */ ++#define SYS_GPE_RBT_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_RBT_TMU_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_TMU_TRIG 0x00000800 ++/** Reboot MRG ++ Triggers a reboot of the MRG domain. This domain contains the Merger. */ ++#define SYS_GPE_RBT_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_RBT_MRG_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_MRG_TRIG 0x00000400 ++/** Reboot DISP ++ Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */ ++#define SYS_GPE_RBT_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_RBT_DISP_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_DISP_TRIG 0x00000200 ++/** Reboot IQM ++ Triggers a reboot of the IQM domain. This domain contains the IQM. */ ++#define SYS_GPE_RBT_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_RBT_IQM_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_IQM_TRIG 0x00000100 ++/** Reboot CPUE ++ Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_RBT_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_CPUE_TRIG 0x00000080 ++/** Reboot CPUI ++ Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_RBT_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_CPUI_TRIG 0x00000040 ++/** Reboot GPONE ++ Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_RBT_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_GPONE_TRIG 0x00000020 ++/** Reboot GPONI ++ Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_RBT_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_GPONI_TRIG 0x00000010 ++/** Reboot LAN3 ++ Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_RBT_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN3_TRIG 0x00000008 ++/** Reboot LAN2 ++ Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_RBT_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN2_TRIG 0x00000004 ++/** Reboot LAN1 ++ Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_RBT_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN1_TRIG 0x00000002 ++/** Reboot LAN0 ++ Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_RBT_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */ ++/** Trigger */ ++#define SYS_GPE_RBT_LAN0_TRIG 0x00000001 ++ ++/* Fields of "Power Down Configuration Register" */ ++/** Enable Power Down COP7 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP7 0x80000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP7_EN 0x80000000 ++/** Enable Power Down COP6 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP6 0x40000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP6_EN 0x40000000 ++/** Enable Power Down COP5 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP5 0x20000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP5_EN 0x20000000 ++/** Enable Power Down COP4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP4 0x10000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP4_EN 0x10000000 ++/** Enable Power Down COP3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP3 0x08000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP3_EN 0x08000000 ++/** Enable Power Down COP2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP2 0x04000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP2_EN 0x04000000 ++/** Enable Power Down COP1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP1 0x02000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP1_EN 0x02000000 ++/** Enable Power Down COP0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_COP0 0x01000000 ++/* Disable ++#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_COP0_EN 0x01000000 ++/** Enable Power Down PE5 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE5 0x00200000 ++/* Disable ++#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE5_EN 0x00200000 ++/** Enable Power Down PE4 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE4 0x00100000 ++/* Disable ++#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE4_EN 0x00100000 ++/** Enable Power Down PE3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE3 0x00080000 ++/* Disable ++#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE3_EN 0x00080000 ++/** Enable Power Down PE2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE2 0x00040000 ++/* Disable ++#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE2_EN 0x00040000 ++/** Enable Power Down PE1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE1 0x00020000 ++/* Disable ++#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE1_EN 0x00020000 ++/** Enable Power Down PE0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_PE0 0x00010000 ++/* Disable ++#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_PE0_EN 0x00010000 ++/** Enable Power Down ARB ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_ARB 0x00002000 ++/* Disable ++#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_ARB_EN 0x00002000 ++/** Enable Power Down FSQM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_FSQM 0x00001000 ++/* Disable ++#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_FSQM_EN 0x00001000 ++/** Enable Power Down TMU ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_TMU 0x00000800 ++/* Disable ++#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_TMU_EN 0x00000800 ++/** Enable Power Down MRG ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_MRG 0x00000400 ++/* Disable ++#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_MRG_EN 0x00000400 ++/** Enable Power Down DISP ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_DISP 0x00000200 ++/* Disable ++#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_DISP_EN 0x00000200 ++/** Enable Power Down IQM ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_IQM 0x00000100 ++/* Disable ++#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_IQM_EN 0x00000100 ++/** Enable Power Down CPUE ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_CPUE 0x00000080 ++/* Disable ++#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_CPUE_EN 0x00000080 ++/** Enable Power Down CPUI ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_CPUI 0x00000040 ++/* Disable ++#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_CPUI_EN 0x00000040 ++/** Enable Power Down GPONE ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_GPONE 0x00000020 ++/* Disable ++#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_GPONE_EN 0x00000020 ++/** Enable Power Down GPONI ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_GPONI 0x00000010 ++/* Disable ++#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_GPONI_EN 0x00000010 ++/** Enable Power Down LAN3 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN3 0x00000008 ++/* Disable ++#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN3_EN 0x00000008 ++/** Enable Power Down LAN2 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN2 0x00000004 ++/* Disable ++#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN2_EN 0x00000004 ++/** Enable Power Down LAN1 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN1 0x00000002 ++/* Disable ++#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN1_EN 0x00000002 ++/** Enable Power Down LAN0 ++ Ignore this bit as power-gating is not supported for this chip. */ ++#define SYS_GPE_PDCFG_LAN0 0x00000001 ++/* Disable ++#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_PDCFG_LAN0_EN 0x00000001 ++ ++/* Fields of "Sleep Source Configuration Register" */ ++/** Sleep/Wakeup Source CPU ++ Selects the CPU access signal as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_CPU 0x00020000 ++/* Not selected ++#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_CPU_SEL 0x00020000 ++/** Sleep/Wakeup Source FSQM ++ Selects the FSQM signal as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_FSQM 0x00008000 ++/* Not selected ++#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000 ++/** Sleep/Wakeup Source GPONT ++ Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONT 0x00002000 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000 ++/** Sleep/Wakeup Source GPONE ++ Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONE 0x00001000 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000 ++/** Sleep/Wakeup Source LAN3E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN3E 0x00000800 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800 ++/** Sleep/Wakeup Source LAN2E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN2E 0x00000400 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400 ++/** Sleep/Wakeup Source LAN1E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN1E 0x00000200 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200 ++/** Sleep/Wakeup Source LAN0E ++ Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN0E 0x00000100 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100 ++/** Sleep/Wakeup Source GPONI ++ Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_GPONI 0x00000010 ++/* Not selected ++#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010 ++/** Sleep/Wakeup Source LAN3I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN3I 0x00000008 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008 ++/** Sleep/Wakeup Source LAN2I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN2I 0x00000004 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004 ++/** Sleep/Wakeup Source LAN1I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN1I 0x00000002 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002 ++/** Sleep/Wakeup Source LAN0I ++ Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */ ++#define SYS_GPE_SSCFG_LAN0I 0x00000001 ++/* Not selected ++#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001 ++ ++/* Fields of "Sleep Source Timer Register" */ ++/** Sleep Delay Value ++ A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */ ++#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF ++/** field offset */ ++#define SYS_GPE_SST_SDV_OFFSET 0 ++ ++/* Fields of "Sleep Destination Status Register" */ ++/** Shutoff COP7 on HW Sleep ++ If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDS_COP7 0x80000000 ++/* Not selected ++#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP7_SEL 0x80000000 ++/** Shutoff COP6 on HW Sleep ++ If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDS_COP6 0x40000000 ++/* Not selected ++#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP6_SEL 0x40000000 ++/** Shutoff COP5 on HW Sleep ++ If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDS_COP5 0x20000000 ++/* Not selected ++#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP5_SEL 0x20000000 ++/** Shutoff COP4 on HW Sleep ++ If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDS_COP4 0x10000000 ++/* Not selected ++#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP4_SEL 0x10000000 ++/** Shutoff COP3 on HW Sleep ++ If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDS_COP3 0x08000000 ++/* Not selected ++#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP3_SEL 0x08000000 ++/** Shutoff COP2 on HW Sleep ++ If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDS_COP2 0x04000000 ++/* Not selected ++#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP2_SEL 0x04000000 ++/** Shutoff COP1 on HW Sleep ++ If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDS_COP1 0x02000000 ++/* Not selected ++#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP1_SEL 0x02000000 ++/** Shutoff COP0 on HW Sleep ++ If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDS_COP0 0x01000000 ++/* Not selected ++#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_COP0_SEL 0x01000000 ++/** Shutoff PE5 on HW Sleep ++ If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDS_PE5 0x00200000 ++/* Not selected ++#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE5_SEL 0x00200000 ++/** Shutoff PE4 on HW Sleep ++ If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDS_PE4 0x00100000 ++/* Not selected ++#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE4_SEL 0x00100000 ++/** Shutoff PE3 on HW Sleep ++ If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDS_PE3 0x00080000 ++/* Not selected ++#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE3_SEL 0x00080000 ++/** Shutoff PE2 on HW Sleep ++ If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDS_PE2 0x00040000 ++/* Not selected ++#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE2_SEL 0x00040000 ++/** Shutoff PE1 on HW Sleep ++ If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDS_PE1 0x00020000 ++/* Not selected ++#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE1_SEL 0x00020000 ++/** Shutoff PE0 on HW Sleep ++ If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDS_PE0 0x00010000 ++/* Not selected ++#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_PE0_SEL 0x00010000 ++/** Shutoff ARB on HW Sleep ++ If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */ ++#define SYS_GPE_SDS_ARB 0x00002000 ++/* Not selected ++#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_ARB_SEL 0x00002000 ++/** Shutoff FSQM on HW Sleep ++ If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */ ++#define SYS_GPE_SDS_FSQM 0x00001000 ++/* Not selected ++#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_FSQM_SEL 0x00001000 ++/** Shutoff TMU on HW Sleep ++ If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */ ++#define SYS_GPE_SDS_TMU 0x00000800 ++/* Not selected ++#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_TMU_SEL 0x00000800 ++/** Shutoff MRG on HW Sleep ++ If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */ ++#define SYS_GPE_SDS_MRG 0x00000400 ++/* Not selected ++#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_MRG_SEL 0x00000400 ++/** Shutoff DISP on HW Sleep ++ If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */ ++#define SYS_GPE_SDS_DISP 0x00000200 ++/* Not selected ++#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_DISP_SEL 0x00000200 ++/** Shutoff IQM on HW Sleep ++ If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */ ++#define SYS_GPE_SDS_IQM 0x00000100 ++/* Not selected ++#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_IQM_SEL 0x00000100 ++/** Shutoff CPUE on HW Sleep ++ If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDS_CPUE 0x00000080 ++/* Not selected ++#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_CPUE_SEL 0x00000080 ++/** Shutoff CPUI on HW Sleep ++ If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDS_CPUI 0x00000040 ++/* Not selected ++#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_CPUI_SEL 0x00000040 ++/** Shutoff GPONE on HW Sleep ++ If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDS_GPONE 0x00000020 ++/* Not selected ++#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_GPONE_SEL 0x00000020 ++/** Shutoff GPONI on HW Sleep ++ If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDS_GPONI 0x00000010 ++/* Not selected ++#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_GPONI_SEL 0x00000010 ++/** Shutoff LAN3 on HW Sleep ++ If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDS_LAN3 0x00000008 ++/* Not selected ++#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN3_SEL 0x00000008 ++/** Shutoff LAN2 on HW Sleep ++ If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDS_LAN2 0x00000004 ++/* Not selected ++#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN2_SEL 0x00000004 ++/** Shutoff LAN1 on HW Sleep ++ If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDS_LAN1 0x00000002 ++/* Not selected ++#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN1_SEL 0x00000002 ++/** Shutoff LAN0 on HW Sleep ++ If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDS_LAN0 0x00000001 ++/* Not selected ++#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */ ++/** Selected */ ++#define SYS_GPE_SDS_LAN0_SEL 0x00000001 ++ ++/* Fields of "Sleep Destination Set Register" */ ++/** Set Sleep Selection COP7 ++ Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDSET_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP7_SET 0x80000000 ++/** Set Sleep Selection COP6 ++ Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDSET_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP6_SET 0x40000000 ++/** Set Sleep Selection COP5 ++ Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDSET_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP5_SET 0x20000000 ++/** Set Sleep Selection COP4 ++ Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDSET_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP4_SET 0x10000000 ++/** Set Sleep Selection COP3 ++ Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDSET_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP3_SET 0x08000000 ++/** Set Sleep Selection COP2 ++ Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDSET_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP2_SET 0x04000000 ++/** Set Sleep Selection COP1 ++ Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDSET_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP1_SET 0x02000000 ++/** Set Sleep Selection COP0 ++ Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDSET_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_COP0_SET 0x01000000 ++/** Set Sleep Selection PE5 ++ Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDSET_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE5_SET 0x00200000 ++/** Set Sleep Selection PE4 ++ Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDSET_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE4_SET 0x00100000 ++/** Set Sleep Selection PE3 ++ Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDSET_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE3_SET 0x00080000 ++/** Set Sleep Selection PE2 ++ Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDSET_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE2_SET 0x00040000 ++/** Set Sleep Selection PE1 ++ Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDSET_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE1_SET 0x00020000 ++/** Set Sleep Selection PE0 ++ Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDSET_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_PE0_SET 0x00010000 ++/** Set Sleep Selection ARB ++ Sets the selection bit for domain ARBThis domain contains the Arbiter. */ ++#define SYS_GPE_SDSET_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_ARB_SET 0x00002000 ++/** Set Sleep Selection FSQM ++ Sets the selection bit for domain FSQMThis domain contains the FSQM. */ ++#define SYS_GPE_SDSET_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_FSQM_SET 0x00001000 ++/** Set Sleep Selection TMU ++ Sets the selection bit for domain TMUThis domain contains the TMU. */ ++#define SYS_GPE_SDSET_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_TMU_SET 0x00000800 ++/** Set Sleep Selection MRG ++ Sets the selection bit for domain MRGThis domain contains the Merger. */ ++#define SYS_GPE_SDSET_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_MRG_SET 0x00000400 ++/** Set Sleep Selection DISP ++ Sets the selection bit for domain DISPThis domain contains the Dispatcher. */ ++#define SYS_GPE_SDSET_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_DISP_SET 0x00000200 ++/** Set Sleep Selection IQM ++ Sets the selection bit for domain IQMThis domain contains the IQM. */ ++#define SYS_GPE_SDSET_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_IQM_SET 0x00000100 ++/** Set Sleep Selection CPUE ++ Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDSET_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_CPUE_SET 0x00000080 ++/** Set Sleep Selection CPUI ++ Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDSET_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_CPUI_SET 0x00000040 ++/** Set Sleep Selection GPONE ++ Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDSET_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_GPONE_SET 0x00000020 ++/** Set Sleep Selection GPONI ++ Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDSET_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_GPONI_SET 0x00000010 ++/** Set Sleep Selection LAN3 ++ Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDSET_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN3_SET 0x00000008 ++/** Set Sleep Selection LAN2 ++ Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDSET_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN2_SET 0x00000004 ++/** Set Sleep Selection LAN1 ++ Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDSET_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN1_SET 0x00000002 ++/** Set Sleep Selection LAN0 ++ Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDSET_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */ ++/** Set */ ++#define SYS_GPE_SDSET_LAN0_SET 0x00000001 ++ ++/* Fields of "Sleep Destination Clear Register" */ ++/** Clear Sleep Selection COP7 ++ Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ ++#define SYS_GPE_SDCLR_COP7 0x80000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP7_CLR 0x80000000 ++/** Clear Sleep Selection COP6 ++ Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ ++#define SYS_GPE_SDCLR_COP6 0x40000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP6_CLR 0x40000000 ++/** Clear Sleep Selection COP5 ++ Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ ++#define SYS_GPE_SDCLR_COP5 0x20000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP5_CLR 0x20000000 ++/** Clear Sleep Selection COP4 ++ Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ ++#define SYS_GPE_SDCLR_COP4 0x10000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP4_CLR 0x10000000 ++/** Clear Sleep Selection COP3 ++ Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ ++#define SYS_GPE_SDCLR_COP3 0x08000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP3_CLR 0x08000000 ++/** Clear Sleep Selection COP2 ++ Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ ++#define SYS_GPE_SDCLR_COP2 0x04000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP2_CLR 0x04000000 ++/** Clear Sleep Selection COP1 ++ Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ ++#define SYS_GPE_SDCLR_COP1 0x02000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP1_CLR 0x02000000 ++/** Clear Sleep Selection COP0 ++ Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ ++#define SYS_GPE_SDCLR_COP0 0x01000000 ++/* No-Operation ++#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_COP0_CLR 0x01000000 ++/** Clear Sleep Selection PE5 ++ Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ ++#define SYS_GPE_SDCLR_PE5 0x00200000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE5_CLR 0x00200000 ++/** Clear Sleep Selection PE4 ++ Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ ++#define SYS_GPE_SDCLR_PE4 0x00100000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE4_CLR 0x00100000 ++/** Clear Sleep Selection PE3 ++ Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ ++#define SYS_GPE_SDCLR_PE3 0x00080000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE3_CLR 0x00080000 ++/** Clear Sleep Selection PE2 ++ Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ ++#define SYS_GPE_SDCLR_PE2 0x00040000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE2_CLR 0x00040000 ++/** Clear Sleep Selection PE1 ++ Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ ++#define SYS_GPE_SDCLR_PE1 0x00020000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE1_CLR 0x00020000 ++/** Clear Sleep Selection PE0 ++ Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ ++#define SYS_GPE_SDCLR_PE0 0x00010000 ++/* No-Operation ++#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_PE0_CLR 0x00010000 ++/** Clear Sleep Selection ARB ++ Clears the selection bit for domain ARBThis domain contains the Arbiter. */ ++#define SYS_GPE_SDCLR_ARB 0x00002000 ++/* No-Operation ++#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_ARB_CLR 0x00002000 ++/** Clear Sleep Selection FSQM ++ Clears the selection bit for domain FSQMThis domain contains the FSQM. */ ++#define SYS_GPE_SDCLR_FSQM 0x00001000 ++/* No-Operation ++#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000 ++/** Clear Sleep Selection TMU ++ Clears the selection bit for domain TMUThis domain contains the TMU. */ ++#define SYS_GPE_SDCLR_TMU 0x00000800 ++/* No-Operation ++#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_TMU_CLR 0x00000800 ++/** Clear Sleep Selection MRG ++ Clears the selection bit for domain MRGThis domain contains the Merger. */ ++#define SYS_GPE_SDCLR_MRG 0x00000400 ++/* No-Operation ++#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_MRG_CLR 0x00000400 ++/** Clear Sleep Selection DISP ++ Clears the selection bit for domain DISPThis domain contains the Dispatcher. */ ++#define SYS_GPE_SDCLR_DISP 0x00000200 ++/* No-Operation ++#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_DISP_CLR 0x00000200 ++/** Clear Sleep Selection IQM ++ Clears the selection bit for domain IQMThis domain contains the IQM. */ ++#define SYS_GPE_SDCLR_IQM 0x00000100 ++/* No-Operation ++#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_IQM_CLR 0x00000100 ++/** Clear Sleep Selection CPUE ++ Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ ++#define SYS_GPE_SDCLR_CPUE 0x00000080 ++/* No-Operation ++#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080 ++/** Clear Sleep Selection CPUI ++ Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ ++#define SYS_GPE_SDCLR_CPUI 0x00000040 ++/* No-Operation ++#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040 ++/** Clear Sleep Selection GPONE ++ Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ ++#define SYS_GPE_SDCLR_GPONE 0x00000020 ++/* No-Operation ++#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020 ++/** Clear Sleep Selection GPONI ++ Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ ++#define SYS_GPE_SDCLR_GPONI 0x00000010 ++/* No-Operation ++#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010 ++/** Clear Sleep Selection LAN3 ++ Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ ++#define SYS_GPE_SDCLR_LAN3 0x00000008 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008 ++/** Clear Sleep Selection LAN2 ++ Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ ++#define SYS_GPE_SDCLR_LAN2 0x00000004 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004 ++/** Clear Sleep Selection LAN1 ++ Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ ++#define SYS_GPE_SDCLR_LAN1 0x00000002 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002 ++/** Clear Sleep Selection LAN0 ++ Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ ++#define SYS_GPE_SDCLR_LAN0 0x00000001 ++/* No-Operation ++#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */ ++/** Clear */ ++#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001 ++ ++/* Fields of "IRNCS Capture Register" */ ++/** FSQM wakeup request ++ The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000 ++/** GPONT wakeup request ++ The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000 ++/** GPONE wakeup request ++ The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000 ++/** LAN3E wakeup request ++ The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000 ++/** LAN1E wakeup request ++ The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000 ++/** LAN0E wakeup request ++ The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000 ++/** GPONI wakeup request ++ The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000 ++/** LAN3I wakeup request ++ The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000 ++/** LAN2I wakeup request ++ The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000 ++/** LAN1I wakeup request ++ The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000 ++/** LAN0I wakeup request ++ The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000 ++/** FSQM sleep request ++ The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000 ++/** GPONT sleep request ++ The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000 ++/** GPONE sleep request ++ The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONESR 0x00001000 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000 ++/** LAN3E sleep request ++ The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400 ++/** LAN1E sleep request ++ The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200 ++/** LAN0E sleep request ++ The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100 ++/** GPONI sleep request ++ The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONISR 0x00000010 ++/* Nothing ++#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010 ++/** LAN3I sleep request ++ The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008 ++/** LAN2I sleep request ++ The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004 ++/** LAN1I sleep request ++ The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002 ++/** LAN0I sleep request ++ The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001 ++/* Nothing ++#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */ ++/** Write: Acknowledge the interrupt. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001 ++/** Read: Interrupt occurred. */ ++#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001 ++ ++/* Fields of "IRNCS Interrupt Control Register" */ ++/** FSQM wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000 ++/** GPONT wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000 ++/** GPONE wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000 ++/** LAN3E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000 ++/** LAN1E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000 ++/** LAN0E wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000 ++/** GPONI wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000 ++/** LAN3I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000 ++/** LAN2I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000 ++/** LAN1I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000 ++/** LAN0I wakeup request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000 ++/** FSQM sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000 ++/** GPONT sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000 ++/** GPONE sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONESR 0x00001000 ++/** LAN3E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400 ++/** LAN1E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200 ++/** LAN0E sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100 ++/** GPONI sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_GPONISR 0x00000010 ++/** LAN3I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008 ++/** LAN2I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004 ++/** LAN1I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002 ++/** LAN0I sleep request ++ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001 ++ ++/* Fields of "IRNCS Interrupt Enable Register" */ ++/** FSQM wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000 ++/** GPONT wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000 ++/** GPONE wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000 ++/** LAN3E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000 ++/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000 ++/** LAN1E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000 ++/** LAN0E wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000 ++/** GPONI wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000 ++/** LAN3I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000 ++/** LAN2I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000 ++/** LAN1I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000 ++/** LAN0I wakeup request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000 ++/** FSQM sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000 ++/* Disable ++#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000 ++/** GPONT sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000 ++/** GPONE sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONESR 0x00001000 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000 ++/** LAN3E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800 ++/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400 ++/** LAN1E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200 ++/** LAN0E sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100 ++/** GPONI sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_GPONISR 0x00000010 ++/* Disable ++#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010 ++/** LAN3I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008 ++/** LAN2I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004 ++/** LAN1I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002 ++/** LAN0I sleep request ++ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ ++#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001 ++/* Disable ++#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */ ++/** Enable */ ++#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001 ++ ++/*! @} */ /* SYS_GPE_REGISTER */ ++ ++#endif /* _sys_gpe_reg_h */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h +@@ -0,0 +1,42 @@ ++/* ++ * This program is free software; you can redistribute it and/or ++ * modify it under the terms of the GNU General Public License as ++ * published by the Free Software Foundation; either version 2 of ++ * the License, or (at your option) any later version. ++ * ++ * This program is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU General Public License for more details. ++ * ++ * You should have received a copy of the GNU General Public License ++ * along with this program; if not, write to the Free Software ++ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, ++ * MA 02111-1307 USA ++ * ++ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland ++ */ ++ ++#ifndef __FALCON_SYSCTRL_H ++#define __FALCON_SYSCTRL_H ++ ++extern void sys1_hw_activate(u32 mask); ++extern void sys1_hw_deactivate(u32 mask); ++extern void sys1_hw_clk_enable(u32 mask); ++extern void sys1_hw_clk_disable(u32 mask); ++extern void sys1_hw_activate_or_reboot(u32 mask); ++ ++extern void sys_eth_hw_activate(u32 mask); ++extern void sys_eth_hw_deactivate(u32 mask); ++extern void sys_eth_hw_clk_enable(u32 mask); ++extern void sys_eth_hw_clk_disable(u32 mask); ++extern void sys_eth_hw_activate_or_reboot(u32 mask); ++ ++extern void sys_gpe_hw_activate(u32 mask); ++extern void sys_gpe_hw_deactivate(u32 mask); ++extern void sys_gpe_hw_clk_enable(u32 mask); ++extern void sys_gpe_hw_clk_disable(u32 mask); ++extern void sys_gpe_hw_activate_or_reboot(u32 mask); ++extern int sys_gpe_hw_is_activated(u32 mask); ++ ++#endif /* __FALCON_SYSCTRL_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h +@@ -0,0 +1,58 @@ ++/* ++ * Lantiq FALCON specific CPU feature overrides ++ * ++ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland ++ * ++ * This file was derived from: include/asm-mips/cpu-features.h ++ * Copyright (C) 2003, 2004 Ralf Baechle ++ * Copyright (C) 2004 Maciej W. Rozycki ++ * ++ * This program is free software; you can redistribute it and/or modify it ++ * under the terms of the GNU General Public License version 2 as published ++ * by the Free Software Foundation. ++ * ++ */ ++#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H ++#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H ++ ++#define cpu_has_tlb 1 ++#define cpu_has_4kex 1 ++#define cpu_has_3k_cache 0 ++#define cpu_has_4k_cache 1 ++#define cpu_has_tx39_cache 0 ++#define cpu_has_sb1_cache 0 ++#define cpu_has_fpu 0 ++#define cpu_has_32fpr 0 ++#define cpu_has_counter 1 ++#define cpu_has_watch 1 ++#define cpu_has_divec 1 ++ ++#define cpu_has_prefetch 1 ++#define cpu_has_ejtag 1 ++#define cpu_has_llsc 1 ++ ++#define cpu_has_mips16 1 ++#define cpu_has_mdmx 0 ++#define cpu_has_mips3d 0 ++#define cpu_has_smartmips 0 ++ ++#define cpu_has_mips32r1 1 ++#define cpu_has_mips32r2 1 ++#define cpu_has_mips64r1 0 ++#define cpu_has_mips64r2 0 ++ ++#define cpu_has_dsp 1 ++#define cpu_has_mipsmt 1 ++ ++#define cpu_has_vint 1 ++#define cpu_has_veic 1 ++ ++#define cpu_has_64bits 0 ++#define cpu_has_64bit_zero_reg 0 ++#define cpu_has_64bit_gp_regs 0 ++#define cpu_has_64bit_addresses 0 ++ ++#define cpu_dcache_line_size() 32 ++#define cpu_icache_line_size() 32 ++ ++#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ +--- /dev/null ++++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h +@@ -0,0 +1,1520 @@ ++/****************************************************************************** ++ ++ Copyright (c) 2010 ++ Lantiq Deutschland GmbH ++ ++ For licensing information, see the file 'LICENSE' in the root folder of ++ this software module. ++ ++******************************************************************************/ ++ ++#ifndef _ebu_reg_h ++#define _ebu_reg_h ++ ++/** \addtogroup EBU_REGISTER ++ @{ ++*/ ++/* access macros */ ++#define ebu_r32(reg) reg_r32(&ebu->reg) ++#define ebu_w32(val, reg) reg_w32(val, &ebu->reg) ++#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg) ++#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx) ++#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx) ++#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx) ++#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx) ++ ++ ++/** EBU register structure */ ++struct gpon_reg_ebu ++{ ++ /** Reserved */ ++ unsigned int res_0[2]; /* 0x00000000 */ ++ /** Module ID Register ++ Module type and version identifier */ ++ unsigned int modid; /* 0x00000008 */ ++ /** Module Control Register ++ This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */ ++ unsigned int modcon; /* 0x0000000C */ ++ /** Bus Read Configuration Register0 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int busrcon0; /* 0x00000010 */ ++ /** Bus Read Parameters Register0 */ ++ unsigned int busrp0; /* 0x00000014 */ ++ /** Bus Write Configuration Register0 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int buswcon0; /* 0x00000018 */ ++ /** Bus Write Parameters Register0 */ ++ unsigned int buswp0; /* 0x0000001C */ ++ /** Bus Read Configuration Register1 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int busrcon1; /* 0x00000020 */ ++ /** Bus Read Parameters Register1 */ ++ unsigned int busrp1; /* 0x00000024 */ ++ /** Bus Write Configuration Register1 ++ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ ++ unsigned int buswcon1; /* 0x00000028 */ ++ /** Bus Write Parameters Register1 */ ++ unsigned int buswp1; /* 0x0000002C */ ++ /** Reserved */ ++ unsigned int res_1[8]; /* 0x00000030 */ ++ /** Bus Protocol Configuration Extension Register 0 */ ++ unsigned int busconext0; /* 0x00000050 */ ++ /** Bus Protocol Configuration Extension Register 1 */ ++ unsigned int busconext1; /* 0x00000054 */ ++ /** Reserved */ ++ unsigned int res_2[10]; /* 0x00000058 */ ++ /** Serial Flash Configuration Register ++ The content of this register configures the EBU's Serial Flash protocol engine. */ ++ unsigned int sfcon; /* 0x00000080 */ ++ /** Serial Flash Timing Register ++ This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */ ++ unsigned int sftime; /* 0x00000084 */ ++ /** Serial Flash Status Register ++ This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */ ++ unsigned int sfstat; /* 0x00000088 */ ++ /** Serial Flash Command Register ++ When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */ ++ unsigned int sfcmd; /* 0x0000008C */ ++ /** Serial Flash Address Register ++ This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */ ++ unsigned int sfaddr; /* 0x00000090 */ ++ /** Serial Flash Data Register ++ This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */ ++ unsigned int sfdata; /* 0x00000094 */ ++ /** Serial Flash I/O Control Register ++ This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */ ++ unsigned int sfio; /* 0x00000098 */ ++ /** Reserved */ ++ unsigned int res_3[25]; /* 0x0000009C */ ++}; ++ ++ ++/* Fields of "Module ID Register" */ ++/** Feature Select ++ This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */ ++#define MODID_FSEL_MASK 0xE0000000 ++/** field offset */ ++#define MODID_FSEL_OFFSET 29 ++/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000 ++/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */ ++#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000 ++/** Serial Flash Support ++ Indicates whether or not the support of Serial Flash devices is available. */ ++#define MODID_SF 0x10000000 ++/* Not Available ++#define MODID_SF_NAV 0x00000000 */ ++/** Available */ ++#define MODID_SF_AV 0x10000000 ++/** AAD-mux Support ++ Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */ ++#define MODID_AAD 0x08000000 ++/* Not Available ++#define MODID_AAD_NAV 0x00000000 */ ++/** Available */ ++#define MODID_AAD_AV 0x08000000 ++/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */ ++#define MODID_DLL 0x04000000 ++/* Not Available ++#define MODID_DLL_NAV 0x00000000 */ ++/** Available */ ++#define MODID_DLL_AV 0x04000000 ++/** Pad Multiplexing Scheme */ ++#define MODID_PMS_MASK 0x03000000 ++/** field offset */ ++#define MODID_PMS_OFFSET 24 ++/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */ ++#define MODID_PMS_PMS_CLASSIC 0x00000000 ++/** Revision ++ Revision Number */ ++#define MODID_REV_MASK 0x000F0000 ++/** field offset */ ++#define MODID_REV_OFFSET 16 ++/** Module ID ++ This field contains the EBU's unique peripheral ID. */ ++#define MODID_ID_MASK 0x0000FF00 ++/** field offset */ ++#define MODID_ID_OFFSET 8 ++/** Version ++ This field gives the EBU version number. */ ++#define MODID_VERSION_MASK 0x000000FF ++/** field offset */ ++#define MODID_VERSION_OFFSET 0 ++ ++/* Fields of "Module Control Register" */ ++/** Reserved */ ++#define MODCON_DLLUPDINT_MASK 0xC0000000 ++/** field offset */ ++#define MODCON_DLLUPDINT_OFFSET 30 ++/** Access Inhibit Acknowledge ++ After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */ ++#define MODCON_AIA 0x02000000 ++/* no access restriction are active in the EBU subsystem ++#define MODCON_AIA_NO_INHIBIT 0x00000000 */ ++/** accesses are restricted to selected (configuration) system bus port(s) */ ++#define MODCON_AIA_INHIBIT 0x02000000 ++/** Access Inhibit request ++ Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */ ++#define MODCON_AI 0x01000000 ++/* no access restriction are active in the EBU subsystem ++#define MODCON_AI_NO_INHIBIT 0x00000000 */ ++/** accesses are restricted to selected (configuration) system bus port(s) */ ++#define MODCON_AI_INHIBIT 0x01000000 ++/** Lock Timeout */ ++#define MODCON_LTO_MASK 0x00FF0000 ++/** field offset */ ++#define MODCON_LTO_OFFSET 16 ++/** Reserved */ ++#define MODCON_DDREN 0x00008000 ++/** Pad Drive Control ++ Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_PEXT 0x00004000 ++/* Normal drive ++#define MODCON_PEXT_NORMAL 0x00000000 */ ++/** Strong drive */ ++#define MODCON_PEXT_STRONG 0x00004000 ++/** Pad Slew Falling Edge Control ++ Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_SLF 0x00002000 ++/* Slow slew rate ++#define MODCON_SLF_SLOW 0x00000000 */ ++/** Fast slew rate */ ++#define MODCON_SLF_FAST 0x00002000 ++/** Pad Slew Rising Edge Control ++ Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ ++#define MODCON_SLR 0x00001000 ++/* Slow slew rate ++#define MODCON_SLR_SLOW 0x00000000 */ ++/** Fast slew rate */ ++#define MODCON_SLR_FAST 0x00001000 ++/** Write Buffering Mode ++ This bit controls when the EBU starts a new write burst transaction from the Memport interface. */ ++#define MODCON_WBM 0x00000040 ++/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect. ++#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */ ++/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */ ++#define MODCON_WBM_START_WRITE_LATE 0x00000040 ++/** Reserved */ ++#define MODCON_SDCLKEN 0x00000020 ++/** Standby Mode Enable ++ When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */ ++#define MODCON_STBYEN 0x00000010 ++/* Disable ++#define MODCON_STBYEN_DIS 0x00000000 */ ++/** Enable */ ++#define MODCON_STBYEN_EN 0x00000010 ++/** Enable BFCLK1 ++ This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */ ++#define MODCON_BFCLK1EN 0x00000008 ++/* Disable ++#define MODCON_BFCLK1EN_DIS 0x00000000 */ ++/** Enable */ ++#define MODCON_BFCLK1EN_EN 0x00000008 ++/** Ready/Busy Status Edge ++ This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */ ++#define MODCON_STSEDGE 0x00000004 ++/** Ready/Busy Status ++ This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */ ++#define MODCON_STS 0x00000002 ++/** External Bus Arbitration Mode ++ This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */ ++#define MODCON_AM 0x00000001 ++/* The EBU does not own the bus (multi-master) ++#define MODCON_AM_SHAREDBUS 0x00000000 */ ++/** The EBU owns the external bus. */ ++#define MODCON_AM_OWNBUS 0x00000001 ++ ++/* Fields of "Bus Read Configuration Register0" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSRCON0_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSRCON0_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSRCON0_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSRCON0_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSRCON0_PORTW_OFFSET 26 ++/** 8-bit multiplexed */ ++#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 ++/** 16-bit multiplexed */ ++#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000 ++/** Twin, 16-bit multiplexed */ ++#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000 ++/** 32-bit multiplexed */ ++#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSRCON0_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSRCON0_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSRCON0_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Disable Burst Address Wrapping */ ++#define BUSRCON0_DBA 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSRCON0_WAITINV 0x00400000 ++/* Low active. ++#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSRCON0_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSRCON0_EBSE 0x00200000 ++/* Low active. ++#define BUSRCON0_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSRCON0_ECSE 0x00100000 ++/* Low active. ++#define BUSRCON0_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSRCON0_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSRCON0_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSRCON0_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSRCON0_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSRCON0_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSRCON0_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSRCON0_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSRCON0_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSRCON0_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSRCON0_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSRCON0_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSRCON0_AAP_LATE 0x00001000 ++/** Burst Flash Read Single Stage Synchronisation */ ++#define BUSRCON0_BFSSS 0x00000800 ++/* Two stages of synchronisation used. ++#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */ ++/** Single stage of synchronisation used. */ ++#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800 ++/** Burst Flash Clock Feedback Enable */ ++#define BUSRCON0_FDBKEN 0x00000400 ++/* Disable ++#define BUSRCON0_FDBKEN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_FDBKEN_EN 0x00000400 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSRCON0_CSA 0x00000200 ++/* Disable ++#define BUSRCON0_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSRCON0_NAA 0x00000100 ++/* Disable ++#define BUSRCON0_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSRCON0_ENABLE 0x00000001 ++/* Disable ++#define BUSRCON0_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON0_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Read Parameters Register0" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSRP0_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSRP0_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSRP0_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSRP0_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSRP0_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSRP0_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSRP0_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSRP0_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSRP0_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSRP0_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSRP0_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSRP0_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSRP0_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSRP0_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For read Accesses ++ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ ++#define BUSRP0_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSRP0_DATAC_OFFSET 12 ++/** Programmed Wait States for read accesses ++ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSRP0_WAITRDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSRP0_WAITRDC_OFFSET 7 ++/** Recovery Cycles After read Accesses, same CS ++ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP0_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSRP0_RECOVC_OFFSET 4 ++/** Recovery Cycles After read Accesses, other CS ++ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP0_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSRP0_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Write Configuration Register0" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSWCON0_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSWCON0_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSWCON0_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSWCON0_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSWCON0_PORTW_OFFSET 26 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSWCON0_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSWCON0_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSWCON0_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Reserved */ ++#define BUSWCON0_LOCKCS 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSWCON0_WAITINV 0x00400000 ++/* Low active. ++#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSWCON0_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSWCON0_EBSE 0x00200000 ++/* Low active. ++#define BUSWCON0_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSWCON0_ECSE 0x00100000 ++/* Low active. ++#define BUSWCON0_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSWCON0_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSWCON0_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSWCON0_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSWCON0_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSWCON0_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSWCON0_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSWCON0_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSWCON0_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSWCON0_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSWCON0_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSWCON0_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSWCON0_AAP_LATE 0x00001000 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSWCON0_CSA 0x00000200 ++/* Disable ++#define BUSWCON0_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSWCON0_NAA 0x00000100 ++/* Disable ++#define BUSWCON0_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSWCON0_ENABLE 0x00000001 ++/* Disable ++#define BUSWCON0_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON0_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Write Parameters Register0" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSWP0_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSWP0_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSWP0_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSWP0_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSWP0_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSWP0_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSWP0_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSWP0_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSWP0_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSWP0_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSWP0_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSWP0_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSWP0_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSWP0_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For write Accesses ++ Number of data hold cycles during write accesses. */ ++#define BUSWP0_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSWP0_DATAC_OFFSET 12 ++/** Programmed Wait States For write Accesses ++ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSWP0_WAITWDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSWP0_WAITWDC_OFFSET 7 ++/** Recovery Cycles After write Accesses, same CS ++ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP0_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSWP0_RECOVC_OFFSET 4 ++/** Recovery Cycles After write Accesses, other CS ++ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP0_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSWP0_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Read Configuration Register1" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSRCON1_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSRCON1_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSRCON1_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSRCON1_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSRCON1_PORTW_OFFSET 26 ++/** 8-bit multiplexed */ ++#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000 ++/** 16-bit multiplexed */ ++#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000 ++/** Twin, 16-bit multiplexed */ ++#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000 ++/** 32-bit multiplexed */ ++#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSRCON1_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSRCON1_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSRCON1_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Disable Burst Address Wrapping */ ++#define BUSRCON1_DBA 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSRCON1_WAITINV 0x00400000 ++/* Low active. ++#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSRCON1_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSRCON1_EBSE 0x00200000 ++/* Low active. ++#define BUSRCON1_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSRCON1_ECSE 0x00100000 ++/* Low active. ++#define BUSRCON1_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSRCON1_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSRCON1_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSRCON1_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSRCON1_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSRCON1_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSRCON1_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSRCON1_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSRCON1_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSRCON1_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSRCON1_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSRCON1_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSRCON1_AAP_LATE 0x00001000 ++/** Burst Flash Read Single Stage Synchronisation */ ++#define BUSRCON1_BFSSS 0x00000800 ++/* Two stages of synchronisation used. ++#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */ ++/** Single stage of synchronisation used. */ ++#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800 ++/** Burst Flash Clock Feedback Enable */ ++#define BUSRCON1_FDBKEN 0x00000400 ++/* Disable ++#define BUSRCON1_FDBKEN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_FDBKEN_EN 0x00000400 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSRCON1_CSA 0x00000200 ++/* Disable ++#define BUSRCON1_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSRCON1_NAA 0x00000100 ++/* Disable ++#define BUSRCON1_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSRCON1_ENABLE 0x00000001 ++/* Disable ++#define BUSRCON1_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSRCON1_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Read Parameters Register1" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSRP1_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSRP1_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSRP1_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSRP1_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSRP1_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSRP1_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSRP1_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSRP1_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSRP1_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSRP1_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSRP1_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSRP1_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSRP1_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSRP1_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For read Accesses ++ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ ++#define BUSRP1_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSRP1_DATAC_OFFSET 12 ++/** Programmed Wait States for read accesses ++ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSRP1_WAITRDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSRP1_WAITRDC_OFFSET 7 ++/** Recovery Cycles After read Accesses, same CS ++ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP1_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSRP1_RECOVC_OFFSET 4 ++/** Recovery Cycles After read Accesses, other CS ++ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ ++#define BUSRP1_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSRP1_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Write Configuration Register1" */ ++/** Device Type For Region ++ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ ++#define BUSWCON1_AGEN_MASK 0xF0000000 ++/** field offset */ ++#define BUSWCON1_AGEN_OFFSET 28 ++/** Muxed Asynchronous Type External Memory */ ++#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 ++/** Muxed Burst Type External Memory */ ++#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 ++/** NAND Flash (page optimised) */ ++#define BUSWCON1_AGEN_NAND_FLASH 0x20000000 ++/** Muxed Cellular RAM External Memory */ ++#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 ++/** Demuxed Asynchronous Type External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 ++/** Demuxed Burst Type External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 ++/** Demuxed Page Mode External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 ++/** Demuxed Cellular RAM External Memory */ ++#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 ++/** Serial Flash */ ++#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000 ++/** Device Addressing Mode ++ t.b.d. */ ++#define BUSWCON1_PORTW_MASK 0x0C000000 ++/** field offset */ ++#define BUSWCON1_PORTW_OFFSET 26 ++/** External Wait Control ++ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ ++#define BUSWCON1_WAIT_MASK 0x03000000 ++/** field offset */ ++#define BUSWCON1_WAIT_OFFSET 24 ++/** WAIT is ignored (default after reset). */ ++#define BUSWCON1_WAIT_OFF 0x00000000 ++/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ ++#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000 ++/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ ++#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000 ++/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ ++#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000 ++/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ ++#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 ++/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ ++#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000 ++/** Reserved */ ++#define BUSWCON1_LOCKCS 0x00800000 ++/** Reversed polarity at wait */ ++#define BUSWCON1_WAITINV 0x00400000 ++/* Low active. ++#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */ ++/** High active */ ++#define BUSWCON1_WAITINV_ACTHI 0x00400000 ++/** Early ADV Enable for Synchronous Bursts */ ++#define BUSWCON1_EBSE 0x00200000 ++/* Low active. ++#define BUSWCON1_EBSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000 ++/** Early Control Signals for Synchronous Bursts */ ++#define BUSWCON1_ECSE 0x00100000 ++/* Low active. ++#define BUSWCON1_ECSE_DELAYED 0x00000000 */ ++/** High active */ ++#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000 ++/** Synchronous Burst Buffer Mode Select */ ++#define BUSWCON1_FBBMSEL 0x00080000 ++/* FIXED_LENGTH ++#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ ++/** CONTINUOUS */ ++#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000 ++/** Burst Length for Synchronous Burst */ ++#define BUSWCON1_FETBLEN_MASK 0x00070000 ++/** field offset */ ++#define BUSWCON1_FETBLEN_OFFSET 16 ++/** Up to 1 data cycle (default after reset). */ ++#define BUSWCON1_FETBLEN_SINGLE 0x00000000 ++/** Up to 2 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST2 0x00010000 ++/** Up to 4 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST4 0x00020000 ++/** Up to 8 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST8 0x00030000 ++/** Up to 16 data cycles. */ ++#define BUSWCON1_FETBLEN_BURST16 0x00040000 ++/** Reserved ++ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ ++#define BUSWCON1_NANDAMAP_MASK 0x0000C000 ++/** field offset */ ++#define BUSWCON1_NANDAMAP_OFFSET 14 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000 ++/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ ++#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 ++/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ ++#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000 ++/** Reserved for future use. Do not use or unpredictable results may occur. */ ++#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000 ++/** AAD-mux Protocol ++ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ ++#define BUSWCON1_AADMUX 0x00002000 ++/* Muxed device is write accessed in AD-mux mode. ++#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */ ++/** Muxed device is write accessed in AAD-mux mode. */ ++#define BUSWCON1_AADMUX_AAD_MUX 0x00002000 ++/** Asynchronous Address Phase */ ++#define BUSWCON1_AAP 0x00001000 ++/* Clock is enabled at beginning of access. ++#define BUSWCON1_AAP_EARLY 0x00000000 */ ++/** Clock is enabled after address phase. */ ++#define BUSWCON1_AAP_LATE 0x00001000 ++/** Auxiliary Chip Select Enable ++ Not supported in GPON-EBU, field must be set to 0. */ ++#define BUSWCON1_CSA 0x00000200 ++/* Disable ++#define BUSWCON1_CSA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_CSA_EN 0x00000200 ++/** Flash Non-Array Access Enable ++ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ ++#define BUSWCON1_NAA 0x00000100 ++/* Disable ++#define BUSWCON1_NAA_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_NAA_EN 0x00000100 ++/** Module Enable */ ++#define BUSWCON1_ENABLE 0x00000001 ++/* Disable ++#define BUSWCON1_ENABLE_DIS 0x00000000 */ ++/** Enable */ ++#define BUSWCON1_ENABLE_EN 0x00000001 ++ ++/* Fields of "Bus Write Parameters Register1" */ ++/** Address Cycles ++ Number of cycles for address phase. */ ++#define BUSWP1_ADDRC_MASK 0xF0000000 ++/** field offset */ ++#define BUSWP1_ADDRC_OFFSET 28 ++/** Address Hold Cycles For Multiplexed Address ++ Number of address hold cycles during multiplexed accesses. */ ++#define BUSWP1_ADHOLC_MASK 0x0F000000 ++/** field offset */ ++#define BUSWP1_ADHOLC_OFFSET 24 ++/** Programmed Command Delay Cycles ++ Number of delay cycles during command delay phase. */ ++#define BUSWP1_CMDDELAY_MASK 0x00F00000 ++/** field offset */ ++#define BUSWP1_CMDDELAY_OFFSET 20 ++/** Extended Data */ ++#define BUSWP1_EXTDATA_MASK 0x000C0000 ++/** field offset */ ++#define BUSWP1_EXTDATA_OFFSET 18 ++/** External device outputs data every BFCLK cycle */ ++#define BUSWP1_EXTDATA_ONE 0x00000000 ++/** External device outputs data every 2nd BFCLK cycles */ ++#define BUSWP1_EXTDATA_TWO 0x00040000 ++/** External device outputs data every 4th BFCLK cycles */ ++#define BUSWP1_EXTDATA_FOUR 0x00080000 ++/** External device outputs data every 8th BFCLK cycles */ ++#define BUSWP1_EXTDATA_EIGHT 0x000C0000 ++/** Frequency of external clock at pin BFCLKO */ ++#define BUSWP1_EXTCLOCK_MASK 0x00030000 ++/** field offset */ ++#define BUSWP1_EXTCLOCK_OFFSET 16 ++/** Equal to ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000 ++/** 1/2 of ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000 ++/** 1/3 of ebu_clk frequency. */ ++#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000 ++/** 1/4 of ebu_clk frequency (default after reset). */ ++#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 ++/** Data Hold Cycles For write Accesses ++ Number of data hold cycles during write accesses. */ ++#define BUSWP1_DATAC_MASK 0x0000F000 ++/** field offset */ ++#define BUSWP1_DATAC_OFFSET 12 ++/** Programmed Wait States For write Accesses ++ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ ++#define BUSWP1_WAITWDC_MASK 0x00000F80 ++/** field offset */ ++#define BUSWP1_WAITWDC_OFFSET 7 ++/** Recovery Cycles After write Accesses, same CS ++ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP1_RECOVC_MASK 0x00000070 ++/** field offset */ ++#define BUSWP1_RECOVC_OFFSET 4 ++/** Recovery Cycles After write Accesses, other CS ++ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ ++#define BUSWP1_DTACS_MASK 0x0000000F ++/** field offset */ ++#define BUSWP1_DTACS_OFFSET 0 ++ ++/* Fields of "Bus Protocol Configuration Extension Register 0" */ ++/** Byte Control Mapping ++ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ ++#define BUSCONEXT0_BCMAP_MASK 0x00030000 ++/** field offset */ ++#define BUSCONEXT0_BCMAP_OFFSET 16 ++/** No mirroring of byte enables. */ ++#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000 ++/** Asynchronous Early Write ++ This bit is obsolete and must be set to 0 or unpredictable results may result. */ ++#define BUSCONEXT0_AEW 0x00008000 ++/** AAD-mux Consecutive Address Cycles ++ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ ++#define BUSCONEXT0_ACAC 0x00004000 ++/* ADV is deasserted between high and low address phase. ++#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */ ++/** ADV is not deasserted between high and low address phase. */ ++#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000 ++/** AAD-mux Write Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ ++#define BUSCONEXT0_WAAC_MASK 0x00003800 ++/** field offset */ ++#define BUSCONEXT0_WAAC_OFFSET 11 ++/** AAD-mux Read Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ ++#define BUSCONEXT0_RAAC_MASK 0x00000700 ++/** field offset */ ++#define BUSCONEXT0_RAAC_OFFSET 8 ++/** AAD-mux Paging Enable for CS0 ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT0_PAGE_EN 0x00000080 ++/* Disable ++#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSCONEXT0_PAGE_EN_EN 0x00000080 ++/** AAD-mux Address Extension Bit Generation Mode ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT0_AEBM_MASK 0x00000070 ++/** field offset */ ++#define BUSCONEXT0_AEBM_OFFSET 4 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010 ++/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ ++#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020 ++/** Do not use */ ++#define BUSCONEXT0_AEBM_reserved 0x00000030 ++/** A[15:14] in the high address cycle is set to 00B. */ ++#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040 ++/** A[15:14] in the high address cycle is set to 01B */ ++#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050 ++/** A[15:14] in the high address cycle is set to 10B */ ++#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060 ++/** A[15:14] in the high address cycle is set to 11B. */ ++#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070 ++/** Most Significant Address Bit of External Device ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ ++#define BUSCONEXT0_AMSB_MASK 0x0000000F ++/** field offset */ ++#define BUSCONEXT0_AMSB_OFFSET 0 ++ ++/* Fields of "Bus Protocol Configuration Extension Register 1" */ ++/** Byte Control Mapping ++ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ ++#define BUSCONEXT1_BCMAP_MASK 0x00030000 ++/** field offset */ ++#define BUSCONEXT1_BCMAP_OFFSET 16 ++/** No mirroring of byte enables. */ ++#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000 ++/** Asynchronous Early Write ++ This bit is obsolete and must be set to 0 or unpredictable results may result. */ ++#define BUSCONEXT1_AEW 0x00008000 ++/** AAD-mux Consecutive Address Cycles ++ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ ++#define BUSCONEXT1_ACAC 0x00004000 ++/* ADV is deasserted between high and low address phase. ++#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */ ++/** ADV is not deasserted between high and low address phase. */ ++#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000 ++/** AAD-mux Write Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ ++#define BUSCONEXT1_WAAC_MASK 0x00003800 ++/** field offset */ ++#define BUSCONEXT1_WAAC_OFFSET 11 ++/** AAD-mux Read Address-to-Address Delay ++ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ ++#define BUSCONEXT1_RAAC_MASK 0x00000700 ++/** field offset */ ++#define BUSCONEXT1_RAAC_OFFSET 8 ++/** AAD-mux Paging Enable for CS0 ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT1_PAGE_EN 0x00000080 ++/* Disable ++#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */ ++/** Enable */ ++#define BUSCONEXT1_PAGE_EN_EN 0x00000080 ++/** AAD-mux Address Extension Bit Generation Mode ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ ++#define BUSCONEXT1_AEBM_MASK 0x00000070 ++/** field offset */ ++#define BUSCONEXT1_AEBM_OFFSET 4 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000 ++/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010 ++/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ ++#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020 ++/** Do not use */ ++#define BUSCONEXT1_AEBM_reserved 0x00000030 ++/** A[15:14] in the high address cycle is set to 00B. */ ++#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040 ++/** A[15:14] in the high address cycle is set to 01B */ ++#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050 ++/** A[15:14] in the high address cycle is set to 10B */ ++#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060 ++/** A[15:14] in the high address cycle is set to 11B. */ ++#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070 ++/** Most Significant Address Bit of External Device ++ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ ++#define BUSCONEXT1_AMSB_MASK 0x0000000F ++/** field offset */ ++#define BUSCONEXT1_AMSB_OFFSET 0 ++ ++/* Fields of "Serial Flash Configuration Register" */ ++/** Direct Access Device Port Width ++ DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */ ++#define SFCON_DA_PORTW_MASK 0xE0000000 ++/** field offset */ ++#define SFCON_DA_PORTW_OFFSET 29 ++/** One signal line used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000 ++/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000 ++/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000 ++/** Two signal lines used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000 ++/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000 ++/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ ++#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000 ++/** Four signal lines used in all phases of the transaction. */ ++#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000 ++/** for future use. */ ++#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000 ++/** Read Abort Enable ++ If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */ ++#define SFCON_RD_ABORT_EN 0x10000000 ++/** Device Size ++ Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */ ++#define SFCON_DEV_SIZE_MASK 0x0F000000 ++/** field offset */ ++#define SFCON_DEV_SIZE_OFFSET 24 ++/** 16 MBit device */ ++#define SFCON_DEV_SIZE_A20_0 0x00000000 ++/** 32 MBit device */ ++#define SFCON_DEV_SIZE_A21_0 0x01000000 ++/** 64 MBit device */ ++#define SFCON_DEV_SIZE_A22_0 0x02000000 ++/** 128 MBit device */ ++#define SFCON_DEV_SIZE_A23_0 0x03000000 ++/** 256 MBit device */ ++#define SFCON_DEV_SIZE_A24_0 0x04000000 ++/** 512 MBit device */ ++#define SFCON_DEV_SIZE_A25_0 0x05000000 ++/** 1 GBit device */ ++#define SFCON_DEV_SIZE_A26_0 0x06000000 ++/** 2 GBit device */ ++#define SFCON_DEV_SIZE_A27_0 0x07000000 ++/** 4 GBit device */ ++#define SFCON_DEV_SIZE_A28_0 0x08000000 ++/** 8 GBit device */ ++#define SFCON_DEV_SIZE_A29_0 0x09000000 ++/** 16 GBit device */ ++#define SFCON_DEV_SIZE_A30_0 0x0A000000 ++/** 32 GBit device */ ++#define SFCON_DEV_SIZE_A31_0 0x0B000000 ++/** Device Page Size ++ Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */ ++#define SFCON_DPS_MASK 0x00C00000 ++/** field offset */ ++#define SFCON_DPS_OFFSET 22 ++/** Device page size is 256 Bytes */ ++#define SFCON_DPS_DPS_256 0x00000000 ++/** Device page size is 512 Bytes */ ++#define SFCON_DPS_DPS_512 0x00400000 ++/** Page Buffer Size ++ Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */ ++#define SFCON_PB_SIZE_MASK 0x00300000 ++/** field offset */ ++#define SFCON_PB_SIZE_OFFSET 20 ++/** No read buffer is available/used. */ ++#define SFCON_PB_SIZE_NONE 0x00000000 ++/** 128 Bytes */ ++#define SFCON_PB_SIZE_SIZE_128 0x00100000 ++/** 256 Bytes */ ++#define SFCON_PB_SIZE_SIZE_256 0x00200000 ++/** Bidirectional Data Bus ++ Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */ ++#define SFCON_BIDIR 0x00080000 ++/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read) ++#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */ ++/** The Serial Flash interface uses a bidirectional data bus. */ ++#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000 ++/** No Busy Error termination ++ By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */ ++#define SFCON_NO_BUSY_ERR 0x00040000 ++/** End-of-Busy Detection Mode ++ Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */ ++#define SFCON_EOBDM_MASK 0x00030000 ++/** field offset */ ++#define SFCON_EOBDM_OFFSET 16 ++/** No read buffer is available/used. */ ++#define SFCON_EOBDM_SOFTWARE 0x00000000 ++/** Poll device status register (not supported yet) */ ++#define SFCON_EOBDM_POLL_SR 0x00010000 ++/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */ ++#define SFCON_EOBDM_POLL_RDY 0x00020000 ++/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */ ++#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000 ++/** Direct Access Keep Chip Select ++ Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */ ++#define SFCON_DA_KEEP_CS 0x00008000 ++/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */ ++/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ ++#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000 ++/** Early Read Abort Enable ++ When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */ ++#define SFCON_EARLY_ABORT 0x00004000 ++/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */ ++/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */ ++#define SFCON_EARLY_ABORT_ENABLE 0x00004000 ++/** Direct Access Address Length ++ Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */ ++#define SFCON_DA_ALEN_MASK 0x00003000 ++/** field offset */ ++#define SFCON_DA_ALEN_OFFSET 12 ++/** 3 address bytes (bits 23:0 of the internal address) */ ++#define SFCON_DA_ALEN_THREE 0x00000000 ++/** Read Access Dummy Bytes ++ This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */ ++#define SFCON_RD_DUMLEN_MASK 0x00000F00 ++/** field offset */ ++#define SFCON_RD_DUMLEN_OFFSET 8 ++/** Direct Read Access Command Opcode ++ This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */ ++#define SFCON_RD_OPC_MASK 0x000000FF ++/** field offset */ ++#define SFCON_RD_OPC_OFFSET 0 ++/** READ */ ++#define SFCON_RD_OPC_READ 0x00000003 ++/** FAST_READ */ ++#define SFCON_RD_OPC_FAST_READ 0x0000000B ++ ++/* Fields of "Serial Flash Timing Register" */ ++/** CS Idle time ++ This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */ ++#define SFTIME_CS_IDLE_MASK 0xF0000000 ++/** field offset */ ++#define SFTIME_CS_IDLE_OFFSET 28 ++/** 1 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_0 0x00000000 ++/** 2 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_1 0x10000000 ++/** 3 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_2 0x20000000 ++/** 4 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_3 0x30000000 ++/** 6 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_4 0x40000000 ++/** 8 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_5 0x50000000 ++/** 10 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_6 0x60000000 ++/** 12 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_7 0x70000000 ++/** 14 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_8 0x80000000 ++/** 16 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_9 0x90000000 ++/** 20 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_10 0xA0000000 ++/** 24 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_11 0xB0000000 ++/** 32 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_12 0xC0000000 ++/** 40 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_13 0xD0000000 ++/** 48 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_14 0xE0000000 ++/** 64 EBU clock cycles */ ++#define SFTIME_CS_IDLE_CLKC_15 0xF0000000 ++/** CS Hold time ++ This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */ ++#define SFTIME_CS_HOLD_MASK 0x0C000000 ++/** field offset */ ++#define SFTIME_CS_HOLD_OFFSET 26 ++/** CS Setup time ++ This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */ ++#define SFTIME_CS_SETUP_MASK 0x03000000 ++/** field offset */ ++#define SFTIME_CS_SETUP_OFFSET 24 ++/** Write-to-Read Pause ++ This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */ ++#define SFTIME_WR2RD_PAUSE_MASK 0x00300000 ++/** field offset */ ++#define SFTIME_WR2RD_PAUSE_OFFSET 20 ++/** Read Data Position ++ This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */ ++#define SFTIME_RD_POS_MASK 0x000F0000 ++/** field offset */ ++#define SFTIME_RD_POS_OFFSET 16 ++/** SCK Fall-edge Position ++ This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */ ++#define SFTIME_SCKF_POS_MASK 0x0000F000 ++/** field offset */ ++#define SFTIME_SCKF_POS_OFFSET 12 ++/** SCK Rise-edge Position ++ This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */ ++#define SFTIME_SCKR_POS_MASK 0x00000F00 ++/** field offset */ ++#define SFTIME_SCKR_POS_OFFSET 8 ++/** SCK Feedback Clock Inversion ++ If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */ ++#define SFTIME_SCK_FDBK_INV 0x00000040 ++/** SCK Clock Feedback ++ If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */ ++#define SFTIME_SCK_FDBK_EN 0x00000020 ++/** Inverted SCK ++ If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */ ++#define SFTIME_SCK_INV 0x00000010 ++/** SCK Period ++ This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */ ++#define SFTIME_SCK_PER_MASK 0x0000000F ++/** field offset */ ++#define SFTIME_SCK_PER_OFFSET 0 ++ ++/* Fields of "Serial Flash Status Register" */ ++/** Command Overwrite Error ++ This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ ++#define SFSTAT_CMD_OVWRT_ERR 0x40000000 ++/** Command Error ++ This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ ++#define SFSTAT_CMD_ERR 0x20000000 ++/** Access Command Pending ++ If set, indicates that access from/to a Serial Flash device has not finished yet. */ ++#define SFSTAT_CMD_PEND 0x00400000 ++/** External Device Selected ++ If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */ ++#define SFSTAT_SELECTED 0x00200000 ++/** Protocol Engine Active ++ If set, indicates that the EBU's Serial Flash protocol engine is active. */ ++#define SFSTAT_ACTIVE 0x00100000 ++/** Page Buffer Invalidate ++ When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */ ++#define SFSTAT_PB_INVALID 0x00010000 ++/** Page Buffer Update ++ This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */ ++#define SFSTAT_PB_UPDATE 0x00002000 ++/** Page Buffer Valid ++ This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */ ++#define SFSTAT_PB_VALID 0x00001000 ++/** Page Buffer Busy ++ The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */ ++#define SFSTAT_PB_BUSY 0x00000100 ++/** Device Busy ++ This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */ ++#define SFSTAT_BUSY 0x00000001 ++ ++/* Fields of "Serial Flash Command Register" */ ++/** Command Type ++ This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */ ++#define SFCMD_CMDTYPE 0x80000000 ++/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device. ++#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */ ++/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */ ++#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000 ++/** Device Port Width ++ Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */ ++#define SFCMD_PORTW_MASK 0x70000000 ++/** field offset */ ++#define SFCMD_PORTW_OFFSET 28 ++/** Bidirectional Signal Lines ++ If set selects bidirectional signal lines to be used for the data transfer. */ ++#define SFCMD_BIDIR 0x08000000 ++/** Chip Select ++ This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */ ++#define SFCMD_CS_MASK 0x07000000 ++/** field offset */ ++#define SFCMD_CS_OFFSET 24 ++/** Disable Auto Address Increment ++ By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */ ++#define SFCMD_DIS_AAI 0x00800000 ++/** Address Length ++ Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */ ++#define SFCMD_ALEN_MASK 0x00700000 ++/** field offset */ ++#define SFCMD_ALEN_OFFSET 20 ++/** Dummy Phase Length ++ Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */ ++#define SFCMD_DUMLEN_MASK 0x000F0000 ++/** field offset */ ++#define SFCMD_DUMLEN_OFFSET 16 ++/** Keep Chip Select ++ Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */ ++#define SFCMD_KEEP_CS 0x00008000 ++/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. ++#define SFCMD_KEEP_CS_DESELECT 0x00000000 */ ++/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ ++#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 ++/** Set Busy Flag ++ If set, starting the command sets EBU_SFSTAT.busy. */ ++#define SFCMD_SET_BUSY 0x00004000 ++/** Ignore Busy ++ By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */ ++#define SFCMD_IGNORE_BUSY 0x00002000 ++/** Skip Opcode ++ If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */ ++#define SFCMD_SKIP_OPC 0x00001000 ++/** Data Length ++ This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */ ++#define SFCMD_DLEN_MASK 0x00000E00 ++/** field offset */ ++#define SFCMD_DLEN_OFFSET 9 ++/** Direction ++ Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */ ++#define SFCMD_DIR 0x00000100 ++/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA. ++#define SFCMD_DIR_READ 0x00000000 */ ++/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */ ++#define SFCMD_DIR_WRITE 0x00000100 ++/** Command Opcode ++ A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */ ++#define SFCMD_OPC_MASK 0x000000FF ++/** field offset */ ++#define SFCMD_OPC_OFFSET 0 ++ ++/* Fields of "Serial Flash Address Register" */ ++/** Address ++ Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ ++#define SFADDR_ADDR_MASK 0xFFFFFFFF ++/** field offset */ ++#define SFADDR_ADDR_OFFSET 0 ++ ++/* Fields of "Serial Flash Data Register" */ ++/** Data Bytes ++ Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ ++#define SFDATA_DATA_MASK 0xFFFFFFFF ++/** field offset */ ++#define SFDATA_DATA_OFFSET 0 ++ ++/* Fields of "Serial Flash I/O Control Register" */ ++/** Start of Write Delay ++ By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */ ++#define SFIO_SOWD_MASK 0x0000F000 ++/** field offset */ ++#define SFIO_SOWD_OFFSET 12 ++/** End of Write Delay ++ This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */ ++#define SFIO_EOWD_MASK 0x00000F00 ++/** field offset */ ++#define SFIO_EOWD_OFFSET 8 ++/** Data Output ++ The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */ ++#define SFIO_UNUSED_WD_MASK 0x0000000F ++/** field offset */ ++#define SFIO_UNUSED_WD_OFFSET 0 ++ ++/*! @} */ /* EBU_REGISTER */ ++ ++#endif /* _ebu_reg_h */ diff --git a/target/linux/lantiq/patches/200-owrt-netif_receive_skb.patch b/target/linux/lantiq/patches/200-owrt-netif_receive_skb.patch new file mode 100644 index 0000000000..d1cb2ab545 --- /dev/null +++ b/target/linux/lantiq/patches/200-owrt-netif_receive_skb.patch @@ -0,0 +1,17 @@ +--- a/drivers/net/lantiq_etop.c ++++ b/drivers/net/lantiq_etop.c +@@ -190,8 +190,12 @@ ltq_etop_hw_receive(struct ltq_etop_chan + + skb_put(skb, len); + skb->dev = ch->netdev; +- skb->protocol = eth_type_trans(skb, ch->netdev); +- netif_receive_skb(skb); ++ if (priv->phydev && priv->phydev->netif_receive_skb) { ++ priv->phydev->netif_receive_skb(skb); ++ } else { ++ skb->protocol = eth_type_trans(skb, ch->netdev); ++ netif_receive_skb(skb); ++ } + } + + static int diff --git a/target/linux/lantiq/patches/201-owrt-mtd_uimage_split.patch b/target/linux/lantiq/patches/201-owrt-mtd_uimage_split.patch new file mode 100644 index 0000000000..6c6a45ac04 --- /dev/null +++ b/target/linux/lantiq/patches/201-owrt-mtd_uimage_split.patch @@ -0,0 +1,116 @@ +--- a/drivers/mtd/Kconfig ++++ b/drivers/mtd/Kconfig +@@ -41,6 +41,10 @@ config MTD_ROOTFS_SPLIT + bool "Automatically split 'rootfs' partition for squashfs" + default y + ++config MTD_UIMAGE_SPLIT ++ bool "Automatically split 'linux' partition into 'kernel' and 'rootfs'" ++ default y ++ + config MTD_REDBOOT_PARTS + tristate "RedBoot partition table parsing" + ---help--- +--- a/drivers/mtd/mtdpart.c ++++ b/drivers/mtd/mtdpart.c +@@ -861,6 +861,82 @@ static int refresh_rootfs_split(struct m + } + #endif /* CONFIG_MTD_ROOTFS_SPLIT */ + ++ ++#ifdef CONFIG_MTD_UIMAGE_SPLIT ++static unsigned long find_uimage_size(struct mtd_info *mtd, ++ unsigned long offset) ++{ ++#define UBOOT_MAGIC 0x56190527 ++ unsigned long magic = 0; ++ unsigned long temp; ++ size_t len; ++ int ret; ++ ++ ret = mtd->read(mtd, offset, 4, &len, (void *)&magic); ++ if (ret || len != sizeof(magic)) ++ return 0; ++ ++ if (le32_to_cpu(magic) != UBOOT_MAGIC) ++ return 0; ++ ++ ret = mtd->read(mtd, offset + 12, 4, &len, (void *)&temp); ++ if (ret || len != sizeof(temp)) ++ return 0; ++ ++ return temp + 0x40; ++} ++ ++static int detect_squashfs_partition(struct mtd_info *mtd, unsigned long offset) ++{ ++ unsigned long temp; ++ size_t len; ++ int ret; ++ ++ ret = mtd->read(mtd, offset, 4, &len, (void *)&temp); ++ if (ret || len != sizeof(temp)) ++ return 0; ++ ++ return le32_to_cpu(temp) == SQUASHFS_MAGIC; ++} ++ ++static int split_uimage(struct mtd_info *mtd, ++ const struct mtd_partition *part) ++{ ++ static struct mtd_partition split_partitions[] = { ++ { ++ .name = "kernel", ++ .offset = 0x0, ++ .size = 0x0, ++ }, { ++ .name = "rootfs", ++ .offset = 0x0, ++ .size = 0x0, ++ }, ++ }; ++ ++ split_partitions[0].size = find_uimage_size(mtd, part->offset); ++ if (!split_partitions[0].size) { ++ printk(KERN_NOTICE "no uImage found in linux partition\n"); ++ return -1; ++ } ++ ++ if (!detect_squashfs_partition(mtd, ++ part->offset ++ + split_partitions[0].size)) { ++ split_partitions[0].size &= ~(mtd->erasesize - 1); ++ split_partitions[0].size += mtd->erasesize; ++ } ++ ++ split_partitions[0].offset = part->offset; ++ split_partitions[1].offset = part->offset + split_partitions[0].size; ++ split_partitions[1].size = part->size - split_partitions[0].size; ++ ++ add_mtd_partitions(mtd, split_partitions, 2); ++ ++ return 0; ++} ++#endif ++ + /* + * This function, given a master MTD object and a partition table, creates + * and registers slave MTD objects which are bound to the master according to +@@ -894,6 +970,17 @@ int add_mtd_partitions(struct mtd_info * + + add_mtd_device(&slave->mtd); + ++#ifdef CONFIG_MTD_UIMAGE_SPLIT ++ if (!strcmp(parts[i].name, "linux")) { ++ ret = split_uimage(master, &parts[i]); ++ ++ if (ret) { ++ printk(KERN_WARNING ++ "Can't split linux partition\n"); ++ } ++ } ++#endif ++ + if (!strcmp(parts[i].name, "rootfs")) { + #ifdef CONFIG_MTD_ROOTFS_ROOT_DEV + if (ROOT_DEV == 0) { diff --git a/target/linux/lantiq/patches/202-owrt-atm.patch b/target/linux/lantiq/patches/202-owrt-atm.patch new file mode 100644 index 0000000000..00af6e98f1 --- /dev/null +++ b/target/linux/lantiq/patches/202-owrt-atm.patch @@ -0,0 +1,60 @@ +--- a/arch/mips/lantiq/irq.c ++++ b/arch/mips/lantiq/irq.c +@@ -9,6 +9,7 @@ + + #include <linux/interrupt.h> + #include <linux/ioport.h> ++#include <linux/module.h> + + #include <asm/bootinfo.h> + #include <asm/irq_cpu.h> +@@ -102,6 +103,7 @@ void ltq_mask_and_ack_irq(struct irq_dat + ltq_icu_w32(ltq_icu_r32(ier) & ~(1 << irq_nr), ier); + ltq_icu_w32((1 << irq_nr), isr); + } ++EXPORT_SYMBOL(ltq_mask_and_ack_irq); + + static void ltq_ack_irq(struct irq_data *d) + { +--- a/arch/mips/mm/cache.c ++++ b/arch/mips/mm/cache.c +@@ -52,6 +52,8 @@ void (*_dma_cache_wback)(unsigned long s + void (*_dma_cache_inv)(unsigned long start, unsigned long size); + + EXPORT_SYMBOL(_dma_cache_wback_inv); ++EXPORT_SYMBOL(_dma_cache_wback); ++EXPORT_SYMBOL(_dma_cache_inv); + + #endif /* CONFIG_DMA_NONCOHERENT */ + +--- a/net/atm/proc.c ++++ b/net/atm/proc.c +@@ -154,7 +154,7 @@ static void *vcc_seq_next(struct seq_fil + static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc) + { + static const char *const class_name[] = { +- "off", "UBR", "CBR", "VBR", "ABR"}; ++ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"}; + static const char *const aal_name[] = { + "---", "1", "2", "3/4", /* 0- 3 */ + "???", "5", "???", "???", /* 4- 7 */ +--- a/net/atm/common.c ++++ b/net/atm/common.c +@@ -62,11 +62,17 @@ static void vcc_remove_socket(struct soc + write_unlock_irq(&vcc_sklist_lock); + } + ++struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL; ++EXPORT_SYMBOL(ifx_atm_alloc_tx); ++ + static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size) + { + struct sk_buff *skb; + struct sock *sk = sk_atm(vcc); + ++ if (ifx_atm_alloc_tx != NULL) ++ return ifx_atm_alloc_tx(vcc, size); ++ + if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) { + pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n", + sk_wmem_alloc_get(sk), size, sk->sk_sndbuf); diff --git a/target/linux/lantiq/patches/203-owrt-cmdline.patch b/target/linux/lantiq/patches/203-owrt-cmdline.patch new file mode 100644 index 0000000000..cd7c95a9c7 --- /dev/null +++ b/target/linux/lantiq/patches/203-owrt-cmdline.patch @@ -0,0 +1,45 @@ +--- a/arch/mips/lantiq/prom.c ++++ b/arch/mips/lantiq/prom.c +@@ -43,6 +43,34 @@ void prom_free_prom_memory(void) + { + } + ++#ifdef CONFIG_IMAGE_CMDLINE_HACK ++extern char __image_cmdline[]; ++ ++static void __init ++prom_init_image_cmdline(void) ++{ ++ char *p = __image_cmdline; ++ int replace = 0; ++ ++ if (*p == '-') { ++ replace = 1; ++ p++; ++ } ++ ++ if (*p == '\0') ++ return; ++ ++ if (replace) { ++ strlcpy(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } else { ++ strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); ++ strlcat(arcs_cmdline, p, sizeof(arcs_cmdline)); ++ } ++} ++#else ++static void __init prom_init_image_cmdline(void) { return; } ++#endif ++ + static void __init prom_init_cmdline(void) + { + int argc = fw_arg0; +@@ -59,6 +87,7 @@ static void __init prom_init_cmdline(voi + strlcat(arcs_cmdline, " ", sizeof(arcs_cmdline)); + } + } ++ prom_init_image_cmdline(); + } + + void __iomem *ltq_remap_resource(struct resource *res) diff --git a/target/linux/lantiq/patches/204-owrt-dm9000-polling.patch b/target/linux/lantiq/patches/204-owrt-dm9000-polling.patch new file mode 100644 index 0000000000..11fa5396a5 --- /dev/null +++ b/target/linux/lantiq/patches/204-owrt-dm9000-polling.patch @@ -0,0 +1,117 @@ +--- a/drivers/net/dm9000.c ++++ b/drivers/net/dm9000.c +@@ -19,6 +19,7 @@ + * Sascha Hauer <s.hauer@pengutronix.de> + */ + ++#define DEBUG + #include <linux/module.h> + #include <linux/ioport.h> + #include <linux/netdevice.h> +@@ -126,6 +127,8 @@ typedef struct board_info { + struct delayed_work phy_poll; + struct net_device *ndev; + ++ struct delayed_work irq_poll; /* for use in irq polling mode */ ++ + spinlock_t lock; + + struct mii_if_info mii; +@@ -839,6 +842,8 @@ static void dm9000_timeout(struct net_de + netif_stop_queue(dev); + dm9000_reset(db); + dm9000_init_dm9000(dev); ++ dm9000_reset(db); ++ dm9000_init_dm9000(dev); + /* We can accept TX packets again */ + dev->trans_start = jiffies; /* prevent tx timeout */ + netif_wake_queue(dev); +@@ -910,6 +915,12 @@ dm9000_start_xmit(struct sk_buff *skb, s + /* free this SKB */ + dev_kfree_skb(skb); + ++ /* directly poll afterwards */ ++ if (dev->irq == -1) { ++ cancel_delayed_work(&db->irq_poll); ++ schedule_delayed_work(&db->irq_poll, 1); ++ } ++ + return NETDEV_TX_OK; + } + +@@ -1151,6 +1162,18 @@ static void dm9000_poll_controller(struc + } + #endif + ++static void dm9000_poll_irq(struct work_struct *w) ++{ ++ struct delayed_work *dw = to_delayed_work(w); ++ board_info_t *db = container_of(dw, board_info_t, irq_poll); ++ struct net_device *ndev = db->ndev; ++ ++ dm9000_interrupt(0, ndev); ++ ++ if (netif_running(ndev)) ++ schedule_delayed_work(&db->irq_poll, HZ /100); ++} ++ + /* + * Open the interface. + * The interface is opened whenever "ifconfig" actives it. +@@ -1164,14 +1187,15 @@ dm9000_open(struct net_device *dev) + if (netif_msg_ifup(db)) + dev_dbg(db->dev, "enabling %s\n", dev->name); + +- /* If there is no IRQ type specified, default to something that +- * may work, and tell the user that this is a problem */ ++ if (dev->irq != -1) { ++ /* If there is no IRQ type specified, default to something that ++ * may work, and tell the user that this is a problem */ + +- if (irqflags == IRQF_TRIGGER_NONE) +- dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); +- +- irqflags |= IRQF_SHARED; ++ if (irqflags == IRQF_TRIGGER_NONE) ++ dev_warn(db->dev, "WARNING: no IRQ resource flags set.\n"); + ++ irqflags |= IRQF_SHARED; ++ } + /* GPIO0 on pre-activate PHY, Reg 1F is not set by reset */ + iow(db, DM9000_GPR, 0); /* REG_1F bit0 activate phyxcer */ + mdelay(1); /* delay needs by DM9000B */ +@@ -1180,8 +1204,14 @@ dm9000_open(struct net_device *dev) + dm9000_reset(db); + dm9000_init_dm9000(dev); + +- if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev)) +- return -EAGAIN; ++ /* testing: init a second time */ ++ dm9000_reset(db); ++ dm9000_init_dm9000(dev); ++ ++ if (dev->irq != -1) { ++ if (request_irq(dev->irq, dm9000_interrupt, irqflags, dev->name, dev)) ++ return -EAGAIN; ++ } + + /* Init driver variable */ + db->dbug_cnt = 0; +@@ -1189,6 +1219,9 @@ dm9000_open(struct net_device *dev) + mii_check_media(&db->mii, netif_msg_link(db), 1); + netif_start_queue(dev); + ++ if (dev->irq == -1) ++ schedule_delayed_work(&db->irq_poll, HZ / 100); ++ + dm9000_schedule_poll(db); + + return 0; +@@ -1386,6 +1419,7 @@ dm9000_probe(struct platform_device *pde + mutex_init(&db->addr_lock); + + INIT_DELAYED_WORK(&db->phy_poll, dm9000_poll_work); ++ INIT_DELAYED_WORK(&db->irq_poll, dm9000_poll_irq); + + db->addr_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); + db->data_res = platform_get_resource(pdev, IORESOURCE_MEM, 1); diff --git a/target/linux/lantiq/patches/205-owrt-gpio-export.patch b/target/linux/lantiq/patches/205-owrt-gpio-export.patch new file mode 100644 index 0000000000..710d2745c9 --- /dev/null +++ b/target/linux/lantiq/patches/205-owrt-gpio-export.patch @@ -0,0 +1,52 @@ +--- a/drivers/gpio/gpiolib.c ++++ b/drivers/gpio/gpiolib.c +@@ -64,9 +64,9 @@ struct gpio_desc { + #define GPIO_FLAGS_MASK ((1 << ID_SHIFT) - 1) + #define GPIO_TRIGGER_MASK (BIT(FLAG_TRIG_FALL) | BIT(FLAG_TRIG_RISE)) + +-#ifdef CONFIG_DEBUG_FS ++//#ifdef CONFIG_DEBUG_FS + const char *label; +-#endif ++//#endif + }; + static struct gpio_desc gpio_desc[ARCH_NR_GPIOS]; + +@@ -76,9 +76,9 @@ static DEFINE_IDR(dirent_idr); + + static inline void desc_set_label(struct gpio_desc *d, const char *label) + { +-#ifdef CONFIG_DEBUG_FS ++//#ifdef CONFIG_DEBUG_FS + d->label = label; +-#endif ++//#endif + } + + /* Warn when drivers omit gpio_request() calls -- legal but ill-advised +@@ -727,7 +727,8 @@ int gpio_export(unsigned gpio, bool dire + + if (desc->chip->names && desc->chip->names[gpio - desc->chip->base]) + ioname = desc->chip->names[gpio - desc->chip->base]; +- ++ else ++ ioname = gpio_desc[gpio].label; + if (status == 0) { + struct device *dev; + +@@ -1347,11 +1348,11 @@ const char *gpiochip_is_requested(struct + return NULL; + if (test_bit(FLAG_REQUESTED, &gpio_desc[gpio].flags) == 0) + return NULL; +-#ifdef CONFIG_DEBUG_FS ++//#ifdef CONFIG_DEBUG_FS + return gpio_desc[gpio].label; +-#else +- return "?"; +-#endif ++//#else ++// return "?"; ++//#endif + } + EXPORT_SYMBOL_GPL(gpiochip_is_requested); + diff --git a/target/linux/lantiq/patches/210-machtypes.patch b/target/linux/lantiq/patches/210-machtypes.patch new file mode 100644 index 0000000000..f4e86b9211 --- /dev/null +++ b/target/linux/lantiq/patches/210-machtypes.patch @@ -0,0 +1,326 @@ +Index: linux-3.1/arch/mips/lantiq/machtypes.h +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/machtypes.h 2011-11-03 10:32:53.117317313 +0100 ++++ linux-3.1/arch/mips/lantiq/machtypes.h 2011-11-03 15:57:57.106151011 +0100 +@@ -20,9 +20,34 @@ + LANTIQ_MACH_EASY98000, /* Falcon Eval Board, NOR Flash */ + LANTIQ_MACH_EASY98000SF, /* Falcon Eval Board, Serial Flash */ + LANTIQ_MACH_EASY98000NAND, /* Falcon Eval Board, NAND Flash */ ++ LANTIQ_MACH_EASY98020, /* EASY98020 Eval Board */ ++ LANTIQ_MACH_EASY98020_1LAN, /* EASY98020 Eval Board (1 LAN port) */ ++ LANTIQ_MACH_EASY98020_2LAN, /* EASY98020 Eval Board (2 LAN port) */ ++ LANTIQ_MACH_95C3AM1, /* 95C3AM1 Eval Board */ + + /* FRITZ!BOX */ + LANTIQ_MACH_FRITZ3370, /* FRITZ!BOX 3370 vdsl cpe */ ++ ++ /* Arcadyan */ ++ LANTIQ_MACH_ARV3527P, /* Arcor easybox a401 */ ++ LANTIQ_MACH_ARV4510PW, /* Wippies Homebox */ ++ LANTIQ_MACH_ARV4518PW, /* Airties WAV-221, SMC-7908A-ISP */ ++ LANTIQ_MACH_ARV4520PW, /* Airties WAV-281, Arcor EasyboxA800 */ ++ LANTIQ_MACH_ARV452CPW, /* Arcor EasyboxA801 */ ++ LANTIQ_MACH_ARV4525PW, /* Speedport W502V */ ++ LANTIQ_MACH_ARV7525PW, /* Speedport W303V */ ++ LANTIQ_MACH_ARV752DPW, /* Arcor easybox a802 */ ++ LANTIQ_MACH_ARV752DPW22, /* Arcor easybox a803 */ ++ LANTIQ_MACH_ARV7518PW, /* ASTORIA */ ++ ++ /* Netgear */ ++ LANTIQ_MACH_DGN3500B, /* Netgear DGN3500 */ ++ ++ /* Gigaset */ ++ LANTIQ_MACH_GIGASX76X, /* Gigaset SX76x */ ++ ++ /* Buffalo */ ++ LANTIQ_MACH_WBMR, /* WBMR-HP-G300H */ + }; + + #endif +Index: linux-3.1/arch/mips/lantiq/xway/Kconfig +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/xway/Kconfig 2011-11-03 10:32:53.117317313 +0100 ++++ linux-3.1/arch/mips/lantiq/xway/Kconfig 2011-11-03 10:32:53.409317325 +0100 +@@ -6,6 +6,22 @@ + bool "Easy50712 - Danube" + default y + ++config LANTIQ_MACH_ARV45XX ++ bool "ARV45XX" ++ default y ++ ++config LANTIQ_MACH_NETGEAR ++ bool "Netgear" ++ default y ++ ++config LANTIQ_MACH_GIGASX76X ++ bool "GIGASX76X" ++ default y ++ ++config LANTIQ_MACH_WBMR ++ bool "WBMR-HP-G300H" ++ default y ++ + endmenu + + endif +Index: linux-3.1/arch/mips/lantiq/xway/Makefile +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/xway/Makefile 2011-11-03 10:32:53.117317313 +0100 ++++ linux-3.1/arch/mips/lantiq/xway/Makefile 2011-11-03 15:57:59.222151170 +0100 +@@ -7,3 +7,7 @@ + obj-$(CONFIG_LANTIQ_MACH_EASY50712) += mach-easy50712.o + obj-$(CONFIG_LANTIQ_MACH_EASY50601) += mach-easy50601.o + obj-$(CONFIG_LANTIQ_MACH_FRITZ3370) += mach-fritz.o ++obj-$(CONFIG_LANTIQ_MACH_ARV45XX) += mach-arv45xx.o ++obj-$(CONFIG_LANTIQ_MACH_NETGEAR) += mach-netgear.o ++obj-$(CONFIG_LANTIQ_MACH_GIGASX76X) += mach-gigasx76x.o ++obj-$(CONFIG_LANTIQ_MACH_WBMR) += mach-wbmr.o +Index: linux-3.1/arch/mips/lantiq/falcon/Kconfig +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/falcon/Kconfig 2011-11-03 10:32:52.697317294 +0100 ++++ linux-3.1/arch/mips/lantiq/falcon/Kconfig 2011-11-03 10:32:53.409317325 +0100 +@@ -6,6 +6,14 @@ + bool "Easy98000" + default y + ++config LANTIQ_MACH_EASY98020 ++ bool "Easy98020" ++ default y ++ ++config LANTIQ_MACH_95C3AM1 ++ bool "95C3AM1" ++ default y ++ + endmenu + + endif +Index: linux-3.1/arch/mips/lantiq/falcon/Makefile +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/falcon/Makefile 2011-11-03 10:32:53.033317309 +0100 ++++ linux-3.1/arch/mips/lantiq/falcon/Makefile 2011-11-03 10:32:53.409317325 +0100 +@@ -1,2 +1,6 @@ + obj-y := clk.o prom.o reset.o sysctrl.o devices.o gpio.o softdog_vpe.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += addon-easy98000.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98000) += dev-leds-easy98000-cpld.o + obj-$(CONFIG_LANTIQ_MACH_EASY98000) += mach-easy98000.o ++obj-$(CONFIG_LANTIQ_MACH_EASY98020) += mach-easy98020.o ++obj-$(CONFIG_LANTIQ_MACH_95C3AM1) += mach-95C3AM1.o +Index: linux-3.1/arch/mips/lantiq/falcon/mach-easy98000.c +=================================================================== +--- linux-3.1.orig/arch/mips/lantiq/falcon/mach-easy98000.c 2011-11-03 10:32:52.805317298 +0100 ++++ linux-3.1/arch/mips/lantiq/falcon/mach-easy98000.c 2011-11-03 10:32:53.413317324 +0100 +@@ -1,23 +1,38 @@ +-/* +- * This program is free software; you can redistribute it and/or modify it +- * under the terms of the GNU General Public License version 2 as published +- * by the Free Software Foundation. +- * +- * Copyright (C) 2011 Thomas Langer <thomas.langer@lantiq.com> +- * Copyright (C) 2011 John Crispin <blogic@openwrt.org> +- */ +- ++#include <linux/init.h> + #include <linux/platform_device.h> ++#include <linux/leds.h> ++#include <linux/gpio.h> ++#include <linux/gpio_buttons.h> ++#include <linux/etherdevice.h> ++#include <linux/mtd/mtd.h> + #include <linux/mtd/partitions.h> ++#include <linux/mtd/physmap.h> ++#include <linux/input.h> ++#include <linux/interrupt.h> ++#include <linux/dm9000.h> ++#include <linux/i2c.h> ++#include <linux/i2c-gpio.h> + #include <linux/spi/spi.h> + #include <linux/spi/spi_gpio.h> + #include <linux/spi/eeprom.h> ++#include <falcon/lantiq_soc.h> + + #include "../machtypes.h" + + #include "devices.h" ++#include "dev-leds-gpio.h" ++ ++#define EASY98000_GPIO_LED_0 9 ++#define EASY98000_GPIO_LED_1 10 ++#define EASY98000_GPIO_LED_2 11 ++#define EASY98000_GPIO_LED_3 12 ++#define EASY98000_GPIO_LED_4 13 ++#define EASY98000_GPIO_LED_5 14 ++ ++extern unsigned char ltq_ethaddr[6]; + +-static struct mtd_partition easy98000_nor_partitions[] = { ++static struct mtd_partition easy98000_nor_partitions[] = ++{ + { + .name = "uboot", + .offset = 0x0, +@@ -35,7 +50,7 @@ + }, + }; + +-struct physmap_flash_data easy98000_nor_flash_data = { ++static struct physmap_flash_data easy98000_nor_flash_data = { + .nr_parts = ARRAY_SIZE(easy98000_nor_partitions), + .parts = easy98000_nor_partitions, + }; +@@ -55,12 +70,105 @@ + .platform_data = &easy98000_spi_flash_platform_data + }; + ++static struct gpio_led easy98000_leds_gpio[] __initdata = { ++ { ++ .name = "easy98000:green:0", ++ .gpio = EASY98000_GPIO_LED_0, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:1", ++ .gpio = EASY98000_GPIO_LED_1, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:2", ++ .gpio = EASY98000_GPIO_LED_2, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:3", ++ .gpio = EASY98000_GPIO_LED_3, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:4", ++ .gpio = EASY98000_GPIO_LED_4, ++ .active_low = 0, ++ }, { ++ .name = "easy98000:green:5", ++ .gpio = EASY98000_GPIO_LED_5, ++ .active_low = 0, ++ } ++}; ++ ++#define CONFIG_DM9000_BASE 0x14000000 ++#define DM9000_IO (CONFIG_DM9000_BASE + 3) ++#define DM9000_DATA (CONFIG_DM9000_BASE + 1) ++ ++static struct dm9000_plat_data dm9000_plat_data = { ++ .flags = DM9000_PLATF_8BITONLY, ++ //.dev_addr = { }, /* possibility to provide an ethernet address for the chip */ ++}; ++ ++static struct resource dm9000_resources[] = { ++ MEM_RES("dm9000_io", DM9000_IO, DM9000_IO), ++ MEM_RES("dm9000_data", DM9000_DATA, DM9000_DATA), ++ [2] = { ++ /* with irq (210 -> gpio 110) the driver is very unreliable */ ++ .start = -1, /* use polling */ ++ .end = -1, ++ .flags = IORESOURCE_IRQ | IRQF_TRIGGER_LOW, ++ }, ++}; ++ ++static struct platform_device dm9000_platform = { ++ .name = "dm9000", ++ .id = 0, ++ .num_resources = ARRAY_SIZE(dm9000_resources), ++ .resource = dm9000_resources, ++ .dev = { ++ .platform_data = (void *) &dm9000_plat_data, ++ } ++}; ++ ++extern int easy98000_addon_has_dm9000(void); ++static void __init register_davicom(void) ++{ ++ if (!easy98000_addon_has_dm9000()) ++ return; ++ ++ if (!is_valid_ether_addr(ltq_ethaddr)) ++ random_ether_addr(dm9000_plat_data.dev_addr); ++ else { ++ memcpy(dm9000_plat_data.dev_addr, ltq_ethaddr, 6); ++ /* change to "Locally Administered Address" */ ++ dm9000_plat_data.dev_addr[0] |= 0x2; ++ } ++ platform_device_register(&dm9000_platform); ++} ++ ++static struct i2c_gpio_platform_data easy98000_i2c_gpio_data = { ++ .sda_pin = 107, ++ .scl_pin = 108, ++}; ++ ++static struct platform_device easy98000_i2c_gpio_device = { ++ .name = "i2c-gpio", ++ .id = 0, ++ .dev = { ++ .platform_data = &easy98000_i2c_gpio_data, ++ } ++}; ++ ++void __init register_easy98000_cpld(void) ++{ ++ platform_device_register_simple("easy98000_cpld_led", 0, NULL, 0); ++ platform_device_register_simple("easy98000_addon", 0, NULL, 0); ++} ++ + /* setup gpio based spi bus/device for access to the eeprom on the board */ +-#define SPI_GPIO_MRST 102 +-#define SPI_GPIO_MTSR 103 +-#define SPI_GPIO_CLK 104 +-#define SPI_GPIO_CS0 105 +-#define SPI_GPIO_CS1 106 ++#define SPI_GPIO_MRST 102 ++#define SPI_GPIO_MTSR 103 ++#define SPI_GPIO_CLK 104 ++#define SPI_GPIO_CS0 105 ++#define SPI_GPIO_CS1 106 + #define SPI_GPIO_BUS_NUM 1 + + static struct spi_gpio_platform_data easy98000_spi_gpio_data = { +@@ -93,29 +201,36 @@ + .platform_data = &at25160n, + }; + +-static void __init +-easy98000_init_common(void) ++static void __init easy98000_spi_gpio_init(void) + { + spi_register_board_info(&easy98000_spi_gpio_devices, 1); + platform_device_register(&easy98000_spi_gpio_device); + } + +-static void __init +-easy98000_init(void) ++static void __init easy98000_init_common(void) ++{ ++ falcon_register_i2c(); ++ platform_device_register(&easy98000_i2c_gpio_device); ++ register_davicom(); ++ ltq_add_device_leds_gpio(-1, ARRAY_SIZE(easy98000_leds_gpio), ++ easy98000_leds_gpio); ++ register_easy98000_cpld(); ++ easy98000_spi_gpio_init(); ++} ++ ++static void __init easy98000_init(void) + { + easy98000_init_common(); + ltq_register_nor(&easy98000_nor_flash_data); + } + +-static void __init +-easy98000sf_init(void) ++static void __init easy98000sf_init(void) + { + easy98000_init_common(); + falcon_register_spi_flash(&easy98000_spi_flash_data); + } + +-static void __init +-easy98000nand_init(void) ++static void __init easy98000nand_init(void) + { + easy98000_init_common(); + falcon_register_nand(); diff --git a/target/linux/lantiq/patches/211-devices.patch b/target/linux/lantiq/patches/211-devices.patch new file mode 100644 index 0000000000..92c2902d1c --- /dev/null +++ b/target/linux/lantiq/patches/211-devices.patch @@ -0,0 +1,190 @@ +--- a/arch/mips/lantiq/devices.c ++++ b/arch/mips/lantiq/devices.c +@@ -18,6 +18,7 @@ + #include <linux/time.h> + #include <linux/io.h> + #include <linux/gpio.h> ++#include <linux/dma-mapping.h> + + #include <asm/bootinfo.h> + #include <asm/irq.h> +@@ -100,3 +101,20 @@ void __init ltq_register_pci(struct ltq_ + pr_err("kernel is compiled without PCI support\n"); + } + #endif ++ ++static unsigned int *cp1_base = 0; ++unsigned int* ++ltq_get_cp1_base(void) ++{ ++ return cp1_base; ++} ++EXPORT_SYMBOL(ltq_get_cp1_base); ++ ++void __init ++ltq_register_tapi(void) ++{ ++#define CP1_SIZE (1 << 20) ++ dma_addr_t dma; ++ cp1_base = ++ (void*)CPHYSADDR(dma_alloc_coherent(NULL, CP1_SIZE, &dma, GFP_ATOMIC)); ++} +--- a/arch/mips/lantiq/devices.h ++++ b/arch/mips/lantiq/devices.h +@@ -23,5 +23,6 @@ extern void ltq_register_nor(struct phys + extern void ltq_register_wdt(void); + extern void ltq_register_asc(int port); + extern void ltq_register_pci(struct ltq_pci_data *data); ++extern void ltq_register_tapi(void); + + #endif +--- a/arch/mips/lantiq/xway/Makefile ++++ b/arch/mips/lantiq/xway/Makefile +@@ -1,5 +1,7 @@ + obj-y := sysctrl.o reset.o gpio.o gpio_stp.o gpio_ebu.o devices.o dma.o nand.o timer.o + ++obj-y += dev-dwc_otg.o ++ + obj-$(CONFIG_SOC_XWAY) += clk-xway.o prom-xway.o + obj-$(CONFIG_SOC_AMAZON_SE) += clk-ase.o prom-ase.o + obj-$(CONFIG_SOC_VR9) += clk-vr9.o prom-vr9.o +--- a/arch/mips/lantiq/xway/devices.c ++++ b/arch/mips/lantiq/xway/devices.c +@@ -19,6 +19,7 @@ + #include <linux/time.h> + #include <linux/io.h> + #include <linux/gpio.h> ++#include <linux/spi/spi.h> + + #include <asm/bootinfo.h> + #include <asm/irq.h> +@@ -99,3 +100,98 @@ ltq_register_etop(struct ltq_eth_data *e + platform_device_register(<q_etop); + } + } ++ ++/* madwifi */ ++int lantiq_emulate_madwifi_eep = 0; ++EXPORT_SYMBOL(lantiq_emulate_madwifi_eep); ++ ++int lantiq_madwifi_eep_addr = 0; ++EXPORT_SYMBOL(lantiq_madwifi_eep_addr); ++ ++void __init ++ltq_register_madwifi_eep(unsigned long long addr) ++{ ++ lantiq_madwifi_eep_addr = addr; ++ lantiq_emulate_madwifi_eep = 1; ++} ++ ++/* ebu */ ++static struct resource ltq_ebu_resource = ++{ ++ .name = "gpio_ebu", ++ .start = LTQ_EBU_GPIO_START, ++ .end = LTQ_EBU_GPIO_START + LTQ_EBU_GPIO_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++}; ++ ++static struct platform_device ltq_ebu = ++{ ++ .name = "ltq_ebu", ++ .resource = <q_ebu_resource, ++ .num_resources = 1, ++}; ++ ++void __init ++ltq_register_gpio_ebu(unsigned int value) ++{ ++ ltq_ebu.dev.platform_data = (void*) value; ++ platform_device_register(<q_ebu); ++} ++ ++/* gpio buttons */ ++static struct gpio_buttons_platform_data ltq_gpio_buttons_platform_data; ++ ++static struct platform_device ltq_gpio_buttons_platform_device = ++{ ++ .name = "gpio-buttons", ++ .id = 0, ++ .dev = { ++ .platform_data = (void *) <q_gpio_buttons_platform_data, ++ }, ++}; ++ ++void __init ++ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt) ++{ ++ ltq_gpio_buttons_platform_data.buttons = buttons; ++ ltq_gpio_buttons_platform_data.nbuttons = cnt; ++ platform_device_register(<q_gpio_buttons_platform_device); ++} ++ ++static struct resource ltq_spi_resources[] = { ++ { ++ .start = LTQ_SSC_BASE_ADDR, ++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ IRQ_RES(spi_tx, LTQ_SSC_TIR), ++ IRQ_RES(spi_rx, LTQ_SSC_RIR), ++ IRQ_RES(spi_err, LTQ_SSC_EIR), ++}; ++ ++static struct resource ltq_spi_resources_ar9[] = { ++ { ++ .start = LTQ_SSC_BASE_ADDR, ++ .end = LTQ_SSC_BASE_ADDR + LTQ_SSC_SIZE - 1, ++ .flags = IORESOURCE_MEM, ++ }, ++ IRQ_RES(spi_tx, LTQ_SSC_TIR_AR9), ++ IRQ_RES(spi_rx, LTQ_SSC_RIR_AR9), ++ IRQ_RES(spi_err, LTQ_SSC_EIR), ++}; ++ ++static struct platform_device ltq_spi = { ++ .name = "ltq-spi", ++ .resource = ltq_spi_resources, ++ .num_resources = ARRAY_SIZE(ltq_spi_resources), ++}; ++ ++void __init ltq_register_spi(struct ltq_spi_platform_data *pdata, ++ struct spi_board_info const *info, unsigned n) ++{ ++ if(ltq_is_ar9()) ++ ltq_spi.resource = ltq_spi_resources_ar9; ++ spi_register_board_info(info, n); ++ ltq_spi.dev.platform_data = pdata; ++ platform_device_register(<q_spi); ++} +--- a/arch/mips/lantiq/xway/devices.h ++++ b/arch/mips/lantiq/xway/devices.h +@@ -11,10 +11,17 @@ + + #include "../devices.h" + #include <linux/phy.h> ++#include <linux/spi/spi.h> ++#include <linux/gpio_buttons.h> + + extern void ltq_register_gpio(void); + extern void ltq_register_gpio_stp(void); + extern void ltq_register_ase_asc(void); + extern void ltq_register_etop(struct ltq_eth_data *eth); ++extern void ltq_register_gpio_ebu(unsigned int value); ++extern void ltq_register_spi(struct ltq_spi_platform_data *pdata, ++ struct spi_board_info const *info, unsigned n); ++extern void ltq_register_madwifi_eep(unsigned long long addr); ++extern void ltq_register_gpio_buttons(struct gpio_button *buttons, int cnt); + + #endif +--- a/arch/mips/lantiq/Makefile ++++ b/arch/mips/lantiq/Makefile +@@ -4,7 +4,7 @@ + # under the terms of the GNU General Public License version 2 as published + # by the Free Software Foundation. + +-obj-y := irq.o setup.o clk.o prom.o devices.o ++obj-y := irq.o setup.o clk.o prom.o devices.o dev-gpio-leds.o dev-gpio-buttons.o + + obj-$(CONFIG_EARLY_PRINTK) += early_printk.o + diff --git a/target/linux/lantiq/patches/800-fix-etop.patch b/target/linux/lantiq/patches/800-fix-etop.patch new file mode 100644 index 0000000000..462a2c313d --- /dev/null +++ b/target/linux/lantiq/patches/800-fix-etop.patch @@ -0,0 +1,67 @@ +--- a/drivers/net/lantiq_etop.c ++++ b/drivers/net/lantiq_etop.c +@@ -397,7 +397,10 @@ ltq_etop_get_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_gset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_gset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -405,7 +408,10 @@ ltq_etop_set_settings(struct net_device + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_ethtool_sset(priv->phydev, cmd); ++ if (priv->phydev) ++ return phy_ethtool_sset(priv->phydev, cmd); ++ else ++ return 0; + } + + static int +@@ -413,7 +419,10 @@ ltq_etop_nway_reset(struct net_device *d + { + struct ltq_etop_priv *priv = netdev_priv(dev); + +- return phy_start_aneg(priv->phydev); ++ if (priv->phydev) ++ return phy_start_aneg(priv->phydev); ++ else ++ return 0; + } + + static const struct ethtool_ops ltq_etop_ethtool_ops = { +@@ -615,7 +624,8 @@ ltq_etop_open(struct net_device *dev) + ltq_dma_open(&ch->dma); + napi_enable(&ch->napi); + } +- phy_start(priv->phydev); ++ if (priv->phydev) ++ phy_start(priv->phydev); + netif_tx_start_all_queues(dev); + return 0; + } +@@ -627,7 +637,8 @@ ltq_etop_stop(struct net_device *dev) + int i; + + netif_tx_stop_all_queues(dev); +- phy_stop(priv->phydev); ++ if (priv->phydev) ++ phy_stop(priv->phydev); + for (i = 0; i < MAX_DMA_CHAN; i++) { + struct ltq_etop_chan *ch = &priv->ch[i]; + +@@ -775,7 +786,7 @@ ltq_etop_init(struct net_device *dev) + ltq_etop_set_multicast_list(dev); + err = ltq_etop_mdio_init(dev); + if (err) +- goto err_netdev; ++ pr_warn("etop: mdio probe failed\n");; + return 0; + + err_netdev: diff --git a/target/linux/lantiq/patches/999-mtd.patch b/target/linux/lantiq/patches/999-mtd.patch new file mode 100644 index 0000000000..713dd1f376 --- /dev/null +++ b/target/linux/lantiq/patches/999-mtd.patch @@ -0,0 +1,11 @@ +--- a/drivers/mtd/maps/lantiq-flash.c ++++ b/drivers/mtd/maps/lantiq-flash.c +@@ -20,6 +20,8 @@ + #include <linux/platform_device.h> + #include <linux/mtd/physmap.h> + ++#include "../mtdcore.h" ++ + #include <lantiq_soc.h> + #include <lantiq_platform.h> + |