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-rw-r--r--target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch14
1 files changed, 13 insertions, 1 deletions
diff --git a/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch
index 956dd10368..93a2972599 100644
--- a/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch
+++ b/target/linux/lantiq/patches-4.1/0033-SPI-MIPS-lantiq-adds-spi-xway.patch
@@ -42,7 +42,7 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+obj-$(CONFIG_SPI_XWAY) += spi-xway.o
--- /dev/null
+++ b/drivers/spi/spi-xway.c
-@@ -0,0 +1,991 @@
+@@ -0,0 +1,1003 @@
+/*
+ * Lantiq SoC SPI controller
+ *
@@ -667,10 +667,22 @@ Signed-off-by: John Crispin <blogic@openwrt.org>
+static void ltq_spi_rxreq_set(struct ltq_spi *hw)
+{
+ u32 rxreq, rxreq_max, rxtodo;
++ u32 fstat, fifo_fill;
+
+ rxtodo = ltq_spi_reg_read(hw, LTQ_SPI_RXCNT) & LTQ_SPI_RXCNT_TODO_MASK;
+
+ /*
++ * Check if there is remaining data in the FIFO before starting a new
++ * receive request. The controller might have processed some more data
++ * since the last FIFO poll.
++ */
++ fstat = ltq_spi_reg_read(hw, LTQ_SPI_FSTAT);
++ fifo_fill = ((fstat >> LTQ_SPI_FSTAT_RXFFL_SHIFT)
++ & LTQ_SPI_FSTAT_RXFFL_MASK);
++ if (fifo_fill)
++ return;
++
++ /*
+ * In RX-only mode the serial clock is activated only after writing
+ * the expected amount of RX bytes into RXREQ register.
+ * To avoid receive overflows at high clocks it is better to request