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-rw-r--r--target/linux/lantiq/patches-3.6/0001-MIPS-lantiq-explicitly-enable-clkout-generation.patch34
-rw-r--r--target/linux/lantiq/patches-3.6/0002-MIPS-lantiq-split-up-IRQ-IM-ranges.patch195
-rw-r--r--target/linux/lantiq/patches-3.6/0003-MIPS-lantiq-timer-irq-can-be-different-to-7.patch84
-rw-r--r--target/linux/lantiq/patches-3.6/0004-MIPS-lantiq-dont-register-irq_chip-for-the-irq-casca.patch30
-rw-r--r--target/linux/lantiq/patches-3.6/0005-MIPS-lantiq-external-irq-sources-are-not-loaded-prop.patch31
-rw-r--r--target/linux/lantiq/patches-3.6/0006-MIPS-lantiq-adds-support-for-nmi-and-ejtag-bootrom-v.patch39
-rw-r--r--target/linux/lantiq/patches-3.6/0007-MIPS-lantiq-falcon-clocks-were-not-enabled-properly.patch30
-rw-r--r--target/linux/lantiq/patches-3.6/0008-MIPS-lantiq-enable-pci-clk-conditional-for-xrx200-So.patch31
-rw-r--r--target/linux/lantiq/patches-3.6/0009-MIPS-lantiq-adds-support-for-gptu-timers.patch246
-rw-r--r--target/linux/lantiq/patches-3.6/0010-OF-pinctrl-MIPS-lantiq-implement-lantiq-xway-pinctrl.patch1632
-rw-r--r--target/linux/lantiq/patches-3.6/0011-OF-pinctrl-MIPS-lantiq-adds-support-for-FALCON-SoC.patch554
-rw-r--r--target/linux/lantiq/patches-3.6/0012-Document-devicetree-add-OF-documents-for-lantiq-xway.patch121
-rw-r--r--target/linux/lantiq/patches-3.6/0013-Document-devicetree-add-OF-documents-for-lantiq-falc.patch108
-rw-r--r--target/linux/lantiq/patches-3.6/0014-MIPS-lantiq-make-use-of-__gpio_to_irq.patch33
-rw-r--r--target/linux/lantiq/patches-3.6/0015-GPIO-MIPS-lantiq-fix-overflow-inside-stp-xway-driver.patch34
-rw-r--r--target/linux/lantiq/patches-3.6/0016-mtd-lantiq-Add-NAND-support-on-Lantiq-XWAY-SoC.patch257
-rw-r--r--target/linux/lantiq/patches-3.6/0100-MIPS-lantiq-external-interrupt-units-not-loaded-prop.patch71
-rw-r--r--target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch27
-rw-r--r--target/linux/lantiq/patches-3.6/0102-MIPS-lantiq-fixes-dma-irq-ack.patch62
-rw-r--r--target/linux/lantiq/patches-3.6/0103-MIPS-lantiq-prom-code-invalidated-devicetree-memory.patch36
-rw-r--r--target/linux/lantiq/patches-3.6/0104-MIPS-lantiq-xway-split-ltq_reset_once-into-2-subfunc.patch60
-rw-r--r--target/linux/lantiq/patches-3.6/0105-MIPS-lantiq-xway-adds-reset-code-for-11G-PHYs.patch210
-rw-r--r--target/linux/lantiq/patches-3.6/0106-MIPS-lantiq-xway-adds-PHY11G-platform-code.patch607
-rw-r--r--target/linux/lantiq/patches-3.6/0107-MIPS-lantiq-add-xrx200-ethernet-clock.patch28
-rw-r--r--target/linux/lantiq/patches-3.6/0108-firmware-lantiq-adds-PHY11G-firmware-blobs.patch2221
-rw-r--r--target/linux/lantiq/patches-3.6/0109-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch47
-rw-r--r--target/linux/lantiq/patches-3.6/0110-NET-PHY-adds-driver-for-lantiq-PHY11G.patch228
-rw-r--r--target/linux/lantiq/patches-3.6/0111-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch807
-rw-r--r--target/linux/lantiq/patches-3.6/0112-NET-MIPS-lantiq-adds-xrx200-net.patch1382
-rw-r--r--target/linux/lantiq/patches-3.6/0113-EASY80920-dts-file.patch539
-rw-r--r--target/linux/lantiq/patches-3.6/0200-MIPS-dtb-image-hack.patch26
-rw-r--r--target/linux/lantiq/patches-3.6/0201-lantiq-dtb-image-hack.patch58
-rw-r--r--target/linux/lantiq/patches-3.6/0300-owrt-mtd-split.patch230
-rw-r--r--target/linux/lantiq/patches-3.6/0301-owrt-atm.patch80
34 files changed, 0 insertions, 10178 deletions
diff --git a/target/linux/lantiq/patches-3.6/0001-MIPS-lantiq-explicitly-enable-clkout-generation.patch b/target/linux/lantiq/patches-3.6/0001-MIPS-lantiq-explicitly-enable-clkout-generation.patch
deleted file mode 100644
index 50428d6e6d..0000000000
--- a/target/linux/lantiq/patches-3.6/0001-MIPS-lantiq-explicitly-enable-clkout-generation.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From 98dbc5764d8b6fa9cabe316fe725281703bf0fc6 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 24 Jul 2012 08:56:41 +0200
-Subject: [PATCH] MIPS: lantiq: explicitly enable clkout generation
-
-Previously we relied on the bootloader to have enabled this bit. However some
-bootloaders seem to not enable this for us.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4120/
----
- arch/mips/lantiq/xway/sysctrl.c | 2 ++
- 1 file changed, 2 insertions(+)
-
-diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
-index befbb76..8430983 100644
---- a/arch/mips/lantiq/xway/sysctrl.c
-+++ b/arch/mips/lantiq/xway/sysctrl.c
-@@ -187,10 +187,12 @@ static int clkout_enable(struct clk *clk)
- for (i = 0; i < 4; i++) {
- if (clk->rates[i] == clk->rate) {
- int shift = 14 - (2 * clk->module);
-+ int enable = 7 - clk->module;
- unsigned int val = ltq_cgu_r32(ifccr);
-
- val &= ~(3 << shift);
- val |= i << shift;
-+ val |= enable;
- ltq_cgu_w32(val, ifccr);
- return 0;
- }
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0002-MIPS-lantiq-split-up-IRQ-IM-ranges.patch b/target/linux/lantiq/patches-3.6/0002-MIPS-lantiq-split-up-IRQ-IM-ranges.patch
deleted file mode 100644
index 17d3ab7e37..0000000000
--- a/target/linux/lantiq/patches-3.6/0002-MIPS-lantiq-split-up-IRQ-IM-ranges.patch
+++ /dev/null
@@ -1,195 +0,0 @@
-From 61fa969f27ec58296544bf94d058f3aa704cb8d9 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 11:39:57 +0000
-Subject: [PATCH 2/9] MIPS: lantiq: split up IRQ IM ranges
-
-Up to now all our SoCs had the 5 IM ranges in a consecutive order. To accomodate
-the SVIP we need to support IM ranges that are scattered inside the register range.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4237/
----
- .../include/asm/mach-lantiq/falcon/falcon_irq.h | 2 +
- .../mips/include/asm/mach-lantiq/xway/lantiq_irq.h | 2 +
- arch/mips/lantiq/irq.c | 60 +++++++++++---------
- 3 files changed, 36 insertions(+), 28 deletions(-)
-
-diff --git a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-index 318f982..c6b63a4 100644
---- a/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/falcon_irq.h
-@@ -20,4 +20,6 @@
-
- #define MIPS_CPU_TIMER_IRQ 7
-
-+#define MAX_IM 5
-+
- #endif /* _FALCON_IRQ__ */
-diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-index aa0b3b8..5eadfe5 100644
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_irq.h
-@@ -21,4 +21,6 @@
-
- #define MIPS_CPU_TIMER_IRQ 7
-
-+#define MAX_IM 5
-+
- #endif
-diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
-index 57c1a4e..a2699a70 100644
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -55,8 +55,8 @@
- */
- #define LTQ_ICU_EBU_IRQ 22
-
--#define ltq_icu_w32(x, y) ltq_w32((x), ltq_icu_membase + (y))
--#define ltq_icu_r32(x) ltq_r32(ltq_icu_membase + (x))
-+#define ltq_icu_w32(m, x, y) ltq_w32((x), ltq_icu_membase[m] + (y))
-+#define ltq_icu_r32(m, x) ltq_r32(ltq_icu_membase[m] + (x))
-
- #define ltq_eiu_w32(x, y) ltq_w32((x), ltq_eiu_membase + (y))
- #define ltq_eiu_r32(x) ltq_r32(ltq_eiu_membase + (x))
-@@ -82,17 +82,17 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
- };
-
- static int exin_avail;
--static void __iomem *ltq_icu_membase;
-+static void __iomem *ltq_icu_membase[MAX_IM];
- static void __iomem *ltq_eiu_membase;
-
- void ltq_disable_irq(struct irq_data *d)
- {
- u32 ier = LTQ_ICU_IM0_IER;
- int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
-+ int im = offset / INT_NUM_IM_OFFSET;
-
-- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
- offset %= INT_NUM_IM_OFFSET;
-- ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
-+ ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
- }
-
- void ltq_mask_and_ack_irq(struct irq_data *d)
-@@ -100,32 +100,31 @@ void ltq_mask_and_ack_irq(struct irq_data *d)
- u32 ier = LTQ_ICU_IM0_IER;
- u32 isr = LTQ_ICU_IM0_ISR;
- int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
-+ int im = offset / INT_NUM_IM_OFFSET;
-
-- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
-- isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
- offset %= INT_NUM_IM_OFFSET;
-- ltq_icu_w32(ltq_icu_r32(ier) & ~BIT(offset), ier);
-- ltq_icu_w32(BIT(offset), isr);
-+ ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
-+ ltq_icu_w32(im, BIT(offset), isr);
- }
-
- static void ltq_ack_irq(struct irq_data *d)
- {
- u32 isr = LTQ_ICU_IM0_ISR;
- int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
-+ int im = offset / INT_NUM_IM_OFFSET;
-
-- isr += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
- offset %= INT_NUM_IM_OFFSET;
-- ltq_icu_w32(BIT(offset), isr);
-+ ltq_icu_w32(im, BIT(offset), isr);
- }
-
- void ltq_enable_irq(struct irq_data *d)
- {
- u32 ier = LTQ_ICU_IM0_IER;
- int offset = d->hwirq - MIPS_CPU_IRQ_CASCADE;
-+ int im = offset / INT_NUM_IM_OFFSET;
-
-- ier += LTQ_ICU_OFFSET * (offset / INT_NUM_IM_OFFSET);
- offset %= INT_NUM_IM_OFFSET;
-- ltq_icu_w32(ltq_icu_r32(ier) | BIT(offset), ier);
-+ ltq_icu_w32(im, ltq_icu_r32(im, ier) | BIT(offset), ier);
- }
-
- static unsigned int ltq_startup_eiu_irq(struct irq_data *d)
-@@ -192,7 +191,7 @@ static void ltq_hw_irqdispatch(int module)
- {
- u32 irq;
-
-- irq = ltq_icu_r32(LTQ_ICU_IM0_IOSR + (module * LTQ_ICU_OFFSET));
-+ irq = ltq_icu_r32(module, LTQ_ICU_IM0_IOSR);
- if (irq == 0)
- return;
-
-@@ -275,7 +274,7 @@ asmlinkage void plat_irq_dispatch(void)
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
-- for (i = 0; i < 5; i++) {
-+ for (i = 0; i < MAX_IM; i++) {
- if (pending & (CAUSEF_IP2 << i)) {
- ltq_hw_irqdispatch(i);
- goto out;
-@@ -318,15 +317,19 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
- struct resource res;
- int i;
-
-- if (of_address_to_resource(node, 0, &res))
-- panic("Failed to get icu memory range");
-+ for (i = 0; i < MAX_IM; i++) {
-+ if (of_address_to_resource(node, i, &res))
-+ panic("Failed to get icu memory range");
-
-- if (request_mem_region(res.start, resource_size(&res), res.name) < 0)
-- pr_err("Failed to request icu memory");
-+ if (request_mem_region(res.start, resource_size(&res),
-+ res.name) < 0)
-+ pr_err("Failed to request icu memory");
-
-- ltq_icu_membase = ioremap_nocache(res.start, resource_size(&res));
-- if (!ltq_icu_membase)
-- panic("Failed to remap icu memory");
-+ ltq_icu_membase[i] = ioremap_nocache(res.start,
-+ resource_size(&res));
-+ if (!ltq_icu_membase[i])
-+ panic("Failed to remap icu memory");
-+ }
-
- /* the external interrupts are optional and xway only */
- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
-@@ -351,17 +354,17 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
- }
-
- /* turn off all irqs by default */
-- for (i = 0; i < 5; i++) {
-+ for (i = 0; i < MAX_IM; i++) {
- /* make sure all irqs are turned off by default */
-- ltq_icu_w32(0, LTQ_ICU_IM0_IER + (i * LTQ_ICU_OFFSET));
-+ ltq_icu_w32(i, 0, LTQ_ICU_IM0_IER);
- /* clear all possibly pending interrupts */
-- ltq_icu_w32(~0, LTQ_ICU_IM0_ISR + (i * LTQ_ICU_OFFSET));
-+ ltq_icu_w32(i, ~0, LTQ_ICU_IM0_ISR);
- }
-
- mips_cpu_irq_init();
-
-- for (i = 2; i <= 6; i++)
-- setup_irq(i, &cascade);
-+ for (i = 0; i < MAX_IM; i++)
-+ setup_irq(i + 2, &cascade);
-
- if (cpu_has_vint) {
- pr_info("Setting up vectored interrupts\n");
-@@ -373,7 +376,8 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
- set_vi_handler(7, ltq_hw5_irqdispatch);
- }
-
-- irq_domain_add_linear(node, 6 * INT_NUM_IM_OFFSET,
-+ irq_domain_add_linear(node,
-+ (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
- &irq_domain_ops, 0);
-
- #if defined(CONFIG_MIPS_MT_SMP)
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0003-MIPS-lantiq-timer-irq-can-be-different-to-7.patch b/target/linux/lantiq/patches-3.6/0003-MIPS-lantiq-timer-irq-can-be-different-to-7.patch
deleted file mode 100644
index 26519d0055..0000000000
--- a/target/linux/lantiq/patches-3.6/0003-MIPS-lantiq-timer-irq-can-be-different-to-7.patch
+++ /dev/null
@@ -1,84 +0,0 @@
-From c2c9c788b91218bccbb9ac31539ffa577fe502bf Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 08:09:20 +0000
-Subject: [PATCH 3/9] MIPS: lantiq: timer irq can be different to 7
-
-The SVIP SoC has its timer IRQ on a different IRQ than 7. Fix up the irq
-code to be able to handle this.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4229/
----
- arch/mips/lantiq/irq.c | 19 ++++++++++++++++---
- 1 file changed, 16 insertions(+), 3 deletions(-)
-
-diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
-index a2699a70..0cec43d 100644
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -84,6 +84,7 @@ static unsigned short ltq_eiu_irq[MAX_EIU] = {
- static int exin_avail;
- static void __iomem *ltq_icu_membase[MAX_IM];
- static void __iomem *ltq_eiu_membase;
-+static struct irq_domain *ltq_domain;
-
- void ltq_disable_irq(struct irq_data *d)
- {
-@@ -219,10 +220,14 @@ DEFINE_HWx_IRQDISPATCH(2)
- DEFINE_HWx_IRQDISPATCH(3)
- DEFINE_HWx_IRQDISPATCH(4)
-
-+#if MIPS_CPU_TIMER_IRQ == 7
- static void ltq_hw5_irqdispatch(void)
- {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- }
-+#else
-+DEFINE_HWx_IRQDISPATCH(5)
-+#endif
-
- #ifdef CONFIG_MIPS_MT_SMP
- void __init arch_init_ipiirq(int irq, struct irqaction *action)
-@@ -270,7 +275,7 @@ asmlinkage void plat_irq_dispatch(void)
- unsigned int pending = read_c0_status() & read_c0_cause() & ST0_IM;
- unsigned int i;
-
-- if (pending & CAUSEF_IP7) {
-+ if ((MIPS_CPU_TIMER_IRQ == 7) && (pending & CAUSEF_IP7)) {
- do_IRQ(MIPS_CPU_TIMER_IRQ);
- goto out;
- } else {
-@@ -376,7 +381,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
- set_vi_handler(7, ltq_hw5_irqdispatch);
- }
-
-- irq_domain_add_linear(node,
-+ ltq_domain = irq_domain_add_linear(node,
- (MAX_IM * INT_NUM_IM_OFFSET) + MIPS_CPU_IRQ_CASCADE,
- &irq_domain_ops, 0);
-
-@@ -401,12 +406,20 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
-
- /* tell oprofile which irq to use */
- cp0_perfcount_irq = LTQ_PERF_IRQ;
-+
-+ /*
-+ * if the timer irq is not one of the mips irqs we need to
-+ * create a mapping
-+ */
-+ if (MIPS_CPU_TIMER_IRQ != 7)
-+ irq_create_mapping(ltq_domain, MIPS_CPU_TIMER_IRQ);
-+
- return 0;
- }
-
- unsigned int __cpuinit get_c0_compare_int(void)
- {
-- return CP0_LEGACY_COMPARE_IRQ;
-+ return MIPS_CPU_TIMER_IRQ;
- }
-
- static struct of_device_id __initdata of_irq_ids[] = {
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0004-MIPS-lantiq-dont-register-irq_chip-for-the-irq-casca.patch b/target/linux/lantiq/patches-3.6/0004-MIPS-lantiq-dont-register-irq_chip-for-the-irq-casca.patch
deleted file mode 100644
index 6d8e38c3a0..0000000000
--- a/target/linux/lantiq/patches-3.6/0004-MIPS-lantiq-dont-register-irq_chip-for-the-irq-casca.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 9c1628b603ee9d2bb220be0400c5dc6950cf012b Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 08:09:21 +0000
-Subject: [PATCH 4/9] MIPS: lantiq: dont register irq_chip for the irq cascade
-
-We dont want to register the irq_chip for the MIPS IRQ cascade.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4230/
----
- arch/mips/lantiq/irq.c | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
-index 0cec43d..87f15d6 100644
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -297,6 +297,9 @@ static int icu_map(struct irq_domain *d, unsigned int irq, irq_hw_number_t hw)
- struct irq_chip *chip = &ltq_irq_type;
- int i;
-
-+ if (hw < MIPS_CPU_IRQ_CASCADE)
-+ return 0;
-+
- for (i = 0; i < exin_avail; i++)
- if (hw == ltq_eiu_irq[i])
- chip = &ltq_eiu_type;
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0005-MIPS-lantiq-external-irq-sources-are-not-loaded-prop.patch b/target/linux/lantiq/patches-3.6/0005-MIPS-lantiq-external-irq-sources-are-not-loaded-prop.patch
deleted file mode 100644
index b67197e7a6..0000000000
--- a/target/linux/lantiq/patches-3.6/0005-MIPS-lantiq-external-irq-sources-are-not-loaded-prop.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From 70ec9054e7a65c878298666083f7d5b70ccf9032 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 08:09:22 +0000
-Subject: [PATCH 5/9] MIPS: lantiq: external irq sources are not loaded
- properly
-
-Support for the external interrupt unit was broken when the code was converted
-to devicetree support.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4231/
----
- arch/mips/lantiq/irq.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
-index 87f15d6..f36acd1 100644
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -341,7 +341,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
-
- /* the external interrupts are optional and xway only */
- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
-- if (eiu_node && of_address_to_resource(eiu_node, 0, &res)) {
-+ if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
- /* find out how many external irq sources we have */
- const __be32 *count = of_get_property(node,
- "lantiq,count", NULL);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0006-MIPS-lantiq-adds-support-for-nmi-and-ejtag-bootrom-v.patch b/target/linux/lantiq/patches-3.6/0006-MIPS-lantiq-adds-support-for-nmi-and-ejtag-bootrom-v.patch
deleted file mode 100644
index a6631b2f36..0000000000
--- a/target/linux/lantiq/patches-3.6/0006-MIPS-lantiq-adds-support-for-nmi-and-ejtag-bootrom-v.patch
+++ /dev/null
@@ -1,39 +0,0 @@
-From f8cd170dabeca90c976e6487ba7a8a7752aae571 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 11:39:56 +0000
-Subject: [PATCH 6/9] MIPS: lantiq: adds support for nmi and ejtag bootrom
- vectors
-
-Register nmi and ejtag bootrom vectors for FALC-ON SoC.
-
-Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4238/
----
- arch/mips/lantiq/falcon/prom.c | 5 +++++
- 1 file changed, 5 insertions(+)
-
-diff --git a/arch/mips/lantiq/falcon/prom.c b/arch/mips/lantiq/falcon/prom.c
-index c1d278f..aa94979 100644
---- a/arch/mips/lantiq/falcon/prom.c
-+++ b/arch/mips/lantiq/falcon/prom.c
-@@ -8,6 +8,8 @@
- */
-
- #include <linux/kernel.h>
-+#include <asm/cacheflush.h>
-+#include <asm/traps.h>
- #include <asm/io.h>
-
- #include <lantiq_soc.h>
-@@ -84,4 +86,7 @@ void __init ltq_soc_detect(struct ltq_soc_info *i)
- unreachable();
- break;
- }
-+
-+ board_nmi_handler_setup = ltq_soc_nmi_setup;
-+ board_ejtag_handler_setup = ltq_soc_ejtag_setup;
- }
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0007-MIPS-lantiq-falcon-clocks-were-not-enabled-properly.patch b/target/linux/lantiq/patches-3.6/0007-MIPS-lantiq-falcon-clocks-were-not-enabled-properly.patch
deleted file mode 100644
index 2053753ac3..0000000000
--- a/target/linux/lantiq/patches-3.6/0007-MIPS-lantiq-falcon-clocks-were-not-enabled-properly.patch
+++ /dev/null
@@ -1,30 +0,0 @@
-From 3a6ac5004c7c8b140319439f8b1f3f6d4cbfe67a Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 08:25:41 +0000
-Subject: [PATCH 7/9] MIPS: lantiq: falcon clocks were not enabled properly
-
-As a result of a non populated ->bits field inside the clock struct, the clock
-domains were never powered on the Falcon. Until now we only used domains that
-were also used and powered by the bootloader.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4234/
----
- arch/mips/lantiq/falcon/sysctrl.c | 1 +
- 1 file changed, 1 insertion(+)
-
-diff --git a/arch/mips/lantiq/falcon/sysctrl.c b/arch/mips/lantiq/falcon/sysctrl.c
-index ba0123d..2d4ced3 100644
---- a/arch/mips/lantiq/falcon/sysctrl.c
-+++ b/arch/mips/lantiq/falcon/sysctrl.c
-@@ -171,6 +171,7 @@ static inline void clkdev_add_sys(const char *dev, unsigned int module,
- clk->cl.con_id = NULL;
- clk->cl.clk = clk;
- clk->module = module;
-+ clk->bits = bits;
- clk->activate = sysctl_activate;
- clk->deactivate = sysctl_deactivate;
- clk->enable = sysctl_clken;
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0008-MIPS-lantiq-enable-pci-clk-conditional-for-xrx200-So.patch b/target/linux/lantiq/patches-3.6/0008-MIPS-lantiq-enable-pci-clk-conditional-for-xrx200-So.patch
deleted file mode 100644
index d68515cff0..0000000000
--- a/target/linux/lantiq/patches-3.6/0008-MIPS-lantiq-enable-pci-clk-conditional-for-xrx200-So.patch
+++ /dev/null
@@ -1,31 +0,0 @@
-From f40e1f9d856ec417468c090c4b56826171daa670 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 08:25:42 +0000
-Subject: [PATCH 8/9] MIPS: lantiq: enable pci clk conditional for xrx200 SoC
-
-The xrx200 SoC family has the same PCI clock register layout as the AR9.
-Enable the same quirk as for AR9
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4235/
----
- arch/mips/lantiq/xway/sysctrl.c | 3 ++-
- 1 file changed, 2 insertions(+), 1 deletion(-)
-
-diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
-index befbb76..67c3a91 100644
---- a/arch/mips/lantiq/xway/sysctrl.c
-+++ b/arch/mips/lantiq/xway/sysctrl.c
-@@ -145,7 +145,8 @@ static int pci_enable(struct clk *clk)
- {
- unsigned int val = ltq_cgu_r32(ifccr);
- /* set bus clock speed */
-- if (of_machine_is_compatible("lantiq,ar9")) {
-+ if (of_machine_is_compatible("lantiq,ar9") ||
-+ of_machine_is_compatible("lantiq,vr9")) {
- val &= ~0x1f00000;
- if (clk->rate == CLOCK_33M)
- val |= 0xe00000;
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0009-MIPS-lantiq-adds-support-for-gptu-timers.patch b/target/linux/lantiq/patches-3.6/0009-MIPS-lantiq-adds-support-for-gptu-timers.patch
deleted file mode 100644
index 0f8b5f6698..0000000000
--- a/target/linux/lantiq/patches-3.6/0009-MIPS-lantiq-adds-support-for-gptu-timers.patch
+++ /dev/null
@@ -1,246 +0,0 @@
-From 30404aec4d093942ba67ded8e1926cbf4472d4f7 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 16 Aug 2012 11:31:02 +0000
-Subject: [PATCH 9/9] MIPS: lantiq: adds support for gptu timers
-
-Lantiq socs have a General Purpose Timer Unit (GPTU). This driver allows us to
-initialize the timers. The voice firmware needs these timers as a reference.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Patchwork: http://patchwork.linux-mips.org/patch/4236/
----
- arch/mips/lantiq/xway/Makefile | 2 +-
- arch/mips/lantiq/xway/gptu.c | 214 ++++++++++++++++++++++++++++++++++++++++
- 2 files changed, 215 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/lantiq/xway/gptu.c
-
-diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
-index dc3194f..f7053b8 100644
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -1 +1 @@
--obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o
-+obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o gptu.o
-diff --git a/arch/mips/lantiq/xway/gptu.c b/arch/mips/lantiq/xway/gptu.c
-new file mode 100644
-index 0000000..cbb56fc
---- /dev/null
-+++ b/arch/mips/lantiq/xway/gptu.c
-@@ -0,0 +1,214 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ * Copyright (C) 2012 Lantiq GmbH
-+ */
-+
-+#include <linux/interrupt.h>
-+#include <linux/ioport.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_irq.h>
-+
-+#include <lantiq_soc.h>
-+#include "../clk.h"
-+
-+/* the magic ID byte of the core */
-+#define GPTU_MAGIC 0x59
-+/* clock control register */
-+#define GPTU_CLC 0x00
-+/* id register */
-+#define GPTU_ID 0x08
-+/* interrupt node enable */
-+#define GPTU_IRNEN 0xf4
-+/* interrupt control register */
-+#define GPTU_IRCR 0xf8
-+/* interrupt capture register */
-+#define GPTU_IRNCR 0xfc
-+/* there are 3 identical blocks of 2 timers. calculate register offsets */
-+#define GPTU_SHIFT(x) (x % 2 ? 4 : 0)
-+#define GPTU_BASE(x) (((x >> 1) * 0x20) + 0x10)
-+/* timer control register */
-+#define GPTU_CON(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x00)
-+/* timer auto reload register */
-+#define GPTU_RUN(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x08)
-+/* timer manual reload register */
-+#define GPTU_RLD(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x10)
-+/* timer count register */
-+#define GPTU_CNT(x) (GPTU_BASE(x) + GPTU_SHIFT(x) + 0x18)
-+
-+/* GPTU_CON(x) */
-+#define CON_CNT BIT(2)
-+#define CON_EDGE_ANY (BIT(7) | BIT(6))
-+#define CON_SYNC BIT(8)
-+#define CON_CLK_INT BIT(10)
-+
-+/* GPTU_RUN(x) */
-+#define RUN_SEN BIT(0)
-+#define RUN_RL BIT(2)
-+
-+/* set clock to runmode */
-+#define CLC_RMC BIT(8)
-+/* bring core out of suspend */
-+#define CLC_SUSPEND BIT(4)
-+/* the disable bit */
-+#define CLC_DISABLE BIT(0)
-+
-+#define gptu_w32(x, y) ltq_w32((x), gptu_membase + (y))
-+#define gptu_r32(x) ltq_r32(gptu_membase + (x))
-+
-+enum gptu_timer {
-+ TIMER1A = 0,
-+ TIMER1B,
-+ TIMER2A,
-+ TIMER2B,
-+ TIMER3A,
-+ TIMER3B
-+};
-+
-+static void __iomem *gptu_membase;
-+static struct resource irqres[6];
-+
-+static irqreturn_t timer_irq_handler(int irq, void *priv)
-+{
-+ int timer = irq - irqres[0].start;
-+ gptu_w32(1 << timer, GPTU_IRNCR);
-+ return IRQ_HANDLED;
-+}
-+
-+static void gptu_hwinit(void)
-+{
-+ gptu_w32(0x00, GPTU_IRNEN);
-+ gptu_w32(0xff, GPTU_IRNCR);
-+ gptu_w32(CLC_RMC | CLC_SUSPEND, GPTU_CLC);
-+}
-+
-+static void gptu_hwexit(void)
-+{
-+ gptu_w32(0x00, GPTU_IRNEN);
-+ gptu_w32(0xff, GPTU_IRNCR);
-+ gptu_w32(CLC_DISABLE, GPTU_CLC);
-+}
-+
-+static int gptu_enable(struct clk *clk)
-+{
-+ int ret = request_irq(irqres[clk->bits].start, timer_irq_handler,
-+ IRQF_TIMER, "gtpu", NULL);
-+ if (ret) {
-+ pr_err("gptu: failed to request irq\n");
-+ return ret;
-+ }
-+
-+ gptu_w32(CON_CNT | CON_EDGE_ANY | CON_SYNC | CON_CLK_INT,
-+ GPTU_CON(clk->bits));
-+ gptu_w32(1, GPTU_RLD(clk->bits));
-+ gptu_w32(gptu_r32(GPTU_IRNEN) | BIT(clk->bits), GPTU_IRNEN);
-+ gptu_w32(RUN_SEN | RUN_RL, GPTU_RUN(clk->bits));
-+ return 0;
-+}
-+
-+static void gptu_disable(struct clk *clk)
-+{
-+ gptu_w32(0, GPTU_RUN(clk->bits));
-+ gptu_w32(0, GPTU_CON(clk->bits));
-+ gptu_w32(0, GPTU_RLD(clk->bits));
-+ gptu_w32(gptu_r32(GPTU_IRNEN) & ~BIT(clk->bits), GPTU_IRNEN);
-+ free_irq(irqres[clk->bits].start, NULL);
-+}
-+
-+static inline void clkdev_add_gptu(struct device *dev, const char *con,
-+ unsigned int timer)
-+{
-+ struct clk *clk = kzalloc(sizeof(struct clk), GFP_KERNEL);
-+
-+ clk->cl.dev_id = dev_name(dev);
-+ clk->cl.con_id = con;
-+ clk->cl.clk = clk;
-+ clk->enable = gptu_enable;
-+ clk->disable = gptu_disable;
-+ clk->bits = timer;
-+ clkdev_add(&clk->cl);
-+}
-+
-+static int __devinit gptu_probe(struct platform_device *pdev)
-+{
-+ struct clk *clk;
-+ struct resource *res;
-+
-+ if (of_irq_to_resource_table(pdev->dev.of_node, irqres, 6) != 6) {
-+ dev_err(&pdev->dev, "Failed to get IRQ list\n");
-+ return -EINVAL;
-+ }
-+
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "Failed to get resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ /* remap gptu register range */
-+ gptu_membase = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!gptu_membase) {
-+ dev_err(&pdev->dev, "Failed to remap resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ /* enable our clock */
-+ clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(clk)) {
-+ dev_err(&pdev->dev, "Failed to get clock\n");
-+ return -ENOENT;
-+ }
-+ clk_enable(clk);
-+
-+ /* power up the core */
-+ gptu_hwinit();
-+
-+ /* the gptu has a ID register */
-+ if (((gptu_r32(GPTU_ID) >> 8) & 0xff) != GPTU_MAGIC) {
-+ dev_err(&pdev->dev, "Failed to find magic\n");
-+ gptu_hwexit();
-+ return -ENAVAIL;
-+ }
-+
-+ /* register the clocks */
-+ clkdev_add_gptu(&pdev->dev, "timer1a", TIMER1A);
-+ clkdev_add_gptu(&pdev->dev, "timer1b", TIMER1B);
-+ clkdev_add_gptu(&pdev->dev, "timer2a", TIMER2A);
-+ clkdev_add_gptu(&pdev->dev, "timer2b", TIMER2B);
-+ clkdev_add_gptu(&pdev->dev, "timer3a", TIMER3A);
-+ clkdev_add_gptu(&pdev->dev, "timer3b", TIMER3B);
-+
-+ dev_info(&pdev->dev, "gptu: 6 timers loaded\n");
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id gptu_match[] = {
-+ { .compatible = "lantiq,gptu-xway" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, dma_match);
-+
-+static struct platform_driver dma_driver = {
-+ .probe = gptu_probe,
-+ .driver = {
-+ .name = "gptu-xway",
-+ .owner = THIS_MODULE,
-+ .of_match_table = gptu_match,
-+ },
-+};
-+
-+int __init gptu_init(void)
-+{
-+ int ret = platform_driver_register(&dma_driver);
-+
-+ if (ret)
-+ pr_info("gptu: Error registering platform driver\n");
-+ return ret;
-+}
-+
-+arch_initcall(gptu_init);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0010-OF-pinctrl-MIPS-lantiq-implement-lantiq-xway-pinctrl.patch b/target/linux/lantiq/patches-3.6/0010-OF-pinctrl-MIPS-lantiq-implement-lantiq-xway-pinctrl.patch
deleted file mode 100644
index 44822553e5..0000000000
--- a/target/linux/lantiq/patches-3.6/0010-OF-pinctrl-MIPS-lantiq-implement-lantiq-xway-pinctrl.patch
+++ /dev/null
@@ -1,1632 +0,0 @@
-From 3f8c50c9b110dad4136ea7226cd87b0c4cdb70c8 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Tue, 28 Aug 2012 12:44:59 +0200
-Subject: [PATCH 10/15] OF: pinctrl: MIPS: lantiq: implement lantiq/xway
- pinctrl support
-
-Implement support for pinctrl on lantiq/xway socs. The IO core found on these
-socs has the registers for pinctrl, pinconf and gpio mixed up in the same
-register range. As the gpio_chip handling is only a few lines, the driver also
-implements the gpio functionality. This obseletes the old gpio driver that was
-located in the arch/ folder.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Cc: devicetree-discuss@lists.ozlabs.org
-Cc: linux-kernel@vger.kernel.org
----
- arch/mips/Kconfig | 2 +
- arch/mips/lantiq/Kconfig | 1 +
- arch/mips/lantiq/xway/Makefile | 2 +-
- arch/mips/lantiq/xway/gpio.c | 183 ---------
- drivers/pinctrl/Kconfig | 11 +
- drivers/pinctrl/Makefile | 2 +
- drivers/pinctrl/pinctrl-lantiq.c | 342 +++++++++++++++++
- drivers/pinctrl/pinctrl-lantiq.h | 194 ++++++++++
- drivers/pinctrl/pinctrl-xway.c | 781 ++++++++++++++++++++++++++++++++++++++
- 9 files changed, 1334 insertions(+), 184 deletions(-)
- delete mode 100644 arch/mips/lantiq/xway/gpio.c
- create mode 100644 drivers/pinctrl/pinctrl-lantiq.c
- create mode 100644 drivers/pinctrl/pinctrl-lantiq.h
- create mode 100644 drivers/pinctrl/pinctrl-xway.c
-
-diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
-index 331d574..b0f74b8 100644
---- a/arch/mips/Kconfig
-+++ b/arch/mips/Kconfig
-@@ -241,6 +241,8 @@ config LANTIQ
- select HAVE_MACH_CLKDEV
- select CLKDEV_LOOKUP
- select USE_OF
-+ select PINCTRL
-+ select PINCTRL_LANTIQ
-
- config LASAT
- bool "LASAT Networks platforms"
-diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
-index 20bdf40..080c013 100644
---- a/arch/mips/lantiq/Kconfig
-+++ b/arch/mips/lantiq/Kconfig
-@@ -2,6 +2,7 @@ if LANTIQ
-
- config SOC_TYPE_XWAY
- bool
-+ select PINCTRL_XWAY
- default n
-
- choice
-diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
-index f7053b8..70a58c7 100644
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -1 +1 @@
--obj-y := prom.o sysctrl.o clk.o reset.o gpio.o dma.o gptu.o
-+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
-diff --git a/arch/mips/lantiq/xway/gpio.c b/arch/mips/lantiq/xway/gpio.c
-deleted file mode 100644
-index 2ab39e9..0000000
---- a/arch/mips/lantiq/xway/gpio.c
-+++ /dev/null
-@@ -1,183 +0,0 @@
--/*
-- * This program is free software; you can redistribute it and/or modify it
-- * under the terms of the GNU General Public License version 2 as published
-- * by the Free Software Foundation.
-- *
-- * Copyright (C) 2010 John Crispin <blogic@openwrt.org>
-- */
--
--#include <linux/slab.h>
--#include <linux/export.h>
--#include <linux/platform_device.h>
--#include <linux/gpio.h>
--#include <linux/ioport.h>
--#include <linux/io.h>
--
--#include <lantiq_soc.h>
--
--#define LTQ_GPIO_OUT 0x00
--#define LTQ_GPIO_IN 0x04
--#define LTQ_GPIO_DIR 0x08
--#define LTQ_GPIO_ALTSEL0 0x0C
--#define LTQ_GPIO_ALTSEL1 0x10
--#define LTQ_GPIO_OD 0x14
--
--#define PINS_PER_PORT 16
--#define MAX_PORTS 3
--
--#define ltq_gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
--#define ltq_gpio_setbit(m, r, p) ltq_w32_mask(0, (1 << p), m + r)
--#define ltq_gpio_clearbit(m, r, p) ltq_w32_mask((1 << p), 0, m + r)
--
--struct ltq_gpio {
-- void __iomem *membase;
-- struct gpio_chip chip;
--};
--
--static struct ltq_gpio ltq_gpio_port[MAX_PORTS];
--
--int ltq_gpio_request(unsigned int pin, unsigned int alt0,
-- unsigned int alt1, unsigned int dir, const char *name)
--{
-- int id = 0;
--
-- if (pin >= (MAX_PORTS * PINS_PER_PORT))
-- return -EINVAL;
-- if (gpio_request(pin, name)) {
-- pr_err("failed to setup lantiq gpio: %s\n", name);
-- return -EBUSY;
-- }
-- if (dir)
-- gpio_direction_output(pin, 1);
-- else
-- gpio_direction_input(pin);
-- while (pin >= PINS_PER_PORT) {
-- pin -= PINS_PER_PORT;
-- id++;
-- }
-- if (alt0)
-- ltq_gpio_setbit(ltq_gpio_port[id].membase,
-- LTQ_GPIO_ALTSEL0, pin);
-- else
-- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
-- LTQ_GPIO_ALTSEL0, pin);
-- if (alt1)
-- ltq_gpio_setbit(ltq_gpio_port[id].membase,
-- LTQ_GPIO_ALTSEL1, pin);
-- else
-- ltq_gpio_clearbit(ltq_gpio_port[id].membase,
-- LTQ_GPIO_ALTSEL1, pin);
-- return 0;
--}
--EXPORT_SYMBOL(ltq_gpio_request);
--
--static void ltq_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
--{
-- struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
--
-- if (value)
-- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
-- else
-- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OUT, offset);
--}
--
--static int ltq_gpio_get(struct gpio_chip *chip, unsigned int offset)
--{
-- struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
--
-- return ltq_gpio_getbit(ltq_gpio->membase, LTQ_GPIO_IN, offset);
--}
--
--static int ltq_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
--{
-- struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
--
-- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
-- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
--
-- return 0;
--}
--
--static int ltq_gpio_direction_output(struct gpio_chip *chip,
-- unsigned int offset, int value)
--{
-- struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
--
-- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_OD, offset);
-- ltq_gpio_setbit(ltq_gpio->membase, LTQ_GPIO_DIR, offset);
-- ltq_gpio_set(chip, offset, value);
--
-- return 0;
--}
--
--static int ltq_gpio_req(struct gpio_chip *chip, unsigned offset)
--{
-- struct ltq_gpio *ltq_gpio = container_of(chip, struct ltq_gpio, chip);
--
-- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL0, offset);
-- ltq_gpio_clearbit(ltq_gpio->membase, LTQ_GPIO_ALTSEL1, offset);
-- return 0;
--}
--
--static int ltq_gpio_probe(struct platform_device *pdev)
--{
-- struct resource *res;
--
-- if (pdev->id >= MAX_PORTS) {
-- dev_err(&pdev->dev, "invalid gpio port %d\n",
-- pdev->id);
-- return -EINVAL;
-- }
-- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-- if (!res) {
-- dev_err(&pdev->dev, "failed to get memory for gpio port %d\n",
-- pdev->id);
-- return -ENOENT;
-- }
-- res = devm_request_mem_region(&pdev->dev, res->start,
-- resource_size(res), dev_name(&pdev->dev));
-- if (!res) {
-- dev_err(&pdev->dev,
-- "failed to request memory for gpio port %d\n",
-- pdev->id);
-- return -EBUSY;
-- }
-- ltq_gpio_port[pdev->id].membase = devm_ioremap_nocache(&pdev->dev,
-- res->start, resource_size(res));
-- if (!ltq_gpio_port[pdev->id].membase) {
-- dev_err(&pdev->dev, "failed to remap memory for gpio port %d\n",
-- pdev->id);
-- return -ENOMEM;
-- }
-- ltq_gpio_port[pdev->id].chip.label = "ltq_gpio";
-- ltq_gpio_port[pdev->id].chip.direction_input = ltq_gpio_direction_input;
-- ltq_gpio_port[pdev->id].chip.direction_output =
-- ltq_gpio_direction_output;
-- ltq_gpio_port[pdev->id].chip.get = ltq_gpio_get;
-- ltq_gpio_port[pdev->id].chip.set = ltq_gpio_set;
-- ltq_gpio_port[pdev->id].chip.request = ltq_gpio_req;
-- ltq_gpio_port[pdev->id].chip.base = PINS_PER_PORT * pdev->id;
-- ltq_gpio_port[pdev->id].chip.ngpio = PINS_PER_PORT;
-- platform_set_drvdata(pdev, &ltq_gpio_port[pdev->id]);
-- return gpiochip_add(&ltq_gpio_port[pdev->id].chip);
--}
--
--static struct platform_driver
--ltq_gpio_driver = {
-- .probe = ltq_gpio_probe,
-- .driver = {
-- .name = "ltq_gpio",
-- .owner = THIS_MODULE,
-- },
--};
--
--int __init ltq_gpio_init(void)
--{
-- int ret = platform_driver_register(&ltq_gpio_driver);
--
-- if (ret)
-- pr_info("ltq_gpio : Error registering platform driver!");
-- return ret;
--}
--
--postcore_initcall(ltq_gpio_init);
-diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
-index 54e3588..f77dce0 100644
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -55,6 +55,12 @@ config PINCTRL_IMX6Q
- help
- Say Y here to enable the imx6q pinctrl driver
-
-+config PINCTRL_LANTIQ
-+ bool
-+ depends on LANTIQ
-+ select PINMUX
-+ select PINCONF
-+
- config PINCTRL_PXA3xx
- bool
- select PINMUX
-@@ -147,6 +153,11 @@ config PINCTRL_COH901
-
- source "drivers/pinctrl/spear/Kconfig"
-
-+config PINCTRL_XWAY
-+ bool
-+ depends on SOC_TYPE_XWAY
-+ depends on PINCTRL_LANTIQ
-+
- endmenu
-
- endif
-diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
-index f40b1f8..e19e207 100644
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -29,5 +29,7 @@ obj-$(CONFIG_PINCTRL_TEGRA20) += pinctrl-tegra20.o
- obj-$(CONFIG_PINCTRL_TEGRA30) += pinctrl-tegra30.o
- obj-$(CONFIG_PINCTRL_U300) += pinctrl-u300.o
- obj-$(CONFIG_PINCTRL_COH901) += pinctrl-coh901.o
-+obj-$(CONFIG_PINCTRL_XWAY) += pinctrl-xway.o
-+obj-$(CONFIG_PINCTRL_LANTIQ) += pinctrl-lantiq.o
-
- obj-$(CONFIG_PLAT_SPEAR) += spear/
-diff --git a/drivers/pinctrl/pinctrl-lantiq.c b/drivers/pinctrl/pinctrl-lantiq.c
-new file mode 100644
-index 0000000..07ba768
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-lantiq.c
-@@ -0,0 +1,342 @@
-+/*
-+ * linux/drivers/pinctrl/pinctrl-lantiq.c
-+ * based on linux/drivers/pinctrl/pinctrl-pxa3xx.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/device.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+#include <linux/slab.h>
-+#include <linux/of.h>
-+
-+#include "pinctrl-lantiq.h"
-+
-+static int ltq_get_group_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ return info->num_grps;
-+}
-+
-+static const char *ltq_get_group_name(struct pinctrl_dev *pctrldev,
-+ unsigned selector)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ if (selector >= info->num_grps)
-+ return NULL;
-+ return info->grps[selector].name;
-+}
-+
-+static int ltq_get_group_pins(struct pinctrl_dev *pctrldev,
-+ unsigned selector,
-+ const unsigned **pins,
-+ unsigned *num_pins)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ if (selector >= info->num_grps)
-+ return -EINVAL;
-+ *pins = info->grps[selector].pins;
-+ *num_pins = info->grps[selector].npins;
-+ return 0;
-+}
-+
-+void ltq_pinctrl_dt_free_map(struct pinctrl_dev *pctldev,
-+ struct pinctrl_map *map, unsigned num_maps)
-+{
-+ int i;
-+
-+ for (i = 0; i < num_maps; i++)
-+ if (map[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
-+ kfree(map[i].data.configs.configs);
-+ kfree(map);
-+}
-+
-+static void ltq_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
-+ struct seq_file *s,
-+ unsigned offset)
-+{
-+ seq_printf(s, " %s", dev_name(pctldev->dev));
-+}
-+
-+static int ltq_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
-+ struct device_node *np,
-+ struct pinctrl_map **map)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
-+ unsigned long configs[3];
-+ unsigned num_configs = 0;
-+ struct property *prop;
-+ const char *group, *pin;
-+ const char *function;
-+ int ret, i;
-+
-+ ret = of_property_read_string(np, "lantiq,function", &function);
-+ if (!ret) {
-+ of_property_for_each_string(np, "lantiq,groups", prop, group) {
-+ (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
-+ (*map)->name = function;
-+ (*map)->data.mux.group = group;
-+ (*map)->data.mux.function = function;
-+ (*map)++;
-+ }
-+ if (of_find_property(np, "lantiq,pins", NULL))
-+ dev_err(pctldev->dev,
-+ "%s mixes pins and groups settings\n",
-+ np->name);
-+ return 0;
-+ }
-+
-+ for (i = 0; i < info->num_params; i++) {
-+ u32 val;
-+ int ret = of_property_read_u32(np,
-+ info->params[i].property, &val);
-+ if (!ret)
-+ configs[num_configs++] =
-+ LTQ_PINCONF_PACK(info->params[i].param,
-+ val);
-+ }
-+
-+ if (!num_configs)
-+ return -EINVAL;
-+
-+ of_property_for_each_string(np, "lantiq,pins", prop, pin) {
-+ (*map)->data.configs.configs = kmemdup(configs,
-+ num_configs * sizeof(unsigned long),
-+ GFP_KERNEL);
-+ (*map)->type = PIN_MAP_TYPE_CONFIGS_PIN;
-+ (*map)->name = pin;
-+ (*map)->data.configs.group_or_pin = pin;
-+ (*map)->data.configs.num_configs = num_configs;
-+ (*map)++;
-+ }
-+ return 0;
-+}
-+
-+static int ltq_pinctrl_dt_subnode_size(struct device_node *np)
-+{
-+ int ret;
-+
-+ ret = of_property_count_strings(np, "lantiq,groups");
-+ if (ret < 0)
-+ ret = of_property_count_strings(np, "lantiq,pins");
-+ return ret;
-+}
-+
-+int ltq_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
-+ struct device_node *np_config,
-+ struct pinctrl_map **map,
-+ unsigned *num_maps)
-+{
-+ struct pinctrl_map *tmp;
-+ struct device_node *np;
-+ int ret;
-+
-+ *num_maps = 0;
-+ for_each_child_of_node(np_config, np)
-+ *num_maps += ltq_pinctrl_dt_subnode_size(np);
-+ *map = kzalloc(*num_maps * sizeof(struct pinctrl_map), GFP_KERNEL);
-+ if (!*map)
-+ return -ENOMEM;
-+ tmp = *map;
-+
-+ for_each_child_of_node(np_config, np) {
-+ ret = ltq_pinctrl_dt_subnode_to_map(pctldev, np, &tmp);
-+ if (ret < 0) {
-+ ltq_pinctrl_dt_free_map(pctldev, *map, *num_maps);
-+ return ret;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static struct pinctrl_ops ltq_pctrl_ops = {
-+ .get_groups_count = ltq_get_group_count,
-+ .get_group_name = ltq_get_group_name,
-+ .get_group_pins = ltq_get_group_pins,
-+ .pin_dbg_show = ltq_pinctrl_pin_dbg_show,
-+ .dt_node_to_map = ltq_pinctrl_dt_node_to_map,
-+ .dt_free_map = ltq_pinctrl_dt_free_map,
-+};
-+
-+static int ltq_pmx_func_count(struct pinctrl_dev *pctrldev)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ return info->num_funcs;
-+}
-+
-+static const char *ltq_pmx_func_name(struct pinctrl_dev *pctrldev,
-+ unsigned selector)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ if (selector >= info->num_funcs)
-+ return NULL;
-+
-+ return info->funcs[selector].name;
-+}
-+
-+static int ltq_pmx_get_groups(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ const char * const **groups,
-+ unsigned * const num_groups)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+
-+ *groups = info->funcs[func].groups;
-+ *num_groups = info->funcs[func].num_groups;
-+
-+ return 0;
-+}
-+
-+/* Return function number. If failure, return negative value. */
-+static int match_mux(const struct ltq_mfp_pin *mfp, unsigned mux)
-+{
-+ int i;
-+ for (i = 0; i < LTQ_MAX_MUX; i++) {
-+ if (mfp->func[i] == mux)
-+ break;
-+ }
-+ if (i >= LTQ_MAX_MUX)
-+ return -EINVAL;
-+ return i;
-+}
-+
-+/* dont assume .mfp is linearly mapped. find the mfp with the correct .pin */
-+static int match_mfp(const struct ltq_pinmux_info *info, int pin)
-+{
-+ int i;
-+ for (i = 0; i < info->num_mfp; i++) {
-+ if (info->mfp[i].pin == pin)
-+ return i;
-+ }
-+ return -1;
-+}
-+
-+/* check whether current pin configuration is valid. Negative for failure */
-+static int match_group_mux(const struct ltq_pin_group *grp,
-+ const struct ltq_pinmux_info *info,
-+ unsigned mux)
-+{
-+ int i, pin, ret = 0;
-+ for (i = 0; i < grp->npins; i++) {
-+ pin = match_mfp(info, grp->pins[i]);
-+ if (pin < 0) {
-+ dev_err(info->dev, "could not find mfp for pin %d\n",
-+ grp->pins[i]);
-+ return -EINVAL;
-+ }
-+ ret = match_mux(&info->mfp[pin], mux);
-+ if (ret < 0) {
-+ dev_err(info->dev, "Can't find mux %d on pin%d\n",
-+ mux, pin);
-+ break;
-+ }
-+ }
-+ return ret;
-+}
-+
-+static int ltq_pmx_enable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ const struct ltq_pin_group *pin_grp = &info->grps[group];
-+ int i, pin, pin_func, ret;
-+
-+ if (!pin_grp->npins ||
-+ (match_group_mux(pin_grp, info, pin_grp->mux) < 0)) {
-+ dev_err(info->dev, "Failed to set the pin group: %s\n",
-+ info->grps[group].name);
-+ return -EINVAL;
-+ }
-+ for (i = 0; i < pin_grp->npins; i++) {
-+ pin = match_mfp(info, pin_grp->pins[i]);
-+ if (pin < 0) {
-+ dev_err(info->dev, "could not find mfp for pin %d\n",
-+ pin_grp->pins[i]);
-+ return -EINVAL;
-+ }
-+ pin_func = match_mux(&info->mfp[pin], pin_grp->mux);
-+ ret = info->apply_mux(pctrldev, pin, pin_func);
-+ if (ret) {
-+ dev_err(info->dev,
-+ "failed to apply mux %d for pin %d\n",
-+ pin_func, pin);
-+ return ret;
-+ }
-+ }
-+ return 0;
-+}
-+
-+static void ltq_pmx_disable(struct pinctrl_dev *pctrldev,
-+ unsigned func,
-+ unsigned group)
-+{
-+ /*
-+ * Nothing to do here. However, pinconf_check_ops() requires this
-+ * callback to be defined.
-+ */
-+}
-+
-+static int ltq_pmx_gpio_request_enable(struct pinctrl_dev *pctrldev,
-+ struct pinctrl_gpio_range *range,
-+ unsigned pin)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ int mfp = match_mfp(info, pin + (range->id * 32));
-+ int pin_func;
-+
-+ if (mfp < 0) {
-+ dev_err(info->dev, "could not find mfp for pin %d\n", pin);
-+ return -EINVAL;
-+ }
-+
-+ pin_func = match_mux(&info->mfp[mfp], 0);
-+ if (pin_func < 0) {
-+ dev_err(info->dev, "No GPIO function on pin%d\n", mfp);
-+ return -EINVAL;
-+ }
-+
-+ return info->apply_mux(pctrldev, mfp, pin_func);
-+}
-+
-+static struct pinmux_ops ltq_pmx_ops = {
-+ .get_functions_count = ltq_pmx_func_count,
-+ .get_function_name = ltq_pmx_func_name,
-+ .get_function_groups = ltq_pmx_get_groups,
-+ .enable = ltq_pmx_enable,
-+ .disable = ltq_pmx_disable,
-+ .gpio_request_enable = ltq_pmx_gpio_request_enable,
-+};
-+
-+/*
-+ * allow different socs to register with the generic part of the lanti
-+ * pinctrl code
-+ */
-+int ltq_pinctrl_register(struct platform_device *pdev,
-+ struct ltq_pinmux_info *info)
-+{
-+ struct pinctrl_desc *desc;
-+
-+ if (!info)
-+ return -EINVAL;
-+ desc = info->desc;
-+ desc->pctlops = &ltq_pctrl_ops;
-+ desc->pmxops = &ltq_pmx_ops;
-+ info->dev = &pdev->dev;
-+
-+ info->pctrl = pinctrl_register(desc, &pdev->dev, info);
-+ if (!info->pctrl) {
-+ dev_err(&pdev->dev, "failed to register LTQ pinmux driver\n");
-+ return -EINVAL;
-+ }
-+ platform_set_drvdata(pdev, info);
-+ return 0;
-+}
-diff --git a/drivers/pinctrl/pinctrl-lantiq.h b/drivers/pinctrl/pinctrl-lantiq.h
-new file mode 100644
-index 0000000..4419d32
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-lantiq.h
-@@ -0,0 +1,194 @@
-+/*
-+ * linux/drivers/pinctrl/pinctrl-lantiq.h
-+ * based on linux/drivers/pinctrl/pinctrl-pxa3xx.h
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#ifndef __PINCTRL_LANTIQ_H
-+
-+#include <linux/clkdev.h>
-+#include <linux/pinctrl/pinctrl.h>
-+#include <linux/pinctrl/pinconf.h>
-+#include <linux/pinctrl/pinmux.h>
-+#include <linux/pinctrl/consumer.h>
-+#include <linux/pinctrl/machine.h>
-+
-+#include "core.h"
-+
-+#define ARRAY_AND_SIZE(x) (x), ARRAY_SIZE(x)
-+
-+#define LTQ_MAX_MUX 4
-+#define MFPR_FUNC_MASK 0x3
-+
-+#define LTQ_PINCONF_PACK(param, arg) ((param) << 16 | (arg))
-+#define LTQ_PINCONF_UNPACK_PARAM(conf) ((conf) >> 16)
-+#define LTQ_PINCONF_UNPACK_ARG(conf) ((conf) & 0xffff)
-+
-+enum ltq_pinconf_param {
-+ LTQ_PINCONF_PARAM_PULL,
-+ LTQ_PINCONF_PARAM_OPEN_DRAIN,
-+ LTQ_PINCONF_PARAM_DRIVE_CURRENT,
-+ LTQ_PINCONF_PARAM_SLEW_RATE,
-+};
-+
-+struct ltq_cfg_param {
-+ const char *property;
-+ enum ltq_pinconf_param param;
-+};
-+
-+struct ltq_mfp_pin {
-+ const char *name;
-+ const unsigned int pin;
-+ const unsigned short func[LTQ_MAX_MUX];
-+};
-+
-+struct ltq_pin_group {
-+ const char *name;
-+ const unsigned mux;
-+ const unsigned *pins;
-+ const unsigned npins;
-+};
-+
-+struct ltq_pmx_func {
-+ const char *name;
-+ const char * const *groups;
-+ const unsigned num_groups;
-+};
-+
-+struct ltq_pinmux_info {
-+ struct device *dev;
-+ struct pinctrl_dev *pctrl;
-+
-+ /* we need to manage up to 5 pad controllers */
-+ void __iomem *membase[5];
-+
-+ /* the descriptor for the subsystem */
-+ struct pinctrl_desc *desc;
-+
-+ /* we expose our pads to the subsystem */
-+ struct pinctrl_pin_desc *pads;
-+
-+ /* the number of pads. this varies between socs */
-+ unsigned int num_pads;
-+
-+ /* these are our multifunction pins */
-+ const struct ltq_mfp_pin *mfp;
-+ unsigned int num_mfp;
-+
-+ /* a number of multifunction pins can be grouped together */
-+ const struct ltq_pin_group *grps;
-+ unsigned int num_grps;
-+
-+ /* a mapping between function string and id */
-+ const struct ltq_pmx_func *funcs;
-+ unsigned int num_funcs;
-+
-+ /* the pinconf options that we are able to read from the DT */
-+ const struct ltq_cfg_param *params;
-+ unsigned int num_params;
-+
-+ /* the pad controller can have a irq mapping */
-+ const unsigned *exin;
-+ unsigned int num_exin;
-+
-+ /* we need 5 clocks max */
-+ struct clk *clk[5];
-+
-+ /* soc specific callback used to apply muxing */
-+ int (*apply_mux)(struct pinctrl_dev *pctrldev, int pin, int mux);
-+};
-+
-+enum ltq_pin {
-+ GPIO0 = 0,
-+ GPIO1,
-+ GPIO2,
-+ GPIO3,
-+ GPIO4,
-+ GPIO5,
-+ GPIO6,
-+ GPIO7,
-+ GPIO8,
-+ GPIO9,
-+ GPIO10, /* 10 */
-+ GPIO11,
-+ GPIO12,
-+ GPIO13,
-+ GPIO14,
-+ GPIO15,
-+ GPIO16,
-+ GPIO17,
-+ GPIO18,
-+ GPIO19,
-+ GPIO20, /* 20 */
-+ GPIO21,
-+ GPIO22,
-+ GPIO23,
-+ GPIO24,
-+ GPIO25,
-+ GPIO26,
-+ GPIO27,
-+ GPIO28,
-+ GPIO29,
-+ GPIO30, /* 30 */
-+ GPIO31,
-+ GPIO32,
-+ GPIO33,
-+ GPIO34,
-+ GPIO35,
-+ GPIO36,
-+ GPIO37,
-+ GPIO38,
-+ GPIO39,
-+ GPIO40, /* 40 */
-+ GPIO41,
-+ GPIO42,
-+ GPIO43,
-+ GPIO44,
-+ GPIO45,
-+ GPIO46,
-+ GPIO47,
-+ GPIO48,
-+ GPIO49,
-+ GPIO50, /* 50 */
-+ GPIO51,
-+ GPIO52,
-+ GPIO53,
-+ GPIO54,
-+ GPIO55,
-+
-+ GPIO64,
-+ GPIO65,
-+ GPIO66,
-+ GPIO67,
-+ GPIO68,
-+ GPIO69,
-+ GPIO70,
-+ GPIO71,
-+ GPIO72,
-+ GPIO73,
-+ GPIO74,
-+ GPIO75,
-+ GPIO76,
-+ GPIO77,
-+ GPIO78,
-+ GPIO79,
-+ GPIO80,
-+ GPIO81,
-+ GPIO82,
-+ GPIO83,
-+ GPIO84,
-+ GPIO85,
-+ GPIO86,
-+ GPIO87,
-+ GPIO88,
-+};
-+
-+extern int ltq_pinctrl_register(struct platform_device *pdev,
-+ struct ltq_pinmux_info *info);
-+extern int ltq_pinctrl_unregister(struct platform_device *pdev);
-+#endif /* __PINCTRL_PXA3XX_H */
-diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
-new file mode 100644
-index 0000000..f8d917d
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-xway.c
-@@ -0,0 +1,781 @@
-+/*
-+ * linux/drivers/pinctrl/pinmux-xway.c
-+ * based on linux/drivers/pinctrl/pinmux-pxa910.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License version 2 as
-+ * publishhed by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/slab.h>
-+#include <linux/module.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+#include <linux/of_gpio.h>
-+#include <linux/ioport.h>
-+#include <linux/io.h>
-+#include <linux/device.h>
-+#include <linux/module.h>
-+#include <linux/io.h>
-+#include <linux/platform_device.h>
-+
-+#include "pinctrl-lantiq.h"
-+
-+#include <lantiq_soc.h>
-+
-+/* we have 3 1/2 banks of 16 bit each */
-+#define PINS 16
-+#define PORT3 3
-+#define PORT(x) (x / PINS)
-+#define PORT_PIN(x) (x % PINS)
-+
-+/* we have 2 mux bits that can be set for each pin */
-+#define MUX_ALT0 0x1
-+#define MUX_ALT1 0x2
-+
-+/*
-+ * each bank has this offset apart from the 1/2 bank that is mixed into the
-+ * other 3 ranges
-+ */
-+#define REG_OFF 0x30
-+
-+/* these are the offsets to our registers */
-+#define GPIO_BASE(p) (REG_OFF * PORT(p))
-+#define GPIO_OUT(p) GPIO_BASE(p)
-+#define GPIO_IN(p) (GPIO_BASE(p) + 0x04)
-+#define GPIO_DIR(p) (GPIO_BASE(p) + 0x08)
-+#define GPIO_ALT0(p) (GPIO_BASE(p) + 0x0C)
-+#define GPIO_ALT1(p) (GPIO_BASE(p) + 0x10)
-+#define GPIO_OD(p) (GPIO_BASE(p) + 0x14)
-+#define GPIO_PUDSEL(p) (GPIO_BASE(p) + 0x1c)
-+#define GPIO_PUDEN(p) (GPIO_BASE(p) + 0x20)
-+
-+/* the 1/2 port needs special offsets for some registers */
-+#define GPIO3_OD (GPIO_BASE(0) + 0x24)
-+#define GPIO3_PUDSEL (GPIO_BASE(0) + 0x28)
-+#define GPIO3_PUDEN (GPIO_BASE(0) + 0x2C)
-+#define GPIO3_ALT1 (GPIO_BASE(PINS) + 0x24)
-+
-+/* macros to help us access the registers */
-+#define gpio_getbit(m, r, p) (!!(ltq_r32(m + r) & BIT(p)))
-+#define gpio_setbit(m, r, p) ltq_w32_mask(0, BIT(p), m + r)
-+#define gpio_clearbit(m, r, p) ltq_w32_mask(BIT(p), 0, m + r)
-+
-+#define MFP_XWAY(a, f0, f1, f2, f3) \
-+ { \
-+ .name = #a, \
-+ .pin = a, \
-+ .func = { \
-+ XWAY_MUX_##f0, \
-+ XWAY_MUX_##f1, \
-+ XWAY_MUX_##f2, \
-+ XWAY_MUX_##f3, \
-+ }, \
-+ }
-+
-+#define GRP_MUX(a, m, p) \
-+ { .name = a, .mux = XWAY_MUX_##m, .pins = p, .npins = ARRAY_SIZE(p), }
-+
-+#define FUNC_MUX(f, m) \
-+ { .func = f, .mux = XWAY_MUX_##m, }
-+
-+#define XWAY_MAX_PIN 32
-+#define XR9_MAX_PIN 56
-+
-+enum xway_mux {
-+ XWAY_MUX_GPIO = 0,
-+ XWAY_MUX_SPI,
-+ XWAY_MUX_ASC,
-+ XWAY_MUX_PCI,
-+ XWAY_MUX_CGU,
-+ XWAY_MUX_EBU,
-+ XWAY_MUX_JTAG,
-+ XWAY_MUX_EXIN,
-+ XWAY_MUX_TDM,
-+ XWAY_MUX_STP,
-+ XWAY_MUX_SIN,
-+ XWAY_MUX_GPT,
-+ XWAY_MUX_NMI,
-+ XWAY_MUX_MDIO,
-+ XWAY_MUX_MII,
-+ XWAY_MUX_EPHY,
-+ XWAY_MUX_DFE,
-+ XWAY_MUX_SDIO,
-+ XWAY_MUX_NONE = 0xffff,
-+};
-+
-+static const struct ltq_mfp_pin xway_mfp[] = {
-+ /* pin f0 f1 f2 f3 */
-+ MFP_XWAY(GPIO0, GPIO, EXIN, NONE, TDM),
-+ MFP_XWAY(GPIO1, GPIO, EXIN, NONE, NONE),
-+ MFP_XWAY(GPIO2, GPIO, CGU, EXIN, NONE),
-+ MFP_XWAY(GPIO3, GPIO, CGU, NONE, PCI),
-+ MFP_XWAY(GPIO4, GPIO, STP, NONE, ASC),
-+ MFP_XWAY(GPIO5, GPIO, STP, NONE, NONE),
-+ MFP_XWAY(GPIO6, GPIO, STP, GPT, ASC),
-+ MFP_XWAY(GPIO7, GPIO, CGU, PCI, NONE),
-+ MFP_XWAY(GPIO8, GPIO, CGU, NMI, NONE),
-+ MFP_XWAY(GPIO9, GPIO, ASC, SPI, EXIN),
-+ MFP_XWAY(GPIO10, GPIO, ASC, SPI, NONE),
-+ MFP_XWAY(GPIO11, GPIO, ASC, PCI, SPI),
-+ MFP_XWAY(GPIO12, GPIO, ASC, NONE, NONE),
-+ MFP_XWAY(GPIO13, GPIO, EBU, SPI, NONE),
-+ MFP_XWAY(GPIO14, GPIO, CGU, PCI, NONE),
-+ MFP_XWAY(GPIO15, GPIO, SPI, JTAG, NONE),
-+ MFP_XWAY(GPIO16, GPIO, SPI, NONE, JTAG),
-+ MFP_XWAY(GPIO17, GPIO, SPI, NONE, JTAG),
-+ MFP_XWAY(GPIO18, GPIO, SPI, NONE, JTAG),
-+ MFP_XWAY(GPIO19, GPIO, PCI, NONE, NONE),
-+ MFP_XWAY(GPIO20, GPIO, JTAG, NONE, NONE),
-+ MFP_XWAY(GPIO21, GPIO, PCI, EBU, GPT),
-+ MFP_XWAY(GPIO22, GPIO, SPI, NONE, NONE),
-+ MFP_XWAY(GPIO23, GPIO, EBU, PCI, STP),
-+ MFP_XWAY(GPIO24, GPIO, EBU, TDM, PCI),
-+ MFP_XWAY(GPIO25, GPIO, TDM, NONE, ASC),
-+ MFP_XWAY(GPIO26, GPIO, EBU, NONE, TDM),
-+ MFP_XWAY(GPIO27, GPIO, TDM, NONE, ASC),
-+ MFP_XWAY(GPIO28, GPIO, GPT, NONE, NONE),
-+ MFP_XWAY(GPIO29, GPIO, PCI, NONE, NONE),
-+ MFP_XWAY(GPIO30, GPIO, PCI, NONE, NONE),
-+ MFP_XWAY(GPIO31, GPIO, EBU, PCI, NONE),
-+ MFP_XWAY(GPIO32, GPIO, NONE, NONE, EBU),
-+ MFP_XWAY(GPIO33, GPIO, NONE, NONE, EBU),
-+ MFP_XWAY(GPIO34, GPIO, NONE, NONE, EBU),
-+ MFP_XWAY(GPIO35, GPIO, NONE, NONE, EBU),
-+ MFP_XWAY(GPIO36, GPIO, SIN, NONE, EBU),
-+ MFP_XWAY(GPIO37, GPIO, PCI, NONE, NONE),
-+ MFP_XWAY(GPIO38, GPIO, PCI, NONE, NONE),
-+ MFP_XWAY(GPIO39, GPIO, EXIN, NONE, NONE),
-+ MFP_XWAY(GPIO40, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO41, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO42, GPIO, MDIO, NONE, NONE),
-+ MFP_XWAY(GPIO43, GPIO, MDIO, NONE, NONE),
-+ MFP_XWAY(GPIO44, GPIO, NONE, NONE, SIN),
-+ MFP_XWAY(GPIO45, GPIO, NONE, NONE, SIN),
-+ MFP_XWAY(GPIO46, GPIO, NONE, NONE, EXIN),
-+ MFP_XWAY(GPIO47, GPIO, NONE, NONE, SIN),
-+ MFP_XWAY(GPIO48, GPIO, EBU, NONE, NONE),
-+ MFP_XWAY(GPIO49, GPIO, EBU, NONE, NONE),
-+ MFP_XWAY(GPIO50, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO51, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO52, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO53, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO54, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO55, GPIO, NONE, NONE, NONE),
-+};
-+
-+static const struct ltq_mfp_pin ase_mfp[] = {
-+ /* pin f0 f1 f2 f3 */
-+ MFP_XWAY(GPIO0, GPIO, EXIN, MII, TDM),
-+ MFP_XWAY(GPIO1, GPIO, STP, DFE, EBU),
-+ MFP_XWAY(GPIO2, GPIO, STP, DFE, EPHY),
-+ MFP_XWAY(GPIO3, GPIO, STP, EPHY, EBU),
-+ MFP_XWAY(GPIO4, GPIO, GPT, EPHY, MII),
-+ MFP_XWAY(GPIO5, GPIO, MII, ASC, GPT),
-+ MFP_XWAY(GPIO6, GPIO, MII, ASC, EXIN),
-+ MFP_XWAY(GPIO7, GPIO, SPI, MII, JTAG),
-+ MFP_XWAY(GPIO8, GPIO, SPI, MII, JTAG),
-+ MFP_XWAY(GPIO9, GPIO, SPI, MII, JTAG),
-+ MFP_XWAY(GPIO10, GPIO, SPI, MII, JTAG),
-+ MFP_XWAY(GPIO11, GPIO, EBU, CGU, JTAG),
-+ MFP_XWAY(GPIO12, GPIO, EBU, MII, SDIO),
-+ MFP_XWAY(GPIO13, GPIO, EBU, MII, CGU),
-+ MFP_XWAY(GPIO14, GPIO, EBU, SPI, CGU),
-+ MFP_XWAY(GPIO15, GPIO, EBU, SPI, SDIO),
-+ MFP_XWAY(GPIO16, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO17, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO18, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO19, GPIO, EBU, MII, SDIO),
-+ MFP_XWAY(GPIO20, GPIO, EBU, MII, SDIO),
-+ MFP_XWAY(GPIO21, GPIO, EBU, MII, SDIO),
-+ MFP_XWAY(GPIO22, GPIO, EBU, MII, CGU),
-+ MFP_XWAY(GPIO23, GPIO, EBU, MII, CGU),
-+ MFP_XWAY(GPIO24, GPIO, EBU, NONE, MII),
-+ MFP_XWAY(GPIO25, GPIO, EBU, MII, GPT),
-+ MFP_XWAY(GPIO26, GPIO, EBU, MII, SDIO),
-+ MFP_XWAY(GPIO27, GPIO, EBU, NONE, MII),
-+ MFP_XWAY(GPIO28, GPIO, MII, EBU, SDIO),
-+ MFP_XWAY(GPIO29, GPIO, EBU, MII, EXIN),
-+ MFP_XWAY(GPIO30, GPIO, NONE, NONE, NONE),
-+ MFP_XWAY(GPIO31, GPIO, NONE, NONE, NONE),
-+};
-+
-+static const unsigned pins_jtag[] = {GPIO15, GPIO16, GPIO17, GPIO19, GPIO35};
-+static const unsigned pins_asc0[] = {GPIO11, GPIO12};
-+static const unsigned pins_asc0_cts_rts[] = {GPIO9, GPIO10};
-+static const unsigned pins_stp[] = {GPIO4, GPIO5, GPIO6};
-+static const unsigned pins_nmi[] = {GPIO8};
-+static const unsigned pins_mdio[] = {GPIO42, GPIO43};
-+
-+static const unsigned pins_ebu_a24[] = {GPIO13};
-+static const unsigned pins_ebu_clk[] = {GPIO21};
-+static const unsigned pins_ebu_cs1[] = {GPIO23};
-+static const unsigned pins_ebu_a23[] = {GPIO24};
-+static const unsigned pins_ebu_wait[] = {GPIO26};
-+static const unsigned pins_ebu_a25[] = {GPIO31};
-+static const unsigned pins_ebu_rdy[] = {GPIO48};
-+static const unsigned pins_ebu_rd[] = {GPIO49};
-+
-+static const unsigned pins_nand_ale[] = {GPIO13};
-+static const unsigned pins_nand_cs1[] = {GPIO23};
-+static const unsigned pins_nand_cle[] = {GPIO24};
-+static const unsigned pins_nand_rdy[] = {GPIO48};
-+static const unsigned pins_nand_rd[] = {GPIO49};
-+
-+static const unsigned pins_exin0[] = {GPIO0};
-+static const unsigned pins_exin1[] = {GPIO1};
-+static const unsigned pins_exin2[] = {GPIO2};
-+static const unsigned pins_exin3[] = {GPIO39};
-+static const unsigned pins_exin4[] = {GPIO46};
-+static const unsigned pins_exin5[] = {GPIO9};
-+
-+static const unsigned pins_spi[] = {GPIO16, GPIO17, GPIO18};
-+static const unsigned pins_spi_cs1[] = {GPIO15};
-+static const unsigned pins_spi_cs2[] = {GPIO21};
-+static const unsigned pins_spi_cs3[] = {GPIO13};
-+static const unsigned pins_spi_cs4[] = {GPIO10};
-+static const unsigned pins_spi_cs5[] = {GPIO9};
-+static const unsigned pins_spi_cs6[] = {GPIO11};
-+
-+static const unsigned pins_gpt1[] = {GPIO28};
-+static const unsigned pins_gpt2[] = {GPIO21};
-+static const unsigned pins_gpt3[] = {GPIO6};
-+
-+static const unsigned pins_clkout0[] = {GPIO8};
-+static const unsigned pins_clkout1[] = {GPIO7};
-+static const unsigned pins_clkout2[] = {GPIO3};
-+static const unsigned pins_clkout3[] = {GPIO2};
-+
-+static const unsigned pins_pci_gnt1[] = {GPIO30};
-+static const unsigned pins_pci_gnt2[] = {GPIO23};
-+static const unsigned pins_pci_gnt3[] = {GPIO19};
-+static const unsigned pins_pci_gnt4[] = {GPIO38};
-+static const unsigned pins_pci_req1[] = {GPIO29};
-+static const unsigned pins_pci_req2[] = {GPIO31};
-+static const unsigned pins_pci_req3[] = {GPIO3};
-+static const unsigned pins_pci_req4[] = {GPIO37};
-+
-+static const unsigned ase_pins_jtag[] = {GPIO7, GPIO8, GPIO9, GPIO10, GPIO11};
-+static const unsigned ase_pins_asc[] = {GPIO5, GPIO6};
-+static const unsigned ase_pins_stp[] = {GPIO1, GPIO2, GPIO3};
-+static const unsigned ase_pins_ephy[] = {GPIO2, GPIO3, GPIO4};
-+static const unsigned ase_pins_dfe[] = {GPIO1, GPIO2};
-+
-+static const unsigned ase_pins_spi[] = {GPIO8, GPIO9, GPIO10};
-+static const unsigned ase_pins_spi_cs1[] = {GPIO7};
-+static const unsigned ase_pins_spi_cs2[] = {GPIO15};
-+static const unsigned ase_pins_spi_cs3[] = {GPIO14};
-+
-+static const unsigned ase_pins_exin0[] = {GPIO6};
-+static const unsigned ase_pins_exin1[] = {GPIO29};
-+static const unsigned ase_pins_exin2[] = {GPIO0};
-+
-+static const unsigned ase_pins_gpt1[] = {GPIO5};
-+static const unsigned ase_pins_gpt2[] = {GPIO4};
-+static const unsigned ase_pins_gpt3[] = {GPIO25};
-+
-+static const struct ltq_pin_group xway_grps[] = {
-+ GRP_MUX("exin0", EXIN, pins_exin0),
-+ GRP_MUX("exin1", EXIN, pins_exin1),
-+ GRP_MUX("exin2", EXIN, pins_exin2),
-+ GRP_MUX("jtag", JTAG, pins_jtag),
-+ GRP_MUX("ebu a23", EBU, pins_ebu_a23),
-+ GRP_MUX("ebu a24", EBU, pins_ebu_a24),
-+ GRP_MUX("ebu a25", EBU, pins_ebu_a25),
-+ GRP_MUX("ebu clk", EBU, pins_ebu_clk),
-+ GRP_MUX("ebu cs1", EBU, pins_ebu_cs1),
-+ GRP_MUX("ebu wait", EBU, pins_ebu_wait),
-+ GRP_MUX("nand ale", EBU, pins_nand_ale),
-+ GRP_MUX("nand cs1", EBU, pins_nand_cs1),
-+ GRP_MUX("nand cle", EBU, pins_nand_cle),
-+ GRP_MUX("spi", SPI, pins_spi),
-+ GRP_MUX("spi_cs1", SPI, pins_spi_cs1),
-+ GRP_MUX("spi_cs2", SPI, pins_spi_cs2),
-+ GRP_MUX("spi_cs3", SPI, pins_spi_cs3),
-+ GRP_MUX("spi_cs4", SPI, pins_spi_cs4),
-+ GRP_MUX("spi_cs5", SPI, pins_spi_cs5),
-+ GRP_MUX("spi_cs6", SPI, pins_spi_cs6),
-+ GRP_MUX("asc0", ASC, pins_asc0),
-+ GRP_MUX("asc0 cts rts", ASC, pins_asc0_cts_rts),
-+ GRP_MUX("stp", STP, pins_stp),
-+ GRP_MUX("nmi", NMI, pins_nmi),
-+ GRP_MUX("gpt1", GPT, pins_gpt1),
-+ GRP_MUX("gpt2", GPT, pins_gpt2),
-+ GRP_MUX("gpt3", GPT, pins_gpt3),
-+ GRP_MUX("clkout0", CGU, pins_clkout0),
-+ GRP_MUX("clkout1", CGU, pins_clkout1),
-+ GRP_MUX("clkout2", CGU, pins_clkout2),
-+ GRP_MUX("clkout3", CGU, pins_clkout3),
-+ GRP_MUX("gnt1", PCI, pins_pci_gnt1),
-+ GRP_MUX("gnt2", PCI, pins_pci_gnt2),
-+ GRP_MUX("gnt3", PCI, pins_pci_gnt3),
-+ GRP_MUX("req1", PCI, pins_pci_req1),
-+ GRP_MUX("req2", PCI, pins_pci_req2),
-+ GRP_MUX("req3", PCI, pins_pci_req3),
-+/* xrx only */
-+ GRP_MUX("nand rdy", EBU, pins_nand_rdy),
-+ GRP_MUX("nand rd", EBU, pins_nand_rd),
-+ GRP_MUX("exin3", EXIN, pins_exin3),
-+ GRP_MUX("exin4", EXIN, pins_exin4),
-+ GRP_MUX("exin5", EXIN, pins_exin5),
-+ GRP_MUX("gnt4", PCI, pins_pci_gnt4),
-+ GRP_MUX("req4", PCI, pins_pci_gnt4),
-+ GRP_MUX("mdio", MDIO, pins_mdio),
-+};
-+
-+static const struct ltq_pin_group ase_grps[] = {
-+ GRP_MUX("exin0", EXIN, ase_pins_exin0),
-+ GRP_MUX("exin1", EXIN, ase_pins_exin1),
-+ GRP_MUX("exin2", EXIN, ase_pins_exin2),
-+ GRP_MUX("jtag", JTAG, ase_pins_jtag),
-+ GRP_MUX("stp", STP, ase_pins_stp),
-+ GRP_MUX("asc", ASC, ase_pins_asc),
-+ GRP_MUX("gpt1", GPT, ase_pins_gpt1),
-+ GRP_MUX("gpt2", GPT, ase_pins_gpt2),
-+ GRP_MUX("gpt3", GPT, ase_pins_gpt3),
-+ GRP_MUX("ephy", EPHY, ase_pins_ephy),
-+ GRP_MUX("dfe", DFE, ase_pins_dfe),
-+ GRP_MUX("spi", SPI, ase_pins_spi),
-+ GRP_MUX("spi_cs1", SPI, ase_pins_spi_cs1),
-+ GRP_MUX("spi_cs2", SPI, ase_pins_spi_cs2),
-+ GRP_MUX("spi_cs3", SPI, ase_pins_spi_cs3),
-+};
-+
-+static const char * const xway_pci_grps[] = {"gnt1", "gnt2",
-+ "gnt3", "req1",
-+ "req2", "req3"};
-+static const char * const xway_spi_grps[] = {"spi", "spi_cs1",
-+ "spi_cs2", "spi_cs3",
-+ "spi_cs4", "spi_cs5",
-+ "spi_cs6"};
-+static const char * const xway_cgu_grps[] = {"clkout0", "clkout1",
-+ "clkout2", "clkout3"};
-+static const char * const xway_ebu_grps[] = {"ebu a23", "ebu a24",
-+ "ebu a25", "ebu cs1",
-+ "ebu wait", "ebu clk",
-+ "nand ale", "nand cs1",
-+ "nand cle"};
-+static const char * const xway_exin_grps[] = {"exin0", "exin1", "exin2"};
-+static const char * const xway_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
-+static const char * const xway_asc_grps[] = {"asc0", "asc0 cts rts"};
-+static const char * const xway_jtag_grps[] = {"jtag"};
-+static const char * const xway_stp_grps[] = {"stp"};
-+static const char * const xway_nmi_grps[] = {"nmi"};
-+
-+/* ar9/vr9/gr9 */
-+static const char * const xrx_mdio_grps[] = {"mdio"};
-+static const char * const xrx_ebu_grps[] = {"ebu a23", "ebu a24",
-+ "ebu a25", "ebu cs1",
-+ "ebu wait", "ebu clk",
-+ "nand ale", "nand cs1",
-+ "nand cle", "nand rdy",
-+ "nand rd"};
-+static const char * const xrx_exin_grps[] = {"exin0", "exin1", "exin2",
-+ "exin3", "exin4", "exin5"};
-+static const char * const xrx_pci_grps[] = {"gnt1", "gnt2",
-+ "gnt3", "gnt4",
-+ "req1", "req2",
-+ "req3", "req4"};
-+
-+/* ase */
-+static const char * const ase_exin_grps[] = {"exin0", "exin1", "exin2"};
-+static const char * const ase_gpt_grps[] = {"gpt1", "gpt2", "gpt3"};
-+static const char * const ase_dfe_grps[] = {"dfe"};
-+static const char * const ase_ephy_grps[] = {"ephy"};
-+static const char * const ase_asc_grps[] = {"asc"};
-+static const char * const ase_jtag_grps[] = {"jtag"};
-+static const char * const ase_stp_grps[] = {"stp"};
-+static const char * const ase_spi_grps[] = {"spi", "spi_cs1",
-+ "spi_cs2", "spi_cs3"};
-+
-+static const struct ltq_pmx_func danube_funcs[] = {
-+ {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
-+ {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
-+ {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
-+ {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
-+ {"exin", ARRAY_AND_SIZE(xway_exin_grps)},
-+ {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
-+ {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
-+ {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
-+ {"pci", ARRAY_AND_SIZE(xway_pci_grps)},
-+ {"ebu", ARRAY_AND_SIZE(xway_ebu_grps)},
-+};
-+
-+static const struct ltq_pmx_func xrx_funcs[] = {
-+ {"spi", ARRAY_AND_SIZE(xway_spi_grps)},
-+ {"asc", ARRAY_AND_SIZE(xway_asc_grps)},
-+ {"cgu", ARRAY_AND_SIZE(xway_cgu_grps)},
-+ {"jtag", ARRAY_AND_SIZE(xway_jtag_grps)},
-+ {"exin", ARRAY_AND_SIZE(xrx_exin_grps)},
-+ {"stp", ARRAY_AND_SIZE(xway_stp_grps)},
-+ {"gpt", ARRAY_AND_SIZE(xway_gpt_grps)},
-+ {"nmi", ARRAY_AND_SIZE(xway_nmi_grps)},
-+ {"pci", ARRAY_AND_SIZE(xrx_pci_grps)},
-+ {"ebu", ARRAY_AND_SIZE(xrx_ebu_grps)},
-+ {"mdio", ARRAY_AND_SIZE(xrx_mdio_grps)},
-+};
-+
-+static const struct ltq_pmx_func ase_funcs[] = {
-+ {"spi", ARRAY_AND_SIZE(ase_spi_grps)},
-+ {"asc", ARRAY_AND_SIZE(ase_asc_grps)},
-+ {"jtag", ARRAY_AND_SIZE(ase_jtag_grps)},
-+ {"exin", ARRAY_AND_SIZE(ase_exin_grps)},
-+ {"stp", ARRAY_AND_SIZE(ase_stp_grps)},
-+ {"gpt", ARRAY_AND_SIZE(ase_gpt_grps)},
-+ {"ephy", ARRAY_AND_SIZE(ase_ephy_grps)},
-+ {"dfe", ARRAY_AND_SIZE(ase_dfe_grps)},
-+};
-+
-+/* --------- pinconf related code --------- */
-+static int xway_pinconf_get(struct pinctrl_dev *pctldev,
-+ unsigned pin,
-+ unsigned long *config)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
-+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
-+ int port = PORT(pin);
-+ u32 reg;
-+
-+ switch (param) {
-+ case LTQ_PINCONF_PARAM_OPEN_DRAIN:
-+ if (port == PORT3)
-+ reg = GPIO3_OD;
-+ else
-+ reg = GPIO_OD(port);
-+ *config = LTQ_PINCONF_PACK(param,
-+ !!gpio_getbit(info->membase[0], reg, PORT_PIN(port)));
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_PULL:
-+ if (port == PORT3)
-+ reg = GPIO3_PUDEN;
-+ else
-+ reg = GPIO_PUDEN(port);
-+ if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port))) {
-+ *config = LTQ_PINCONF_PACK(param, 0);
-+ break;
-+ }
-+
-+ if (port == PORT3)
-+ reg = GPIO3_PUDSEL;
-+ else
-+ reg = GPIO_PUDSEL(port);
-+ if (!gpio_getbit(info->membase[0], reg, PORT_PIN(port)))
-+ *config = LTQ_PINCONF_PACK(param, 2);
-+ else
-+ *config = LTQ_PINCONF_PACK(param, 1);
-+ break;
-+
-+ default:
-+ dev_err(pctldev->dev, "Invalid config param %04x\n", param);
-+ return -ENOTSUPP;
-+ }
-+ return 0;
-+}
-+
-+static int xway_pinconf_set(struct pinctrl_dev *pctldev,
-+ unsigned pin,
-+ unsigned long config)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctldev);
-+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
-+ int arg = LTQ_PINCONF_UNPACK_ARG(config);
-+ int port = PORT(pin);
-+ u32 reg;
-+
-+ switch (param) {
-+ case LTQ_PINCONF_PARAM_OPEN_DRAIN:
-+ if (port == PORT3)
-+ reg = GPIO3_OD;
-+ else
-+ reg = GPIO_OD(port);
-+ gpio_setbit(info->membase[0], reg, PORT_PIN(port));
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_PULL:
-+ if (port == PORT3)
-+ reg = GPIO3_PUDEN;
-+ else
-+ reg = GPIO_PUDEN(port);
-+ if (arg == 0) {
-+ gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
-+ break;
-+ }
-+ gpio_setbit(info->membase[0], reg, PORT_PIN(port));
-+
-+ if (port == PORT3)
-+ reg = GPIO3_PUDSEL;
-+ else
-+ reg = GPIO_PUDSEL(port);
-+ if (arg == 1)
-+ gpio_clearbit(info->membase[0], reg, PORT_PIN(port));
-+ else if (arg == 2)
-+ gpio_setbit(info->membase[0], reg, PORT_PIN(port));
-+ else
-+ dev_err(pctldev->dev, "Invalid pull value %d\n", arg);
-+ break;
-+
-+ default:
-+ dev_err(pctldev->dev, "Invalid config param %04x\n", param);
-+ return -ENOTSUPP;
-+ }
-+ return 0;
-+}
-+
-+struct pinconf_ops xway_pinconf_ops = {
-+ .pin_config_get = xway_pinconf_get,
-+ .pin_config_set = xway_pinconf_set,
-+};
-+
-+static struct pinctrl_desc xway_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .confops = &xway_pinconf_ops,
-+};
-+
-+static inline int xway_mux_apply(struct pinctrl_dev *pctrldev,
-+ int pin, int mux)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ int port = PORT(pin);
-+ u32 alt1_reg = GPIO_ALT1(pin);
-+
-+ if (port == PORT3)
-+ alt1_reg = GPIO3_ALT1;
-+
-+ if (mux & MUX_ALT0)
-+ gpio_setbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
-+ else
-+ gpio_clearbit(info->membase[0], GPIO_ALT0(pin), PORT_PIN(pin));
-+
-+ if (mux & MUX_ALT1)
-+ gpio_setbit(info->membase[0], alt1_reg, PORT_PIN(pin));
-+ else
-+ gpio_clearbit(info->membase[0], alt1_reg, PORT_PIN(pin));
-+
-+ return 0;
-+}
-+
-+static const struct ltq_cfg_param xway_cfg_params[] = {
-+ {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
-+ {"lantiq,open-drain", LTQ_PINCONF_PARAM_OPEN_DRAIN},
-+};
-+
-+static struct ltq_pinmux_info xway_info = {
-+ .desc = &xway_pctrl_desc,
-+ .apply_mux = xway_mux_apply,
-+ .params = xway_cfg_params,
-+ .num_params = ARRAY_SIZE(xway_cfg_params),
-+};
-+
-+/* --------- gpio_chip related code --------- */
-+static void xway_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
-+{
-+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
-+
-+ if (val)
-+ gpio_setbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
-+ else
-+ gpio_clearbit(info->membase[0], GPIO_OUT(pin), PORT_PIN(pin));
-+}
-+
-+static int xway_gpio_get(struct gpio_chip *chip, unsigned int pin)
-+{
-+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
-+
-+ return gpio_getbit(info->membase[0], GPIO_IN(pin), PORT_PIN(pin));
-+}
-+
-+static int xway_gpio_dir_in(struct gpio_chip *chip, unsigned int pin)
-+{
-+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
-+
-+ gpio_clearbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
-+
-+ return 0;
-+}
-+
-+static int xway_gpio_dir_out(struct gpio_chip *chip, unsigned int pin, int val)
-+{
-+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
-+
-+ gpio_setbit(info->membase[0], GPIO_DIR(pin), PORT_PIN(pin));
-+ xway_gpio_set(chip, pin, val);
-+
-+ return 0;
-+}
-+
-+static int xway_gpio_req(struct gpio_chip *chip, unsigned offset)
-+{
-+ int gpio = chip->base + offset;
-+
-+ return pinctrl_request_gpio(gpio);
-+}
-+
-+static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
-+{
-+ int gpio = chip->base + offset;
-+
-+ pinctrl_free_gpio(gpio);
-+}
-+
-+static struct gpio_chip xway_chip = {
-+ .label = "gpio-xway",
-+ .direction_input = xway_gpio_dir_in,
-+ .direction_output = xway_gpio_dir_out,
-+ .get = xway_gpio_get,
-+ .set = xway_gpio_set,
-+ .request = xway_gpio_req,
-+ .free = xway_gpio_free,
-+ .base = -1,
-+};
-+
-+
-+/* --------- register the pinctrl layer --------- */
-+static const unsigned xway_exin_pin_map[] = {GPIO0, GPIO1, GPIO2, GPIO39, GPIO46, GPIO9};
-+static const unsigned ase_exin_pins_map[] = {GPIO6, GPIO29, GPIO0};
-+
-+static struct pinctrl_xway_soc {
-+ int pin_count;
-+ const struct ltq_mfp_pin *mfp;
-+ const struct ltq_pin_group *grps;
-+ unsigned int num_grps;
-+ const struct ltq_pmx_func *funcs;
-+ unsigned int num_funcs;
-+ const unsigned *exin;
-+ unsigned int num_exin;
-+} soc_cfg[] = {
-+ /* legacy xway */
-+ {XWAY_MAX_PIN, xway_mfp,
-+ xway_grps, ARRAY_SIZE(xway_grps),
-+ danube_funcs, ARRAY_SIZE(danube_funcs),
-+ xway_exin_pin_map, 3},
-+ /* xway xr9 series */
-+ {XR9_MAX_PIN, xway_mfp,
-+ xway_grps, ARRAY_SIZE(xway_grps),
-+ xrx_funcs, ARRAY_SIZE(xrx_funcs),
-+ xway_exin_pin_map, 6},
-+ /* xway ase series */
-+ {XWAY_MAX_PIN, ase_mfp,
-+ ase_grps, ARRAY_SIZE(ase_grps),
-+ ase_funcs, ARRAY_SIZE(ase_funcs),
-+ ase_exin_pins_map, 3},
-+};
-+
-+static struct pinctrl_gpio_range xway_gpio_range = {
-+ .name = "XWAY GPIO",
-+ .gc = &xway_chip,
-+};
-+
-+static const struct of_device_id xway_match[] = {
-+ { .compatible = "lantiq,pinctrl-xway", .data = &soc_cfg[0]},
-+ { .compatible = "lantiq,pinctrl-xr9", .data = &soc_cfg[1]},
-+ { .compatible = "lantiq,pinctrl-ase", .data = &soc_cfg[2]},
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, xway_match);
-+
-+static int __devinit pinmux_xway_probe(struct platform_device *pdev)
-+{
-+ const struct of_device_id *match;
-+ const struct pinctrl_xway_soc *xway_soc;
-+ struct resource *res;
-+ int ret, i;
-+
-+ /* get and remap our register range */
-+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-+ if (!res) {
-+ dev_err(&pdev->dev, "Failed to get resource\n");
-+ return -ENOENT;
-+ }
-+ xway_info.membase[0] = devm_request_and_ioremap(&pdev->dev, res);
-+ if (!xway_info.membase[0]) {
-+ dev_err(&pdev->dev, "Failed to remap resource\n");
-+ return -ENOMEM;
-+ }
-+
-+ match = of_match_device(xway_match, &pdev->dev);
-+ if (match)
-+ xway_soc = (const struct pinctrl_xway_soc *) match->data;
-+ else
-+ xway_soc = &soc_cfg[0];
-+
-+ /* find out how many pads we have */
-+ xway_chip.ngpio = xway_soc->pin_count;
-+
-+ /* load our pad descriptors */
-+ xway_info.pads = devm_kzalloc(&pdev->dev,
-+ sizeof(struct pinctrl_pin_desc) * xway_chip.ngpio,
-+ GFP_KERNEL);
-+ if (!xway_info.pads) {
-+ dev_err(&pdev->dev, "Failed to allocate pads\n");
-+ return -ENOMEM;
-+ }
-+ for (i = 0; i < xway_chip.ngpio; i++) {
-+ /* strlen("ioXY") + 1 = 5 */
-+ char *name = devm_kzalloc(&pdev->dev, 5, GFP_KERNEL);
-+
-+ if (!name) {
-+ dev_err(&pdev->dev, "Failed to allocate pad name\n");
-+ return -ENOMEM;
-+ }
-+ snprintf(name, 5, "io%d", i);
-+ xway_info.pads[i].number = GPIO0 + i;
-+ xway_info.pads[i].name = name;
-+ }
-+ xway_pctrl_desc.pins = xway_info.pads;
-+
-+ /* load the gpio chip */
-+ xway_chip.dev = &pdev->dev;
-+ of_gpiochip_add(&xway_chip);
-+ ret = gpiochip_add(&xway_chip);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Failed to register gpio chip\n");
-+ return ret;
-+ }
-+
-+ /* setup the data needed by pinctrl */
-+ xway_pctrl_desc.name = dev_name(&pdev->dev);
-+ xway_pctrl_desc.npins = xway_chip.ngpio;
-+
-+ xway_info.num_pads = xway_chip.ngpio;
-+ xway_info.num_mfp = xway_chip.ngpio;
-+ xway_info.mfp = xway_soc->mfp;
-+ xway_info.grps = xway_soc->grps;
-+ xway_info.num_grps = xway_soc->num_grps;
-+ xway_info.funcs = xway_soc->funcs;
-+ xway_info.num_funcs = xway_soc->num_funcs;
-+ xway_info.exin = xway_soc->exin;
-+ xway_info.num_exin = xway_soc->num_exin;
-+
-+ /* register with the generic lantiq layer */
-+ ret = ltq_pinctrl_register(pdev, &xway_info);
-+ if (ret) {
-+ dev_err(&pdev->dev, "Failed to register pinctrl driver\n");
-+ return ret;
-+ }
-+
-+ /* finish with registering the gpio range in pinctrl */
-+ xway_gpio_range.npins = xway_chip.ngpio;
-+ xway_gpio_range.base = xway_chip.base;
-+ pinctrl_add_gpio_range(xway_info.pctrl, &xway_gpio_range);
-+ dev_info(&pdev->dev, "Init done\n");
-+ return 0;
-+}
-+
-+static struct platform_driver pinmux_xway_driver = {
-+ .probe = pinmux_xway_probe,
-+ .driver = {
-+ .name = "pinctrl-xway",
-+ .owner = THIS_MODULE,
-+ .of_match_table = xway_match,
-+ },
-+};
-+
-+static int __init pinmux_xway_init(void)
-+{
-+ return platform_driver_register(&pinmux_xway_driver);
-+}
-+
-+core_initcall_sync(pinmux_xway_init);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0011-OF-pinctrl-MIPS-lantiq-adds-support-for-FALCON-SoC.patch b/target/linux/lantiq/patches-3.6/0011-OF-pinctrl-MIPS-lantiq-adds-support-for-FALCON-SoC.patch
deleted file mode 100644
index ec413fcd4f..0000000000
--- a/target/linux/lantiq/patches-3.6/0011-OF-pinctrl-MIPS-lantiq-adds-support-for-FALCON-SoC.patch
+++ /dev/null
@@ -1,554 +0,0 @@
-From e316cb2b16bbfbe48387b56e7e6b5d32ec686f82 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 20 May 2012 00:33:56 +0200
-Subject: [PATCH 11/15] OF: pinctrl: MIPS: lantiq: adds support for FALCON SoC
-
-Implement support for pinctrl on lantiq/falcon socs. The FALCON has 5 banks
-of up to 32 pins.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Cc: devicetree-discuss@lists.ozlabs.org
-Cc: linux-kernel@vger.kernel.org
----
- .../include/asm/mach-lantiq/falcon/lantiq_soc.h | 4 +
- arch/mips/lantiq/Kconfig | 1 +
- drivers/pinctrl/Kconfig | 5 +
- drivers/pinctrl/Makefile | 1 +
- drivers/pinctrl/pinctrl-falcon.c | 468 ++++++++++++++++++++
- 5 files changed, 479 insertions(+)
- create mode 100644 drivers/pinctrl/pinctrl-falcon.c
-
-diff --git a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
-index b385252..fccac35 100644
---- a/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
-+++ b/arch/mips/include/asm/mach-lantiq/falcon/lantiq_soc.h
-@@ -57,6 +57,10 @@ extern __iomem void *ltq_sys1_membase;
- #define ltq_sys1_w32_mask(clear, set, reg) \
- ltq_sys1_w32((ltq_sys1_r32(reg) & ~(clear)) | (set), reg)
-
-+/* allow the gpio and pinctrl drivers to talk to eachother */
-+extern int pinctrl_falcon_get_range_size(int id);
-+extern void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range);
-+
- /*
- * to keep the irq code generic we need to define this to 0 as falcon
- * has no EIU/EBU
-diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
-index 080c013..d84f361 100644
---- a/arch/mips/lantiq/Kconfig
-+++ b/arch/mips/lantiq/Kconfig
-@@ -20,6 +20,7 @@ config SOC_XWAY
-
- config SOC_FALCON
- bool "FALCON"
-+ select PINCTRL_FALCON
-
- endchoice
-
-diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
-index f77dce0..45d2158 100644
---- a/drivers/pinctrl/Kconfig
-+++ b/drivers/pinctrl/Kconfig
-@@ -65,6 +65,11 @@ config PINCTRL_PXA3xx
- bool
- select PINMUX
-
-+config PINCTRL_FALCON
-+ bool
-+ depends on SOC_FALCON
-+ depends on PINCTRL_LANTIQ
-+
- config PINCTRL_MMP2
- bool "MMP2 pin controller driver"
- depends on ARCH_MMP
-diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile
-index e19e207..c0566c8 100644
---- a/drivers/pinctrl/Makefile
-+++ b/drivers/pinctrl/Makefile
-@@ -14,6 +14,7 @@ obj-$(CONFIG_PINCTRL_IMX51) += pinctrl-imx51.o
- obj-$(CONFIG_PINCTRL_IMX53) += pinctrl-imx53.o
- obj-$(CONFIG_PINCTRL_IMX6Q) += pinctrl-imx6q.o
- obj-$(CONFIG_PINCTRL_PXA3xx) += pinctrl-pxa3xx.o
-+obj-$(CONFIG_PINCTRL_FALCON) += pinctrl-falcon.o
- obj-$(CONFIG_PINCTRL_MMP2) += pinctrl-mmp2.o
- obj-$(CONFIG_PINCTRL_MXS) += pinctrl-mxs.o
- obj-$(CONFIG_PINCTRL_IMX23) += pinctrl-imx23.o
-diff --git a/drivers/pinctrl/pinctrl-falcon.c b/drivers/pinctrl/pinctrl-falcon.c
-new file mode 100644
-index 0000000..ee73059
---- /dev/null
-+++ b/drivers/pinctrl/pinctrl-falcon.c
-@@ -0,0 +1,468 @@
-+/*
-+ * linux/drivers/pinctrl/pinmux-falcon.c
-+ * based on linux/drivers/pinctrl/pinmux-pxa910.c
-+ *
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright (C) 2012 Thomas Langer <thomas.langer@lantiq.com>
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/gpio.h>
-+#include <linux/interrupt.h>
-+#include <linux/slab.h>
-+#include <linux/export.h>
-+#include <linux/err.h>
-+#include <linux/module.h>
-+#include <linux/of.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_address.h>
-+#include <linux/of_gpio.h>
-+#include <linux/platform_device.h>
-+
-+#include "pinctrl-lantiq.h"
-+
-+#include <lantiq_soc.h>
-+
-+/* Multiplexer Control Register */
-+#define LTQ_PADC_MUX(x) (x * 0x4)
-+/* Pull Up Enable Register */
-+#define LTQ_PADC_PUEN 0x80
-+/* Pull Down Enable Register */
-+#define LTQ_PADC_PDEN 0x84
-+/* Slew Rate Control Register */
-+#define LTQ_PADC_SRC 0x88
-+/* Drive Current Control Register */
-+#define LTQ_PADC_DCC 0x8C
-+/* Pad Control Availability Register */
-+#define LTQ_PADC_AVAIL 0xF0
-+
-+#define pad_r32(p, reg) ltq_r32(p + reg)
-+#define pad_w32(p, val, reg) ltq_w32(val, p + reg)
-+#define pad_w32_mask(c, clear, set, reg) \
-+ pad_w32(c, (pad_r32(c, reg) & ~(clear)) | (set), reg)
-+
-+#define pad_getbit(m, r, p) (!!(ltq_r32(m + r) & (1 << p)))
-+
-+#define PORTS 5
-+#define PINS 32
-+#define PORT(x) (x / PINS)
-+#define PORT_PIN(x) (x % PINS)
-+
-+#define MFP_FALCON(a, f0, f1, f2, f3) \
-+{ \
-+ .name = #a, \
-+ .pin = a, \
-+ .func = { \
-+ FALCON_MUX_##f0, \
-+ FALCON_MUX_##f1, \
-+ FALCON_MUX_##f2, \
-+ FALCON_MUX_##f3, \
-+ }, \
-+}
-+
-+#define GRP_MUX(a, m, p) \
-+{ \
-+ .name = a, \
-+ .mux = FALCON_MUX_##m, \
-+ .pins = p, \
-+ .npins = ARRAY_SIZE(p), \
-+}
-+
-+enum falcon_mux {
-+ FALCON_MUX_GPIO = 0,
-+ FALCON_MUX_RST,
-+ FALCON_MUX_NTR,
-+ FALCON_MUX_MDIO,
-+ FALCON_MUX_LED,
-+ FALCON_MUX_SPI,
-+ FALCON_MUX_ASC,
-+ FALCON_MUX_I2C,
-+ FALCON_MUX_HOSTIF,
-+ FALCON_MUX_SLIC,
-+ FALCON_MUX_JTAG,
-+ FALCON_MUX_PCM,
-+ FALCON_MUX_MII,
-+ FALCON_MUX_PHY,
-+ FALCON_MUX_NONE = 0xffff,
-+};
-+
-+static struct pinctrl_pin_desc falcon_pads[PORTS * PINS];
-+static int pad_count[PORTS];
-+
-+static void lantiq_load_pin_desc(struct pinctrl_pin_desc *d, int bank, int len)
-+{
-+ int base = bank * PINS;
-+ int i;
-+
-+ for (i = 0; i < len; i++) {
-+ /* strlen("ioXYZ") + 1 = 6 */
-+ char *name = kzalloc(6, GFP_KERNEL);
-+ snprintf(name, 6, "io%d", base + i);
-+ d[i].number = base + i;
-+ d[i].name = name;
-+ }
-+ pad_count[bank] = len;
-+}
-+
-+static struct ltq_mfp_pin falcon_mfp[] = {
-+ /* pin f0 f1 f2 f3 */
-+ MFP_FALCON(GPIO0, RST, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO1, GPIO, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO2, GPIO, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO3, GPIO, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO4, NTR, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO5, NTR, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO6, RST, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO7, MDIO, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO8, MDIO, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO9, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO10, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO11, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO12, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO13, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO14, LED, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO32, ASC, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO33, ASC, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO34, SPI, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO35, SPI, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO36, SPI, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO37, SPI, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO38, SPI, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO39, I2C, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO40, I2C, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO41, HOSTIF, GPIO, HOSTIF, JTAG),
-+ MFP_FALCON(GPIO42, HOSTIF, GPIO, HOSTIF, NONE),
-+ MFP_FALCON(GPIO43, SLIC, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO44, SLIC, GPIO, PCM, ASC),
-+ MFP_FALCON(GPIO45, SLIC, GPIO, PCM, ASC),
-+ MFP_FALCON(GPIO64, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO65, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO66, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO67, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO68, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO69, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO70, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO71, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO72, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO73, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO74, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO75, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO76, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO77, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO78, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO79, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO80, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO81, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO82, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO83, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO84, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO85, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO86, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO87, MII, GPIO, NONE, NONE),
-+ MFP_FALCON(GPIO88, PHY, GPIO, NONE, NONE),
-+};
-+
-+static const unsigned pins_por[] = {GPIO0};
-+static const unsigned pins_ntr[] = {GPIO4};
-+static const unsigned pins_ntr8k[] = {GPIO5};
-+static const unsigned pins_hrst[] = {GPIO6};
-+static const unsigned pins_mdio[] = {GPIO7, GPIO8};
-+static const unsigned pins_bled[] = {GPIO7, GPIO10, GPIO11,
-+ GPIO12, GPIO13, GPIO14};
-+static const unsigned pins_asc0[] = {GPIO32, GPIO33};
-+static const unsigned pins_spi[] = {GPIO34, GPIO35, GPIO36};
-+static const unsigned pins_spi_cs0[] = {GPIO37};
-+static const unsigned pins_spi_cs1[] = {GPIO38};
-+static const unsigned pins_i2c[] = {GPIO39, GPIO40};
-+static const unsigned pins_jtag[] = {GPIO41};
-+static const unsigned pins_slic[] = {GPIO43, GPIO44, GPIO45};
-+static const unsigned pins_pcm[] = {GPIO44, GPIO45};
-+static const unsigned pins_asc1[] = {GPIO44, GPIO45};
-+
-+static struct ltq_pin_group falcon_grps[] = {
-+ GRP_MUX("por", RST, pins_por),
-+ GRP_MUX("ntr", NTR, pins_ntr),
-+ GRP_MUX("ntr8k", NTR, pins_ntr8k),
-+ GRP_MUX("hrst", RST, pins_hrst),
-+ GRP_MUX("mdio", MDIO, pins_mdio),
-+ GRP_MUX("bootled", LED, pins_bled),
-+ GRP_MUX("asc0", ASC, pins_asc0),
-+ GRP_MUX("spi", SPI, pins_spi),
-+ GRP_MUX("spi cs0", SPI, pins_spi_cs0),
-+ GRP_MUX("spi cs1", SPI, pins_spi_cs1),
-+ GRP_MUX("i2c", I2C, pins_i2c),
-+ GRP_MUX("jtag", JTAG, pins_jtag),
-+ GRP_MUX("slic", SLIC, pins_slic),
-+ GRP_MUX("pcm", PCM, pins_pcm),
-+ GRP_MUX("asc1", ASC, pins_asc1),
-+};
-+
-+static const char * const ltq_rst_grps[] = {"por", "hrst"};
-+static const char * const ltq_ntr_grps[] = {"ntr", "ntr8k"};
-+static const char * const ltq_mdio_grps[] = {"mdio"};
-+static const char * const ltq_bled_grps[] = {"bootled"};
-+static const char * const ltq_asc_grps[] = {"asc0", "asc1"};
-+static const char * const ltq_spi_grps[] = {"spi", "spi cs0", "spi cs1"};
-+static const char * const ltq_i2c_grps[] = {"i2c"};
-+static const char * const ltq_jtag_grps[] = {"jtag"};
-+static const char * const ltq_slic_grps[] = {"slic"};
-+static const char * const ltq_pcm_grps[] = {"pcm"};
-+
-+static struct ltq_pmx_func falcon_funcs[] = {
-+ {"rst", ARRAY_AND_SIZE(ltq_rst_grps)},
-+ {"ntr", ARRAY_AND_SIZE(ltq_ntr_grps)},
-+ {"mdio", ARRAY_AND_SIZE(ltq_mdio_grps)},
-+ {"led", ARRAY_AND_SIZE(ltq_bled_grps)},
-+ {"asc", ARRAY_AND_SIZE(ltq_asc_grps)},
-+ {"spi", ARRAY_AND_SIZE(ltq_spi_grps)},
-+ {"i2c", ARRAY_AND_SIZE(ltq_i2c_grps)},
-+ {"jtag", ARRAY_AND_SIZE(ltq_jtag_grps)},
-+ {"slic", ARRAY_AND_SIZE(ltq_slic_grps)},
-+ {"pcm", ARRAY_AND_SIZE(ltq_pcm_grps)},
-+};
-+
-+
-+
-+
-+/* --------- pinconf related code --------- */
-+static int falcon_pinconf_group_get(struct pinctrl_dev *pctrldev,
-+ unsigned group, unsigned long *config)
-+{
-+ return -ENOTSUPP;
-+}
-+
-+static int falcon_pinconf_group_set(struct pinctrl_dev *pctrldev,
-+ unsigned group, unsigned long config)
-+{
-+ return -ENOTSUPP;
-+}
-+
-+static int falcon_pinconf_get(struct pinctrl_dev *pctrldev,
-+ unsigned pin, unsigned long *config)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(*config);
-+ void __iomem *mem = info->membase[PORT(pin)];
-+
-+ switch (param) {
-+ case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
-+ *config = LTQ_PINCONF_PACK(param,
-+ !!pad_getbit(mem, LTQ_PADC_DCC, PORT_PIN(pin)));
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_SLEW_RATE:
-+ *config = LTQ_PINCONF_PACK(param,
-+ !!pad_getbit(mem, LTQ_PADC_SRC, PORT_PIN(pin)));
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_PULL:
-+ if (pad_getbit(mem, LTQ_PADC_PDEN, PORT_PIN(pin)))
-+ *config = LTQ_PINCONF_PACK(param, 1);
-+ else if (pad_getbit(mem, LTQ_PADC_PUEN, PORT_PIN(pin)))
-+ *config = LTQ_PINCONF_PACK(param, 2);
-+ else
-+ *config = LTQ_PINCONF_PACK(param, 0);
-+
-+ break;
-+
-+ default:
-+ return -ENOTSUPP;
-+ }
-+
-+ return 0;
-+}
-+
-+static int falcon_pinconf_set(struct pinctrl_dev *pctrldev,
-+ unsigned pin, unsigned long config)
-+{
-+ enum ltq_pinconf_param param = LTQ_PINCONF_UNPACK_PARAM(config);
-+ int arg = LTQ_PINCONF_UNPACK_ARG(config);
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ void __iomem *mem = info->membase[PORT(pin)];
-+ u32 reg;
-+
-+ switch (param) {
-+ case LTQ_PINCONF_PARAM_DRIVE_CURRENT:
-+ reg = LTQ_PADC_DCC;
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_SLEW_RATE:
-+ reg = LTQ_PADC_SRC;
-+ break;
-+
-+ case LTQ_PINCONF_PARAM_PULL:
-+ if (arg == 1)
-+ reg = LTQ_PADC_PDEN;
-+ else
-+ reg = LTQ_PADC_PUEN;
-+ break;
-+
-+ default:
-+ pr_err("%s: Invalid config param %04x\n",
-+ pinctrl_dev_get_name(pctrldev), param);
-+ return -ENOTSUPP;
-+ }
-+
-+ pad_w32(mem, BIT(PORT_PIN(pin)), reg);
-+ if (!(pad_r32(mem, reg) & BIT(PORT_PIN(pin))))
-+ return -ENOTSUPP;
-+ return 0;
-+}
-+
-+static void falcon_pinconf_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s, unsigned offset)
-+{
-+}
-+
-+static void falcon_pinconf_group_dbg_show(struct pinctrl_dev *pctrldev,
-+ struct seq_file *s, unsigned selector)
-+{
-+}
-+
-+struct pinconf_ops falcon_pinconf_ops = {
-+ .pin_config_get = falcon_pinconf_get,
-+ .pin_config_set = falcon_pinconf_set,
-+ .pin_config_group_get = falcon_pinconf_group_get,
-+ .pin_config_group_set = falcon_pinconf_group_set,
-+ .pin_config_dbg_show = falcon_pinconf_dbg_show,
-+ .pin_config_group_dbg_show = falcon_pinconf_group_dbg_show,
-+};
-+
-+static struct pinctrl_desc falcon_pctrl_desc = {
-+ .owner = THIS_MODULE,
-+ .pins = falcon_pads,
-+ .confops = &falcon_pinconf_ops,
-+};
-+
-+static inline int falcon_mux_apply(struct pinctrl_dev *pctrldev,
-+ int mfp, int mux)
-+{
-+ struct ltq_pinmux_info *info = pinctrl_dev_get_drvdata(pctrldev);
-+ int port = PORT(info->mfp[mfp].pin);
-+
-+ if ((port >= PORTS) || (!info->membase[port]))
-+ return -ENODEV;
-+
-+ pad_w32(info->membase[port], mux,
-+ LTQ_PADC_MUX(PORT_PIN(info->mfp[mfp].pin)));
-+ return 0;
-+}
-+
-+static const struct ltq_cfg_param falcon_cfg_params[] = {
-+ {"lantiq,pull", LTQ_PINCONF_PARAM_PULL},
-+ {"lantiq,drive-current", LTQ_PINCONF_PARAM_DRIVE_CURRENT},
-+ {"lantiq,slew-rate", LTQ_PINCONF_PARAM_SLEW_RATE},
-+};
-+
-+static struct ltq_pinmux_info falcon_info = {
-+ .desc = &falcon_pctrl_desc,
-+ .apply_mux = falcon_mux_apply,
-+};
-+
-+
-+
-+
-+/* --------- register the pinctrl layer --------- */
-+
-+int pinctrl_falcon_get_range_size(int id)
-+{
-+ u32 avail;
-+
-+ if ((id >= PORTS) || (!falcon_info.membase[id]))
-+ return -EINVAL;
-+
-+ avail = pad_r32(falcon_info.membase[id], LTQ_PADC_AVAIL);
-+
-+ return fls(avail);
-+}
-+
-+void pinctrl_falcon_add_gpio_range(struct pinctrl_gpio_range *range)
-+{
-+ pinctrl_add_gpio_range(falcon_info.pctrl, range);
-+}
-+
-+static int pinctrl_falcon_probe(struct platform_device *pdev)
-+{
-+ struct device_node *np;
-+ int pad_count = 0;
-+ int ret = 0;
-+
-+ /* load and remap the pad resources of the different banks */
-+ for_each_compatible_node(np, NULL, "lantiq,pad-falcon") {
-+ struct platform_device *ppdev = of_find_device_by_node(np);
-+ const __be32 *bank = of_get_property(np, "lantiq,bank", NULL);
-+ struct resource res;
-+ u32 avail;
-+ int pins;
-+
-+ if (!ppdev) {
-+ dev_err(&pdev->dev, "failed to find pad pdev\n");
-+ continue;
-+ }
-+ if (!bank || *bank >= PORTS)
-+ continue;
-+ if (of_address_to_resource(np, 0, &res))
-+ continue;
-+ falcon_info.clk[*bank] = clk_get(&ppdev->dev, NULL);
-+ if (IS_ERR(falcon_info.clk[*bank])) {
-+ dev_err(&ppdev->dev, "failed to get clock\n");
-+ return PTR_ERR(falcon_info.clk[*bank]);
-+ }
-+ falcon_info.membase[*bank] =
-+ devm_request_and_ioremap(&pdev->dev, &res);
-+ if (!falcon_info.membase[*bank]) {
-+ dev_err(&pdev->dev,
-+ "Failed to remap memory for bank %d\n",
-+ *bank);
-+ return -ENOMEM;
-+ }
-+ avail = pad_r32(falcon_info.membase[*bank],
-+ LTQ_PADC_AVAIL);
-+ pins = fls(avail);
-+ lantiq_load_pin_desc(&falcon_pads[pad_count], *bank, pins);
-+ pad_count += pins;
-+ clk_enable(falcon_info.clk[*bank]);
-+ dev_dbg(&pdev->dev, "found %s with %d pads\n",
-+ res.name, pins);
-+ }
-+ dev_dbg(&pdev->dev, "found a total of %d pads\n", pad_count);
-+ falcon_pctrl_desc.name = dev_name(&pdev->dev);
-+ falcon_pctrl_desc.npins = pad_count;
-+
-+ falcon_info.mfp = falcon_mfp;
-+ falcon_info.num_mfp = ARRAY_SIZE(falcon_mfp);
-+ falcon_info.grps = falcon_grps;
-+ falcon_info.num_grps = ARRAY_SIZE(falcon_grps);
-+ falcon_info.funcs = falcon_funcs;
-+ falcon_info.num_funcs = ARRAY_SIZE(falcon_funcs);
-+
-+ ret = ltq_pinctrl_register(pdev, &falcon_info);
-+ if (!ret)
-+ dev_info(&pdev->dev, "Init done\n");
-+ return ret;
-+}
-+
-+static const struct of_device_id falcon_match[] = {
-+ { .compatible = "lantiq,pinctrl-falcon" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, falcon_match);
-+
-+static struct platform_driver pinctrl_falcon_driver = {
-+ .probe = pinctrl_falcon_probe,
-+ .driver = {
-+ .name = "pinctrl-falcon",
-+ .owner = THIS_MODULE,
-+ .of_match_table = falcon_match,
-+ },
-+};
-+
-+int __init pinctrl_falcon_init(void)
-+{
-+ return platform_driver_register(&pinctrl_falcon_driver);
-+}
-+
-+core_initcall_sync(pinctrl_falcon_init);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0012-Document-devicetree-add-OF-documents-for-lantiq-xway.patch b/target/linux/lantiq/patches-3.6/0012-Document-devicetree-add-OF-documents-for-lantiq-xway.patch
deleted file mode 100644
index 84f930fa8a..0000000000
--- a/target/linux/lantiq/patches-3.6/0012-Document-devicetree-add-OF-documents-for-lantiq-xway.patch
+++ /dev/null
@@ -1,121 +0,0 @@
-From 5c56f76995691cf761f66d6d89a00eea80be660c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 20 Jul 2012 19:01:00 +0200
-Subject: [PATCH 12/15] Document: devicetree: add OF documents for lantiq xway
- pinctrl
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Cc: devicetree-discuss@lists.ozlabs.org
-Cc: linux-kernel@vger.kernel.org
----
- .../bindings/pinctrl/lantiq,xway-pinumx.txt | 97 ++++++++++++++++++++
- 1 file changed, 97 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
-
-diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
-new file mode 100644
-index 0000000..b5469db
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/lantiq,xway-pinumx.txt
-@@ -0,0 +1,97 @@
-+Lantiq XWAY pinmux controller
-+
-+Required properties:
-+- compatible: "lantiq,pinctrl-xway" or "lantiq,pinctrl-xr9"
-+- reg: Should contain the physical address and length of the gpio/pinmux
-+ register range
-+
-+Please refer to pinctrl-bindings.txt in this directory for details of the
-+common pinctrl bindings used by client devices, including the meaning of the
-+phrase "pin configuration node".
-+
-+Lantiq's pin configuration nodes act as a container for an abitrary number of
-+subnodes. Each of these subnodes represents some desired configuration for a
-+pin, a group, or a list of pins or groups. This configuration can include the
-+mux function to select on those group(s), and two pin configuration parameters:
-+pull-up and open-drain
-+
-+The name of each subnode is not important as long as it is unique; all subnodes
-+should be enumerated and processed purely based on their content.
-+
-+Each subnode only affects those parameters that are explicitly listed. In
-+other words, a subnode that lists a mux function but no pin configuration
-+parameters implies no information about any pin configuration parameters.
-+Similarly, a pin subnode that describes a pullup parameter implies no
-+information about e.g. the mux function.
-+
-+We support 2 types of nodes.
-+
-+Definition of mux function groups:
-+
-+Required subnode-properties:
-+- lantiq,groups : An array of strings. Each string contains the name of a group.
-+ Valid values for these names are listed below.
-+- lantiq,function: A string containing the name of the function to mux to the
-+ group. Valid values for function names are listed below.
-+
-+Valid values for group and function names:
-+
-+ mux groups:
-+ exin0, exin1, exin2, jtag, ebu a23, ebu a24, ebu a25, ebu clk, ebu cs1,
-+ ebu wait, nand ale, nand cs1, nand cle, spi, spi_cs1, spi_cs2, spi_cs3,
-+ spi_cs4, spi_cs5, spi_cs6, asc0, asc0 cts rts, stp, nmi , gpt1, gpt2,
-+ gpt3, clkout0, clkout1, clkout2, clkout3, gnt1, gnt2, gnt3, req1, req2,
-+ req3
-+
-+ additional mux groups (XR9 only):
-+ mdio, nand rdy, nand rd, exin3, exin4, gnt4, req4
-+
-+ functions:
-+ spi, asc, cgu, jtag, exin, stp, gpt, nmi, pci, ebu, mdio
-+
-+
-+
-+Definition of pin configurations:
-+
-+Required subnode-properties:
-+- lantiq,pins : An array of strings. Each string contains the name of a pin.
-+ Valid values for these names are listed below.
-+
-+Optional subnode-properties:
-+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
-+ 0: none, 1: down, 2: up.
-+- lantiq,open-drain: Boolean, enables open-drain on the defined pin.
-+
-+Valid values for XWAY pin names:
-+ Pinconf pins can be referenced via the names io0-io31.
-+
-+Valid values for XR9 pin names:
-+ Pinconf pins can be referenced via the names io0-io55.
-+
-+Example:
-+ gpio: pinmux@E100B10 {
-+ compatible = "lantiq,pinctrl-xway";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&state_default>;
-+
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+ reg = <0xE100B10 0xA0>;
-+
-+ state_default: pinmux {
-+ stp {
-+ lantiq,groups = "stp";
-+ lantiq,function = "stp";
-+ };
-+ pci {
-+ lantiq,groups = "gnt1";
-+ lantiq,function = "pci";
-+ };
-+ conf_out {
-+ lantiq,pins = "io4", "io5", "io6"; /* stp */
-+ lantiq,open-drain;
-+ lantiq,pull = <0>;
-+ };
-+ };
-+ };
-+
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0013-Document-devicetree-add-OF-documents-for-lantiq-falc.patch b/target/linux/lantiq/patches-3.6/0013-Document-devicetree-add-OF-documents-for-lantiq-falc.patch
deleted file mode 100644
index 28fd21276c..0000000000
--- a/target/linux/lantiq/patches-3.6/0013-Document-devicetree-add-OF-documents-for-lantiq-falc.patch
+++ /dev/null
@@ -1,108 +0,0 @@
-From 8e004b47b7645fe8ebe1bb81f75cd8f16650de68 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sun, 22 Jul 2012 09:23:50 +0200
-Subject: [PATCH 13/15] Document: devicetree: add OF documents for lantiq
- falcon pinctrl
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Signed-off-by: Thomas Langer <thomas.langer@lantiq.com>
-Acked-by: Linus Walleij <linus.walleij@linaro.org>
-Cc: devicetree-discuss@lists.ozlabs.org
-Cc: linux-kernel@vger.kernel.org
----
- .../bindings/pinctrl/lantiq,falcon-pinumx.txt | 83 ++++++++++++++++++++
- 1 file changed, 83 insertions(+)
- create mode 100644 Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
-
-diff --git a/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
-new file mode 100644
-index 0000000..daa7689
---- /dev/null
-+++ b/Documentation/devicetree/bindings/pinctrl/lantiq,falcon-pinumx.txt
-@@ -0,0 +1,83 @@
-+Lantiq FALCON pinmux controller
-+
-+Required properties:
-+- compatible: "lantiq,pinctrl-falcon"
-+- reg: Should contain the physical address and length of the gpio/pinmux
-+ register range
-+
-+Please refer to pinctrl-bindings.txt in this directory for details of the
-+common pinctrl bindings used by client devices, including the meaning of the
-+phrase "pin configuration node".
-+
-+Lantiq's pin configuration nodes act as a container for an abitrary number of
-+subnodes. Each of these subnodes represents some desired configuration for a
-+pin, a group, or a list of pins or groups. This configuration can include the
-+mux function to select on those group(s), and two pin configuration parameters:
-+pull-up and open-drain
-+
-+The name of each subnode is not important as long as it is unique; all subnodes
-+should be enumerated and processed purely based on their content.
-+
-+Each subnode only affects those parameters that are explicitly listed. In
-+other words, a subnode that lists a mux function but no pin configuration
-+parameters implies no information about any pin configuration parameters.
-+Similarly, a pin subnode that describes a pullup parameter implies no
-+information about e.g. the mux function.
-+
-+We support 2 types of nodes.
-+
-+Definition of mux function groups:
-+
-+Required subnode-properties:
-+- lantiq,groups : An array of strings. Each string contains the name of a group.
-+ Valid values for these names are listed below.
-+- lantiq,function: A string containing the name of the function to mux to the
-+ group. Valid values for function names are listed below.
-+
-+Valid values for group and function names:
-+
-+ mux groups:
-+ por, ntr, ntr8k, hrst, mdio, bootled, asc0, spi, spi cs0, spi cs1, i2c,
-+ jtag, slic, pcm, asc1
-+
-+ functions:
-+ rst, ntr, mdio, led, asc, spi, i2c, jtag, slic, pcm
-+
-+
-+Definition of pin configurations:
-+
-+Required subnode-properties:
-+- lantiq,pins : An array of strings. Each string contains the name of a pin.
-+ Valid values for these names are listed below.
-+
-+Optional subnode-properties:
-+- lantiq,pull: Integer, representing the pull-down/up to apply to the pin.
-+ 0: none, 1: down
-+- lantiq,drive-current: Boolean, enables drive-current
-+- lantiq,slew-rate: Boolean, enables slew-rate
-+
-+Example:
-+ pinmux0 {
-+ compatible = "lantiq,pinctrl-falcon";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&state_default>;
-+
-+ state_default: pinmux {
-+ asc0 {
-+ lantiq,groups = "asc0";
-+ lantiq,function = "asc";
-+ };
-+ ntr {
-+ lantiq,groups = "ntr8k";
-+ lantiq,function = "ntr";
-+ };
-+ i2c {
-+ lantiq,groups = "i2c";
-+ lantiq,function = "i2c";
-+ };
-+ hrst {
-+ lantiq,groups = "hrst";
-+ lantiq,function = "rst";
-+ };
-+ };
-+ };
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0014-MIPS-lantiq-make-use-of-__gpio_to_irq.patch b/target/linux/lantiq/patches-3.6/0014-MIPS-lantiq-make-use-of-__gpio_to_irq.patch
deleted file mode 100644
index 6b24782b68..0000000000
--- a/target/linux/lantiq/patches-3.6/0014-MIPS-lantiq-make-use-of-__gpio_to_irq.patch
+++ /dev/null
@@ -1,33 +0,0 @@
-From 6a88a0f762a61f212d4bbcf1ad45369f28014484 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 15 Aug 2012 15:41:50 +0200
-Subject: [PATCH 14/15] MIPS: lantiq: make use of __gpio_to_irq
-
-The gpio_chip struct allows us to set a .to_irq callback. Once this is set
-we can rely on the generic __gpio_to_irq() function to map gpio->irq allowing
-more than one gpio_chip to register an interrupt
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-lantiq/gpio.h | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/arch/mips/include/asm/mach-lantiq/gpio.h b/arch/mips/include/asm/mach-lantiq/gpio.h
-index f79505b..9ba1cae 100644
---- a/arch/mips/include/asm/mach-lantiq/gpio.h
-+++ b/arch/mips/include/asm/mach-lantiq/gpio.h
-@@ -1,10 +1,7 @@
- #ifndef __ASM_MIPS_MACH_LANTIQ_GPIO_H
- #define __ASM_MIPS_MACH_LANTIQ_GPIO_H
-
--static inline int gpio_to_irq(unsigned int gpio)
--{
-- return -1;
--}
-+#define gpio_to_irq __gpio_to_irq
-
- #define gpio_get_value __gpio_get_value
- #define gpio_set_value __gpio_set_value
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0015-GPIO-MIPS-lantiq-fix-overflow-inside-stp-xway-driver.patch b/target/linux/lantiq/patches-3.6/0015-GPIO-MIPS-lantiq-fix-overflow-inside-stp-xway-driver.patch
deleted file mode 100644
index d142420a3c..0000000000
--- a/target/linux/lantiq/patches-3.6/0015-GPIO-MIPS-lantiq-fix-overflow-inside-stp-xway-driver.patch
+++ /dev/null
@@ -1,34 +0,0 @@
-From c9e854cf940fbc09846c255895efceb3bc9bf095 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 11 Jul 2012 16:33:43 +0200
-Subject: [PATCH 15/15] GPIO: MIPS: lantiq: fix overflow inside stp-xway
- driver
-
-The driver was using a 16 bit field for storing the shadow value of the shift
-register cascade. This resulted in only the first 2 shift registeres receiving
-the correct data. The third shift register would always receive 0x00.
-
-Fix this by using a 32bit field for the shadow value.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Cc: linux-kernel@vger.kernel.org
----
- drivers/gpio/gpio-stp-xway.c | 2 +-
- 1 file changed, 1 insertion(+), 1 deletion(-)
-
-diff --git a/drivers/gpio/gpio-stp-xway.c b/drivers/gpio/gpio-stp-xway.c
-index e35096b..8bead0b 100644
---- a/drivers/gpio/gpio-stp-xway.c
-+++ b/drivers/gpio/gpio-stp-xway.c
-@@ -82,7 +82,7 @@ struct xway_stp {
- struct gpio_chip gc;
- void __iomem *virt;
- u32 edge; /* rising or falling edge triggered shift register */
-- u16 shadow; /* shadow the shift registers state */
-+ u32 shadow; /* shadow the shift registers state */
- u8 groups; /* we can drive 1-3 groups of 8bit each */
- u8 dsl; /* the 2 LSBs can be driven by the dsl core */
- u8 phy1; /* 3 bits can be driven by phy1 */
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0016-mtd-lantiq-Add-NAND-support-on-Lantiq-XWAY-SoC.patch b/target/linux/lantiq/patches-3.6/0016-mtd-lantiq-Add-NAND-support-on-Lantiq-XWAY-SoC.patch
deleted file mode 100644
index b57790a89d..0000000000
--- a/target/linux/lantiq/patches-3.6/0016-mtd-lantiq-Add-NAND-support-on-Lantiq-XWAY-SoC.patch
+++ /dev/null
@@ -1,257 +0,0 @@
-From 99f2b107924c07bee0bae7151426495fb815ca6e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 23 Aug 2012 20:28:32 +0200
-Subject: [PATCH] mtd: lantiq: Add NAND support on Lantiq XWAY SoC.
-
-The driver uses plat_nand. As the platform_device is loaded from DT, we need
-to lookup the node and attach our xway specific "struct platform_nand_data"
-to it.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
-Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
-Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
----
- drivers/mtd/nand/Kconfig | 8 ++
- drivers/mtd/nand/Makefile | 1 +
- drivers/mtd/nand/xway_nand.c | 201 ++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 210 insertions(+)
- create mode 100644 drivers/mtd/nand/xway_nand.c
-
-diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
-index 7101e8a..ce5cf02 100644
---- a/drivers/mtd/nand/Kconfig
-+++ b/drivers/mtd/nand/Kconfig
-@@ -580,4 +580,12 @@ config MTD_NAND_FSMC
- Enables support for NAND Flash chips on the ST Microelectronics
- Flexible Static Memory Controller (FSMC)
-
-+config MTD_NAND_XWAY
-+ tristate "Support for NAND on Lantiq XWAY SoC"
-+ depends on LANTIQ && SOC_TYPE_XWAY
-+ select MTD_NAND_PLATFORM
-+ help
-+ Enables support for NAND Flash chips on Lantiq XWAY SoCs. NAND is attached
-+ to the External Bus Unit (EBU).
-+
- endif # MTD_NAND
-diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile
-index ddee818..c4b0ab3 100644
---- a/drivers/mtd/nand/Makefile
-+++ b/drivers/mtd/nand/Makefile
-@@ -53,5 +53,6 @@ obj-$(CONFIG_MTD_NAND_MPC5121_NFC) += mpc5121_nfc.o
- obj-$(CONFIG_MTD_NAND_RICOH) += r852.o
- obj-$(CONFIG_MTD_NAND_JZ4740) += jz4740_nand.o
- obj-$(CONFIG_MTD_NAND_GPMI_NAND) += gpmi-nand/
-+obj-$(CONFIG_MTD_NAND_XWAY) += xway_nand.o
-
- nand-objs := nand_base.o nand_bbt.o
-diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
-new file mode 100644
-index 0000000..3f81dc8
---- /dev/null
-+++ b/drivers/mtd/nand/xway_nand.c
-@@ -0,0 +1,201 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * Copyright © 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/mtd/nand.h>
-+#include <linux/of_gpio.h>
-+#include <linux/of_platform.h>
-+
-+#include <lantiq_soc.h>
-+
-+/* nand registers */
-+#define EBU_ADDSEL1 0x24
-+#define EBU_NAND_CON 0xB0
-+#define EBU_NAND_WAIT 0xB4
-+#define EBU_NAND_ECC0 0xB8
-+#define EBU_NAND_ECC_AC 0xBC
-+
-+/* nand commands */
-+#define NAND_CMD_ALE (1 << 2)
-+#define NAND_CMD_CLE (1 << 3)
-+#define NAND_CMD_CS (1 << 4)
-+#define NAND_WRITE_CMD_RESET 0xff
-+#define NAND_WRITE_CMD (NAND_CMD_CS | NAND_CMD_CLE)
-+#define NAND_WRITE_ADDR (NAND_CMD_CS | NAND_CMD_ALE)
-+#define NAND_WRITE_DATA (NAND_CMD_CS)
-+#define NAND_READ_DATA (NAND_CMD_CS)
-+#define NAND_WAIT_WR_C (1 << 3)
-+#define NAND_WAIT_RD (0x1)
-+
-+/* we need to tel the ebu which addr we mapped the nand to */
-+#define ADDSEL1_MASK(x) (x << 4)
-+#define ADDSEL1_REGEN 1
-+
-+/* we need to tell the EBU that we have nand attached and set it up properly */
-+#define BUSCON1_SETUP (1 << 22)
-+#define BUSCON1_BCGEN_RES (0x3 << 12)
-+#define BUSCON1_WAITWRC2 (2 << 8)
-+#define BUSCON1_WAITRDC2 (2 << 6)
-+#define BUSCON1_HOLDC1 (1 << 4)
-+#define BUSCON1_RECOVC1 (1 << 2)
-+#define BUSCON1_CMULT4 1
-+
-+#define NAND_CON_CE (1 << 20)
-+#define NAND_CON_OUT_CS1 (1 << 10)
-+#define NAND_CON_IN_CS1 (1 << 8)
-+#define NAND_CON_PRE_P (1 << 7)
-+#define NAND_CON_WP_P (1 << 6)
-+#define NAND_CON_SE_P (1 << 5)
-+#define NAND_CON_CS_P (1 << 4)
-+#define NAND_CON_CSMUX (1 << 1)
-+#define NAND_CON_NANDM 1
-+
-+static void xway_reset_chip(struct nand_chip *chip)
-+{
-+ unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
-+ unsigned long flags;
-+
-+ nandaddr &= ~NAND_WRITE_ADDR;
-+ nandaddr |= NAND_WRITE_CMD;
-+
-+ /* finish with a reset */
-+ spin_lock_irqsave(&ebu_lock, flags);
-+ writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
-+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
-+ ;
-+ spin_unlock_irqrestore(&ebu_lock, flags);
-+}
-+
-+static void xway_select_chip(struct mtd_info *mtd, int chip)
-+{
-+
-+ switch (chip) {
-+ case -1:
-+ ltq_ebu_w32_mask(NAND_CON_CE, 0, EBU_NAND_CON);
-+ ltq_ebu_w32_mask(NAND_CON_NANDM, 0, EBU_NAND_CON);
-+ break;
-+ case 0:
-+ ltq_ebu_w32_mask(0, NAND_CON_NANDM, EBU_NAND_CON);
-+ ltq_ebu_w32_mask(0, NAND_CON_CE, EBU_NAND_CON);
-+ break;
-+ default:
-+ BUG();
-+ }
-+}
-+
-+static void xway_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-+{
-+ struct nand_chip *this = mtd->priv;
-+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-+ unsigned long flags;
-+
-+ if (ctrl & NAND_CTRL_CHANGE) {
-+ nandaddr &= ~(NAND_WRITE_CMD | NAND_WRITE_ADDR);
-+ if (ctrl & NAND_CLE)
-+ nandaddr |= NAND_WRITE_CMD;
-+ else
-+ nandaddr |= NAND_WRITE_ADDR;
-+ this->IO_ADDR_W = (void __iomem *) nandaddr;
-+ }
-+
-+ if (cmd != NAND_CMD_NONE) {
-+ spin_lock_irqsave(&ebu_lock, flags);
-+ writeb(cmd, this->IO_ADDR_W);
-+ while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
-+ ;
-+ spin_unlock_irqrestore(&ebu_lock, flags);
-+ }
-+}
-+
-+static int xway_dev_ready(struct mtd_info *mtd)
-+{
-+ return ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_RD;
-+}
-+
-+static unsigned char xway_read_byte(struct mtd_info *mtd)
-+{
-+ struct nand_chip *this = mtd->priv;
-+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_R;
-+ unsigned long flags;
-+ int ret;
-+
-+ spin_lock_irqsave(&ebu_lock, flags);
-+ ret = ltq_r8((void __iomem *)(nandaddr + NAND_READ_DATA));
-+ spin_unlock_irqrestore(&ebu_lock, flags);
-+
-+ return ret;
-+}
-+
-+static int xway_nand_probe(struct platform_device *pdev)
-+{
-+ struct nand_chip *this = platform_get_drvdata(pdev);
-+ unsigned long nandaddr = (unsigned long) this->IO_ADDR_W;
-+ const __be32 *cs = of_get_property(pdev->dev.of_node,
-+ "lantiq,cs", NULL);
-+ u32 cs_flag = 0;
-+
-+ /* load our CS from the DT. Either we find a valid 1 or default to 0 */
-+ if (cs && (*cs == 1))
-+ cs_flag = NAND_CON_IN_CS1 | NAND_CON_OUT_CS1;
-+
-+ /* setup the EBU to run in NAND mode on our base addr */
-+ ltq_ebu_w32(CPHYSADDR(nandaddr)
-+ | ADDSEL1_MASK(3) | ADDSEL1_REGEN, EBU_ADDSEL1);
-+
-+ ltq_ebu_w32(BUSCON1_SETUP | BUSCON1_BCGEN_RES | BUSCON1_WAITWRC2
-+ | BUSCON1_WAITRDC2 | BUSCON1_HOLDC1 | BUSCON1_RECOVC1
-+ | BUSCON1_CMULT4, LTQ_EBU_BUSCON1);
-+
-+ ltq_ebu_w32(NAND_CON_NANDM | NAND_CON_CSMUX | NAND_CON_CS_P
-+ | NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
-+ | cs_flag, EBU_NAND_CON);
-+
-+ /* finish with a reset */
-+ xway_reset_chip(this);
-+
-+ return 0;
-+}
-+
-+/* allow users to override the partition in DT using the cmdline */
-+static const char *part_probes[] = { "cmdlinepart", "ofpart", NULL };
-+
-+static struct platform_nand_data xway_nand_data = {
-+ .chip = {
-+ .nr_chips = 1,
-+ .chip_delay = 30,
-+ .part_probe_types = part_probes,
-+ },
-+ .ctrl = {
-+ .probe = xway_nand_probe,
-+ .cmd_ctrl = xway_cmd_ctrl,
-+ .dev_ready = xway_dev_ready,
-+ .select_chip = xway_select_chip,
-+ .read_byte = xway_read_byte,
-+ }
-+};
-+
-+/*
-+ * Try to find the node inside the DT. If it is available attach out
-+ * platform_nand_data
-+ */
-+static int __init xway_register_nand(void)
-+{
-+ struct device_node *node;
-+ struct platform_device *pdev;
-+
-+ node = of_find_compatible_node(NULL, NULL, "lantiq,nand-xway");
-+ if (!node)
-+ return -ENOENT;
-+ pdev = of_find_device_by_node(node);
-+ if (!pdev)
-+ return -EINVAL;
-+ pdev->dev.platform_data = &xway_nand_data;
-+ of_node_put(node);
-+ return 0;
-+}
-+
-+subsys_initcall(xway_register_nand);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0100-MIPS-lantiq-external-interrupt-units-not-loaded-prop.patch b/target/linux/lantiq/patches-3.6/0100-MIPS-lantiq-external-interrupt-units-not-loaded-prop.patch
deleted file mode 100644
index 1ae8d59a0f..0000000000
--- a/target/linux/lantiq/patches-3.6/0100-MIPS-lantiq-external-interrupt-units-not-loaded-prop.patch
+++ /dev/null
@@ -1,71 +0,0 @@
-From b27b8f1bd7d46f1affc9a2bc4142e248411c1afa Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 17:42:48 +0200
-Subject: [PATCH 100/113] MIPS: lantiq: external interrupt units not loaded
- properly
-
-The code references the wrong device node causing the number of EIU pins to
-be wrong.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/lantiq/irq.c | 2 +-
- drivers/pinctrl/pinctrl-xway.c | 15 +++++++++++++++
- 2 files changed, 16 insertions(+), 1 deletion(-)
-
-diff --git a/arch/mips/lantiq/irq.c b/arch/mips/lantiq/irq.c
-index f36acd1..8e55622 100644
---- a/arch/mips/lantiq/irq.c
-+++ b/arch/mips/lantiq/irq.c
-@@ -343,7 +343,7 @@ int __init icu_of_init(struct device_node *node, struct device_node *parent)
- eiu_node = of_find_compatible_node(NULL, NULL, "lantiq,eiu");
- if (eiu_node && !of_address_to_resource(eiu_node, 0, &res)) {
- /* find out how many external irq sources we have */
-- const __be32 *count = of_get_property(node,
-+ const __be32 *count = of_get_property(eiu_node,
- "lantiq,count", NULL);
-
- if (count)
-diff --git a/drivers/pinctrl/pinctrl-xway.c b/drivers/pinctrl/pinctrl-xway.c
-index b9bcaec..ea5e017 100644
---- a/drivers/pinctrl/pinctrl-xway.c
-+++ b/drivers/pinctrl/pinctrl-xway.c
-@@ -14,6 +14,7 @@
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
- #include <linux/of_gpio.h>
-+#include <linux/of_irq.h>
- #include <linux/ioport.h>
- #include <linux/io.h>
- #include <linux/device.h>
-@@ -618,6 +619,19 @@ static void xway_gpio_free(struct gpio_chip *chip, unsigned offset)
- pinctrl_free_gpio(gpio);
- }
-
-+static int xway_gpio_to_irq(struct gpio_chip *chip, unsigned int offset)
-+{
-+ struct ltq_pinmux_info *info = dev_get_drvdata(chip->dev);
-+ struct resource res;
-+ int i;
-+
-+ for (i = 0; i < info->num_exin; i++)
-+ if (offset == info->exin[i])
-+ if (of_irq_to_resource(chip->dev->of_node, i, &res))
-+ return res.start;
-+ return 0;
-+}
-+
- static struct gpio_chip xway_chip = {
- .label = "gpio-xway",
- .direction_input = xway_gpio_dir_in,
-@@ -626,6 +640,7 @@ static struct gpio_chip xway_chip = {
- .set = xway_gpio_set,
- .request = xway_gpio_req,
- .free = xway_gpio_free,
-+ .to_irq = xway_gpio_to_irq,
- .base = -1,
- };
-
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch b/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch
deleted file mode 100644
index e8a24051c5..0000000000
--- a/target/linux/lantiq/patches-3.6/0101-MIPS-lantiq-bootsel-bits-are-wrong.patch
+++ /dev/null
@@ -1,27 +0,0 @@
-From 50b5073dd266721a690323519fb906a56daa09d7 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 1 Nov 2012 20:39:43 +0100
-Subject: [PATCH 101/113] MIPS: lantiq: bootsel bits are wrong
-
----
- arch/mips/lantiq/xway/reset.c | 4 ++--
- 1 file changed, 2 insertions(+), 2 deletions(-)
-
-diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
-index 22c55f7..a89d1a3 100644
---- a/arch/mips/lantiq/xway/reset.c
-+++ b/arch/mips/lantiq/xway/reset.c
-@@ -34,8 +34,8 @@
- /* reset cause */
- #define RCU_STAT_SHIFT 26
- /* boot selection */
--#define RCU_BOOT_SEL_SHIFT 26
--#define RCU_BOOT_SEL_MASK 0x7
-+#define RCU_BOOT_SEL_SHIFT 17
-+#define RCU_BOOT_SEL_MASK 0xf
-
- /* remapped base addr of the reset control unit */
- static void __iomem *ltq_rcu_membase;
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0102-MIPS-lantiq-fixes-dma-irq-ack.patch b/target/linux/lantiq/patches-3.6/0102-MIPS-lantiq-fixes-dma-irq-ack.patch
deleted file mode 100644
index 89bcd709b6..0000000000
--- a/target/linux/lantiq/patches-3.6/0102-MIPS-lantiq-fixes-dma-irq-ack.patch
+++ /dev/null
@@ -1,62 +0,0 @@
-From 671f34ea864ddc353f32272b3a2f7ee62d6f8548 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 1 Nov 2012 20:50:39 +0100
-Subject: [PATCH 102/113] MIPS: lantiq: fixes dma irq ack
-
----
- arch/mips/lantiq/xway/dma.c | 11 ++++++++++-
- 1 file changed, 10 insertions(+), 1 deletion(-)
-
-diff --git a/arch/mips/lantiq/xway/dma.c b/arch/mips/lantiq/xway/dma.c
-index 55d2c4f..a301b3b 100644
---- a/arch/mips/lantiq/xway/dma.c
-+++ b/arch/mips/lantiq/xway/dma.c
-@@ -25,6 +25,7 @@
- #include <lantiq_soc.h>
- #include <xway_dma.h>
-
-+#define LTQ_DMA_ID 0x08
- #define LTQ_DMA_CTRL 0x10
- #define LTQ_DMA_CPOLL 0x14
- #define LTQ_DMA_CS 0x18
-@@ -89,7 +90,7 @@ ltq_dma_ack_irq(struct ltq_dma_channel *ch)
-
- local_irq_save(flags);
- ltq_dma_w32(ch->nr, LTQ_DMA_CS);
-- ltq_dma_w32(DMA_IRQ_ACK, LTQ_DMA_CIS);
-+ ltq_dma_w32(ltq_dma_r32(LTQ_DMA_CIS), LTQ_DMA_CIS);
- local_irq_restore(flags);
- }
- EXPORT_SYMBOL_GPL(ltq_dma_ack_irq);
-@@ -103,6 +104,7 @@ ltq_dma_open(struct ltq_dma_channel *ch)
- ltq_dma_w32(ch->nr, LTQ_DMA_CS);
- ltq_dma_w32_mask(0, DMA_CHAN_ON, LTQ_DMA_CCTRL);
- ltq_dma_enable_irq(ch);
-+ ltq_dma_ack_irq(ch);
- local_irq_restore(flag);
- }
- EXPORT_SYMBOL_GPL(ltq_dma_open);
-@@ -214,6 +216,7 @@ ltq_dma_init(struct platform_device *pdev)
- {
- struct clk *clk;
- struct resource *res;
-+ unsigned id;
- int i;
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-@@ -243,6 +246,12 @@ ltq_dma_init(struct platform_device *pdev)
- ltq_dma_w32(DMA_POLL | DMA_CLK_DIV4, LTQ_DMA_CPOLL);
- ltq_dma_w32_mask(DMA_CHAN_ON, 0, LTQ_DMA_CCTRL);
- }
-+
-+ id = ltq_dma_r32(LTQ_DMA_ID);
-+ dev_info(&pdev->dev,
-+ "Init done - hw rev: %X, ports: %d, channels: %d\n",
-+ id & 0x1f, (id >> 16) & 0xf, id >> 20);
-+
- dev_info(&pdev->dev, "init done\n");
- return 0;
- }
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0103-MIPS-lantiq-prom-code-invalidated-devicetree-memory.patch b/target/linux/lantiq/patches-3.6/0103-MIPS-lantiq-prom-code-invalidated-devicetree-memory.patch
deleted file mode 100644
index 0c6d91b03a..0000000000
--- a/target/linux/lantiq/patches-3.6/0103-MIPS-lantiq-prom-code-invalidated-devicetree-memory.patch
+++ /dev/null
@@ -1,36 +0,0 @@
-From 176aad2b97d2e7d623ef07ee9b68b71c7db8cce4 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Thu, 1 Nov 2012 20:50:52 +0100
-Subject: [PATCH 103/113] MIPS: lantiq: prom code invalidated devicetree
- memory
-
----
- arch/mips/lantiq/prom.c | 5 +----
- 1 file changed, 1 insertion(+), 4 deletions(-)
-
-diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
-index 6cfd611..9f9e875 100644
---- a/arch/mips/lantiq/prom.c
-+++ b/arch/mips/lantiq/prom.c
-@@ -87,9 +87,6 @@ void __init device_tree_init(void)
- reserve_bootmem(base, size, BOOTMEM_DEFAULT);
-
- unflatten_device_tree();
--
-- /* free the space reserved for the dt blob */
-- free_bootmem(base, size);
- }
-
- void __init prom_init(void)
-@@ -119,7 +116,7 @@ int __init plat_of_setup(void)
- sizeof(of_ids[0].compatible));
- strncpy(of_ids[1].compatible, "simple-bus",
- sizeof(of_ids[1].compatible));
-- return of_platform_bus_probe(NULL, of_ids, NULL);
-+ return of_platform_populate(NULL, of_ids, NULL, NULL);
- }
-
- arch_initcall(plat_of_setup);
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0104-MIPS-lantiq-xway-split-ltq_reset_once-into-2-subfunc.patch b/target/linux/lantiq/patches-3.6/0104-MIPS-lantiq-xway-split-ltq_reset_once-into-2-subfunc.patch
deleted file mode 100644
index 7a4c3c7e7c..0000000000
--- a/target/linux/lantiq/patches-3.6/0104-MIPS-lantiq-xway-split-ltq_reset_once-into-2-subfunc.patch
+++ /dev/null
@@ -1,60 +0,0 @@
-From 8fc2eacbe332fbf6bfd09425fb141bb47d843a78 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 09:32:46 +0200
-Subject: [PATCH 104/113] MIPS: lantiq: xway: split ltq_reset_once into 2
- subfunctions
-
-We need to call the reset functions from within the phy reset code and dont
-want to duplicate the access code for the reset registers.
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +++
- arch/mips/lantiq/xway/reset.c | 14 ++++++++++++--
- 2 files changed, 15 insertions(+), 2 deletions(-)
-
-diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-index 6a2df70..6b9f5be 100644
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-@@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase;
- extern void ltq_pmu_enable(unsigned int module);
- extern void ltq_pmu_disable(unsigned int module);
-
-+/* allow drivers to reset clock domains and ip cores */
-+void ltq_reset_once(unsigned int module, ulong u);
-+
- #endif /* CONFIG_SOC_TYPE_XWAY */
- #endif /* _LTQ_XWAY_H__ */
-diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
-index a89d1a3..1b77f82 100644
---- a/arch/mips/lantiq/xway/reset.c
-+++ b/arch/mips/lantiq/xway/reset.c
-@@ -55,12 +55,22 @@ unsigned char ltq_boot_select(void)
- return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
- }
-
-+static void ltq_reset_enter(unsigned int module)
-+{
-+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-+}
-+
-+static void ltq_reset_leave(unsigned int module)
-+{
-+ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-+}
-+
- /* reset a io domain for u micro seconds */
- void ltq_reset_once(unsigned int module, ulong u)
- {
-- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-+ ltq_reset_enter(RCU_RST_REQ);
- udelay(u);
-- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-+ ltq_reset_leave(RCU_RST_REQ);
- }
-
- static void ltq_machine_restart(char *command)
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0105-MIPS-lantiq-xway-adds-reset-code-for-11G-PHYs.patch b/target/linux/lantiq/patches-3.6/0105-MIPS-lantiq-xway-adds-reset-code-for-11G-PHYs.patch
deleted file mode 100644
index 9b2dc977e9..0000000000
--- a/target/linux/lantiq/patches-3.6/0105-MIPS-lantiq-xway-adds-reset-code-for-11G-PHYs.patch
+++ /dev/null
@@ -1,210 +0,0 @@
-From 4ed46c23c7257e15a419eb3176375601b312c157 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 09:47:09 +0200
-Subject: [PATCH 105/113] MIPS: lantiq: xway: adds reset code for 11G PHYs
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/a | 42 +++++++++++++
- arch/mips/b | 36 +++++++++++
- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 3 +
- arch/mips/lantiq/xway/reset.c | 63 +++++++++++++++++++-
- 4 files changed, 142 insertions(+), 2 deletions(-)
- create mode 100644 arch/mips/a
- create mode 100644 arch/mips/b
-
-diff --git a/arch/mips/a b/arch/mips/a
-new file mode 100644
-index 0000000..31e61f8
---- /dev/null
-+++ b/arch/mips/a
-@@ -0,0 +1,42 @@
-+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+index 6a2df70..056df1a 100644
-+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+@@ -87,5 +87,8 @@ extern __iomem void *ltq_cgu_membase;
-+ extern void ltq_pmu_enable(unsigned int module);
-+ extern void ltq_pmu_disable(unsigned int module);
-+
-++/* allow drivers to reset clock domains and ip cores */
-++void ltq_reset_once(unsigned int module, ulong u);
-++
-+ #endif /* CONFIG_SOC_TYPE_XWAY */
-+ #endif /* _LTQ_XWAY_H__ */
-+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
-+index 22c55f7..c2a7e65 100644
-+--- a/arch/mips/lantiq/xway/reset.c
-++++ b/arch/mips/lantiq/xway/reset.c
-+@@ -55,13 +62,23 @@ unsigned char ltq_boot_select(void)
-+ return (val >> RCU_BOOT_SEL_SHIFT) & RCU_BOOT_SEL_MASK;
-+ }
-+
-++static void ltq_reset_enter(unsigned int module)
-++{
-++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-++}
-++
-++static void ltq_reset_leave(unsigned int module)
-++{
-++ ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-++}
-++
-+ /* reset a io domain for u micro seconds */
-+ void ltq_reset_once(unsigned int module, ulong u)
-+ {
-+- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) | module, RCU_RST_REQ);
-++ ltq_reset_enter(RCU_RST_REQ);
-+ udelay(u);
-+- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
-++ ltq_reset_leave(RCU_RST_REQ);
-+ }
-+
-+ static void ltq_machine_restart(char *command)
-diff --git a/arch/mips/b b/arch/mips/b
-new file mode 100644
-index 0000000..c6a0323
---- /dev/null
-+++ b/arch/mips/b
-@@ -0,0 +1,36 @@
-+diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+index 6a2df70..056df1a 100644
-+--- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-++++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+@@ -87,8 +87,11 @@ extern __iomem void *ltq_cgu_membase;
-+ extern void ltq_pmu_enable(unsigned int module);
-+ extern void ltq_pmu_disable(unsigned int module);
-+
-++/* allow booting xrx200 phys */
-++int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
-++
-+ #endif /* CONFIG_SOC_TYPE_XWAY */
-+ #endif /* _LTQ_XWAY_H__ */
-+diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
-+index 22c55f7..c2a7e65 100644
-+--- a/arch/mips/lantiq/xway/reset.c
-++++ b/arch/mips/lantiq/xway/reset.c
-+@@ -26,11 +26,18 @@
-+
-+ /* reset request register */
-+ #define RCU_RST_REQ 0x0010
-++
-++#define VR9_RCU_GFS_ADD0 0x0020
-++#define VR9_RCU_GFS_ADD1 0x0068
-++
-+ /* reset status register */
-+ #define RCU_RST_STAT 0x0014
-+
-+ /* reboot bit */
-++#define VR9_RCU_RD_GPHY0 BIT(31)
-+ #define RCU_RD_SRST BIT(30)
-++#define VR9_RCU_RD_GPHY1 BIT(29)
-++
-+ /* reset cause */
-+ #define RCU_STAT_SHIFT 26
-+ /* boot selection */
-diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-index 6b9f5be..056df1a 100644
---- a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-+++ b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-@@ -90,5 +90,8 @@ extern void ltq_pmu_disable(unsigned int module);
- /* allow drivers to reset clock domains and ip cores */
- void ltq_reset_once(unsigned int module, ulong u);
-
-+/* allow booting xrx200 phys */
-+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr);
-+
- #endif /* CONFIG_SOC_TYPE_XWAY */
- #endif /* _LTQ_XWAY_H__ */
-diff --git a/arch/mips/lantiq/xway/reset.c b/arch/mips/lantiq/xway/reset.c
-index 1b77f82..56293cf 100644
---- a/arch/mips/lantiq/xway/reset.c
-+++ b/arch/mips/lantiq/xway/reset.c
-@@ -28,9 +28,15 @@
- #define RCU_RST_REQ 0x0010
- /* reset status register */
- #define RCU_RST_STAT 0x0014
-+/* vr9 gphy registers */
-+#define VR9_RCU_GFS_ADD0 0x0020
-+#define VR9_RCU_GFS_ADD1 0x0068
-
- /* reboot bit */
-+#define VR9_RCU_RD_GPHY0 BIT(31)
- #define RCU_RD_SRST BIT(30)
-+#define VR9_RCU_RD_GPHY1 BIT(29)
-+
- /* reset cause */
- #define RCU_STAT_SHIFT 26
- /* boot selection */
-@@ -65,13 +71,66 @@ static void ltq_reset_leave(unsigned int module)
- ltq_rcu_w32(ltq_rcu_r32(RCU_RST_REQ) & ~module, RCU_RST_REQ);
- }
-
-+/* reset / boot a gphy */
-+static struct ltq_xrx200_gphy_reset {
-+ u32 rd;
-+ u32 addr;
-+} xrx200_gphy[] = {
-+ {VR9_RCU_RD_GPHY0, VR9_RCU_GFS_ADD0},
-+ {VR9_RCU_RD_GPHY1, VR9_RCU_GFS_ADD1},
-+};
-+
-+/* reset and boot a gphy. these phys only exist on xrx200 SoC */
-+int xrx200_gphy_boot(struct device *dev, unsigned int id, dma_addr_t dev_addr)
-+{
-+ if (id > 1) {
-+ dev_err(dev, "%u is an invalid gphy id\n", id);
-+ return -EINVAL;
-+ }
-+ dev_info(dev, "booting GPHY%u firmware at %X\n", id, dev_addr);
-+
-+ ltq_reset_enter(xrx200_gphy[id].rd);
-+ ltq_rcu_w32(dev_addr, xrx200_gphy[id].addr);
-+ ltq_reset_leave(xrx200_gphy[id].rd);
-+ return 0;
-+}
-+EXPORT_SYMBOL_GPL(xrx200_gphy_boot);
-+
- /* reset a io domain for u micro seconds */
- void ltq_reset_once(unsigned int module, ulong u)
- {
-- ltq_reset_enter(RCU_RST_REQ);
-+ ltq_reset_enter(module);
- udelay(u);
-- ltq_reset_leave(RCU_RST_REQ);
-+ ltq_reset_leave(module);
-+}
-+
-+int ifx_rcu_rst(unsigned int reset_domain_id, unsigned int module_id)
-+{
-+ ltq_reset_once(BIT(module_id), 20);
-+ return 0;
-+}
-+EXPORT_SYMBOL(ifx_rcu_rst);
-+
-+unsigned int ifx_rcu_rst_req_read(void)
-+{
-+ unsigned int ret;
-+
-+ ret = ltq_rcu_r32(RCU_RST_REQ);
-+
-+ return ret;
-+}
-+EXPORT_SYMBOL(ifx_rcu_rst_req_read);
-+
-+void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask)
-+{
-+ unsigned int ret;
-+
-+ ret = ltq_rcu_r32(RCU_RST_REQ);
-+ ret &= ~mask;
-+ ret |= value & mask;
-+ ltq_rcu_w32(ret, RCU_RST_REQ);
- }
-+EXPORT_SYMBOL(ifx_rcu_rst_req_write);
-
- static void ltq_machine_restart(char *command)
- {
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0106-MIPS-lantiq-xway-adds-PHY11G-platform-code.patch b/target/linux/lantiq/patches-3.6/0106-MIPS-lantiq-xway-adds-PHY11G-platform-code.patch
deleted file mode 100644
index b6108c1c45..0000000000
--- a/target/linux/lantiq/patches-3.6/0106-MIPS-lantiq-xway-adds-PHY11G-platform-code.patch
+++ /dev/null
@@ -1,607 +0,0 @@
-From b2ea96b934fcf665b4c0cc844416a7a2618e198e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 09:52:50 +0200
-Subject: [PATCH 106/113] MIPS: lantiq: xway: adds PHY11G platform code
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/lantiq/xway/Makefile | 2 +-
- arch/mips/lantiq/xway/vr9_switch_regs.h | 425 +++++++++++++++++++++++++++++++
- arch/mips/lantiq/xway/xway_phy_fw.c | 146 +++++++++++
- 3 files changed, 572 insertions(+), 1 deletion(-)
- create mode 100644 arch/mips/lantiq/xway/vr9_switch_regs.h
- create mode 100644 arch/mips/lantiq/xway/xway_phy_fw.c
-
-diff --git a/arch/mips/lantiq/xway/Makefile b/arch/mips/lantiq/xway/Makefile
-index 70a58c7..1998b7c 100644
---- a/arch/mips/lantiq/xway/Makefile
-+++ b/arch/mips/lantiq/xway/Makefile
-@@ -1 +1 @@
--obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o
-+obj-y := prom.o sysctrl.o clk.o reset.o dma.o gptu.o xway_phy_fw.o
-diff --git a/arch/mips/lantiq/xway/vr9_switch_regs.h b/arch/mips/lantiq/xway/vr9_switch_regs.h
-new file mode 100644
-index 0000000..339e4c1
---- /dev/null
-+++ b/arch/mips/lantiq/xway/vr9_switch_regs.h
-@@ -0,0 +1,425 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-+ */
-+
-+#ifndef __VR9_SWITCH_REGS_H__
-+#define __VR9_SWITCH_REGS_H__
-+
-+/* Switch core registers */
-+struct vr9_switch_core_regs {
-+ __be32 swres;
-+ /* TODO: implement registers */
-+ __be32 rsvd0[0x3f];
-+};
-+
-+/* Switch buffer management registers */
-+struct vr9_switch_bm_regs {
-+ struct bm_core {
-+ __be32 ram_val3; /* RAM value 3 */
-+ __be32 ram_val2; /* RAM value 2 */
-+ __be32 ram_val1; /* RAM value 1 */
-+ __be32 ram_val0; /* RAM value 0 */
-+ __be32 ram_addr; /* RAM address */
-+ __be32 ram_ctrl; /* RAM access control */
-+ __be32 fsqm_gctrl; /* Free segment queue global control */
-+ __be32 cons_sel; /* Number of consumed segments */
-+ __be32 cons_pkt; /* Number of consumed packet pointers */
-+ __be32 gctrl; /* Global control */
-+ __be32 queue_gctrl; /* Queue manager global control */
-+ /* TODO: implement registers */
-+ __be32 rsvd0[0x35];
-+ } core;
-+
-+ struct bm_port {
-+ __be32 pcfg; /* Port config */
-+ __be32 rmon_ctrl; /* RMON control */
-+ } port[13];
-+
-+ __be32 rsvd0[0x66];
-+
-+ struct bm_queue {
-+ __be32 rsvd0;
-+ __be32 pqm_rs; /* Packet queue manager rate shape assignment */
-+ } queue[32];
-+
-+ struct bm_shaper {
-+ __be32 ctrl; /* Rate shaper control */
-+ __be32 cbs; /* Rate shaper committed burst size */
-+ __be32 ibs; /* Rate shaper instantaneous burst size */
-+ __be32 cir_ext; /* Rate shaper rate exponent */
-+ __be32 cir_mant; /* Rate shaper rate mantissa */
-+ } shaper[16];
-+
-+ __be32 rsvd1[0x2a8];
-+};
-+
-+/* Switch parser and classification engine registers */
-+struct vr9_switch_pce_regs {
-+ struct pce_core {
-+ __be32 tbl_key[16]; /* Table key data */
-+ __be32 tbl_mask; /* Table mask */
-+ __be32 tbl_val[5]; /* Table value */
-+ __be32 tbl_addr; /* Table entry address */
-+ __be32 tbl_ctrl; /* Table access control */
-+ __be32 tbl_stat; /* Table general status */
-+ __be32 age_0; /* Aging counter config 0 */
-+ __be32 age_1; /* Aging counter config 1 */
-+ __be32 pmap_1; /* Port map (monitoring) */
-+ __be32 pmap_2; /* Port map (multicast) */
-+ __be32 pmap_3; /* Port map (unknown unicast) */
-+ __be32 gctrl_0; /* Global control 0 */
-+ __be32 gctrl_1; /* Global control 1 */
-+ __be32 tcm_gctrl; /* Three-color marker global control */
-+ __be32 igmp_ctrl; /* IGMP control */
-+ __be32 igmp_drpm; /* IGMP default router port map */
-+ __be32 igmp_age_0; /* IGMP aging 0 */
-+ __be32 igmp_age_1; /* IGMP aging 1 */
-+ __be32 igmp_stat; /* IGMP status */
-+ __be32 wol_gctrl; /* Wake-on-LAN control */
-+ __be32 wol_da_0; /* Wake-on-LAN destination address 0 */
-+ __be32 wol_da_1; /* Wake-on-LAN destination address 1 */
-+ __be32 wol_da_2; /* Wake-on-LAN destination address 2 */
-+ __be32 wol_pw_0; /* Wake-on-LAN password 0 */
-+ __be32 wol_pw_1; /* Wake-on-LAN password 1 */
-+ __be32 wol_pw_2; /* Wake-on-LAN password 2 */
-+ __be32 ier_0; /* PCE global interrupt enable 0 */
-+ __be32 ier_1; /* PCE global interrupt enable 1 */
-+ __be32 isr_0; /* PCE global interrupt status 0 */
-+ __be32 isr_1; /* PCE global interrupt status 1 */
-+ __be32 parser_stat; /* Parser status */
-+ __be32 rsvd0[0x6];
-+ } core;
-+
-+ __be32 rsvd0[0x10];
-+
-+ struct pce_port {
-+ __be32 pctrl_0; /* Port control 0 */
-+ __be32 pctrl_1; /* Port control 1 */
-+ __be32 pctrl_2; /* Port control 2 */
-+ __be32 pctrl_3; /* Port control 3 */
-+ __be32 wol_ctrl; /* Wake-on-LAN control */
-+ __be32 vlan_ctrl; /* VLAN control */
-+ __be32 def_pvid; /* Default port VID */
-+ __be32 pstat; /* Port status */
-+ __be32 pier; /* Interrupt enable */
-+ __be32 pisr; /* Interrupt status */
-+ } port[13];
-+
-+ __be32 rsvd1[0x7e];
-+
-+ struct pce_meter {
-+ /* TODO: implement registers */
-+ __be32 rsvd0[0x7];
-+ } meter[8];
-+
-+ __be32 rsvd2[0x308];
-+};
-+
-+static inline unsigned int to_pce_tbl_key_id(unsigned int id)
-+{
-+ return 15 - id;
-+}
-+
-+static inline unsigned int to_pce_tbl_value_id(unsigned int id)
-+{
-+ return 4 - id;
-+}
-+
-+/* Switch ethernet MAC registers */
-+struct vr9_switch_mac_regs {
-+ struct mac_core {
-+ __be32 test; /* MAC test */
-+ __be32 pfad_cfg; /* Pause frame source address config */
-+ __be32 pfsa_0; /* Pause frame source address 0 */
-+ __be32 pfsa_1; /* Pause frame source address 1 */
-+ __be32 pfsa_2; /* Pause frame source address 2 */
-+ __be32 flen; /* Frame length */
-+ __be32 vlan_etype_0; /* VLAN ethertype 0 */
-+ __be32 vlan_etype_1; /* VLAN ethertype 1 */
-+ __be32 ier; /* Interrupt enable */
-+ __be32 isr; /* Interrupt status */
-+ __be32 rsvd0[0x36];
-+ } core;
-+
-+ struct mac_port {
-+ __be32 pstat; /* Port status */
-+ __be32 pisr; /* Interrupt status */
-+ __be32 pier; /* Interrupt enable */
-+ __be32 ctrl_0; /* Control 0 */
-+ __be32 ctrl_1; /* Control 1 */
-+ __be32 ctrl_2; /* Control 2 */
-+ __be32 ctrl_3; /* Control 3 */
-+ __be32 ctrl_4; /* Control 4 */
-+ __be32 ctrl_5; /* Control 5 */
-+ __be32 rsvd0[0x2];
-+ __be32 testen; /* Test enable */
-+ } port[13];
-+
-+ __be32 rsvd0[0xa4];
-+};
-+
-+/* Switch Fetch DMA registers */
-+struct vr9_switch_fdma_regs {
-+ struct fdma_core {
-+ __be32 ctrl; /* FDMA control */
-+ __be32 stetype; /* Special tag ethertype control */
-+ __be32 vtetype; /* VLAN tag ethertype control */
-+ __be32 stat; /* FDMA status */
-+ __be32 ier; /* FDMA interrupt enable */
-+ __be32 isr; /* FDMA interrupt status */
-+ } core;
-+
-+ __be32 rsvd0[0x3a];
-+
-+ struct fdma_port {
-+ __be32 pctrl; /* Port control */
-+ __be32 prio; /* Port priority */
-+ __be32 pstat_0; /* Port status 0 */
-+ __be32 pstat_1; /* Port status 1 */
-+ __be32 tstamp_0; /* Egress time stamp 0 */
-+ __be32 tstamp_1; /* Egress time stamp 1 */
-+ } port[13];
-+
-+ __be32 rsvd1[0x72];
-+};
-+
-+/* Switch Store DMA registers */
-+struct vr9_switch_sdma_regs {
-+ struct sdma_core {
-+ __be32 ctrl; /* SDMA Control */
-+ __be32 fcthr_1; /* Flow control threshold 1 */
-+ __be32 rsvd0;
-+ __be32 fcthr_3; /* Flow control threshold 3 */
-+ __be32 fcthr_4; /* Flow control threshold 4 */
-+ __be32 fcthr_5; /* Flow control threshold 5 */
-+ __be32 fcthr_6; /* Flow control threshold 6 */
-+ __be32 fcthr_7; /* Flow control threshold 7 */
-+ __be32 stat_0; /* SDMA status 0 */
-+ __be32 stat_1; /* SDMA status 1 */
-+ __be32 stat_2; /* SDMA status 2 */
-+ __be32 ier; /* SDMA interrupt enable */
-+ __be32 isr; /* SDMA interrupt status */
-+ } core;
-+
-+ __be32 rsvd0[0x73];
-+
-+ struct sdma_port {
-+ __be32 pctrl; /* Port control */
-+ __be32 prio; /* Port priority */
-+ __be32 pstat_0; /* Port status 0 */
-+ __be32 pstat_1; /* Port status 1 */
-+ __be32 tstamp_0; /* Ingress time stamp 0 */
-+ __be32 tstamp_1; /* Ingress time stamp 1 */
-+ } port[13];
-+
-+ __be32 rsvd1[0x32];
-+};
-+
-+/* Switch MDIO control and status registers */
-+struct vr9_switch_mdio_regs {
-+ __be32 glob_ctrl; /* Global control 0 */
-+ __be32 rsvd0[7];
-+ __be32 mdio_ctrl; /* MDIO control */
-+ __be32 mdio_read; /* MDIO read data */
-+ __be32 mdio_write; /* MDIO write data */
-+ __be32 mdc_cfg_0; /* MDC clock configuration 0 */
-+ __be32 mdc_cfg_1; /* MDC clock configuration 1 */
-+ __be32 rsvd1[0x3];
-+ __be32 phy_addr[6]; /* PHY address port 5..0 */
-+ __be32 mdio_stat[6]; /* MDIO PHY polling status port 0..5 */
-+ __be32 aneg_eee[6]; /* EEE auto-neg overrides port 0..5 */
-+ __be32 rsvd2[0x14];
-+};
-+
-+static inline unsigned int to_mdio_phyaddr_id(unsigned int id)
-+{
-+ return 5 - id;
-+}
-+
-+/* Switch xMII control registers */
-+struct vr9_switch_mii_regs {
-+ __be32 mii_cfg0; /* xMII port 0 configuration */
-+ __be32 pcdu0; /* Port 0 clock delay configuration */
-+ __be32 mii_cfg1; /* xMII port 1 configuration */
-+ __be32 pcdu1; /* Port 1 clock delay configuration */
-+ __be32 rsvd0[0x6];
-+ __be32 mii_cfg5; /* xMII port 5 configuration */
-+ __be32 pcdu5; /* Port 5 clock delay configuration */
-+ __be32 rsvd1[0x14];
-+ __be32 rxb_ctl_0; /* Port 0 receive buffer control */
-+ __be32 rxb_ctl_1; /* Port 1 receive buffer control */
-+ __be32 rxb_ctl_5; /* Port 5 receive buffer control */
-+ __be32 rsvd2[0x28];
-+ __be32 dbg_ctl; /* Debug control */
-+};
-+
-+/* Switch Pseudo-MAC registers */
-+struct vr9_switch_pmac_regs {
-+ __be32 hd_ctl; /* PMAC header control */
-+ __be32 tl; /* PMAC type/length */
-+ __be32 sa1; /* PMAC source address 1 */
-+ __be32 sa2; /* PMAC source address 2 */
-+ __be32 sa3; /* PMAC source address 3 */
-+ __be32 da1; /* PMAC destination address 1 */
-+ __be32 da2; /* PMAC destination address 2 */
-+ __be32 da3; /* PMAC destination address 3 */
-+ __be32 vlan; /* PMAC VLAN */
-+ __be32 rx_ipg; /* PMAC interpacket gap in RX direction */
-+ __be32 st_etype; /* PMAC special tag ethertype */
-+ __be32 ewan; /* PMAC ethernet WAN group */
-+ __be32 ctl; /* PMAC control */
-+ __be32 rsvd0[0x2];
-+};
-+
-+struct vr9_switch_regs {
-+ struct vr9_switch_core_regs core;
-+ struct vr9_switch_bm_regs bm;
-+ struct vr9_switch_pce_regs pce;
-+ struct vr9_switch_mac_regs mac;
-+ struct vr9_switch_fdma_regs fdma;
-+ struct vr9_switch_sdma_regs sdma;
-+ struct vr9_switch_mdio_regs mdio;
-+ struct vr9_switch_mii_regs mii;
-+ struct vr9_switch_pmac_regs pmac;
-+};
-+
-+#define VR9_SWITCH_REG_OFFSET(reg) (4 * (reg))
-+
-+#define BUILD_CHECK_VR9_REG(name, offset) \
-+ BUILD_BUG_ON(offsetof(struct vr9_switch_regs, name) != (4 * offset))
-+
-+static inline void build_check_vr9_registers(void)
-+{
-+ BUILD_CHECK_VR9_REG(core, 0x0);
-+ BUILD_CHECK_VR9_REG(bm.core, 0x40);
-+ BUILD_CHECK_VR9_REG(bm.core.queue_gctrl, 0x4a);
-+ BUILD_CHECK_VR9_REG(bm.port[0], 0x80);
-+ BUILD_CHECK_VR9_REG(bm.queue, 0x100);
-+ BUILD_CHECK_VR9_REG(bm.shaper, 0x140);
-+ BUILD_CHECK_VR9_REG(pce.core, 0x438);
-+ BUILD_CHECK_VR9_REG(pce.core.tbl_ctrl, 0x44f);
-+ BUILD_CHECK_VR9_REG(pce.core.parser_stat, 0x469);
-+ BUILD_CHECK_VR9_REG(pce.port[0], 0x480);
-+ BUILD_CHECK_VR9_REG(pce.meter[0], 0x580);
-+ BUILD_CHECK_VR9_REG(mac.core, 0x8c0);
-+ BUILD_CHECK_VR9_REG(mac.port[0].pstat, 0x900);
-+ BUILD_CHECK_VR9_REG(mac.port[0].ctrl_0, 0x903);
-+ BUILD_CHECK_VR9_REG(mac.port[1].pstat, 0x90c);
-+ BUILD_CHECK_VR9_REG(mac.port[1].ctrl_0, 0x90f);
-+ BUILD_CHECK_VR9_REG(mac.port[2].pstat, 0x918);
-+ BUILD_CHECK_VR9_REG(mac.port[2].ctrl_0, 0x91b);
-+ BUILD_CHECK_VR9_REG(fdma.core, 0xa40);
-+ BUILD_CHECK_VR9_REG(fdma.port[0], 0xa80);
-+ BUILD_CHECK_VR9_REG(sdma.core, 0xb40);
-+ BUILD_CHECK_VR9_REG(sdma.port[0], 0xbc0);
-+ BUILD_CHECK_VR9_REG(mdio, 0xc40);
-+ BUILD_CHECK_VR9_REG(mii, (0xc40 + 0x36));
-+ BUILD_CHECK_VR9_REG(pmac, (0xc40 + 0x82));
-+}
-+
-+#define MAC_CTRL0_BM BIT(12)
-+#define MAC_CTRL0_APADEN BIT(11)
-+#define MAC_CTRL0_VPAD2EN BIT(10)
-+#define MAC_CTRL0_VPADEN BIT(9)
-+#define MAC_CTRL0_PADEN BIT(8)
-+#define MAC_CTRL0_FCS BIT(7)
-+#define MAC_CTRL0_FCON_SHIFT 4
-+#define MAC_CTRL0_FCON_AUTO (0x0 << MAC_CTRL0_FCON_SHIFT)
-+#define MAC_CTRL0_FCON_RX (0x1 << MAC_CTRL0_FCON_SHIFT)
-+#define MAC_CTRL0_FCON_TX (0x2 << MAC_CTRL0_FCON_SHIFT)
-+#define MAC_CTRL0_FCON_RXTX (0x3 << MAC_CTRL0_FCON_SHIFT)
-+#define MAC_CTRL0_FCON_NONE (0x4 << MAC_CTRL0_FCON_SHIFT)
-+#define MAC_CTRL0_FDUP_SHIFT 2
-+#define MAC_CTRL0_FDUP_AUTO (0x0 << MAC_CTRL0_FDUP_SHIFT)
-+#define MAC_CTRL0_FDUP_EN (0x1 << MAC_CTRL0_FDUP_SHIFT)
-+#define MAC_CTRL0_FDUP_DIS (0x3 << MAC_CTRL0_FDUP_SHIFT)
-+#define MAC_CTRL0_GMII_AUTO 0x0
-+#define MAC_CTRL0_GMII_MII 0x1
-+#define MAC_CTRL0_GMII_GMII 0x2
-+#define MAC_CTRL0_GMII_GMII_2G 0x3
-+
-+#define MAC_CTRL1_DEFERMODE BIT(15)
-+#define MAC_CTRL1_SHORTPRE BIT(8)
-+
-+#define MAC_CTRL2_MLEN BIT(3)
-+#define MAC_CTRL2_LCHKL BIT(2)
-+#define MAC_CTRL2_LCHKS_DIS 0x0
-+#define MAC_CTRL2_LCHKS_UNTAG 0x1
-+#define MAC_CTRL2_LCHKS_TAG 0x2
-+
-+#define PHY_ADDR_LNKST_SHIFT 13
-+#define PHY_ADDR_LNKST_AUTO (0x0 << PHY_ADDR_LNKST_SHIFT)
-+#define PHY_ADDR_LNKST_UP (0x1 << PHY_ADDR_LNKST_SHIFT)
-+#define PHY_ADDR_LNKST_DOWN (0x2 << PHY_ADDR_LNKST_SHIFT)
-+#define PHY_ADDR_SPEED_SHIFT 11
-+#define PHY_ADDR_SPEED_M10 (0x0 << PHY_ADDR_SPEED_SHIFT)
-+#define PHY_ADDR_SPEED_M100 (0x1 << PHY_ADDR_SPEED_SHIFT)
-+#define PHY_ADDR_SPEED_G1 (0x2 << PHY_ADDR_SPEED_SHIFT)
-+#define PHY_ADDR_SPEED_AUTO (0x3 << PHY_ADDR_SPEED_SHIFT)
-+#define PHY_ADDR_FDUP_SHIFT 9
-+#define PHY_ADDR_FDUP_AUTO (0x0 << PHY_ADDR_FDUP_SHIFT)
-+#define PHY_ADDR_FDUP_EN (0x1 << PHY_ADDR_FDUP_SHIFT)
-+#define PHY_ADDR_FDUP_DIS (0x3 << PHY_ADDR_FDUP_SHIFT)
-+#define PHY_ADDR_FCONTX_SHIFT 7
-+#define PHY_ADDR_FCONTX_AUTO (0x0 << PHY_ADDR_FCONTX_SHIFT)
-+#define PHY_ADDR_FCONTX_EN (0x1 << PHY_ADDR_FCONTX_SHIFT)
-+#define PHY_ADDR_FCONTX_DIS (0x3 << PHY_ADDR_FCONTX_SHIFT)
-+#define PHY_ADDR_FCONRX_SHIFT 5
-+#define PHY_ADDR_FCONRX_AUTO (0x0 << PHY_ADDR_FCONRX_SHIFT)
-+#define PHY_ADDR_FCONRX_EN (0x1 << PHY_ADDR_FCONRX_SHIFT)
-+#define PHY_ADDR_FCONRX_DIS (0x3 << PHY_ADDR_FCONRX_SHIFT)
-+
-+#define MII_CFG_RES BIT(15)
-+#define MII_CFG_EN BIT(14)
-+#define MII_CFG_LDCLKDIS BIT(12)
-+#define MII_CFG_MIIRATE_SHIFT 4
-+#define MII_CFG_MIIRATE_MASK (0x7 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIRATE_M2P5 (0x0 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIRATE_M25 (0x1 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIRATE_M125 (0x2 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIRATE_M50 (0x3 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIRATE_AUTO (0x4 << MII_CFG_MIIRATE_SHIFT)
-+#define MII_CFG_MIIMODE_MASK 0xf
-+#define MII_CFG_MIIMODE_MIIP 0x0
-+#define MII_CFG_MIIMODE_MIIM 0x1
-+#define MII_CFG_MIIMODE_RMIIP 0x2
-+#define MII_CFG_MIIMODE_RMIIM 0x3
-+#define MII_CFG_MIIMODE_RGMII 0x4
-+
-+#define PMAC_HD_CTL_FC BIT(10)
-+#define PMAC_HD_CTL_RST BIT(8)
-+#define PMAC_HD_CTL_AST BIT(7)
-+#define PMAC_HD_CTL_RXSH BIT(6)
-+#define PMAC_HD_CTL_RC BIT(4)
-+#define PMAC_HD_CTL_AS BIT(3)
-+#define PMAC_HD_CTL_AC BIT(2)
-+
-+#define PCE_PCTRL_0_IGSTEN BIT(11)
-+
-+#define FDMA_PCTRL_STEN BIT(1)
-+#define FDMA_PCTRL_EN BIT(0)
-+
-+#define SDMA_PCTRL_EN BIT(0)
-+
-+#define MDIO_CTRL_MBUSY BIT(12)
-+#define MDIO_CTRL_OP_READ BIT(11)
-+#define MDIO_CTRL_OP_WRITE BIT(10)
-+#define MDIO_CTRL_PHYAD_SHIFT 5
-+#define MDIO_CTRL_PHYAD_MASK (0x1f << MDIO_CTRL_PHYAD_SHIFT)
-+#define MDIO_CTRL_REGAD_MASK 0x1f
-+
-+#endif /* __VR9_SWITCH_REGS_H__ */
-diff --git a/arch/mips/lantiq/xway/xway_phy_fw.c b/arch/mips/lantiq/xway/xway_phy_fw.c
-new file mode 100644
-index 0000000..97a6d22
---- /dev/null
-+++ b/arch/mips/lantiq/xway/xway_phy_fw.c
-@@ -0,0 +1,146 @@
-+#include <linux/kernel.h>
-+#include <linux/slab.h>
-+#include <linux/errno.h>
-+#include <linux/types.h>
-+#include <linux/interrupt.h>
-+#include <linux/uaccess.h>
-+#include <linux/in.h>
-+#include <linux/netdevice.h>
-+#include <linux/etherdevice.h>
-+#include <linux/phy.h>
-+#include <linux/ip.h>
-+#include <linux/tcp.h>
-+#include <linux/skbuff.h>
-+#include <linux/mm.h>
-+#include <linux/ethtool.h>
-+#include <linux/init.h>
-+#include <linux/delay.h>
-+#include <linux/io.h>
-+#include <linux/dma-mapping.h>
-+#include <linux/module.h>
-+#include <linux/firmware.h>
-+#include <linux/ihex.h>
-+#include <linux/of_platform.h>
-+#include <linux/of_net.h>
-+#include <linux/of_address.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_gpio.h>
-+
-+#include <asm/checksum.h>
-+
-+#include <lantiq_soc.h>
-+
-+#include "vr9_switch_regs.h"
-+
-+#define XWAY_GPHY_FW_ALIGN (16 * 1024)
-+#define XWAY_GPHY_FW_NAME_SIZE 32
-+
-+struct xway_gphy_core {
-+ struct device *dev;
-+ char fw_name[XWAY_GPHY_FW_NAME_SIZE];
-+ dma_addr_t dev_addr;
-+ void *fw_addr;
-+ size_t fw_size;
-+};
-+
-+static int xway_gphy_load(struct platform_device *pdev, struct xway_gphy_core *gphy)
-+{
-+ const struct firmware *fw;
-+ dma_addr_t dev_addr;
-+ void *fw_addr;
-+ int err;
-+ size_t size;
-+ const char *fw_name;
-+
-+ err = of_property_read_string(pdev->dev.of_node, "firmware", &fw_name);
-+ if (err) {
-+ dev_err(&pdev->dev, "failed to load firmware filename\n");
-+ return err;
-+ }
-+
-+ if (strlen(fw_name) >= sizeof(gphy->fw_name)) {
-+ dev_err(&pdev->dev, "firmware filename too long\n");
-+ return ENAMETOOLONG;
-+ }
-+
-+ strncpy(gphy->fw_name, fw_name, sizeof(gphy->fw_name));
-+
-+ dev_info(&pdev->dev, "requesting %s\n", gphy->fw_name);
-+ err = request_firmware(&fw, gphy->fw_name, &pdev->dev);
-+ if (err) {
-+ dev_err(&pdev->dev, "failed to load firmware: %s\n", gphy->fw_name);
-+ return err;
-+ }
-+
-+ /*
-+ * GPHY cores need the firmware code in a persistent and contiguous
-+ * memory area with a 16 kB boundary aligned start address
-+ */
-+ size = fw->size + XWAY_GPHY_FW_ALIGN;
-+ fw_addr = dma_alloc_coherent(&pdev->dev, size, &dev_addr, GFP_KERNEL);
-+ if (!fw_addr) {
-+ dev_err(&pdev->dev, "failed to alloc firmware memory\n");
-+ goto err_release;
-+ }
-+
-+ fw_addr = PTR_ALIGN(fw_addr, XWAY_GPHY_FW_ALIGN);
-+ dev_addr = ALIGN(dev_addr, XWAY_GPHY_FW_ALIGN);
-+
-+ memcpy(fw_addr, fw->data, fw->size);
-+ release_firmware(fw);
-+
-+ gphy->dev = &pdev->dev;
-+ gphy->dev_addr = dev_addr;
-+ gphy->fw_addr = fw_addr;
-+ gphy->fw_size = size;
-+
-+ return 0;
-+
-+err_release:
-+ release_firmware(fw);
-+
-+ return err;
-+}
-+
-+static int __devinit xway_phy_fw_probe(struct platform_device *pdev)
-+{
-+ struct xway_gphy_core gphy;
-+ struct property *pp;
-+ unsigned char *phyids;
-+ int i, ret;
-+
-+ ret = xway_gphy_load(pdev, &gphy);
-+ if (ret)
-+ return ret;
-+ pp = of_find_property(pdev->dev.of_node, "phys", NULL);
-+ if (!pp)
-+ return -ENOENT;
-+ phyids = pp->value;
-+ for (i = 0; i < pp->length && !ret; i++)
-+ ret = xrx200_gphy_boot(&pdev->dev, phyids[i], gphy.dev_addr);
-+ if (!ret)
-+ mdelay(100);
-+ return ret;
-+}
-+
-+static const struct of_device_id xway_phy_match[] = {
-+ { .compatible = "lantiq,phy-xrx200" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, xway_phy_match);
-+
-+static struct platform_driver xway_phy_driver = {
-+ .probe = xway_phy_fw_probe,
-+ .driver = {
-+ .name = "phy-xrx200",
-+ .owner = THIS_MODULE,
-+ .of_match_table = xway_phy_match,
-+ },
-+};
-+
-+module_platform_driver(xway_phy_driver);
-+
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_DESCRIPTION("Lantiq XRX200 PHY Firmware Loader");
-+MODULE_LICENSE("GPL");
-+
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0107-MIPS-lantiq-add-xrx200-ethernet-clock.patch b/target/linux/lantiq/patches-3.6/0107-MIPS-lantiq-add-xrx200-ethernet-clock.patch
deleted file mode 100644
index e941ee3db6..0000000000
--- a/target/linux/lantiq/patches-3.6/0107-MIPS-lantiq-add-xrx200-ethernet-clock.patch
+++ /dev/null
@@ -1,28 +0,0 @@
-From 00b0721cce51988b6dda27b21afb0e09c620bc21 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Sat, 27 Oct 2012 09:14:17 +0200
-Subject: [PATCH 107/113] MIPS: lantiq: add xrx200 ethernet clock
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- arch/mips/lantiq/xway/sysctrl.c | 4 ++++
- 1 file changed, 4 insertions(+)
-
-diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c
-index 2917b56..3925e66 100644
---- a/arch/mips/lantiq/xway/sysctrl.c
-+++ b/arch/mips/lantiq/xway/sysctrl.c
-@@ -370,6 +370,10 @@ void __init ltq_soc_init(void)
- clkdev_add_pmu("1d900000.pcie", "pdi", 1, PMU1_PCIE_PDI);
- clkdev_add_pmu("1d900000.pcie", "ctl", 1, PMU1_PCIE_CTL);
- clkdev_add_pmu("1d900000.pcie", "ahb", 0, PMU_AHBM | PMU_AHBS);
-+ clkdev_add_pmu("1e108000.eth", NULL, 0,
-+ PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM |
-+ PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 |
-+ PMU_PPE_QSB | PMU_PPE_TOP);
- } else if (of_machine_is_compatible("lantiq,ar9")) {
- clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(),
- ltq_ar9_fpi_hz());
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0108-firmware-lantiq-adds-PHY11G-firmware-blobs.patch b/target/linux/lantiq/patches-3.6/0108-firmware-lantiq-adds-PHY11G-firmware-blobs.patch
deleted file mode 100644
index 4ba49e4463..0000000000
--- a/target/linux/lantiq/patches-3.6/0108-firmware-lantiq-adds-PHY11G-firmware-blobs.patch
+++ /dev/null
@@ -1,2221 +0,0 @@
-From 817acb2b92075a3c1e6aed7972c32710cf3a10c3 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 09:26:24 +0200
-Subject: [PATCH 108/113] firmware: lantiq: adds PHY11G firmware blobs
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- firmware/Makefile | 1 +
- firmware/lantiq/COPYING | 286 ++++++++++++++++++++++++++++++++++++
- firmware/lantiq/README | 45 ++++++
- firmware/lantiq/vr9_phy11g_a1x.bin | Bin 0 -> 65536 bytes
- firmware/lantiq/vr9_phy11g_a2x.bin | Bin 0 -> 65536 bytes
- firmware/lantiq/vr9_phy22f_a1x.bin | Bin 0 -> 65536 bytes
- firmware/lantiq/vr9_phy22f_a2x.bin | Bin 0 -> 65536 bytes
- 7 files changed, 332 insertions(+)
- create mode 100644 firmware/lantiq/COPYING
- create mode 100644 firmware/lantiq/README
- create mode 100644 firmware/lantiq/vr9_phy11g_a1x.bin
- create mode 100644 firmware/lantiq/vr9_phy11g_a2x.bin
- create mode 100644 firmware/lantiq/vr9_phy22f_a1x.bin
- create mode 100644 firmware/lantiq/vr9_phy22f_a2x.bin
-
-diff --git a/firmware/Makefile b/firmware/Makefile
-index eeb1403..4259bed 100644
---- a/firmware/Makefile
-+++ b/firmware/Makefile
-@@ -135,6 +135,7 @@ fw-shipped-$(CONFIG_USB_SERIAL_KEYSPAN_PDA) += keyspan_pda/keyspan_pda.fw
- fw-shipped-$(CONFIG_USB_SERIAL_XIRCOM) += keyspan_pda/xircom_pgs.fw
- fw-shipped-$(CONFIG_USB_VICAM) += vicam/firmware.fw
- fw-shipped-$(CONFIG_VIDEO_CPIA2) += cpia2/stv0672_vp4.bin
-+fw-shipped-$(CONFIG_SOC_TYPE_XWAY) += lantiq/vr9_phy11g_a2x.bin
- fw-shipped-$(CONFIG_YAM) += yam/1200.bin yam/9600.bin
-
- fw-shipped-all := $(fw-shipped-y) $(fw-shipped-m) $(fw-shipped-)
-diff --git a/firmware/lantiq/COPYING b/firmware/lantiq/COPYING
-new file mode 100644
-index 0000000..5ec70b2
---- /dev/null
-+++ b/firmware/lantiq/COPYING
-@@ -0,0 +1,286 @@
-+All firmware files are copyrighted by Lantiq Deutschland GmbH.
-+The files have been extracted from header files found in Lantiq BSPs.
-+If not stated otherwise all files are licensed under GPL.
-+
-+=======================================================================
-+
-+ GNU GENERAL PUBLIC LICENSE
-+ Version 2, June 1991
-+
-+ Copyright (C) 1989, 1991 Free Software Foundation, Inc.
-+ 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
-+ Everyone is permitted to copy and distribute verbatim copies
-+ of this license document, but changing it is not allowed.
-+
-+ Preamble
-+
-+ The licenses for most software are designed to take away your
-+freedom to share and change it. By contrast, the GNU General Public
-+License is intended to guarantee your freedom to share and change free
-+software--to make sure the software is free for all its users. This
-+General Public License applies to most of the Free Software
-+Foundation's software and to any other program whose authors commit to
-+using it. (Some other Free Software Foundation software is covered by
-+the GNU Library General Public License instead.) You can apply it to
-+your programs, too.
-+
-+ When we speak of free software, we are referring to freedom, not
-+price. Our General Public Licenses are designed to make sure that you
-+have the freedom to distribute copies of free software (and charge for
-+this service if you wish), that you receive source code or can get it
-+if you want it, that you can change the software or use pieces of it
-+in new free programs; and that you know you can do these things.
-+
-+ To protect your rights, we need to make restrictions that forbid
-+anyone to deny you these rights or to ask you to surrender the rights.
-+These restrictions translate to certain responsibilities for you if you
-+distribute copies of the software, or if you modify it.
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-+ END OF TERMS AND CONDITIONS
-diff --git a/firmware/lantiq/README b/firmware/lantiq/README
-new file mode 100644
-index 0000000..cb1a10a
---- /dev/null
-+++ b/firmware/lantiq/README
-@@ -0,0 +1,45 @@
-+#
-+# This program is free software; you can redistribute it and/or
-+# modify it under the terms of the GNU General Public License as
-+# published by the Free Software Foundation; either version 2 of
-+# the License, or (at your option) any later version.
-+#
-+# This program is distributed in the hope that it will be useful,
-+# but WITHOUT ANY WARRANTY; without even the implied warranty of
-+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+# GNU General Public License for more details.
-+#
-+# You should have received a copy of the GNU General Public License
-+# along with this program; if not, write to the Free Software
-+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-+# MA 02111-1307 USA
-+#
-+# (C) Copyright 2007 - 2012
-+# Lantiq Deutschland GmbH
-+#
-+# (C) Copyright 2012
-+# Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-+#
-+
-+#
-+# How to use
-+#
-+Configure kernel with:
-+CONFIG_FW_LOADER=y
-+CONFIG_EXTRA_FIRMWARE_DIR="FIRMWARE_DIR"
-+CONFIG_EXTRA_FIRMWARE="FIRMWARE_FILES"
-+
-+where FIRMWARE_DIR should point to this git tree and FIRMWARE_FILES is a list
-+of space separated files from list below.
-+
-+#
-+# Firmware files
-+#
-+
-+# GPHY core on Lantiq XWAY VR9 v1.1
-+lantiq/vr9_phy11g_a1x.bin
-+lantiq/vr9_phy22f_a1x.bin
-+
-+# GPHY core on Lantiq XWAY VR9 v1.1
-+lantiq/vr9_phy11g_a2x.bin
-+lantiq/vr9_phy22f_a2x.bin
-diff --git a/firmware/lantiq/vr9_phy11g_a1x.bin b/firmware/lantiq/vr9_phy11g_a1x.bin
-new file mode 100644
-index 0000000000000000000000000000000000000000..cdf3d3063405c1239d15bae873e11f4ad8644e0f
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-
-literal 0
-HcmV?d00001
-
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0109-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch b/target/linux/lantiq/patches-3.6/0109-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch
deleted file mode 100644
index 0b2ce06e69..0000000000
--- a/target/linux/lantiq/patches-3.6/0109-MTD-lantiq-xway-fix-NAND-reset-timeout-handling.patch
+++ /dev/null
@@ -1,47 +0,0 @@
-From 5967e3171d56b7c433587aa418b87ae7fea02f28 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 10:25:39 +0200
-Subject: [PATCH 109/113] MTD: lantiq: xway: fix NAND reset timeout handling
-
-Fixes a possible deadlock in the code that resets the NAND flash.
-
-http://lists.infradead.org/pipermail/linux-mtd/2012-September/044240.html
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/mtd/nand/xway_nand.c | 12 ++++++++++--
- 1 file changed, 10 insertions(+), 2 deletions(-)
-
-diff --git a/drivers/mtd/nand/xway_nand.c b/drivers/mtd/nand/xway_nand.c
-index 3f81dc8..4731300 100644
---- a/drivers/mtd/nand/xway_nand.c
-+++ b/drivers/mtd/nand/xway_nand.c
-@@ -58,15 +58,23 @@ static void xway_reset_chip(struct nand_chip *chip)
- {
- unsigned long nandaddr = (unsigned long) chip->IO_ADDR_W;
- unsigned long flags;
-+ unsigned long timeout;
-
- nandaddr &= ~NAND_WRITE_ADDR;
- nandaddr |= NAND_WRITE_CMD;
-
- /* finish with a reset */
-+ timeout = jiffies + msecs_to_jiffies(200);
-+
- spin_lock_irqsave(&ebu_lock, flags);
-+
- writeb(NAND_WRITE_CMD_RESET, (void __iomem *) nandaddr);
-- while ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
-- ;
-+ do {
-+ if ((ltq_ebu_r32(EBU_NAND_WAIT) & NAND_WAIT_WR_C) == 0)
-+ break;
-+ cond_resched();
-+ } while (!time_after_eq(jiffies, timeout));
-+
- spin_unlock_irqrestore(&ebu_lock, flags);
- }
-
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0110-NET-PHY-adds-driver-for-lantiq-PHY11G.patch b/target/linux/lantiq/patches-3.6/0110-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
deleted file mode 100644
index f3a31cd348..0000000000
--- a/target/linux/lantiq/patches-3.6/0110-NET-PHY-adds-driver-for-lantiq-PHY11G.patch
+++ /dev/null
@@ -1,228 +0,0 @@
-From 2fa550e1ca132377ee4910eaaf331a257190b75e Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 09:28:30 +0200
-Subject: [PATCH 110/113] NET: PHY: adds driver for lantiq PHY11G
-
-Signed-off-by: John Crispin <blogic@openwrt.org>
----
- drivers/net/phy/Kconfig | 5 ++
- drivers/net/phy/Makefile | 1 +
- drivers/net/phy/lantiq.c | 178 ++++++++++++++++++++++++++++++++++++++++++++++
- 3 files changed, 184 insertions(+)
- create mode 100644 drivers/net/phy/lantiq.c
-
-diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
-index 983bbf4..a7ff1d2 100644
---- a/drivers/net/phy/Kconfig
-+++ b/drivers/net/phy/Kconfig
-@@ -102,6 +102,11 @@ config MICREL_PHY
- ---help---
- Supports the KSZ9021, VSC8201, KS8001 PHYs.
-
-+config LANTIQ_PHY
-+ tristate "Driver for Lantiq PHYs"
-+ ---help---
-+ Supports the 11G and 22E PHYs.
-+
- config FIXED_PHY
- bool "Driver for MDIO Bus/PHY emulation with fixed speed/link PHYs"
- depends on PHYLIB=y
-diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
-index 426674d..3aa92bf 100644
---- a/drivers/net/phy/Makefile
-+++ b/drivers/net/phy/Makefile
-@@ -23,6 +23,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o
- obj-$(CONFIG_DP83640_PHY) += dp83640.o
- obj-$(CONFIG_STE10XP) += ste10Xp.o
- obj-$(CONFIG_MICREL_PHY) += micrel.o
-+obj-$(CONFIG_LANTIQ_PHY) += lantiq.o
- obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o
- obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o
- obj-$(CONFIG_AMD_PHY) += amd.o
-diff --git a/drivers/net/phy/lantiq.c b/drivers/net/phy/lantiq.c
-new file mode 100644
-index 0000000..ba4d7b7
---- /dev/null
-+++ b/drivers/net/phy/lantiq.c
-@@ -0,0 +1,178 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify
-+ * it under the terms of the GNU General Public License as published by
-+ * the Free Software Foundation; either version 2 of the License, or
-+ * (at your option) any later version.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2012 Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
-+ */
-+
-+#include <linux/module.h>
-+#include <linux/phy.h>
-+
-+#define MII_MMDCTRL 0x0d
-+#define MII_MMDDATA 0x0e
-+
-+#define MII_VR9_11G_IMASK 0x19 /* interrupt mask */
-+#define MII_VR9_11G_ISTAT 0x1a /* interrupt status */
-+
-+#define INT_VR9_11G_WOL BIT(15) /* Wake-On-LAN */
-+#define INT_VR9_11G_ANE BIT(11) /* Auto-Neg error */
-+#define INT_VR9_11G_ANC BIT(10) /* Auto-Neg complete */
-+#define INT_VR9_11G_ADSC BIT(5) /* Link auto-downspeed detect */
-+#define INT_VR9_11G_DXMC BIT(2) /* Duplex mode change */
-+#define INT_VR9_11G_LSPC BIT(1) /* Link speed change */
-+#define INT_VR9_11G_LSTC BIT(0) /* Link state change */
-+#define INT_VR9_11G_MASK (INT_VR9_11G_LSTC | INT_VR9_11G_ADSC)
-+
-+#define ADVERTISED_MPD BIT(10) /* Multi-port device */
-+
-+#define MMD_DEVAD 0x1f
-+#define MMD_ACTYPE_SHIFT 14
-+#define MMD_ACTYPE_ADDRESS (0 << MMD_ACTYPE_SHIFT)
-+#define MMD_ACTYPE_DATA (1 << MMD_ACTYPE_SHIFT)
-+#define MMD_ACTYPE_DATA_PI (2 << MMD_ACTYPE_SHIFT)
-+#define MMD_ACTYPE_DATA_PIWR (3 << MMD_ACTYPE_SHIFT)
-+
-+static __maybe_unused int vr9_gphy_mmd_read(struct phy_device *phydev,
-+ u16 regnum)
-+{
-+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
-+ phy_write(phydev, MII_MMDDATA, regnum);
-+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
-+
-+ return phy_read(phydev, MII_MMDDATA);
-+}
-+
-+static __maybe_unused int vr9_gphy_mmd_write(struct phy_device *phydev,
-+ u16 regnum, u16 val)
-+{
-+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_ADDRESS | MMD_DEVAD);
-+ phy_write(phydev, MII_MMDDATA, regnum);
-+ phy_write(phydev, MII_MMDCTRL, MMD_ACTYPE_DATA | MMD_DEVAD);
-+ phy_write(phydev, MII_MMDDATA, val);
-+
-+ return 0;
-+}
-+
-+static int vr9_gphy_config_init(struct phy_device *phydev)
-+{
-+ int err;
-+
-+ dev_dbg(&phydev->dev, "%s\n", __func__);
-+
-+ /* Mask all interrupts */
-+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
-+ if (err)
-+ return err;
-+
-+ /* Clear all pending interrupts */
-+ phy_read(phydev, MII_VR9_11G_ISTAT);
-+
-+ return 0;
-+}
-+
-+static int vr9_gphy_config_aneg(struct phy_device *phydev)
-+{
-+ int reg, err;
-+
-+ /* Advertise as multi-port device */
-+ reg = phy_read(phydev, MII_CTRL1000);
-+ reg |= ADVERTISED_MPD;
-+ err = phy_write(phydev, MII_CTRL1000, reg);
-+ if (err)
-+ return err;
-+
-+ return genphy_config_aneg(phydev);
-+}
-+
-+static int vr9_gphy_ack_interrupt(struct phy_device *phydev)
-+{
-+ int reg;
-+
-+ /*
-+ * Possible IRQ numbers:
-+ * - IM3_IRL18 for GPHY0
-+ * - IM3_IRL17 for GPHY1
-+ *
-+ * Due to a silicon bug IRQ lines are not really independent from
-+ * each other. Sometimes the two lines are driven at the same time
-+ * if only one GPHY core raises the interrupt.
-+ */
-+
-+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
-+
-+ return (reg < 0) ? reg : 0;
-+}
-+
-+static int vr9_gphy_did_interrupt(struct phy_device *phydev)
-+{
-+ int reg;
-+
-+ reg = phy_read(phydev, MII_VR9_11G_ISTAT);
-+
-+ return reg > 0;
-+}
-+
-+static int vr9_gphy_config_intr(struct phy_device *phydev)
-+{
-+ int err;
-+
-+ if (phydev->interrupts == PHY_INTERRUPT_ENABLED)
-+ err = phy_write(phydev, MII_VR9_11G_IMASK, INT_VR9_11G_MASK);
-+ else
-+ err = phy_write(phydev, MII_VR9_11G_IMASK, 0);
-+
-+ return err;
-+}
-+
-+/* TODO: add vr9_gphy_22f_driver and drivers for external Lantiq PEF7071 PHYs */
-+static struct phy_driver vr9_gphy_11g_driver = {
-+ .phy_id = 0xd565a408,
-+ .phy_id_mask = 0xfffffff0,
-+ .name = "Lantiq XWAY VR9 GPHY 11G",
-+ .features = (PHY_GBIT_FEATURES | SUPPORTED_Pause),
-+ .flags = 0, /*PHY_HAS_INTERRUPT,*/
-+ .config_init = vr9_gphy_config_init,
-+ .config_aneg = vr9_gphy_config_aneg,
-+ .read_status = genphy_read_status,
-+ .ack_interrupt = vr9_gphy_ack_interrupt,
-+ .did_interrupt = vr9_gphy_did_interrupt,
-+ .config_intr = vr9_gphy_config_intr,
-+ .driver = { .owner = THIS_MODULE },
-+};
-+
-+static int __init ltq_phy_init(void)
-+{
-+ int err;
-+
-+ err = phy_driver_register(&vr9_gphy_11g_driver);
-+ if (err)
-+ goto err_out;
-+
-+ return 0;
-+
-+err_out:
-+ return err;
-+}
-+
-+static void __exit ltq_phy_exit(void)
-+{
-+ phy_driver_unregister(&vr9_gphy_11g_driver);
-+}
-+
-+module_init(ltq_phy_init);
-+module_exit(ltq_phy_exit);
-+
-+MODULE_DESCRIPTION("Lantiq PHY drivers");
-+MODULE_AUTHOR("Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>");
-+MODULE_LICENSE("GPL");
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0111-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch b/target/linux/lantiq/patches-3.6/0111-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
deleted file mode 100644
index ff857ac51a..0000000000
--- a/target/linux/lantiq/patches-3.6/0111-NET-MIPS-lantiq-update-etop-driver-for-devicetree.patch
+++ /dev/null
@@ -1,807 +0,0 @@
-From 6db31b14d4998f480349dd5f1ef83dc68a1fab0c Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Wed, 24 Oct 2012 19:50:30 +0200
-Subject: [PATCH 111/113] NET: MIPS: lantiq: update etop driver for devicetree
-
----
- drivers/net/ethernet/lantiq_etop.c | 470 +++++++++++++++++++++++++-----------
- 1 file changed, 333 insertions(+), 137 deletions(-)
-
-diff --git a/drivers/net/ethernet/lantiq_etop.c b/drivers/net/ethernet/lantiq_etop.c
-index 003c5bc..dc5457a 100644
---- a/drivers/net/ethernet/lantiq_etop.c
-+++ b/drivers/net/ethernet/lantiq_etop.c
-@@ -12,7 +12,7 @@
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
- *
-- * Copyright (C) 2011 John Crispin <blogic@openwrt.org>
-+ * Copyright (C) 2011-12 John Crispin <blogic@openwrt.org>
- */
-
- #include <linux/kernel.h>
-@@ -36,6 +36,10 @@
- #include <linux/io.h>
- #include <linux/dma-mapping.h>
- #include <linux/module.h>
-+#include <linux/clk.h>
-+#include <linux/of_net.h>
-+#include <linux/of_irq.h>
-+#include <linux/of_platform.h>
-
- #include <asm/checksum.h>
-
-@@ -71,25 +75,56 @@
- #define ETOP_MII_REVERSE 0xe
- #define ETOP_PLEN_UNDER 0x40
- #define ETOP_CGEN 0x800
--
--/* use 2 static channels for TX/RX */
--#define LTQ_ETOP_TX_CHANNEL 1
--#define LTQ_ETOP_RX_CHANNEL 6
--#define IS_TX(x) (x == LTQ_ETOP_TX_CHANNEL)
--#define IS_RX(x) (x == LTQ_ETOP_RX_CHANNEL)
--
-+#define ETOP_CFG_MII0 0x01
-+
-+#define LTQ_GBIT_MDIO_CTL 0xCC
-+#define LTQ_GBIT_MDIO_DATA 0xd0
-+#define LTQ_GBIT_GCTL0 0x68
-+#define LTQ_GBIT_PMAC_HD_CTL 0x8c
-+#define LTQ_GBIT_P0_CTL 0x4
-+#define LTQ_GBIT_PMAC_RX_IPG 0xa8
-+
-+#define PMAC_HD_CTL_AS (1 << 19)
-+#define PMAC_HD_CTL_RXSH (1 << 22)
-+
-+/* Switch Enable (0=disable, 1=enable) */
-+#define GCTL0_SE 0x80000000
-+/* Disable MDIO auto polling (0=disable, 1=enable) */
-+#define PX_CTL_DMDIO 0x00400000
-+
-+/* register information for the gbit's MDIO bus */
-+#define MDIO_XR9_REQUEST 0x00008000
-+#define MDIO_XR9_READ 0x00000800
-+#define MDIO_XR9_WRITE 0x00000400
-+#define MDIO_XR9_REG_MASK 0x1f
-+#define MDIO_XR9_ADDR_MASK 0x1f
-+#define MDIO_XR9_RD_MASK 0xffff
-+#define MDIO_XR9_REG_OFFSET 0
-+#define MDIO_XR9_ADDR_OFFSET 5
-+#define MDIO_XR9_WR_OFFSET 16
-+
-+#define LTQ_DMA_ETOP ((of_machine_is_compatible("lantiq,ase")) ? \
-+ (INT_NUM_IM3_IRL0) : (INT_NUM_IM2_IRL0))
-+
-+/* the newer xway socks have a embedded 3/7 port gbit multiplexer */
- #define ltq_etop_r32(x) ltq_r32(ltq_etop_membase + (x))
- #define ltq_etop_w32(x, y) ltq_w32(x, ltq_etop_membase + (y))
- #define ltq_etop_w32_mask(x, y, z) \
- ltq_w32_mask(x, y, ltq_etop_membase + (z))
-
--#define DRV_VERSION "1.0"
-+#define ltq_gbit_r32(x) ltq_r32(ltq_gbit_membase + (x))
-+#define ltq_gbit_w32(x, y) ltq_w32(x, ltq_gbit_membase + (y))
-+#define ltq_gbit_w32_mask(x, y, z) \
-+ ltq_w32_mask(x, y, ltq_gbit_membase + (z))
-+
-+#define DRV_VERSION "1.2"
-
- static void __iomem *ltq_etop_membase;
-+static void __iomem *ltq_gbit_membase;
-
- struct ltq_etop_chan {
-- int idx;
- int tx_free;
-+ int irq;
- struct net_device *netdev;
- struct napi_struct napi;
- struct ltq_dma_channel dma;
-@@ -99,22 +134,35 @@ struct ltq_etop_chan {
- struct ltq_etop_priv {
- struct net_device *netdev;
- struct platform_device *pdev;
-- struct ltq_eth_data *pldata;
- struct resource *res;
-
- struct mii_bus *mii_bus;
- struct phy_device *phydev;
-
-- struct ltq_etop_chan ch[MAX_DMA_CHAN];
-- int tx_free[MAX_DMA_CHAN >> 1];
-+ struct ltq_etop_chan txch;
-+ struct ltq_etop_chan rxch;
-+
-+ int tx_irq;
-+ int rx_irq;
-+
-+ const void *mac;
-+ int mii_mode;
-
- spinlock_t lock;
-+
-+ struct clk *clk_ppe;
-+ struct clk *clk_switch;
-+ struct clk *clk_ephy;
-+ struct clk *clk_ephycgu;
- };
-
-+static int ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr,
-+ int phy_reg, u16 phy_data);
-+
- static int
- ltq_etop_alloc_skb(struct ltq_etop_chan *ch)
- {
-- ch->skb[ch->dma.desc] = netdev_alloc_skb(ch->netdev, MAX_DMA_DATA_LEN);
-+ ch->skb[ch->dma.desc] = dev_alloc_skb(MAX_DMA_DATA_LEN);
- if (!ch->skb[ch->dma.desc])
- return -ENOMEM;
- ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
-@@ -149,8 +197,11 @@ ltq_etop_hw_receive(struct ltq_etop_chan *ch)
- spin_unlock_irqrestore(&priv->lock, flags);
-
- skb_put(skb, len);
-+ skb->dev = ch->netdev;
- skb->protocol = eth_type_trans(skb, ch->netdev);
- netif_receive_skb(skb);
-+ ch->netdev->stats.rx_packets++;
-+ ch->netdev->stats.rx_bytes += len;
- }
-
- static int
-@@ -158,8 +209,10 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
- {
- struct ltq_etop_chan *ch = container_of(napi,
- struct ltq_etop_chan, napi);
-+ struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
- int rx = 0;
- int complete = 0;
-+ unsigned long flags;
-
- while ((rx < budget) && !complete) {
- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
-@@ -173,7 +226,9 @@ ltq_etop_poll_rx(struct napi_struct *napi, int budget)
- }
- if (complete || !rx) {
- napi_complete(&ch->napi);
-+ spin_lock_irqsave(&priv->lock, flags);
- ltq_dma_ack_irq(&ch->dma);
-+ spin_unlock_irqrestore(&priv->lock, flags);
- }
- return rx;
- }
-@@ -185,12 +240,14 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
- container_of(napi, struct ltq_etop_chan, napi);
- struct ltq_etop_priv *priv = netdev_priv(ch->netdev);
- struct netdev_queue *txq =
-- netdev_get_tx_queue(ch->netdev, ch->idx >> 1);
-+ netdev_get_tx_queue(ch->netdev, ch->dma.nr >> 1);
- unsigned long flags;
-
- spin_lock_irqsave(&priv->lock, flags);
- while ((ch->dma.desc_base[ch->tx_free].ctl &
- (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
-+ ch->netdev->stats.tx_packets++;
-+ ch->netdev->stats.tx_bytes += ch->skb[ch->tx_free]->len;
- dev_kfree_skb_any(ch->skb[ch->tx_free]);
- ch->skb[ch->tx_free] = NULL;
- memset(&ch->dma.desc_base[ch->tx_free], 0,
-@@ -203,7 +260,9 @@ ltq_etop_poll_tx(struct napi_struct *napi, int budget)
- if (netif_tx_queue_stopped(txq))
- netif_tx_start_queue(txq);
- napi_complete(&ch->napi);
-+ spin_lock_irqsave(&priv->lock, flags);
- ltq_dma_ack_irq(&ch->dma);
-+ spin_unlock_irqrestore(&priv->lock, flags);
- return 1;
- }
-
-@@ -211,9 +270,10 @@ static irqreturn_t
- ltq_etop_dma_irq(int irq, void *_priv)
- {
- struct ltq_etop_priv *priv = _priv;
-- int ch = irq - LTQ_DMA_CH0_INT;
--
-- napi_schedule(&priv->ch[ch].napi);
-+ if (irq == priv->txch.dma.irq)
-+ napi_schedule(&priv->txch.napi);
-+ else
-+ napi_schedule(&priv->rxch.napi);
- return IRQ_HANDLED;
- }
-
-@@ -225,7 +285,7 @@ ltq_etop_free_channel(struct net_device *dev, struct ltq_etop_chan *ch)
- ltq_dma_free(&ch->dma);
- if (ch->dma.irq)
- free_irq(ch->dma.irq, priv);
-- if (IS_RX(ch->idx)) {
-+ if (ch == &priv->txch) {
- int desc;
- for (desc = 0; desc < LTQ_DESC_NUM; desc++)
- dev_kfree_skb_any(ch->skb[ch->dma.desc]);
-@@ -236,23 +296,55 @@ static void
- ltq_etop_hw_exit(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-- int i;
-
-- ltq_pmu_disable(PMU_PPE);
-- for (i = 0; i < MAX_DMA_CHAN; i++)
-- if (IS_TX(i) || IS_RX(i))
-- ltq_etop_free_channel(dev, &priv->ch[i]);
-+ clk_disable(priv->clk_ppe);
-+
-+ if (of_machine_is_compatible("lantiq,ar9"))
-+ clk_disable(priv->clk_switch);
-+
-+ if (of_machine_is_compatible("lantiq,ase")) {
-+ clk_disable(priv->clk_ephy);
-+ clk_disable(priv->clk_ephycgu);
-+ }
-+
-+ ltq_etop_free_channel(dev, &priv->txch);
-+ ltq_etop_free_channel(dev, &priv->rxch);
-+}
-+
-+static void
-+ltq_etop_gbit_init(struct net_device *dev)
-+{
-+ struct ltq_etop_priv *priv = netdev_priv(dev);
-+
-+ clk_enable(priv->clk_switch);
-+
-+ ltq_gbit_w32_mask(0, GCTL0_SE, LTQ_GBIT_GCTL0);
-+ /** Disable MDIO auto polling mode */
-+ ltq_gbit_w32_mask(0, PX_CTL_DMDIO, LTQ_GBIT_P0_CTL);
-+ /* set 1522 packet size */
-+ ltq_gbit_w32_mask(0x300, 0, LTQ_GBIT_GCTL0);
-+ /* disable pmac & dmac headers */
-+ ltq_gbit_w32_mask(PMAC_HD_CTL_AS | PMAC_HD_CTL_RXSH, 0,
-+ LTQ_GBIT_PMAC_HD_CTL);
-+ /* Due to traffic halt when burst length 8,
-+ replace default IPG value with 0x3B */
-+ ltq_gbit_w32(0x3B, LTQ_GBIT_PMAC_RX_IPG);
- }
-
- static int
- ltq_etop_hw_init(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-- int i;
-
-- ltq_pmu_enable(PMU_PPE);
-+ clk_enable(priv->clk_ppe);
-
-- switch (priv->pldata->mii_mode) {
-+ if (of_machine_is_compatible("lantiq,ar9")) {
-+ ltq_etop_gbit_init(dev);
-+ /* force the etops link to the gbit to MII */
-+ priv->mii_mode = PHY_INTERFACE_MODE_MII;
-+ }
-+
-+ switch (priv->mii_mode) {
- case PHY_INTERFACE_MODE_RMII:
- ltq_etop_w32_mask(ETOP_MII_MASK,
- ETOP_MII_REVERSE, LTQ_ETOP_CFG);
-@@ -264,39 +356,68 @@ ltq_etop_hw_init(struct net_device *dev)
- break;
-
- default:
-+ if (of_machine_is_compatible("lantiq,ase")) {
-+ clk_enable(priv->clk_ephy);
-+ /* disable external MII */
-+ ltq_etop_w32_mask(0, ETOP_CFG_MII0, LTQ_ETOP_CFG);
-+ /* enable clock for internal PHY */
-+ clk_enable(priv->clk_ephycgu);
-+ /* we need to write this magic to the internal phy to
-+ make it work */
-+ ltq_etop_mdio_wr(NULL, 0x8, 0x12, 0xC020);
-+ pr_info("Selected EPHY mode\n");
-+ break;
-+ }
- netdev_err(dev, "unknown mii mode %d\n",
-- priv->pldata->mii_mode);
-+ priv->mii_mode);
- return -ENOTSUPP;
- }
-
- /* enable crc generation */
- ltq_etop_w32(PPE32_CGEN, LQ_PPE32_ENET_MAC_CFG);
-
-+ return 0;
-+}
-+
-+static int
-+ltq_etop_dma_init(struct net_device *dev)
-+{
-+ struct ltq_etop_priv *priv = netdev_priv(dev);
-+ int tx = priv->tx_irq - LTQ_DMA_ETOP;
-+ int rx = priv->rx_irq - LTQ_DMA_ETOP;
-+ int err;
-+
- ltq_dma_init_port(DMA_PORT_ETOP);
-
-- for (i = 0; i < MAX_DMA_CHAN; i++) {
-- int irq = LTQ_DMA_CH0_INT + i;
-- struct ltq_etop_chan *ch = &priv->ch[i];
--
-- ch->idx = ch->dma.nr = i;
--
-- if (IS_TX(i)) {
-- ltq_dma_alloc_tx(&ch->dma);
-- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
-- "etop_tx", priv);
-- } else if (IS_RX(i)) {
-- ltq_dma_alloc_rx(&ch->dma);
-- for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
-- ch->dma.desc++)
-- if (ltq_etop_alloc_skb(ch))
-- return -ENOMEM;
-- ch->dma.desc = 0;
-- request_irq(irq, ltq_etop_dma_irq, IRQF_DISABLED,
-- "etop_rx", priv);
-+ priv->txch.dma.nr = tx;
-+ ltq_dma_alloc_tx(&priv->txch.dma);
-+ err = request_irq(priv->tx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
-+ "eth_tx", priv);
-+ if (err) {
-+ netdev_err(dev, "failed to allocate tx irq\n");
-+ goto err_out;
-+ }
-+ priv->txch.dma.irq = priv->tx_irq;
-+
-+ priv->rxch.dma.nr = rx;
-+ ltq_dma_alloc_rx(&priv->rxch.dma);
-+ for (priv->rxch.dma.desc = 0; priv->rxch.dma.desc < LTQ_DESC_NUM;
-+ priv->rxch.dma.desc++) {
-+ if (ltq_etop_alloc_skb(&priv->rxch)) {
-+ netdev_err(dev, "failed to allocate skbs\n");
-+ err = -ENOMEM;
-+ goto err_out;
- }
-- ch->dma.irq = irq;
- }
-- return 0;
-+ priv->rxch.dma.desc = 0;
-+ err = request_irq(priv->rx_irq, ltq_etop_dma_irq, IRQF_DISABLED,
-+ "eth_rx", priv);
-+ if (err)
-+ netdev_err(dev, "failed to allocate rx irq\n");
-+ else
-+ priv->rxch.dma.irq = priv->rx_irq;
-+err_out:
-+ return err;
- }
-
- static void
-@@ -312,7 +433,10 @@ ltq_etop_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-
-- return phy_ethtool_gset(priv->phydev, cmd);
-+ if (priv->phydev)
-+ return phy_ethtool_gset(priv->phydev, cmd);
-+ else
-+ return 0;
- }
-
- static int
-@@ -320,7 +444,10 @@ ltq_etop_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-
-- return phy_ethtool_sset(priv->phydev, cmd);
-+ if (priv->phydev)
-+ return phy_ethtool_sset(priv->phydev, cmd);
-+ else
-+ return 0;
- }
-
- static int
-@@ -328,7 +455,10 @@ ltq_etop_nway_reset(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-
-- return phy_start_aneg(priv->phydev);
-+ if (priv->phydev)
-+ return phy_start_aneg(priv->phydev);
-+ else
-+ return 0;
- }
-
- static const struct ethtool_ops ltq_etop_ethtool_ops = {
-@@ -339,6 +469,39 @@ static const struct ethtool_ops ltq_etop_ethtool_ops = {
- };
-
- static int
-+ltq_etop_mdio_wr_xr9(struct mii_bus *bus, int phy_addr,
-+ int phy_reg, u16 phy_data)
-+{
-+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_WRITE |
-+ (phy_data << MDIO_XR9_WR_OFFSET) |
-+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
-+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
-+
-+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
-+ ;
-+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
-+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
-+ ;
-+ return 0;
-+}
-+
-+static int
-+ltq_etop_mdio_rd_xr9(struct mii_bus *bus, int phy_addr, int phy_reg)
-+{
-+ u32 val = MDIO_XR9_REQUEST | MDIO_XR9_READ |
-+ ((phy_addr & MDIO_XR9_ADDR_MASK) << MDIO_XR9_ADDR_OFFSET) |
-+ ((phy_reg & MDIO_XR9_REG_MASK) << MDIO_XR9_REG_OFFSET);
-+
-+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
-+ ;
-+ ltq_gbit_w32(val, LTQ_GBIT_MDIO_CTL);
-+ while (ltq_gbit_r32(LTQ_GBIT_MDIO_CTL) & MDIO_XR9_REQUEST)
-+ ;
-+ val = ltq_gbit_r32(LTQ_GBIT_MDIO_DATA) & MDIO_XR9_RD_MASK;
-+ return val;
-+}
-+
-+static int
- ltq_etop_mdio_wr(struct mii_bus *bus, int phy_addr, int phy_reg, u16 phy_data)
- {
- u32 val = MDIO_REQUEST |
-@@ -379,14 +542,11 @@ ltq_etop_mdio_probe(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
- struct phy_device *phydev = NULL;
-- int phy_addr;
-
-- for (phy_addr = 0; phy_addr < PHY_MAX_ADDR; phy_addr++) {
-- if (priv->mii_bus->phy_map[phy_addr]) {
-- phydev = priv->mii_bus->phy_map[phy_addr];
-- break;
-- }
-- }
-+ if (of_machine_is_compatible("lantiq,ase"))
-+ phydev = priv->mii_bus->phy_map[8];
-+ else
-+ phydev = priv->mii_bus->phy_map[0];
-
- if (!phydev) {
- netdev_err(dev, "no PHY found\n");
-@@ -394,7 +554,7 @@ ltq_etop_mdio_probe(struct net_device *dev)
- }
-
- phydev = phy_connect(dev, dev_name(&phydev->dev), &ltq_etop_mdio_link,
-- 0, priv->pldata->mii_mode);
-+ 0, priv->mii_mode);
-
- if (IS_ERR(phydev)) {
- netdev_err(dev, "Could not attach to PHY\n");
-@@ -408,6 +568,9 @@ ltq_etop_mdio_probe(struct net_device *dev)
- | SUPPORTED_Autoneg
- | SUPPORTED_MII
- | SUPPORTED_TP);
-+ if (of_machine_is_compatible("lantiq,ar9"))
-+ phydev->supported &= SUPPORTED_1000baseT_Half
-+ | SUPPORTED_1000baseT_Full;
-
- phydev->advertising = phydev->supported;
- priv->phydev = phydev;
-@@ -433,8 +596,13 @@ ltq_etop_mdio_init(struct net_device *dev)
- }
-
- priv->mii_bus->priv = dev;
-- priv->mii_bus->read = ltq_etop_mdio_rd;
-- priv->mii_bus->write = ltq_etop_mdio_wr;
-+ if (of_machine_is_compatible("lantiq,ar9")) {
-+ priv->mii_bus->read = ltq_etop_mdio_rd_xr9;
-+ priv->mii_bus->write = ltq_etop_mdio_wr_xr9;
-+ } else {
-+ priv->mii_bus->read = ltq_etop_mdio_rd;
-+ priv->mii_bus->write = ltq_etop_mdio_wr;
-+ }
- priv->mii_bus->name = "ltq_mii";
- snprintf(priv->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
- priv->pdev->name, priv->pdev->id);
-@@ -483,17 +651,19 @@ static int
- ltq_etop_open(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-- int i;
-+ unsigned long flags;
-
-- for (i = 0; i < MAX_DMA_CHAN; i++) {
-- struct ltq_etop_chan *ch = &priv->ch[i];
-+ napi_enable(&priv->txch.napi);
-+ napi_enable(&priv->rxch.napi);
-+
-+ spin_lock_irqsave(&priv->lock, flags);
-+ ltq_dma_open(&priv->txch.dma);
-+ ltq_dma_open(&priv->rxch.dma);
-+ spin_unlock_irqrestore(&priv->lock, flags);
-+
-+ if (priv->phydev)
-+ phy_start(priv->phydev);
-
-- if (!IS_TX(i) && (!IS_RX(i)))
-- continue;
-- ltq_dma_open(&ch->dma);
-- napi_enable(&ch->napi);
-- }
-- phy_start(priv->phydev);
- netif_tx_start_all_queues(dev);
- return 0;
- }
-@@ -502,18 +672,19 @@ static int
- ltq_etop_stop(struct net_device *dev)
- {
- struct ltq_etop_priv *priv = netdev_priv(dev);
-- int i;
-+ unsigned long flags;
-
- netif_tx_stop_all_queues(dev);
-- phy_stop(priv->phydev);
-- for (i = 0; i < MAX_DMA_CHAN; i++) {
-- struct ltq_etop_chan *ch = &priv->ch[i];
-+ if (priv->phydev)
-+ phy_stop(priv->phydev);
-+ napi_disable(&priv->txch.napi);
-+ napi_disable(&priv->rxch.napi);
-+
-+ spin_lock_irqsave(&priv->lock, flags);
-+ ltq_dma_close(&priv->txch.dma);
-+ ltq_dma_close(&priv->rxch.dma);
-+ spin_unlock_irqrestore(&priv->lock, flags);
-
-- if (!IS_RX(i) && !IS_TX(i))
-- continue;
-- napi_disable(&ch->napi);
-- ltq_dma_close(&ch->dma);
-- }
- return 0;
- }
-
-@@ -523,16 +694,16 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
- int queue = skb_get_queue_mapping(skb);
- struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
- struct ltq_etop_priv *priv = netdev_priv(dev);
-- struct ltq_etop_chan *ch = &priv->ch[(queue << 1) | 1];
-- struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
-- int len;
-+ struct ltq_dma_desc *desc =
-+ &priv->txch.dma.desc_base[priv->txch.dma.desc];
- unsigned long flags;
- u32 byte_offset;
-+ int len;
-
- len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
-
-- if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
-- dev_kfree_skb_any(skb);
-+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) ||
-+ priv->txch.skb[priv->txch.dma.desc]) {
- netdev_err(dev, "tx ring full\n");
- netif_tx_stop_queue(txq);
- return NETDEV_TX_BUSY;
-@@ -540,7 +711,7 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
-
- /* dma needs to start on a 16 byte aligned address */
- byte_offset = CPHYSADDR(skb->data) % 16;
-- ch->skb[ch->dma.desc] = skb;
-+ priv->txch.skb[priv->txch.dma.desc] = skb;
-
- dev->trans_start = jiffies;
-
-@@ -550,11 +721,11 @@ ltq_etop_tx(struct sk_buff *skb, struct net_device *dev)
- wmb();
- desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
- LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
-- ch->dma.desc++;
-- ch->dma.desc %= LTQ_DESC_NUM;
-+ priv->txch.dma.desc++;
-+ priv->txch.dma.desc %= LTQ_DESC_NUM;
- spin_unlock_irqrestore(&priv->lock, flags);
-
-- if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
-+ if (priv->txch.dma.desc_base[priv->txch.dma.desc].ctl & LTQ_DMA_OWN)
- netif_tx_stop_queue(txq);
-
- return NETDEV_TX_OK;
-@@ -633,34 +804,32 @@ ltq_etop_init(struct net_device *dev)
- struct ltq_etop_priv *priv = netdev_priv(dev);
- struct sockaddr mac;
- int err;
-- bool random_mac = false;
-
- ether_setup(dev);
- dev->watchdog_timeo = 10 * HZ;
- err = ltq_etop_hw_init(dev);
- if (err)
- goto err_hw;
-+ err = ltq_etop_dma_init(dev);
-+ if (err)
-+ goto err_hw;
-+
- ltq_etop_change_mtu(dev, 1500);
-
-- memcpy(&mac, &priv->pldata->mac, sizeof(struct sockaddr));
-+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
- if (!is_valid_ether_addr(mac.sa_data)) {
- pr_warn("etop: invalid MAC, using random\n");
-- eth_random_addr(mac.sa_data);
-- random_mac = true;
-+ random_ether_addr(mac.sa_data);
- }
-
- err = ltq_etop_set_mac_address(dev, &mac);
- if (err)
- goto err_netdev;
--
-- /* Set addr_assign_type here, ltq_etop_set_mac_address would reset it. */
-- if (random_mac)
-- dev->addr_assign_type |= NET_ADDR_RANDOM;
--
- ltq_etop_set_multicast_list(dev);
-- err = ltq_etop_mdio_init(dev);
-- if (err)
-- goto err_netdev;
-+ if (!ltq_etop_mdio_init(dev))
-+ dev->ethtool_ops = &ltq_etop_ethtool_ops;
-+ else
-+ pr_warn("etop: mdio probe failed\n");;
- return 0;
-
- err_netdev:
-@@ -680,6 +849,9 @@ ltq_etop_tx_timeout(struct net_device *dev)
- err = ltq_etop_hw_init(dev);
- if (err)
- goto err_hw;
-+ err = ltq_etop_dma_init(dev);
-+ if (err)
-+ goto err_hw;
- dev->trans_start = jiffies;
- netif_wake_queue(dev);
- return;
-@@ -703,14 +875,19 @@ static const struct net_device_ops ltq_eth_netdev_ops = {
- .ndo_tx_timeout = ltq_etop_tx_timeout,
- };
-
--static int __init
-+static int __devinit
- ltq_etop_probe(struct platform_device *pdev)
- {
- struct net_device *dev;
- struct ltq_etop_priv *priv;
-- struct resource *res;
-+ struct resource *res, *gbit_res, irqres[2];
- int err;
-- int i;
-+
-+ err = of_irq_to_resource_table(pdev->dev.of_node, irqres, 2);
-+ if (err != 2) {
-+ dev_err(&pdev->dev, "failed to get etop irqs\n");
-+ return -EINVAL;
-+ }
-
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- if (!res) {
-@@ -736,30 +913,58 @@ ltq_etop_probe(struct platform_device *pdev)
- goto err_out;
- }
-
-- dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
-- if (!dev) {
-- err = -ENOMEM;
-- goto err_out;
-+ if (of_machine_is_compatible("lantiq,ar9")) {
-+ gbit_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
-+ if (!gbit_res) {
-+ dev_err(&pdev->dev, "failed to get gbit resource\n");
-+ err = -ENOENT;
-+ goto err_out;
-+ }
-+ ltq_gbit_membase = devm_ioremap_nocache(&pdev->dev,
-+ gbit_res->start, resource_size(gbit_res));
-+ if (!ltq_gbit_membase) {
-+ dev_err(&pdev->dev, "failed to remap gigabit switch %d\n",
-+ pdev->id);
-+ err = -ENOMEM;
-+ goto err_out;
-+ }
- }
-+
-+ dev = alloc_etherdev_mq(sizeof(struct ltq_etop_priv), 4);
- strcpy(dev->name, "eth%d");
- dev->netdev_ops = &ltq_eth_netdev_ops;
-- dev->ethtool_ops = &ltq_etop_ethtool_ops;
- priv = netdev_priv(dev);
- priv->res = res;
- priv->pdev = pdev;
-- priv->pldata = dev_get_platdata(&pdev->dev);
- priv->netdev = dev;
-+ priv->tx_irq = irqres[0].start;
-+ priv->rx_irq = irqres[1].start;
-+ priv->mii_mode = of_get_phy_mode(pdev->dev.of_node);
-+ priv->mac = of_get_mac_address(pdev->dev.of_node);
-+
-+ priv->clk_ppe = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(priv->clk_ppe))
-+ return PTR_ERR(priv->clk_ppe);
-+ if (of_machine_is_compatible("lantiq,ar9")) {
-+ priv->clk_switch = clk_get(&pdev->dev, "switch");
-+ if (IS_ERR(priv->clk_switch))
-+ return PTR_ERR(priv->clk_switch);
-+ }
-+ if (of_machine_is_compatible("lantiq,ase")) {
-+ priv->clk_ephy = clk_get(&pdev->dev, "ephy");
-+ if (IS_ERR(priv->clk_ephy))
-+ return PTR_ERR(priv->clk_ephy);
-+ priv->clk_ephycgu = clk_get(&pdev->dev, "ephycgu");
-+ if (IS_ERR(priv->clk_ephycgu))
-+ return PTR_ERR(priv->clk_ephycgu);
-+ }
-+
- spin_lock_init(&priv->lock);
-
-- for (i = 0; i < MAX_DMA_CHAN; i++) {
-- if (IS_TX(i))
-- netif_napi_add(dev, &priv->ch[i].napi,
-- ltq_etop_poll_tx, 8);
-- else if (IS_RX(i))
-- netif_napi_add(dev, &priv->ch[i].napi,
-- ltq_etop_poll_rx, 32);
-- priv->ch[i].netdev = dev;
-- }
-+ netif_napi_add(dev, &priv->txch.napi, ltq_etop_poll_tx, 8);
-+ netif_napi_add(dev, &priv->rxch.napi, ltq_etop_poll_rx, 32);
-+ priv->txch.netdev = dev;
-+ priv->rxch.netdev = dev;
-
- err = register_netdev(dev);
- if (err)
-@@ -788,32 +993,23 @@ ltq_etop_remove(struct platform_device *pdev)
- return 0;
- }
-
-+static const struct of_device_id ltq_etop_match[] = {
-+ { .compatible = "lantiq,etop-xway" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, ltq_etop_match);
-+
- static struct platform_driver ltq_mii_driver = {
-+ .probe = ltq_etop_probe,
- .remove = __devexit_p(ltq_etop_remove),
- .driver = {
- .name = "ltq_etop",
- .owner = THIS_MODULE,
-+ .of_match_table = ltq_etop_match,
- },
- };
-
--int __init
--init_ltq_etop(void)
--{
-- int ret = platform_driver_probe(&ltq_mii_driver, ltq_etop_probe);
--
-- if (ret)
-- pr_err("ltq_etop: Error registering platform driver!");
-- return ret;
--}
--
--static void __exit
--exit_ltq_etop(void)
--{
-- platform_driver_unregister(&ltq_mii_driver);
--}
--
--module_init(init_ltq_etop);
--module_exit(exit_ltq_etop);
-+module_platform_driver(ltq_mii_driver);
-
- MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
- MODULE_DESCRIPTION("Lantiq SoC ETOP");
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0112-NET-MIPS-lantiq-adds-xrx200-net.patch b/target/linux/lantiq/patches-3.6/0112-NET-MIPS-lantiq-adds-xrx200-net.patch
deleted file mode 100644
index ea69c5c21e..0000000000
--- a/target/linux/lantiq/patches-3.6/0112-NET-MIPS-lantiq-adds-xrx200-net.patch
+++ /dev/null
@@ -1,1382 +0,0 @@
-From dd440736aa03cbe9fcf49e4bfdbb22c947f8ba67 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 12:22:23 +0200
-Subject: [PATCH 112/113] NET: MIPS: lantiq: adds xrx200-net
-
----
- drivers/net/ethernet/Kconfig | 8 +-
- drivers/net/ethernet/Makefile | 1 +
- drivers/net/ethernet/lantiq_pce.h | 163 +++++
- drivers/net/ethernet/lantiq_xrx200.c | 1159 ++++++++++++++++++++++++++++++++++
- 4 files changed, 1330 insertions(+), 1 deletion(-)
- create mode 100644 drivers/net/ethernet/lantiq_pce.h
- create mode 100644 drivers/net/ethernet/lantiq_xrx200.c
-
-diff --git a/drivers/net/ethernet/Kconfig b/drivers/net/ethernet/Kconfig
-index e4ff389..35cb7b0 100644
---- a/drivers/net/ethernet/Kconfig
-+++ b/drivers/net/ethernet/Kconfig
-@@ -83,7 +83,13 @@ config LANTIQ_ETOP
- tristate "Lantiq SoC ETOP driver"
- depends on SOC_TYPE_XWAY
- ---help---
-- Support for the MII0 inside the Lantiq SoC
-+ Support for the MII0 inside the Lantiq ADSL SoC
-+
-+config LANTIQ_XRX200
-+ tristate "Lantiq SoC XRX200 driver"
-+ depends on SOC_TYPE_XWAY
-+ ---help---
-+ Support for the MII0 inside the Lantiq VDSL SoC
-
- source "drivers/net/ethernet/marvell/Kconfig"
- source "drivers/net/ethernet/mellanox/Kconfig"
-diff --git a/drivers/net/ethernet/Makefile b/drivers/net/ethernet/Makefile
-index d447307..4f95100 100644
---- a/drivers/net/ethernet/Makefile
-+++ b/drivers/net/ethernet/Makefile
-@@ -36,6 +36,7 @@ obj-$(CONFIG_IP1000) += icplus/
- obj-$(CONFIG_JME) += jme.o
- obj-$(CONFIG_KORINA) += korina.o
- obj-$(CONFIG_LANTIQ_ETOP) += lantiq_etop.o
-+obj-$(CONFIG_LANTIQ_XRX200) += lantiq_xrx200.o
- obj-$(CONFIG_NET_VENDOR_MARVELL) += marvell/
- obj-$(CONFIG_NET_VENDOR_MELLANOX) += mellanox/
- obj-$(CONFIG_NET_VENDOR_MICREL) += micrel/
-diff --git a/drivers/net/ethernet/lantiq_pce.h b/drivers/net/ethernet/lantiq_pce.h
-new file mode 100644
-index 0000000..0c38efe
---- /dev/null
-+++ b/drivers/net/ethernet/lantiq_pce.h
-@@ -0,0 +1,163 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2010 Lantiq Deutschland GmbH
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ *
-+ * PCE microcode extracted from UGW5.2 switch api
-+ */
-+
-+/* Switch API Micro Code V0.3 */
-+enum {
-+ OUT_MAC0 = 0,
-+ OUT_MAC1,
-+ OUT_MAC2,
-+ OUT_MAC3,
-+ OUT_MAC4,
-+ OUT_MAC5,
-+ OUT_ETHTYP,
-+ OUT_VTAG0,
-+ OUT_VTAG1,
-+ OUT_ITAG0,
-+ OUT_ITAG1, /*10 */
-+ OUT_ITAG2,
-+ OUT_ITAG3,
-+ OUT_IP0,
-+ OUT_IP1,
-+ OUT_IP2,
-+ OUT_IP3,
-+ OUT_SIP0,
-+ OUT_SIP1,
-+ OUT_SIP2,
-+ OUT_SIP3, /*20*/
-+ OUT_SIP4,
-+ OUT_SIP5,
-+ OUT_SIP6,
-+ OUT_SIP7,
-+ OUT_DIP0,
-+ OUT_DIP1,
-+ OUT_DIP2,
-+ OUT_DIP3,
-+ OUT_DIP4,
-+ OUT_DIP5, /*30*/
-+ OUT_DIP6,
-+ OUT_DIP7,
-+ OUT_SESID,
-+ OUT_PROT,
-+ OUT_APP0,
-+ OUT_APP1,
-+ OUT_IGMP0,
-+ OUT_IGMP1,
-+ OUT_IPOFF, /*39*/
-+ OUT_NONE = 63
-+};
-+
-+/* parser's microcode length type */
-+#define INSTR 0
-+#define IPV6 1
-+#define LENACCU 2
-+
-+/* parser's microcode flag type */
-+enum {
-+ FLAG_ITAG = 0,
-+ FLAG_VLAN,
-+ FLAG_SNAP,
-+ FLAG_PPPOE,
-+ FLAG_IPV6,
-+ FLAG_IPV6FL,
-+ FLAG_IPV4,
-+ FLAG_IGMP,
-+ FLAG_TU,
-+ FLAG_HOP,
-+ FLAG_NN1, /*10 */
-+ FLAG_NN2,
-+ FLAG_END,
-+ FLAG_NO, /*13*/
-+};
-+
-+/* Micro code version V2_11 (extension for parsing IPv6 in PPPoE) */
-+#define MC_ENTRY(val, msk, ns, out, len, type, flags, ipv4_len) \
-+ { {val, msk, (ns<<10 | out<<4 | len>>1), (len&1)<<15 | type<<13 | flags<<9 | ipv4_len<<8 }}
-+struct pce_microcode {
-+ unsigned short val[4];
-+/* unsigned short val_2;
-+ unsigned short val_1;
-+ unsigned short val_0;*/
-+} pce_microcode[] = {
-+ /* value mask ns fields L type flags ipv4_len */
-+ MC_ENTRY(0x88c3, 0xFFFF, 1, OUT_ITAG0, 4, INSTR, FLAG_ITAG, 0),
-+ MC_ENTRY(0x8100, 0xFFFF, 2, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
-+ MC_ENTRY(0x88A8, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
-+ MC_ENTRY(0x8100, 0xFFFF, 1, OUT_VTAG0, 2, INSTR, FLAG_VLAN, 0),
-+ MC_ENTRY(0x8864, 0xFFFF, 17, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0800, 0xFFFF, 21, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x86DD, 0xFFFF, 22, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x8863, 0xFFFF, 16, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0xF800, 10, OUT_NONE, 0, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0600, 0x0600, 38, OUT_ETHTYP, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 12, OUT_NONE, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0xAAAA, 0xFFFF, 14, OUT_NONE, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0300, 0xFF00, 39, OUT_NONE, 0, INSTR, FLAG_SNAP, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_DIP7, 3, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 18, OUT_DIP7, 3, INSTR, FLAG_PPPOE, 0),
-+ MC_ENTRY(0x0021, 0xFFFF, 21, OUT_NONE, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0057, 0xFFFF, 22, OUT_NONE, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x4000, 0xF000, 24, OUT_IP0, 4, INSTR, FLAG_IPV4, 1),
-+ MC_ENTRY(0x6000, 0xF000, 27, OUT_IP0, 3, INSTR, FLAG_IPV6, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 25, OUT_IP3, 2, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 26, OUT_SIP0, 4, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 38, OUT_NONE, 0, LENACCU, FLAG_NO, 0),
-+ MC_ENTRY(0x1100, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0600, 0xFF00, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_HOP, 0),
-+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN1, 0),
-+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_IP3, 17, INSTR, FLAG_NN2, 0),
-+ MC_ENTRY(0x0000, 0x0000, 37, OUT_PROT, 1, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_HOP, 0),
-+ MC_ENTRY(0x2B00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN1, 0),
-+ MC_ENTRY(0x3C00, 0xFF00, 33, OUT_NONE, 0, IPV6, FLAG_NN2, 0),
-+ MC_ENTRY(0x0000, 0x0000, 38, OUT_PROT, 1, IPV6, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 38, OUT_SIP0, 16, INSTR, FLAG_NO, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_APP0, 4, INSTR, FLAG_IGMP, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+ MC_ENTRY(0x0000, 0x0000, 39, OUT_NONE, 0, INSTR, FLAG_END, 0),
-+};
-diff --git a/drivers/net/ethernet/lantiq_xrx200.c b/drivers/net/ethernet/lantiq_xrx200.c
-new file mode 100644
-index 0000000..71abc7d
---- /dev/null
-+++ b/drivers/net/ethernet/lantiq_xrx200.c
-@@ -0,0 +1,1159 @@
-+/*
-+ * This program is free software; you can redistribute it and/or modify it
-+ * under the terms of the GNU General Public License version 2 as published
-+ * by the Free Software Foundation.
-+ *
-+ * This program is distributed in the hope that it will be useful,
-+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
-+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
-+ * GNU General Public License for more details.
-+ *
-+ * You should have received a copy of the GNU General Public License
-+ * along with this program; if not, write to the Free Software
-+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307, USA.
-+ *
-+ * Copyright (C) 2010 Lantiq Deutschland
-+ * Copyright (C) 2012 John Crispin <blogic@openwrt.org>
-+ */
-+
-+#include <linux/etherdevice.h>
-+#include <linux/module.h>
-+#include <linux/platform_device.h>
-+#include <linux/interrupt.h>
-+#include <linux/clk.h>
-+#include <asm/delay.h>
-+
-+#include <linux/of_net.h>
-+#include <linux/of_mdio.h>
-+
-+#include <xway_dma.h>
-+#include <lantiq_soc.h>
-+
-+#include "lantiq_pce.h"
-+
-+#define SW_POLLING
-+#define SW_ROUTING
-+
-+#ifdef SW_ROUTING
-+#define XRX200_MAX_DEV 2
-+#else
-+#define XRX200_MAX_DEV 1
-+#endif
-+
-+#define XRX200_MAX_PORT 7
-+#define XRX200_MAX_DMA 8
-+
-+#define XRX200_HEADROOM 4
-+
-+#define XRX200_TX_TIMEOUT (10 * HZ)
-+
-+/* port type */
-+#define XRX200_PORT_TYPE_PHY 1
-+#define XRX200_PORT_TYPE_MAC 2
-+
-+/* DMA */
-+#define XRX200_DMA_CRC_LEN 0x4
-+#define XRX200_DMA_DATA_LEN 0x600
-+#define XRX200_DMA_IRQ INT_NUM_IM2_IRL0
-+#define XRX200_DMA_RX 0
-+#define XRX200_DMA_TX 1
-+
-+/* fetch / store dma */
-+#define FDMA_PCTRL0 0x2A00
-+#define FDMA_PCTRLx(x) (FDMA_PCTRL0 + (x * 0x18))
-+#define SDMA_PCTRL0 0x2F00
-+#define SDMA_PCTRLx(x) (SDMA_PCTRL0 + (x * 0x18))
-+
-+/* buffer management */
-+#define BM_PCFG0 0x200
-+#define BM_PCFGx(x) (BM_PCFG0 + (x * 8))
-+
-+/* MDIO */
-+#define MDIO_GLOB 0x0000
-+#define MDIO_CTRL 0x0020
-+#define MDIO_READ 0x0024
-+#define MDIO_WRITE 0x0028
-+#define MDIO_PHY0 0x0054
-+#define MDIO_PHY(x) (0x0054 - (x * sizeof(unsigned)))
-+#define MDIO_CLK_CFG0 0x002C
-+#define MDIO_CLK_CFG1 0x0030
-+
-+#define MDIO_GLOB_ENABLE 0x8000
-+#define MDIO_BUSY BIT(12)
-+#define MDIO_RD BIT(11)
-+#define MDIO_WR BIT(10)
-+#define MDIO_MASK 0x1f
-+#define MDIO_ADDRSHIFT 5
-+#define MDIO1_25MHZ 9
-+
-+#define MDIO_PHY_LINK_DOWN 0x4000
-+#define MDIO_PHY_LINK_UP 0x2000
-+
-+#define MDIO_PHY_SPEED_M10 0x0000
-+#define MDIO_PHY_SPEED_M100 0x0800
-+#define MDIO_PHY_SPEED_G1 0x1000
-+
-+#define MDIO_PHY_FDUP_EN 0x0600
-+#define MDIO_PHY_FDUP_DIS 0x0200
-+
-+#define MDIO_PHY_LINK_MASK 0x6000
-+#define MDIO_PHY_SPEED_MASK 0x1800
-+#define MDIO_PHY_FDUP_MASK 0x0600
-+#define MDIO_PHY_ADDR_MASK 0x001f
-+#define MDIO_UPDATE_MASK MDIO_PHY_ADDR_MASK | MDIO_PHY_LINK_MASK | \
-+ MDIO_PHY_SPEED_MASK | MDIO_PHY_FDUP_MASK
-+
-+/* MII */
-+#define MII_CFG(p) (p * 8)
-+
-+#define MII_CFG_EN BIT(14)
-+
-+#define MII_CFG_MODE_MIIP 0x0
-+#define MII_CFG_MODE_MIIM 0x1
-+#define MII_CFG_MODE_RMIIP 0x2
-+#define MII_CFG_MODE_RMIIM 0x3
-+#define MII_CFG_MODE_RGMII 0x4
-+#define MII_CFG_MODE_MASK 0xf
-+
-+#define MII_CFG_RATE_M2P5 0x00
-+#define MII_CFG_RATE_M25 0x10
-+#define MII_CFG_RATE_M125 0x20
-+#define MII_CFG_RATE_M50 0x30
-+#define MII_CFG_RATE_AUTO 0x40
-+#define MII_CFG_RATE_MASK 0x70
-+
-+/* cpu port mac */
-+#define PMAC_HD_CTL 0x0000
-+#define PMAC_RX_IPG 0x0024
-+#define PMAC_EWAN 0x002c
-+
-+#define PMAC_IPG_MASK 0xf
-+#define PMAC_HD_CTL_AS 0x0008
-+#define PMAC_HD_CTL_AC 0x0004
-+#define PMAC_HD_CTL_RXSH 0x0040
-+#define PMAC_HD_CTL_AST 0x0080
-+
-+/* PCE */
-+#define PCE_TBL_KEY(x) (0x1100 + ((7 - x) * 4))
-+#define PCE_TBL_MASK 0x1120
-+#define PCE_TBL_VAL(x) (0x1124 + ((4 - x) * 4))
-+#define PCE_TBL_ADDR 0x1138
-+#define PCE_TBL_CTRL 0x113c
-+#define PCE_PMAP1 0x114c
-+#define PCE_PMAP2 0x1150
-+#define PCE_PMAP3 0x1154
-+#define PCE_GCTRL_REG(x) (0x1158 + (x * 4))
-+#define PCE_PCTRL_REG(p, x) (0x1200 + (((p * 0xa) + x) * 4))
-+
-+#define PCE_TBL_BUSY BIT(15)
-+#define PCE_TBL_CFG_ADDR_MASK 0x1f
-+#define PCE_TBL_CFG_ADWR 0x20
-+#define PCE_TBL_CFG_ADWR_MASK 0x60
-+#define PCE_INGRESS BIT(11)
-+
-+/* buffer management */
-+#define BM_PCFG(p) (0x200 + (p * 8))
-+
-+/* special tag in TX path header */
-+#define SPID_SHIFT 24
-+#define DPID_SHIFT 16
-+#define DPID_ENABLE 1
-+#define SPID_CPU_PORT 2
-+
-+#define SPPID_MASK 0x7
-+#define SPPID_SHIFT 4
-+
-+/* MII regs not yet in linux */
-+#define MDIO_DEVAD_NONE (-1)
-+#define ADVERTIZE_MPD (1 << 10)
-+
-+struct xrx200_port {
-+ u8 num;
-+ u8 phy_addr;
-+ u16 flags;
-+ phy_interface_t phy_if;
-+
-+ int link;
-+
-+ struct phy_device *phydev;
-+ struct device_node *phy_node;
-+};
-+
-+struct xrx200_chan {
-+ int idx;
-+ int refcount;
-+ int tx_free;
-+
-+ struct net_device dummy_dev;
-+ struct net_device *devs[XRX200_MAX_DEV];
-+
-+ struct napi_struct napi;
-+ struct ltq_dma_channel dma;
-+ struct sk_buff *skb[LTQ_DESC_NUM];
-+};
-+
-+struct xrx200_hw {
-+ struct clk *clk;
-+ struct mii_bus *mii_bus;
-+
-+ struct xrx200_chan chan[XRX200_MAX_DMA];
-+
-+ struct net_device *devs[XRX200_MAX_DEV];
-+ int num_devs;
-+
-+ int port_map[XRX200_MAX_PORT];
-+ unsigned short wan_map;
-+
-+ spinlock_t lock;
-+};
-+
-+struct xrx200_priv {
-+ struct net_device_stats stats;
-+ int id;
-+
-+ struct xrx200_port port[XRX200_MAX_PORT];
-+ int num_port;
-+ int wan;
-+ const void *mac;
-+
-+ struct xrx200_hw *hw;
-+};
-+
-+static __iomem void *xrx200_switch_membase;
-+static __iomem void *xrx200_mii_membase;
-+static __iomem void *xrx200_mdio_membase;
-+static __iomem void *xrx200_pmac_membase;
-+
-+#define ltq_switch_r32(x) ltq_r32(xrx200_switch_membase + (x))
-+#define ltq_switch_w32(x, y) ltq_w32(x, xrx200_switch_membase + (y))
-+#define ltq_switch_w32_mask(x, y, z) \
-+ ltq_w32_mask(x, y, xrx200_switch_membase + (z))
-+
-+#define ltq_mdio_r32(x) ltq_r32(xrx200_mdio_membase + (x))
-+#define ltq_mdio_w32(x, y) ltq_w32(x, xrx200_mdio_membase + (y))
-+#define ltq_mdio_w32_mask(x, y, z) \
-+ ltq_w32_mask(x, y, xrx200_mdio_membase + (z))
-+
-+#define ltq_mii_r32(x) ltq_r32(xrx200_mii_membase + (x))
-+#define ltq_mii_w32(x, y) ltq_w32(x, xrx200_mii_membase + (y))
-+#define ltq_mii_w32_mask(x, y, z) \
-+ ltq_w32_mask(x, y, xrx200_mii_membase + (z))
-+
-+#define ltq_pmac_r32(x) ltq_r32(xrx200_pmac_membase + (x))
-+#define ltq_pmac_w32(x, y) ltq_w32(x, xrx200_pmac_membase + (y))
-+#define ltq_pmac_w32_mask(x, y, z) \
-+ ltq_w32_mask(x, y, xrx200_pmac_membase + (z))
-+
-+static int xrx200_open(struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ unsigned long flags;
-+ int i;
-+
-+ for (i = 0; i < XRX200_MAX_DMA; i++) {
-+ if (!priv->hw->chan[i].dma.irq)
-+ continue;
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ if (!priv->hw->chan[i].refcount) {
-+ napi_enable(&priv->hw->chan[i].napi);
-+ ltq_dma_open(&priv->hw->chan[i].dma);
-+ }
-+ priv->hw->chan[i].refcount++;
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+ }
-+ for (i = 0; i < priv->num_port; i++)
-+ if (priv->port[i].phydev)
-+ phy_start(priv->port[i].phydev);
-+ netif_start_queue(dev);
-+
-+ return 0;
-+}
-+
-+static int xrx200_close(struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ unsigned long flags;
-+ int i;
-+
-+ netif_stop_queue(dev);
-+
-+ for (i = 0; i < priv->num_port; i++)
-+ if (priv->port[i].phydev)
-+ phy_stop(priv->port[i].phydev);
-+
-+ for (i = 0; i < XRX200_MAX_DMA; i++) {
-+ if (!priv->hw->chan[i].dma.irq)
-+ continue;
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ priv->hw->chan[i].refcount--;
-+ if (!priv->hw->chan[i].refcount) {
-+ napi_disable(&priv->hw->chan[i].napi);
-+ ltq_dma_close(&priv->hw->chan[XRX200_DMA_RX].dma);
-+ }
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+ }
-+
-+ return 0;
-+}
-+
-+static int xrx200_alloc_skb(struct xrx200_chan *ch)
-+{
-+#define DMA_PAD (NET_IP_ALIGN) // + NET_SKB_PAD)
-+ ch->skb[ch->dma.desc] = dev_alloc_skb(XRX200_DMA_DATA_LEN + DMA_PAD);
-+ if (!ch->skb[ch->dma.desc])
-+ return -ENOMEM;
-+
-+ ch->dma.desc_base[ch->dma.desc].addr = dma_map_single(NULL,
-+ ch->skb[ch->dma.desc]->data, XRX200_DMA_DATA_LEN,
-+ DMA_FROM_DEVICE);
-+ ch->dma.desc_base[ch->dma.desc].addr =
-+ CPHYSADDR(ch->skb[ch->dma.desc]->data);
-+ ch->dma.desc_base[ch->dma.desc].ctl =
-+ LTQ_DMA_OWN | LTQ_DMA_RX_OFFSET(NET_IP_ALIGN) |
-+ XRX200_DMA_DATA_LEN;
-+ skb_reserve(ch->skb[ch->dma.desc], DMA_PAD);
-+
-+ return 0;
-+}
-+
-+static void xrx200_hw_receive(struct xrx200_chan *ch, int id)
-+{
-+ struct net_device *dev = ch->devs[id];
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
-+ struct sk_buff *skb = ch->skb[ch->dma.desc];
-+ int len = (desc->ctl & LTQ_DMA_SIZE_MASK) - XRX200_DMA_CRC_LEN;
-+ unsigned long flags;
-+
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ if (xrx200_alloc_skb(ch)) {
-+ netdev_err(dev,
-+ "failed to allocate new rx buffer, stopping DMA\n");
-+ ltq_dma_close(&ch->dma);
-+ }
-+
-+ ch->dma.desc++;
-+ ch->dma.desc %= LTQ_DESC_NUM;
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+
-+ skb_put(skb, len);
-+#ifdef SW_ROUTING
-+ skb_pull(skb, 8);
-+#endif
-+ skb->dev = dev;
-+ skb->protocol = eth_type_trans(skb, dev);
-+ netif_receive_skb(skb);
-+ priv->stats.rx_packets++;
-+ priv->stats.rx_bytes+=len;
-+}
-+
-+static int xrx200_poll_rx(struct napi_struct *napi, int budget)
-+{
-+ struct xrx200_chan *ch = container_of(napi,
-+ struct xrx200_chan, napi);
-+ struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
-+ int rx = 0;
-+ int complete = 0;
-+ unsigned long flags;
-+
-+ while ((rx < budget) && !complete) {
-+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
-+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
-+#ifdef SW_ROUTING
-+ struct sk_buff *skb = ch->skb[ch->dma.desc];
-+ u32 *special_tag = (u32*)skb->data;
-+ int port = (special_tag[1] >> SPPID_SHIFT) & SPPID_MASK;
-+ xrx200_hw_receive(ch, priv->hw->port_map[port]);
-+#else
-+ xrx200_hw_receive(ch, 0);
-+#endif
-+ rx++;
-+ } else {
-+ complete = 1;
-+ }
-+ }
-+ if (complete || !rx) {
-+ napi_complete(&ch->napi);
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ ltq_dma_ack_irq(&ch->dma);
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+ }
-+ return rx;
-+}
-+
-+static int xrx200_poll_tx(struct napi_struct *napi, int budget)
-+{
-+ struct xrx200_chan *ch =
-+ container_of(napi, struct xrx200_chan, napi);
-+ struct xrx200_priv *priv = netdev_priv(ch->devs[0]);
-+ unsigned long flags;
-+ int i;
-+
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ while ((ch->dma.desc_base[ch->tx_free].ctl &
-+ (LTQ_DMA_OWN | LTQ_DMA_C)) == LTQ_DMA_C) {
-+ dev_kfree_skb_any(ch->skb[ch->tx_free]);
-+ ch->skb[ch->tx_free] = NULL;
-+ memset(&ch->dma.desc_base[ch->tx_free], 0,
-+ sizeof(struct ltq_dma_desc));
-+ ch->tx_free++;
-+ ch->tx_free %= LTQ_DESC_NUM;
-+ }
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+
-+ for (i = 0; i < XRX200_MAX_DEV; i++) {
-+ struct netdev_queue *txq =
-+ netdev_get_tx_queue(ch->devs[i], 0);
-+ if (netif_tx_queue_stopped(txq))
-+ netif_tx_start_queue(txq);
-+ }
-+ napi_complete(&ch->napi);
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ ltq_dma_ack_irq(&ch->dma);
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+
-+ return 1;
-+}
-+
-+static struct net_device_stats *xrx200_get_stats (struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+
-+ return &priv->stats;
-+}
-+
-+static void xrx200_tx_timeout(struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+
-+ printk(KERN_ERR "%s: transmit timed out, disable the dma channel irq\n", dev->name);
-+
-+ priv->stats.tx_errors++;
-+ netif_wake_queue(dev);
-+}
-+
-+static int xrx200_start_xmit(struct sk_buff *skb, struct net_device *dev)
-+{
-+ int queue = skb_get_queue_mapping(skb);
-+ struct netdev_queue *txq = netdev_get_tx_queue(dev, queue);
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ struct xrx200_chan *ch = &priv->hw->chan[XRX200_DMA_TX];
-+ struct ltq_dma_desc *desc = &ch->dma.desc_base[ch->dma.desc];
-+ unsigned long flags;
-+ u32 byte_offset;
-+ int len;
-+#ifdef SW_ROUTING
-+ u32 special_tag = (SPID_CPU_PORT << SPID_SHIFT) | DPID_ENABLE;
-+#endif
-+
-+ len = skb->len < ETH_ZLEN ? ETH_ZLEN : skb->len;
-+
-+ if ((desc->ctl & (LTQ_DMA_OWN | LTQ_DMA_C)) || ch->skb[ch->dma.desc]) {
-+ netdev_err(dev, "tx ring full\n");
-+ netif_tx_stop_queue(txq);
-+ return NETDEV_TX_BUSY;
-+ }
-+#ifdef SW_ROUTING
-+ if(priv->id)
-+ special_tag |= (1 << DPID_SHIFT);
-+ if(skb_headroom(skb) < 4) {
-+ struct sk_buff *tmp = skb_realloc_headroom(skb, 4);
-+ dev_kfree_skb_any(skb);
-+ skb = tmp;
-+ }
-+ skb_push(skb, 4);
-+ memcpy(skb->data, &special_tag, sizeof(u32));
-+ len += 4;
-+#endif
-+
-+ /* dma needs to start on a 16 byte aligned address */
-+ byte_offset = CPHYSADDR(skb->data) % 16;
-+ ch->skb[ch->dma.desc] = skb;
-+
-+ dev->trans_start = jiffies;
-+
-+ spin_lock_irqsave(&priv->hw->lock, flags);
-+ desc->addr = ((unsigned int) dma_map_single(NULL, skb->data, len,
-+ DMA_TO_DEVICE)) - byte_offset;
-+ wmb();
-+ desc->ctl = LTQ_DMA_OWN | LTQ_DMA_SOP | LTQ_DMA_EOP |
-+ LTQ_DMA_TX_OFFSET(byte_offset) | (len & LTQ_DMA_SIZE_MASK);
-+ ch->dma.desc++;
-+ ch->dma.desc %= LTQ_DESC_NUM;
-+ spin_unlock_irqrestore(&priv->hw->lock, flags);
-+
-+ if (ch->dma.desc_base[ch->dma.desc].ctl & LTQ_DMA_OWN)
-+ netif_tx_stop_queue(txq);
-+
-+ priv->stats.tx_packets++;
-+ priv->stats.tx_bytes+=len;
-+
-+ return NETDEV_TX_OK;
-+}
-+
-+static irqreturn_t xrx200_dma_irq(int irq, void *priv)
-+{
-+ struct xrx200_hw *hw = priv;
-+ int ch = irq - XRX200_DMA_IRQ;
-+
-+ napi_schedule(&hw->chan[ch].napi);
-+
-+ return IRQ_HANDLED;
-+}
-+
-+static int xrx200_dma_init(struct xrx200_hw *hw)
-+{
-+ int i, err = 0;
-+
-+ ltq_dma_init_port(DMA_PORT_ETOP);
-+
-+ for (i = 0; i < 8 && !err; i++) {
-+ int irq = XRX200_DMA_IRQ + i;
-+ struct xrx200_chan *ch = &hw->chan[i];
-+
-+ ch->idx = ch->dma.nr = i;
-+
-+ if (i == XRX200_DMA_TX) {
-+ ltq_dma_alloc_tx(&ch->dma);
-+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_tx", hw);
-+ } else if (i == XRX200_DMA_RX) {
-+ ltq_dma_alloc_rx(&ch->dma);
-+ for (ch->dma.desc = 0; ch->dma.desc < LTQ_DESC_NUM;
-+ ch->dma.desc++)
-+ if (xrx200_alloc_skb(ch))
-+ err = -ENOMEM;
-+ ch->dma.desc = 0;
-+ err = request_irq(irq, xrx200_dma_irq, 0, "vrx200_rx", hw);
-+ } else
-+ continue;
-+
-+ if (!err)
-+ ch->dma.irq = irq;
-+ }
-+
-+ return err;
-+}
-+
-+#ifdef SW_POLLING
-+static void xrx200_gmac_update(struct xrx200_port *port)
-+{
-+ u16 phyaddr = port->phydev->addr & MDIO_PHY_ADDR_MASK;
-+ u16 miimode = ltq_mii_r32(MII_CFG(port->num)) & MII_CFG_MODE_MASK;
-+ u16 miirate = 0;
-+
-+ switch (port->phydev->speed) {
-+ case SPEED_1000:
-+ phyaddr |= MDIO_PHY_SPEED_G1;
-+ miirate = MII_CFG_RATE_M125;
-+ break;
-+
-+ case SPEED_100:
-+ phyaddr |= MDIO_PHY_SPEED_M100;
-+ switch (miimode) {
-+ case MII_CFG_MODE_RMIIM:
-+ case MII_CFG_MODE_RMIIP:
-+ miirate = MII_CFG_RATE_M50;
-+ break;
-+ default:
-+ miirate = MII_CFG_RATE_M25;
-+ break;
-+ }
-+ break;
-+
-+ default:
-+ phyaddr |= MDIO_PHY_SPEED_M10;
-+ miirate = MII_CFG_RATE_M2P5;
-+ break;
-+ }
-+
-+ if (port->phydev->link)
-+ phyaddr |= MDIO_PHY_LINK_UP;
-+ else
-+ phyaddr |= MDIO_PHY_LINK_DOWN;
-+
-+ if (port->phydev->duplex == DUPLEX_FULL)
-+ phyaddr |= MDIO_PHY_FDUP_EN;
-+ else
-+ phyaddr |= MDIO_PHY_FDUP_DIS;
-+
-+ ltq_mdio_w32_mask(MDIO_UPDATE_MASK, phyaddr, MDIO_PHY(port->num));
-+ ltq_mii_w32_mask(MII_CFG_RATE_MASK, miirate, MII_CFG(port->num));
-+ udelay(1);
-+}
-+#else
-+static void xrx200_gmac_update(struct xrx200_port *port)
-+{
-+
-+}
-+#endif
-+
-+static void xrx200_mdio_link(struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ int i;
-+
-+ for (i = 0; i < priv->num_port; i++) {
-+ if (!priv->port[i].phydev)
-+ continue;
-+
-+ if (priv->port[i].link != priv->port[i].phydev->link) {
-+ xrx200_gmac_update(&priv->port[i]);
-+ priv->port[i].link = priv->port[i].phydev->link;
-+ netdev_info(dev, "port %d %s link\n",
-+ priv->port[i].num,
-+ (priv->port[i].link)?("got"):("lost"));
-+ }
-+ }
-+}
-+
-+static inline int xrx200_mdio_poll(struct mii_bus *bus)
-+{
-+ unsigned cnt = 10000;
-+
-+ while (likely(cnt--)) {
-+ unsigned ctrl = ltq_mdio_r32(MDIO_CTRL);
-+ if ((ctrl & MDIO_BUSY) == 0)
-+ return 0;
-+ }
-+
-+ return 1;
-+}
-+
-+static int xrx200_mdio_wr(struct mii_bus *bus, int addr, int reg, u16 val)
-+{
-+ if (xrx200_mdio_poll(bus))
-+ return 1;
-+
-+ ltq_mdio_w32(val, MDIO_WRITE);
-+ ltq_mdio_w32(MDIO_BUSY | MDIO_WR |
-+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
-+ (reg & MDIO_MASK),
-+ MDIO_CTRL);
-+
-+ return 0;
-+}
-+
-+static int xrx200_mdio_rd(struct mii_bus *bus, int addr, int reg)
-+{
-+ if (xrx200_mdio_poll(bus))
-+ return -1;
-+
-+ ltq_mdio_w32(MDIO_BUSY | MDIO_RD |
-+ ((addr & MDIO_MASK) << MDIO_ADDRSHIFT) |
-+ (reg & MDIO_MASK),
-+ MDIO_CTRL);
-+
-+ if (xrx200_mdio_poll(bus))
-+ return -1;
-+
-+ return ltq_mdio_r32(MDIO_READ);
-+}
-+
-+static int xrx200_mdio_probe(struct net_device *dev, struct xrx200_port *port)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ struct phy_device *phydev = NULL;
-+ unsigned val;
-+
-+ phydev = priv->hw->mii_bus->phy_map[port->phy_addr];
-+
-+ if (!phydev) {
-+ netdev_err(dev, "no PHY found\n");
-+ return -ENODEV;
-+ }
-+
-+ phydev = phy_connect(dev, dev_name(&phydev->dev), &xrx200_mdio_link,
-+ 0, port->phy_if);
-+
-+ if (IS_ERR(phydev)) {
-+ netdev_err(dev, "Could not attach to PHY\n");
-+ return PTR_ERR(phydev);
-+ }
-+
-+ phydev->supported &= (SUPPORTED_10baseT_Half
-+ | SUPPORTED_10baseT_Full
-+ | SUPPORTED_100baseT_Half
-+ | SUPPORTED_100baseT_Full
-+ | SUPPORTED_1000baseT_Half
-+ | SUPPORTED_1000baseT_Full
-+ | SUPPORTED_Autoneg
-+ | SUPPORTED_MII
-+ | SUPPORTED_TP);
-+ phydev->advertising = phydev->supported;
-+ port->phydev = phydev;
-+
-+ pr_info("%s: attached PHY [%s] (phy_addr=%s, irq=%d)\n",
-+ dev->name, phydev->drv->name,
-+ dev_name(&phydev->dev), phydev->irq);
-+
-+#ifdef SW_POLLING
-+ phy_read_status(phydev);
-+
-+ val = xrx200_mdio_rd(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000);
-+ val |= ADVERTIZE_MPD;
-+ xrx200_mdio_wr(priv->hw->mii_bus, MDIO_DEVAD_NONE, MII_CTRL1000, val);
-+ xrx200_mdio_wr(priv->hw->mii_bus, 0, 0, 0x1040);
-+
-+ phy_start_aneg(phydev);
-+#endif
-+ return 0;
-+}
-+
-+static void xrx200_port_config(struct xrx200_priv *priv,
-+ const struct xrx200_port *port)
-+{
-+ u16 miimode = 0;
-+
-+ switch (port->num) {
-+ case 0: /* xMII0 */
-+ case 1: /* xMII1 */
-+ switch (port->phy_if) {
-+ case PHY_INTERFACE_MODE_MII:
-+ if (port->flags & XRX200_PORT_TYPE_PHY)
-+ /* MII MAC mode, connected to external PHY */
-+ miimode = MII_CFG_MODE_MIIM;
-+ else
-+ /* MII PHY mode, connected to external MAC */
-+ miimode = MII_CFG_MODE_MIIP;
-+ break;
-+ case PHY_INTERFACE_MODE_RMII:
-+ if (port->flags & XRX200_PORT_TYPE_PHY)
-+ /* RMII MAC mode, connected to external PHY */
-+ miimode = MII_CFG_MODE_RMIIM;
-+ else
-+ /* RMII PHY mode, connected to external MAC */
-+ miimode = MII_CFG_MODE_RMIIP;
-+ break;
-+ case PHY_INTERFACE_MODE_RGMII:
-+ /* RGMII MAC mode, connected to external PHY */
-+ miimode = MII_CFG_MODE_RGMII;
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ case 2: /* internal GPHY0 */
-+ case 3: /* internal GPHY0 */
-+ case 4: /* internal GPHY1 */
-+ switch (port->phy_if) {
-+ case PHY_INTERFACE_MODE_MII:
-+ case PHY_INTERFACE_MODE_GMII:
-+ /* MII MAC mode, connected to internal GPHY */
-+ miimode = MII_CFG_MODE_MIIM;
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ case 5: /* internal GPHY1 or xMII2 */
-+ switch (port->phy_if) {
-+ case PHY_INTERFACE_MODE_MII:
-+ /* MII MAC mode, connected to internal GPHY */
-+ miimode = MII_CFG_MODE_MIIM;
-+ break;
-+ case PHY_INTERFACE_MODE_RGMII:
-+ /* RGMII MAC mode, connected to external PHY */
-+ miimode = MII_CFG_MODE_RGMII;
-+ break;
-+ default:
-+ break;
-+ }
-+ break;
-+ default:
-+ break;
-+ }
-+
-+ ltq_mii_w32_mask(MII_CFG_MODE_MASK, miimode | MII_CFG_EN,
-+ MII_CFG(port->num));
-+}
-+
-+static int xrx200_init(struct net_device *dev)
-+{
-+ struct xrx200_priv *priv = netdev_priv(dev);
-+ struct sockaddr mac;
-+ int err, i;
-+
-+#ifndef SW_POLLING
-+ unsigned int reg = 0;
-+
-+ /* enable auto polling */
-+ for (i = 0; i < priv->num_port; i++)
-+ reg |= BIT(priv->port[i].num);
-+ ltq_mdio_w32(reg, MDIO_CLK_CFG0);
-+ ltq_mdio_w32(MDIO1_25MHZ, MDIO_CLK_CFG1);
-+#endif
-+
-+ /* setup each port */
-+ for (i = 0; i < priv->num_port; i++)
-+ xrx200_port_config(priv, &priv->port[i]);
-+
-+ memcpy(&mac.sa_data, priv->mac, ETH_ALEN);
-+ if (!is_valid_ether_addr(mac.sa_data)) {
-+ pr_warn("net-xrx200: invalid MAC, using random\n");
-+ eth_random_addr(mac.sa_data);
-+ dev->addr_assign_type |= NET_ADDR_RANDOM;
-+ }
-+
-+ err = eth_mac_addr(dev, &mac);
-+ if (err)
-+ goto err_netdev;
-+
-+ for (i = 0; i < priv->num_port; i++)
-+ if (xrx200_mdio_probe(dev, &priv->port[i]))
-+ pr_warn("xrx200-mdio: probing phy of port %d failed\n",
-+ priv->port[i].num);
-+
-+ return 0;
-+
-+err_netdev:
-+ unregister_netdev(dev);
-+ free_netdev(dev);
-+ return err;
-+}
-+
-+static void xrx200_pci_microcode(void)
-+{
-+ int i;
-+
-+ ltq_switch_w32_mask(PCE_TBL_CFG_ADDR_MASK | PCE_TBL_CFG_ADWR_MASK,
-+ PCE_TBL_CFG_ADWR, PCE_TBL_CTRL);
-+ ltq_switch_w32(0, PCE_TBL_MASK);
-+
-+ for (i = 0; i < ARRAY_SIZE(pce_microcode); i++) {
-+ ltq_switch_w32(i, PCE_TBL_ADDR);
-+ ltq_switch_w32(pce_microcode[i].val[3], PCE_TBL_VAL(0));
-+ ltq_switch_w32(pce_microcode[i].val[2], PCE_TBL_VAL(1));
-+ ltq_switch_w32(pce_microcode[i].val[1], PCE_TBL_VAL(2));
-+ ltq_switch_w32(pce_microcode[i].val[0], PCE_TBL_VAL(3));
-+
-+ // start the table access:
-+ ltq_switch_w32_mask(0, PCE_TBL_BUSY, PCE_TBL_CTRL);
-+ while (ltq_switch_r32(PCE_TBL_CTRL) & PCE_TBL_BUSY);
-+ }
-+
-+ /* tell the switch that the microcode is loaded */
-+ ltq_switch_w32_mask(0, BIT(3), PCE_GCTRL_REG(0));
-+}
-+
-+static void xrx200_hw_init(struct xrx200_hw *hw)
-+{
-+ int i;
-+
-+ /* enable clock gate */
-+ clk_enable(hw->clk);
-+
-+ /*
-+ * TODO: we should really disbale all phys/miis here and explicitly
-+ * enable them in the device secific init function
-+ */
-+
-+ /* disable port fetch/store dma */
-+ for (i = 0; i < 7; i++ ) {
-+ ltq_switch_w32(0, FDMA_PCTRLx(i));
-+ ltq_switch_w32(0, SDMA_PCTRLx(i));
-+ }
-+
-+ /* enable Switch */
-+ ltq_mdio_w32_mask(0, MDIO_GLOB_ENABLE, MDIO_GLOB);
-+
-+ /* load the pce microcode */
-+ xrx200_pci_microcode();
-+
-+ /* Default unknown Broadcat/Multicast/Unicast port maps */
-+ ltq_switch_w32(0x7f, PCE_PMAP1);
-+ ltq_switch_w32(0x7f, PCE_PMAP2);
-+ ltq_switch_w32(0x7f, PCE_PMAP3);
-+
-+ /* RMON Counter Enable for all physical ports */
-+ for (i = 0; i < 7; i++)
-+ ltq_switch_w32(0x1, BM_PCFG(i));
-+
-+ /* disable auto polling */
-+ ltq_mdio_w32(0x0, MDIO_CLK_CFG0);
-+
-+ /* enable port statistic counters */
-+ for (i = 0; i < 7; i++)
-+ ltq_switch_w32(0x1, BM_PCFGx(i));
-+
-+ /* set IPG to 12 */
-+ ltq_pmac_w32_mask(PMAC_IPG_MASK, 0xb, PMAC_RX_IPG);
-+
-+#ifdef SW_ROUTING
-+ /* enable status header, enable CRC */
-+ ltq_pmac_w32_mask(0,
-+ PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS | PMAC_HD_CTL_AC,
-+ PMAC_HD_CTL);
-+#else
-+ /* disable status header, enable CRC */
-+ ltq_pmac_w32_mask(PMAC_HD_CTL_AST | PMAC_HD_CTL_RXSH | PMAC_HD_CTL_AS,
-+ PMAC_HD_CTL_AC,
-+ PMAC_HD_CTL);
-+#endif
-+
-+ /* enable port fetch/store dma */
-+ for (i = 0; i < 7; i++ ) {
-+ ltq_switch_w32_mask(0, 0x01, FDMA_PCTRLx(i));
-+ ltq_switch_w32_mask(0, 0x01, SDMA_PCTRLx(i));
-+ ltq_switch_w32_mask(0, PCE_INGRESS, PCE_PCTRL_REG(i, 0));
-+ }
-+
-+ /* enable special tag insertion on cpu port */
-+ ltq_switch_w32_mask(0, 0x02, FDMA_PCTRLx(6));
-+}
-+
-+static void xrx200_hw_cleanup(struct xrx200_hw *hw)
-+{
-+ int i;
-+
-+ /* disable the switch */
-+ ltq_mdio_w32_mask(MDIO_GLOB_ENABLE, 0, MDIO_GLOB);
-+
-+ /* free the channels and IRQs */
-+ for (i = 0; i < 2; i++) {
-+ ltq_dma_free(&hw->chan[i].dma);
-+ if (hw->chan[i].dma.irq)
-+ free_irq(hw->chan[i].dma.irq, hw);
-+ }
-+
-+ /* free the allocated RX ring */
-+ for (i = 0; i < LTQ_DESC_NUM; i++)
-+ dev_kfree_skb_any(hw->chan[XRX200_DMA_RX].skb[i]);
-+
-+ /* clear the mdio bus */
-+ mdiobus_unregister(hw->mii_bus);
-+ mdiobus_free(hw->mii_bus);
-+
-+ /* release the clock */
-+ clk_disable(hw->clk);
-+ clk_put(hw->clk);
-+}
-+
-+static int xrx200_of_mdio(struct xrx200_hw *hw, struct device_node *np)
-+{
-+ hw->mii_bus = mdiobus_alloc();
-+ if (!hw->mii_bus)
-+ return -ENOMEM;
-+
-+ hw->mii_bus->read = xrx200_mdio_rd;
-+ hw->mii_bus->write = xrx200_mdio_wr;
-+ hw->mii_bus->name = "lantiq,xrx200-mdio";
-+ snprintf(hw->mii_bus->id, MII_BUS_ID_SIZE, "%x", 0);
-+
-+ if (of_mdiobus_register(hw->mii_bus, np)) {
-+ mdiobus_free(hw->mii_bus);
-+ return -ENXIO;
-+ }
-+
-+ return 0;
-+}
-+
-+static void xrx200_of_port(struct xrx200_priv *priv, struct device_node *port)
-+{
-+ const __be32 *addr, *id = of_get_property(port, "reg", NULL);
-+ struct xrx200_port *p = &priv->port[priv->num_port];
-+
-+ if (!id)
-+ return;
-+
-+ memset(p, 0, sizeof(struct xrx200_port));
-+ p->phy_node = of_parse_phandle(port, "phy-handle", 0);
-+ addr = of_get_property(p->phy_node, "reg", NULL);
-+ if (!addr)
-+ return;
-+
-+ p->num = *id;
-+ p->phy_addr = *addr;
-+ p->phy_if = of_get_phy_mode(port);
-+ if (p->phy_addr > 0x10)
-+ p->flags = XRX200_PORT_TYPE_MAC;
-+ else
-+ p->flags = XRX200_PORT_TYPE_PHY;
-+ priv->num_port++;
-+
-+ /* is this port a wan port ? */
-+ if (priv->wan)
-+ priv->hw->wan_map |= BIT(p->num);
-+
-+ /* store the port id in the hw struct so we can map ports -> devices */
-+ priv->hw->port_map[p->num] = priv->hw->num_devs;
-+}
-+
-+static const struct net_device_ops xrx200_netdev_ops = {
-+ .ndo_init = xrx200_init,
-+ .ndo_open = xrx200_open,
-+ .ndo_stop = xrx200_close,
-+ .ndo_start_xmit = xrx200_start_xmit,
-+ .ndo_set_mac_address = eth_mac_addr,
-+ .ndo_validate_addr = eth_validate_addr,
-+ .ndo_change_mtu = eth_change_mtu,
-+ .ndo_get_stats = xrx200_get_stats,
-+ .ndo_tx_timeout = xrx200_tx_timeout,
-+};
-+
-+static void xrx200_of_iface(struct xrx200_hw *hw, struct device_node *iface)
-+{
-+ struct xrx200_priv *priv;
-+ struct device_node *port;
-+ const __be32 *wan;
-+
-+ /* alloc the network device */
-+ hw->devs[hw->num_devs] = alloc_etherdev(sizeof(struct xrx200_priv));
-+ if (!hw->devs[hw->num_devs])
-+ return;
-+
-+ /* setup the network device */
-+ strcpy(hw->devs[hw->num_devs]->name, "eth%d");
-+ hw->devs[hw->num_devs]->netdev_ops = &xrx200_netdev_ops;
-+ hw->devs[hw->num_devs]->watchdog_timeo = XRX200_TX_TIMEOUT;
-+ hw->devs[hw->num_devs]->needed_headroom = XRX200_HEADROOM;
-+
-+ /* setup our private data */
-+ priv = netdev_priv(hw->devs[hw->num_devs]);
-+ priv->hw = hw;
-+ priv->mac = of_get_mac_address(iface);
-+ priv->id = hw->num_devs;
-+
-+ /* is this the wan interface ? */
-+ wan = of_get_property(iface, "lantiq,wan", NULL);
-+ if (wan && (*wan == 1))
-+ priv->wan = 1;
-+
-+ /* load the ports that are part of the interface */
-+ for_each_child_of_node(iface, port)
-+ if (of_device_is_compatible(port, "lantiq,xrx200-pdi-port"))
-+ xrx200_of_port(priv, port);
-+
-+ /* register the actual device */
-+ if (!register_netdev(hw->devs[hw->num_devs]))
-+ hw->num_devs++;
-+}
-+
-+static struct xrx200_hw xrx200_hw;
-+
-+static int __devinit xrx200_probe(struct platform_device *pdev)
-+{
-+ struct resource *res[4];
-+ struct device_node *mdio_np, *iface_np;
-+ int i;
-+
-+ /* load the memory ranges */
-+ for (i = 0; i < 4; i++) {
-+ res[i] = platform_get_resource(pdev, IORESOURCE_MEM, i);
-+ if (!res[i]) {
-+ dev_err(&pdev->dev, "failed to get resources\n");
-+ return -ENOENT;
-+ }
-+ }
-+ xrx200_switch_membase = devm_request_and_ioremap(&pdev->dev, res[0]);
-+ xrx200_mdio_membase = devm_request_and_ioremap(&pdev->dev, res[1]);
-+ xrx200_mii_membase = devm_request_and_ioremap(&pdev->dev, res[2]);
-+ xrx200_pmac_membase = devm_request_and_ioremap(&pdev->dev, res[3]);
-+ if (!xrx200_switch_membase || !xrx200_mdio_membase ||
-+ !xrx200_mii_membase || !xrx200_pmac_membase) {
-+ dev_err(&pdev->dev, "failed to request and remap io ranges \n");
-+ return -ENOMEM;
-+ }
-+
-+ /* get the clock */
-+ xrx200_hw.clk = clk_get(&pdev->dev, NULL);
-+ if (IS_ERR(xrx200_hw.clk)) {
-+ dev_err(&pdev->dev, "failed to get clock\n");
-+ return PTR_ERR(xrx200_hw.clk);
-+ }
-+
-+ /* bring up the dma engine and IP core */
-+ spin_lock_init(&xrx200_hw.lock);
-+ xrx200_dma_init(&xrx200_hw);
-+ xrx200_hw_init(&xrx200_hw);
-+
-+ /* bring up the mdio bus */
-+ mdio_np = of_find_compatible_node(pdev->dev.of_node, NULL,
-+ "lantiq,xrx200-mdio");
-+ if (mdio_np)
-+ if (xrx200_of_mdio(&xrx200_hw, mdio_np))
-+ dev_err(&pdev->dev, "mdio probe failed\n");
-+
-+ /* load the interfaces */
-+ for_each_child_of_node(pdev->dev.of_node, iface_np)
-+ if (of_device_is_compatible(iface_np, "lantiq,xrx200-pdi")) {
-+ if (xrx200_hw.num_devs < XRX200_MAX_DEV)
-+ xrx200_of_iface(&xrx200_hw, iface_np);
-+ else
-+ dev_err(&pdev->dev,
-+ "only %d interfaces allowed\n",
-+ XRX200_MAX_DEV);
-+ }
-+
-+ if (!xrx200_hw.num_devs) {
-+ xrx200_hw_cleanup(&xrx200_hw);
-+ dev_err(&pdev->dev, "failed to load interfaces\n");
-+ return -ENOENT;
-+ }
-+
-+ /* set wan port mask */
-+ ltq_pmac_w32(xrx200_hw.wan_map, PMAC_EWAN);
-+
-+ for (i = 0; i < xrx200_hw.num_devs; i++) {
-+ xrx200_hw.chan[XRX200_DMA_RX].devs[i] = xrx200_hw.devs[i];
-+ xrx200_hw.chan[XRX200_DMA_TX].devs[i] = xrx200_hw.devs[i];
-+ }
-+
-+ /* setup NAPI */
-+ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev);
-+ init_dummy_netdev(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev);
-+ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_RX].dummy_dev,
-+ &xrx200_hw.chan[XRX200_DMA_RX].napi, xrx200_poll_rx, 32);
-+ netif_napi_add(&xrx200_hw.chan[XRX200_DMA_TX].dummy_dev,
-+ &xrx200_hw.chan[XRX200_DMA_TX].napi, xrx200_poll_tx, 8);
-+
-+ platform_set_drvdata(pdev, &xrx200_hw);
-+
-+ return 0;
-+}
-+
-+static int __devexit xrx200_remove(struct platform_device *pdev)
-+{
-+ struct net_device *dev = platform_get_drvdata(pdev);
-+ struct xrx200_priv *priv;
-+
-+ if (!dev)
-+ return 0;
-+
-+ priv = netdev_priv(dev);
-+
-+ /* free stack related instances */
-+ netif_stop_queue(dev);
-+ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_RX].napi);
-+ netif_napi_del(&xrx200_hw.chan[XRX200_DMA_TX].napi);
-+
-+ /* shut down hardware */
-+ xrx200_hw_cleanup(&xrx200_hw);
-+
-+ /* remove the actual device */
-+ unregister_netdev(dev);
-+ free_netdev(dev);
-+
-+ return 0;
-+}
-+
-+static const struct of_device_id xrx200_match[] = {
-+ { .compatible = "lantiq,xrx200-net" },
-+ {},
-+};
-+MODULE_DEVICE_TABLE(of, xrx200_match);
-+
-+static struct platform_driver xrx200_driver = {
-+ .probe = xrx200_probe,
-+ .remove = __devexit_p(xrx200_remove),
-+ .driver = {
-+ .name = "lantiq,xrx200-net",
-+ .of_match_table = xrx200_match,
-+ .owner = THIS_MODULE,
-+ },
-+};
-+
-+module_platform_driver(xrx200_driver);
-+
-+MODULE_AUTHOR("John Crispin <blogic@openwrt.org>");
-+MODULE_DESCRIPTION("Lantiq SoC XRX200 ethernet");
-+MODULE_LICENSE("GPL");
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0113-EASY80920-dts-file.patch b/target/linux/lantiq/patches-3.6/0113-EASY80920-dts-file.patch
deleted file mode 100644
index 72dd3696c0..0000000000
--- a/target/linux/lantiq/patches-3.6/0113-EASY80920-dts-file.patch
+++ /dev/null
@@ -1,539 +0,0 @@
-From b072ba5c8e730b6d6e828cbc7caf99f669667831 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Mon, 22 Oct 2012 12:22:10 +0200
-Subject: [PATCH 113/113] EASY80920 dts file
-
----
- arch/mips/lantiq/Kconfig | 4 +
- arch/mips/lantiq/dts/Makefile | 1 +
- arch/mips/lantiq/dts/easy80920.dts | 369 ++++++++++++++++++++++++++++++++++++
- arch/mips/lantiq/dts/vr9.dtsi | 116 ++++++++++++
- 4 files changed, 490 insertions(+)
- create mode 100644 arch/mips/lantiq/dts/easy80920.dts
- create mode 100644 arch/mips/lantiq/dts/vr9.dtsi
-
-diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
-index d84f361..c9d0984 100644
---- a/arch/mips/lantiq/Kconfig
-+++ b/arch/mips/lantiq/Kconfig
-@@ -30,6 +30,10 @@ choice
- config DT_EASY50712
- bool "Easy50712"
- depends on SOC_XWAY
-+
-+config DT_EASY80920
-+ bool "Easy80920"
-+ depends on SOC_XWAY
- endchoice
-
- config PCI_LANTIQ
-diff --git a/arch/mips/lantiq/dts/Makefile b/arch/mips/lantiq/dts/Makefile
-index 674fca4..0876c97 100644
---- a/arch/mips/lantiq/dts/Makefile
-+++ b/arch/mips/lantiq/dts/Makefile
-@@ -1,4 +1,5 @@
- obj-$(CONFIG_DT_EASY50712) := easy50712.dtb.o
-+obj-$(CONFIG_DT_EASY80920) := easy80920.dtb.o
-
- $(obj)/%.dtb: $(obj)/%.dts
- $(call if_changed,dtc)
-diff --git a/arch/mips/lantiq/dts/easy80920.dts b/arch/mips/lantiq/dts/easy80920.dts
-new file mode 100644
-index 0000000..703e768
---- /dev/null
-+++ b/arch/mips/lantiq/dts/easy80920.dts
-@@ -0,0 +1,369 @@
-+/dts-v1/;
-+
-+
-+/include/ "vr9.dtsi"
-+
-+/ {
-+ chosen {
-+ bootargs = "console=ttyLTQ0,115200 init=/etc/preinit";
-+ };
-+
-+ memory@0 {
-+ reg = <0x0 0x4000000>;
-+ };
-+
-+ fpi@10000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,fpi", "simple-bus";
-+ ranges = <0x0 0x10000000 0xEEFFFFF>;
-+ reg = <0x10000000 0xEF00000>;
-+
-+ localbus@0 {
-+ #address-cells = <2>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,localbus", "simple-bus";
-+
-+ ranges = <0 0 0x0 0x3ffffff>;
-+ nor-boot@0 {
-+ compatible = "lantiq,nor";
-+ bank-width = <2>;
-+ reg = <0 0x0 0x2000000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "uboot";
-+ reg = <0x00000 0x10000>;
-+ };
-+
-+ partition@10000 {
-+ label = "uboot_env";
-+ reg = <0x10000 0x10000>;
-+ };
-+
-+ partition@20000 {
-+ label = "linux";
-+ reg = <0x20000 0x7e0000>;
-+ };
-+ };
-+
-+ /*ranges = <0 0 0x4000000 0x3ffffff>;
-+ nand-parts@0 {
-+ compatible = "gen_nand", "lantiq,nand-xway";
-+ lantiq,cs = <1>;
-+ bank-width = <2>;
-+ reg = <0 0x0 0x2000000>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "uboot";
-+ reg = <0x00000 0x40000>;
-+ };
-+
-+ partition@10000 {
-+ label = "uboot_env";
-+ reg = <0x40000 0x40000>;
-+ };
-+
-+ partition@20000 {
-+ label = "linux";
-+ reg = <0x80000 0x3f80000>;
-+ };
-+ };*/
-+ };
-+
-+ sflash@E100800 {
-+ compatible = "lantiq,sflash";
-+ reg = <0xE100800 0x100>;
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+
-+ partition@0 {
-+ label = "uboot";
-+ reg = <0x00000 0x10000>;
-+ };
-+
-+ partition@10000 {
-+ label = "uboot_env";
-+ reg = <0x10000 0x10000>;
-+ };
-+
-+ partition@20000 {
-+ label = "linux";
-+ reg = <0x20000 0x1d0000>;
-+ };
-+ };
-+
-+ gpio: pinmux@E100B10 {
-+ compatible = "lantiq,pinctrl-xr9";
-+ pinctrl-names = "default";
-+ pinctrl-0 = <&state_default>;
-+
-+ interrupt-parent = <&icu0>;
-+ interrupts = <166 135 66 40 41 42 38>;
-+
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+ reg = <0xE100B10 0xA0>;
-+
-+ state_default: pinmux {
-+ stp {
-+ lantiq,groups = "stp";
-+ lantiq,function = "stp";
-+ };
-+ /*spi {
-+ lantiq,groups = "spi", "spi_cs4";
-+ lantiq,function = "spi";
-+ };*/
-+ nand {
-+ lantiq,groups = "nand cle", "nand ale",
-+ "nand rd", "nand rdy";
-+ lantiq,function = "ebu";
-+ };
-+ mdio {
-+ lantiq,groups = "mdio";
-+ lantiq,function = "mdio";
-+ };
-+ pci {
-+ lantiq,groups = "gnt1", "req1";
-+ lantiq,function = "pci";
-+ };
-+ exin {
-+ lantiq,groups = "exin3";
-+ lantiq,function = "exin";
-+ };
-+ conf_out {
-+ lantiq,pins = "io24", "io13", "io49", /* nand cle, ale and rd */
-+ "io4", "io5", "io6", /* stp */
-+ "io17", "io18", /* spi dout & clk */
-+ "io21", /* pci-rst */
-+ "io38"; /* pcie-rst */
-+ lantiq,open-drain;
-+ lantiq,pull = <0>;
-+ };
-+ conf_in {
-+ lantiq,pins = "io39", /* exin3 */
-+ "io48"; /* nand rdy */
-+ lantiq,pull = <2>;
-+ };
-+ };
-+ };
-+
-+ eth@0xE108000 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "lantiq,xrx200-net";
-+ reg = < 0xE108000 0x3000 /* switch */
-+ 0xE10B100 0x70 /* mdio */
-+ 0xE10B1D8 0x30 /* mii */
-+ 0xE10B308 0x30 /* pmac */
-+ >;
-+ interrupt-parent = <&icu0>;
-+ interrupts = <73 72>;
-+
-+ lan: interface@0 {
-+ compatible = "lantiq,xrx200-pdi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <0>;
-+ mac-address = [ 00 11 22 33 44 55 ];
-+
-+ ethernet@0 {
-+ compatible = "lantiq,xrx200-pdi-port";
-+ reg = <0>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy0>;
-+ };
-+ ethernet@1 {
-+ compatible = "lantiq,xrx200-pdi-port";
-+ reg = <1>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy1>;
-+ };
-+ ethernet@2 {
-+ compatible = "lantiq,xrx200-pdi-port";
-+ reg = <2>;
-+ phy-mode = "gmii";
-+ phy-handle = <&phy11>;
-+ };
-+ ethernet@4 {
-+ compatible = "lantiq,xrx200-pdi-port";
-+ reg = <4>;
-+ phynmode0 = "gmii";
-+ phy-handle = <&phy13>;
-+ };
-+ };
-+
-+ wan: interface@1 {
-+ compatible = "lantiq,xrx200-pdi";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ reg = <1>;
-+ mac-address = [ 00 11 22 33 44 56 ];
-+
-+ ethernet@5 {
-+ compatible = "lantiq,xrx200-pdi-port";
-+ reg = <5>;
-+ phy-mode = "rgmii";
-+ phy-handle = <&phy5>;
-+ };
-+ };
-+
-+ mdio@0 {
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ compatible = "lantiq,xrx200-mdio";
-+ phy0: ethernet-phy@0 {
-+ reg = <0x0>;
-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+ lantiq,c45-reg-init = <1 0 0 0>;
-+ };
-+ phy1: ethernet-phy@1 {
-+ reg = <0x1>;
-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+ lantiq,c45-reg-init = <1 0 0 0>;
-+ };
-+ phy5: ethernet-phy@5 {
-+ reg = <0x5>;
-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+ lantiq,c45-reg-init = <1 0 0 0>;
-+ };
-+ phy11: ethernet-phy@11 {
-+ reg = <0x11>;
-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+ lantiq,c45-reg-init = <1 0 0 0>;
-+ };
-+ phy13: ethernet-phy@13 {
-+ reg = <0x13>;
-+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
-+ lantiq,c45-reg-init = <1 0 0 0>;
-+ };
-+ };
-+ };
-+
-+ stp: stp@E100BB0 {
-+ compatible = "lantiq,gpio-stp-xway";
-+ reg = <0xE100BB0 0x40>;
-+ #gpio-cells = <2>;
-+ gpio-controller;
-+
-+ lantiq,shadow = <0xffff>;
-+ lantiq,groups = <0x7>;
-+ lantiq,dsl = <0x3>;
-+ lantiq,phy1 = <0x7>;
-+ lantiq,phy2 = <0x7>;
-+ /* lantiq,rising; */
-+ };
-+
-+ pci@E105400 {
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ compatible = "lantiq,pci-xway";
-+ bus-range = <0x0 0x0>;
-+ ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
-+ 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
-+ reg = <0x7000000 0x8000 /* config space */
-+ 0xE105400 0x400>; /* pci bridge */
-+ lantiq,bus-clock = <33333333>;
-+ /*lantiq,external-clock;*/
-+ lantiq,delay-hi = <0>; /* 0ns delay */
-+ lantiq,delay-lo = <0>; /* 0.0ns delay */
-+ interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
-+ interrupt-map = <
-+ 0x7000 0 0 1 &icu0 29 1 // slot 14, irq 29
-+ >;
-+ gpios-reset = <&gpio 21 0>;
-+ req-mask = <0x1>; /* GNT1 */
-+ };
-+ };
-+
-+ ifxhcd {
-+ compatible = "lantiq,ifxhcd";
-+ interrupt-parent = <&icu0>;
-+ interrupts = <62 91>;
-+ };
-+
-+ gphy-xrx200 {
-+ compatible = "lantiq,phy-xrx200";
-+ firmware = "lantiq/vr9_phy11g_a2x.bin";
-+ phys = [ 00 01 ];
-+ };
-+
-+ gpio-keys-polled {
-+ compatible = "gpio-keys-polled";
-+ #address-cells = <1>;
-+ #size-cells = <0>;
-+ poll-interval = <100>;
-+ reset {
-+ label = "Reset";
-+ gpios = <&gpio 7 0>;
-+ linux,code = <0x100>;
-+ };
-+ paging {
-+ label = "paging";
-+ gpios = <&gpio 11 1>;
-+ linux,code = <0x100>;
-+ };
-+ };
-+
-+/* gpio-keys {
-+ compatible = "gpio-keys";
-+ wps {
-+ gpios = <&gpio 39 0>;
-+ linux,code = <0x100>;
-+ };
-+ };*/
-+
-+ gpio-leds {
-+ compatible = "gpio-leds";
-+
-+ led0 {
-+ label = "led0";
-+ gpios = <&stp 9 0>;
-+ default-state = "on";
-+ };
-+ warning {
-+ label = "warning";
-+ gpios = <&stp 22 0>;
-+ default-state = "on";
-+ };
-+ fxs1 {
-+ label = "fxs1";
-+ gpios = <&stp 21 0>;
-+ default-state = "on";
-+ };
-+ fxs2 {
-+ label = "fxs2";
-+ gpios = <&stp 20 0>;
-+ default-state = "on";
-+ };
-+ fxo {
-+ label = "fxo";
-+ gpios = <&stp 19 0>;
-+ default-state = "on";
-+ };
-+ usb1 {
-+ label = "usb1";
-+ gpios = <&stp 18 0>;
-+ default-state = "on";
-+ };
-+ usb2 {
-+ label = "usb2";
-+ gpios = <&stp 15 0>;
-+ default-state = "on";
-+ };
-+ sd {
-+ label = "sd";
-+ gpios = <&stp 14 0>;
-+ default-state = "on";
-+ };
-+ wps {
-+ label = "wps";
-+ gpios = <&stp 12 0>;
-+ default-state = "on";
-+ };
-+ };
-+};
-diff --git a/arch/mips/lantiq/dts/vr9.dtsi b/arch/mips/lantiq/dts/vr9.dtsi
-new file mode 100644
-index 0000000..d3adb58
---- /dev/null
-+++ b/arch/mips/lantiq/dts/vr9.dtsi
-@@ -0,0 +1,116 @@
-+/ {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,xway", "lantiq,vr9";
-+
-+ cpus {
-+ cpu@0 {
-+ compatible = "mips,mips34Kc";
-+ };
-+ };
-+
-+ biu@1F800000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,biu", "simple-bus";
-+ reg = <0x1F800000 0x800000>;
-+ ranges = <0x0 0x1F800000 0x7FFFFF>;
-+
-+ icu0: icu@80200 {
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ compatible = "lantiq,icu";
-+ reg = <0x80200 0x28
-+ 0x80228 0x28
-+ 0x80250 0x28
-+ 0x80278 0x28
-+ 0x802a0 0x28>;
-+ };
-+
-+ watchdog@803F0 {
-+ compatible = "lantiq,wdt";
-+ reg = <0x803F0 0x10>;
-+ };
-+ };
-+
-+ sram@1F000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,sram";
-+ reg = <0x1F000000 0x800000>;
-+ ranges = <0x0 0x1F000000 0x7FFFFF>;
-+
-+ eiu0: eiu@101000 {
-+ compatible = "lantiq,eiu";
-+ #interrupt-cells = <1>;
-+ interrupt-controller;
-+ interrupt-parent;
-+ reg = <0x101000 0x1000>;
-+ lantiq,count = <6>;
-+ };
-+
-+ pmu0: pmu@102000 {
-+ compatible = "lantiq,pmu-xway";
-+ reg = <0x102000 0x1000>;
-+ };
-+
-+ cgu0: cgu@103000 {
-+ compatible = "lantiq,cgu-xway";
-+ reg = <0x103000 0x1000>;
-+ #clock-cells = <1>;
-+ };
-+
-+ rcu0: rcu@203000 {
-+ compatible = "lantiq,rcu-xway";
-+ reg = <0x203000 0x1000>;
-+ /* irq for thermal sensor */
-+ interrupt-parent = <&icu0>;
-+ interrupts = <115>;
-+ };
-+ };
-+
-+ fpi@10000000 {
-+ #address-cells = <1>;
-+ #size-cells = <1>;
-+ compatible = "lantiq,fpi", "simple-bus";
-+ ranges = <0x0 0x10000000 0xEEFFFFF>;
-+ reg = <0x10000000 0xEF00000>;
-+
-+ gptu@E100A00 {
-+ compatible = "lantiq,gptu-xway";
-+ reg = <0xE100A00 0x100>;
-+ interrupt-parent = <&icu0>;
-+ interrupts = <126 127 128 129 130 131>;
-+ };
-+
-+ asc1: serial@E100C00 {
-+ compatible = "lantiq,asc";
-+ reg = <0xE100C00 0x400>;
-+ interrupt-parent = <&icu0>;
-+ interrupts = <112 113 114>;
-+ };
-+
-+ dma0: dma@E104100 {
-+ compatible = "lantiq,dma-xway";
-+ reg = <0xE104100 0x800>;
-+ };
-+
-+ ebu0: ebu@E105300 {
-+ compatible = "lantiq,ebu-xway";
-+ reg = <0xE105300 0x100>;
-+ };
-+
-+ pci0: pci@E105400 {
-+ #address-cells = <3>;
-+ #size-cells = <2>;
-+ #interrupt-cells = <1>;
-+ compatible = "lantiq,pci-xway";
-+ bus-range = <0x0 0x0>;
-+ ranges = <0x2000000 0 0x8000000 0x8000000 0 0x2000000 /* pci memory */
-+ 0x1000000 0 0x00000000 0xAE00000 0 0x200000>; /* io space */
-+ reg = <0x7000000 0x8000 /* config space */
-+ 0xE105400 0x400>; /* pci bridge */
-+ };
-+
-+ };
-+};
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0200-MIPS-dtb-image-hack.patch b/target/linux/lantiq/patches-3.6/0200-MIPS-dtb-image-hack.patch
deleted file mode 100644
index 0c6fa51e1e..0000000000
--- a/target/linux/lantiq/patches-3.6/0200-MIPS-dtb-image-hack.patch
+++ /dev/null
@@ -1,26 +0,0 @@
-From 5dd6dd9cddc0327b638d15f8c4f489fee6257fb0 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 2 Nov 2012 15:40:08 +0100
-Subject: [PATCH 200/201] MIPS: dtb image hack
-
----
- arch/mips/kernel/head.S | 3 +++
- 1 file changed, 3 insertions(+)
-
-diff --git a/arch/mips/kernel/head.S b/arch/mips/kernel/head.S
-index ea695d9..be87456 100644
---- a/arch/mips/kernel/head.S
-+++ b/arch/mips/kernel/head.S
-@@ -141,6 +141,9 @@ FEXPORT(__kernel_entry)
- j kernel_entry
- #endif
-
-+ .ascii "OWRTDTB:"
-+ EXPORT(__image_dtb)
-+ .fill 0x4000
- __REF
-
- NESTED(kernel_entry, 16, sp) # kernel entry point
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0201-lantiq-dtb-image-hack.patch b/target/linux/lantiq/patches-3.6/0201-lantiq-dtb-image-hack.patch
deleted file mode 100644
index b2f781e557..0000000000
--- a/target/linux/lantiq/patches-3.6/0201-lantiq-dtb-image-hack.patch
+++ /dev/null
@@ -1,58 +0,0 @@
-From a86a157eb87fb21a62205a5382842c2f331fb473 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 2 Nov 2012 15:40:34 +0100
-Subject: [PATCH 201/201] lantiq: dtb image hack
-
----
- arch/mips/lantiq/Kconfig | 12 ------------
- arch/mips/lantiq/prom.c | 4 +++-
- 2 files changed, 3 insertions(+), 13 deletions(-)
-
-diff --git a/arch/mips/lantiq/Kconfig b/arch/mips/lantiq/Kconfig
-index c9d0984..bef648f 100644
---- a/arch/mips/lantiq/Kconfig
-+++ b/arch/mips/lantiq/Kconfig
-@@ -24,18 +24,6 @@ config SOC_FALCON
-
- endchoice
-
--choice
-- prompt "Devicetree"
--
--config DT_EASY50712
-- bool "Easy50712"
-- depends on SOC_XWAY
--
--config DT_EASY80920
-- bool "Easy80920"
-- depends on SOC_XWAY
--endchoice
--
- config PCI_LANTIQ
- bool "PCI Support"
- depends on SOC_XWAY && PCI
-diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c
-index 9f9e875..72b183a 100644
---- a/arch/mips/lantiq/prom.c
-+++ b/arch/mips/lantiq/prom.c
-@@ -57,6 +57,8 @@ static void __init prom_init_cmdline(void)
- }
- }
-
-+extern struct boot_param_header __image_dtb;
-+
- void __init plat_mem_setup(void)
- {
- ioport_resource.start = IOPORT_RESOURCE_START;
-@@ -70,7 +72,7 @@ void __init plat_mem_setup(void)
- * Load the builtin devicetree. This causes the chosen node to be
- * parsed resulting in our memory appearing
- */
-- __dt_setup_arch(&__dtb_start);
-+ __dt_setup_arch(&__image_dtb);
- }
-
- void __init device_tree_init(void)
---
-1.7.10.4
-
diff --git a/target/linux/lantiq/patches-3.6/0300-owrt-mtd-split.patch b/target/linux/lantiq/patches-3.6/0300-owrt-mtd-split.patch
deleted file mode 100644
index 4f69ef96b3..0000000000
--- a/target/linux/lantiq/patches-3.6/0300-owrt-mtd-split.patch
+++ /dev/null
@@ -1,230 +0,0 @@
-From 2a295753a10823a47542c779a25bbb1f52c71281 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:13 +0200
-Subject: [PATCH 19/25] owrt mtd split
-
----
- .../mips/include/asm/mach-lantiq/xway/lantiq_soc.h | 1 +
- arch/mips/lantiq/setup.c | 7 +
- drivers/mtd/Kconfig | 4 +
- drivers/mtd/mtdpart.c | 173 +++++++++++++++++++-
- 4 files changed, 184 insertions(+), 1 deletions(-)
-
-diff --git a/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h b/arch/mips/include/asm/mach-lantiq/xway/lantiq_soc.h
-index 1ec8f2a..1ff93cc 100644
-diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
-index 982a98b..e2f3f3e 100644
---- a/drivers/mtd/Kconfig
-+++ b/drivers/mtd/Kconfig
-@@ -31,6 +31,10 @@ config MTD_ROOTFS_SPLIT
- bool "Automatically split 'rootfs' partition for squashfs"
- default y
-
-+config MTD_UIMAGE_SPLIT
-+ bool "Automatically split 'linux' partition into 'kernel' and 'rootfs'"
-+ default y
-+
- config MTD_REDBOOT_PARTS
- tristate "RedBoot partition table parsing"
- ---help---
-diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
-index 855b70b..93711e2 100644
---- a/drivers/mtd/mtdpart.c
-+++ b/drivers/mtd/mtdpart.c
-@@ -867,6 +867,168 @@ static int refresh_rootfs_split(struct mtd_info *mtd)
- }
- #endif /* CONFIG_MTD_ROOTFS_SPLIT */
-
-+#ifdef CONFIG_MTD_UIMAGE_SPLIT
-+static unsigned long find_uimage_size(struct mtd_info *mtd,
-+ unsigned long offset)
-+{
-+#define UBOOT_MAGIC 0x56190527
-+ unsigned long magic = 0;
-+ unsigned long temp;
-+ size_t len;
-+ int ret;
-+
-+ ret = mtd_read(mtd, offset, 4, &len, (void *)&magic);
-+ if (ret || len != sizeof(magic))
-+ return 0;
-+
-+ if (le32_to_cpu(magic) != UBOOT_MAGIC)
-+ return 0;
-+
-+ ret = mtd_read(mtd, offset + 12, 4, &len, (void *)&temp);
-+ if (ret || len != sizeof(temp))
-+ return 0;
-+
-+ return temp + 0x40;
-+}
-+
-+static unsigned long find_eva_size(struct mtd_info *mtd,
-+ unsigned long offset)
-+{
-+#define EVA_MAGIC 0xfeed1281
-+ unsigned long magic = 0;
-+ unsigned long temp;
-+ size_t len;
-+ int ret;
-+
-+ ret = mtd_read(mtd, offset, 4, &len, (void *)&magic);
-+ if (ret || len != sizeof(magic))
-+ return 0;
-+
-+ if (le32_to_cpu(magic) != EVA_MAGIC)
-+ return 0;
-+
-+ ret = mtd_read(mtd, offset + 4, 4, &len, (void *)&temp);
-+ if (ret || len != sizeof(temp))
-+ return 0;
-+
-+ /* add eva header size */
-+ temp = le32_to_cpu(temp) + 0x18;
-+
-+ temp &= ~0xffff;
-+ temp += 0x10000;
-+ return temp;
-+}
-+
-+static int detect_squashfs_partition(struct mtd_info *mtd, unsigned long offset)
-+{
-+ unsigned long temp;
-+ size_t len;
-+ int ret;
-+
-+ ret = mtd_read(mtd, offset, 4, &len, (void *)&temp);
-+ if (ret || len != sizeof(temp))
-+ return 0;
-+
-+
-+ return le32_to_cpu(temp) == SQUASHFS_MAGIC;
-+}
-+
-+static int detect_eva_squashfs_partition(struct mtd_info *mtd, unsigned long offset)
-+{
-+ unsigned long temp;
-+ size_t len;
-+ int ret;
-+
-+ ret = mtd_read(mtd, offset, 4, &len, (void *)&temp);
-+ if (ret || len != sizeof(temp))
-+ return 0;
-+
-+ return be32_to_cpu(temp) == SQUASHFS_MAGIC;
-+}
-+
-+static unsigned long find_brnimage_size(struct mtd_info *mtd,
-+ unsigned long offset)
-+{
-+ unsigned long buf[4];
-+ // Assume at most 2MB of kernel image
-+ unsigned long end = offset + (2 << 20);
-+ unsigned long ptr = offset + 0x400 - 12;
-+ size_t len;
-+ int ret;
-+
-+ while (ptr < end) {
-+ long size_min = ptr - 0x400 - 12 - offset;
-+ long size_max = ptr + 12 - offset;
-+ ret = mtd_read(mtd, ptr, 16, &len, (void *)buf);
-+ if (ret || len != 16)
-+ return 0;
-+
-+ if (le32_to_cpu(buf[0]) < size_min ||
-+ le32_to_cpu(buf[0]) > size_max) {
-+ ptr += 0x400;
-+ continue;
-+ }
-+
-+ if (le32_to_cpu(buf[3]) == SQUASHFS_MAGIC)
-+ return ptr + 12 - offset;
-+
-+ ptr += 0x400;
-+ }
-+
-+ return 0;
-+}
-+
-+static int split_uimage(struct mtd_info *mtd,
-+ const struct mtd_partition *part)
-+{
-+ static struct mtd_partition split_partitions[] = {
-+ {
-+ .name = "kernel",
-+ .offset = 0x0,
-+ .size = 0x0,
-+ }, {
-+ .name = "rootfs",
-+ .offset = 0x0,
-+ .size = 0x0,
-+ },
-+ };
-+
-+ split_partitions[0].size = find_uimage_size(mtd, part->offset);
-+ if (!split_partitions[0].size) {
-+ split_partitions[0].size = find_eva_size(mtd, part->offset);
-+ if (!split_partitions[0].size) {
-+ split_partitions[0].size = find_brnimage_size(mtd, part->offset);
-+ if (!split_partitions[0].size) {
-+ printk(KERN_NOTICE "no uImage or brnImage or eva found in linux partition\n");
-+ return -1;
-+ }
-+ }
-+ }
-+
-+ if (detect_eva_squashfs_partition(mtd,
-+ part->offset
-+ + split_partitions[0].size)) {
-+ split_partitions[0].size += 0x100;
-+ pr_info("found eva dummy squashfs behind kernel\n");
-+ } else if (!detect_squashfs_partition(mtd,
-+ part->offset
-+ + split_partitions[0].size)) {
-+ split_partitions[0].size &= ~(mtd->erasesize - 1);
-+ split_partitions[0].size += mtd->erasesize;
-+ } else {
-+ pr_info("found squashfs behind kernel\n");
-+ }
-+
-+ split_partitions[0].offset = part->offset;
-+ split_partitions[1].offset = part->offset + split_partitions[0].size;
-+ split_partitions[1].size = part->size - split_partitions[0].size;
-+
-+ add_mtd_partitions(mtd, split_partitions, 2);
-+
-+ return 0;
-+}
-+#endif
-+
- /*
- * This function, given a master MTD object and a partition table, creates
- * and registers slave MTD objects which are bound to the master according to
-@@ -883,7 +1045,7 @@ int add_mtd_partitions(struct mtd_info *master,
- struct mtd_part *slave;
- uint64_t cur_offset = 0;
- int i;
--#ifdef CONFIG_MTD_ROOTFS_SPLIT
-+#if defined(CONFIG_MTD_ROOTFS_SPLIT) || defined(CONFIG_MTD_UIMAGE_SPLIT)
- int ret;
- #endif
-
-@@ -900,6 +1062,15 @@ int add_mtd_partitions(struct mtd_info *master,
-
- add_mtd_device(&slave->mtd);
-
-+#ifdef CONFIG_MTD_UIMAGE_SPLIT
-+ if (!strcmp(parts[i].name, "linux")) {
-+ ret = split_uimage(master, &parts[i]);
-+
-+ if (ret)
-+ printk(KERN_WARNING "Can't split linux partition\n");
-+ }
-+#endif
-+
- if (!strcmp(parts[i].name, "rootfs")) {
- #ifdef CONFIG_MTD_ROOTFS_ROOT_DEV
- if (ROOT_DEV == 0) {
---
-1.7.9.1
-
diff --git a/target/linux/lantiq/patches-3.6/0301-owrt-atm.patch b/target/linux/lantiq/patches-3.6/0301-owrt-atm.patch
deleted file mode 100644
index 63eb820c49..0000000000
--- a/target/linux/lantiq/patches-3.6/0301-owrt-atm.patch
+++ /dev/null
@@ -1,80 +0,0 @@
-From 8d2a7d1fb561c9cb098c2b13ded34fe0f49dcca5 Mon Sep 17 00:00:00 2001
-From: John Crispin <blogic@openwrt.org>
-Date: Fri, 3 Aug 2012 10:27:25 +0200
-Subject: [PATCH 20/25] owrt atm
-
----
- arch/mips/lantiq/irq.c | 2 ++
- arch/mips/mm/cache.c | 2 ++
- net/atm/common.c | 6 ++++++
- net/atm/proc.c | 2 +-
- 4 files changed, 11 insertions(+), 1 deletions(-)
-
-Index: linux-3.6.6/arch/mips/lantiq/irq.c
-===================================================================
---- linux-3.6.6.orig/arch/mips/lantiq/irq.c 2012-11-08 23:08:47.000000000 +0100
-+++ linux-3.6.6/arch/mips/lantiq/irq.c 2012-11-08 23:10:32.023843184 +0100
-@@ -14,6 +14,7 @@
- #include <linux/of_platform.h>
- #include <linux/of_address.h>
- #include <linux/of_irq.h>
-+#include <linux/module.h>
-
- #include <asm/bootinfo.h>
- #include <asm/irq_cpu.h>
-@@ -107,6 +108,7 @@
- ltq_icu_w32(im, ltq_icu_r32(im, ier) & ~BIT(offset), ier);
- ltq_icu_w32(im, BIT(offset), isr);
- }
-+EXPORT_SYMBOL(ltq_mask_and_ack_irq);
-
- static void ltq_ack_irq(struct irq_data *d)
- {
-Index: linux-3.6.6/arch/mips/mm/cache.c
-===================================================================
---- linux-3.6.6.orig/arch/mips/mm/cache.c 2012-11-08 23:08:45.000000000 +0100
-+++ linux-3.6.6/arch/mips/mm/cache.c 2012-11-08 23:09:41.155841939 +0100
-@@ -58,6 +58,8 @@
- void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
- EXPORT_SYMBOL(_dma_cache_wback_inv);
-+EXPORT_SYMBOL(_dma_cache_wback);
-+EXPORT_SYMBOL(_dma_cache_inv);
-
- #endif /* CONFIG_DMA_NONCOHERENT */
-
-Index: linux-3.6.6/net/atm/common.c
-===================================================================
---- linux-3.6.6.orig/net/atm/common.c 2012-11-05 09:57:06.000000000 +0100
-+++ linux-3.6.6/net/atm/common.c 2012-11-08 23:09:41.155841939 +0100
-@@ -62,11 +62,17 @@
- write_unlock_irq(&vcc_sklist_lock);
- }
-
-+struct sk_buff* (*ifx_atm_alloc_tx)(struct atm_vcc *, unsigned int) = NULL;
-+EXPORT_SYMBOL(ifx_atm_alloc_tx);
-+
- static struct sk_buff *alloc_tx(struct atm_vcc *vcc, unsigned int size)
- {
- struct sk_buff *skb;
- struct sock *sk = sk_atm(vcc);
-
-+ if (ifx_atm_alloc_tx != NULL)
-+ return ifx_atm_alloc_tx(vcc, size);
-+
- if (sk_wmem_alloc_get(sk) && !atm_may_send(vcc, size)) {
- pr_debug("Sorry: wmem_alloc = %d, size = %d, sndbuf = %d\n",
- sk_wmem_alloc_get(sk), size, sk->sk_sndbuf);
-Index: linux-3.6.6/net/atm/proc.c
-===================================================================
---- linux-3.6.6.orig/net/atm/proc.c 2012-11-05 09:57:06.000000000 +0100
-+++ linux-3.6.6/net/atm/proc.c 2012-11-08 23:09:41.159841940 +0100
-@@ -154,7 +154,7 @@
- static void pvc_info(struct seq_file *seq, struct atm_vcc *vcc)
- {
- static const char *const class_name[] = {
-- "off", "UBR", "CBR", "VBR", "ABR"};
-+ "off","UBR","CBR","NTR-VBR","ABR","ANY","RT-VBR","UBR+","GFR"};
- static const char *const aal_name[] = {
- "---", "1", "2", "3/4", /* 0- 3 */
- "???", "5", "???", "???", /* 4- 7 */