diff options
Diffstat (limited to 'target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch | 82118 |
1 files changed, 0 insertions, 82118 deletions
diff --git a/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch b/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch deleted file mode 100644 index 34c31bfac5..0000000000 --- a/target/linux/lantiq/patches-3.3/0014-import-compat-headers.patch +++ /dev/null @@ -1,82118 +0,0 @@ -From a34f44106e933def9f66bfe0a806d7daa27ce387 Mon Sep 17 00:00:00 2001 -From: John Crispin <blogic@openwrt.org> -Date: Fri, 6 Jul 2012 14:46:44 +0200 -Subject: [PATCH 14/25] import compat headers - ---- - arch/mips/include/asm/ifx/amazon_se/amazon_se.h | 1167 +++ - .../include/asm/ifx/amazon_se/amazon_se_admmod.h | 248 + - .../mips/include/asm/ifx/amazon_se/boards/Makefile | 13 + - .../asm/ifx/amazon_se/boards/amazon_se_admmod.c | 722 ++ - .../asm/ifx/amazon_se/boards/amazon_se_admmod.h | 248 + - .../asm/ifx/amazon_se/boards/amazon_se_ref_board.c | 437 ++ - .../asm/ifx/amazon_se/boards/amazon_se_ref_board.h | 55 + - .../mips/include/asm/ifx/amazon_se/boards/boards.h | 4 + - arch/mips/include/asm/ifx/amazon_se/irq.h | 116 + - arch/mips/include/asm/ifx/amazon_se/model.h | 54 + - arch/mips/include/asm/ifx/ar10/ar10.h | 1705 ++++ - arch/mips/include/asm/ifx/ar10/ar10_ref_board.h | 54 + - arch/mips/include/asm/ifx/ar10/emulation.h | 46 + - arch/mips/include/asm/ifx/ar10/irq.h | 214 + - arch/mips/include/asm/ifx/ar10/model.h | 54 + - arch/mips/include/asm/ifx/ar9/ar9.h | 1327 ++++ - arch/mips/include/asm/ifx/ar9/ar9_ref_board.h | 48 + - arch/mips/include/asm/ifx/ar9/irq.h | 176 + - arch/mips/include/asm/ifx/ar9/model.h | 54 + - arch/mips/include/asm/ifx/common_routines.h | 221 + - arch/mips/include/asm/ifx/danube/danube.h | 1442 ++++ - .../mips/include/asm/ifx/danube/danube_ref_board.h | 37 + - arch/mips/include/asm/ifx/danube/irq.h | 152 + - arch/mips/include/asm/ifx/danube/model.h | 54 + - arch/mips/include/asm/ifx/hn1/emulation.h | 40 + - arch/mips/include/asm/ifx/hn1/hn1.h | 1293 +++ - arch/mips/include/asm/ifx/hn1/hn1_eval_board.h | 36 + - arch/mips/include/asm/ifx/hn1/hn1_ref_board.h | 36 + - arch/mips/include/asm/ifx/hn1/irq.h | 183 + - arch/mips/include/asm/ifx/hn1/model.h | 28 + - arch/mips/include/asm/ifx/ifx_atm.h | 196 + - arch/mips/include/asm/ifx/ifx_board.h | 52 + - arch/mips/include/asm/ifx/ifx_clk.h | 140 + - arch/mips/include/asm/ifx/ifx_dcdc.h | 255 + - arch/mips/include/asm/ifx/ifx_dma_core.h | 316 + - arch/mips/include/asm/ifx/ifx_ebu_led.h | 76 + - arch/mips/include/asm/ifx/ifx_eth_framework.h | 90 + - arch/mips/include/asm/ifx/ifx_gpio.h | 428 + - arch/mips/include/asm/ifx/ifx_gptu.h | 239 + - arch/mips/include/asm/ifx/ifx_led.h | 331 + - arch/mips/include/asm/ifx/ifx_ledc.h | 351 + - arch/mips/include/asm/ifx/ifx_mmc_wlan.h | 311 + - arch/mips/include/asm/ifx/ifx_pmcu.h | 417 + - arch/mips/include/asm/ifx/ifx_pmon.h | 204 + - arch/mips/include/asm/ifx/ifx_pmu.h | 776 ++ - arch/mips/include/asm/ifx/ifx_ptm.h | 203 + - arch/mips/include/asm/ifx/ifx_rcu.h | 298 + - arch/mips/include/asm/ifx/ifx_regs.h | 262 + - arch/mips/include/asm/ifx/ifx_si.h | 246 + - arch/mips/include/asm/ifx/ifx_ssc.h | 242 + - arch/mips/include/asm/ifx/ifx_types.h | 217 + - arch/mips/include/asm/ifx/ifx_usif_spi.h | 247 + - arch/mips/include/asm/ifx/ifx_wdt.h | 118 + - arch/mips/include/asm/ifx/irq.h | 256 + - arch/mips/include/asm/ifx/model.h | 50 + - arch/mips/include/asm/ifx/vr9/emulation.h | 46 + - arch/mips/include/asm/ifx/vr9/irq.h | 196 + - arch/mips/include/asm/ifx/vr9/model.h | 54 + - arch/mips/include/asm/ifx/vr9/vr9.h | 1785 +++++ - arch/mips/include/asm/ifx/vr9/vr9_ref_board.h | 46 + - arch/mips/include/asm/ifx/war.h | 25 + - .../asm/mach-lantiq/falcon/cpu-feature-overrides.h | 58 + - arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h | 1520 ++++ - .../include/asm/mach-lantiq/falcon/gpon_reg_base.h | 376 + - arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h | 830 ++ - .../mips/include/asm/mach-lantiq/falcon/icu0_reg.h | 4324 ++++++++++ - .../include/asm/mach-lantiq/falcon/status_reg.h | 529 ++ - .../mips/include/asm/mach-lantiq/falcon/sys1_reg.h | 2008 +++++ - .../include/asm/mach-lantiq/falcon/sys_eth_reg.h | 1132 +++ - .../include/asm/mach-lantiq/falcon/sys_gpe_reg.h | 2829 +++++++ - arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h | 60 + - include/linux/atm.h | 5 + - include/linux/pci.h | 1 + - include/linux/pci_ids.h | 8 + - include/net/ifx_ppa_api.h | 2606 +++++++ - include/net/ifx_ppa_api_common.h | 47 + - include/net/ifx_ppa_api_directpath.h | 301 + - include/net/ifx_ppa_hook.h | 1150 +++ - include/net/ifx_ppa_ppe_hal.h | 317 + - include/net/ifx_ppa_stack_al.h | 1559 ++++ - include/net/ipv6.h | 5 + - include/switch_api/AR9.h | 4342 +++++++++++ - include/switch_api/Tantos3G.h | 5882 ++++++++++++++ - include/switch_api/VR9_switch.h | 2637 +++++++ - include/switch_api/VR9_top.h | 798 ++ - include/switch_api/commonReg.h | 1312 ++++ - include/switch_api/gphy_fw.h | 20 + - include/switch_api/gphy_fw_fe.h | 8217 ++++++++++++++++++++ - include/switch_api/gphy_fw_ge.h | 8216 +++++++++++++++++++ - include/switch_api/ifx_ethsw.h | 3820 +++++++++ - include/switch_api/ifx_ethsw_PSB6970.h | 647 ++ - include/switch_api/ifx_ethsw_PSB6970_core.h | 182 + - include/switch_api/ifx_ethsw_PSB6970_ll.h | 1722 ++++ - include/switch_api/ifx_ethsw_api.h | 172 + - include/switch_api/ifx_ethsw_core_platform.h | 94 + - include/switch_api/ifx_ethsw_flow.h | 845 ++ - include/switch_api/ifx_ethsw_flow_core.h | 254 + - include/switch_api/ifx_ethsw_flow_ll.h | 2015 +++++ - include/switch_api/ifx_ethsw_init.h | 29 + - include/switch_api/ifx_ethsw_kernel_api.h | 80 + - include/switch_api/ifx_ethsw_linux.h | 64 + - include/switch_api/ifx_ethsw_ll_fkt.h | 41 + - include/switch_api/ifx_ethsw_pce.h | 385 + - include/switch_api/ifx_ethsw_pm.h | 63 + - include/switch_api/ifx_ethsw_pm_plat.h | 63 + - include/switch_api/ifx_ethsw_pm_pmcu.h | 36 + - include/switch_api/ifx_ethsw_ral.h | 56 + - include/switch_api/ifx_ethsw_reg_access.h | 38 + - include/switch_api/ifx_ethsw_rml.h | 49 + - include/switch_api/ifx_ethsw_vr9_reg_access.h | 23 + - include/switch_api/ifx_switch_ll.h | 101 + - include/switch_api/ifx_types.h | 118 + - include/switch_api/ifxmips_gphy_sw.h | 124 + - include/switch_api/ifxmips_sw_reg.h | 300 + - include/switch_api/regmapper.h | 27 + - 115 files changed, 81174 insertions(+), 0 deletions(-) - create mode 100644 arch/mips/include/asm/ifx/amazon_se/amazon_se.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/Makefile - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/boards/boards.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/irq.h - create mode 100644 arch/mips/include/asm/ifx/amazon_se/model.h - create mode 100644 arch/mips/include/asm/ifx/ar10/ar10.h - create mode 100644 arch/mips/include/asm/ifx/ar10/ar10_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/ar10/emulation.h - create mode 100644 arch/mips/include/asm/ifx/ar10/irq.h - create mode 100644 arch/mips/include/asm/ifx/ar10/model.h - create mode 100644 arch/mips/include/asm/ifx/ar9/ar9.h - create mode 100644 arch/mips/include/asm/ifx/ar9/ar9_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/ar9/irq.h - create mode 100644 arch/mips/include/asm/ifx/ar9/model.h - create mode 100644 arch/mips/include/asm/ifx/common_routines.h - create mode 100644 arch/mips/include/asm/ifx/danube/danube.h - create mode 100644 arch/mips/include/asm/ifx/danube/danube_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/danube/irq.h - create mode 100644 arch/mips/include/asm/ifx/danube/model.h - create mode 100644 arch/mips/include/asm/ifx/hn1/emulation.h - create mode 100644 arch/mips/include/asm/ifx/hn1/hn1.h - create mode 100644 arch/mips/include/asm/ifx/hn1/hn1_eval_board.h - create mode 100644 arch/mips/include/asm/ifx/hn1/hn1_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/hn1/irq.h - create mode 100644 arch/mips/include/asm/ifx/hn1/model.h - create mode 100644 arch/mips/include/asm/ifx/ifx_atm.h - create mode 100644 arch/mips/include/asm/ifx/ifx_board.h - create mode 100644 arch/mips/include/asm/ifx/ifx_clk.h - create mode 100644 arch/mips/include/asm/ifx/ifx_dcdc.h - create mode 100644 arch/mips/include/asm/ifx/ifx_dma_core.h - create mode 100644 arch/mips/include/asm/ifx/ifx_ebu_led.h - create mode 100644 arch/mips/include/asm/ifx/ifx_eth_framework.h - create mode 100644 arch/mips/include/asm/ifx/ifx_gpio.h - create mode 100644 arch/mips/include/asm/ifx/ifx_gptu.h - create mode 100644 arch/mips/include/asm/ifx/ifx_led.h - create mode 100644 arch/mips/include/asm/ifx/ifx_ledc.h - create mode 100644 arch/mips/include/asm/ifx/ifx_mmc_wlan.h - create mode 100644 arch/mips/include/asm/ifx/ifx_pmcu.h - create mode 100644 arch/mips/include/asm/ifx/ifx_pmon.h - create mode 100644 arch/mips/include/asm/ifx/ifx_pmu.h - create mode 100644 arch/mips/include/asm/ifx/ifx_ptm.h - create mode 100644 arch/mips/include/asm/ifx/ifx_rcu.h - create mode 100644 arch/mips/include/asm/ifx/ifx_regs.h - create mode 100644 arch/mips/include/asm/ifx/ifx_si.h - create mode 100644 arch/mips/include/asm/ifx/ifx_ssc.h - create mode 100644 arch/mips/include/asm/ifx/ifx_types.h - create mode 100644 arch/mips/include/asm/ifx/ifx_usif_spi.h - create mode 100644 arch/mips/include/asm/ifx/ifx_wdt.h - create mode 100644 arch/mips/include/asm/ifx/irq.h - create mode 100644 arch/mips/include/asm/ifx/model.h - create mode 100644 arch/mips/include/asm/ifx/vr9/emulation.h - create mode 100644 arch/mips/include/asm/ifx/vr9/irq.h - create mode 100644 arch/mips/include/asm/ifx/vr9/model.h - create mode 100644 arch/mips/include/asm/ifx/vr9/vr9.h - create mode 100644 arch/mips/include/asm/ifx/vr9/vr9_ref_board.h - create mode 100644 arch/mips/include/asm/ifx/war.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/status_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h - create mode 100644 arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h - create mode 100644 include/net/ifx_ppa_api.h - create mode 100644 include/net/ifx_ppa_api_common.h - create mode 100644 include/net/ifx_ppa_api_directpath.h - create mode 100644 include/net/ifx_ppa_hook.h - create mode 100644 include/net/ifx_ppa_ppe_hal.h - create mode 100644 include/net/ifx_ppa_stack_al.h - create mode 100644 include/switch_api/AR9.h - create mode 100644 include/switch_api/Tantos3G.h - create mode 100644 include/switch_api/VR9_switch.h - create mode 100644 include/switch_api/VR9_top.h - create mode 100644 include/switch_api/commonReg.h - create mode 100644 include/switch_api/gphy_fw.h - create mode 100644 include/switch_api/gphy_fw_fe.h - create mode 100644 include/switch_api/gphy_fw_ge.h - create mode 100644 include/switch_api/ifx_ethsw.h - create mode 100644 include/switch_api/ifx_ethsw_PSB6970.h - create mode 100644 include/switch_api/ifx_ethsw_PSB6970_core.h - create mode 100644 include/switch_api/ifx_ethsw_PSB6970_ll.h - create mode 100644 include/switch_api/ifx_ethsw_api.h - create mode 100644 include/switch_api/ifx_ethsw_core_platform.h - create mode 100644 include/switch_api/ifx_ethsw_flow.h - create mode 100644 include/switch_api/ifx_ethsw_flow_core.h - create mode 100644 include/switch_api/ifx_ethsw_flow_ll.h - create mode 100644 include/switch_api/ifx_ethsw_init.h - create mode 100644 include/switch_api/ifx_ethsw_kernel_api.h - create mode 100644 include/switch_api/ifx_ethsw_linux.h - create mode 100644 include/switch_api/ifx_ethsw_ll_fkt.h - create mode 100644 include/switch_api/ifx_ethsw_pce.h - create mode 100644 include/switch_api/ifx_ethsw_pm.h - create mode 100644 include/switch_api/ifx_ethsw_pm_plat.h - create mode 100644 include/switch_api/ifx_ethsw_pm_pmcu.h - create mode 100644 include/switch_api/ifx_ethsw_ral.h - create mode 100644 include/switch_api/ifx_ethsw_reg_access.h - create mode 100644 include/switch_api/ifx_ethsw_rml.h - create mode 100644 include/switch_api/ifx_ethsw_vr9_reg_access.h - create mode 100644 include/switch_api/ifx_switch_ll.h - create mode 100644 include/switch_api/ifx_types.h - create mode 100644 include/switch_api/ifxmips_gphy_sw.h - create mode 100644 include/switch_api/ifxmips_sw_reg.h - create mode 100644 include/switch_api/regmapper.h - -diff --git a/arch/mips/include/asm/ifx/amazon_se/amazon_se.h b/arch/mips/include/asm/ifx/amazon_se/amazon_se.h -new file mode 100644 -index 0000000..af1c692 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/amazon_se.h -@@ -0,0 +1,1167 @@ -+/****************************************************************************** -+** -+** FILE NAME : amazon_se.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Amazon-SE -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AMAZON_SE_H -+#define AMAZON_SE_H -+#include <asm/bootinfo.h> -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define MACH_GROUP_IFX MACH_GROUP_AMAZON_SE -+#define MACH_TYPE_IFX MACH_AMAZON_SE -+ -+ -+#define IFX_MC_BASE (KSEG1 | 0x1F800000) -+#define IFX_MC_ERRCAUSE ((volatile u32*)(IFX_MC_BASE + 0x10)) -+#define IFX_MC_ERRADD ((volatile u32*)(IFX_MC_BASE + 0x20)) -+#define IFX_MC_PRIO ((volatile u32*)(IFX_MC_BASE + 0x50)) -+#define IFX_MC_CON ((volatile u32*)(IFX_MC_BASE + 0x60)) -+#define IFX_MC_SRAM0 ((volatile u32*)(IFX_MC_BASE + 0x100)) -+ -+/* This defers from Amazon_SE Hardware Users Manual Revision 1.0.pdf which is wrong */ -+#define IFX_MC_PRIO_AHB_SHIFT 6 -+#define IFX_MC_PRIO_FPI_SHIFT 8 -+#define IFX_MC_PRIO_DMA_SHIFT 2 -+#define IFX_MC_PRIO_2NDPRIOPORT_SHIFT 4 -+#define IFX_MC_PRIO_CPU0_SHIFT 0 -+ -+#define IFX_MC_PRIO_0 0 -+#define IFX_MC_PRIO_1 1 -+#define IFX_MC_PRIO_2 2 -+#define IFX_MC_PRIO_3 3 -+ -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) -+ -+#define IFX_RST_ALL (1 << 30) -+#define IFX_RCU_ARC_DFE_RESET (1 << 7) -+#define IFX_RCU_AHB_RESET (1 << 6) -+#define IFX_RCU_PPE_RESET (1 << 8) -+ -+/***Reset Request Register***/ -+#define IFX_RCU_RST_REQ_CPU0 (1 << 31) -+#define IFX_RCU_RST_REQ_CPU1 (1 << 3) -+#define IFX_RCU_RST_REQ_CPUSUB (1 << 29) -+#define IFX_RCU_RST_REQ_HRST (1 << 28) -+#define IFX_RCU_RST_REQ_WDT0 (1 << 27) -+#define IFX_RCU_RST_REQ_WDT1 (1 << 26) -+#define IFX_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -+#define IFX_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -+#define IFX_RCU_RST_REQ_MUX_ARC (1 << 23) -+#define IFX_RCU_RST_REQ_SWTBOOT (1 << 22) -+#define IFX_RCU_RST_REQ_DMA (1 << 21) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 29) -+#define IFX_RCU_RST_REQ_ETHPHY0 (1 << 19) -+#define IFX_RCU_RST_REQ_CPU0_BR (1 << 18) -+ -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL IFX_RST_ALL -+ -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MEI register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) -+#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) -+ -+/*All mei related registers are defined in amazon_se_mei_bsp.h */ -+ -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) -+/***CGU Interface Clock Control Register***/ -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) -+/***CGU Osc Control ***/ -+#define IFX_CGU_OSC_CON ((volatile u32*)(IFX_CGU + 0x001c)) -+ -+#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD+ 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD+ 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD+ 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x1E105300) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32 *)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON0 ((volatile u32 *)(IFX_EBU + 0x0060)) -+#define IFX_EBU_CON1 ((volatile u32 *)(IFX_EBU + 0x0064)) -+ -+#define IFX_EBU_CON_EBU_TA_MASK 7 -+#define IFX_EBU_CON_EBU_TA_SHIFT 29 -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+#define IFX_EBU_CON_1 (1 << 3) -+ -+/* IFX_EBU_CON0 */ -+#define IFX_EBU_CON0_WAITWRC_MASK 0xF00 -+#define IFX_EBU_CON0_WAITWRC_SHIFT 8 -+#define IFX_EBU_CON0_WAITRDC_MASK 0xC0 -+#define IFX_EBU_CON0_WAITRDC_SHIFT 6 -+#define IFX_EBU_CON0_RECOVC_MASK 0xC -+#define IFX_EBU_CON0_CMULT_MASK 3 -+#define IFX_EBU_CON0_CMULT_SHIFT 0 -+#define IFX_EBU_CON0_WRDIS (1 << 31) -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL0_REGEN (1 << 0) -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL2_REGEN (1 << 0) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL3_REGEN (1 << 0) -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_PG_EN 0x20000000 -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_WRDIS (1 << 31) -+//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+//#define IFX_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -+//#define IFX_EBU_BUSCON1_AGEN (value) (((( 1 << 2) - 1) & (value)) << 24) -+//#define IFX_EBU_BUSCON1_CMULTR (value) (((( 1 << 2) - 1) & (value)) << 22) -+//#define IFX_EBU_BUSCON1_WAIT (value) (((( 1 << 2) - 1) & (value)) << 20) -+//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) -+//#define IFX_EBU_BUSCON1_SETUP (1 << 18) -+//#define IFX_EBU_BUSCON1_PORTW (value) (((( 1 << 2) - 1) & (value)) << 16) -+//#define IFX_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -+//#define IFX_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -+//#define IFX_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -+//#define IFX_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -+//#define IFX_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+ }; -+ -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+ }; -+ -+ -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+ }; -+ -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+ }; -+ -+ -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+ }; -+ -+ -+ -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+#define IFX_EBU_BUSCON2_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON2_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON2_SETUP (1 << 18) -+#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU + 0x0090)) -+#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU + 0x0094)) -+#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU + 0x00A0)) -+#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU + 0x00A4)) -+ -+ -+/* NAND Flash Controller control Register */ -+#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+ -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+ }; -+ -+ -+ -+/* NAND Flash Device RD/BY State Register */ -+#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) -+#define IFX_EBU_NAND_WAIT_RD (0x1) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+ -+ -+ -+ -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+/***ASC Clock Control Register***/ -+#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) -+#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_ASC1_CLC_DISS (1 << 1) -+#define IFX_ASC1_CLC_DISR (1 << 0) -+ -+/***ASC Port Input Select Register***/ -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL_RIS (1 << 0) -+ -+/***ASC Control Register***/ -+#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) -+#define IFX_ASC1_CON_BEN (1 << 20) -+#define IFX_ASC1_CON_TOEN (1 << 20) -+#define IFX_ASC1_CON_ROEN (1 << 19) -+#define IFX_ASC1_CON_RUEN (1 << 18) -+#define IFX_ASC1_CON_FEN (1 << 17) -+#define IFX_ASC1_CON_PAL (1 << 16) -+#define IFX_ASC1_CON_R (1 << 15) -+#define IFX_ASC1_CON_ACO (1 << 14) -+#define IFX_ASC1_CON_LB (1 << 13) -+#define IFX_ASC1_CON_ERCLK (1 << 10) -+#define IFX_ASC1_CON_FDE (1 << 9) -+#define IFX_ASC1_CON_BRS (1 << 8) -+#define IFX_ASC1_CON_STP (1 << 7) -+#define IFX_ASC1_CON_SP (1 << 6) -+#define IFX_ASC1_CON_ODD (1 << 5) -+#define IFX_ASC1_CON_PEN (1 << 4) -+#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***ASC Staus Register***/ -+#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) -+/***ASC Write Hardware Modified Control Register***/ -+#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) -+#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) -+#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) -+#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) -+#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) -+#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) -+#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) -+#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) -+#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) -+#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) -+#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) -+#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) -+#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) -+#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) -+ -+/***ASC Baudrate Timer/Reload Register***/ -+#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) -+#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) -+ -+/***ASC Fractional Divider Register***/ -+#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Transmit Buffer Register***/ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Receive Buffer Register***/ -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Autobaud Control Register***/ -+#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) -+#define IFX_ASC1_ABCON_RXINV (1 << 11) -+#define IFX_ASC1_ABCON_TXINV (1 << 10) -+#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -+#define IFX_ASC1_ABCON_FCDETEN (1 << 4) -+#define IFX_ASC1_ABCON_ABDETEN (1 << 3) -+#define IFX_ASC1_ABCON_ABSTEN (1 << 2) -+#define IFX_ASC1_ABCON_AUREN (1 << 1) -+#define IFX_ASC1_ABCON_ABEN (1 << 0) -+ -+/***Receive FIFO Control Register***/ -+#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) -+#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) -+#define IFX_ASC1_RXFCON_RXFEN (1 << 0) -+ -+/***Transmit FIFO Control Register***/ -+#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) -+#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) -+#define IFX_ASC1_TXFCON_TXFEN (1 << 0) -+ -+/***FIFO Status Register***/ -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -+#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+/***ASC Autobaud Status Register***/ -+#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) -+#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) -+#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) -+#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) -+#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) -+#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) -+ -+/***ASC Write HW Modified Autobaud Status Register***/ -+#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) -+#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) -+#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) -+#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) -+#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) -+#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) -+#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) -+#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) -+#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) -+#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) -+#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) -+ -+/***ASC IRNCR0 **/ -+#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) -+#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) -+/***ASC IRNCR1 **/ -+#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) -+#define IFX_ASC_IRNCR_TIR 0x1 -+#define IFX_ASC_IRNCR_RIR 0x2 -+#define IFX_ASC_IRNCR_EIR 0x4 -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)IFX_DMA_BASE -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) -+#define IFX_DMA_CS (volatile u32*)(IFX_DMA_BASE + 0x18) -+#define IFX_DMA_CCTRL (volatile u32*)(IFX_DMA_BASE + 0x1C) -+#define IFX_DMA_CDBA (volatile u32*)(IFX_DMA_BASE + 0x20) -+#define IFX_DMA_CDLEN (volatile u32*)(IFX_DMA_BASE + 0x24) -+#define IFX_DMA_CIS (volatile u32*)(IFX_DMA_BASE + 0x28) -+#define IFX_DMA_CIE (volatile u32*)(IFX_DMA_BASE + 0x2C) -+#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) -+#define IFX_DMA_PS (volatile u32*)(IFX_DMA_BASE + 0x40) -+#define IFX_DMA_PCTRL (volatile u32*)(IFX_DMA_BASE + 0x44) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug + 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+#define IFX_ICU_IM0_IMR_IID (1 << 31) -+#define IFX_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM0_IR(value) (1 << (value)) -+ -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+#define IFX_ICU_IM1_IMR_IID (1 << 31) -+#define IFX_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM1_IR(value) (1 << (value)) -+ -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+#define IFX_ICU_IM2_IMR_IID (1 << 31) -+#define IFX_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM2_IR(value) (1 << (value)) -+ -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+#define IFX_ICU_IM3_IMR_IID (1 << 31) -+#define IFX_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM3_IR(value) (1 << (value)) -+ -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+#define IFX_ICU_IM4_IMR_IID (1 << 31) -+#define IFX_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM4_IR(value) (1 << (value)) -+ -+#define IFX_ICU_IM5_ISR ((volatile u32*)(IFX_ICU + 0x00C8)) -+#define IFX_ICU_IM5_IER ((volatile u32*)(IFX_ICU + 0x00D0)) -+#define IFX_ICU_IM5_IOSR ((volatile u32*)(IFX_ICU + 0x00D8)) -+#define IFX_ICU_IM5_IRSR ((volatile u32*)(IFX_ICU + 0x00E0)) -+#define IFX_ICU_IM5_IMR ((volatile u32*)(IFX_ICU + 0x00E8)) -+#define IFX_ICU_IM5_IMR_IID (1 << 31) -+#define IFX_ICU_IM5_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM5_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM5_IR(value) (1 << (value)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU+ 0x00f8)) -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK 0x0000003f -+#define IFX_ICU_IM1_VEC_MASK 0x00000fc0 -+#define IFX_ICU_IM2_VEC_MASK 0x0003f000 -+#define IFX_ICU_IM3_VEC_MASK 0x00fc0000 -+#define IFX_ICU_IM4_VEC_MASK 0x3f000000 -+ -+#define IFX_ICU_IM0_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM0_IER_IR(value) (1<<(value)) -+#define IFX_ICU_IM1_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM1_IER_IR(value) (1<<(value)) -+#define IFX_ICU_IM2_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM2_IER_IR(value) (1<<(value)) -+#define IFX_ICU_IM3_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM3_IER_IR(value) (1<<(value)) -+#define IFX_ICU_IM4_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM4_IER_IR(value) (1<<(value)) -+#define IFX_ICU_IM5_ISR_IR(value) (1<<(value)) -+#define IFX_ICU_IM5_IER_IR(value) (1<<(value)) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1+0x1f101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32*)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32*)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32*)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32*)(IFX_ICU_EIU + 0x000c)) -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) -+ -+ -+ -+/************************************************************************/ -+/* Module : DEU register address and bits */ -+/************************************************************************/ -+ -+#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) -+ -+/* DEU Control Register */ -+#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) -+#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) -+ -+/* DEU control register */ -+#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) -+#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) -+#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) -+#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) -+#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) -+#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) -+#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) -+#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) -+#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) -+#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) -+#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+ -+/* AES DEU register */ -+#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) -+#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) -+#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) -+#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) -+ -+/* AES Key register */ -+#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) -+#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) -+#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) -+#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) -+#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) -+#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) -+#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) -+#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) -+ -+/* AES vector register */ -+#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) -+#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) -+#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) -+#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) -+#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) -+#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) -+#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) -+#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) -+ -+/* hash control registe */ -+#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) -+#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) -+#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8 )) -+#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC )) -+#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0 )) -+#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) -+#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) -+ -+#define IFX_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) -+ -+#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) -+#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) -+#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) -+ -+ -+ -+/************************************************************************/ -+/* Module : PPE register address and bits */ -+/************************************************************************/ -+ -+#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) -+#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) -+#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) -+#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) -+#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) -+ -+#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) -+ -+/* -+ * ETOP MDIO Registers -+ */ -+#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -+#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -+#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -+#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -+#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -+#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -+#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -+#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -+#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -+#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -+#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -+#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -+#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -+#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -+#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -+#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -+#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -+#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -+#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -+#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) -+ -+#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -+#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -+#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -+#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -+#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -+#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -+#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) -+ -+#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -+#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -+#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -+#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -+#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -+#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) -+ -+ -+/* Sharebuff SB RAM2 control data */ -+#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) -+#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) -+ -+ -+ -+#endif //IFX_H -diff --git a/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h b/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h -new file mode 100644 -index 0000000..7f98fd3 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/amazon_se_admmod.h -@@ -0,0 +1,248 @@ -+/****************************************************************************** -+ Copyright (c) 2004, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+ ****************************************************************************** -+ Module : ifx_swdrv.h -+ Date : 2004-09-01 -+ Description : JoeLin -+ Remarks: -+ *****************************************************************************/ -+/****************************************************************************** -+** 2009/12/17 Lantiq Inc. Revised by Richard Hsu -+** Rename to amazon_se_admmod.h. -+** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. -+** ASE WAVE board uses PHY2PHY connection to Tantos 0G -+** -+*******************************************************************************/ -+ -+ -+ -+ -+#ifndef _ADM_6996_MODULE_H_ -+#define _ADM_6996_MODULE_H_ -+ -+#include <asm/ifx/amazon_se/amazon_se.h> -+ -+//Wrapper for ASE GPIO setting -+#define AMAZON_SE_GPIO_P1_OUT IFX_GPIO_P1_OUT -+#define AMAZON_SE_GPIO_P1_ALTSEL0 IFX_GPIO_P1_ALTSEL0 -+#define AMAZON_SE_GPIO_P1_ALTSEL1 IFX_GPIO_P1_ALTSEL1 -+#define AMAZON_SE_GPIO_P1_DIR IFX_GPIO_P1_DIR -+#define AMAZON_SE_GPIO_P1_IN IFX_GPIO_P1_IN -+ -+#define ifx_printf(x) printk x -+ -+/* command codes */ -+#define ADM_SW_SMI_READ 0x02 -+#define ADM_SW_SMI_WRITE 0x01 -+#define ADM_SW_SMI_START 0x01 -+ -+#define ADM_SW_EEPROM_WRITE 0x01 -+#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 -+#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 -+#define EEPROM_TYPE 8 /* for 93C66 */ -+ -+/* bit masks */ -+#define ADM_SW_BIT_MASK_1 0x00000001 -+#define ADM_SW_BIT_MASK_2 0x00000002 -+#define ADM_SW_BIT_MASK_4 0x00000008 -+#define ADM_SW_BIT_MASK_10 0x00000200 -+#define ADM_SW_BIT_MASK_16 0x00008000 -+#define ADM_SW_BIT_MASK_32 0x80000000 -+ -+/* delay timers */ -+#define ADM_SW_MDC_DOWN_DELAY 5 -+#define ADM_SW_MDC_UP_DELAY 5 -+#define ADM_SW_CS_DELAY 5 -+ -+/* MDIO modes */ -+#define ADM_SW_MDIO_OUTPUT 1 -+#define ADM_SW_MDIO_INPUT 0 -+ -+#define ADM_SW_MAX_PORT_NUM 5 -+#define ADM_SW_MAX_VLAN_NUM 15 -+ -+/* registers */ -+#define ADM_SW_PORT0_CONF 0x1 -+#define ADM_SW_PORT1_CONF 0x3 -+#define ADM_SW_PORT2_CONF 0x5 -+#define ADM_SW_PORT3_CONF 0x7 -+#define ADM_SW_PORT4_CONF 0x8 -+#define ADM_SW_PORT5_CONF 0x9 -+#define ADM_SW_VLAN_MODE 0x11 -+#define ADM_SW_MAC_LOCK 0x12 -+#define ADM_SW_VLAN0_CONF 0x13 -+#define ADM_SW_PORT0_PVID 0x28 -+#define ADM_SW_PORT1_PVID 0x29 -+#define ADM_SW_PORT2_PVID 0x2a -+#define ADM_SW_PORT34_PVID 0x2b -+#define ADM_SW_PORT5_PVID 0x2c -+#define ADM_SW_PHY_RESET 0x2f -+#define ADM_SW_MISC_CONF 0x30 -+#define ADM_SW_BNDWDH_CTL0 0x31 -+#define ADM_SW_BNDWDH_CTL1 0x32 -+#define ADM_SW_BNDWDH_CTL_ENA 0x33 -+ -+/* port modes */ -+#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ -+#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ -+#define ADM_SW_PORT_100M 0x4 /* 100M */ -+#define ADM_SW_PORT_FULL 0x8 /* full duplex */ -+#define ADM_SW_PORT_TAG 0x10 /* output tag on */ -+#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ -+#define ADM_SW_PORT_TOS 0x40 /* TOS first */ -+#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ -+#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ -+#define ADM_SW_PORT_PVID_SHIFT 10 -+#define ADM_SW_PORT_PVID_BITS 4 -+ -+/* VLAN */ -+#define ADM_SW_VLAN_PORT0 0x1 -+#define ADM_SW_VLAN_PORT1 0x2 -+#define ADM_SW_VLAN_PORT2 0x10 -+#define ADM_SW_VLAN_PORT3 0x40 -+#define ADM_SW_VLAN_PORT4 0x80 -+#define ADM_SW_VLAN_PORT5 0x100 -+ -+ -+/* GPIO 012 enabled, output mode */ -+#define GPIO_ENABLEBITS 0x000700f8 -+ -+/* -+ define AMAZON GPIO port to ADM6996 EEPROM interface -+ MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction -+ MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only -+ MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only -+ EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ -+ -+#define GPIO_MDIO 1 //P1.0 -+#define GPIO_MDC 2 //P1.1 -+#define GPIO_MDCS 4 //P1.2 -+ -+//joelin #define GPIO_MDIO 0 -+//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ -+//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ -+ -+ -+#define MDIO_INPUT 0x00000001 -+#define MDIO_OUTPUT_EN 0x00010000 -+ -+ -+/* type definitions */ -+typedef unsigned char U8; -+typedef unsigned short U16; -+typedef unsigned int U32; -+ -+typedef struct _REGRW_ -+{ -+ unsigned int addr; -+ unsigned int value; -+ unsigned int mode; -+}REGRW, *PREGRW; -+ -+//joelin adm6996i -+typedef struct _MACENTRY_ -+{ -+ unsigned char mac_addr[6]; -+ unsigned long fid:4; -+ unsigned long portmap:6; -+ union { -+ unsigned long age_timer:9; -+ unsigned long info_ctrl:9; -+ } ctrl; -+ unsigned long occupy:1; -+ unsigned long info_type:1; -+ unsigned long bad:1; -+ unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error -+ -+ }MACENTRY, *PMACENTRY; -+typedef struct _PROTOCOLFILTER_ -+{ -+ int protocol_filter_num;//[0~7] -+ int ip_p; //Value Compared with Protocol in IP Heade[7:0] -+ char action:2;//Action for protocol Filter . -+//00 = Protocol Portmap is Default Output Ports. -+//01 = Protocol Portmap is 6'b0. -+//10 = Protocol Portmap is the CPU port if the incoming port -+//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. -+ }PROTOCOLFILTER, *PPROTOCOLFILTER; -+ -+//joelin adm6996i -+ -+/* Santosh: for IGMP proxy/snooping */ -+ -+//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); -+//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); -+ -+ -+/* IOCTL keys */ -+#define KEY_IOCTL_ADM_REGRW 0x01 -+#define KEY_IOCTL_ADM_SW_REGRW 0x02 -+#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 -+#define KEY_IOCTL_ADM_SW_INIT 0x04 -+//for adm6996i-start -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b -+ -+//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 -+#define KEY_IOCTL_MAX_KEY 0x0c -+//for adm6996i-end -+/* IOCTL MAGIC */ -+#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') -+ -+/* IOCTL parameters */ -+#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) -+#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) -+#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) -+#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) -+ -+ -+//6996i-stat -+#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) -+#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) -+#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) -+#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) -+ -+//6996i-end -+ -+ -+#define REG_READ 0x0 -+#define REG_WRITE 0x1 -+ -+/* undefine symbol */ -+//#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) -+//#define GPIO0_INPUT_MASK 0 -+//#define GPIO_conf0_REG 0x12345678 -+//#define GPIO_SET_HI -+//#define GPIO_SET_LOW -+ -+#endif -+/* _ADM_6996_MODULE_H_ */ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/Makefile b/arch/mips/include/asm/ifx/amazon_se/boards/Makefile -new file mode 100644 -index 0000000..f731c7e ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/Makefile -@@ -0,0 +1,13 @@ -+# -+# Makefile for the platform specific kernel interface routines under Linux. -+# -+ -+all: ifxmips_amazon_se_boards.a -+ -+obj-$(CONFIG_AMAZON_SE_REF_BOARD) += amazon_se_ref_board.o -+ -+EXTRA_AFLAGS := $(CFLAGS) -+ -+clean: -+ rm -f *.o *.a -+ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c -new file mode 100644 -index 0000000..cfdce24 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.c -@@ -0,0 +1,722 @@ -+/****************************************************************************** -+** -+** FILE NAME : admmod.c -+** PROJECT : Danube -+** MODULES : ADM6996 -+** -+** DATE : 1 SEP 2004 -+** AUTHOR : Joe Lin -+** DESCRIPTION : ADM6996 Switch Driver -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+*******************************************************************************/ -+ -+/****************************************************************************** -+** 2009/12/17 Lantiq Inc. Revised by Richard Hsu -+** Rename to amazon_se_admmod.c. -+** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. -+** ASE WAVE board uses PHY2PHY connection to Tantos 0G -+** -+*******************************************************************************/ -+ -+ -+ -+#include <linux/module.h> -+#include <linux/string.h> -+#include <linux/proc_fs.h> -+#include <linux/delay.h> -+#include <asm/uaccess.h> -+#include <linux/init.h> -+#include <linux/ioctl.h> -+#include <asm/atomic.h> -+ -+ -+#include <asm/ifx/amazon_se/amazon_se_admmod.h> -+#include <asm/ifx/amazon_se/amazon_se.h> -+ -+// Using GPIO to access Tantos as default -+#define CONFIG_SWITCH_GPIO_ACCESS -+ -+#ifdef CONFIG_SWITCH_GPIO_ACCESS -+ #undef CONFIG_SWITCH_ADM6996_MDIO -+#endif -+ -+#define ADM_SW_IOCTL_PORTSTS _IO(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS) -+#define ADM_SW_IOCTL_INIT _IO(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT) -+ -+/* -+ initialize GPIO pins. -+ output mode, low -+*/ -+ -+// We use GPIO24/27 on ASE WAVE board for simulation -+#define ASE_TANTOS_MDIO 0x00000100 -+#define ASE_TANTOS_MDC 0x00000800 -+ -+#define ASE_TANTOS_MDIO_COMPLEMENT 0xfffffeff -+#define ASE_TANTOS_MDC_COMPLEMENT 0xfffff7ff -+#define TANTOS_SW_MDC_UP_DELAY 5 -+#define TANTOS_SW_MDC_DOWN_DELAY 5 -+ -+void ifx_gpio_init(void) -+{ -+ //GPIO24: MDIO P1.8 -+ //GPIO27: MDC P1.11 -+ -+/* -+ P1.8 as GPIO Out: -+ AMAZON_SE_GPIO_P1_ALTSEL0.8=0 -+ AMAZON_SE_GPIO_P1_ALTSEL1.8=0 -+ AMAZON_SE_GPIO_P1_DIR.8 = 1 -+ -+ P1.8 as MDIO pin: -+ AMAZON_SE_GPIO_P1_ALTSEL0.8=1 -+ AMAZON_SE_GPIO_P1_ALTSEL1.8=1 -+ AMAZON_SE_GPIO_P1_DIR.8 =1 -+ -+P1.11 as GPIO Out: -+ AMAZON_SE_GPIO_P1_ALTSEL0.8=0 -+ AMAZON_SE_GPIO_P1_ALTSEL1.8=0 -+ AMAZON_SE_GPIO_P1_DIR.8 =1 -+ -+P1.11 as MDC pin: -+ AMAZON_SE_GPIO_P1_ALTSEL0.8=1 -+ AMAZON_SE_GPIO_P1_ALTSEL1.8=1 -+ AMAZON_SE_GPIO_P1_DIR.8 =1 -+*/ -+ -+ -+ *(AMAZON_SE_GPIO_P1_OUT) |= (ASE_TANTOS_MDC|ASE_TANTOS_MDIO); -+ *(AMAZON_SE_GPIO_P1_ALTSEL0) &= ASE_TANTOS_MDC_COMPLEMENT; -+ *(AMAZON_SE_GPIO_P1_ALTSEL0) &= ASE_TANTOS_MDIO_COMPLEMENT; -+ *(AMAZON_SE_GPIO_P1_ALTSEL1) &= ASE_TANTOS_MDC_COMPLEMENT; -+ *(AMAZON_SE_GPIO_P1_ALTSEL1) &= ASE_TANTOS_MDIO_COMPLEMENT; -+ *(AMAZON_SE_GPIO_P1_DIR) |= (ASE_TANTOS_MDC|ASE_TANTOS_MDIO); -+ -+} -+ -+void gpio_info() -+{ -+/* -+ printk("*(AMAZON_SE_GPIO_P1_ALTSEL0) is %04x\n",*(AMAZON_SE_GPIO_P1_ALTSEL0)); -+ printk("*(AMAZON_SE_GPIO_P1_ALTSEL1) is %04x\n",*(AMAZON_SE_GPIO_P1_ALTSEL1)); -+ printk("*(AMAZON_SE_GPIO_P1_DIR) is %04x\n\n",*(AMAZON_SE_GPIO_P1_DIR)); -+*/ -+} -+/* read one bit from mdio port */ -+int ifx_sw_mdio_readbit(void) -+{ -+ //GPIO24 as MDIO -+ return *(AMAZON_SE_GPIO_P1_IN)& 0x0100 ; -+} -+ -+/* -+ MDIO mode selection -+ 1 -> output -+ 0 -> input -+ -+ switch input/output mode of GPIO 0 -+*/ -+void ifx_mdio_mode(int mode) -+{ -+ if (mode) -+ {*(AMAZON_SE_GPIO_P1_DIR) |= ASE_TANTOS_MDIO;} -+ else -+ {*(AMAZON_SE_GPIO_P1_DIR) &= ASE_TANTOS_MDIO_COMPLEMENT;} -+} -+ -+void ifx_mdc_hi(void) -+{ -+ *AMAZON_SE_GPIO_P1_OUT |= (ASE_TANTOS_MDC); -+} -+ -+void ifx_mdio_hi(void) -+{ -+ *AMAZON_SE_GPIO_P1_OUT |= (ASE_TANTOS_MDIO); -+} -+ -+void ifx_mdcs_hi(void) -+{ -+} -+ -+void ifx_mdc_lo(void) -+{ -+ *AMAZON_SE_GPIO_P1_OUT &= (ASE_TANTOS_MDC_COMPLEMENT); -+} -+ -+void ifx_mdio_lo(void) -+{ -+ *AMAZON_SE_GPIO_P1_OUT &= (ASE_TANTOS_MDIO_COMPLEMENT); -+} -+ -+void ifx_mdcs_lo(void) -+{ -+} -+ -+/* -+ mdc pulse -+ 0 -> 1 -> 0 -+*/ -+static void ifx_sw_mdc_pulse(void) -+{ -+ -+ ifx_mdc_lo(); -+ udelay(TANTOS_SW_MDC_DOWN_DELAY); -+ ifx_mdc_hi(); -+ udelay(TANTOS_SW_MDC_DOWN_DELAY); -+ ifx_mdc_lo(); -+ -+} -+ -+/* -+ mdc toggle -+ 1 -> 0 -+*/ -+static void ifx_sw_mdc_toggle(void) -+{ -+ -+ ifx_mdc_hi(); -+ udelay(TANTOS_SW_MDC_DOWN_DELAY); -+ ifx_mdc_lo(); -+ udelay(TANTOS_SW_MDC_DOWN_DELAY); -+ -+} -+ -+/* -+ enable eeprom write -+ For ATC 93C66 type EEPROM; accessing ADM6996 internal EEPROM type registers -+*/ -+static void ifx_sw_eeprom_write_enable(void) -+{ -+ // no need for ASE WAVE board -+} -+ -+/* -+ disable eeprom write -+*/ -+static void ifx_sw_eeprom_write_disable(void) -+{ -+} -+ -+ -+ -+#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added -+static int ifx_sw_read_adm6996_smi(unsigned int addr, unsigned int *dat) -+{ -+//060620:henryhsu modify for vlan addr=((addr<<16)|(1<<21))&0x3ff0000; -+ addr=(addr<<16)&0x3ff0000; -+ *AMAZON_SE_PPE32_ETOP_MDIO_ACC =(0xC0000000|addr); -+ while ((*AMAZON_SE_PPE32_ETOP_MDIO_ACC)&0x80000000){}; -+ *dat=((*AMAZON_SE_PPE32_ETOP_MDIO_ACC)&0x0FFFF); -+ return 0; -+} -+#endif -+ -+ -+static int ifx_sw_read_tantos(unsigned int addr, unsigned int *dat) -+{ -+ unsigned int op; -+ ifx_gpio_init(); -+ -+ ifx_mdcs_hi(); -+ udelay(ADM_SW_CS_DELAY); -+ -+ ifx_mdcs_lo(); -+ ifx_mdc_lo(); -+ ifx_mdio_lo(); -+ -+ udelay(ADM_SW_CS_DELAY); -+ -+ /* preamble, 32 bit 1 */ -+ ifx_mdio_hi(); -+ op = ADM_SW_BIT_MASK_32; -+ while (op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* command start (01b) */ -+ op = ADM_SW_BIT_MASK_2; -+ while (op) -+ { -+ if (op & ADM_SW_SMI_START) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* read command (10b) */ -+ op = ADM_SW_BIT_MASK_2; -+ while (op) -+ { -+ if (op & ADM_SW_SMI_READ) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* send address A9 ~ A0 */ -+ op = ADM_SW_BIT_MASK_10; -+ while (op) -+ { -+ if (op & addr) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* turnaround bits */ -+ op = ADM_SW_BIT_MASK_2; -+ ifx_mdio_hi(); -+ while (op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ udelay(ADM_SW_MDC_DOWN_DELAY); -+ -+ /* set MDIO pin to input mode */ -+ -+ ifx_mdio_mode(ADM_SW_MDIO_INPUT); -+ -+ /* start read data */ -+ -+ *dat = 0; -+ op = ADM_SW_BIT_MASK_32; -+ while (op) -+ { -+ *dat <<= 1; -+ if (ifx_sw_mdio_readbit()) *dat |= 1; -+ ifx_sw_mdc_toggle(); -+ -+ op >>= 1; -+ } -+ -+ /* set MDIO to output mode */ -+ ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); -+ -+ /* dummy clock */ -+ op = ADM_SW_BIT_MASK_4; -+ ifx_mdio_lo(); -+ while(op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ ifx_mdc_lo(); -+ ifx_mdio_lo(); -+ ifx_mdcs_hi(); -+ -+ /* EEPROM registers */ -+ *dat >>= 16; -+ -+ return 0; -+} -+ -+int ifx_sw_read(unsigned int addr, unsigned int *dat) -+{ -+//printk("ifx_sw_read\n"); -+//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin -+#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added -+ ifx_sw_read_adm6996_smi(addr,dat); -+#else -+ #ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added -+ ifx_sw_read_tantos(addr,dat); -+ #endif -+#endif -+ return 0; -+} -+ -+/* -+ write register to ADM6996 eeprom registers -+*/ -+//for adm6996i -start -+//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin -+#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added -+static int ifx_sw_write_adm6996_smi(unsigned int addr, unsigned int dat) -+{ -+//060620:henryhsu modify for vlan *DANUBE_PPE32_ETOP_MDIO_ACC = (((addr<<16)|(1<<21))&0x3ff0000)|dat|0x80000000; -+ *AMAZON_SE_PPE32_ETOP_MDIO_ACC = ((addr<<16) &0x3ff0000)|dat|0x80000000; -+ while ((*AMAZON_SE_PPE32_ETOP_MDIO_ACC )&0x80000000){}; -+ return 0; -+} -+#endif //ADM6996_MDC_MDIO_MODE //000001.joelin -+ -+static int ifx_sw_write_tantos(unsigned int addr, unsigned int dat) -+{ -+#if 1 -+ unsigned int op; -+ -+ ifx_gpio_init(); -+ -+ ifx_mdcs_hi(); -+ udelay(ADM_SW_CS_DELAY); -+ -+ ifx_mdcs_lo(); -+ ifx_mdc_lo(); -+ ifx_mdio_lo(); -+ -+ udelay(ADM_SW_CS_DELAY); -+ -+ /* preamble, 32 bit 1 */ -+ ifx_mdio_hi(); -+ op = ADM_SW_BIT_MASK_32; -+ while (op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* command start (01b) */ -+ op = ADM_SW_BIT_MASK_2; -+ while (op) -+ { -+ if (op & ADM_SW_SMI_START) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* write command (01b) */ -+ op = ADM_SW_BIT_MASK_2; -+ while (op) -+ { -+ if (op & ADM_SW_SMI_WRITE) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* send address A9 ~ A0 */ -+ op = ADM_SW_BIT_MASK_10; -+ while (op) -+ { -+ if (op & addr) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ /* turnaround bits */ -+ op = ADM_SW_BIT_MASK_2; -+ ifx_mdio_hi(); -+ while (op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ udelay(ADM_SW_MDC_DOWN_DELAY); -+ -+ /* set MDIO pin to output mode */ -+ ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); -+ -+ -+ /* start write data */ -+ op = ADM_SW_BIT_MASK_16; -+ while (op) -+ { -+ if (op & dat) -+ ifx_mdio_hi(); -+ else -+ ifx_mdio_lo(); -+ -+ ifx_sw_mdc_toggle(); -+ op >>= 1; -+ } -+ -+ // /* set MDIO to output mode */ -+ // ifx_mdio_mode(ADM_SW_MDIO_OUTPUT); -+ -+ /* dummy clock */ -+ op = ADM_SW_BIT_MASK_4; -+ ifx_mdio_lo(); -+ while(op) -+ { -+ ifx_sw_mdc_pulse(); -+ op >>= 1; -+ } -+ -+ ifx_mdc_lo(); -+ ifx_mdio_lo(); -+ ifx_mdcs_hi(); -+ -+#endif -+ return 0; -+} -+ -+int ifx_sw_write(unsigned int addr, unsigned int dat) -+{ -+//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode ////000001.joelin -+#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added -+ ifx_sw_write_adm6996_smi(addr,dat); -+#else //000001.joelin -+ #ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added -+ ifx_sw_write_tantos(addr,dat); -+ #endif //605112:fchang.added -+#endif //000001.joelin -+ return 0; -+} -+ -+/* -+ do switch PHY reset -+*/ -+int ifx_sw_reset(void) -+{ -+ /* reset PHY */ -+ ifx_sw_write(ADM_SW_PHY_RESET, 0); -+ return 0; -+} -+ -+ -+static int ifx_sw_init(void) -+{ -+ ifx_printf(("Setting default ADM6996 registers... \n")); -+ /* -+ ifx_sw_write(0x11,0xe300); -+ ifx_sw_write(0x2e,0); -+ ifx_sw_write(0x13,0x1d5); -+ ifx_sw_write(0x14,0x1d5); -+ ifx_sw_write(0x15,0x1d5); -+ ifx_sw_write(0x16,0x1d5); -+ ifx_sw_write(0x17,0x1d5); -+ ifx_sw_write(0x19,0xffd5); -+ ifx_sw_write(0x1a,0xffd5); -+ ifx_sw_write(0x1b,0xffd5); -+ */ -+ return 0; -+} -+ -+ -+int adm_open(struct inode *node, struct file *filp) -+{ -+ //MOD_INC_USE_COUNT; -+ return 0; -+} -+ -+ssize_t adm_read(struct file *filep, char *buf, size_t count, loff_t *ppos) -+{ -+ return count; -+} -+ -+ssize_t adm_write(struct file *filep, const char *buf, size_t count, loff_t *ppos) -+{ -+ return count; -+} -+ -+/* close */ -+int adm_release(struct inode *inode, struct file *filp) -+{ -+ //MOD_DEC_USE_COUNT; -+ return 0; -+} -+ -+/* IOCTL function */ -+int adm_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long args) -+{ -+ -+ PREGRW uREGRW; -+ unsigned int rtval; -+ unsigned int val; -+ unsigned int control[6] ; -+ unsigned int status[6] ; -+ -+ if (_IOC_TYPE(cmd) != ADM_MAGIC) -+ { -+ printk("adm_ioctl: IOC_TYPE(%x) != ADM_MAGIC(%x)! \n", _IOC_TYPE(cmd), ADM_MAGIC); -+ return (-EINVAL); -+ } -+ -+ if(_IOC_NR(cmd) >= KEY_IOCTL_MAX_KEY) -+ { -+ printk(KERN_WARNING "adm_ioctl: IOC_NR(%x) invalid! \n", _IOC_NR(cmd)); -+ return (-EINVAL); -+ } -+ -+ switch (cmd) -+ { -+ case ADM_IOCTL_REGRW: -+ { -+ uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); -+ rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); -+ if (rtval != 0) -+ { -+ printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); -+ return (-EFAULT); -+ } -+ -+ switch(uREGRW->mode) -+ { -+ case REG_READ: -+ uREGRW->value = 0x12345678;//inl(uREGRW->addr); -+ copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); -+ break; -+ case REG_WRITE: -+ //outl(uREGRW->value, uREGRW->addr); -+ break; -+ -+ default: -+ printk("No such Register Read/Write function!! \n"); -+ return (-EFAULT); -+ } -+ kfree(uREGRW); -+ break; -+ } -+ -+ case ADM_SW_IOCTL_REGRW: -+ { -+ unsigned int val = 0xff; -+ -+ uREGRW = (PREGRW)kmalloc(sizeof(REGRW), GFP_KERNEL); -+ rtval = copy_from_user(uREGRW, (PREGRW)args, sizeof(REGRW)); -+ if (rtval != 0) -+ { -+ printk("ADM_IOCTL_REGRW: copy from user FAILED!! \n"); -+ return (-EFAULT); -+ } -+ -+ switch(uREGRW->mode) -+ { -+ case REG_READ: -+ ifx_sw_read(uREGRW->addr, &val); -+ uREGRW->value = val; -+ copy_to_user((PREGRW)args, uREGRW, sizeof(REGRW)); -+ break; -+ -+ case REG_WRITE: -+ ifx_sw_write(uREGRW->addr, uREGRW->value); -+ break; -+ default: -+ printk("No such Register Read/Write function!! \n"); -+ return (-EFAULT); -+ } -+ kfree(uREGRW); -+ break; -+ } -+ -+ //case ADM_SW_IOCTL_INIT: -+ // ifx_sw_init(); -+ // break; -+ -+ // others -+ default: -+ return -EFAULT; -+ } -+ // end of switch -+ -+ return 0; -+} -+ -+struct file_operations adm_ops = -+{ -+ read: adm_read, -+ write: adm_write, -+ open: adm_open, -+ release: adm_release, -+ ioctl: adm_ioctl -+}; -+ -+int adm_proc(char *buf, char **start, off_t offset, int count, int *eof, void *data) -+{ -+ int len = 0; -+ -+ len += sprintf(buf+len, " ************ Registers ************ \n"); -+ *eof = 1; -+ return len; -+} -+ -+ -+ -+int __init init_adm6996_module(void) -+{ -+ unsigned int val = 000; -+ unsigned int val1 = 000; -+ -+ ifx_sw_init(); -+ -+//605112:fchang.removed #ifdef ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin -+#ifdef CONFIG_SWITCH_ADM6996_MDIO //605112:fchang.added -+ register_chrdev(69, "adm6996", &adm_ops); -+ *AMAZON_SE_PPE32_ETOP_MDIO_CFG=0; -+ *AMAZON_SE_PPE32_ENET_MAC_CFG &= ~0x18; //ENET0 MAC Configuration -+ ifx_sw_read(0xa0, &val); -+ ifx_sw_read(0xa1, &val1); -+ val=((val1&0x0f)<<16)|val; -+ printk ("\n6996I SMI Mode-"); -+ printk ("Chip ID:%5x \n ", val); -+ //ADM6996_MDC_MDIO_MODE //smi mode //000001.joelin -+#endif -+ -+#ifdef CONFIG_SWITCH_GPIO_ACCESS //605112:fchang.added -+ printk("Loading Tantos 0G GPIO driver\n"); -+ ifx_gpio_init(); -+ register_chrdev(69, "adm6996", &adm_ops); -+#endif //605112:fchang.added -+ return 0; -+} -+ -+void __exit cleanup_adm6996_module(void) -+{ -+ printk("Free 6996 device driver... \n"); -+ unregister_chrdev(69, "adm6996"); -+} -+ -+ -+static int ifx_hw_reset(void) -+{ -+ printk("Free 6996 device driver... \n"); -+ unregister_chrdev(69, "adm6996"); -+ udelay(200000); -+ ifx_sw_init(); -+ udelay(200000); -+ return init_adm6996_module(); -+} -+ -+ -+//int (*adm6996_hw_reset)(void) = ifx_hw_reset; -+//EXPORT_SYMBOL(adm6996_hw_reset); -+//int (*adm6996_sw_read)(unsigned int addr, unsigned int *data) = ifx_sw_read; -+//EXPORT_SYMBOL(adm6996_sw_read); -+//int (*adm6996_sw_write)(unsigned int addr, unsigned int data) = ifx_sw_write; -+//EXPORT_SYMBOL(adm6996_sw_write); -+ -+//EXPORT_SYMBOL(switch_model); -+EXPORT_SYMBOL(ifx_sw_read); -+EXPORT_SYMBOL(ifx_sw_write); -+ -+ -+MODULE_DESCRIPTION("ADMtek 6996 Driver"); -+MODULE_AUTHOR("Joe Lin <joe.lin@infineon.com>"); -+MODULE_LICENSE("GPL"); -+ -+module_init(init_adm6996_module); -+module_exit(cleanup_adm6996_module); -+ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h -new file mode 100644 -index 0000000..7f98fd3 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_admmod.h -@@ -0,0 +1,248 @@ -+/****************************************************************************** -+ Copyright (c) 2004, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+ ****************************************************************************** -+ Module : ifx_swdrv.h -+ Date : 2004-09-01 -+ Description : JoeLin -+ Remarks: -+ *****************************************************************************/ -+/****************************************************************************** -+** 2009/12/17 Lantiq Inc. Revised by Richard Hsu -+** Rename to amazon_se_admmod.h. -+** We use GPIO to simulate MDIO/MDC operations on AmazonSE WAVE board. -+** ASE WAVE board uses PHY2PHY connection to Tantos 0G -+** -+*******************************************************************************/ -+ -+ -+ -+ -+#ifndef _ADM_6996_MODULE_H_ -+#define _ADM_6996_MODULE_H_ -+ -+#include <asm/ifx/amazon_se/amazon_se.h> -+ -+//Wrapper for ASE GPIO setting -+#define AMAZON_SE_GPIO_P1_OUT IFX_GPIO_P1_OUT -+#define AMAZON_SE_GPIO_P1_ALTSEL0 IFX_GPIO_P1_ALTSEL0 -+#define AMAZON_SE_GPIO_P1_ALTSEL1 IFX_GPIO_P1_ALTSEL1 -+#define AMAZON_SE_GPIO_P1_DIR IFX_GPIO_P1_DIR -+#define AMAZON_SE_GPIO_P1_IN IFX_GPIO_P1_IN -+ -+#define ifx_printf(x) printk x -+ -+/* command codes */ -+#define ADM_SW_SMI_READ 0x02 -+#define ADM_SW_SMI_WRITE 0x01 -+#define ADM_SW_SMI_START 0x01 -+ -+#define ADM_SW_EEPROM_WRITE 0x01 -+#define ADM_SW_EEPROM_WRITE_ENABLE 0x03 -+#define ADM_SW_EEPROM_WRITE_DISABLE 0x00 -+#define EEPROM_TYPE 8 /* for 93C66 */ -+ -+/* bit masks */ -+#define ADM_SW_BIT_MASK_1 0x00000001 -+#define ADM_SW_BIT_MASK_2 0x00000002 -+#define ADM_SW_BIT_MASK_4 0x00000008 -+#define ADM_SW_BIT_MASK_10 0x00000200 -+#define ADM_SW_BIT_MASK_16 0x00008000 -+#define ADM_SW_BIT_MASK_32 0x80000000 -+ -+/* delay timers */ -+#define ADM_SW_MDC_DOWN_DELAY 5 -+#define ADM_SW_MDC_UP_DELAY 5 -+#define ADM_SW_CS_DELAY 5 -+ -+/* MDIO modes */ -+#define ADM_SW_MDIO_OUTPUT 1 -+#define ADM_SW_MDIO_INPUT 0 -+ -+#define ADM_SW_MAX_PORT_NUM 5 -+#define ADM_SW_MAX_VLAN_NUM 15 -+ -+/* registers */ -+#define ADM_SW_PORT0_CONF 0x1 -+#define ADM_SW_PORT1_CONF 0x3 -+#define ADM_SW_PORT2_CONF 0x5 -+#define ADM_SW_PORT3_CONF 0x7 -+#define ADM_SW_PORT4_CONF 0x8 -+#define ADM_SW_PORT5_CONF 0x9 -+#define ADM_SW_VLAN_MODE 0x11 -+#define ADM_SW_MAC_LOCK 0x12 -+#define ADM_SW_VLAN0_CONF 0x13 -+#define ADM_SW_PORT0_PVID 0x28 -+#define ADM_SW_PORT1_PVID 0x29 -+#define ADM_SW_PORT2_PVID 0x2a -+#define ADM_SW_PORT34_PVID 0x2b -+#define ADM_SW_PORT5_PVID 0x2c -+#define ADM_SW_PHY_RESET 0x2f -+#define ADM_SW_MISC_CONF 0x30 -+#define ADM_SW_BNDWDH_CTL0 0x31 -+#define ADM_SW_BNDWDH_CTL1 0x32 -+#define ADM_SW_BNDWDH_CTL_ENA 0x33 -+ -+/* port modes */ -+#define ADM_SW_PORT_FLOWCTL 0x1 /* 802.3x flow control */ -+#define ADM_SW_PORT_AN 0x2 /* auto negotiation */ -+#define ADM_SW_PORT_100M 0x4 /* 100M */ -+#define ADM_SW_PORT_FULL 0x8 /* full duplex */ -+#define ADM_SW_PORT_TAG 0x10 /* output tag on */ -+#define ADM_SW_PORT_DISABLE 0x20 /* disable port */ -+#define ADM_SW_PORT_TOS 0x40 /* TOS first */ -+#define ADM_SW_PORT_PPRI 0x80 /* port based priority first */ -+#define ADM_SW_PORT_MDIX 0x8000 /* auto MDIX on */ -+#define ADM_SW_PORT_PVID_SHIFT 10 -+#define ADM_SW_PORT_PVID_BITS 4 -+ -+/* VLAN */ -+#define ADM_SW_VLAN_PORT0 0x1 -+#define ADM_SW_VLAN_PORT1 0x2 -+#define ADM_SW_VLAN_PORT2 0x10 -+#define ADM_SW_VLAN_PORT3 0x40 -+#define ADM_SW_VLAN_PORT4 0x80 -+#define ADM_SW_VLAN_PORT5 0x100 -+ -+ -+/* GPIO 012 enabled, output mode */ -+#define GPIO_ENABLEBITS 0x000700f8 -+ -+/* -+ define AMAZON GPIO port to ADM6996 EEPROM interface -+ MDIO -> EEDI GPIO 16, AMAZON GPIO P1.0, bi-direction -+ MDC -> EESK GPIO 17, AMAZON GPIO P1.1, output only -+ MDCS -> EECS GPIO 18, AMAZON GPIO P1.2, output only -+ EEDO GPIO 15, AMAZON GPIO P0.15, do not need this one! */ -+ -+#define GPIO_MDIO 1 //P1.0 -+#define GPIO_MDC 2 //P1.1 -+#define GPIO_MDCS 4 //P1.2 -+ -+//joelin #define GPIO_MDIO 0 -+//joelin #define GPIO_MDC 5 /* PORT 0 GPIO5 */ -+//joelin #define GPIO_MDCS 6 /* PORT 0 GPIO6 */ -+ -+ -+#define MDIO_INPUT 0x00000001 -+#define MDIO_OUTPUT_EN 0x00010000 -+ -+ -+/* type definitions */ -+typedef unsigned char U8; -+typedef unsigned short U16; -+typedef unsigned int U32; -+ -+typedef struct _REGRW_ -+{ -+ unsigned int addr; -+ unsigned int value; -+ unsigned int mode; -+}REGRW, *PREGRW; -+ -+//joelin adm6996i -+typedef struct _MACENTRY_ -+{ -+ unsigned char mac_addr[6]; -+ unsigned long fid:4; -+ unsigned long portmap:6; -+ union { -+ unsigned long age_timer:9; -+ unsigned long info_ctrl:9; -+ } ctrl; -+ unsigned long occupy:1; -+ unsigned long info_type:1; -+ unsigned long bad:1; -+ unsigned long result:3;//000:command ok ,001:all entry used,010:Entry Not found ,011:try next entry ,101:command error -+ -+ }MACENTRY, *PMACENTRY; -+typedef struct _PROTOCOLFILTER_ -+{ -+ int protocol_filter_num;//[0~7] -+ int ip_p; //Value Compared with Protocol in IP Heade[7:0] -+ char action:2;//Action for protocol Filter . -+//00 = Protocol Portmap is Default Output Ports. -+//01 = Protocol Portmap is 6'b0. -+//10 = Protocol Portmap is the CPU port if the incoming port -+//is not the CPU port. But if the incoming port is the CPU port, then Type Portmap contains Default Output Ports, excluding the CPU port. -+ }PROTOCOLFILTER, *PPROTOCOLFILTER; -+ -+//joelin adm6996i -+ -+/* Santosh: for IGMP proxy/snooping */ -+ -+//050614:fchang int adm_process_mac_table_request (unsigned int cmd, struct _MACENTRY_ *mac); -+//050614:fchang int adm_process_protocol_filter_request (unsigned int cmd, struct _PROTOCOLFILTER_ *filter); -+ -+ -+/* IOCTL keys */ -+#define KEY_IOCTL_ADM_REGRW 0x01 -+#define KEY_IOCTL_ADM_SW_REGRW 0x02 -+#define KEY_IOCTL_ADM_SW_PORTSTS 0x03 -+#define KEY_IOCTL_ADM_SW_INIT 0x04 -+//for adm6996i-start -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD 0x05 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL 0x06 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT 0x07 -+#define KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE 0x08 -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD 0x09 -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL 0x0a -+#define KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET 0x0b -+ -+//adm6996i #define KEY_IOCTL_MAX_KEY 0x05 -+#define KEY_IOCTL_MAX_KEY 0x0c -+//for adm6996i-end -+/* IOCTL MAGIC */ -+#define ADM_MAGIC ('a'|'d'|'m'|'t'|'e'|'k') -+ -+/* IOCTL parameters */ -+#define ADM_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_REGRW, REGRW) -+#define ADM_SW_IOCTL_REGRW _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_REGRW, REGRW) -+#define ADM_SW_IOCTL_PORTSTS _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_PORTSTS, NULL) -+#define ADM_SW_IOCTL_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_INIT, NULL) -+ -+ -+//6996i-stat -+#define ADM_SW_IOCTL_MACENTRY_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_ADD,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_DEL,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_GET_INIT _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_INIT,MACENTRY) -+#define ADM_SW_IOCTL_MACENTRY_GET_MORE _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_MACENTRY_GET_MORE,MACENTRY) -+#define ADM_SW_IOCTL_FILTER_ADD _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_ADD,PROTOCOLFILTER) -+#define ADM_SW_IOCTL_FILTER_DEL _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_DEL,PROTOCOLFILTER) -+#define ADM_SW_IOCTL_FILTER_GET _IOWR(ADM_MAGIC, KEY_IOCTL_ADM_SW_IOCTL_FILTER_GET,PROTOCOLFILTER) -+ -+//6996i-end -+ -+ -+#define REG_READ 0x0 -+#define REG_WRITE 0x1 -+ -+/* undefine symbol */ -+//#define AMAZON_SW_REG(reg) *((volatile U32*)(reg)) -+//#define GPIO0_INPUT_MASK 0 -+//#define GPIO_conf0_REG 0x12345678 -+//#define GPIO_SET_HI -+//#define GPIO_SET_LOW -+ -+#endif -+/* _ADM_6996_MODULE_H_ */ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c -new file mode 100644 -index 0000000..847d25d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.c -@@ -0,0 +1,437 @@ -+/****************************************************************************** -+** -+** FILE NAME : amazon_se_ref_board.c -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : source file for Amazon-SE -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AUTOCONF_INCLUDED -+#include <linux/config.h> -+#endif /* AUTOCONF_INCLUDED */ -+#include <linux/module.h> -+#include <linux/types.h> -+#include <linux/kallsyms.h> -+#include <linux/mtd/mtd.h> -+#include <linux/mtd/partitions.h> -+ -+#include <asm/ifx/ifx_regs.h> -+#include <asm/ifx/ifx_types.h> -+#include <asm/ifx/ifx_board.h> -+#include <asm/ifx/irq.h> -+#include <asm/ifx/ifx_gpio.h> -+#include <asm/ifx/ifx_ledc.h> -+#include <asm/ifx/ifx_led.h> -+ -+/* -+struct ifx_si_eiu_config g_si_eiu_config = { -+ .irq = -1, // no serial input -+ .intsync = 0, -+ .sampling_clk = 0, -+ .shift_clk = 0, -+ .group = 0, -+ .active_high = 0, -+}; -+*/ -+ -+#if defined(IFX_LEDGPIO_USB_VBUS) || defined(IFX_LEDGPIO_USB_VBUS1) || defined(IFX_LEDGPIO_USB_VBUS2) -+ #undef IFX_GPIO_USB_VBUS -+ #undef IFX_GPIO_USB_VBUS1 -+ #undef IFX_GPIO_USB_VBUS2 -+#endif -+ -+// GPIO PIN to Module Mapping and default PIN configuration -+struct ifx_gpio_ioctl_pin_config g_board_gpio_pin_map[] = { -+ // module_id of last item must be IFX_GPIO_PIN_AVAILABLE -+ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 8), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR}, -+ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 9), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ {IFX_GPIO_MODULE_SSC, IFX_GPIO_PIN_ID(0, 10), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ -+ {IFX_GPIO_MODULE_SPI_FLASH, IFX_GPIO_PIN_ID(0, 7), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ -+ // XWAY ASE WAVE board doesn't support shift register -+ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 1), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 2), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LEDC, IFX_GPIO_PIN_ID(0, 3), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ -+ /* -+ * GPIO LEDs (Amazon-SE Reference Board use GPIO to control LEDs) -+ */ -+ -+ // XWAY ASE WAVE board support only 2 LED. -+ // GPIO2 for ADSL_DAT , GPIO3 for ADSL_LINK -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 1), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ {IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 2), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ {IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 3), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 4), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 12), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(0, 13), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(1, 8), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ //{IFX_GPIO_MODULE_LED, IFX_GPIO_PIN_ID(1, 11), IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ -+ /* -+ * USB -+ */ -+ #if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+ #if defined(IFX_LEDGPIO_USB_VBUS) -+ {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_VBUS, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET | IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET}, -+ #endif -+ #if defined(IFX_GPIO_USB_VBUS) -+ {IFX_GPIO_MODULE_USB, IFX_GPIO_USB_VBUS, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET | IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET}, -+ #endif -+ #endif -+ #if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) -+ {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_LED, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ #elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) -+// {IFX_GPIO_MODULE_LED, IFX_LEDGPIO_USB_LED, IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR | IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET}, -+ #endif -+ {IFX_GPIO_PIN_AVAILABLE, 0, 0}, -+}; -+EXPORT_SYMBOL(g_board_gpio_pin_map); -+ -+struct ifx_ledc_config_param g_board_ledc_hw_config = { -+ .operation_mask = IFX_LEDC_CFG_OP_UPDATE_SOURCE | IFX_LEDC_CFG_OP_BLINK | IFX_LEDC_CFG_OP_UPDATE_CLOCK | IFX_LEDC_CFG_OP_STORE_MODE | IFX_LEDC_CFG_OP_SHIFT_CLOCK | IFX_LEDC_CFG_OP_DATA_OFFSET | IFX_LEDC_CFG_OP_NUMBER_OF_LED | IFX_LEDC_CFG_OP_DATA | IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE, -+ .source_mask = 3, -+ .source = 0, // by default all LEDs controlled by LEDC DATA -+ .blink_mask = (1 << 16) - 1, -+ .blink = 0, // disable blink for all LEDs -+ .update_clock = LED_CON1_UPDATE_SRC_SOFTWARE, -+ .fpid = 0, -+ .store_mode = 0, // single store -+ .fpis = 0, -+ .data_offset = 0, -+ .number_of_enabled_led = 0, // disable LEDC -+ .data_mask = (1 << 16) - 1, -+ .data = (1 << 2), // LED2 - Power LED turn on by default -+ .mips0_access_mask = (1 << 16) - 1, -+ .mips0_access = (1 << 16) - 1, -+ .f_data_clock_on_rising = 0, // falling edge -+}; -+EXPORT_SYMBOL(g_board_ledc_hw_config); -+ -+struct ifx_led_device g_board_led_hw_config[] = { -+#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+ #if defined(IFX_LEDGPIO_USB_VBUS) -+ { -+ .name = "USB_VBUS", -+ .default_trigger = "USB_VBUS", -+ .phys_id = IFX_LEDGPIO_USB_VBUS, -+ .value_on = 1, -+ .value_off = 0, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ #endif -+#endif -+#if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) -+ { -+ .default_trigger = IFX_LED_TRIGGER_USB_LINK, -+ .phys_id = IFX_LEDGPIO_USB_LED, -+ .value_on = 0, -+ .value_off = 1, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+#elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) -+ { -+// .default_trigger = IFX_LED_TRIGGER_USB_LINK, -+// .phys_id = IFX_LEDGPIO_USB_LED, -+// .value_on = 0, -+// .value_off = 1, -+// .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+#endif -+ { -+ .name = "broadband_led", -+ //.default_trigger = IFX_LED_TRIGGER_DSL_LINK, -+ .default_trigger = NULL, -+ .phys_id = 3, -+ .value_on = 1, -+ .value_off = 0, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .name = "internet_led", -+ //.default_trigger = IFX_LED_TRIGGER_DSL_DATA, -+ .default_trigger = NULL, -+ .phys_id = 2, -+ .value_on = 1, -+ .value_off = 0, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ // XWAY ASE WAVE board supports only 2 LEDs. -+/* -+ { -+ .default_trigger = IFX_LED_TRIGGER_EPHY_LINK, -+ .phys_id = 3, -+ .value_on = 1, -+ .value_off = 0, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .default_trigger = IFX_LED_TRIGGER_EPHY_SPEED, -+ .phys_id = 4, -+ .value_on = 1, -+ .value_off = 0, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .default_trigger = IFX_LED_TRIGGER_WAN_STATUS, -+ .phys_id = 12, -+ .value_on = 0, -+ .value_off = 1, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .default_trigger = IFX_LED_TRIGGER_POWER_ON, -+ .phys_id = 13, -+ .value_on = 0, -+ .value_off = 1, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .default_trigger = IFX_LED_TRIGGER_WARNING, -+ .phys_id = 24, -+ .value_on = 0, -+ .value_off = 1, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+ { -+ .default_trigger = IFX_LED_TRIGGER_USB_LINK, -+ .phys_id = 27, -+ .value_on = 0, -+ .value_off = 1, -+ .flags = IFX_LED_DEVICE_FLAG_PHYS_GPIO, -+ }, -+*/ -+ { -+ .flags = IFX_LED_DEVICE_FLAG_INVALID, -+ } -+}; -+EXPORT_SYMBOL(g_board_led_hw_config); -+ -+ -+#ifdef CONFIG_MTD_IFX_NOR -+ -+#if (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 2) -+#define IFX_MTD_NOR_PARTITION_SIZE 0x001B0000 -+const struct mtd_partition g_ifx_mtd_nor_partitions[] = { -+ { -+ .name = "U-Boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00020000, //128K -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "firmware", /* firmware */ -+ .offset = 0x00020000, -+ .size = 0x00030000, //192K -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "rootfs,kernel,Data,Environment", /* default partition */ -+ .offset = 0x00050000, -+ .size = IFX_MTD_NOR_PARTITION_SIZE, -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+}; -+#elif (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 4) -+#define IFX_MTD_NOR_PARTITION_SIZE 0x003C0000 -+const struct mtd_partition g_ifx_mtd_nor_partitions[] = { -+ { -+ .name = "U-Boot", -+ .offset = 0x00000000, -+ .size = 0x00010000, -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "Firmware", -+ .offset = 0x00010000, -+ .size = 0x00030000, -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "RootFS,Kernel,Data,Environment", /* default partition */ -+ .offset = 0x00040000, -+ .size = IFX_MTD_NOR_PARTITION_SIZE, -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+}; -+#elif (CONFIG_MTD_IFX_NOR_FLASH_SIZE == 8) -+#define IFX_MTD_NOR_PARTITION_SIZE 0x007A0000 -+const struct mtd_partition g_ifx_mtd_nor_partitions[] = { -+ { -+ .name = "U-Boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00020000, //128K -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "firmware", /* firmware */ -+ .offset = 0x00020000, -+ .size = 0x00040000, //256K -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "rootfs,kernel,Data,Environment", /* default partition */ -+ .offset = 0x00060000, -+ .size = IFX_MTD_NOR_PARTITION_SIZE, -+/* .mask_flags = MTD_WRITEABLE, force read-only */ -+ }, -+}; -+#else -+#error "Configure MTD NOR flash size first!!" -+#endif -+const int g_ifx_mtd_partion_num = ARRAY_SIZE(g_ifx_mtd_nor_partitions); -+ -+EXPORT_SYMBOL(g_ifx_mtd_nor_partitions); -+EXPORT_SYMBOL(g_ifx_mtd_partion_num); -+#endif /* CONFIG_IFX_MTD_NOR */ -+/*fix me, need more concept to define the partitions, and need add partition for 2M*/ -+#if defined(CONFIG_MTD_IFX_NAND) && !defined(CONFIG_MTD_CMDLINE_PARTS) -+ -+const struct mtd_partition g_ifx_mtd_nand_partitions[] = { -+#if (CONFIG_MTD_IFX_NAND_FLASH_SIZE == 4) -+ { -+ .name = "U-Boot", -+ .offset = 0x00000000, -+ .size = 0x00008000, -+ }, -+ { -+ .name = "kernel", -+ .offset = 0x00080000, -+ .size = 0x00100000, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x00180000, -+ .size = 0x00220000, -+ }, -+ -+#elif (CONFIG_MTD_IFX_NAND_FLASH_SIZE == 8) -+ { -+ .name = "U-Boot", -+ .offset = 0x00000000, -+ .size = 0x00080000, -+ }, -+ { -+ .name = "kernel", -+ .offset = 0x00080000, -+ .size = 0x00200000, -+ }, -+ { -+ .name = "rootfs", -+ .offset = 0x00280000, -+ .size = 0x00510000, -+ }, -+#endif -+}; -+const int g_ifx_mtd_nand_partion_num = ARRAY_SIZE(g_ifx_mtd_nand_partitions); -+EXPORT_SYMBOL(g_ifx_mtd_nand_partion_num); -+EXPORT_SYMBOL(g_ifx_mtd_nand_partitions); -+#endif /* CONFIG_MTD_IFX_NAND */ -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) -+/* -+ * spi flash partition information -+ * Here are partition information for all known series devices. -+ * See include/linux/mtd/partitions.h for definition of the mtd_partition -+ * structure. -+ */ -+#define IFX_MTD_SPI_PARTITION_2MB_SIZE 0x001B0000 -+#define IFX_MTD_SPI_PARTITION_4MB_SIZE 0x003A0000 -+ -+const struct mtd_partition g_ifx_mtd_spi_partitions[IFX_SPI_FLASH_MAX][IFX_MTD_SPI_PART_NB] = { -+ {{0, 0, 0}}, -+ -+/* 256K Byte */ -+ {{ -+ .name = "spi-boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00040000, /* 256 */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, {0}, {0}, -+ }, -+ -+/* 512K Byte */ -+ {{0, 0, 0}}, -+ -+/* 1M Byte */ -+ {{ -+ .name = "spi-boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00010000, /* 64K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-firmware", /* firmware */ -+ .offset = 0x00010000, -+ .size = 0x00030000, /* 64K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ -+ .offset = 0x00030000, -+ .size = 0x000C0000, -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }}, -+ -+/* 2M Byte */ -+ {{ -+ .name = "spi-boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00020000, /* 128K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-firmware", /* firmware */ -+ .offset = 0x00020000, -+ .size = 0x00030000, /* 192K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ -+ .offset = 0x00050000, -+ .size = IFX_MTD_SPI_PARTITION_2MB_SIZE, -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }}, -+ -+/* 4M Byte */ -+ {{ -+ .name = "spi-boot", /* U-Boot firmware */ -+ .offset = 0x00000000, -+ .size = 0x00020000, /* 128K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-firmware", /* firmware */ -+ .offset = 0x00020000, -+ .size = 0x00040000, /* 256K */ -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }, -+ { -+ .name = "spi-rootfs,kernel,Data,Environment", /* default partition */ -+ .offset = 0x00060000, -+ .size = IFX_MTD_SPI_PARTITION_4MB_SIZE, -+ /* mask_flags: MTD_WRITEABLE, force read-only */ -+ }}, -+}; -+EXPORT_SYMBOL(g_ifx_mtd_spi_partitions); -+ -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h -new file mode 100644 -index 0000000..1f193b1 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/amazon_se_ref_board.h -@@ -0,0 +1,55 @@ -+/****************************************************************************** -+** -+** FILE NAME : amazon_se_ref_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Amazon-SE -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AMAZON_SE_REF_BOARD_H -+#define AMAZON_SE_REF_BOARD_H -+#ifndef AUTOCONF_INCLUDED -+#include <linux/config.h> -+#endif /* AUTOCONF_INCLUDED */ -+ -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 6 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+ #if 1 // Control VBus through LED abstract layer -+ #define IFX_LEDGPIO_USB_VBUS IFX_GPIO_PIN_ID(1, 7) -+ #else // Control VBus through GPIO driver directly -+ #define IFX_GPIO_USB_VBUS IFX_GPIO_PIN_ID(1, 7) -+ #endif -+#endif -+ -+#if (defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE)) && defined(CONFIG_USB_HOST_IFX_LED) -+// #define IFX_LEDGPIO_USB_LED IFX_GPIO_PIN_ID(1, 11) -+#elif (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) -+// #define IFX_LEDGPIO_USB_LED IFX_GPIO_PIN_ID(1, 11) -+#endif -+ -+ -+ -+#endif /* AMAZON_SE_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/amazon_se/boards/boards.h b/arch/mips/include/asm/ifx/amazon_se/boards/boards.h -new file mode 100644 -index 0000000..3a31400 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/boards/boards.h -@@ -0,0 +1,4 @@ -+#if defined(CONFIG_AMAZON_SE_REF_BOARD) -+# include "./amazon_se_ref_board.h" -+#endif -+ -diff --git a/arch/mips/include/asm/ifx/amazon_se/irq.h b/arch/mips/include/asm/ifx/amazon_se/irq.h -new file mode 100644 -index 0000000..885b8d2 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/irq.h -@@ -0,0 +1,116 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Amazon-SE -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AMAZON_SE_IRQ -+#define AMAZON_SE_IRQ -+ -+ -+ -+/****** Interrupt Assigments ***********/ -+ -+#define IFX_ASC1_TIR INT_NUM_IM2_IRL0 // INT_NUM_IM0_IRL0 -+#define IFX_ASC1_TBIR INT_NUM_IM2_IRL1 // INT_NUM_IM0_IRL1 -+#define IFX_ASC1_RIR INT_NUM_IM2_IRL2 // INT_NUM_IM0_IRL2 -+#define IFX_ASC1_EIR INT_NUM_IM2_IRL3 // INT_NUM_IM0_IRL3 -+#define IFX_ASC1_ABSTIR INT_NUM_IM2_IRL4 // INT_NUM_IM0_IRL4 -+#define IFX_ASC1_ABDETIR INT_NUM_IM2_IRL5 // INT_NUM_IM0_IRL5 -+#define IFX_ASC1_SFCIR INT_NUM_IM2_IRL6 // INT_NUM_IM0_IRL6 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM2_IRL7 // INT_NUM_IM0_IRL7 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM2_IRL8 // INT_NUM_IM0_IRL8 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_DSL_DFE_IR INT_NUM_IM2_IRL9 // INT_NUM_IM0_IRL9 -+#define IFX_DSL_AFEOVL_IR INT_NUM_IM2_IRL10 // INT_NUM_IM0_IRL10 -+#define IFX_DSL_DYING_GASP_INT INT_NUM_IM2_IRL11 // INT_NUM_IM0_IRL11 -+#define IFX_DSL_DFE_INT0IR INT_NUM_IM1_IRL16 // INT_NUM_IM3_IRL16 -+#define IFX_DSL_DFE_INT1IR INT_NUM_IM1_IRL17 // INT_NUM_IM3_IRL17 -+#define IFX_DSL_DFE_INT2IR INT_NUM_IM1_IRL18 // INT_NUM_IM3_IRL18 -+#define IFX_DSL_DFE_INT3IR INT_NUM_IM1_IRL19 // INT_NUM_IM3_IRL19 -+#define IFX_MEI_INT IFX_DSL_DFE_IR -+#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT -+#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR -+#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM3_IRL0 // INT_NUM_IM1_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM3_IRL1 // INT_NUM_IM1_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM3_IRL2 // INT_NUM_IM1_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM3_IRL3 // INT_NUM_IM1_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM3_IRL4 // INT_NUM_IM1_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM3_IRL5 // INT_NUM_IM1_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM3_IRL6 // INT_NUM_IM1_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM3_IRL7 // INT_NUM_IM1_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM3_IRL8 // INT_NUM_IM1_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM3_IRL9 // INT_NUM_IM1_IRL9 -+ -+#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL12 // INT_NUM_IM0_IRL12 -+#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL13 // INT_NUM_IM0_IRL13 -+#define IFX_PPE_MBOX_INT2 INT_NUM_IM2_IRL14 // INT_NUM_IM0_IRL14 -+#define IFX_PPE_QSB_INT INT_NUM_IM2_IRL15 // INT_NUM_IM0_IRL15 -+ -+#define IFX_EPHY_INT INT_NUM_IM3_IRL29 // INT_NUM_IM1_IRL29 -+ -+#define IFX_EIU_IR0 INT_NUM_IM2_IRL21 // INT_NUM_IM0_IRL21 -+#define IFX_EIU_IR1 INT_NUM_IM0_IRL22 // INT_NUM_IM2_IRL22 -+#define IFX_EIU_IR2 INT_NUM_IM2_IRL23 // INT_NUM_IM0_IRL23 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM2_IRL25 // INT_NUM_IM0_IRL25 -+#define IFX_GPTU_TC1B INT_NUM_IM2_IRL26 // INT_NUM_IM0_IRL26 -+#define IFX_GPTU_TC2A INT_NUM_IM2_IRL27 // INT_NUM_IM0_IRL27 -+#define IFX_GPTU_TC2B INT_NUM_IM2_IRL28 // INT_NUM_IM0_IRL28 -+#define IFX_GPTU_TC3A INT_NUM_IM2_IRL29 // INT_NUM_IM0_IRL29 -+#define IFX_GPTU_TC3B INT_NUM_IM2_IRL30 // INT_NUM_IM0_IRL30 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL24 // INT_NUM_IM1_IRL24 -+ -+#define IFX_EBU_IR INT_NUM_IM2_IRL24 // INT_NUM_IM0_IRL24 -+ -+#define IFX_PMC_HIT_IR INT_NUM_IM3_IRL25 // INT_NUM_IM1_IRL25 -+#define IFX_PMC_MISS_IR INT_NUM_IM3_IRL23 // INT_NUM_IM1_IRL23 -+#define IFX_PMCIR IFX_PMC_HIT_IR -+ -+#define IFX_SBIU_ERRIR INT_NUM_IM3_IRL26 // INT_NUM_IM1_IRL26 -+ -+#define IFX_SSC_RIR INT_NUM_IM2_IRL16 // INT_NUM_IM0_IRL16 -+#define IFX_SSC_TIR INT_NUM_IM2_IRL17 // INT_NUM_IM0_IRL17 -+#define IFX_SSC_EIR INT_NUM_IM2_IRL18 // INT_NUM_IM0_IRL18 -+#define IFX_SSC_FIR INT_NUM_IM2_IRL19 // INT_NUM_IM0_IRL19 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM1_IRL20 // INT_NUM_IM3_IRL20 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM1_IRL21 // INT_NUM_IM3_IRL21 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM1_IRL22 // INT_NUM_IM3_IRL22 -+ -+#define IFX_USB0_IR INT_NUM_IM2_IRL31 // INT_NUM_IM0_IRL31 -+#define IFX_USB0_OCIR INT_NUM_IM2_IRL20 // INT_NUM_IM0_IRL20 -+#define IFX_USB_INT IFX_USB0_IR -+#define IFX_USB_OC_INT IFX_USB0_OCIR -+ -+#define IFX_WDT_PIR INT_NUM_IM3_IRL27 // INT_NUM_IM1_IRL27 -+#define IFX_WDT_AEIR INT_NUM_IM3_IRL28 // INT_NUM_IM1_IRL28 -+ -+ -+ -+#endif // AMAZON_SE_IRQ -diff --git a/arch/mips/include/asm/ifx/amazon_se/model.h b/arch/mips/include/asm/ifx/amazon_se/model.h -new file mode 100644 -index 0000000..58fd0c8 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/amazon_se/model.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Amazon-SE -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AMAZON_SE_MODEL_H -+#define AMAZON_SE_MODEL_H -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define BOARD_SYSTEM_TYPE "Amazon-SE" -+#define SYSTEM_MODEL_NAME "Amazon-SE Reference Board" -+#endif -diff --git a/arch/mips/include/asm/ifx/ar10/ar10.h b/arch/mips/include/asm/ifx/ar10/ar10.h -new file mode 100644 -index 0000000..2da2d82 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar10/ar10.h -@@ -0,0 +1,1705 @@ -+/****************************************************************************** -+** -+** FILE NAME : ar10.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR10 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR10_H -+#define AR10_H -+ -+#include <asm/bootinfo.h> -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define MACH_GROUP_IFX MACH_GROUP_AR10 -+#define MACH_TYPE_IFX MACH_AR10 -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ -+ -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_RCU_USB0_CFG ((volatile u32*)(IFX_RCU + 0x0018)) -+#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) -+#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) -+#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) -+#define IFX_RCU_PCI_BOOT_READY ((volatile u32*)(IFX_RCU + 0x0028)) -+#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) -+#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) -+#define IFX_RCU_USB1_CFG ((volatile u32*)(IFX_RCU + 0x0034)) -+#define IFX_RCU_USB_AFE_CFG_1A ((volatile u32*)(IFX_RCU + 0x0038)) -+#define IFX_RCU_USB_AFE_CFG_1B ((volatile u32*)(IFX_RCU + 0x003C)) -+#define IFX_RCU_USB_AFE_CFG_2A ((volatile u32*)(IFX_RCU + 0x0040)) -+#define IFX_RCU_USB_AFE_CFG_2B ((volatile u32*)(IFX_RCU + 0x0044)) -+#define IFX_RCU_SLIC_USB_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) -+ -+/* AHB Endian Register */ -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+ -+#define IFX_RCU_BE_AHB4S 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_BE_AHB3M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define IFX_RCU_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ -+#define IFX_RCU_BE_AHB2S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ -+#define IFX_RCU_BE_PCIE0S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in big endian */ -+#define IFX_RCU_BE_PCIE0_DBI 0x00000020 /* Configure DBI module in big endian */ -+#define IFX_RCU_BE_DCDC_PDI 0x00000040 /* Configure DC PDI module in big endian */ -+#define IFX_RCU_BE_PCIE0_PDI 0x00000080 /* Configure PCIE PDI module in big endian */ -+#define IFX_RCU_BE_PCIE1S 0x00000100 /* Configure AHB slave port that connects to PCIe1 RC in big endian */ -+#define IFX_RCU_BE_PCIE1_DBI 0x00000200 /* Configure DBI1 module in big endian */ -+#define IFX_RCU_BE_PCIE1_PDI 0x00000400 /* Configure PCIE1 PDI module in big endian */ -+#define IFX_RCU_BE_AHB1S 0x00000800 /* Configure PCIE1 PDI module in big endian */ -+#define IFX_RCU_BE_PCIE0M 0x00001000 /* RC0 Master as big endian */ -+#define IFX_RCU_BE_PCIE1M 0x00002000 /* RC1 Master as big endian */ -+ -+#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) -+#define IFX_RCU_GPHY1_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0068)) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ_SRST (1 << 30) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL IFX_RCU_RST_REQ_SRST -+ -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MEI register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) -+#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) -+ -+/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -+#if 0 -+#define MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) -+#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) -+ -+ -+#define MEI_VERSION ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) -+#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_TO_ARC_INT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) -+#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_CLK_CONTROL ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_RST_CONTROL ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) -+#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DBG_MASTER ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_DEC ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_RAD ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_WAD ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DEBUG_DATA ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XFR_ADDR ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DATA_XFR ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_DATA_XFR_STAT ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_MAX_WAIT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_ARC_GP_STAT ((volatile u32*)(0x004C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XDATA_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR0 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR1 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR2 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR3 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR4 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR5 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR6 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR7 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR8 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR9 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR10 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR11 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR12 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR13 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR14 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR15 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) -+#define MEI_XMEM_BAR16 ((volatile u32*)(0x0098 + IFX_MEI_SPACE_ACCESS)) -+//#else -+#define ME_VERSION ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) -+#define ME_ARC2ME_STAT ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define ME_ARC2ME_MASK ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) -+#define ME_ME2ARC_INT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) -+#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) -+#define ME_CLK_CTRL ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) -+#define ME_RST_CTRL ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) -+#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_MASTER ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_DECODE ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_RD_AD ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_WR_AD ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DBG_DATA ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_AD ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_DATA ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_STAT ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) -+#define ME_DX_MWS ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) -+#define ME_ARC_GP_STAT ((volatile u32*)(0x004C + IFX_MEI_SPACE_ACCESS)) -+#define ME_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XDATA_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR0 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR1 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR2 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR3 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR4 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR5 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR6 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR7 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR8 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR9 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR10 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR11 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR12 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR13 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR14 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR15 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) -+#define ME_XMEM_BAR16 ((volatile u32*)(0x0098 + IFX_MEI_SPACE_ACCESS)) -+#endif -+ -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 2 Data Output Register (0070H)***/ -+#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) -+/***Port 3 Data Output Register (00A0H)***/ -+#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 2 Data Input Register (0074H)***/ -+#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) -+/***Port 3 Data Input Register (00A4H)***/ -+#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 2 Direction Register (0078H)***/ -+#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) -+/***Port 3 Direction Register (0048H)***/ -+#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 2 Alternate Function Select Register 0 (007C H) ***/ -+#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) -+/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ -+#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ -+#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) -+/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ -+#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 2 Open Drain Control Register (0084H)***/ -+#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) -+/***Port 3 Open Drain Control Register (0034H)***/ -+#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ -+#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) -+/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ -+ -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ -+#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) -+/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ -+#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+/***Port 2 Pull Up Device Enable Register (0090 H)***/ -+#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) -+/***Port 3 Pull Up Device Enable Register (003c H)***/ -+#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU CGU Clock Frequency Select Register***/ -+#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) -+/**Update CGU Register***/ -+#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) -+/***CGU Interface Clock Control Register***/ -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) -+/***CGU PCI Clock Control Register**/ -+#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0038)) -+ -+#define IFX_PCI_CLK_SHIFT 20 -+#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ -+ -+#define IFX_PCI_CLK_FROM_CGU 0x80000000 -+#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 -+#define IFX_PCI_DELAY_SHIFT 21 -+#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) -+ -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x16000000) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL0_REGEN (1 << 0) -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL2_REGEN (1 << 0) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) -+#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL3_REGEN (1 << 0) -+ -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) -+ -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+#define IFX_EBU_BUSCON1_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_PG_EN 0x20000000 -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+ }; -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+ }; -+ -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+ -+#define IFX_EBU_BUSCON1_WRDIS (1 << 31) -+//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) -+//#define IFX_EBU_BUSCON1_SETUP (1 << 18) -+//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+#define IFX_EBU_BUSCON2_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON2_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON2_SETUP (1 << 18) -+#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) -+#define IFX_EBU_BUSCON3_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) -+#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) -+#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON3_SETUP (1 << 22) -+#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON3_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON3_VN_EN (1 << 18) -+#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) -+#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) -+#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/* PC-Card Configuration */ -+#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) -+#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 -+#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 -+#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 -+#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 -+#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 -+#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A -+#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C -+ -+#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) -+#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) -+#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) -+#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 -+ -+#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) -+#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) -+ -+#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) -+#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENALBE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+ }; -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+ }; -+ -+#define IFX_EBU_NAND_WAIT_RD (0x1) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+ -+/***********************************************************************/ -+/* Module : HSNAND register address and bits */ -+/***********************************************************************/ -+#define IFX_NAND (KSEG1 | 0x16000100) -+ -+#define IFX_NDAC_CTL_1 (volatile u32 *)(IFX_NAND + 0x0010) -+#define IFX_NDAC_CTL_2 (volatile u32 *)(IFX_NAND + 0x0014) -+#define EBU_INT_MSK_CTL (volatile u32 *)(IFX_NAND + 0x0024) -+#define EBU_INT_STAT (volatile u32 *)(IFX_NAND + 0x0028) -+#define IFX_HSMD_CTL (volatile u32 *)(IFX_NAND + 0x0030) -+#define IFX_ND_PARA0 (volatile u32 *)(IFX_NAND + 0x003C) -+#define IFX_ND_ODD_ECC (volatile u32 *)(IFX_NAND + 0x0040) -+#define IFX_ND_ODD_ECC1 (volatile u32 *)(IFX_NAND + 0x0044) -+#define IFX_ND_EVEN_ECC (volatile u32 *)(IFX_NAND + 0x0048) -+#define IFX_ND_EVEN_ECC1 (volatile u32 *)(IFX_NAND + 0x004C) -+ -+#define IFX_NAND_TYPE_S 18 -+#define IFX_NAND_TYPE 0x00040000 -+#define IFX_NAND_PCOUNT_S 10 -+#define IFX_NAND_PCOUNT 0x0003FC00 -+#define IFX_NAND_PLANE_MODE_S 9 -+#define IFX_NAND_PLANE_MODE 0x00000200 -+#define IFX_NAND_ECC_MODE_S 8 -+#define IFX_NAND_ECC_MODE 0x00000100 -+#define IFX_NAND_ECC_LOC_S 7 -+#define IFX_NAND_ECC_LOC 0x00000080 -+#define IFX_NAND_ECC_STRENGTH_S 6 -+#define IFX_NAND_ECC_STRENGTH 0x00000040 -+#define IFX_NAND_PIB_S 4 -+#define IFX_NAND_PIB 0x00000030 -+#define IFX_NAND_PAGE_SIZE_S 0 -+#define IFX_NAND_PAGE_SIZE 0x0000000F -+ -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+/***MC Status Register***/ -+#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) -+ -+/***MC DDR Control Register 00***/ -+#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) -+/***MC DDR Control Register 03***/ -+#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) -+/***MC DDR Control Register 17***/ -+#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+/***ASC Clock Control Register***/ -+#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) -+#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_ASC1_CLC_DISS (1 << 1) -+#define IFX_ASC1_CLC_DISR (1 << 0) -+ -+/***ASC Port Input Select Register***/ -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL_RIS (1 << 0) -+ -+/***ASC Control Register***/ -+#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) -+#define IFX_ASC1_CON_BEN (1 << 20) -+#define IFX_ASC1_CON_TOEN (1 << 20) -+#define IFX_ASC1_CON_ROEN (1 << 19) -+#define IFX_ASC1_CON_RUEN (1 << 18) -+#define IFX_ASC1_CON_FEN (1 << 17) -+#define IFX_ASC1_CON_PAL (1 << 16) -+#define IFX_ASC1_CON_R (1 << 15) -+#define IFX_ASC1_CON_ACO (1 << 14) -+#define IFX_ASC1_CON_LB (1 << 13) -+#define IFX_ASC1_CON_ERCLK (1 << 10) -+#define IFX_ASC1_CON_FDE (1 << 9) -+#define IFX_ASC1_CON_BRS (1 << 8) -+#define IFX_ASC1_CON_STP (1 << 7) -+#define IFX_ASC1_CON_SP (1 << 6) -+#define IFX_ASC1_CON_ODD (1 << 5) -+#define IFX_ASC1_CON_PEN (1 << 4) -+#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***ASC Staus Register***/ -+#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) -+/***ASC Write Hardware Modified Control Register***/ -+#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) -+#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) -+#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) -+#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) -+#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) -+#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) -+#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) -+#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) -+#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) -+#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) -+#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) -+#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) -+#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) -+#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) -+ -+/***ASC Baudrate Timer/Reload Register***/ -+#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) -+#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) -+ -+/***ASC Fractional Divider Register***/ -+#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Transmit Buffer Register***/ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Receive Buffer Register***/ -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Autobaud Control Register***/ -+#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) -+#define IFX_ASC1_ABCON_RXINV (1 << 11) -+#define IFX_ASC1_ABCON_TXINV (1 << 10) -+#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -+#define IFX_ASC1_ABCON_FCDETEN (1 << 4) -+#define IFX_ASC1_ABCON_ABDETEN (1 << 3) -+#define IFX_ASC1_ABCON_ABSTEN (1 << 2) -+#define IFX_ASC1_ABCON_AUREN (1 << 1) -+#define IFX_ASC1_ABCON_ABEN (1 << 0) -+ -+/***Receive FIFO Control Register***/ -+#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) -+#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) -+#define IFX_ASC1_RXFCON_RXFEN (1 << 0) -+ -+/***Transmit FIFO Control Register***/ -+#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) -+#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) -+#define IFX_ASC1_TXFCON_TXFEN (1 << 0) -+ -+/***FIFO Status Register***/ -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -+#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+/***ASC Autobaud Status Register***/ -+#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) -+#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) -+#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) -+#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) -+#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) -+#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) -+ -+/***ASC Write HW Modified Autobaud Status Register***/ -+#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) -+#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) -+#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) -+#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) -+#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) -+#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) -+#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) -+#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) -+#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) -+#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) -+#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) -+ -+/***ASC IRNCR0 **/ -+#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) -+#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) -+/***ASC IRNCR1 **/ -+#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) -+#define IFX_ASC_IRNCR_TIR 0x1 -+#define IFX_ASC_IRNCR_RIR 0x2 -+#define IFX_ASC_IRNCR_EIR 0x4 -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) -+ -+#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) -+#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) -+#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) -+#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) -+#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) -+#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) -+ -+#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) -+ -+#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) -+#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) -+/* Global Software Reset (0) */ -+#define IFX_DMA_CTRL_RST (0x1) -+ -+/* Channel Polling Register */ -+ -+/* Enable (31) */ -+#define IFX_DMA_CPOLL_EN (0x1 << 31) -+#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) -+ -+/* Counter (15:4) */ -+#define IFX_DMA_CPOLL_CNT (0xfff << 4) -+#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) -+ -+/* Channel Control Register */ -+ -+/* Peripheral to Peripheral Copy (24) */ -+#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) -+#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) -+#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) -+ -+/* Channel Weight for Transmit Direction (17:16) */ -+#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) -+#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) -+#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) -+ -+/* Port Assignment (13:11) */ -+#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) -+#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) -+ -+/* Class (10:9) */ -+#define IFX_DMA_CCTRL_CLASS (0x3 << 9) -+#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) -+#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) -+ -+/* Direction (8) */ -+#define IFX_DMA_CCTRL_DIR (0x1 << 8) -+/* Reset (1) */ -+#define IFX_DMA_CCTRL_RST (0x1 << 1) -+/* Channel On or Off (0) */ -+#define IFX_DMA_CCTRL_ON (0x1) -+ -+/* Channel Interrupt Status Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIS_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIS_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt (3) */ -+#define IFX_DMA_CIS_DESCPT (0x1 << 3) -+/* Descriptor Under-Run Interrupt (2) */ -+#define IFX_DMA_CIS_DUR (0x1 << 2) -+/* End of Packet Interrupt (1) */ -+#define IFX_DMA_CIS_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ -+ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ -+ IFX_DMA_CIS_EOP) -+ -+/* Channel Interrupt Enable Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIE_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIE_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt Enable (3) */ -+#define IFX_DMA_CIE_DESCPT (0x1 << 3) -+/* Descriptor Under Run Interrupt Enable (2) */ -+#define IFX_DMA_CIE_DUR (0x1 << 2) -+/* End of Packet Interrupt Enable (1) */ -+#define IFX_DMA_CIE_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) -+ -+/* Port Select Register */ -+ -+/* Port Selection (2:0) */ -+#define IFX_DMA_PS_PS (0x7) -+#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) -+ -+/* Port Control Register */ -+ -+/* General Purpose Control (16) */ -+#define IFX_DMA_PCTRL_GPC (0x1 << 16) -+#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) -+ -+/* Port Weight for Transmit Direction (14:12) */ -+#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) -+#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) -+/* Endianness for Transmit Direction (11:10) */ -+#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) -+#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) -+/* Endianness for Receive Direction (9:8) */ -+#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) -+#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) -+/* Packet Drop Enable (6) */ -+#define IFX_DMA_PCTRL_PDEN (0x1 << 6) -+#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) -+/* Burst Length for Transmit Direction (5:4) */ -+#define IFX_DMA_PCTRL_TXBL (0x3 << 4) -+#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) -+/* Burst Length for Receive Direction (3:2) */ -+#define IFX_DMA_PCTRL_RXBL (0x3 << 2) -+#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+ -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+ -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+ -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+ -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) -+ -+/***********************************************************************/ -+ -+#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) -+#define IFX_ICU1 IFX_ICU_VPE1 -+ -+#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) -+#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) -+#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) -+#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) -+#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) -+ -+#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) -+#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) -+#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) -+#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) -+#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) -+ -+#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) -+#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) -+#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) -+#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) -+#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) -+ -+#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) -+#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) -+#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) -+#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) -+#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) -+ -+#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) -+#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) -+#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) -+#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) -+#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) -+#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) -+#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC -+ -+/* MSI PIC */ -+#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) -+ -+#define IFX_MSI1_PIC_REG_BASE (KSEG1 | 0x1F500000) -+ -+#define IFX_MSI_PIC_BIG_ENDIAN 1 -+#define IFX_MSI_PIC_LITTLE_ENDIAN 0 -+ -+#define IFX_MSI_PCI_INT_DISABLE 0x80000000 -+#define IFX_MSI_PIC_INT_LINE 0x30000000 -+#define IFX_MSI_PIC_INT_LINE_S 28 -+#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 -+#define IFX_MSI_PIC_MSG_ADDR_S 16 -+#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF -+#define IFX_MSI_PIC_MSG_DATA_S 0x0 -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) -+#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) -+#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) -+#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) -+#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1 | 0x1F101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) -+#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) -+#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) -+#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) -+ -+ -+/* voice channel 0 ... 3 interrupt enable register */ -+#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) -+#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) -+#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) -+#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) -+/* voice channel 0 ... 3 interrupt status read register */ -+#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) -+#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) -+#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) -+#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) -+/* voice channel 0 ... 3 interrupt status set register */ -+#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) -+#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) -+#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) -+#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) -+/* voice channel 0 ... 3 interrupt status clear register */ -+#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) -+#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) -+#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) -+#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) -+/* common status 0 and 1 read register */ -+#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) -+#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) -+/* common status 0 and 1 set register */ -+#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) -+#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) -+/* common status 0 and 1 clear register */ -+#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) -+#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) -+/* common status 0 and 1 enable register */ -+#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) -+#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) -+/* notification enable register */ -+#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) -+#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) -+/* CPU to CPU interrup request register */ -+#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) -+#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) -+/* Global interrupt request and request enable register */ -+#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) -+#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) -+ -+#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) -+ -+#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) -+ -+#define IFX_FUSE_ID_CFG ((volatile u32*)(KSEG1 | 0x1F107350)) -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+ -+ -+/************************************************************************/ -+/* Module : DEU register address and bits */ -+/************************************************************************/ -+ -+#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) -+ -+/* DEU Control Register */ -+#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) -+#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) -+ -+/* DEU control register */ -+#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) -+#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) -+#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) -+#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) -+#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) -+#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) -+#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) -+#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) -+#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) -+#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) -+#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+ -+/* AES DEU register */ -+#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) -+#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) -+#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) -+#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) -+ -+/* AES Key register */ -+#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) -+#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) -+#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) -+#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) -+#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) -+#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) -+#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) -+#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) -+ -+/* AES vector register */ -+#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) -+#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) -+#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) -+#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) -+#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) -+#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) -+#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) -+#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) -+ -+/* ARC4 DEU register */ -+#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) -+#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) -+#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) -+#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) -+#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) -+#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) -+ -+/* ARC4 Key register */ -+#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) -+#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) -+#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) -+#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) -+ -+/* ARC4 vector register */ -+#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) -+#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) -+#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) -+#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) -+ -+/* hash control register */ -+#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) -+#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) -+#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) -+#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) -+#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) -+#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) -+#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) -+ -+#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) -+#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) -+#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) -+ -+#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) -+ -+#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) -+#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) -+#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) -+ -+ -+ -+/************************************************************************/ -+/* Module : PPE register address and bits */ -+/************************************************************************/ -+ -+#define IFX_PPE32_BASE (KSEG1 | 0x1E200000) -+#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) -+#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) -+#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) -+#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) -+ -+#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) -+ -+/* -+ * ETOP MDIO Registers -+ */ -+#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -+#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -+#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -+#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -+#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -+#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -+#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -+#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -+#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -+#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -+#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -+#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -+#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -+#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -+#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -+#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -+#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -+#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -+#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -+#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) -+ -+#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -+#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -+#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -+#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -+#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -+#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -+#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) -+ -+#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -+#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -+#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -+#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -+#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -+#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) -+ -+ -+/* Sharebuff SB RAM2 control data */ -+#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) -+#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) -+ -+ -+#if 0 // AR10 has 7 port switch inherited from VR9 -+/************************************************************************/ -+/* Module : 3-port Switch register address and bits */ -+/************************************************************************/ -+ -+#define IFX_SW (KSEG1 | 0x1E108000) -+ -+#define IFX_SW_PS (IFX_SW + 0x000) -+#define IFX_SW_P0_CTL (IFX_SW + 0x004) -+#define IFX_SW_P1_CTL (IFX_SW + 0x008) -+#define IFX_SW_P2_CTL (IFX_SW + 0x00C) -+#define IFX_SW_P0_VLAN (IFX_SW + 0x010) -+#define IFX_SW_P1_VLAN (IFX_SW + 0x014) -+#define IFX_SW_P2_VLAN (IFX_SW + 0x018) -+#define IFX_SW_P0_INCTL (IFX_SW + 0x020) -+#define IFX_SW_P1_INCTL (IFX_SW + 0x024) -+#define IFX_SW_P2_INCTL (IFX_SW + 0x028) -+#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) -+#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) -+#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) -+#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) -+#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) -+#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) -+#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) -+#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) -+#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) -+#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) -+#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) -+#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) -+#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) -+#define IFX_SW_INT_ENA (IFX_SW + 0x060) -+#define IFX_SW_INT_ST (IFX_SW + 0x064) -+#define IFX_SW_GCTL0 (IFX_SW + 0x068) -+#define IFX_SW_GCTL1 (IFX_SW + 0x06C) -+#define IFX_SW_ARP (IFX_SW + 0x070) -+#define IFX_SW_STRM_CTL (IFX_SW + 0x074) -+#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) -+#define IFX_SW_1P_PRT (IFX_SW + 0x07C) -+#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) -+#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) -+#define IFX_SW_BF_TH (IFX_SW + 0x088) -+#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) -+#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) -+#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) -+#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) -+#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) -+#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) -+#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) -+#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) -+#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) -+#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) -+#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) -+#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) -+#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) -+#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) -+#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) -+#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) -+#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) -+#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) -+#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) -+#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) -+#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) -+#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) -+#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) -+#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) -+#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) -+#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) -+#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) -+#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) -+#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) -+#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) -+#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) -+#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) -+#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) -+#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) -+#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) -+#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) -+#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) -+#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) -+#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) -+#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) -+#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) -+#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) -+#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) -+#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) -+#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) -+#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) -+#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) -+#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) -+#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) -+#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) -+#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) -+#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) -+#define IFX_SW_RA_03_00 (IFX_SW + 0x180) -+#define IFX_SW_RA_07_04 (IFX_SW + 0x184) -+#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) -+#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) -+#define IFX_SW_RA_13_10 (IFX_SW + 0x190) -+#define IFX_SW_RA_17_14 (IFX_SW + 0x194) -+#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) -+#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) -+#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) -+#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) -+#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) -+#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) -+#define IFX_SW_F0 (IFX_SW + 0x1B0) -+#define IFX_SW_F1 (IFX_SW + 0x1B4) -+#endif -+ -+/************************************************************************/ -+/* Module : XBAR Register definition */ -+/************************************************************************/ -+#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) -+ -+#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) -+#define IFX_XBAR_FPI_BURST_EN 0x00000002 -+#define IFX_XBAR_AHB_BURST_EN 0x00000004 -+ -+/* -+ * Routine for Voice -+ */ -+extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); -+ -+#endif /* AR10_H */ -diff --git a/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h b/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h -new file mode 100644 -index 0000000..12fcac7 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar10/ar10_ref_board.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : ar10_ref_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR10 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR10_REF_BOARD_H -+#define AR10_REF_BOARD_H -+#ifndef AUTOCONF_INCLUDED -+#include <linux/config.h> -+#endif /* AUTOCONF_INCLUDED */ -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ -+ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 8 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+#if defined(CONFIG_AR10_FAMILY_BOARD_1_1) -+ #define IFX_LEDLED_USB_VBUS1 19 -+ #define IFX_LEDLED_USB_VBUS2 16 -+#endif -+ -+#if defined(CONFIG_AR10_FAMILY_BOARD_1_2) -+ #define IFX_LEDLED_USB_VBUS1 4 -+ #define IFX_LEDLED_USB_VBUS2 7 -+#endif -+ -+#endif -+ -+ -+ -+#endif /* AR10_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ar10/emulation.h b/arch/mips/include/asm/ifx/ar10/emulation.h -new file mode 100644 -index 0000000..e26ea1f ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar10/emulation.h -@@ -0,0 +1,46 @@ -+/****************************************************************************** -+** -+** FILE NAME : emulation.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Lei Chuan Hua -+** DESCRIPTION : header file for AR10 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Lei Chuan Hua The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef EMULATION_H -+#define EMULATION_H -+ -+#ifdef CONFIG_USE_EMULATOR -+ -+#ifdef CONFIG_USE_VENUS -+ #define EMULATOR_CPU_SPEED 4000000 //3333333 -+ #define PLL0_CLK_SPEED 2500000 -+#elif defined(CONFIG_USE_PALLADIUM) -+ #define EMULATOR_CPU_SPEED 120000 -+ #define PLL0_CLK_SPEED 120000 -+#else -+ #define EMULATOR_CPU_SPEED 25000 -+ #define PLL0_CLK_SPEED 25000 -+#endif /* CONFIG_USE_VENUS */ -+#else /* Real chip */ -+ #define PLL0_CLK_SPEED 1000000000 -+#endif /* CONFIG_USE_EMULATOR */ -+#endif /* */ -+ /* EMULATION_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ar10/irq.h b/arch/mips/include/asm/ifx/ar10/irq.h -new file mode 100644 -index 0000000..1af143e ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar10/irq.h -@@ -0,0 +1,214 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR10 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR10_IRQ_H -+#define AR10_IRQ_H -+ -+ -+ -+/****** Interrupt Assigments ***********/ -+ -+#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ -+#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ -+#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ -+#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ -+#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 -+#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 -+#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 -+#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 -+#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 -+#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 -+#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 -+#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 -+#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 -+#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 -+#define IFX_DSL_SI INT_NUM_IM2_IRL20 -+#define IFX_DSL_WAKEUP INT_NUM_IM2_IRL22 -+#define IFX_MEI_INT IFX_DSL_DFE_IR -+#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT -+#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR -+#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR -+ -+#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 -+#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 -+#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 -+#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 -+#define IFX_PCIE_IR INT_NUM_IM4_IRL25 -+#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 -+#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 -+#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 -+#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 -+#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 -+#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 -+ -+#define IFX_PCIE1_INTA INT_NUM_IM0_IRL9 -+#define IFX_PCIE1_INTB INT_NUM_IM0_IRL10 -+#define IFX_PCIE1_INTC INT_NUM_IM0_IRL11 -+#define IFX_PCIE1_INTD INT_NUM_IM0_IRL12 -+#define IFX_PCIE1_IR INT_NUM_IM1_IRL17 -+#define IFX_PCIE1_WAKE INT_NUM_IM1_IRL18 -+#define IFX_PCIE1_MSI_IR0 INT_NUM_IM1_IRL9 -+#define IFX_PCIE1_MSI_IR1 INT_NUM_IM1_IRL10 -+#define IFX_PCIE1_MSI_IR2 INT_NUM_IM1_IRL11 -+#define IFX_PCIE1_MSI_IR3 INT_NUM_IM1_IRL12 -+#define IFX_PCIE1_L3_INT INT_NUM_IM1_IRL13 -+ -+#define IFX_VOICE_DFE0_CH0_RX INT_NUM_IM4_IRL12 -+#define IFX_VOICE_DFE0_CH0_TX INT_NUM_IM4_IRL13 -+#define IFX_VOICE_DFE0_CH0_GP INT_NUM_IM0_IRL31 -+#define IFX_VOICE_DFE0_CH1_RX INT_NUM_IM3_IRL19 -+#define IFX_VOICE_DFE0_CH1_TX INT_NUM_IM3_IRL20 -+#define IFX_VOICE_DFE0_CH1_GP INT_NUM_IM3_IRL14 -+#define IFX_VOICE_DFE1_CH0_RX INT_NUM_IM1_IRL3 -+#define IFX_VOICE_DFE1_CH0_TX INT_NUM_IM1_IRL4 -+#define IFX_VOICE_DFE1_CH0_GP INT_NUM_IM1_IRL5 -+#define IFX_VOICE_DFE1_CH1_RX INT_NUM_IM1_IRL6 -+#define IFX_VOICE_DFE1_CH1_TX INT_NUM_IM1_IRL7 -+#define IFX_VOICE_DFE1_CH1_GP INT_NUM_IM1_IRL8 -+ -+#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 -+#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 -+#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 -+#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 -+#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 -+#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 -+#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 -+#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 -+#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 -+#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 -+#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 -+#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 -+#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 -+#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 -+#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 -+#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 -+#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 -+#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 -+#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 -+#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 -+#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 -+#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 -+#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 -+ -+#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 -+#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 -+#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 -+#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 -+ -+#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 -+ -+#define IFX_GPHY_CD_INT INT_NUM_IM3_IRL17 -+#define IFX_GPHY_INT INT_NUM_IM3_IRL18 -+ -+#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ -+#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ -+#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ -+#define IFX_EIU_IR3 INT_NUM_IM1_IRL1 /* 33 */ -+#define IFX_EIU_IR4 INT_NUM_IM1_IRL2 /* 34 */ -+ -+#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 -+#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 -+#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 -+#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 -+#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 -+#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 -+#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 -+#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 -+#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 -+#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 -+#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 -+ -+#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 -+#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 -+#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 -+#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 -+#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 -+#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL28 -+ -+#define IFX_EBU_IR INT_NUM_IM0_IRL22 -+ -+#define IFX_PCI_IR INT_NUM_IM1_IRL17 -+#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 -+ -+#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 -+#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 -+ -+#define IFX_PMCIR INT_NUM_IM4_IRL31 -+ -+#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 -+ -+#define IFX_SSC_RIR INT_NUM_IM0_IRL14 -+#define IFX_SSC_TIR INT_NUM_IM0_IRL15 -+#define IFX_SSC_EIR INT_NUM_IM0_IRL16 -+#define IFX_SSC_FIR INT_NUM_IM0_IRL17 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 -+ -+#define IFX_USB0_IR INT_NUM_IM1_IRL22 -+#define IFX_USB1_IR INT_NUM_IM1_IRL16 -+#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 -+#define IFX_USB1_OCIR INT_NUM_IM1_IRL24 // same as IFX_DSL_AFEOVL_IR -+#define IFX_USB_INT IFX_USB0_IR -+#define IFX_USB_OC_INT IFX_USB0_OCIR -+ -+#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 -+ -+#define IFX_OVD_INT INT_NUM_IM3_IRL15 -+#define IFX_PSU_INT INT_NUM_IM3_IRL30 -+ -+#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 -+#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 -+#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 -+#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 -+#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 -+#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 -+ -+ -+#endif // AR10_IRQ_H -+ -diff --git a/arch/mips/include/asm/ifx/ar10/model.h b/arch/mips/include/asm/ifx/ar10/model.h -new file mode 100644 -index 0000000..9ddcba0 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar10/model.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR10 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR10_MODEL_H -+#define AR10_MODEL_H -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define BOARD_SYSTEM_TYPE "AR10" -+#define SYSTEM_MODEL_NAME "AR10 First Version" -+#endif -diff --git a/arch/mips/include/asm/ifx/ar9/ar9.h b/arch/mips/include/asm/ifx/ar9/ar9.h -new file mode 100644 -index 0000000..f359985 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar9/ar9.h -@@ -0,0 +1,1327 @@ -+/****************************************************************************** -+** -+** FILE NAME : ar9.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR9_H -+#define AR9_H -+#include <asm/bootinfo.h> -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define MACH_GROUP_IFX MACH_GROUP_AR9 -+#define MACH_TYPE_IFX MACH_AR9 -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) -+#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) -+ -+/***Reset Request Register***/ -+#define IFX_RCU_RST_REQ_SRST (1 << 30) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_PPE (1 << 8) -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL IFX_RCU_RST_REQ_SRST -+ -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MEI register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) -+#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) -+ -+/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -+#define IFX_MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_ARC_TO_MEI_INT ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) -+ -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) // only valid for first 3 ports (0-2) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 2 Data Output Register (0070H)***/ -+#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) -+/***Port 3 Data Output Register (00A0H)***/ -+#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 2 Data Input Register (0074H)***/ -+#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) -+/***Port 3 Data Input Register (00A4H)***/ -+#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 2 Direction Register (0078H)***/ -+#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) -+/***Port 3 Direction Register (0048H)***/ -+#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 2 Alternate Function Select Register 0 (007C H) ***/ -+#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) -+/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ -+#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ -+#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) -+/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ -+#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 2 Open Drain Control Register (0084H)***/ -+#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) -+/***Port 3 Open Drain Control Register (0034H)***/ -+#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ -+#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) -+/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ -+// not available -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ -+#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) -+/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ -+#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+/***Port 2 Pull Up Device Enable Register (0090 H)***/ -+#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) -+/***Port 3 Pull Up Device Enable Register (003c H)***/ -+#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) -+ -+#define IFX_CGU_SYS_SEL 0x00000018 -+#define IFX_CGU_SYS_SEL_S 3 -+#define IFX_CGU_SYS_SEL_333 0 -+#define IFX_CGU_SYS_SEL_393 2 -+ -+/**Update CGU Register***/ -+#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0014)) -+/***CGU Interface Clock Register***/ -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) -+/***CGU SDRAM Memory Control Register***/ -+#define IFX_CGU_SMD ((volatile u32*)(IFX_CGU + 0x0020)) -+/***CGU CT Status Register 1***/ -+#define IFX_CGU_CT1SR ((volatile u32*)(IFX_CGU + 0x0028)) -+/***CGU CT Kval Register***/ -+#define IFX_CGU_CT_KVAL ((volatile u32*)(IFX_CGU + 0x002C)) -+/***CGU PCM Control Register***/ -+#define IFX_CGU_PCMCR ((volatile u32*)(IFX_CGU + 0x0030)) -+/***CGU PCI Clock Control Register***/ -+#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) -+ -+#define IFX_PCI_CLK_SHIFT 20 -+#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ -+ -+#define IFX_PCI_CLK_FROM_CGU 0x80000000 -+#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 -+#define IFX_PCI_DELAY_SHIFT 21 -+#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x1E105300) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL0_REGEN (1 << 0) -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL2_REGEN (1 << 0) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) -+#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL3_REGEN (1 << 0) -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) -+ -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_PG_EN 0x20000000 -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+}; -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+#define IFX_EBU_BUSCON1_WRDIS (1 << 31) -+//#define IFX_EBU_BUSCON1_ALEC (value) (((( 1 << 2) - 1) & (value)) << 29) -+//#define IFX_EBU_BUSCON1_BCGEN (value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON1_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+//#define IFX_EBU_BUSCON1_WAITRDC (value) (((( 1 << 7) - 1) & (value)) << 9) -+//#define IFX_EBU_BUSCON1_WAITWRC (value) (((( 1 << 3) - 1) & (value)) << 6) -+//#define IFX_EBU_BUSCON1_HOLDC (value) (((( 1 << 2) - 1) & (value)) << 4) -+//#define IFX_EBU_BUSCON1_RECOVC (value) (((( 1 << 2) - 1) & (value)) << 2) -+//#define IFX_EBU_BUSCON1_CMULT (value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+#define IFX_EBU_BUSCON2_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON2_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON2_SETUP (1 << 18) -+#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) -+#define IFX_EBU_BUSCON3_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) -+#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) -+#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON3_SETUP (1 << 22) -+#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON3_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON3_VN_EN (1 << 18) -+#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) -+#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) -+#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/* PC Card Control Register */ -+#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) -+#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 -+#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 -+#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 -+#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 -+#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 -+#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A -+#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C -+ -+#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) -+#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) -+#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) -+#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 -+ -+#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) -+#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) -+ -+#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+}; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+}; -+ -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+}; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+}; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+}; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+}; -+#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) -+#define IFX_EBU_NAND_WAIT_RD (0x1) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+ -+ -+ -+ -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+/***MC Status Register***/ -+#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) -+ -+/***MC DDR Control Register 00***/ -+#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) -+/***MC DDR Control Register 03***/ -+#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) -+/***MC DDR Control Register 17***/ -+#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) -+ -+ -+/***********************************************************************/ -+/* Module : ASC0 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC0 (KSEG1 | 0x1E100400) -+ -+#define IFX_ASC0_TBUF ((volatile u32*)(IFX_ASC0 + 0x0020)) -+#define IFX_ASC0_RBUF ((volatile u32*)(IFX_ASC0 + 0x0024)) -+#define IFX_ASC0_FSTAT ((volatile u32*)(IFX_ASC0 + 0x0048)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) -+ -+#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) -+#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) -+#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) -+#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) -+#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) -+#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) -+ -+#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) -+ -+#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) -+#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+ -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+ -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+ -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+ -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) -+ -+/***********************************************************************/ -+ -+#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) -+#define IFX_ICU1 IFX_ICU_VPE1 -+ -+#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) -+#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) -+#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) -+#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) -+#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) -+ -+#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) -+#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) -+#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) -+#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) -+#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) -+ -+#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) -+#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) -+#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) -+#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) -+#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) -+ -+#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) -+#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) -+#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) -+#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) -+#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) -+ -+#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) -+#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) -+#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) -+#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) -+#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) -+#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) -+#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) -+#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) -+#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) -+#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) -+ -+#define IFX_ICU_IM0_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM0_IER_IR(value) (1 << (value)) -+#define IFX_ICU_IM1_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM1_IER_IR(value) (1 << (value)) -+#define IFX_ICU_IM2_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM2_IER_IR(value) (1 << (value)) -+#define IFX_ICU_IM3_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM3_IER_IR(value) (1 << (value)) -+#define IFX_ICU_IM4_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM4_IER_IR(value) (1 << (value)) -+#define IFX_ICU_IM5_ISR_IR(value) (1 << (value)) -+#define IFX_ICU_IM5_IER_IR(value) (1 << (value)) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1 | 0x1F101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) -+#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) -+#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) -+#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) -+ -+ -+/* voice channel 0 ... 3 interrupt enable register */ -+#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) -+#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) -+#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) -+#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) -+/* voice channel 0 ... 3 interrupt status read register */ -+#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) -+#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) -+#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) -+#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) -+/* voice channel 0 ... 3 interrupt status set register */ -+#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) -+#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) -+#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) -+#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) -+/* voice channel 0 ... 3 interrupt status clear register */ -+#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) -+#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) -+#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) -+#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) -+/* common status 0 and 1 read register */ -+#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) -+#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) -+/* common status 0 and 1 set register */ -+#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) -+#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) -+/* common status 0 and 1 clear register */ -+#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) -+#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) -+/* common status 0 and 1 enable register */ -+#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) -+#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) -+/* notification enable register */ -+#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) -+#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) -+/* CPU to CPU interrup request register */ -+#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) -+#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) -+/* Global interrupt request and request enable register */ -+#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) -+#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) -+ -+#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) -+ -+#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) -+ -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+ -+ -+/************************************************************************/ -+/* Module : DEU register address and bits */ -+/************************************************************************/ -+ -+#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) -+ -+/* DEU Control Register */ -+#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) -+#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) -+ -+/* DEU control register */ -+#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) -+#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) -+#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) -+#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) -+#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) -+#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) -+#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) -+#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) -+#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) -+#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) -+#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+ -+/* AES DEU register */ -+#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) -+#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) -+#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) -+#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) -+ -+/* AES Key register */ -+#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) -+#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) -+#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) -+#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) -+#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) -+#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) -+#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) -+#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) -+ -+/* AES vector register */ -+#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) -+#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) -+#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) -+#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) -+#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) -+#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) -+#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) -+#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) -+ -+/* ARC4 DEU register */ -+#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) -+#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) -+#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) -+#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) -+#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) -+#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) -+ -+/* ARC4 Key register */ -+#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) -+#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) -+#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) -+#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) -+ -+/* ARC4 vector register */ -+#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) -+#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) -+#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) -+#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) -+ -+/* hash control register */ -+#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) -+#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) -+#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) -+#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) -+#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) -+#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) -+#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) -+ -+#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) -+#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) -+#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) -+ -+#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) -+ -+#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) -+#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) -+#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) -+ -+ -+ -+/************************************************************************/ -+/* Module : PPE register address and bits */ -+/************************************************************************/ -+ -+#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) -+#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) -+#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) -+#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) -+#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) -+ -+#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) -+ -+/* -+ * ETOP MDIO Registers -+ */ -+#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -+#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -+#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -+#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -+#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -+#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -+#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -+#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -+#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -+#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -+#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -+#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -+#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -+#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -+#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -+#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -+#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -+#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -+#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -+#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) -+ -+#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -+#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -+#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -+#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -+#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -+#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -+#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) -+ -+#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -+#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -+#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -+#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -+#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -+#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) -+ -+ -+/* Sharebuff SB RAM2 control data */ -+#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) -+#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) -+ -+ -+ -+/************************************************************************/ -+/* Module : 3-port Switch register address and bits */ -+/************************************************************************/ -+ -+#define IFX_SW (KSEG1 | 0x1E108000) -+ -+#define IFX_SW_PS (IFX_SW + 0x000) -+#define IFX_SW_P0_CTL (IFX_SW + 0x004) -+#define IFX_SW_P1_CTL (IFX_SW + 0x008) -+#define IFX_SW_P2_CTL (IFX_SW + 0x00C) -+#define IFX_SW_P0_VLAN (IFX_SW + 0x010) -+#define IFX_SW_P1_VLAN (IFX_SW + 0x014) -+#define IFX_SW_P2_VLAN (IFX_SW + 0x018) -+#define IFX_SW_P0_INCTL (IFX_SW + 0x020) -+#define IFX_SW_P1_INCTL (IFX_SW + 0x024) -+#define IFX_SW_P2_INCTL (IFX_SW + 0x028) -+#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) -+#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) -+#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) -+#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) -+#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) -+#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) -+#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) -+#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) -+#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) -+#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) -+#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) -+#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) -+#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) -+#define IFX_SW_INT_ENA (IFX_SW + 0x060) -+#define IFX_SW_INT_ST (IFX_SW + 0x064) -+#define IFX_SW_GCTL0 (IFX_SW + 0x068) -+#define IFX_SW_GCTL1 (IFX_SW + 0x06C) -+#define IFX_SW_ARP (IFX_SW + 0x070) -+#define IFX_SW_STRM_CTL (IFX_SW + 0x074) -+#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) -+#define IFX_SW_1P_PRT (IFX_SW + 0x07C) -+#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) -+#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) -+#define IFX_SW_BF_TH (IFX_SW + 0x088) -+#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) -+#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) -+#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) -+#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) -+#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) -+#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) -+#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) -+#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) -+#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) -+#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) -+#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) -+#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) -+#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) -+#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) -+#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) -+#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) -+#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) -+#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) -+#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) -+#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) -+#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) -+#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) -+#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) -+#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) -+#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) -+#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) -+#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) -+#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) -+#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) -+#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) -+#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) -+#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) -+#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) -+#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) -+#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) -+#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) -+#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) -+#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) -+#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) -+#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) -+#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) -+#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) -+#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) -+#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) -+#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) -+#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) -+#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) -+#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) -+#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) -+#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) -+#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) -+#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) -+#define IFX_SW_RA_03_00 (IFX_SW + 0x180) -+#define IFX_SW_RA_07_04 (IFX_SW + 0x184) -+#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) -+#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) -+#define IFX_SW_RA_13_10 (IFX_SW + 0x190) -+#define IFX_SW_RA_17_14 (IFX_SW + 0x194) -+#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) -+#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) -+#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) -+#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) -+#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) -+#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) -+#define IFX_SW_F0 (IFX_SW + 0x1B0) -+#define IFX_SW_F1 (IFX_SW + 0x1B4) -+ -+/* -+ * Routine for Voice -+ */ -+extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); -+ -+ -+#endif /* AR9_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h b/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h -new file mode 100644 -index 0000000..b37710d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar9/ar9_ref_board.h -@@ -0,0 +1,48 @@ -+/****************************************************************************** -+** -+** FILE NAME : ar9_ref_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR9_REF_BOARD_H -+#define AR9_REF_BOARD_H -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 8 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+ #if defined(CONFIG_IFX_GW188) -+// #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(2, 5) -+ #else -+// #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(1, 13) -+ #endif -+// #define IFX_GPIO_USB_VBUS2 IFX_GPIO_PIN_ID(3, 4) -+#endif -+ -+#if (defined(CONFIG_USB_GADGET_IFX) || defined(CONFIG_USB_GADGET_IFX_MODULE)) && defined(CONFIG_USB_GADGET_IFX_LED) -+ #define IFX_LEDLED_USB_LED 10 -+#endif -+ -+#endif /* AR9_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ar9/irq.h b/arch/mips/include/asm/ifx/ar9/irq.h -new file mode 100644 -index 0000000..3c8cd28 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar9/irq.h -@@ -0,0 +1,176 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR9_IRQ_H -+#define AR9_IRQ_H -+ -+ -+ -+/****** Interrupt Assigments ***********/ -+ -+#define IFX_ASC0_TIR INT_NUM_IM3_IRL0 /* TX interrupt */ -+#define IFX_ASC0_TBIR INT_NUM_IM3_IRL1 /* TX buffer interrupt */ -+#define IFX_ASC0_RIR INT_NUM_IM3_IRL2 /* RX interrupt */ -+#define IFX_ASC0_EIR INT_NUM_IM3_IRL3 /* ERROR interrupt */ -+#define IFX_ASC0_ABSTIR INT_NUM_IM3_IRL4 -+#define IFX_ASC0_ABDETIR INT_NUM_IM3_IRL5 -+#define IFX_ASC0_SFCIR INT_NUM_IM3_IRL6 -+#define IFX_ASC0_MIR INT_NUM_IM3_IRL21 -+#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ -+#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ -+#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ -+#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ -+#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 -+#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 -+#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 -+#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 -+#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 -+#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 -+#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 -+#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 -+#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 -+#define IFX_MEI_INT IFX_DSL_DFE_IR -+#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT -+#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR -+#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR -+ -+#define IFX_VOICE_DFE0_CH0_RX INT_NUM_IM4_IRL12 -+#define IFX_VOICE_DFE0_CH0_TX INT_NUM_IM4_IRL13 -+#define IFX_VOICE_DFE0_CH0_GP INT_NUM_IM0_IRL31 -+#define IFX_VOICE_DFE0_CH1_RX INT_NUM_IM3_IRL19 -+#define IFX_VOICE_DFE0_CH1_TX INT_NUM_IM3_IRL20 -+#define IFX_VOICE_DFE0_CH1_GP INT_NUM_IM3_IRL14 -+#define IFX_VOICE_DFE1_CH0_RX INT_NUM_IM1_IRL3 -+#define IFX_VOICE_DFE1_CH0_TX INT_NUM_IM1_IRL4 -+#define IFX_VOICE_DFE1_CH0_GP INT_NUM_IM1_IRL5 -+#define IFX_VOICE_DFE1_CH1_RX INT_NUM_IM1_IRL6 -+#define IFX_VOICE_DFE1_CH1_TX INT_NUM_IM1_IRL7 -+#define IFX_VOICE_DFE1_CH1_GP INT_NUM_IM1_IRL8 -+ -+#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 -+#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 -+#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 -+#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 -+#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 -+#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 -+#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 -+#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 -+#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 -+#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 -+#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 -+#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 -+#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 -+#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 -+ -+#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 -+#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 -+#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 -+#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 -+ -+#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 -+ -+#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ -+#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ -+#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ -+#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ -+#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ -+#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ -+ -+#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ -+#define IFX_SI_EIU_IR IFX_EIU_IR6 -+ -+#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 -+#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 -+#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 -+#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 -+#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 -+#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 -+#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 -+#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 -+#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 -+#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 -+#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 -+ -+#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 -+#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 -+#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 -+#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 -+#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 -+#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL28 -+ -+#define IFX_EBU_IR INT_NUM_IM0_IRL22 -+ -+#define IFX_PCI_IR INT_NUM_IM1_IRL17 -+#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 -+ -+#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 -+#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 -+ -+#define IFX_PMCIR INT_NUM_IM4_IRL31 -+ -+#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 -+ -+#define IFX_SSC_RIR INT_NUM_IM0_IRL14 -+#define IFX_SSC_TIR INT_NUM_IM0_IRL15 -+#define IFX_SSC_EIR INT_NUM_IM0_IRL16 -+#define IFX_SSC_FIR INT_NUM_IM0_IRL17 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 -+ -+#define IFX_VLYNQ_IR INT_NUM_IM2_IRL20 -+ -+#define IFX_USB0_IR INT_NUM_IM1_IRL22 -+#define IFX_USB1_IR INT_NUM_IM2_IRL19 -+#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 -+#define IFX_USB_INT IFX_USB0_IR -+#define IFX_USB_OC_INT IFX_USB0_OCIR -+ -+ -+ -+#endif // AR9_IRQ_H -diff --git a/arch/mips/include/asm/ifx/ar9/model.h b/arch/mips/include/asm/ifx/ar9/model.h -new file mode 100644 -index 0000000..2717929 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ar9/model.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for AR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef AR9_MODEL_H -+#define AR9_MODEL_H -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define BOARD_SYSTEM_TYPE "AR9" -+#define SYSTEM_MODEL_NAME "AR9 First Version" -+#endif -diff --git a/arch/mips/include/asm/ifx/common_routines.h b/arch/mips/include/asm/ifx/common_routines.h -new file mode 100644 -index 0000000..85733e2 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/common_routines.h -@@ -0,0 +1,221 @@ -+/****************************************************************************** -+** -+** FILE NAME : common_routines.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : common header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef COMMON_ROUTINES_H -+#define COMMON_ROUTINES_H -+ -+ -+ -+#include <asm/ifx/ifx_types.h> -+ -+ -+ -+/* -+ * Array Help Macro -+ */ -+#define NUM_ENTITY(x) (sizeof(x) / sizeof(*(x))) -+ -+/* Always report fatal error */ -+#define IFX_KASSERT(exp, msg) do { \ -+ if (unlikely(!(exp))) { \ -+ printk msg; \ -+ BUG(); \ -+ } \ -+} while (0) -+ -+ -+/* -+ * find first 1 from MSB in a 32-bit word -+ * if all ZERO, return -1 -+ * e.g. 0x10000000 => 28 -+ */ -+static inline IFX_int32_t clz(IFX_uint32_t x) -+{ -+ __asm__ ( -+ " .set push \n" -+ " .set mips32 \n" -+ " clz %0, %1 \n" -+ " .set pop \n" -+ : "=r" (x) -+ : "r" (x)); -+ -+ return 31 - (IFX_int32_t)x; -+} -+ -+/* -+ * find first 0 from MSB in a 32-bit word -+ * if all ONE, return -1 -+ * e.g. 0xF0000000 => 27 -+ */ -+static inline IFX_int32_t clo(IFX_uint32_t x) -+{ -+ __asm__ ( -+ " .set push \n" -+ " .set mips32 \n" -+ " clo %0, %1 \n" -+ " .set pop \n" -+ : "=r" (x) -+ : "r" (x)); -+ -+ return 31 - (IFX_int32_t)x; -+} -+ -+/* Tail queue declarations */ -+#define TAILQ_HEAD(name, type) \ -+struct name { \ -+ struct type *tqh_first; /* first element */ \ -+ struct type **tqh_last; /* addr of last next element */ \ -+} -+ -+#define TAILQ_HEAD_INITIALIZER(head) \ -+ { NULL, &(head).tqh_first } -+ -+#define TAILQ_ENTRY(type) \ -+struct { \ -+ struct type *tqe_next; /* next element */ \ -+ struct type **tqe_prev; /* address of previous next element */ \ -+} -+/* -+ * Tail queue functions. -+ */ -+#define TAILQ_CONCAT(head1, head2, field) do { \ -+ if (!TAILQ_EMPTY(head2)) { \ -+ *(head1)->tqh_last = (head2)->tqh_first; \ -+ (head2)->tqh_first->field.tqe_prev = (head1)->tqh_last; \ -+ (head1)->tqh_last = (head2)->tqh_last; \ -+ TAILQ_INIT((head2)); \ -+ } \ -+} while (0) -+ -+#define TAILQ_EMPTY(head) ((head)->tqh_first == NULL) -+ -+#define TAILQ_FIRST(head) ((head)->tqh_first) -+ -+#define TAILQ_FOREACH(var, head, field) \ -+ for ((var) = TAILQ_FIRST((head)); \ -+ (var); \ -+ (var) = TAILQ_NEXT((var), field)) -+ -+#define TAILQ_FOREACH_SAFE(var, head, field, tvar) \ -+ for ((var) = TAILQ_FIRST((head)); \ -+ (var) && ((tvar) = TAILQ_NEXT((var), field), 1); \ -+ (var) = (tvar)) -+ -+#define TAILQ_FOREACH_REVERSE(var, head, headname, field) \ -+ for ((var) = TAILQ_LAST((head), headname); \ -+ (var); \ -+ (var) = TAILQ_PREV((var), headname, field)) -+ -+#define TAILQ_FOREACH_REVERSE_SAFE(var, head, headname, field, tvar) \ -+ for ((var) = TAILQ_LAST((head), headname); \ -+ (var) && ((tvar) = TAILQ_PREV((var), headname, field), 1); \ -+ (var) = (tvar)) -+ -+#define TAILQ_INIT(head) do { \ -+ TAILQ_FIRST((head)) = NULL; \ -+ (head)->tqh_last = &TAILQ_FIRST((head)); \ -+} while (0) -+ -+#define TAILQ_INSERT_AFTER(head, listelm, elm, field) do { \ -+ if ((TAILQ_NEXT((elm), field) = TAILQ_NEXT((listelm), field)) != NULL)\ -+ TAILQ_NEXT((elm), field)->field.tqe_prev = \ -+ &TAILQ_NEXT((elm), field); \ -+ else { \ -+ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ -+ } \ -+ TAILQ_NEXT((listelm), field) = (elm); \ -+ (elm)->field.tqe_prev = &TAILQ_NEXT((listelm), field); \ -+} while (0) -+ -+#define TAILQ_INSERT_BEFORE(listelm, elm, field) do { \ -+ (elm)->field.tqe_prev = (listelm)->field.tqe_prev; \ -+ TAILQ_NEXT((elm), field) = (listelm); \ -+ *(listelm)->field.tqe_prev = (elm); \ -+ (listelm)->field.tqe_prev = &TAILQ_NEXT((elm), field); \ -+} while (0) -+ -+#define TAILQ_INSERT_HEAD(head, elm, field) do { \ -+ if ((TAILQ_NEXT((elm), field) = TAILQ_FIRST((head))) != NULL) \ -+ TAILQ_FIRST((head))->field.tqe_prev = \ -+ &TAILQ_NEXT((elm), field); \ -+ else \ -+ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ -+ TAILQ_FIRST((head)) = (elm); \ -+ (elm)->field.tqe_prev = &TAILQ_FIRST((head)); \ -+} while (0) -+ -+#define TAILQ_INSERT_TAIL(head, elm, field) do { \ -+ TAILQ_NEXT((elm), field) = NULL; \ -+ (elm)->field.tqe_prev = (head)->tqh_last; \ -+ *(head)->tqh_last = (elm); \ -+ (head)->tqh_last = &TAILQ_NEXT((elm), field); \ -+} while (0) -+ -+#define TAILQ_LAST(head, headname) \ -+ (*(((struct headname *)((head)->tqh_last))->tqh_last)) -+ -+#define TAILQ_NEXT(elm, field) ((elm)->field.tqe_next) -+ -+#define TAILQ_PREV(elm, headname, field) \ -+ (*(((struct headname *)((elm)->field.tqe_prev))->tqh_last)) -+ -+#define TAILQ_REMOVE(head, elm, field) do { \ -+ if ((TAILQ_NEXT((elm), field)) != NULL) \ -+ TAILQ_NEXT((elm), field)->field.tqe_prev = \ -+ (elm)->field.tqe_prev; \ -+ else { \ -+ (head)->tqh_last = (elm)->field.tqe_prev; \ -+ } \ -+ *(elm)->field.tqe_prev = TAILQ_NEXT((elm), field); \ -+} while (0) -+ -+ -+static inline int -+ifx_drv_ver(char *buf, char *module, int major, int mid, int minor) -+{ -+ return sprintf(buf, "Lantiq %s driver, version %d.%d.%d, (c) 2001-2011 Lantiq Deutschland GmbH\n", -+ module, major, mid, minor); -+} -+ -+/* -+ * Basic Clock Functions (not for 100% precise usage) -+ */ -+extern unsigned int ifx_get_cpu_hz(void); -+extern unsigned int ifx_get_fpi_hz(void); -+ -+/* -+ * Output on ASC (before ASC/Console driver is ready) -+ */ -+extern void prom_printf(const char *, ...); -+ -+/* -+ * Get Reserved Memory for Voice -+ */ -+extern unsigned int* ifx_get_cp1_base(void); -+extern unsigned int ifx_get_cp1_size(void); -+ -+ -+ -+#endif // COMMON_ROUTINES_H -diff --git a/arch/mips/include/asm/ifx/danube/danube.h b/arch/mips/include/asm/ifx/danube/danube.h -new file mode 100644 -index 0000000..c07661e ---- /dev/null -+++ b/arch/mips/include/asm/ifx/danube/danube.h -@@ -0,0 +1,1442 @@ -+/****************************************************************************** -+** -+** FILE NAME : danube.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Danube -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef DANUBE_H -+#define DANUBE_H -+#include <asm/bootinfo.h> -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define MACH_GROUP_IFX MACH_GROUP_DANUBE -+#define MACH_TYPE_IFX MACH_DANUBE -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+#define IFX_RCU_UBSCFG ((volatile u32*)(IFX_RCU + 0x18)) -+ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_USB_CFG ((volatile u32*)(IFX_RCU + 0x0018)) -+#define IFX_USBCFG_HDSEL_BIT 11 // 0:host, 1:device -+#define IFX_USBCFG_HOST_END_BIT 10 // 0:little_end, 1:big_end -+#define IFX_USBCFG_AHB_END_BIT 9 // 0:little_end, 1:big_end -+ -+#define IFX_RST_ALL (1 << 30) -+ -+/***Reset Request Register***/ -+#define IFX_RCU_RST_REQ_CPU0 (1 << 31) -+#define IFX_RCU_RST_REQ_CPU1 (1 << 3) -+#define IFX_RCU_RST_REQ_CPUSUB (1 << 29) -+#define IFX_RCU_RST_REQ_HRST (1 << 28) -+#define IFX_RCU_RST_REQ_WDT0 (1 << 27) -+#define IFX_RCU_RST_REQ_WDT1 (1 << 26) -+#define IFX_RCU_RST_REQ_CFG_GET(value) (((value) >> 23) & ((1 << 3) - 1)) -+#define IFX_RCU_RST_REQ_CFG_SET(value) (((( 1 << 3) - 1) & (value)) << 23) -+#define IFX_RCU_RST_REQ_SWTBOOT (1 << 22) -+#define IFX_RCU_RST_REQ_DMA (1 << 21) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) -+#define IFX_RCU_RST_REQ_ETHPHY0 (1 << 19) -+#define IFX_RCU_RST_REQ_CPU0_BR (1 << 18) -+ -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_PPE (1 << 8) -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL IFX_RST_ALL -+ -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : LED register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_LED (KSEG1 | 0x1E100BB0) -+ -+#define IFX_LED_CON0 ((volatile u32*)(IFX_LED + 0x0000)) -+#define IFX_LED_CON1 ((volatile u32*)(IFX_LED + 0x0004)) -+#define IFX_LED_CPU0 ((volatile u32*)(IFX_LED + 0x0008)) -+#define IFX_LED_CPU1 ((volatile u32*)(IFX_LED + 0x000C)) -+#define IFX_LED_AR ((volatile u32*)(IFX_LED + 0x0010)) -+ -+/* -+ * LED Control 0 Register -+ */ -+#define IFX_LED_SWU_SHIFT 31 -+#define IFX_LED_RZFL_SHIFT 26 -+#define IFX_LED_AD1_SHIFT 25 -+#define IFX_LED_AD0_SHIFT 24 -+ -+#define IFX_LED_ADSL_MASK (3 << LED_AD0_SHIFT) -+#define IFX_LED_CON0_SWU (*IFX_LED_CON0 & (1 << 31)) -+#define IFX_LED_CON0_FALLING_EDGE (*IFX_LED_CON0 & (1 << 26)) -+#define IFX_LED_CON0_AD1 (*IFX_LED_CON0 & (1 << 25)) -+#define IFX_LED_CON0_AD0 (*IFX_LED_CON0 & (1 << 24)) -+#define IFX_LED_CON0_LBn(n) (*IFX_LED_CON0 & (1 << n)) -+#define IFX_LED_CON0_DEFAULT_VALUE (0x80000000 | (DATA_CLOCKING_EDGE << 26)) -+ -+/* -+ * LED Control 1 Register -+ */ -+#define IFX_LED_CON1_US (*IFX_LED_CON1 >> 30) -+#define IFX_LED_CON1_SCS (*IFX_LED_CON1 & (1 << 28)) -+#define IFX_LED_CON1_FPID GET_BITS(*IFX_LED_CON1, 27, 23) -+#define IFX_LED_CON1_FPIS GET_BITS(*IFX_LED_CON1, 21, 20) -+#define IFX_LED_CON1_DO GET_BITS(*IFX_LED_CON1, 19, 18) -+#define IFX_LED_CON1_G2 (*IFX_LED_CON1 & (1 << 2)) -+#define IFX_LED_CON1_G1 (*IFX_LED_CON1 & (1 << 1)) -+#define IFX_LED_CON1_G0 (*IFX_LED_CON1 & 0x01) -+#define IFX_LED_CON1_G (*IFX_LED_CON1 & 0x07) -+#define IFX_LED_CON1_DEFAULT_VALUE 0x00000000 -+ -+/* -+ * LED Data Output CPU 0 Register -+ */ -+#define IFX_LED_CPU0_Ln(n) (*IFX_LED_CPU0 & (1 << n)) -+#define IFX_LED_LED_CPU0_DEFAULT_VALUE 0x00000000 -+ -+/* -+ * LED Data Output CPU 1 Register -+ */ -+#define IFX_LED_CPU1_Ln(n) (*IFX_LED_CPU1 & (1 << n)) -+#define IFX_LED_LED_CPU1_DEFAULT_VALUE 0x00000000 -+ -+/* -+ * LED Data Output Access Rights Register -+ */ -+#define IFX_LED_AR_Ln(n) (*IFX_LED_AR & (1 << n)) -+#define IFX_LED_AR_DEFAULT_VALUE 0x00000000 -+ -+ -+ -+/***********************************************************************/ -+/* Module : MEI register address and bits */ -+/***********************************************************************/ -+#define IFX_MEI_SPACE_ACCESS (KSEG1 | 0x1E116000) -+ -+/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -+#define IFX_MEI_DATA_XFR ((volatile u32*)(0x0000 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_VERSION ((volatile u32*)(0x0004 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_ARC_TO_MEI_INT ((volatile u32*)(0x001C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_CONFIG ((volatile u32*)(0x0034 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_DBG_MASTER ((volatile u32*)(0x003C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_BIST_STAT ((volatile u32*)(0x0048 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFX_MEI_SPACE_ACCESS)) -+#define IFX_MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFX_MEI_SPACE_ACCESS)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : SSC1 register address and bits */ -+/***********************************************************************/ -+ -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+#define IFX_GPIO_Pn_BASE(n) (IFX_GPIO + 0x0010 + 0x0030 * (n)) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x0010)) -+#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0014)) -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0018)) -+#define IFX_CGU_OSC_CON ((volatile u32*)(IFX_CGU + 0x001C)) -+#define IFX_CGU_SMD ((volatile u32*)(IFX_CGU + 0x0020)) -+#define IFX_CGU_CT1SR ((volatile u32*)(IFX_CGU + 0x0028)) -+#define IFX_CGU_CT2SR ((volatile u32*)(IFX_CGU + 0x002C)) -+#define IFX_CGU_PCMCR ((volatile u32*)(IFX_CGU + 0x0030)) -+#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0034)) -+#define IFX_CGU_PD_PC ((volatile u32*)(IFX_CGU + 0x0038)) -+#define IFX_CGU_FMR ((volatile u32*)(IFX_CGU + 0x003C)) -+ -+/* -+ * CGU PLL0 Configure Register -+ */ -+#define CGU_PLL0_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL0_CFG & (1 << 31)) -+#define CGU_PLL0_BYPASS (*IFX_CGU_PLL0_CFG & (1 << 30)) -+#define CGU_PLL0_SRC (*IFX_CGU_PLL0_CFG & (1 << 29)) -+#define CGU_PLL0_CFG_DSMSEL (*IFX_CGU_PLL0_CFG & (1 << 28)) -+#define CGU_PLL0_CFG_FRAC_EN (*IFX_CGU_PLL0_CFG & (1 << 27)) -+#define CGU_PLL0_CFG_PLLK GET_BITS(*IFX_CGU_PLL0_CFG, 26, 17) -+//#define CGU_PLL0_CFG_PLLD GET_BITS(*IFX_CGU_PLL0_CFG, 16, 13) -+#define CGU_PLL0_CFG_PLLN GET_BITS(*IFX_CGU_PLL0_CFG, 12, 6) -+#define CGU_PLL0_CFG_PLLM GET_BITS(*IFX_CGU_PLL0_CFG, 5, 2) -+#define CGU_PLL0_CFG_PLLL (*IFX_CGU_PLL0_CFG & (1 << 1)) -+#define CGU_PLL0_CFG_PLLEN (*IFX_CGU_PLL0_CFG & (1 << 0)) -+ -+/* -+ * CGU PLL1 Configure Register -+ */ -+#define CGU_PLL1_SRC (*IFX_CGU_PLL1_CFG & (1 << 31)) -+#define CGU_PLL1_BYPASS (*IFX_CGU_PLL1_CFG & (1 << 30)) -+#define CGU_PLL1_CFG_CTEN (*IFX_CGU_PLL1_CFG & (1 << 29)) -+#define CGU_PLL1_CFG_DSMSEL (*IFX_CGU_PLL1_CFG & (1 << 28)) -+#define CGU_PLL1_CFG_FRAC_EN (*IFX_CGU_PLL1_CFG & (1 << 27)) -+#define CGU_PLL1_CFG_PLLK GET_BITS(*IFX_CGU_PLL1_CFG, 26, 17) -+//#define CGU_PLL1_CFG_PLLD GET_BITS(*IFX_CGU_PLL1_CFG, 16, 13) -+#define CGU_PLL1_CFG_PLLN GET_BITS(*IFX_CGU_PLL1_CFG, 12, 6) -+#define CGU_PLL1_CFG_PLLM GET_BITS(*IFX_CGU_PLL1_CFG, 5, 2) -+#define CGU_PLL1_CFG_PLLL (*IFX_CGU_PLL1_CFG & (1 << 1)) -+#define CGU_PLL1_CFG_PLLEN (*IFX_CGU_PLL1_CFG & (1 << 0)) -+ -+/* -+ * CGU PLL2 Configure/Status Register -+ */ -+//#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL2_CFG & (1 << 31)) // Write bit 31, Read from bit 20 -+#define CGU_PLL2_PHASE_DIVIDER_ENABLE (*IFX_CGU_PLL2_CFG & (1 << 20)) -+#define CGU_PLL2_BYPASS (*IFX_CGU_PLL2_CFG & (1 << 19)) -+#define CGU_PLL2_SRC GET_BITS(*IFX_CGU_PLL2_CFG, 18, 17) -+#define CGU_PLL2_CFG_INPUT_DIV GET_BITS(*IFX_CGU_PLL2_CFG, 16, 13) -+#define CGU_PLL2_CFG_PLLN GET_BITS(*IFX_CGU_PLL2_CFG, 12, 6) -+#define CGU_PLL2_CFG_PLLM GET_BITS(*IFX_CGU_PLL2_CFG, 5, 2) -+#define CGU_PLL2_CFG_PLLL (*IFX_CGU_PLL2_CFG & (1 << 1)) -+#define CGU_PLL2_CFG_PLLEN (*IFX_CGU_PLL2_CFG & (1 << 0)) -+ -+/* -+ * CGU Clock Sys Mux Register -+ */ -+#define CGU_SYS_PPESEL GET_BITS(*IFX_CGU_SYS, 8, 7) -+#define CGU_SYS_FPI_SEL (*IFX_CGU_SYS & (1 << 6)) -+#define CGU_SYS_CPU1SEL GET_BITS(*IFX_CGU_SYS, 5, 4) -+#define CGU_SYS_CPU0SEL GET_BITS(*IFX_CGU_SYS, 3, 2) -+#define CGU_SYS_DDR_SEL GET_BITS(*IFX_CGU_SYS, 1, 0) -+ -+/* -+ * CGU Update Register -+ */ -+#define CGU_UPDATE_UPDATE (*IFX_CGU_UPDATE & (1 << 0)) -+ -+/* -+ * CGU Interface Clock Register -+ */ -+#define CGU_IF_CLK_O_RMII1 (*IFX_CGU_IF_CLK & (1 << 25)) -+#define CGU_IF_CLK_O_RMII0 (*IFX_CGU_IF_CLK & (1 << 24)) -+#define CGU_IF_CLK_PCI_CLK GET_BITS(*IFX_CGU_IF_CLK, 23, 20) -+#define CGU_IF_CLK_PDA (*IFX_CGU_IF_CLK & (1 << 19)) -+#define CGU_IF_CLK_PCI_B (*IFX_CGU_IF_CLK & (1 << 18)) -+#define CGU_IF_CLK_PCIBM (*IFX_CGU_IF_CLK & (1 << 17)) -+#define CGU_IF_CLK_PCIS (*IFX_CGU_IF_CLK & (1 << 16)) -+#define CGU_IF_CLK_CLKOD0 GET_BITS(*IFX_CGU_IF_CLK, 15, 14) -+#define CGU_IF_CLK_CLKOD1 GET_BITS(*IFX_CGU_IF_CLK, 13, 12) -+#define CGU_IF_CLK_CLKOD2 GET_BITS(*IFX_CGU_IF_CLK, 11, 10) -+#define CGU_IF_CLK_CLKOD3 GET_BITS(*IFX_CGU_IF_CLK, 9, 8) -+//#define CGU_IF_CLK_PPESEL GET_BITS(*IFX_CGU_IF_CLK, 7, 6) -+#define CGU_IF_CLK_USBSEL GET_BITS(*IFX_CGU_IF_CLK, 5, 4) -+#define CGU_IF_CLK_MDCSEL GET_BITS(*IFX_CGU_IF_CLK, 3, 2) -+#define CGU_IF_CLK_MIISEL GET_BITS(*IFX_CGU_IF_CLK, 1, 0) -+ -+/* -+ * CGU SDRAM Memory Delay Register -+ */ -+//#define CGU_SMD_CLKI (*IFX_CGU_SMD & (1 << 31)) -+#define CGU_SMD_CLK_IN_S (*IFX_CGU_SMD & (1 << 22)) -+#define CGU_SMD_DDR_PRG (*IFX_CGU_SMD & (1 << 21)) -+#define CGU_SMD_DDR_CQ (*IFX_CGU_SMD & (1 << 20)) -+#define CGU_SMD_DDR_EQ (*IFX_CGU_SMD & (1 << 19)) -+#define CGU_SMD_SDR_CLKS (*IFX_CGU_SMD & (1 << 18)) -+#define CGU_SMD_MIDS GET_BITS(*IFX_CGU_SMD, 17, 12) -+#define CGU_SMD_MODS GET_BITS(*IFX_CGU_SMD, 11, 6) -+#define CGU_SMD_MDSEL GET_BITS(*IFX_CGU_SMD, 5, 0) -+ -+/* -+ * CGU CT Status Register 1 -+ */ -+#define CGU_CT1SR_PDOUT GET_BITS(*IFX_CGU_CT1SR, 14, 0) -+ -+/* -+ * CGU CT Status Register 2 -+ */ -+#define CGU_CT1SR_PLL1K GET_BITS(*IFX_CGU_CT2SR, 9, 0) -+ -+/* -+ * CGU PCM Control Register -+ */ -+#define CGU_PCMCR_DCL1 GET_BITS(*IFX_CGU_PCMCR, 27, 25) -+#define CGU_PCMCR_MUXDCL (*IFX_CGU_MUXDCL & (1 << 22)) -+#define CGU_PCMCR_MUXFSC (*IFX_CGU_MUXDCL & (1 << 18)) -+#define CGU_PCMCR_PCM_SL (*IFX_CGU_MUXDCL & (1 << 13)) -+#define CGU_PCMCR_DNTR GET_BITS(*IFX_CGU_PCMCR, 12, 11) -+#define CGU_PCMCR_NTRS (*IFX_CGU_MUXDCL & (1 << 10)) -+#define CGU_PCMCR_AC97_EN (*IFX_CGU_MUXDCL & (1 << 9)) -+#define CGU_PCMCR_CTTMUX (*IFX_CGU_MUXDCL & (1 << 8)) -+ -+/* -+ * PCI Clock Control Register -+ */ -+#define CGU_PCI_CR_PADSEL (*IFX_CGU_PCI_CR & (1 << 31)) -+#define CGU_PCI_CR_RESSEL (*IFX_CGU_PCI_CR & (1 << 30)) -+#define CGU_PCI_CR_PCID_H GET_BITS(*IFX_CGU_PCI_CR, 23, 21) -+#define CGU_PCI_CR_PCID_L GET_BITS(*IFX_CGU_PCI_CR, 20, 18) -+ -+#define IFX_PCI_CLK_SHIFT 20 -+#define IFX_PCI_CLK_MASK (0xF << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_33MHZ (8 << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_60MHZ (4 << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ -+ -+#define IFX_PCI_CLK_FROM_CGU 0x80000000 -+#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 -+#define IFX_PCI_DELAY_SHIFT 21 -+#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & 0xFFFF) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((value) & 0xFFFF) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x1E105300) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+#define IFX_EBU_CON_1 (1 << 3) -+ -+#define IFX_EBU_ADDR_SEL_EN 1 -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE (KSEG1 + 0x10000000) -+#define IFX_EBU_ADDR_SEL0 IFX_EBU_ADDSEL0 -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE (KSEG1 + 0x14000000) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x0028)) -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU + 0x0060)) -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+}; -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+ -+#define IFX_EBU_ADDRSEL_SHIFT 4 -+#define IFX_EBU_ADDRSEL_MASK 0xF -+#define IFX_EBU_ADDRSEL_MASK_SET(value) ((value & BSP_EBU_ADDRSEL_MASK) << BSP_EBU_ADDRSEL_SHIFT) -+ -+#define IFX_EBU_BUSCON_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON_ADSWP (1 << 30) -+#define IFX_EBU_BUSCON_AGEN_SHIFT 24 -+#define IFX_EBU_BUSCON_AGEN_MASK 7 -+#define IFX_EBU_BUSCON_SETUP (1 << 22) -+#define IFX_EBU_BUSCON_WAIT_SHIFT 20 -+#define IFX_EBU_BUSCON_WAIT_MASK 3 -+#define IFX_EBU_BUSCON_ACTIVE_WAIT_LEVEL (1 << 19) -+#define IFX_EBU_BUSCON_DATA_WIDTH_SHIFT 16 -+#define IFX_EBU_BUSCON_DATA_WIDTH_MASK 3 -+#define IFX_EBU_BUSCON_ALE_DUR_SHIFT 14 -+#define IFX_EBU_BUSCON_ALE_DUR_MASK 3 -+#define IFX_EBU_BUSCON_BCGEN_SHIFT 12 -+#define IFX_EBU_BUSCON_BCGEN_MASK 3 -+#define IFX_EBU_BUSCON_WAITWRC_SHIFT 8 -+#define IFX_EBU_BUSCON_WAITWRC_MASK 7 -+#define IFX_EBU_BUSCON_WAITRDC_SHIFT 6 -+#define IFX_EBU_BUSCON_WAITRDC_MASK 3 -+#define IFX_EBU_BUSCON_HOLDC_SHIFT 4 -+#define IFX_EBU_BUSCON_HOLDC_MASK 3 -+#define IFX_EBU_BUSCON_RECOVC_SHIFT 2 -+#define IFX_EBU_BUSCON_RECOVC_MASK 3 -+#define IFX_EBU_BUSCON_CMULT_SHIFT 0 -+#define IFX_EBU_BUSCON_CMULT_MASK 3 -+ -+#define IFX_EBU_BUSCON_AGEN(value) ((value & IFX_EBU_BUSCON_AGEN_MASK) << IFX_EBU_BUSCON_AGEN_SHIFT) -+#define IFX_EBU_BUSCON_WAIT(value) ((value & IFX_EBU_BUSCON_WAIT_MASK) << IFX_EBU_BUSCON_WAIT_SHIFT) -+#define IFX_EBU_BUSCON_DATA_WIDTH(value) ((value & IFX_EBU_BUSCON_DATA_WIDTH_MASK) << IFX_EBU_BUSCON_DATA_WIDTH_SHIFT) -+#define IFX_EBU_BUSCON_ALEC(value) ((value & IFX_EBU_BUSCON_ALE_DUR_MASK) << IFX_EBU_BUSCON_ALE_DUR_SHIFT) -+#define IFX_EBU_BUSCON_BCGEN(value) ((value & IFX_EBU_BUSCON_BCGEN_MASK) << IFX_EBU_BUSCON_BCGEN_SHIFT) -+#define IFX_EBU_BUSCON_WR_WAIT(value) ((value & IFX_EBU_BUSCON_WAITWRC_MASK) << IFX_EBU_BUSCON_WAITWRC_SHIFT) -+#define IFX_EBU_BUSCON_RD_WAIT(value) ((value & IFX_EBU_BUSCON_WAITRDC_MASK) << IFX_EBU_BUSCON_WAITRDC_SHIFT) -+#define IFX_EBU_BUSCON_HOLD(value) ((value & IFX_EBU_BUSCON_HOLDC_MASK) << IFX_EBU_BUSCON_HOLDC_SHIFT) -+#define IFX_EBU_BUSCON_RECOV(value) ((value & IFX_EBU_BUSCON_RECOVC_MASK) << IFX_EBU_BUSCON_RECOVC_SHIFT) -+#define IFX_EBU_BUSCON_CMULT(value) ((value & IFX_EBU_BUSCON_CMULT_MASK) << IFX_EBU_BUSCON_CMULT_SHIFT) -+ -+#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU + 0x0090)) -+#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 -+#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 -+#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 -+#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 -+#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 -+#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A -+#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C -+ -+#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU + 0x0094)) -+#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU + 0x00A0)) -+#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU + 0x00A4)) -+#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 -+ -+#define IFX_EBU_NAND_CON ((volatile u32*)(IFX_EBU + 0xB0)) -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+ }; -+ -+ -+#define IFX_EBU_NAND_WAIT ((volatile u32*)(IFX_EBU + 0xB4)) -+#define IFX_EBU_NAND_WAIT_RD (1<<0) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#define IFX_EBU_NAND_ECC0 ((volatile u32*)(IFX_EBU + 0xB8)) -+#define IFX_EBU_NAND_ECC_AC ((volatile u32*)(IFX_EBU + 0xBC)) -+ -+#define IFX_EBU_NAND_ECC_ON (1 << 31) -+#define IFX_EBU_NAND_LATCH_EN_SHIFT 18 -+#define IFX_EBU_NAND_LATCH_EN_MASK 0x3F -+#define IFX_EBU_NAND_OUT_CS_SHIFT 10 -+#define IFX_EBU_NAND_OUT_CS_MASK 3 -+#define IFX_EBU_NAND_IN_CS_SHIFT 8 -+#define IFX_EBU_NAND_IN_CS_MASK 3 -+#define IFX_EBU_NAND_PRE_P (1 << 7) -+#define IFX_EBU_NAND_WP_P (1 << 6) -+#define IFX_EBU_NAND_SE_P (1 << 5) -+#define IFX_EBU_NAND_CS_P (1 << 4) -+#define IFX_EBU_NAND_CLE_P (1 << 3) -+#define IFX_EBU_NAND_ALE_P (1 << 2) -+#define IFX_EBU_NAND_CSMUX_E (1 << 1) -+#define IFX_EBU_NAND_NANDM 1 -+ -+#define IFX_EBU_NAND_LATCH_EN(value) ((value & IFX_EBU_NAND_LATCH_EN_MASK) << IFX_EBU_NAND_LATCH_EN_SHIFT) -+#define IFX_EBU_NAND_OUT_CS(value) ((value & IFX_EBU_NAND_OUT_CS_MASK) << IFX_EBU_NAND_OUT_CS_SHIFT) -+#define IFX_EBU_NAND_IN_CS(value) ((value & IFX_EBU_NAND_IN_CS_MASK) << IFX_EBU_NAND_IN_CS_SHIFT) -+#define IFX_EBU_NAND_LATCH_PRE_P (1 << 23) -+#define IFX_EBU_NAND_LATCH_WP_P (1 << 22) -+#define IFX_EBU_NAND_LATCH_SE_P (1 << 21) -+#define IFX_EBU_NAND_LATCH_CS_P (1 << 20) -+#define IFX_EBU_NAND_LATCH_CLE_P (1 << 19) -+#define IFX_EBU_NAND_LATCH_ALE_P (1 << 18) -+ -+ -+ -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+ -+ -+/***********************************************************************/ -+/* Module : GPTC register address and bits */ -+/***********************************************************************/ -+ -+/***********************************************************************/ -+/* Module : ASC0 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC0 (KSEG1 | 0x1E100400) -+ -+#define IFX_ASC0_TBUF ((volatile u32*)(IFX_ASC0 + 0x0020)) -+#define IFX_ASC0_RBUF ((volatile u32*)(IFX_ASC0 + 0x0024)) -+#define IFX_ASC0_FSTAT ((volatile u32*)(IFX_ASC0 + 0x0048)) -+#define IFX_ASC0_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC0_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC0_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC0_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC0_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC0_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC0_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC0_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+/***ASC Clock Control Register***/ -+#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1+ 0x0000)) -+#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_ASC1_CLC_DISS (1 << 1) -+#define IFX_ASC1_CLC_DISR (1 << 0) -+ -+/***ASC Port Input Select Register***/ -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1+ 0x0004)) -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1+ 0x0004)) -+#define IFX_ASC1_PISEL_RIS (1 << 0) -+ -+/***ASC Control Register***/ -+#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1+ 0x0010)) -+#define IFX_ASC1_CON_BEN (1 << 20) -+#define IFX_ASC1_CON_TOEN (1 << 20) -+#define IFX_ASC1_CON_ROEN (1 << 19) -+#define IFX_ASC1_CON_RUEN (1 << 18) -+#define IFX_ASC1_CON_FEN (1 << 17) -+#define IFX_ASC1_CON_PAL (1 << 16) -+#define IFX_ASC1_CON_R (1 << 15) -+#define IFX_ASC1_CON_ACO (1 << 14) -+#define IFX_ASC1_CON_LB (1 << 13) -+#define IFX_ASC1_CON_ERCLK (1 << 10) -+#define IFX_ASC1_CON_FDE (1 << 9) -+#define IFX_ASC1_CON_BRS (1 << 8) -+#define IFX_ASC1_CON_STP (1 << 7) -+#define IFX_ASC1_CON_SP (1 << 6) -+#define IFX_ASC1_CON_ODD (1 << 5) -+#define IFX_ASC1_CON_PEN (1 << 4) -+#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***ASC Staus Register***/ -+#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) -+/***ASC Write Hardware Modified Control Register***/ -+#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) -+#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) -+#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) -+#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) -+#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) -+#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) -+#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) -+#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) -+#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) -+#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) -+#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) -+#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) -+#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) -+#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) -+ -+/***ASC Baudrate Timer/Reload Register***/ -+#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) -+#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) -+ -+/***ASC Fractional Divider Register***/ -+#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Transmit Buffer Register***/ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Receive Buffer Register***/ -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Autobaud Control Register***/ -+#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) -+#define IFX_ASC1_ABCON_RXINV (1 << 11) -+#define IFX_ASC1_ABCON_TXINV (1 << 10) -+#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -+#define IFX_ASC1_ABCON_FCDETEN (1 << 4) -+#define IFX_ASC1_ABCON_ABDETEN (1 << 3) -+#define IFX_ASC1_ABCON_ABSTEN (1 << 2) -+#define IFX_ASC1_ABCON_AUREN (1 << 1) -+#define IFX_ASC1_ABCON_ABEN (1 << 0) -+ -+/***Receive FIFO Control Register***/ -+#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) -+#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) -+#define IFX_ASC1_RXFCON_RXFEN (1 << 0) -+ -+/***Transmit FIFO Control Register***/ -+#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) -+#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) -+#define IFX_ASC1_TXFCON_TXFEN (1 << 0) -+ -+/***FIFO Status Register***/ -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -+#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+/***ASC Autobaud Status Register***/ -+#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) -+#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) -+#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) -+#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) -+#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) -+#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) -+ -+/***ASC Write HW Modified Autobaud Status Register***/ -+#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) -+#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) -+#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) -+#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) -+#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) -+#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) -+#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) -+#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) -+#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) -+#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) -+#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) -+ -+/***ASC IRNCR0 **/ -+#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) -+#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) -+/***ASC IRNCR1 **/ -+#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) -+#define IFX_ASC_IRNCR_TIR 0x1 -+#define IFX_ASC_IRNCR_RIR 0x2 -+#define IFX_ASC_IRNCR_EIR 0x4 -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)IFX_DMA_BASE -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE+0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE+0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE+0x14) -+#define IFX_DMA_CS (volatile u32*)(IFX_DMA_BASE+0x18) -+#define IFX_DMA_CCTRL (volatile u32*)(IFX_DMA_BASE+0x1C) -+#define IFX_DMA_CDBA (volatile u32*)(IFX_DMA_BASE+0x20) -+#define IFX_DMA_CDLEN (volatile u32*)(IFX_DMA_BASE+0x24) -+#define IFX_DMA_CIS (volatile u32*)(IFX_DMA_BASE+0x28) -+#define IFX_DMA_CIE (volatile u32*)(IFX_DMA_BASE+0x2C) -+ -+#define IFX_DMA_PS (volatile u32*)(IFX_DMA_BASE+0x40) -+#define IFX_DMA_PCTRL (volatile u32*)(IFX_DMA_BASE+0x44) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE+0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE+0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE+0xfc) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+#define IFX_ICU_IM0_IMR_IID (1 << 31) -+#define IFX_ICU_IM0_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM0_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM0_IR(value) (1 << (value)) -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+#define IFX_ICU_IM1_IMR_IID (1 << 31) -+#define IFX_ICU_IM1_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM1_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM1_IR(value) (1 << (value)) -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+#define IFX_ICU_IM2_IMR_IID (1 << 31) -+#define IFX_ICU_IM2_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM2_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM2_IR(value) (1 << (value)) -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+#define IFX_ICU_IM3_IMR_IID (1 << 31) -+#define IFX_ICU_IM3_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM3_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM3_IR(value) (1 << (value)) -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+#define IFX_ICU_IM4_IMR_IID (1 << 31) -+#define IFX_ICU_IM4_IMR_IN_GET(value) (((value) >> 0) & ((1 << 5) - 1)) -+#define IFX_ICU_IM4_IMR_IN_SET(value) (((( 1 << 5) - 1) & (value)) << 0) -+#define IFX_ICU_IM4_IR(value) (1 << (value)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00F8)) -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK 0x3F -+#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) -+#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) -+#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) -+#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1 | 0x1f101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32*)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32*)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32*)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32*)(IFX_ICU_EIU + 0x000c)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & 0xF) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((value) & 0xF) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & 0xFFFF) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((value) & 0xFFFF) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & 0x7FF) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((value) & 0x7FF) << 1) -+ -+/* voice channel 0 ... 3 interrupt enable register */ -+#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) -+#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) -+#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) -+#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) -+/* voice channel 0 ... 3 interrupt status read register */ -+#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) -+#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) -+#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) -+#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) -+/* voice channel 0 ... 3 interrupt status set register */ -+#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) -+#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) -+#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) -+#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) -+/* voice channel 0 ... 3 interrupt status clear register */ -+#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) -+#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) -+#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) -+#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) -+/* common status 0 and 1 read register */ -+#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) -+#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) -+/* common status 0 and 1 set register */ -+#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) -+#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) -+/* common status 0 and 1 clear register */ -+#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) -+#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) -+/* common status 0 and 1 enable register */ -+#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) -+#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) -+/* notification enable register */ -+#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) -+#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) -+/* CPU to CPU interrup request register */ -+#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) -+#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) -+/* Global interrupt request and request enable register */ -+#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) -+#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) -+ -+#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 + 0x1F200000)) -+ -+#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 + 0x1F2001E0)) -+ -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+ -+ -+/************************************************************************/ -+/* Module : DEU register address and bits */ -+/************************************************************************/ -+ -+#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) -+ -+/* DEU Control Register */ -+#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) -+#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) -+ -+/* DEU control register */ -+#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) -+#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) -+#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) -+#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) -+#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) -+#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) -+#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) -+#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) -+#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) -+#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) -+#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+ -+/* AES DEU register */ -+#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) -+#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) -+#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) -+#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) -+ -+/* AES Key register */ -+#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) -+#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) -+#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) -+#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) -+#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) -+#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) -+#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) -+#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) -+ -+/* AES vector register */ -+#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) -+#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) -+#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) -+#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) -+#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) -+#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) -+#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) -+#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) -+ -+/* hash control registe */ -+#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) -+#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) -+#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) -+#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) -+#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) -+#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) -+#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) -+ -+#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) -+ -+#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) -+#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) -+#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) -+ -+ -+ -+/************************************************************************/ -+/* Module : PPE register address and bits */ -+/************************************************************************/ -+ -+#define IFX_PPE32_BASE (KSEG1 | 0x1E180000) -+#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) -+#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) -+#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) -+#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) -+ -+#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) -+ -+/* -+ * ETOP MDIO Registers -+ */ -+#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -+#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -+#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -+#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -+#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -+#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -+#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -+#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -+#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -+#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -+#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -+#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -+#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -+#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -+#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -+#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -+#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -+#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -+#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -+#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) -+ -+#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -+#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -+#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -+#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -+#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -+#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -+#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) -+ -+#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -+#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -+#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -+#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -+#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -+#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) -+ -+ -+/* Sharebuff SB RAM2 control data */ -+#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) -+#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) -+ -+#endif /* DANUBE_H */ -+ -diff --git a/arch/mips/include/asm/ifx/danube/danube_ref_board.h b/arch/mips/include/asm/ifx/danube/danube_ref_board.h -new file mode 100644 -index 0000000..18d2c58 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/danube/danube_ref_board.h -@@ -0,0 +1,37 @@ -+/****************************************************************************** -+** -+** FILE NAME : danube_ref_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Danube -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef DANUBE_REF_BOARD_H -+#define DANUBE_REF_BOARD_H -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 7 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#define IFX_LEDLED_USB_VBUS -+ -+#endif /* DANUBE_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/danube/irq.h b/arch/mips/include/asm/ifx/danube/irq.h -new file mode 100644 -index 0000000..1c5f57b ---- /dev/null -+++ b/arch/mips/include/asm/ifx/danube/irq.h -@@ -0,0 +1,152 @@ -+/****************************************************************************** -+** -+** file name : irq.h -+** project : ifx ueip -+** modules : bsp basic -+** -+** date : 27 may 2009 -+** author : xu liang -+** description : header file for danube -+** copyright : copyright (c) 2009 -+** infineon technologies ag -+** am campeon 1-12, 85579 neubiberg, germany -+** -+** this program is free software; you can redistribute it and/or modify -+** it under the terms of the gnu general public license as published by -+** the free software foundation; either version 2 of the license, or -+** (at your option) any later version. -+** -+** history -+** $date $author $comment -+** 27 may 2009 xu liang the first ueip release -+*******************************************************************************/ -+ -+ -+ -+#ifndef DANUBE_IRQ -+#define DANUBE_IRQ -+ -+ -+ -+/****** Interrupt Assigments ***********/ -+ -+#define IFX_ASC0_TIR INT_NUM_IM3_IRL0 // INT_NUM_IM0_IRL0 -+#define IFX_ASC0_TBIR INT_NUM_IM3_IRL1 // INT_NUM_IM0_IRL1 -+#define IFX_ASC0_RIR INT_NUM_IM3_IRL2 // INT_NUM_IM0_IRL2 -+#define IFX_ASC0_EIR INT_NUM_IM3_IRL3 // INT_NUM_IM0_IRL3 -+#define IFX_ASC0_ABSTIR INT_NUM_IM3_IRL4 // INT_NUM_IM0_IRL4 -+#define IFX_ASC0_ABDETIR INT_NUM_IM3_IRL5 // INT_NUM_IM0_IRL5 -+#define IFX_ASC0_SFCIR INT_NUM_IM3_IRL6 // INT_NUM_IM0_IRL6 -+#define IFX_ASC0_MIR INT_NUM_IM3_IRL21 // INT_NUM_IM0_IRL21 -+#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 // INT_NUM_IM0_IRL7 -+#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 // INT_NUM_IM0_IRL8 -+#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 // INT_NUM_IM0_IRL9 -+#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 // INT_NUM_IM0_IRL10 -+#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 // INT_NUM_IM0_IRL11 -+#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 // INT_NUM_IM0_IRL12 -+#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 // INT_NUM_IM0_IRL13 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_DSL_DFE_IR INT_NUM_IM2_IRL14 // INT_NUM_IM1_IRL23 -+#define IFX_DSL_AFEOVL_IR INT_NUM_IM2_IRL15 // INT_NUM_IM1_IRL24 -+#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 -+#define IFX_DSL_DFE_INT0IR INT_NUM_IM4_IRL12 // INT_NUM_IM2_IRL12 -+#define IFX_DSL_DFE_INT1IR INT_NUM_IM4_IRL13 // INT_NUM_IM2_IRL13 -+#define IFX_FCSI_IR INT_NUM_IM1_IRL16 // INT_NUM_IM0_IRL31 -+#define IFX_MEI_INT IFX_DSL_DFE_IR -+#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT -+#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR -+#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR -+ -+#define IFX_DEU_DESIR INT_NUM_IM1_IRL6 // INT_NUM_IM0_IRL27 -+#define IFX_DEU_AESIR INT_NUM_IM1_IRL7 // INT_NUM_IM0_IRL28 -+#define IFX_DEU_HASHIR INT_NUM_IM1_IRL8 // INT_NUM_IM0_IRL29 -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM4_IRL0 // INT_NUM_IM2_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM4_IRL1 // INT_NUM_IM2_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM4_IRL2 // INT_NUM_IM2_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM4_IRL3 // INT_NUM_IM2_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM4_IRL4 // INT_NUM_IM2_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM4_IRL5 // INT_NUM_IM2_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM4_IRL6 // INT_NUM_IM2_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM4_IRL7 // INT_NUM_IM2_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM4_IRL8 // INT_NUM_IM2_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM4_IRL9 // INT_NUM_IM2_IRL9 -+#define IFX_DMA_CH10_INT INT_NUM_IM4_IRL10 // INT_NUM_IM2_IRL10 -+#define IFX_DMA_CH11_INT INT_NUM_IM4_IRL11 // INT_NUM_IM2_IRL11 -+#define IFX_DMA_CH12_INT INT_NUM_IM4_IRL25 // INT_NUM_IM2_IRL25 -+#define IFX_DMA_CH13_INT INT_NUM_IM4_IRL26 // INT_NUM_IM2_IRL26 -+#define IFX_DMA_CH14_INT INT_NUM_IM4_IRL27 // INT_NUM_IM2_IRL27 -+#define IFX_DMA_CH15_INT INT_NUM_IM4_IRL28 // INT_NUM_IM2_IRL28 -+#define IFX_DMA_CH16_INT INT_NUM_IM4_IRL29 // INT_NUM_IM2_IRL29 -+#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 // INT_NUM_IM0_IRL30 -+#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 -+#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 -+ -+#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 // INT_NUM_IM0_IRL23 -+#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 // INT_NUM_IM0_IRL24 -+#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 -+#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 -+ -+#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 -+#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 // INT_NUM_IM2_IRL31 -+#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 // INT_NUM_IM0_IRL26 -+ -+#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 // INT_NUM_IM1_IRL9 -+#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 // INT_NUM_IM1_IRL10 -+#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 // INT_NUM_IM1_IRL11 -+#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 // INT_NUM_IM1_IRL12 -+#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 // INT_NUM_IM1_IRL13 -+#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 // INT_NUM_IM1_IRL14 -+#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 // INT_NUM_IM1_IRL15 -+#define IFX_MPS_IR7 INT_NUM_IM3_IRL29 // INT_NUM_IM0_IRL7 ! MIPS1 -+#define IFX_MPS_IR8 INT_NUM_IM4_IRL21 // INT_NUM_IM3_IRL29 -+#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 -+#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 // INT_NUM_IM1_IRL0 -+#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 // INT_NUM_IM1_IRL1 -+#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 // INT_NUM_IM1_IRL2 -+#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 // INT_NUM_IM1_IRL3 -+#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 // INT_NUM_IM1_IRL4 -+#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 // INT_NUM_IM1_IRL5 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL28 -+ -+#define IFX_EBU_IR INT_NUM_IM0_IRL22 -+ -+#define IFX_PCI_IR INT_NUM_IM2_IRL17 // INT_NUM_IM1_IRL17 -+#define IFX_PCI_WRIR INT_NUM_IM2_IRL18 // INT_NUM_IM1_IRL18 -+ -+#define IFX_PCM_TXIR INT_NUM_IM2_IRL19 // INT_NUM_IM1_IRL19 -+#define IFX_PCM_RXIR INT_NUM_IM2_IRL20 // INT_NUM_IM1_IRL20 -+ -+#define IFX_PMCIR INT_NUM_IM4_IRL31 // INT_NUM_IM2_IRL30 -+ -+#define IFX_SBIU0_ERRIR INT_NUM_IM1_IRL27 -+#define IFX_SBIU1_ERRIR INT_NUM_IM1_IRL28 -+#define IFX_SBIU_ERRIR IFX_SBIU0_ERRIR -+ -+#define IFX_SSC_RIR INT_NUM_IM3_IRL14 // INT_NUM_IM0_IRL14 -+#define IFX_SSC_TIR INT_NUM_IM3_IRL15 // INT_NUM_IM0_IRL15 -+#define IFX_SSC_EIR INT_NUM_IM3_IRL16 // INT_NUM_IM0_IRL16 -+#define IFX_SSC_FIR INT_NUM_IM3_IRL17 // INT_NUM_IM0_IRL17 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM3_IRL18 // INT_NUM_IM0_IRL18 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM3_IRL19 // INT_NUM_IM0_IRL19 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM3_IRL20 // INT_NUM_IM0_IRL20 -+ -+#define IFX_USB0_IR INT_NUM_IM2_IRL22 // INT_NUM_IM1_IRL22 -+#define IFX_USB0_OCIR INT_NUM_IM4_IRL23 -+#define IFX_USB_INT IFX_USB0_IR -+#define IFX_USB_OC_INT IFX_USB0_OCIR -+ -+#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 -+ -+ -+ -+#endif // DANUBE_IRQ -diff --git a/arch/mips/include/asm/ifx/danube/model.h b/arch/mips/include/asm/ifx/danube/model.h -new file mode 100644 -index 0000000..befff4c ---- /dev/null -+++ b/arch/mips/include/asm/ifx/danube/model.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for Danube -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef DANUBE_MODEL_H -+#define DANUBE_MODEL_H -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define BOARD_SYSTEM_TYPE "Danube" -+#define SYSTEM_MODEL_NAME "Danube Reference Board BSP26" -+#endif -diff --git a/arch/mips/include/asm/ifx/hn1/emulation.h b/arch/mips/include/asm/ifx/hn1/emulation.h -new file mode 100644 -index 0000000..68a7093 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/emulation.h -@@ -0,0 +1,40 @@ -+/****************************************************************************** -+** -+** FILE NAME : emulation.h -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Lei Chuan Hua -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2011 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+*******************************************************************************/ -+ -+ -+ -+#ifndef EMULATION_H -+#define EMULATION_H -+ -+#ifdef CONFIG_USE_EMULATOR -+ -+//For Palladium using db.rel_106.c database the EMULATOR_CPU_SPEED is 271KHz -+ #define EMULATOR_CPU_SPEED 271000 -+ #define PLL0_CLK_SPEED 271000 -+ -+#else /* Real chip */ -+ #define PLL0_CLK_SPEED 1000000000 -+#endif /* CONFIG_USE_EMULATOR */ -+ -+ -+#endif /* */ -+ /* EMULATION_H */ -+ -diff --git a/arch/mips/include/asm/ifx/hn1/hn1.h b/arch/mips/include/asm/ifx/hn1/hn1.h -new file mode 100644 -index 0000000..8c0037d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/hn1.h -@@ -0,0 +1,1293 @@ -+/****************************************************************************** -+** -+** FILE NAME : hn1.h -+** MODULES : BSP Basic -+** -+** DATE : 11 Jan 2011 -+** AUTHOR : Kishore Kankipati -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 11 Jan 2011 Kishore First version for HN1 derived from VR9 -+** 11 Feb 2011 Yinglei Modified for HN1 -+*******************************************************************************/ -+ -+ -+ -+#ifndef HN1_H -+#define HN1_H -+ -+#include <asm/bootinfo.h> -+ -+#define MACH_GROUP_IFX MACH_GROUP_HN1 -+#define MACH_TYPE_IFX MACH_HN1 -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ -+ -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) -+#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) -+#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) -+#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) -+#define IFX_RCU_GPHY01_MDIO_ADD ((volatile u32*)(IFX_RCU + 0x0044)) -+#define IFX_RCU_GPHY0_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) -+ -+/* AHB Endian Register */ -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+ -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define IFX_RCU_AHB_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ -+#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_PCIE_DBI 0x00000020 /* Configure DBI module in big endian*/ -+#define IFX_RCU_AHB_BE_DC_PDI 0x00000040 /* Configure DC PDI module in big endian*/ -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ_GPHY0 (1 << 31) -+#define IFX_RCU_RST_REQ_SRST (1 << 30) -+#define IFX_RCU_RST_REQ_GPHY1 (1 << 29) -+#define IFX_RCU_RST_REQ_MIPS0 (1 << 1) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL (IFX_RCU_RST_REQ_SRST | IFX_RCU_RST_REQ_GPHY0 | IFX_RCU_RST_REQ_GPHY1 | IFX_RCU_RST_REQ_MIPS0) -+ -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1E000000) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+/***********************************************************************/ -+/* Module : HSNAND register address and bits */ -+/***********************************************************************/ -+#define IFX_HSNAND_BASE (KSEG1 | 0x1E100400) -+ -+/****** HSNAND REGISTERS *******/ -+#define IFX_NDAC_CTL1 ((volatile u32*)(0x0010 + IFX_HSNAND_BASE)) -+#define IFX_NDAC_CTL2 ((volatile u32*)(0x0014 + IFX_HSNAND_BASE)) -+#define IFX_BASE_A ((volatile u32*)(0x0018 + IFX_HSNAND_BASE)) -+#define IFX_RX_CNT ((volatile u32*)(0x001C + IFX_HSNAND_BASE)) -+#define IFX_DPLUS_CTRL ((volatile u32*)(0x0020 + IFX_HSNAND_BASE)) -+#define IFX_HSNAND_INTR_MASK_CTRL ((volatile u32*)(0x0024 + IFX_HSNAND_BASE)) -+#define IFX_HSNAND_INTR_STAT ((volatile u32*)(0x0028 + IFX_HSNAND_BASE)) -+#define IFX_HSMD_CTRL ((volatile u32*)(0x0030 + IFX_HSNAND_BASE)) -+#define IFX_CS_BASE_A ((volatile u32*)(0x0034 + IFX_HSNAND_BASE)) -+#define IFX_NAND_INFO ((volatile u32*)(0X0038 + IFX_HSNAND_BASE)) -+ -+#define IFX_HSNAND_CE_SEL (0xF<<3) -+#define IFX_HSNAND_CE_SEL_S 3 -+#define IFX_HSNAND_CE_SEL_NONE 0 -+#define IFX_HSNAND_CE_SEL_CS0 1 -+#define IFX_HSNAND_CE_SEL_CS1 2 -+#define IFX_HSNAND_CE_SEL_CS2 4 -+#define IFX_HSNAND_CE_SEL_CS3 8 -+ -+#define IFX_HSNAND_FSM (1<<2) -+#define IFX_HSNAND_FSM_S 2 -+enum { -+ IFX_HSNAND_FSM_DISABLED = 0, -+ IFX_HSNAND_FSM_ENABLED, -+}; -+ -+#define IFX_HSNAND_ENR (3<<0) -+#define IFX_HSNAND_ENR_S 0 -+enum { -+ IFX_HSNAND_ENR_XIP = 0, -+ IFX_HSNAND_ENR_HSDMA, -+ IFX_HSNAND_ENR_IO, -+ IFX_HSNAND_ENR_NONE -+}; -+ -+#define IFX_HSNAND_XFER_SEL (7<<0) -+#define IFX_HSNAND_XFER_SEL_S 7 -+enum { -+ IFX_HSNAND_NO_XFER = 0, -+ IFX_HSNAND_START_XFER -+}; -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 2 Data Output Register (0070H)***/ -+#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) -+/***Port 3 Data Output Register (00A0H)***/ -+#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 2 Data Input Register (0074H)***/ -+#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) -+/***Port 3 Data Input Register (00A4H)***/ -+#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 2 Direction Register (0078H)***/ -+#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) -+/***Port 3 Direction Register (0048H)***/ -+#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 2 Alternate Function Select Register 0 (007C H) ***/ -+#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) -+/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ -+#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ -+#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) -+/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ -+#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 2 Open Drain Control Register (0084H)***/ -+#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) -+/***Port 3 Open Drain Control Register (0034H)***/ -+#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ -+#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) -+/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ -+ -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ -+#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) -+/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ -+#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+/***Port 2 Pull Up Device Enable Register (0090 H)***/ -+#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) -+/***Port 3 Pull Up Device Enable Register (003c H)***/ -+#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU CGU Clock Frequency Select Register***/ -+#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) -+/**Update CGU Register***/ -+#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) -+/***CGU Interface Clock Control Register***/ -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x1E105300) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL0_REGEN (1 << 0) -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL2_REGEN (1 << 0) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) -+#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL3_REGEN (1 << 0) -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) -+ -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_PG_EN 0x20000000 -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+ }; -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+ }; -+ -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+ -+#define IFX_EBU_BUSCON1_WRDIS (1 << 31) -+//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) -+//#define IFX_EBU_BUSCON1_SETUP (1 << 18) -+//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+#define IFX_EBU_BUSCON2_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON2_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON2_SETUP (1 << 18) -+#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) -+#define IFX_EBU_BUSCON3_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) -+#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) -+#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON3_SETUP (1 << 22) -+#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON3_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON3_VN_EN (1 << 18) -+#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) -+#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) -+#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+#define IFX_EBU_PCC_ISTAT IFX_EBU_ECC_ISTAT -+#define IFX_EBU_ECC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) -+#define IFX_EBU_ECC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) -+#define IFX_EBU_ECC_IEN_PCI_EN 0x00000010 -+ -+#define IFX_EBU_ECC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) -+ -+#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) -+#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+#define IFX_EBU_NAND_ECC_CR (volatile u32*)(IFX_EBU + 0xC0) -+#define IFX_EBU_SYN_CON1 (volatile u32*)(IFX_EBU + 0xC4) -+ -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_ALE_P (1<<2) -+#define IFX_EBU_NAND_CON_ALE_P_S 2 -+enum { -+ IFX_EBU_NAND_CON_ALE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_ALE_P_LOW, -+}; -+ -+#define IFX_EBU_NAND_CON_CLE_P (1<<3) -+#define IFX_EBU_NAND_CON_CLE_P_S 3 -+enum { -+ IFX_EBU_NAND_CON_CLE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CLE_P_LOW, -+}; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+ }; -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_ECC (1<<31) -+#define IFX_EBU_NAND_CON_ECC_S 31 -+enum { -+ IFX_EBU_NAND_CON_ECC_OFF = 0, -+ IFX_EBU_NAND_CON_ECC_ON, -+}; -+ -+#define IFX_EBU_NAND_CON_LAT_EN (0x3F << 18) -+#define IFX_EBU_NAND_CON_LAT_EN_S 18 -+enum { -+ IFX_EBU_NAND_CON_LAT_EN_DEF = 0x3D, -+}; -+ -+#define IFX_EBU_NAND_ECC_CRM (1<<31) -+#define IFX_EBU_NAND_ECC_CRM_S 31 -+enum { -+ IFX_EBU_NAND_ECC_CRM_DISABLE = 0, -+ IFX_EBU_NAND_ECC_CRM_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_ECC_PAGE (3<<14) -+#define IFX_EBU_NAND_ECC_PAGE_S 14 -+enum { -+ IFX_EBU_NAND_ECC_PAGE_256 = 0, -+ IFX_EBU_NAND_ECC_PAGE_512, -+ IFX_EBU_NAND_ECC_PAGE_RES, -+}; -+ -+#define IFX_EBU_ECC_IEN_IR (1<<5) -+#define IFX_EBU_ECC_IEN_IR_S 5 -+enum { -+ IFX_EBU_ECC_IEN_DISABLE = 0, -+ IFX_EBU_ECC_IEN_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_ECC_STATE (3<<0) -+#define IFX_EBU_NAND_ECC_STATE_S 0 -+ -+#define IFX_EBU_NAND_ECC_ROW_VAL (0x1FF<<5) -+#define IFX_EBU_NAND_ECC_ROW_VAL_S 5 -+ -+#define IFX_EBU_NAND_ECC_BIT_POS (7<<2) -+#define IFX_EBU_NAND_ECC_BIT_POS_S 2 -+ -+#define IFX_EBU_NAND_WAIT_RD (0x1) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#if 0 //YLH: Not exist anymore -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+/***MC Status Register***/ -+#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) -+ -+/***MC DDR Control Register 00***/ -+#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) -+/***MC DDR Control Register 03***/ -+#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) -+/***MC DDR Control Register 17***/ -+#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) -+#endif -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+/***ASC Clock Control Register***/ -+#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) -+#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_ASC1_CLC_DISS (1 << 1) -+#define IFX_ASC1_CLC_DISR (1 << 0) -+ -+/***ASC Port Input Select Register***/ -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_ID ((volatile u32*)(IFX_ASC1 + 0x0008)) -+#define IFX_ASC1_PISEL_RIS (1 << 0) -+ -+/***ASC Control Register***/ -+#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) -+#define IFX_ASC1_CON_BEN (1 << 20) -+#define IFX_ASC1_CON_TOEN (1 << 20) -+#define IFX_ASC1_CON_ROEN (1 << 19) -+#define IFX_ASC1_CON_RUEN (1 << 18) -+#define IFX_ASC1_CON_FEN (1 << 17) -+#define IFX_ASC1_CON_PAL (1 << 16) -+#define IFX_ASC1_CON_R (1 << 15) -+#define IFX_ASC1_CON_ACO (1 << 14) -+#define IFX_ASC1_CON_LB (1 << 13) -+#define IFX_ASC1_CON_ERCLK (1 << 10) -+#define IFX_ASC1_CON_FDE (1 << 9) -+#define IFX_ASC1_CON_BRS (1 << 8) -+#define IFX_ASC1_CON_STP (1 << 7) -+#define IFX_ASC1_CON_SP (1 << 6) -+#define IFX_ASC1_CON_ODD (1 << 5) -+#define IFX_ASC1_CON_PEN (1 << 4) -+#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***ASC Staus Register***/ -+#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) -+/***ASC Write Hardware Modified Control Register***/ -+#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) -+#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) -+#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) -+#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) -+#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) -+#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) -+#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) -+#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) -+#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) -+#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) -+#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) -+#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) -+#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) -+#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) -+ -+/***ASC Baudrate Timer/Reload Register***/ -+#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) -+#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) -+ -+/***ASC Fractional Divider Register***/ -+#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0058)) -+#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Transmit Buffer Register***/ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Receive Buffer Register***/ -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Autobaud Control Register***/ -+#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) -+#define IFX_ASC1_ABCON_RXINV (1 << 11) -+#define IFX_ASC1_ABCON_TXINV (1 << 10) -+#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -+#define IFX_ASC1_ABCON_FCDETEN (1 << 4) -+#define IFX_ASC1_ABCON_ABDETEN (1 << 3) -+#define IFX_ASC1_ABCON_ABSTEN (1 << 2) -+#define IFX_ASC1_ABCON_AUREN (1 << 1) -+#define IFX_ASC1_ABCON_ABEN (1 << 0) -+ -+/***Receive FIFO Control Register***/ -+#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) -+#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) -+#define IFX_ASC1_RXFCON_RXFEN (1 << 0) -+ -+/***Transmit FIFO Control Register***/ -+#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) -+#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) -+#define IFX_ASC1_TXFCON_TXFEN (1 << 0) -+ -+/***FIFO Status Register***/ -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -+#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+/***ASC Autobaud Status Register***/ -+#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) -+#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) -+#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) -+#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) -+#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) -+#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) -+ -+/***ASC Write HW Modified Autobaud Status Register***/ -+#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) -+#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) -+#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) -+#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) -+#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) -+#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) -+#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) -+#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) -+#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) -+#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) -+#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) -+ -+/***ASC IRNCR0 **/ -+#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) -+#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) -+/***ASC IRNCR1 **/ -+#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) -+#define IFX_ASC_IRNCR_TIR 0x1 -+#define IFX_ASC_IRNCR_RIR 0x2 -+#define IFX_ASC_IRNCR_EIR 0x4 -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) -+ -+#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) -+#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) -+#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) -+#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) -+#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) -+#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) -+ -+#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) -+#define IFX_DMA_CDPTNRD (volatile u32*)(IFX_DMA_BASE + 0x34) -+ -+#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) -+#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) -+/* Global Software Reset (0) */ -+#define IFX_DMA_CTRL_RST (0x1) -+ -+/* Channel Polling Register */ -+ -+/* Enable (31) */ -+#define IFX_DMA_CPOLL_EN (0x1 << 31) -+#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) -+ -+/* Counter (15:4) */ -+#define IFX_DMA_CPOLL_CNT (0xfff << 4) -+#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) -+ -+/* Channel Control Register */ -+ -+/* Peripheral to Peripheral Copy (24) */ -+#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) -+#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) -+#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) -+ -+/* Channel Weight for Transmit Direction (17:16) */ -+#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) -+#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) -+#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) -+ -+/* Port Assignment (13:11) */ -+#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) -+#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) -+ -+/* Class (10:9) */ -+#define IFX_DMA_CCTRL_CLASS (0x3 << 9) -+#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) -+#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) -+ -+/* Direction (8) */ -+#define IFX_DMA_CCTRL_DIR (0x1 << 8) -+/* Reset (1) */ -+#define IFX_DMA_CCTRL_RST (0x1 << 1) -+/* Channel On or Off (0) */ -+#define IFX_DMA_CCTRL_ON (0x1) -+ -+/* Channel Interrupt Status Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIS_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIS_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt (3) */ -+#define IFX_DMA_CIS_DESCPT (0x1 << 3) -+/* Descriptor Under-Run Interrupt (2) */ -+#define IFX_DMA_CIS_DUR (0x1 << 2) -+/* End of Packet Interrupt (1) */ -+#define IFX_DMA_CIS_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ -+ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ -+ IFX_DMA_CIS_EOP) -+ -+/* Channel Interrupt Enable Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIE_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIE_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt Enable (3) */ -+#define IFX_DMA_CIE_DESCPT (0x1 << 3) -+/* Descriptor Under Run Interrupt Enable (2) */ -+#define IFX_DMA_CIE_DUR (0x1 << 2) -+/* End of Packet Interrupt Enable (1) */ -+#define IFX_DMA_CIE_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) -+ -+/* Port Select Register */ -+ -+/* Port Selection (2:0) */ -+#define IFX_DMA_PS_PS (0x7) -+#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) -+ -+/* Port Control Register */ -+ -+/* General Purpose Control (16) */ -+#define IFX_DMA_PCTRL_GPC (0x1 << 16) -+#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) -+ -+/* Port Weight for Transmit Direction (14:12) */ -+#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) -+#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) -+/* Endianness for Transmit Direction (11:10) */ -+#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) -+#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) -+/* Endianness for Receive Direction (9:8) */ -+#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) -+#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) -+/* Packet Drop Enable (6) */ -+#define IFX_DMA_PCTRL_PDEN (0x1 << 6) -+#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) -+/* Burst Length for Transmit Direction (5:4) */ -+#define IFX_DMA_PCTRL_TXBL (0x3 << 4) -+#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) -+/* Burst Length for Receive Direction (3:2) */ -+#define IFX_DMA_PCTRL_RXBL (0x3 << 2) -+#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+ -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+ -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+ -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+ -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00C8)) -+ -+/***********************************************************************/ -+ -+#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) -+#define IFX_ICU1 IFX_ICU_VPE1 -+ -+#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) -+#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) -+#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) -+#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) -+#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) -+ -+#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) -+#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) -+#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) -+#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) -+#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) -+ -+#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) -+#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) -+#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) -+#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) -+#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) -+ -+#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) -+#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) -+#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) -+#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) -+#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) -+ -+#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) -+#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) -+#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) -+#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) -+#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) -+#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC -+ -+/* MSI PIC */ -+#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) -+ -+#define IFX_MSI_PIC_BIG_ENDIAN 1 -+#define IFX_MSI_PIC_LITTLE_ENDIAN 0 -+ -+#define IFX_MSI_PCI_INT_DISABLE 0x80000000 -+#define IFX_MSI_PIC_INT_LINE 0x30000000 -+#define IFX_MSI_PIC_INT_LINE_S 28 -+#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 -+#define IFX_MSI_PIC_MSG_ADDR_S 16 -+#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF -+#define IFX_MSI_PIC_MSG_DATA_S 0x0 -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) -+#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) -+#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) -+#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) -+#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1 | 0x1F101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) -+#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) -+#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) -+#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) -+ -+ -+/* notification enable register */ -+#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) -+#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) -+/* CPU to CPU interrup request register */ -+#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) -+#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) -+/* Global interrupt request and request enable register */ -+#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) -+#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) -+#define IFX_MPS_VPE0_2_VPE1_ICR ((volatile u32*)(IFX_MPS + 0x0080)) -+#define IFX_MPS_VPE0_2_VPE1_IRDR ((volatile u32*)(IFX_MPS + 0x0084)) -+#define IFX_MPS_GIRDR ((volatile u32*)(IFX_MPS + 0x0088)) -+#define IFX_MPS_GICR ((volatile u32*)(IFX_MPS + 0x008C)) -+#define IFX_MPS_VPE0_NFICR ((volatile u32*)(IFX_MPS + 0x0090)) -+#define IFX_MPS_VPE1_NFICR ((volatile u32*)(IFX_MPS + 0x0094)) -+#define IFX_MPS_VPE0_BINSEM0 ((volatile u32*)(IFX_MPS + 0x0100)) -+#define IFX_MPS_VPE1_BINSEM0 ((volatile u32*)(IFX_MPS + 0x0200)) -+ -+#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) -+ -+#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) -+ -+//YLH: 0x354 is FAB_LOT_ID0, 0x35C is chip configuration fuse register -+// -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+/************************************************************************/ -+/* Module : XBAR Register definition */ -+/************************************************************************/ -+#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) -+ -+#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) -+#define IFX_XBAR_FPI_BURST_EN 0x00000002 -+#define IFX_XBAR_AHB_BURST_EN 0x00000004 -+#define IFX_XBAR_DDR_SEL_EN 0x00000001 -+ -+/* -+ * Routine for Voice -+ */ -+extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); -+ -+#endif /* HN1_H */ -diff --git a/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h b/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h -new file mode 100644 -index 0000000..e017045 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/hn1_eval_board.h -@@ -0,0 +1,36 @@ -+/****************************************************************************** -+** -+** FILE NAME : hn1_eval_board.h -+** MODULES : BSP Basic -+** -+** DATE : 11 Jan 2011 -+** AUTHOR : Kishore Kankipati -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 11 Jan 2011 Kishore First version for HN1 derived from VR9 -+*******************************************************************************/ -+ -+#ifndef HN1_EVAL_BOARD_H -+#define HN1_EVAL_BOARD_H -+#ifndef AUTOCONF_INCLUDED -+#include <linux/config.h> -+#endif /* AUTOCONF_INCLUDED */ -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ -+ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 8 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#endif /* HN1_EVAL_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h b/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h -new file mode 100644 -index 0000000..330f65d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/hn1_ref_board.h -@@ -0,0 +1,36 @@ -+/****************************************************************************** -+** -+** FILE NAME : hn1_ref_board.h -+** MODULES : BSP Basic -+** -+** DATE : 11 Jan 2011 -+** AUTHOR : Kishore Kankipati -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 11 Jan 2011 Kishore First version for HN1 derived from VR9 -+*******************************************************************************/ -+ -+#ifndef HN1_REF_BOARD_H -+#define HN1_REF_BOARD_H -+#ifndef AUTOCONF_INCLUDED -+#include <linux/config.h> -+#endif /* AUTOCONF_INCLUDED */ -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ -+ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 8 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#endif /* HN1_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/hn1/irq.h b/arch/mips/include/asm/ifx/hn1/irq.h -new file mode 100644 -index 0000000..4700d5e ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/irq.h -@@ -0,0 +1,183 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : HN1 -+** MODULES : BSP Basic -+** -+** DATE : 11 January 2011 -+** AUTHOR : Kishore Kankipati -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 11 Jan 2011 Kishore Kankipati The first HN1 release (file derived from VR9) -+** 11 Feb 2011 Yinglei Modified for HN1 -+** 13 May 2011 Kishore Kankipati Added defintion of missing interrupts. -+*******************************************************************************/ -+ -+ -+#ifndef HN1_IRQ_H -+#define HN1_IRQ_H -+ -+ -+ -+/****** Interrupt Assigments based on HN1_SOC_SAS_V1.0.4_Spec.pdf, P. 701-707***********/ -+ -+#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ -+#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ -+#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ -+#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ -+#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 -+#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 -+#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 -+#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_HN1_ZERO_CROSS_INT INT_NUM_IM1_IRL21 -+#define IFX_HN1_DFE_INT0IR INT_NUM_IM2_IRL12 -+#define IFX_HN1_DFE_INT1IR INT_NUM_IM2_IRL13 -+#define IFX_HN1_DFE_INT2IR INT_NUM_IM2_IRL14 -+#define IFX_HN1_DFE_INT3IR INT_NUM_IM2_IRL15 -+#define IFX_HN1_DFE_TXIR IFX_HN1_DFE_INT0IR -+#define IFX_HN1_DFE_RXIR IFX_HN1_DFE_INT1IR -+ -+#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 -+#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 -+#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 -+#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 -+#define IFX_PCIE_IR INT_NUM_IM4_IRL25 -+#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 -+#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 -+#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 -+#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 -+#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 -+#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 -+ -+#define IFX_HN1_I2C_IR0 INT_NUM_IM1_IRL3 -+#define IFX_HN1_I2C_IR1 INT_NUM_IM1_IRL4 -+#define IFX_HN1_I2C_IR2 INT_NUM_IM1_IRL5 -+#define IFX_HN1_I2C_IR3 INT_NUM_IM1_IRL6 -+#define IFX_HN1_I2C_IR4 INT_NUM_IM1_IRL7 -+#define IFX_HN1_I2C_IR5 INT_NUM_IM1_IRL8 -+ -+#define IFX_HN1_I2S_IR0 INT_NUM_IM0_IRL11 -+#define IFX_HN1_I2S_IR1 INT_NUM_IM0_IRL12 -+#define IFX_HN1_I2S_IR2 INT_NUM_IM0_IRL23 -+#define IFX_HN1_I2S_IR3 INT_NUM_IM0_IRL24 -+#define IFX_HN1_I2S_IR4 INT_NUM_IM0_IRL26 -+#define IFX_HN1_I2S_IR5 INT_NUM_IM0_IRL27 -+#define IFX_HN1_I2S_IR6 INT_NUM_IM0_IRL28 -+#define IFX_HN1_I2S_IR7 INT_NUM_IM0_IRL29 -+#define IFX_HN1_I2S_IR8 INT_NUM_IM0_IRL31 -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 -+#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 -+#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 -+#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 -+#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 -+#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 -+#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 -+#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 -+#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 -+#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 -+#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 -+#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 -+#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 -+#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 -+#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 -+#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 -+#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 -+#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 -+#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 -+#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 -+ -+#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 -+ -+#define IFX_GPHY_INT INT_NUM_IM3_IRL18 -+ -+#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ -+#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ -+#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ -+#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ -+#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ -+#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ -+#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ -+ -+#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 -+#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 -+#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 -+#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 -+#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 -+#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 -+#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 -+#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 -+#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 -+#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 -+#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 -+ -+#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 -+#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 -+#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 -+#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 -+#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 -+#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL28 -+ -+#define IFX_EBU_IR INT_NUM_IM0_IRL22 -+ -+#define IFX_PCI_IR INT_NUM_IM1_IRL17 -+#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 -+ -+#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 -+#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 -+ -+#define IFX_PMCIR INT_NUM_IM4_IRL31 -+ -+#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 -+ -+#define IFX_SSC_RIR INT_NUM_IM0_IRL14 -+#define IFX_SSC_TIR INT_NUM_IM0_IRL15 -+#define IFX_SSC_EIR INT_NUM_IM0_IRL16 -+#define IFX_SSC_FIR INT_NUM_IM0_IRL17 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 -+ -+#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 -+ -+#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 -+#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 -+#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 -+#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 -+#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 -+#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 -+ -+#define IFX_AHB1S_BUS_ERROR INT_NUM_IM3_IRL1 -+ -+#endif // HN1_IRQ_H -+ -diff --git a/arch/mips/include/asm/ifx/hn1/model.h b/arch/mips/include/asm/ifx/hn1/model.h -new file mode 100644 -index 0000000..b7ac967 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/hn1/model.h -@@ -0,0 +1,28 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** MODULES : BSP Basic -+** -+** DATE : 11 Jan 2011 -+** AUTHOR : Kishore -+** DESCRIPTION : header file for HN1 -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 11 Jan 2011 Kishore -+*******************************************************************************/ -+ -+ -+#ifndef HN1_MODEL_H -+#define HN1_MODEL_H -+#define BOARD_SYSTEM_TYPE "HNX100" -+#define SYSTEM_MODEL_NAME "HNX Eval Version" -+#endif -diff --git a/arch/mips/include/asm/ifx/ifx_atm.h b/arch/mips/include/asm/ifx/ifx_atm.h -new file mode 100644 -index 0000000..bf045a9 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_atm.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_atm.h -+** PROJECT : UEIP -+** MODULES : ATM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ATM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_ATM_H -+#define IFX_ATM_H -+ -+ -+ -+/*! -+ \defgroup IFX_ATM UEIP Project - ATM driver module -+ \brief UEIP Project - ATM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_IOCTL IOCTL Commands -+ \ingroup IFX_ATM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_ATM_STRUCT Structures -+ \ingroup IFX_ATM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_atm.h -+ \ingroup IFX_ATM -+ \brief ATM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ATM MIB -+ */ -+ -+/*! -+ \struct atm_cell_ifEntry_t -+ \brief Structure used for Cell Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_CELL". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress cells (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress cells (lower 32 bits, total 64 bits) */ -+ __u32 ifInErrors; /*!< counter of error ingress cells */ -+ __u32 ifInUnknownProtos; /*!< counter of unknown ingress cells */ -+ __u32 ifOutErrors; /*!< counter of error egress cells */ -+} atm_cell_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_ifEntry_t -+ \brief Structure used for AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_AAL5". -+ */ -+typedef struct { -+ __u32 ifHCInOctets_h; /*!< byte counter of ingress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCInOctets_l; /*!< byte counter of ingress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_h; /*!< byte counter of egress packets (upper 32 bits, total 64 bits) */ -+ __u32 ifHCOutOctets_l; /*!< byte counter of egress packets (lower 32 bits, total 64 bits) */ -+ __u32 ifInUcastPkts; /*!< counter of ingress packets */ -+ __u32 ifOutUcastPkts; /*!< counter of egress packets */ -+ __u32 ifInErrors; /*!< counter of error ingress packets */ -+ __u32 ifInDiscards; /*!< counter of dropped ingress packets */ -+ __u32 ifOutErros; /*!< counter of error egress packets */ -+ __u32 ifOutDiscards; /*!< counter of dropped egress packets */ -+} atm_aal5_ifEntry_t; -+ -+/*! -+ \struct atm_aal5_vcc_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ This structure is a part of structure "atm_aal5_vcc_x_t". -+ */ -+typedef struct { -+ __u32 aal5VccCrcErrors; /*!< counter of ingress packets with CRC error */ -+ __u32 aal5VccSarTimeOuts; /*!< counter of ingress packets with Re-assemble timeout */ //no timer support yet -+ __u32 aal5VccOverSizedSDUs; /*!< counter of oversized ingress packets */ -+} atm_aal5_vcc_t; -+ -+/*! -+ \struct atm_aal5_vcc_x_t -+ \brief Structure used for per PVC AAL5 Frame Level MIB Counters. -+ -+ User application use this structure to call IOCTL command "PPE_ATM_MIB_VCC". -+ */ -+typedef struct { -+ int vpi; /*!< VPI of the VCC to get MIB counters */ -+ int vci; /*!< VCI of the VCC to get MIB counters */ -+ atm_aal5_vcc_t mib_vcc; /*!< structure to get MIB counters */ -+} atm_aal5_vcc_x_t; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_ATM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief ATM IOCTL Magic Number -+ */ -+#define PPE_ATM_IOC_MAGIC 'o' -+/*! -+ \brief ATM IOCTL Command - Get Cell Level MIB Counters -+ -+ This command is obsolete. User can get cell level MIB from DSL API. -+ This command uses structure "atm_cell_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_CELL _IOW(PPE_ATM_IOC_MAGIC, 0, atm_cell_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get AAL5 Level MIB Counters -+ -+ Get AAL5 packet counters. -+ This command uses structure "atm_aal5_ifEntry_t" as parameter for output of MIB counters. -+ */ -+#define PPE_ATM_MIB_AAL5 _IOW(PPE_ATM_IOC_MAGIC, 1, atm_aal5_ifEntry_t) -+/*! -+ \brief ATM IOCTL Command - Get Per PVC MIB Counters -+ -+ Get AAL5 packet counters for each PVC. -+ This command uses structure "atm_aal5_vcc_x_t" as parameter for input of VPI/VCI information and output of MIB counters. -+ */ -+#define PPE_ATM_MIB_VCC _IOWR(PPE_ATM_IOC_MAGIC, 2, atm_aal5_vcc_x_t) -+/*! -+ \brief Total Number of ATM IOCTL Commands -+ */ -+#define PPE_ATM_IOC_MAXNR 3 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_ATM_H -+ -diff --git a/arch/mips/include/asm/ifx/ifx_board.h b/arch/mips/include/asm/ifx/ifx_board.h -new file mode 100644 -index 0000000..e5706e5 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_board.h -@@ -0,0 +1,52 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : common header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_BOARD_H -+#define IFX_BOARD_H -+ -+ -+ -+#if defined(CONFIG_DANUBE) -+# include "danube/danube_ref_board.h" -+#elif defined(CONFIG_AMAZON_SE) -+# include "amazon_se/boards/boards.h" -+#elif defined(CONFIG_AR9) || defined(CONFIG_AR9_CUSTOM_BOARD) -+# include "ar9/ar9_ref_board.h" -+#elif defined(CONFIG_VR9) -+# include "vr9/vr9_ref_board.h" -+#elif defined(CONFIG_AR10) -+# include "ar10/ar10_ref_board.h" -+#elif defined(CONFIG_HN1_EVAL_BOARD) -+# include "hn1/hn1_eval_board.h" -+#elif defined(CONFIG_HN1) -+# include "hn1/hn1_ref_board.h" -+#else -+# error unknown board -+#endif -+ -+ -+ -+#endif // IFX_BOARD_H -+ -diff --git a/arch/mips/include/asm/ifx/ifx_clk.h b/arch/mips/include/asm/ifx/ifx_clk.h -new file mode 100644 -index 0000000..ad45bdf ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_clk.h -@@ -0,0 +1,140 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_clk.h -+** PROJECT : IFX UEIP -+** MODULES : CGU -+** -+** DATE : 28 May 2009 -+** AUTHOR : Huang Xiaogang -+** DESCRIPTION : IFX Cross-Platform Clock Generation Unit driver header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 28 May 2009 Huang Xiaogang The first UEIP release -+*******************************************************************************/ -+ -+#ifndef IFX_CLK_H -+#define IFX_CLK_H -+ -+/*! -+ \defgroup IFX_CGU UEIP Project - CGU driver module -+ \brief UEIP Project - CGU driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_CGU_API APIs -+ \ingroup IFX_CGU -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_CGU_IOCTL IOCTL Commands -+ \ingroup IFX_CGU -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_CGU_STRUCT Structures -+ \ingroup IFX_CGU -+ \brief Structures used by user application. -+ */ -+ -+/*! \file ifx_clk.h -+ \brief This file contains the interface of clock(cgu) driver. -+*/ -+ -+#define IFX_CGU_MAJOR 246 -+ -+#define IFX_CGU_VER_MAJOR 1 -+#define IFX_CGU_VER_MID 1 -+#define IFX_CGU_VER_MINOR 32 -+ -+/*! -+ \addtogroup IFX_CGU_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_cgu_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_cgu_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+/*@}*/ -+ -+/*! -+ \addtogroup IFX_CGU_IOCTL -+ */ -+/*@{*/ -+#define IFX_CGU_IOC_MAGIC 'u' -+/*! -+ \def IFX_CGU_GET_CLOCK_RATES -+ \brief Get Clock rates -+ */ -+#define IFX_CGU_GET_CLOCK_RATES _IOR(IFX_CGU_IOC_MAGIC, 0, struct cgu_clock_rates) -+/*! -+ \def IFX_CGU_IOC_VERSION -+ \brief Get CGU driver version -+ */ -+#define IFX_CGU_IOC_VERSION _IOR(IFX_CGU_IOC_MAGIC, 1, struct ifx_cgu_ioctl_version) -+#define CGU_IOC_MAXNR 1 -+/*@}*/ -+ -+#ifndef CONFIG_USE_EMULATOR -+ #define PLL0_CLK_SPEED 1000000000 -+#endif -+ -+/* -+ * Data Type Used to Call ioctl(GET_CLOCK_RATES) -+ */ -+struct cgu_clock_rates { -+ u32 mips0; -+ u32 mips1; -+ u32 cpu; -+ u32 io_region; -+ u32 fpi_bus1; -+ u32 fpi_bus2; -+ u32 pp32; -+ u32 pci; -+ u32 mii0; -+ u32 mii1; -+ u32 usb; -+ u32 clockout0; -+ u32 clockout1; -+ u32 clockout2; -+ u32 clockout3; -+}; -+ -+#if defined(__KERNEL__) -+ extern u32 cgu_get_cpu_clock(void); -+ extern u32 cgu_get_io_region_clock(void); -+#if defined(CONFIG_VR9) || defined(CONFIG_HN1) -+ extern u32 ifx_get_ddr_hz(void); -+#endif -+#if defined(CONFIG_DANUBE) || defined(CONFIG_VR9) || defined(CONFIG_AR10) || defined(CONFIG_HN1) -+ extern u32 cgu_get_mips_clock(int); -+ extern u32 cgu_get_fpi_bus_clock (int); -+#else -+ extern u32 cgu_get_mips_clock(void); -+ extern u32 cgu_get_fpi_bus_clock(void); -+#endif -+ extern u32 cgu_get_pp32_clock(void); -+ extern u32 cgu_get_qsb_clock(void); -+ extern u32 cgu_get_pci_clock(void); -+ extern u32 cgu_get_ethernet_clock(void); -+ extern u32 cgu_get_usb_clock(void); -+ extern u32 cgu_get_clockout(int); -+#endif // defined(__KERNEL__) -+ -+#endif // IFX_CLK_H -diff --git a/arch/mips/include/asm/ifx/ifx_dcdc.h b/arch/mips/include/asm/ifx/ifx_dcdc.h -new file mode 100644 -index 0000000..75bb9c1 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_dcdc.h -@@ -0,0 +1,255 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_dcdc.h -+** PROJECT : IFX UEIP -+** MODULES : IFX DCDC converter driver -+** DATE : 07 Dec 2010 -+** AUTHOR : Sameer Ahmad -+** DESCRIPTION : IFX Cross platform DCDC converter driver -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 Dec 2010 Sameer Ahmad -+*******************************************************************************/ -+#ifndef _IFX_DCDC_H_ -+#define _IFX_DCDC_H_ -+#include "linux/spinlock.h" -+ -+//#define IFX_DEBUG -+#ifdef IFX_DEBUG -+#define IFX_DCDC_PRINT(format, arg...) \ -+ printk(format, ##arg) -+#else -+#define IFX_DCDC_PRINT(format, arg...) \ -+ do {} while(0) -+#endif -+ -+/*DCDC drive ioctl control*/ -+ -+/*DCDC driver IOCTL magic number*/ -+#define IFX_DCDC_IOCTL_MAGIC 0xd0 -+/*IOCTL command to read the DCDC driver version*/ -+#define IFX_DCDC_VERSION _IOR(IFX_DCDC_IOCTL_MAGIC, 0, char*) -+/*IOCTL comand to read the power state*/ -+#define IFX_DCDC_PWSTATE_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 1, int) -+/*IOCTL command to query the voltage*/ -+#define IFX_DCDC_VOLTAGE_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 2, int) -+/*IOCTL command to query the voltage level*/ -+#define IFX_DCDC_VOLTAGE_LEVEL_QUERY _IOR(IFX_DCDC_IOCTL_MAGIC, 3, int) -+ -+/* Name of the DCDC device*/ -+#define IFX_DCDC_DEV_NAME "ifx_dcdc" -+#define IFX_DCDC_DEV_NAMSIZ 16 -+#define IFX_DCDC_DRV_VERSION "1.0.3" -+#define IFX_SUCCESS 0 -+#define IFX_ERROR -1 -+/* DCDC Converter Core Voltage Level: Table to Map the Power state to voltage -+* is maintained by the CPU driver and we define the core voltage level params -+* as integers and following is the mapping -+* 930 ----> .93 V -+* 1000 ----> 1.0 V -+* 1175 ----> 1.175 V -+*/ -+#define IFX_DCDC_CORE_VOLTAGE_930 930 -+#define IFX_DCDC_CORE_VOLTAGE_1000 1000 -+#define IFX_DCDC_CORE_VOLTAGE_1050 1050 -+#define IFX_DCDC_CORE_VOLTAGE_1175 1175 -+#define IFX_DCDC_MAX_VOLTAGE_LEVELS 3 -+#define IFX_DIGREF_DEFAULT_VALUE 1000 -+#define IFX_DIGREF_DEFAULT_BITMASK 0x7f -+ -+/*Define Bit mask corrosponding to the core voltage*/ -+#define IFX_DCDC_CORE_VOLTAGE_930_BITMASK 0x0 -+#define IFX_DCDC_CORE_VOLTAGE_1000_BITMASK 0x1 -+#define IFX_DCDC_CORE_VOLTAGE_1050_BITMASK 0x2 -+#define IFX_DCDC_CORE_VOLTAGE_1175_BITMASK 0x3 -+/*DCDC ABSOLUTE REGISTER BASE ADDRESS*/ -+#define IFX_DCDC_MODULE_BASE_ADDRESS 0x1F106A00 -+#define IFX_DCDC_ABSOLUTE_REGISTER_ADDR KSEG1ADDR(IFX_DCDC_MODULE_BASE_ADDRESS) -+/* -+* DCDC Device struct -+*/ -+typedef struct _dcdc_dev { -+ char name[16]; -+ int major_num; -+ int minor_num; -+ unsigned int Current_voltage; -+ unsigned int Power_state; -+ spinlock_t ifx_dcdc_lock; -+}DcDcDevt; -+ -+/* -+* DCDC Converter Registers definition -+*/ -+ -+/*Clock setup register 0*/ -+typedef union _Clock_setup0_t { -+ unsigned char byte; -+ struct _Clock_setup0_reg { -+ unsigned char mdll_byp : 1; -+ unsigned char clk_sel_p : 1; -+ unsigned char mdll_m : 6; -+ }Clock_setup0_reg; -+} __attribute__((packed)) Clock_setup0_t; -+ -+/*Clock setup register 1*/ -+typedef union _Clock_setup1_t { -+ unsigned char byte; -+ struct _Clock_setup1_reg { -+ unsigned char res0 : 2; -+ unsigned char sel_div25 : 1; -+ unsigned char clk_sel_adc : 1; -+ unsigned char mdll_ix2 : 1; -+ unsigned char mdll_res : 2; -+ unsigned char res1 : 1; -+ }Clock_setup1_reg; -+} __attribute__((packed)) Clock_setup1_t; -+ -+/*BIAS setting register*/ -+typedef union _Bias_Vreg0_t { -+ unsigned char byte; -+ struct _Bias_reg { -+ unsigned char res0 : 1; -+ unsigned char ii_loadinc : 1; -+ unsigned char ii_red : 1; -+ unsigned char vreg_sel : 2; -+ unsigned char vref_sel : 3; -+ }Bias_reg; -+} __attribute__((packed)) Bias_Vreg0_t; -+ -+/*ADC setting register*/ -+typedef union _Adc_Gen0_t { -+ unsigned char byte; -+ struct _Adc_reg0 { -+ unsigned char iset_lsb_dr : 1; -+ unsigned char del_inc_p : 1; -+ unsigned char del_inc_n : 1; -+ unsigned char out_inv : 1; -+ unsigned char os_en8 : 1; -+ unsigned char os_en : 1; -+ unsigned char pfm_mode : 1; -+ unsigned char forc_sta_dc : 1; -+ }Adc_reg0; -+} __attribute__((packed)) Adc_Gen0_t; -+ -+/*ADC setting register*/ -+typedef union _Adc_Gen1_t { -+ unsigned char byte; -+ struct _Adc_reg1 { -+ unsigned char set_ROM_sel : 2; -+ unsigned char set_coma : 3; -+ unsigned char set_compr : 3; -+ }Adc_reg1; -+} __attribute__((packed)) Adc_Gen1_t; -+ -+/*ADC Configure setting register*/ -+typedef union _Adc_CON0_t { -+ unsigned char byte; -+ struct _Adc_Con0 { -+ unsigned char res0 : 1; -+ unsigned char set_scr : 2; -+ unsigned char set_compc : 3; -+ unsigned char set_off_cal : 1; -+ unsigned char set_rsta : 1; -+ }Adc_Con0; -+} __attribute__((packed)) Adc_CON0_t; -+ -+/*ADC Configure setting register*/ -+typedef union _Adc_CON1_t { -+ unsigned char byte; -+ struct _Adc_Con1 { -+ unsigned char set_start : 4; -+ unsigned char set_Rstart : 4; -+ }Adc_Con1; -+} __attribute__((packed)) Adc_CON1_t; -+ -+/*OSC Configure setting register*/ -+typedef union _Osc_Conf_t { -+ unsigned char byte; -+ struct _Osc_Conf { -+ unsigned char pd_osc : 1; -+ unsigned char res0 : 4; -+ unsigned char SHP_By : 1; -+ unsigned char CAPUP : 1; -+ unsigned char res1 : 1; -+ }Osc_Conf; -+} __attribute__((packed)) Osc_Conf_t; -+ -+/*OSC Status register*/ -+typedef union _Osc_Status_t { -+ unsigned char byte; -+ struct _Osc_Status { -+ unsigned char res0 : 7; -+ unsigned char Clk_Det : 1; -+ }Osc_Status; -+} __attribute__((packed)) Osc_Status_t; -+ -+/*NON OV delay register*/ -+typedef union _NonOv_Delay_t { -+ unsigned char byte; -+ struct _NonOv_Delay { -+ unsigned char Delay_P :4; -+ unsigned char Delay_N :4; -+ }NonOv_Delay; -+}__attribute__((packed))NonOv_Delay_t; -+ -+/* Register MAP of DCDC converter*/ -+ -+typedef struct _Dcdc_register_map { -+ unsigned char B0_Coeh; -+ unsigned char B0_Coel; -+ unsigned char B1_Coeh; -+ unsigned char B1_Coel; -+ unsigned char B2_Coeh; -+ unsigned char B2_Coel; -+ Clock_setup0_t Clk_Set0; -+ Clock_setup1_t Clk_Set1; -+ unsigned char PWM_Confh; -+ unsigned char PWM_Confl; -+ Bias_Vreg0_t Bias_Vreg0; -+ unsigned char Bias_Vreg1; -+ Adc_Gen0_t Adc_Gen0; -+ Adc_Gen1_t Adc_Gen1; -+ Adc_CON0_t Adc_Con0; -+ Adc_CON1_t Adc_Con1; -+ unsigned char res0[5]; -+ NonOv_Delay_t Non_OV_Delay; -+ unsigned char res1; -+ unsigned char Duty_Cycle_max_sat; -+ unsigned char Duty_Cycle_min_sat; -+ unsigned char res2[6]; -+ Osc_Conf_t Osc_Conf; -+ Osc_Status_t Osc_Sta; -+} __attribute__((packed)) Dcdc_register_map; -+ -+/*Define a pointer to the platform dependent set function*/ -+typedef int (*IfxDcdcPlatformSetCallback_t)(int arg); -+/*Define a pointer to the platform dependent get function*/ -+typedef int (*IfxDcdcPlatformGetCallback_t)(void); -+/*Define a pointer to the platform dependent Enable/Disable function*/ -+typedef int (*IfxDcdcPlatformEnableDisableCallback_t)(void); -+/*CB type to set the Non-OV Delay*/ -+typedef int (*IfxDcdcPlatformSetCallbackType2_t)(unsigned int arg1, -+ unsigned int arg2); -+ -+/*Table which contains the pointers to the platform dependent callbacks -+* These callbacks would be used to access platform dependent DCDC converter -+* Registers, Each platform should provide these callbacks*/ -+typedef struct _Ifx_dcdc_platform_callbacks_table { -+ IfxDcdcPlatformSetCallback_t Ifx_dcdc_voltage_set_cb; -+ IfxDcdcPlatformGetCallback_t Ifx_dcdc_voltage_get_cb; -+ IfxDcdcPlatformSetCallback_t Ifx_dcdc_DutyCycleMax_set_cb; -+ IfxDcdcPlatformSetCallback_t Ifx_dcdc_PwmSwitchingFreq_set_cb; -+ IfxDcdcPlatformSetCallbackType2_t Ifx_dcdc_NonOvDelay_set_cb; -+ IfxDcdcPlatformEnableDisableCallback_t Ifx_dcdc_PfmModeEnable_cb; -+ IfxDcdcPlatformEnableDisableCallback_t Ifx_dcdc_PfmModeDisable_cb; -+} Ifx_dcdc_platform_callbacks_table; -+#endif -diff --git a/arch/mips/include/asm/ifx/ifx_dma_core.h b/arch/mips/include/asm/ifx/ifx_dma_core.h -new file mode 100644 -index 0000000..20c2d57 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_dma_core.h -@@ -0,0 +1,316 @@ -+/** -+** FILE NAME : ifx_dma_core.h -+** PROJECT : IFX UEIP -+** MODULES : Central DMA -+** DATE : 03 June 2009 -+** AUTHOR : Reddy Mallikarjuna -+** DESCRIPTION : IFX Cross-Platform Central DMA driver header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 03 June 2009 Reddy Mallikarjuna Initial release -+*******************************************************************************/ -+#ifndef _IFX_DMA_CORE_H_ -+#define _IFX_DMA_CORE_H_ -+ -+/*! -+ \defgroup IFX_DMA_CORE UEIP Project - Central DMA core driver -+ \brief UEIP Project - Central DMA core Module, supports IFX CPE platforms(Danube/ASE/ARx/VRx). -+ */ -+ -+/*! -+ \defgroup IFX_DMA_DRV_API External APIs -+ \ingroup IFX_DMA_CORE -+ \brief External APIs definitions for other modules. -+ */ -+ -+/*! -+ \defgroup IFX_DMA_DRV_STRUCTURE Driver Structures -+ \ingroup IFX_DMA_CORE -+ \brief Definitions/Structures of IFX dma core module. -+ */ -+ -+/*! -+ \file ifx_dma_core.h -+ \ingroup IFX_DMA_CORE -+ \brief Header file for IFX Central DMA core driver -+ */ -+ -+/** =============================*/ -+/* Includes */ -+/** =============================*/ -+#include <asm/ifx/ifx_types.h> -+ -+#define CONFIG_IFX_DMA_DESCRIPTOR_NUMBER 32 -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+/** Platform specific supported DMA channel & Devices */ -+#if defined(CONFIG_DANUBE) -+#define ENABLE_RX_DPLUS_PATH 0 -+/** Max num of ports */ -+#if !defined(ENABLE_RX_DPLUS_PATH) || !ENABLE_RX_DPLUS_PATH -+#define MAX_DMA_DEVICE_NUM 6 -+#else -+#define MAX_DMA_DEVICE_NUM 7 -+#endif -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 20 -+#elif defined(CONFIG_AMAZON_SE) -+/** Max num of ports */ -+#define MAX_DMA_DEVICE_NUM 3 -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 10 -+#elif defined(CONFIG_AR9) -+/** Max num of ports */ -+#define MAX_DMA_DEVICE_NUM 6 -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 20 -+#elif defined(CONFIG_VR9) -+/** Max num of ports */ -+#define MAX_DMA_DEVICE_NUM 7 -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 28 -+#elif defined(CONFIG_AR10) -+/** Max num of ports */ -+#define MAX_DMA_DEVICE_NUM 5 -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 24 -+#elif defined(CONFIG_HN1) -+/** Max num of ports */ -+#define MAX_DMA_DEVICE_NUM 6 -+/** Max num of dma channels */ -+#define MAX_DMA_CHANNEL_NUM 28 -+#else -+#error "Platform is not specified(ifx_dma_core.h)!!!\n" -+#endif -+ -+/** Config the Num of descriptors from Kernel configurations -+* or else if will take default number of descriptors per channel -+*/ -+//#ifdef CONFIG_IFX_EXTRA_CFG -+#define IFX_DMA_DESCRIPTOR_OFFSET CONFIG_IFX_DMA_DESCRIPTOR_NUMBER -+//#else -+//#define IFX_DMA_DESCRIPTOR_OFFSET 32 -+//#endif -+ -+/*! -+ \addtogroup IFX_DMA_DRV_STRUCTURE -+ */ -+/*@{*/ -+ -+/*! \enum dma_psuedeo_interrupts_t -+* \brief DMA pseudo interrupts. -+ These interrupts are generated by dma core driver to sync with client drivers to handle the data between the clinet and core driver. -+*/ -+typedef enum { -+ RCV_INT = 1, /*!< Receive psuedo interrupt */ -+ TX_BUF_FULL_INT = 2, /*!< Tx channel descriptors full interrupt */ -+ TRANSMIT_CPT_INT = 4, /*!< Tx channel descriptors available interrupt */ -+}dma_psuedeo_interrupts_t; -+ -+/*! \enum ifx_dma_channel_onOff_t -+ \brief dma channel is on/ off. -+*/ -+typedef enum { -+ IFX_DMA_CH_OFF = 0, /*!< DMA channel is OFF */ -+ IFX_DMA_CH_ON = 1, /*!< DMA channel is ON */ -+} ifx_dma_channel_onOff_t; -+ -+/*! \enum ifx_dma_class_t -+ \brief dma channel class value. -+*/ -+typedef enum { -+ IFX_DMA_CLASS_0 = 0, -+ IFX_DMA_CLASS_1, -+ IFX_DMA_CLASS_2, -+ IFX_DMA_CLASS_3, -+ IFX_DMA_CLASS_4, -+ IFX_DMA_CLASS_5, -+ IFX_DMA_CLASS_6, -+ IFX_DMA_CLASS_7, -+} ifx_dma_class_t; -+ -+/*! \enum ifx_dma_endian_t -+ \brief DMA endiannes type. -+*/ -+typedef enum { -+ IFX_DMA_ENDIAN_TYPE0 = 0, /*!< No byte Swapping */ -+ IFX_DMA_ENDIAN_TYPE1, /*!< Byte Swap(B0B1B2B3 => B1B0B3B2)*/ -+ IFX_DMA_ENDIAN_TYPE2, /*!< Word Swap (B0B1B2B3 => B2B3B0B1)*/ -+ IFX_DMA_ENDIAN_TYPE3, /*!< DWord Swap (B0B1B2B3 => B3B2B1B0) */ -+}ifx_dma_endian_t; -+ -+enum { -+ /** 2 DWORDS */ -+ IFX_DMA_BURSTL_2 = 1, -+ /** 4 DWORDS */ -+ IFX_DMA_BURSTL_4 = 2, -+ /** 8 DWORDS */ -+ IFX_DMA_BURSTL_8 = 3, -+}; -+ -+/*! \enum ifx_dma_burst_len_t -+ \brief DMA Burst length. -+*/ -+typedef enum { -+ DMA_BURSTL_2DW = 2, /*!< 2 DWORD DMA burst length */ -+ DMA_BURSTL_4DW = 4, /*!< 4 DWORD DMA burst length */ -+ DMA_BURSTL_8DW = 8, /*!< 8 DWORD DMA burst length (not supported all peripherals) */ -+}ifx_dma_burst_len_t; -+ -+/*! \typedef _dma_arbitration_info -+ \brief Parameter Structure to used to configure DMA arbitration -+ based on packet or burst also Descriptor read back enabled/disabled (Supported only VR9) -+ Used by reference dma_device_info -+*/ -+typedef struct dma_arbitration_info { -+ IFX_enDis_t packet_arbitration; /*!< enabled/disabled packet arbitration*/ -+ IFX_enDis_t multiple_burst_arbitration;/*!< Enabled/Disabled Multi burst arbitration */ -+ unsigned int multiple_burst_counter; /*!< Counter of the Multi burst arbitration(Num of bursts that served before the arbitration of another peri port)*/ -+ IFX_enDis_t desc_read_back; /*!< enabled/disabled Descriptor read back */ -+}_dma_arbitration_info; -+ -+/*! \typedef _dma_channel_info -+ \brief The parameter structure is used to configure the DMA channel info -+ when the peripheral driver need to register with DMA core device driver. -+*/ -+typedef struct dma_channel_info { -+ int rel_chan_no; /*!< Relative channel number(if more than one DMA channel for device) */ -+ int dir; /*!< Direction of channel */ -+ int irq; /*!< DMA channel IRQ number */ -+ unsigned int desc_base; /*!< Channel descriptor base address*/ -+ int desc_len; /*!< Num of descriptors per channel */ -+ int curr_desc; /*!< Current Descriptor number*/ -+ int prev_desc; /*!< Previous Descriptor number */ -+ int byte_offset; /*!< Byte offset */ -+ int desc_handle; /*!< Descriptor handled flag ( to handle Rx Descriptor by client driver)*/ -+ int weight; /*!< WFQ present weight value for DMA channel */ -+ int default_weight; /*!< WFQ default weight value to handle in driver for DMA channel */ -+ int tx_channel_weight; /*!< Config the Tx DMA channel weight value */ -+ ifx_dma_class_t class_value; /*!< Config the DMA class value */ -+ int packet_size; /*!< Size of the packet length */ -+ int channel_packet_drop_enable; /*!< Config channel based packet drop(supported only VR9)*/ -+ int channel_packet_drop_counter;/*!< Channel based packet drop counter */ -+ int peri_to_peri; /*!< Config Peripheral to Peripheral(not supported Danube) */ -+ int global_buffer_len; /*!< Config global buffer length, valid only when enabled peri_to_peri) */ -+ int loopback_enable; /*!< Config Loop back between the DMA channels (Supported only VRx)*/ -+ int loopback_channel_number; /*!< Config the loopback Channel number (supported only VRx) */ -+ int req_irq_to_free; /*!< Release the DMA channel IRQ, which was already requested */ -+ int dur; /*!< Flag for Descriptor underrun interrupt */ -+ spinlock_t irq_lock; /*!< spin lock */ -+ ifx_dma_channel_onOff_t control; /*!< Channel on/off flag */ -+ void* opt[IFX_DMA_DESCRIPTOR_OFFSET]; /*!< Optional info*/ -+ void* dma_dev; /*!< Pointing to the devices */ -+ void (*open)(struct dma_channel_info* pCh); /*!< DMA channel ON */ -+ void (*close)(struct dma_channel_info* pCh);/*!< DMA channel OFF */ -+ void (*reset)(struct dma_channel_info* pCh);/*!< Reset DMA channel */ -+ void (*enable_irq)(struct dma_channel_info* pCh);/*!< Enable DMA channel interrupt */ -+ void (*disable_irq)(struct dma_channel_info* pCh);/*!< Disable DMA channel interrupt */ -+} _dma_channel_info; -+ -+/*! \typedef _dma_device_info -+ \brief The parameter structure is used to configure the DMA Peripheral ports info -+ when the peripheral driver need to register with DMA core device driver. -+*/ -+typedef struct dma_device_info { -+ char device_name[16]; /*!< Peripheral Device name */ -+ int port_reserved; /*!< Reserve the device by client driver */ -+ int port_num; /*!< Port number */ -+ ifx_dma_burst_len_t tx_burst_len; /*!< Configure the Tx burst length */ -+ ifx_dma_burst_len_t rx_burst_len; /*!< Conigure the Rx burst length */ -+ int port_tx_weight; /*!< Configure the Port based weight value */ -+ int port_packet_drop_enable; /*!< Packet drop Enabled/Disabled*/ -+ int port_packet_drop_counter; /*!< Packet drop counter */ -+ int mem_port_control; /*!< Configure the mem port control, only used Memory Ports */ -+ ifx_dma_endian_t tx_endianness_mode; /*!< Configure the Endiannes in Tx direction */ -+ ifx_dma_endian_t rx_endianness_mode; /*!< Configure the Endiannes in Rx direction */ -+ int current_tx_chan; /*!< Current Tx channel of the device*/ -+ int current_rx_chan; /*!< Current Rx channel of the device */ -+ int num_tx_chan; /*!< Config the num of Tx channels for device */ -+ int num_rx_chan; /*!< Config the num of Rx channels for device */ -+ int max_rx_chan_num; /*!< Max number of Rx channels supported */ -+ int max_tx_chan_num; /*!< Max number of Tx channels supported */ -+ spinlock_t irq_lock; /*!< spin lock */ -+ _dma_arbitration_info arbitration_info; /*!< Structure of the arbitration config*/ -+ _dma_channel_info* tx_chan[MAX_DMA_CHANNEL_NUM]; /*!< Max number of Channesl */ -+ _dma_channel_info* rx_chan[MAX_DMA_CHANNEL_NUM]; /*!< Max number of Channesl */ -+ u8* (*buffer_alloc)(int len, int* offset, void** opt); /*!< Buffer allocation */ -+ int (*buffer_free)(u8* dataptr, void* opt); /*!< Buffer free */ -+ int (*intr_handler)(struct dma_device_info* info, int status); /*!< DMA pseudo interrupt handler */ -+ void (*activate_poll)(struct dma_device_info* dma_dev); /*!< activate the polling (Used when NAPI enables)*/ -+ void (*inactivate_poll)(struct dma_device_info* dma_dev); /*!< Deactivate the polling (used when NAPI enabled) */ -+ void * priv; /*!< Pointer to the device private structure */ -+}_dma_device_info; -+ -+/* @} */ -+ -+/** Reserve the dma device port -+* This function should call before the dma_device_register */ -+extern _dma_device_info* dma_device_reserve(char* dev_name); -+ -+/** Unreseve the dma device port -+* This function will called after the dma_device_unregister */ -+extern int dma_device_release(_dma_device_info* dev); -+ -+/** Register with DMA device driver. -+This function should call after dma_device_reserve function. -+* This function register with dma device driver to handle dma functionality. -+* Should provide the required configuration info during the register with dma device. -+* if not provide config info, then take default values. */ -+extern int dma_device_register(_dma_device_info* info); -+ -+/** Unregister with DMA core driver -+* This function unregister with dma core driver. Once it unregister there is no -+* DMA handling with client driver.*/ -+extern int dma_device_unregister(_dma_device_info* info); -+ -+/** Read data packet from DMA Rx channel. -+* This function gets the data from the current rx descriptor of the DMA channel and send -+* to the client driver. -+* This functions is called when the client driver gets a pseudo DMA interrupt(RCV_INT). -+* Handle with care when call this function as well as dma_device_desc_setup function.*/ -+extern int dma_device_read(struct dma_device_info* info, u8** dataptr, void** opt); -+ -+/** Write data Packet to DMA Tx channel. -+* This function gets the data packet from the client driver and send over on DMA channel.*/ -+extern int dma_device_write(struct dma_device_info* info, u8* dataptr, int len, void* opt); -+ -+/** Setup the DMA channel descriptor. -+* This function setup the descriptor of the DMA channel used by client driver. -+* The client driver will take care the buffer allocation and do proper checking of -+* buffer for DMA burst alignment. -+* Handle with care when call this function as well as dma_device_read function */ -+extern int dma_device_desc_setup(_dma_device_info *dma_dev, char *buf, size_t len); -+ -+/** Clear the interrupt status flag -+* This function used to exit from DMA tasklet(tasklet don't need to run again and again ) -+* This is also used to avoid multiple psuedo interrupt (RCV_INT) per packet.*/ -+extern int dma_device_clear_int(_dma_device_info *dma_dev, int dir); -+ -+/**Clear the descriptor status word from the client driver once receive -+ a pseudo interrupt(RCV_INT) from the DMA module to avoid duplicate interrupts from tasklet. -+*/ -+extern int dma_device_clear_desc_status_word(_dma_device_info *dma_dev, int dir); -+ -+/** Poll the DMA device channel descriptors -+* This function polls the interrupts status in polling mode. */ -+extern int dma_device_poll(struct dma_device_info* info, int work_to_do, int *work_done); -+ -+/** setup the dma channel class value -+* This function setup the class of service value for DMA channel.*/ -+extern void dma_device_setup_class_val(_dma_channel_info* pCh, int cls); -+ -+/** poll DMA ownership bit to ensure that rx transactions are complete -+* to prevent descriptor errors */ -+extern void poll_dma_ownership_bit(_dma_device_info *dma_dev); -+#endif /* _IFX_DMA_CORE_H_ */ -diff --git a/arch/mips/include/asm/ifx/ifx_ebu_led.h b/arch/mips/include/asm/ifx/ifx_ebu_led.h -new file mode 100644 -index 0000000..c14b621 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_ebu_led.h -@@ -0,0 +1,76 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ebu_led.h -+** PROJECT : UEIP -+** MODULES : EBU to Control LEDs -+** -+** DATE : 16 Jul 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global EBU LED Controller driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 16 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_EBU_LED_H -+#define IFX_EBU_LED_H -+ -+ -+ -+/*! -+ \defgroup IFX_LEDEBU UEIP Project - LED EBU sub-driver module -+ \brief UEIP Project - LED EBU sub-driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_LEDEBU_API APIs -+ \ingroup IFX_LEDEBU -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \file ifx_ebu_led.h -+ \ingroup IFX_LEDEBU -+ \brief LED EBU sub-driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ #ifdef CONFIG_IFX_EBU_LED -+ int ifx_ebu_led_set_data(unsigned int led, unsigned int data); -+ void ifx_ebu_led_enable(void); -+ void ifx_ebu_led_disable(void); -+ #else -+ #define ifx_ebu_led_set_data(led, data) -+ #define ifx_ebu_led_enable() -+ #define ifx_ebu_led_disable() -+ #endif -+#endif -+ -+ -+ -+#endif // IFX_EBU_LED_H -diff --git a/arch/mips/include/asm/ifx/ifx_eth_framework.h b/arch/mips/include/asm/ifx/ifx_eth_framework.h -new file mode 100644 -index 0000000..b55d735 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_eth_framework.h -@@ -0,0 +1,90 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_eth_framework.h -+** PROJECT : UEIP -+** MODULES : ETH -+** -+** DATE : 2 Nov 2010 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global ETH driver framework header file -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 02 NOV 2010 Xu Liang Init Version -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_ETH_FRAMEWORK_H -+#define IFX_ETH_FRAMEWORK_H -+ -+ -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+ -+typedef enum { -+ IFX_ETH_FW_POLL_COMPLETE = 0, -+ IFX_ETH_FW_POLL_CONTINUE = 1, -+} ifx_eth_fw_poll_ret_t; -+ -+struct ifx_eth_fw_netdev_ops { -+ // routines usually implemented by IFX ETH/PPE drivers -+ // not all routines defined in net_device/net_device_ops are covered -+ int (*init)(struct net_device *dev); -+ void (*uninit)(struct net_device *dev); -+ -+ int (*open)(struct net_device *dev); -+ int (*stop)(struct net_device *dev); -+ -+ int (*start_xmit)(struct sk_buff *skb, struct net_device *dev); -+ -+ void (*set_multicast_list)(struct net_device *dev); -+ int (*set_mac_address)(struct net_device *dev, void *addr); -+ int (*do_ioctl)(struct net_device *dev, struct ifreq *ifr, int cmd); -+ int (*set_config)(struct net_device *dev, struct ifmap *map); -+ int (*change_mtu)(struct net_device *dev, int new_mtu); -+ int (*neigh_setup)(struct net_device *dev, struct neigh_parms *); -+ -+ struct net_device_stats* -+ (*get_stats)(struct net_device *dev); -+ -+#ifdef CONFIG_NET_POLL_CONTROLLER -+ void (*poll_controller)(struct net_device *dev); -+#endif -+ ifx_eth_fw_poll_ret_t -+ (*poll)(struct net_device *dev, int work_to_do, int *work_done); -+ int weight; -+ -+ void (*tx_timeout)(struct net_device *dev); -+ int watchdog_timeo; -+}; -+ -+ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+ -+extern void *ifx_eth_fw_netdev_priv(struct net_device *dev); -+extern struct net_device *ifx_eth_fw_alloc_netdev(int sizeof_priv, const char *name, struct ifx_eth_fw_netdev_ops *ops); -+extern void ifx_eth_fw_free_netdev(struct net_device *dev, int force); -+extern int ifx_eth_fw_register_netdev(struct net_device *dev); -+void ifx_eth_fw_unregister_netdev(struct net_device *dev, int force); -+extern int ifx_eth_fw_poll_schedule(struct net_device *dev); -+extern int ifx_eth_fw_poll_complete(struct net_device *dev); -+ -+ -+ -+#endif // IFX_ETH_FRAMEWORK_H -diff --git a/arch/mips/include/asm/ifx/ifx_gpio.h b/arch/mips/include/asm/ifx/ifx_gpio.h -new file mode 100644 -index 0000000..429029e ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_gpio.h -@@ -0,0 +1,428 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_gpio.h -+** PROJECT : UEIP -+** MODULES : GPIO -+** -+** DATE : 3 Jul 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global GPIO driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 03 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_GPIO_H -+#define IFX_GPIO_H -+ -+ -+ -+/*! -+ \defgroup IFX_GPIO UEIP Project - GPIO driver module -+ \brief UEIP Project - GPIO driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_GPIO_API APIs -+ \ingroup IFX_GPIO -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_GPIO_IOCTL IOCTL Commands -+ \ingroup IFX_GPIO -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_GPIO_STRUCT Structures -+ \ingroup IFX_GPIO -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_gpio.h -+ \ingroup IFX_GPIO -+ \brief GPIO driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+#define IFX_GPIO_PIN_NUMBER_PER_PORT 16 -+#define IFX_GPIO_PIN_ID(port, pin) ((port) * IFX_GPIO_PIN_NUMBER_PER_PORT + (pin)) -+#define IFX_GPIO_PIN_ID_TO_PORT(pin_id) (pin_id >> 4) -+#define IFX_GPIO_PIN_ID_TO_PIN(pin_id) (pin_id & 0x0F) -+ -+enum { -+ IFX_GPIO_PIN_AVAILABLE = 0, -+ IFX_GPIO_MODULE_MIN = IFX_GPIO_PIN_AVAILABLE, -+ // following are module_id used by component while registering -+ IFX_GPIO_MODULE_TEST, -+ IFX_GPIO_MODULE_MEI, -+ IFX_GPIO_MODULE_DSL_NTR, -+ IFX_GPIO_MODULE_SSC, -+ IFX_GPIO_MODULE_ASC0, -+ IFX_GPIO_MODULE_SDIO, -+ IFX_GPIO_MODULE_LEDC, -+ IFX_GPIO_MODULE_USB, -+ IFX_GPIO_MODULE_INTERNAL_SWITCH, -+ IFX_GPIO_MODULE_PCI, -+ IFX_GPIO_MODULE_PCIE, -+ IFX_GPIO_MODULE_NAND, -+ IFX_GPIO_MODULE_PPA, -+ IFX_GPIO_MODULE_TAPI_VMMC, -+ IFX_GPIO_MODULE_TAPI_DEMO, -+ IFX_GPIO_MODULE_TAPI_FXO, -+ IFX_GPIO_MODULE_TAPI_DXT, -+ IFX_GPIO_MODULE_TAPI_VCPE, -+ IFX_GPIO_MODULE_VINAX, -+ IFX_GPIO_MODULE_USIF_UART, -+ IFX_GPIO_MODULE_USIF_SPI, -+ IFX_GPIO_MODULE_SPI_FLASH, -+ IFX_GPIO_MODULE_SPI_EEPROM, -+ IFX_GPIO_MODULE_USIF_SPI_SFLASH, -+ IFX_GPIO_MODULE_LED, -+ IFX_GPIO_MODULE_EBU_LED, -+ IFX_GPIO_MODULE_EXIN, // external interrupt detection unit -+ IFX_GPIO_MODULE_PAGE, // page button gpio -+ IFX_GPIO_MODULE_DECT, // DECT -+ IFX_GPIO_MODULE_SI, -+ IFX_GPIO_MODULE_SWRESET,// sw reset button -+ // add more component in the future -+ IFX_GPIO_MODULE_MAX, -+ // flag to init module during system bootup no matter whether this module is loaded or not -+ IFX_GPIO_MODULE_EARLY_REGISTER = 0x08000000, // this bit flag trigger pin init during system bootup -+}; -+ -+#define IFX_GPIO_DECLARE_MODULE_NAME(var) \ -+ char *var[] = { \ -+ "Available", \ -+ "TEST", \ -+ "MEI", \ -+ "DSL-NTR", \ -+ "SSC", \ -+ "ASC0", \ -+ "SDIO", \ -+ "LEDC", \ -+ "USB", \ -+ "INT_SW", \ -+ "PCI", \ -+ "PCIE", \ -+ "NAND", \ -+ "PPA", \ -+ "TAPI-VMMC", \ -+ "TAPI-DEMO", \ -+ "TAPI-FXO", \ -+ "TAPI-DXT", \ -+ "TAPI-VCPE", \ -+ "VINAX", \ -+ "USIF-UART", \ -+ "USIF-SPI", \ -+ "SFLASH", \ -+ "EEPROM", \ -+ "USIF-SFLASH", \ -+ "LED", \ -+ "EBU_LED", \ -+ "EXIN", \ -+ "PAGE_BUTTON", \ -+ "DECT", \ -+ "SERIAL_IN", \ -+ "SWRESET", \ -+ } -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_GPIO_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_gpio_ioctl_parm -+ \brief Structure used for single pin configuration. -+ -+ User application use this structure to call single pin configuration IOCTL commands: -+ IFX_GPIO_IOC_OD, IFX_GPIO_IOC_PUDSEL, IFX_GPIO_IOC_PUDEN, IFX_GPIO_IOC_STOFF, -+ IFX_GPIO_IOC_DIR, IFX_GPIO_IOC_OUTPUT, IFX_GPIO_IOC_INPUT, IFX_GPIO_IOC_ALTSEL0, -+ IFX_GPIO_IOC_ALTSEL1. "port", "pin" and "module" are input. Driver takes input -+ "port" and "pin" to identify which pin to configure. "module" is module ID so that -+ driver can do sanity check to avoid improper pin usage (e.g. two module share one pin). -+ "value" could be either input or output. -+ */ -+struct ifx_gpio_ioctl_parm { -+ int port; /*!< input, GPIO port number 0 ~ 3 */ -+ int pin; /*!< input, GPIO pin number 0 ~ 15 */ -+ int value; /*!< input/output, value to be set (or get) */ -+ int module; /*!< input, module id of this operation */ -+}; -+ -+/*! -+ \struct ifx_gpio_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_gpio_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+ -+/*! -+ \struct ifx_gpio_ioctl_pin_reserve -+ \brief Structure used to reserve pin. -+ */ -+struct ifx_gpio_ioctl_pin_reserve { -+ int pin; /*!< input, pin ID */ -+ int module_id; /*!< input, module ID */ -+}; -+ -+/*! -+ \struct ifx_gpio_ioctl_pin_config -+ \brief Structure used for single pin configuration (IFX_GPIO_IOC_PIN_CONFIG). -+ -+ User application use this structure to call pin configuration IOCTL command - IFX_GPIO_IOC_PIN_CONFIG. -+ */ -+struct ifx_gpio_ioctl_pin_config { -+ int module_id; /*!< input, module ID */ -+ int pin; /*!< input, pin ID */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_OD_SET (1 << 0) /*!< config flag, enable Open Drain */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_OD_CLEAR (1 << 1) /*!< config flag, disable Open Drain */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_SET (1 << 2) /*!< config flag, set Pull-Up */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDSEL_CLEAR (1 << 3) /*!< config flag, set Pull-Down */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_SET (1 << 4) /*!< config flag, enable Pull-Up/Down */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_PUDEN_CLEAR (1 << 5) /*!< config flag, disable Pull-Up/Down */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_STOFF_SET (1 << 6) /*!< config flag, enable Schmitt Trigger */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_STOFF_CLEAR (1 << 7) /*!< config flag, disable Schmitt Trigger */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_DIR_OUT (1 << 8) /*!< config flag, configure GPIO pin as output */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_DIR_IN (1 << 9) /*!< config flag, configure GPIO pin as input */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_OUTPUT_SET (1 << 10) /*!< config flag, output 1 */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_OUTPUT_CLEAR (1 << 11) /*!< config flag, output 0 */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_SET (1 << 12) /*!< config flag, set Alternative Select 0 with value 1 */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL0_CLEAR (1 << 13) /*!< config flag, set Alternative Select 0 with value 0 */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_SET (1 << 14) /*!< config flag, set Alternative Select 1 with value 1 */ -+#define IFX_GPIO_IOCTL_PIN_CONFIG_ALTSEL1_CLEAR (1 << 15) /*!< config flag, set Alternative Select 1 with value 0 */ -+ unsigned int config; /*!< input, config flags */ -+}; -+ -+/*! -+ \struct ifx_gpio_ioctl_module_query -+ \brief Structure used for query of port. -+ -+ User application use this structure to call IOCTL command - IFX_GPIO_IOC_MODULE_QUERY. -+ Driver will check the GPIO port and return all pins' status of this port. -+ */ -+struct ifx_gpio_ioctl_module_query { -+ int module_id; /*!< input, ID of port (0 ~ 3) */ -+ unsigned int pin_num; /*!< input, number of pins in this port */ -+ unsigned int pin[IFX_GPIO_PIN_NUMBER_PER_PORT]; /*!< input, status of each pin (module using this pin) */ -+}; -+ -+/*! -+ \struct ifx_gpio_ioctl_pin_query -+ \brief Structure used for query of pin. -+ -+ User application use this structure to call IOCTL command - IFX_GPIO_IOC_PIN_CONFIG. -+ Driver will check the module ID using this pin. If this pin is configured as input, -+ the input value will be stored in member "input". -+ */ -+struct ifx_gpio_ioctl_pin_query { -+ int pin; /*!< input, pin ID to query */ -+ int module_id; /*!< output, module ID using this pin, ZERO if the pin is not reserved */ -+ int input; /*!< output, input value if this pin is configured as input */ -+}; -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_GPIO_IOCTL -+ */ -+/*@{*/ -+#define IFX_GPIO_IOC_MAGIC 0xbf -+// backward compatible -+/*! -+ \def IFX_GPIO_IOC_OD -+ \brief GPIO IOCTL Command - Configure Open Drain for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Open Drain for given pin. -+ */ -+#define IFX_GPIO_IOC_OD _IOW( IFX_GPIO_IOC_MAGIC, 0, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_PUDSEL -+ \brief GPIO IOCTL Command - Configure Pull-Up/Down resistor for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Pull-Up/Down resistor for given pin. -+ */ -+#define IFX_GPIO_IOC_PUDSEL _IOW( IFX_GPIO_IOC_MAGIC, 1, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_PUDEN -+ \brief GPIO IOCTL Command - Enable/Disable Pull-Up/Down feature for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to enable/disable Pull-Up/Down feature for given pin. -+ */ -+#define IFX_GPIO_IOC_PUDEN _IOW( IFX_GPIO_IOC_MAGIC, 2, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_STOFF -+ \brief GPIO IOCTL Command - Enable/Disable Pull-Up/Down feature for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to enable/disable Pull-Up/Down feature for given pin. -+ */ -+#define IFX_GPIO_IOC_STOFF _IOW( IFX_GPIO_IOC_MAGIC, 3, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_DIR -+ \brief GPIO IOCTL Command - Configure given pin to be input or output. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure given pin to be input or output. -+ */ -+#define IFX_GPIO_IOC_DIR _IOW( IFX_GPIO_IOC_MAGIC, 4, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_OUTPUT -+ \brief GPIO IOCTL Command - Configure given pin to output 0 or 1. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure given pin to output 0 or 1. -+ */ -+#define IFX_GPIO_IOC_OUTPUT _IOW( IFX_GPIO_IOC_MAGIC, 5, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_INPUT -+ \brief GPIO IOCTL Command - Collect input from given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to collect input from given pin. -+ */ -+#define IFX_GPIO_IOC_INPUT _IOWR(IFX_GPIO_IOC_MAGIC, 6, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_ALTSEL0 -+ \brief GPIO IOCTL Command - Configure Alternative Select 0 for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Alternative Select 0 for given pin. -+ */ -+#define IFX_GPIO_IOC_ALTSEL0 _IOW( IFX_GPIO_IOC_MAGIC, 7, struct ifx_gpio_ioctl_parm) -+/*! -+ \def IFX_GPIO_IOC_ALTSEL1 -+ \brief GPIO IOCTL Command - Configure Alternative Select 1 for given pin. -+ -+ This command uses structure "ifx_gpio_ioctl_parm" as parameter to configure Alternative Select 1 for given pin. -+ */ -+#define IFX_GPIO_IOC_ALTSEL1 _IOW( IFX_GPIO_IOC_MAGIC, 8, struct ifx_gpio_ioctl_parm) -+// UEIP IOCTL commands -+/*! -+ \def IFX_GPIO_IOC_VERSION -+ \brief GPIO IOCTL Command - Get version number of driver. -+ -+ This command uses structure "ifx_gpio_ioctl_version" as parameter to get version number of driver. -+ */ -+#define IFX_GPIO_IOC_VERSION _IOR( IFX_GPIO_IOC_MAGIC, 10, struct ifx_gpio_ioctl_version) -+/*! -+ \def IFX_GPIO_IOC_REGISTER -+ \brief GPIO IOCTL Command - Register module. -+ -+ This command uses "arg" as parameter (module_id) to register module. -+ */ -+#define IFX_GPIO_IOC_REGISTER _IO( IFX_GPIO_IOC_MAGIC, 11) -+/*! -+ \def IFX_GPIO_IOC_DEREGISTER -+ \brief GPIO IOCTL Command - Deregister module. -+ -+ This command uses "arg" as parameter (module_id) to deregister module. -+ */ -+#define IFX_GPIO_IOC_DEREGISTER _IO( IFX_GPIO_IOC_MAGIC, 12) -+/*! -+ \def IFX_GPIO_IOC_PIN_RESERVE -+ \brief GPIO IOCTL Command - Reserve pin. -+ -+ This command uses struct "ifx_gpio_ioctl_pin_reserve" as parameter to reserve pin. -+ */ -+#define IFX_GPIO_IOC_PIN_RESERVE _IOW( IFX_GPIO_IOC_MAGIC, 13, struct ifx_gpio_ioctl_pin_reserve) -+/*! -+ \def IFX_GPIO_IOC_PIN_FREE -+ \brief GPIO IOCTL Command - Free pin. -+ -+ This command uses struct "ifx_gpio_ioctl_pin_reserve" as parameter to free pin. -+ */ -+#define IFX_GPIO_IOC_PIN_FREE _IOW( IFX_GPIO_IOC_MAGIC, 14, struct ifx_gpio_ioctl_pin_reserve) -+/*! -+ \def IFX_GPIO_IOC_PIN_CONFIG -+ \brief GPIO IOCTL Command - Configure pin. -+ -+ This command uses struct "ifx_gpio_ioctl_pin_config" as parameter to configure pin. -+ */ -+#define IFX_GPIO_IOC_PIN_CONFIG _IOR( IFX_GPIO_IOC_MAGIC, 15, struct ifx_gpio_ioctl_pin_config) -+/*! -+ \def IFX_GPIO_IOC_MODULE_QUERY -+ \brief GPIO IOCTL Command - Get pin information of given module ID. -+ -+ This command uses struct "ifx_gpio_ioctl_module_query" as parameter to get pin information of given module ID. -+ */ -+#define IFX_GPIO_IOC_MODULE_QUERY _IOWR(IFX_GPIO_IOC_MAGIC, 16, struct ifx_gpio_ioctl_module_query) -+/*! -+ \def IFX_GPIO_IOC_PIN_QUERY -+ \brief GPIO IOCTL Command - Get pin information of given pin ID. -+ -+ This command uses struct "ifx_gpio_ioctl_module_query" as parameter to get pin information of given pin ID. -+ */ -+#define IFX_GPIO_IOC_PIN_QUERY _IOWR(IFX_GPIO_IOC_MAGIC, 17, struct ifx_gpio_ioctl_pin_query) -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ /* -+ * Module Level Functions -+ */ -+ int ifx_gpio_register(int module_id); -+ int ifx_gpio_deregister(int module_id); -+ /* -+ * Pin Operation Functions -+ */ -+ int ifx_gpio_output_set(int pin, int module_id); -+ int ifx_gpio_output_clear(int pin, int module_id); -+ int ifx_gpio_input_get(int pin, int module_id, int *input); -+ /* -+ * Pin Operation Functions (Backward Compatible) -+ */ -+ int ifx_gpio_pin_reserve(int pin, int module_id); -+ int ifx_gpio_pin_free(int pin, int module_id); -+ int ifx_gpio_open_drain_set(int pin, int module_id); -+ int ifx_gpio_open_drain_clear(int pin, int module_id); -+ int ifx_gpio_pudsel_set(int pin, int module_id); -+ int ifx_gpio_pudsel_clear(int pin, int module_id); -+ int ifx_gpio_puden_set(int pin, int module_id); -+ int ifx_gpio_puden_clear(int pin, int module_id); -+ int ifx_gpio_stoff_set(int pin, int module_id); -+ int ifx_gpio_stoff_clear(int pin, int module_id); -+ int ifx_gpio_dir_out_set(int pin, int module_id); -+ int ifx_gpio_dir_in_set(int pin, int module_id); -+ int ifx_gpio_altsel0_set(int pin, int module_id); -+ int ifx_gpio_altsel0_clear(int pin, int module_id); -+ int ifx_gpio_altsel1_set(int pin, int module_id); -+ int ifx_gpio_altsel1_clear(int pin, int module_id); -+#endif // __KERNEL__ -+ -+ -+ -+#endif // IFX_GPIO_H -diff --git a/arch/mips/include/asm/ifx/ifx_gptu.h b/arch/mips/include/asm/ifx/ifx_gptu.h -new file mode 100644 -index 0000000..1acb9da ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_gptu.h -@@ -0,0 +1,239 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_gptu.h -+** PROJECT : IFX UEIP -+** MODULES : GPTU -+** -+** DATE : 28 May 2009 -+** AUTHOR : Huang Xiaogang -+** DESCRIPTION : IFX General Purpose Timer Counter driver header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 28 May 2009 Huang Xiaogang The first UEIP release -+*******************************************************************************/ -+#ifndef IFX_GPTU_H -+#define IFX_GPTU_H -+ -+/*! -+ \defgroup IFX_GPTU UEIP Project - GPTU driver module -+ \brief UEIP Project - GPTU driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_GPTU_API APIs -+ \ingroup IFX_GPTU -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_GPTU_IOCTL IOCTL Commands -+ \ingroup IFX_GPTU -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_GPTU_STRUCT Structures -+ \ingroup IFX_GPTU -+ \brief Structures used by user application. -+ */ -+ -+/*! \file ifx_gptu.h -+ \ingroup IFX_GPTU -+ \brief This file contains the interface to GPTU driver. -+*/ -+ -+/* -+ * Available Timer/Counter Index -+ */ -+#define TIMER(n, X) (n * 2 + (X ? 1 : 0)) -+#define TIMER_ANY 0x00 -+#define TIMER1A TIMER(1, 0) -+#define TIMER1B TIMER(1, 1) -+#define TIMER2A TIMER(2, 0) -+#define TIMER2B TIMER(2, 1) -+#define TIMER3A TIMER(3, 0) -+#define TIMER3B TIMER(3, 1) -+ -+/* -+ * Flag of Timer/Counter -+ * These flags specify the way in which timer is configured. -+ */ -+/* Bit size of timer/counter. */ -+#define TIMER_FLAG_16BIT 0x0000 -+#define TIMER_FLAG_32BIT 0x0001 -+/* Switch between timer and counter. */ -+#define TIMER_FLAG_TIMER 0x0000 -+#define TIMER_FLAG_COUNTER 0x0002 -+/* Stop or continue when overflowing/underflowing. */ -+#define TIMER_FLAG_ONCE 0x0000 -+#define TIMER_FLAG_CYCLIC 0x0004 -+/* Count up or counter down. */ -+#define TIMER_FLAG_UP 0x0000 -+#define TIMER_FLAG_DOWN 0x0008 -+/* Count on specific level or edge. */ -+#define TIMER_FLAG_HIGH_LEVEL_SENSITIVE 0x0000 -+#define TIMER_FLAG_LOW_LEVEL_SENSITIVE 0x0040 -+#define TIMER_FLAG_RISE_EDGE 0x0010 -+#define TIMER_FLAG_FALL_EDGE 0x0020 -+#define TIMER_FLAG_ANY_EDGE 0x0030 -+/* Signal is syncronous to module clock or not. */ -+#define TIMER_FLAG_UNSYNC 0x0000 -+#define TIMER_FLAG_SYNC 0x0080 -+/* Different interrupt handle type. */ -+#define TIMER_FLAG_NO_HANDLE 0x0000 -+#if defined(__KERNEL__) -+ #define TIMER_FLAG_CALLBACK_IN_IRQ 0x0100 -+#endif // defined(__KERNEL__) -+#define TIMER_FLAG_SIGNAL 0x0300 -+/* Internal clock source or external clock source */ -+#define TIMER_FLAG_INT_SRC 0x0000 -+#define TIMER_FLAG_EXT_SRC 0x1000 -+ -+#define IFX_GPTU_VER_MAJOR 2 -+#define IFX_GPTU_VER_MID 0 -+#define IFX_GPTU_VER_MINOR 1 -+ -+/*! -+ \addtogroup IFX_GPTU_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_gptu_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_gptu_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+ -+/*! -+ \struct gptu_ioctl_param -+ \brief data type used to call ioctl -+ */ -+struct gptu_ioctl_param { -+ unsigned int timer; /*!< In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and -+ GPTU_SET_COUNTER, this field is ID of expected -+ timer/counter. If it's zero, a timer/counter would -+ be dynamically allocated and ID would be stored in -+ this field. -+ In command GPTU_GET_COUNT_VALUE, this field is -+ ignored. -+ In other command, this field is ID of timer/counter -+ allocated.*/ -+ unsigned int flag; /*!< In command GPTU_REQUEST_TIMER, GPTU_SET_TIMER, and -+ GPTU_SET_COUNTER, this field contains flags to -+ specify how to configure timer/counter. -+ In command GPTU_START_TIMER, zero indicate start -+ and non-zero indicate resume timer/counter. -+ In other command, this field is ignored.*/ -+ unsigned long value; /*!< In command GPTU_REQUEST_TIMER, this field contains -+ init/reload value. -+ In command GPTU_SET_TIMER, this field contains -+ frequency (0.001Hz) of timer. -+ In command GPTU_GET_COUNT_VALUE, current count -+ value would be stored in this field. -+ In command GPTU_CALCULATE_DIVIDER, this field -+ contains frequency wanted, and after calculation, -+ divider would be stored in this field to overwrite -+ the frequency.*/ -+ int pid; /*!< In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, -+ if signal is required, this field contains process -+ ID to which signal would be sent. -+ In other command, this field is ignored.*/ -+ int sig; /*!< In command GPTU_REQUEST_TIMER and GPTU_SET_TIMER, -+ if signal is required, this field contains signal -+ number which would be sent. -+ In other command, this field is ignored.*/ -+}; -+/*@}*/ -+ -+/*! -+ \addtogroup IFX_GPTU_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+#define IFX_GPTU_IOC_MAGIC 'g' -+ -+/*! -+ \def IFX_GPTU_REQUEST_TIMER -+ \brief General method to setup timer/counter. -+ */ -+#define IFX_GPTU_REQUEST_TIMER _IOWR(IFX_GPTU_IOC_MAGIC, 1, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_FREE_TIMER -+ \brief Free timer/counter -+ */ -+#define IFX_GPTU_FREE_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 2, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_START_TIMER -+ \brief Start or resume timer/counter -+ */ -+#define IFX_GPTU_START_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 3, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_STOP_TIMER -+ \brief Suspend timer/counter -+ */ -+#define IFX_GPTU_STOP_TIMER _IOW(IFX_GPTU_IOC_MAGIC, 4, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_GET_COUNT_VALUE -+ \brief Get current count value -+ */ -+#define IFX_GPTU_GET_COUNT_VALUE _IOWR(IFX_GPTU_IOC_MAGIC, 5, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_CALCULATE_DIVIDER -+ \brief Calculate timer divider from given freq -+ */ -+#define IFX_GPTU_CALCULATE_DIVIDER _IOWR(IFX_GPTU_IOC_MAGIC, 6, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_SET_TIMER -+ \brief Simplified method to setup timer -+ */ -+#define IFX_GPTU_SET_TIMER _IOWR(IFX_GPTU_IOC_MAGIC, 7, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_SET_COUNTER -+ \brief Simplified method to setup counter -+ */ -+#define IFX_GPTU_SET_COUNTER _IOWR(IFX_GPTU_IOC_MAGIC, 8, struct gptu_ioctl_param) -+ -+/*! -+ \def IFX_GPTU_VERSION -+ \brief Get GPTU driver version number -+ */ -+#define IFX_GPTU_VERSION _IOR(IFX_GPTU_IOC_MAGIC, 9, struct ifx_gptu_ioctl_version) -+/*@}*/ -+ -+typedef void (*timer_callback)(unsigned long arg); -+ -+extern int ifx_gptu_timer_request(unsigned int, unsigned int, unsigned long, unsigned long, unsigned long); -+extern int ifx_gptu_timer_free(unsigned int); -+extern int ifx_gptu_timer_start(unsigned int, int); -+extern int ifx_gptu_timer_stop(unsigned int); -+extern int ifx_gptu_counter_flags_reset(u32 timer, u32 flags); -+extern int ifx_gptu_countvalue_get(unsigned int, unsigned long *); -+extern u32 ifx_gptu_divider_cal(unsigned long); -+extern int ifx_gptu_timer_set(unsigned int, unsigned int, int, int, unsigned int, unsigned long, unsigned long); -+extern int ifx_gptu_counter_set(unsigned int timer, unsigned int flag, -+ u32 reload, unsigned long arg1, unsigned long arg2); -+ -+#endif /* IFX_GPTU_H */ -diff --git a/arch/mips/include/asm/ifx/ifx_led.h b/arch/mips/include/asm/ifx/ifx_led.h -new file mode 100644 -index 0000000..2d1e956 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_led.h -@@ -0,0 +1,331 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_led.h -+** PROJECT : UEIP -+** MODULES : LED Driver -+** -+** DATE : 16 Jul 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global LED driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 16 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_LED_H -+#define IFX_LED_H -+ -+ -+ -+/*! -+ \defgroup IFX_LED UEIP Project - LED driver module -+ \brief UEIP Project - LED driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_LED_API APIs -+ \ingroup IFX_LED -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_LED_IOCTL IOCTL Commands -+ \ingroup IFX_LED -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_LED_STRUCT Structures -+ \ingroup IFX_LED -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_led.h -+ \ingroup IFX_LED -+ \brief LED driver header file -+ */ -+ -+ -+ -+#include <linux/leds.h> -+#include "asm/ifx/ifx_types.h" -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * LED Events -+ */ -+#define IFX_LED_TRIGGER_POWER_ON "power_on" -+#define IFX_LED_TRIGGER_WARNING "warning" -+#define IFX_LED_TRIGGER_DSL_LINK "dsl_link" -+#define IFX_LED_TRIGGER_DSL_DATA "dsl_data" -+#define IFX_LED_TRIGGER_USB_LINK "usb_link" -+#define IFX_LED_TRIGGER_WAN_STATUS "wan_status" -+#define IFX_LED_TRIGGER_EPHY_LINK "ephy_link" -+#define IFX_LED_TRIGGER_EPHY_SPEED "ephy_speed" -+#define IFX_LED_TRIGGER_FXS1_LINK "fxs1_link" -+#define IFX_LED_TRIGGER_FXS2_LINK "fxs2_link" -+#define IFX_LED_TRIGGER_FXO_ACT "fxo_act" -+#define IFX_LED_TRIGGER_WLAN_READY1 "wlan_ready1" -+#define IFX_LED_TRIGGER_WLAN_READY2 "wlan_ready2" -+#define IFX_LED_TRIGGER_SD_LINK "sd_link" -+ -+/* -+ * Macros for dual color LED -+ */ -+#define IFX_LED_DUAL_MAKE_PHYS_ID(phys_id_led1, phys_id_led2) (((phys_id_led2) << 16) | (phys_id_led1)) -+#define IFX_LED_DUAL_GET_PHYS_ID_LED1(phys_id) ((phys_id) & 0xffff) -+#define IFX_LED_DUAL_GET_PHYS_ID_LED2(phys_id) (((phys_id) >> 16) & 0xffff) -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_LED_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * LED Device Definition -+ */ -+/*! -+ \struct ifx_led_device -+ \brief Structure used for LED device. -+ */ -+struct ifx_led_device { -+ struct led_classdev device; /*!< LED device */ -+ char name[32]; /*!< LED device name */ -+ -+ char *default_trigger; /*!< default event/trigger of LED device */ -+ unsigned int phys_id; /*!< physical ID of LED device, driver use this ID to communicate with physical LED driver */ -+ unsigned int value_on; /*!< value to turn on LED */ -+ unsigned int value_off; /*!< value to turn off LED */ -+ unsigned int color; /*!< color of the LED */ -+/*! -+ \def IFX_LED_DEVICE_FLAG_PHYS_GPIO -+ \brief field "flags" of struct "ifx_led_device" - LED drived by GPIO. -+ */ -+#define IFX_LED_DEVICE_FLAG_PHYS_GPIO 0 -+/*! -+ \def IFX_LED_DEVICE_FLAG_PHYS_LEDC -+ \brief field "flags" of struct "ifx_led_device" - LED drived by LED Controller (Serial Out). -+ */ -+#define IFX_LED_DEVICE_FLAG_PHYS_LEDC 1 -+/*! -+ \def IFX_LED_DEVICE_FLAG_PHYS_EBU -+ \brief field "flags" of struct "ifx_led_device" - LED drived by EBU. -+ */ -+#define IFX_LED_DEVICE_FLAG_PHYS_EBU 2 -+#define IFX_LED_DEVICE_FLAG_PHYS_MASK 3 -+#define IFX_LED_DEVICE_FLAG_DUAL_LED (1 << 29) -+#define IFX_LED_DEVICE_FLAG_CREATED (1 << 30) -+/*! -+ \def IFX_LED_DEVICE_FLAG_INVALID -+ \brief field "flags" of struct "ifx_led_device" - LED is not in use. -+ */ -+#define IFX_LED_DEVICE_FLAG_INVALID (1 << 31) -+ unsigned int flags; /*!< additional flags */ -+}; -+ -+/* -+ * LED Trigger Atrribute -+ */ -+/*! -+ \struct ifx_led_trigger_attrib -+ \brief Structure used for LED default behavior (attibutes). -+ */ -+struct ifx_led_trigger_attrib { -+ unsigned int delay_on; /*!< delay of LED on (in millisecond) */ -+ unsigned int delay_off; /*!< delay of LED off (in millisecond) */ -+ unsigned int timeout; /*!< stop blinking/on after timeout (in millisecond) */ -+ unsigned int def_value; /*!< default state of LED (on/off) */ -+/*! -+ \def IFX_LED_TRIGGER_ATTRIB_DELAY_ON -+ \brief field "flags" of struct "ifx_led_trigger_attrib" - delay_on is valid. -+ */ -+#define IFX_LED_TRIGGER_ATTRIB_DELAY_ON (1 << 0) -+/*! -+ \def IFX_LED_TRIGGER_ATTRIB_DELAY_OFF -+ \brief field "flags" of struct "ifx_led_trigger_attrib" - delay_off is valid. -+ */ -+#define IFX_LED_TRIGGER_ATTRIB_DELAY_OFF (1 << 1) -+/*! -+ \def IFX_LED_TRIGGER_ATTRIB_TIMEOUT -+ \brief field "flags" of struct "ifx_led_trigger_attrib" - timeout is valid. -+ */ -+#define IFX_LED_TRIGGER_ATTRIB_TIMEOUT (1 << 2) -+/*! -+ \def IFX_LED_TRIGGER_ATTRIB_DEF_VALUE -+ \brief field "flags" of struct "ifx_led_trigger_attrib" - def_value is valid. -+ */ -+#define IFX_LED_TRIGGER_ATTRIB_DEF_VALUE (1 << 3) -+ unsigned int flags; /*!< additional flags */ -+}; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_LED_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_led_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_led_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+ -+/*! -+ \struct ifx_led_ioctl_trigger -+ \brief Structure used for trigger operations. -+ */ -+struct ifx_led_ioctl_trigger { -+ char name[32]; /*!< input, name of trigger */ -+ void *handler; /*!< input/output, handler of trigger */ -+ struct ifx_led_trigger_attrib attrib; /*!< input, behavior of LED */ -+}; -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_LED_IOCTL -+ */ -+/*@{*/ -+#define IFX_LED_IOC_MAGIC 0xed -+/*! -+ \def IFX_LED_IOC_VERSION -+ \brief LED IOCTL Command - Get version number of driver. -+ -+ This command uses structure "ifx_led_ioctl_version" as parameter to get version number of driver. -+ */ -+#define IFX_LED_IOC_VERSION _IOR( IFX_LED_IOC_MAGIC, 0, struct ifx_led_ioctl_version) -+/*! -+ \def IFX_LED_IOC_TRIGGER_REGISTER -+ \brief LED IOCTL Command - Register a LED trigger (source of event). -+ -+ This command uses structure "ifx_led_ioctl_trigger" as parameter to register a LED trigger (source of event). -+ User need provide valid "name" before call this IOCTL. -+ The return value is hold in "handler", and it should be used for other IOCTL commands. -+ */ -+#define IFX_LED_IOC_TRIGGER_REGISTER _IOWR(IFX_LED_IOC_MAGIC, 1, struct ifx_led_ioctl_trigger) -+/*! -+ \def IFX_LED_IOC_TRIGGER_DEREGISTER -+ \brief LED IOCTL Command - Deregister a LED trigger (source of event). -+ -+ This command uses structure "ifx_led_ioctl_trigger" as parameter to deregister a LED trigger (source of event). -+ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". -+ After this command, the "handler" is destroyed and can not be used anymore. -+ */ -+#define IFX_LED_IOC_TRIGGER_DEREGISTER _IOW( IFX_LED_IOC_MAGIC, 2, struct ifx_led_ioctl_trigger) -+/*! -+ \def IFX_LED_IOC_TRIGGER_ACTIVATE -+ \brief LED IOCTL Command - send LED trigger (event). -+ -+ This command uses structure "ifx_led_ioctl_trigger" as parameter to send a LED trigger (event). -+ User uses this command to give a notice on LED event, and LED driver will drive LED according to attributes. -+ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". -+ */ -+#define IFX_LED_IOC_TRIGGER_ACTIVATE _IOW( IFX_LED_IOC_MAGIC, 3, struct ifx_led_ioctl_trigger) -+/*! -+ \def IFX_LED_IOC_TRIGGER_DEACTIVATE -+ \brief LED IOCTL Command - reset LED to default status. -+ -+ This command uses structure "ifx_led_ioctl_trigger" as parameter to reset LED to default status. -+ User uses this command to reset LED to default status (e.g. LED off). -+ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". -+ */ -+#define IFX_LED_IOC_TRIGGER_DEACTIVATE _IOW( IFX_LED_IOC_MAGIC, 4, struct ifx_led_ioctl_trigger) -+/*! -+ \def IFX_LED_IOC_TRIGGER_SET_ATTRIB -+ \brief LED IOCTL Command - define LED behavior. -+ -+ This command uses structure "ifx_led_ioctl_trigger" as parameter to define LED behavior. -+ User need provide valid "handler" which is got from "IFX_LED_IOC_TRIGGER_REGISTER". -+ */ -+#define IFX_LED_IOC_TRIGGER_SET_ATTRIB _IOW( IFX_LED_IOC_MAGIC, 5, struct ifx_led_ioctl_trigger) -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ int ifx_led_trigger_register(const char *trigger, void **pphandler); -+ void ifx_led_trigger_deregister(void *phandler); -+ void ifx_led_trigger_activate(void *phandler); -+ void ifx_led_trigger_deactivate(void *phandler); -+ void ifx_led_trigger_set_attrib(void *phandler, struct ifx_led_trigger_attrib *attrib); -+ -+ // Use LED for GPIO Output operation. -+ // Register LED trigger. -+ static inline int ifx_led_gpio_output_register(const char *trigger, void **pphandler) -+ { -+ int ret; -+ struct ifx_led_trigger_attrib attrib = {0}; -+ -+ attrib.flags = IFX_LED_TRIGGER_ATTRIB_DELAY_ON | IFX_LED_TRIGGER_ATTRIB_DELAY_OFF | IFX_LED_TRIGGER_ATTRIB_TIMEOUT | IFX_LED_TRIGGER_ATTRIB_DEF_VALUE; -+ -+ ret = ifx_led_trigger_register(trigger, pphandler); -+ if ( ret == IFX_SUCCESS && *pphandler != NULL ) -+ ifx_led_trigger_set_attrib(*pphandler, &attrib); -+ -+ return ret; -+ } -+ -+ // Use LED for GPIO Output operation. -+ // Deregister LED trigger. -+ static inline void ifx_led_gpio_output_deregister(void *phandler) -+ { -+ ifx_led_trigger_deregister(phandler); -+ } -+ -+ // Use LED for GPIO Output operation. -+ // Output value. -+ static inline void ifx_led_gpio_output_value(void *phandler, unsigned int value) -+ { -+ if ( value != 0 ) -+ ifx_led_trigger_activate(phandler); -+ else -+ ifx_led_trigger_deactivate(phandler); -+ } -+#endif -+ -+ -+ -+#endif // IFX_LED_H -diff --git a/arch/mips/include/asm/ifx/ifx_ledc.h b/arch/mips/include/asm/ifx/ifx_ledc.h -new file mode 100644 -index 0000000..d1a89c1 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_ledc.h -@@ -0,0 +1,351 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ledc.h -+** PROJECT : UEIP -+** MODULES : LED Controller (Serial Out) -+** -+** DATE : 16 Jul 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global LED Controller driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 16 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_LEDC_H -+#define IFX_LEDC_H -+ -+ -+ -+/*! -+ \defgroup IFX_LEDC UEIP Project - LED Controller sub-driver module -+ \brief UEIP Project - LED Controller (Serial Out) sub-driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_LEDC_API APIs -+ \ingroup IFX_LEDC -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_LEDC_IOCTL IOCTL Commands -+ \ingroup IFX_LEDC -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_LEDC_STRUCT Structures -+ \ingroup IFX_LEDC -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ledc.h -+ \ingroup IFX_LEDC -+ \brief LED Controller (Serial Out) sub-driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_LEDC_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * Definition of Operation MASK -+ */ -+/*! -+ \def IFX_LEDC_CFG_OP_UPDATE_SOURCE -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select LED data source. -+ */ -+#define IFX_LEDC_CFG_OP_UPDATE_SOURCE 0x0001 -+/*! -+ \def IFX_LEDC_CFG_OP_BLINK -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - enable/disable blink. -+ */ -+#define IFX_LEDC_CFG_OP_BLINK 0x0002 -+/*! -+ \def IFX_LEDC_CFG_OP_UPDATE_CLOCK -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select update clock source. -+ */ -+#define IFX_LEDC_CFG_OP_UPDATE_CLOCK 0x0004 -+/*! -+ \def IFX_LEDC_CFG_OP_STORE_MODE -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select clock store mode or single pulse store mode. -+ */ -+#define IFX_LEDC_CFG_OP_STORE_MODE 0x0008 -+/*! -+ \def IFX_LEDC_CFG_OP_SHIFT_CLOCK -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select shift clock source. -+ */ -+#define IFX_LEDC_CFG_OP_SHIFT_CLOCK 0x0010 -+/*! -+ \def IFX_LEDC_CFG_OP_DATA_OFFSET -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select cycles (0 ~ 3) to be inserted before data transmition. -+ */ -+#define IFX_LEDC_CFG_OP_DATA_OFFSET 0x0020 -+/*! -+ \def IFX_LEDC_CFG_OP_NUMBER_OF_LED -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select number of LEDs (8, 16, 24). -+ */ -+#define IFX_LEDC_CFG_OP_NUMBER_OF_LED 0x0040 -+/*! -+ \def IFX_LEDC_CFG_OP_DATA -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - LED on/off. -+ */ -+#define IFX_LEDC_CFG_OP_DATA 0x0080 -+/*! -+ \def IFX_LEDC_CFG_OP_MIPS0_ACCESS -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select owner of LED (mips0/mips1). -+ */ -+#define IFX_LEDC_CFG_OP_MIPS0_ACCESS 0x0100 -+/*! -+ \def IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE -+ \brief field "operation_mask" of struct "ifx_ledc_config_param" - select data clock effective edge (rising/falling). -+ */ -+#define IFX_LEDC_CFG_OP_DATA_CLOCK_EDGE 0x0200 -+ -+/* -+ * Constant for Some Operations -+ */ -+/*! -+ \def IFX_LED_CON1_UPDATE_SRC_SOFTWARE -+ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by software trigger. -+ */ -+#define IFX_LED_CON1_UPDATE_SRC_SOFTWARE 0 -+#define LED_CON1_UPDATE_SRC_SOFTWARE IFX_LED_CON1_UPDATE_SRC_SOFTWARE -+/*! -+ \def IFX_LED_CON1_UPDATE_SRC_GPT -+ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by GPT timer. -+ */ -+#define IFX_LED_CON1_UPDATE_SRC_GPT 1 -+#define LED_CON1_UPDATE_SRC_GPT IFX_LED_CON1_UPDATE_SRC_GPT -+/*! -+ \def IFX_LED_CON1_UPDATE_SRC_FPI -+ \brief field "update_clock" of struct "ifx_ledc_config_param" - update LED by FPI clock. -+ */ -+#define IFX_LED_CON1_UPDATE_SRC_FPI 2 -+#define LED_CON1_UPDATE_SRC_FPI IFX_LED_CON1_UPDATE_SRC_FPI -+ -+ -+#define IFX_LED_CON1_GROUP2 (1 << 2) -+#define IFX_LED_CON1_GROUP1 (1 << 1) -+#define IFX_LED_CON1_GROUP0 (1 << 0) -+#define LED_CON1_GROUP2 IFX_LED_CON1_GROUP2 -+#define LED_CON1_GROUP1 IFX_LED_CON1_GROUP1 -+#define LED_CON1_GROUP0 IFX_LED_CON1_GROUP0 -+ -+/*! -+ \def IFX_LED_EXT_SRC_DSL_LED0 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of DSL LED0 -+ */ -+#define IFX_LED_EXT_SRC_DSL_LED0 0 -+/*! -+ \def IFX_LED_EXT_SRC_DSL_LED1 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of DSL LED1 -+ */ -+#define IFX_LED_EXT_SRC_DSL_LED1 1 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY1_LED0 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED0 -+ */ -+#define IFX_LED_EXT_SRC_GPHY1_LED0 2 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY1_LED1 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED1 -+ */ -+#define IFX_LED_EXT_SRC_GPHY1_LED1 3 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY1_LED2 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY1 LED2 -+ */ -+#define IFX_LED_EXT_SRC_GPHY1_LED2 4 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY0_LED0 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED0 -+ */ -+#define IFX_LED_EXT_SRC_GPHY0_LED0 5 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY0_LED1 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED1 -+ */ -+#define IFX_LED_EXT_SRC_GPHY0_LED1 6 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY0_LED2 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY0 LED2 -+ */ -+#define IFX_LED_EXT_SRC_GPHY0_LED2 7 -+/*! -+ \def IFX_LED_EXT_SRC_EPHY_LINK_LED -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Link LED -+ */ -+#define IFX_LED_EXT_SRC_EPHY_LINK_LED IFX_LED_EXT_SRC_GPHY1_LED0 -+/*! -+ \def IFX_LED_EXT_SRC_EPHY_SPEED_LED -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Speed LED -+ */ -+#define IFX_LED_EXT_SRC_EPHY_SPEED_LED IFX_LED_EXT_SRC_GPHY1_LED1 -+/*! -+ \def IFX_LED_EXT_SRC_EPHY_COLLISION_LED -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Collision LED -+ */ -+#define IFX_LED_EXT_SRC_EPHY_COLLISION_LED IFX_LED_EXT_SRC_GPHY1_LED2 -+/*! -+ \def IFX_LED_EXT_SRC_EPHY_DUPLEX_LED -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of Ephy Duplex LED -+ */ -+#define IFX_LED_EXT_SRC_EPHY_DUPLEX_LED IFX_LED_EXT_SRC_GPHY0_LED0 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY2_LED0 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED0 -+ */ -+#define IFX_LED_EXT_SRC_GPHY2_LED0 8 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY2_LED1 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED1 -+ */ -+#define IFX_LED_EXT_SRC_GPHY2_LED1 9 -+/*! -+ \def IFX_LED_EXT_SRC_GPHY2_LED2 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of GPHY2 LED2 -+ */ -+#define IFX_LED_EXT_SRC_GPHY2_LED2 10 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_SB_LQ -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link Quality Single Band LED -+ */ -+#define IFX_LED_EXT_SRC_WLAN_SB_LQ 11 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_DB_LQ -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link Quality Dual Band LED -+ */ -+#define IFX_LED_EXT_SRC_WLAN_DB_LQ 12 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_SB_LA -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link/Activity Single Band LED -+ */ -+#define IFX_LED_EXT_SRC_WLAN_SB_LA 13 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_DB_LA -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Link/Activity Dual Band LED -+ */ -+#define IFX_LED_EXT_SRC_WLAN_DB_LA 14 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_SECU0 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Security LED0 (Dual Color) -+ */ -+#define IFX_LED_EXT_SRC_WLAN_SECU0 15 -+/*! -+ \def IFX_LED_EXT_SRC_WLAN_SECU1 -+ \brief field "source" and "source_mask" of struct "ifx_ledc_config_param" - index of WLAN Security LED1 (Dual Color) -+ */ -+#define IFX_LED_EXT_SRC_WLAN_SECU1 16 -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_LEDC_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_ledc_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_ledc_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+ -+/*! -+ \struct ifx_ledc_config_param -+ \brief Structure used for configure LED Controller (Serial Out). -+ */ -+struct ifx_ledc_config_param { -+ unsigned long operation_mask; /*!< input, Select operations to be performed */ -+ unsigned long source_mask; /*!< input, LED to change update source (LEDC or Ext - ADSL, PHY) */ -+ unsigned long source; /*!< input, Corresponding update source (LEDC or Ext - ADSL, PHY), 0 - LEDC, 1 - EXT */ -+ unsigned long blink_mask; /*!< input, LEDs to set blink mode */ -+ unsigned long blink; /*!< input, Set to blink mode or normal mode, 0 - blinking, 1 - non-blinking */ -+ unsigned long update_clock; /*!< input, Select the source of update clock, 0 - Software, 1 - GPT, 2 - FPI */ -+ unsigned long fpid; /*!< input, If FPI is the source of update clock, set the divider */ -+ /*!< input, else if GPT is the source, set the frequency (unit 1/10Hz) */ -+ /*!< input, else if SOFTWARE is the source, set the frequency (unit 1/10Hz), or 0 stands for update on request */ -+ unsigned long store_mode; /*!< input, Set clock mode or single pulse mode for store signal, 0 - single store, 1 - shift clock store */ -+ unsigned long fpis; /*!< input, FPI is the source of shift clock, set the divider */ -+ unsigned long data_offset; /*!< input, Set cycles to be inserted before data is transmitted (0 - 3) */ -+ unsigned long number_of_enabled_led; /*!< input, Total number of LED to be enabled (0, 8, 16, 24) */ -+ unsigned long data_mask; /*!< input, LEDs to set value */ -+ unsigned long data; /*!< input, Corresponding value, 0 - low output (off), 1 - high output (on) */ -+ unsigned long mips0_access_mask; /*!< input, LEDs to set access right (not valid for Amazon-SE) */ -+ unsigned long mips0_access; /*!< input, 1: the corresponding data is output from MIPS0, 0: MIPS1 */ -+ unsigned long f_data_clock_on_rising; /*!< input, 1: data clock on rising edge, 0: data clock on falling edge */ -+}; -+ -+/*@}*/ -+ -+/*! -+ \addtogroup IFX_LEDC_IOCTL -+ */ -+/*@{*/ -+#define IFX_LEDC_IOC_MAGIC 'k' -+/*! -+ \def IFX_LEDC_IOC_VERSION -+ \brief LED Controller IOCTL Command - Get driver version number. -+ -+ This command uses struct "ifx_ledc_ioctl_version" as parameter to LED Controller driver version number. -+ */ -+#define IFX_LEDC_IOC_VERSION _IOR(IFX_LEDC_IOC_MAGIC, 0, struct ifx_ledc_ioctl_version) -+/*! -+ \def IFX_LEDC_IOC_SET_CONFIG -+ \brief LED Controller IOCTL Command - Config LED Controller (Serial Out). -+ -+ This command uses struct "ifx_ledc_config_param" as parameter to configure LED Controller (Serial Out). -+ */ -+#define IFX_LEDC_IOC_SET_CONFIG _IOW(IFX_LEDC_IOC_MAGIC, 1, struct ifx_ledc_config_param) -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ int ifx_ledc_set_blink(unsigned int led, unsigned int blink); -+ int ifx_ledc_set_data(unsigned int led, unsigned int data); -+int ifx_ledc_set_data2(unsigned int led1, unsigned int data1, unsigned int led2, unsigned int data2); -+ int ifx_ledc_config(struct ifx_ledc_config_param *param); -+#endif -+ -+ -+ -+#endif // IFX_LEDC_H -diff --git a/arch/mips/include/asm/ifx/ifx_mmc_wlan.h b/arch/mips/include/asm/ifx/ifx_mmc_wlan.h -new file mode 100644 -index 0000000..6f770f6 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_mmc_wlan.h -@@ -0,0 +1,311 @@ -+/** -+** FILE NAME : ifx_mmc_wlan.h -+** PROJECT : IFX UEIP -+** MODULES : MMC module for WLAN -+** DATE : -+** AUTHOR : Ralf Janssen -+** DESCRIPTION : IFX Cross-Platform MMC for WLAN device driver header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 12 May 2010 Ralf Janssen Initial release -+*******************************************************************************/ -+/*! -+ \file ifx_mmc_wlan.h -+ \ingroup IFX_MMC_DRV -+ \brief MMC host driver for WLAN SDIO Card -+*/ -+ -+#ifndef __IFX_SDIO_WLAN_H__ -+#define __IFX_SDIO_WLAN_H__ -+ -+/*! -+ @brief Handle, that is returned by \ref ifx_sdio_open and is passed to all SDIO functions. -+ */ -+typedef uint32_t ifx_sdio_handle_t; -+ -+/*! -+ @brief Function pointer to callback handler. -+ -+ The WLAN driver (or any other driver using this SDIO driver) can use this callback handler -+ to get informed, when an asynchronous transaction has been completed. -+ */ -+typedef void (*ifx_sdio_callback_handler_t)(void *context, int status); -+ -+/*! -+ @brief Structure containing the required configuration and default parameters for the SDIO driver. -+ -+ This structure is passed to \ref ifx_sdio_open to configure the SDIO interface with respect to -+ clock, function select, block/byte mode, bus width, CRC handling, interrupt path (in-band/out-of-band) -+ and which GPIO is used for reset. -+ */ -+typedef struct ifx_sdio_config { -+ ifx_sdio_callback_handler_t callback_handler; /*!< Callback handler, used for async operations */ -+ void *context; /*!< Context of SDIO device driver, -+ will be passed to async callback handlers. */ -+ uint32_t clock; /*!< SDIO clock freuqency in Hz */ -+ -+ /* The following parameters are used to pre-define some parameters */ -+ /* used with almost all SDIO commands (CMD52/CMD53). */ -+ uint8_t function; /*!< Default function number in CMD52/53 */ -+ uint8_t raw; /*!< Default RAW flag in CMD52 */ -+ uint8_t block_mode; /*!< Default block-/byte-mode flag in CMD53 */ -+ uint8_t opcode; /*!< Default opcode flag in CMD53 */ -+ -+ uint16_t block_len; /*!< @brief Default block length for CMD53 block transfers */ -+ uint8_t bus_width; /*!< 1-/4-Bit bus */ -+ -+ /* The SDIO controller does not generate a CRC in byte mode */ -+ /* Therefore the driver allows to calculate and append the CRC in SW */ -+ uint8_t crc; /*!< If set, calculate and append CRC for CMD53 byte mode */ -+ uint8_t irq_oob; /*!< If set, use Out-Of-Band interrupt via GPIO29 */ -+ uint8_t rst_gpio; /*!< GPIO-Number for external reset (255 for none) */ -+} ifx_sdio_config_t; -+ -+ -+/*! -+ @brief Structure containing definition for SDIO commands. -+ -+ This structure contains information about the command (0..63), the argument of the command -+ and the response type (\ref MMC_RSP_TYPES). -+ */ -+typedef struct ifx_sdio_cmd { -+ uint32_t op_code; /*!< SDIO command (0..63) */ -+ uint32_t args; /*!< argument to SDIO command */ -+ uint32_t response_type; /*!< Response type (\ref MMC_RSP_TYPES) */ -+ uint32_t response[4]; /*!< Short/Long response from SDIO device */ -+ int error; /*!< return code of \ref ifx_sdio_cmd */ -+} ifx_sdio_cmd_t; -+ -+/*! -+ @internal -+ */ -+/*@{*/ -+/* response types, copied from linux-2.6.26.1/include/linux/mmc/core.h */ -+#define MMC_RSP_PRESENT (1 << 0) -+#define MMC_RSP_136 (1 << 1) /* 136 bit response */ -+#define MMC_RSP_CRC (1 << 2) /* expect valid crc */ -+#define MMC_RSP_BUSY (1 << 3) /* card may send busy */ -+#define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */ -+ -+/*! -+ @defgroup MMC_RSP_TYPES SDIO Response types -+ @{ -+ */ -+#define MMC_RSP_NONE (0) /*!< No response expected */ -+#define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R1 expected */ -+#define MMC_RSP_R1B (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE|MMC_RSP_BUSY) /*!< Response R1B expected */ -+#define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC) /*!< Response R2 expected */ -+#define MMC_RSP_R3 (MMC_RSP_PRESENT) /*!< Response R3 expected */ -+#define MMC_RSP_R4 (MMC_RSP_PRESENT) /*!< Response R4 expected */ -+#define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R5 expected */ -+#define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R6 expected */ -+#define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE) /*!< Response R7 expected */ -+/* @} */ -+ -+ -+/* -+ * Exported functions -+ */ -+ -+/* open SDIO interface and set configuration */ -+/*! -+ * @brief -+ * This function opens the SDIO interface. -+ * -+ * It initializes all registers and activates the module clock.\n -+ * The second parameter allows to configure the operational mode. -+ * @param[in] -+ * dev_index Device index starting with 0 for the first SDIO device. -+ * @param[in] -+ * cfg Requested configuration of the SDIO interface. -+ * @return -+ * < 0 In case of errors (see errno.h for error codes).\n -+ * >=0 Device handle that is used to call SDIO functions. -+ */ -+ifx_sdio_handle_t ifx_sdio_open(int dev_index, ifx_sdio_config_t *cfg); -+ -+ -+/* close SDIO interface and release resources */ -+/*! -+ * @brief -+ * This function closes the SDIO interface. -+ * -+ * It clears all registers and deactivates the module clock. -+ * @param[in] -+ * sh Device handle returned by ifx_sdio_open -+ * @return -+ * < 0 In case of errors (see errno.h for error codes).\n -+ * 0 If no error ocurred. -+ */ -+int ifx_sdio_close(ifx_sdio_handle_t sh); -+ -+ -+/* configure various settings of the driver */ -+/*! -+ * @brief -+ * Provide ioctl style function for configuration purposes. -+ * -+ * -+ * @param[in] -+ * sh Device handle returned by \ref ifx_sdio_open -+ * @param[in] -+ * command Command that should be executed (\ref IFX_SDIO_IOCTL_COMMANDS).\n -+ * @param[in, out] -+ * param Parameter to command. The meaning is command specific -+ * -+ * @return -+ * < 0 In case of errors (see errno.h for error codes).\n -+ * 0 If no error ocurred. -+ */ -+int ifx_sdio_ioctl(ifx_sdio_handle_t sh, uint32_t command, uint32_t param); -+ -+/* Request SDIO device interrupt line from kernel and enable interrupt in SDIO core */ -+int ifx_sdio_request_irq(ifx_sdio_handle_t sh, irq_handler_t handler, -+ unsigned long flags, const char *dev_name, -+ void *dev_id); -+ -+/* Disable interrupt in SDIO core and free interrupt line. */ -+int ifx_sdio_free_irq (ifx_sdio_handle_t sh, void *dev_id); -+ -+/* This functions enables the SDIO device interrupt. */ -+int ifx_sdio_enable_irq (ifx_sdio_handle_t sh); -+ -+/* This function disables the SDIO device interrupt. */ -+int ifx_sdio_disable_irq (ifx_sdio_handle_t sh); -+ -+/* send a command to the SDIO device and wait for response */ -+int ifx_sdio_cmd(ifx_sdio_handle_t sh, ifx_sdio_cmd_t *cmd); -+ -+/* send a command to the SDIO device and wait for response, -+ provide all parameters directly */ -+int ifx_sdio_cmd_ext(ifx_sdio_handle_t sh, uint8_t op_code, uint32_t args, -+ uint32_t response_type, uint32_t *response); -+ -+/* write one byte via CMD52 to SDIO device */ -+int ifx_sdio_write_byte(ifx_sdio_handle_t sh, uint32_t address, -+ uint8_t in, uint8_t *out); -+ -+/* write one byte via CMD52 to SDIO device, but provide all parameter */ -+int ifx_sdio_write_byte_ext(ifx_sdio_handle_t sh, uint32_t address, -+ uint8_t function, uint8_t raw, -+ uint8_t in, uint8_t *out); -+ -+/* Write arbitrary number of bytes to device. -+ Return, when all data has been transferred. */ -+int ifx_sdio_write_sync(ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count); -+ -+/* Write arbitrary number of bytes to device, but provide all parameter. -+ Return, when all data has been transferred. */ -+int ifx_sdio_write_sync_ext(ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count, -+ uint8_t function, uint8_t block_len_pow, uint8_t opcode); -+ -+/* Write arbitrary number of bytes to device. -+ Return immediately after starting the transfer. */ -+int ifx_sdio_write_async(ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count); -+ -+/* Write arbitrary number of bytes to device, but provide all parameter -+ Return immediately after starting the transfer. */ -+int ifx_sdio_write_async_ext(ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count, -+ uint8_t function, uint8_t block_len_pow, uint8_t opcode); -+ -+/* Read a single byte via CMD52. */ -+int ifx_sdio_read_byte(ifx_sdio_handle_t sh, uint32_t address, uint8_t *pdata); -+ -+/* Read a single byte via CMD52, but provide all paramter. */ -+int ifx_sdio_read_byte_ext(ifx_sdio_handle_t sh, uint32_t address, -+ uint8_t function, uint8_t *pdata); -+ -+/* Read arbitrary number of bytes from device. -+ Return, when all data has been transferred. */ -+int ifx_sdio_read_sync (ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count); -+ -+/* Read arbitrary number of bytes from device, but provide all parameter. -+ Return, when all data has been transferred. */ -+int ifx_sdio_read_sync_ext (ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count, -+ uint8_t function, uint8_t block_len_pow, uint8_t opcode); -+ -+/* Read arbitrary number of bytes from device. -+ Return immediately after starting the transfer. */ -+int ifx_sdio_read_async (ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count); -+ -+/* Read arbitrary number of bytes from device, but provide all parameter. -+ Return immediately after starting the transfer. */ -+int ifx_sdio_read_async_ext(ifx_sdio_handle_t sh, uint32_t address, -+ void *data, uint32_t count, -+ uint8_t function, uint8_t block_len_pow, uint8_t opcode); -+ -+ -+ -+int ifx_sdio_enumerate(ifx_sdio_handle_t sh); -+ -+int ifx_sdio_poll_async_state(ifx_sdio_handle_t sh); -+ -+ -+/* -+ * IOCTL commands -+ */ -+/*! -+ @defgroup IFX_SDIO_IOCTL_COMMANDS IFX SDIO ioctl commands -+ @{ -+ -+ This section lists the available ioctl commands of the SDIO driver. -+ Also the meaning of the \ref ifx_sdio_ioctl parameter -+ is described per command. -+*/ -+ -+/*! -+ IFX_SDIO_IOCTL_SET_CLK sets the clock frequency of SDIO interface in Hz. -+ -+ @param The requested SDIO clock in HZ is specified as parameter in \ref ifx_sdio_ioctl. -+ The actual frequency is rounded to the next valid value less or equal to the requested one. -+*/ -+#define IFX_SDIO_IOCTL_SET_CLK 1 -+ -+/*! -+ IFX_SDIO_IOCTL_SET_BUS_WIDTH select the bus width of the SDIO interface, when using CMD53. -+ -+ @param Bus width selection as defined by \ref IFX_SDIO_IOCTL_PARAM_BUS_WIDTH. -+ */ -+#define IFX_SDIO_IOCTL_SET_BUS_WIDTH 2 -+ -+/*! -+ IFX_SDIO_IOCTL_SET_BLOCK_LENGTH sets the block length for CMD53 block-transactions. -+ -+ @param Block length in bytes. The block length must be a power of 2. -+ */ -+#define IFX_SDIO_IOCTL_SET_BLOCK_LENGTH 3 -+ -+/*! -+ IFX_SDIO_IOCTL_SET_FUNCTION modifies the by default selected function withtin the SDIO device. -+ This feature has not been implemented, yet. -+ -+ @param Function number (0..7) of SDIO device. -+ */ -+#define IFX_SDIO_IOCTL_SET_FUNCTION 4 -+/* @} */ -+ -+/*! -+ @defgroup IFX_SDIO_IOCTL_PARAM_BUS_WIDTH ioctl parameter for command \ref IFX_SDIO_IOCTL_SET_BUS_WIDTH -+ @{ -+ */ -+#define IFX_SDIO_IOCTL_BUS_WIDTH_1 0 /*!< Set Bus width to 1-Bit */ -+#define IFX_SDIO_IOCTL_BUS_WIDTH_4 1 /*!< Set Bus width to 4-Bit */ -+/* @} */ -+ -+#endif /* __IFX_SDIO_WLAN_H__ */ -diff --git a/arch/mips/include/asm/ifx/ifx_pmcu.h b/arch/mips/include/asm/ifx/ifx_pmcu.h -new file mode 100644 -index 0000000..128431d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_pmcu.h -@@ -0,0 +1,417 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+#ifndef _IFX_PMCU_H_ -+#define _IFX_PMCU_H_ -+ -+#include "ifx_types.h" -+ -+/** -+ \file ifx_pmcu.h -+ PMCU (Power Management Control Unit) , userinterface controls and kernel API -+ -+ Header file contains defines, structures, constants and prototypes for I/O -+*/ -+ -+ -+/** -+ \defgroup LQ_PMCU_IOCTL IOCTL's -+ \ingroup LQ_PMCU -+*/ -+/* @{ */ -+/*=============================================================================*/ -+/* PMCU IOCTL DEFINES */ -+/*=============================================================================*/ -+/** Set a given module into a specific power state -+ -+ \param IFX_PMCU_MODULE_STATE_t* Pointer to a -+ \ref IFX_PMCU_MODULE_STATE_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ IFX_PMCU_MODULE_STATE_t param; -+ param.pmcuModule=IFX_PMCU_MODULE_CPU; -+ param.pmcuModuleNr=0; -+ param.pmcuState=IFX_PMCU_STATE_D0; -+ ioctl(fd, IFX_PMCU_STATE_REQ, ¶m); -+ \endcode -+*/ -+#define IFX_PMCU_STATE_REQ 0 -+ -+ -+/** Get the current power state from a given module -+ \param IFX_PMCU_MODULE_STATE_t* Pointer to a -+ \ref IFX_PMCU_MODULE_STATE_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ IFX_PMCU_MODULE_STATE_t param; -+ param.pmcuModule=IFX_PMCU_MODULE_CPU; -+ param.pmcuModuleNr=0; -+ param.pmcuState=IFX_PMCU_STATE_INVALID; -+ ioctl(fd, IFX_PMCU_STATE_GET, ¶m); -+ \endcode -+*/ -+#define IFX_PMCU_STATE_GET 1 -+ -+ -+/** Change the log level for the PMCU module -+ \param integer value which specifies the log level -+ - <0 = quiet -+ - 0 = only ERRORS,WARNINGS (default) -+ - 1 = + INFO -+ - 2 = all -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ int loglevel = 2; -+ ioctl(fd, IFX_PMCU_LOG_LEVEL, &loglevel); -+ \endcode -+*/ -+#define IFX_PMCU_LOG_LEVEL 2 -+ -+ -+/** Control the acceptance of the powerstate request for the -+ PMCU module. To have a central possibility for a global -+ enable/disable of the powerstate requests coming from other -+ modules, this IOCTL is introduced. -+ \param integer value to enable/disable the powerstate -+ request inside the PMCU driver. -+ - 0 = All powerstate requests received by the PMCU -+ will be rejected. Default -+ - 1 = Powerstate requests are accepted by the PMCU -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ enable the powerstate request acceptance -+ int reqCtrl = 1; -+ ioctl(fd, IFX_PMCU_REQ_CTRL, &reqCtrl); -+ \endcode -+*/ -+#define IFX_PMCU_REQ_CTRL 3 -+ -+//########################################## -+/** Switch the available power management features of the system -+ on and off. -+ -+ \param IFX_PMCU_MODULE_PWR_FEATURE_STATE_t* Pointer to struct -+ \ref IFX_PMCU_MODULE_PWR_FEATURE_STATE_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ IFX_PMCU_MODULE_PWR_FEATURE_STATE_t param; -+ param.pmcuModule=IFX_PMCU_MODULE_CPU; -+ param.pmcuModuleNr=0; -+ param.pmcuPwrFeatureState=IFX_PMCU_PWR_STATE_OFF; -+ ioctl(fd, IFX_PMCU_PWR_FEATURE_SWITCH, ¶m); -+ \endcode -+*/ -+#define IFX_PMCU_PWR_FEATURE_SWITCH 4 -+ -+//########################################## -+ -+ -+ -+/* @} */ /* LQ_PMCU_IOCTL */ -+ -+/** -+ \defgroup LQ_PMCU Power Management Control Unit -+ \ingroup LQ_COC -+ Ifx pmcu driver module -+*/ -+/* @{ */ -+/*=============================================================================*/ -+/* PMCU ENUMERATION */ -+/*=============================================================================*/ -+/** IFX_PMCU_MODULE_t -+ Definition of the modules identifier -+ */ -+typedef enum { -+ IFX_PMCU_MODULE_PMCU = 0, /** all modules registered within PMCU */ -+ IFX_PMCU_MODULE_CPU = 1, -+ IFX_PMCU_MODULE_ETH = 2, -+ IFX_PMCU_MODULE_USB = 3, -+ IFX_PMCU_MODULE_DSL = 4, -+ IFX_PMCU_MODULE_WLAN = 5, -+ IFX_PMCU_MODULE_DECT = 6, -+ IFX_PMCU_MODULE_FXS = 7, -+ IFX_PMCU_MODULE_FXO = 8, -+ IFX_PMCU_MODULE_VE = 9, -+ IFX_PMCU_MODULE_PPE = 10, -+ IFX_PMCU_MODULE_SWITCH = 11, -+ IFX_PMCU_MODULE_UART = 12, -+ IFX_PMCU_MODULE_SPI = 13, -+ IFX_PMCU_MODULE_SDIO = 14, -+ IFX_PMCU_MODULE_PCI = 15, -+ IFX_PMCU_MODULE_VLYNQ = 16, -+ IFX_PMCU_MODULE_DEU = 17, -+ IFX_PMCU_MODULE_CPU_PS = 18, -+ IFX_PMCU_MODULE_GPTC = 19, -+ IFX_PMCU_MODULE_USIF_UART = 20, /* VR9 usage */ -+ IFX_PMCU_MODULE_USIF_SPI = 21, /* VR9 usage */ -+ IFX_PMCU_MODULE_PCIE = 22, /* VR9 usage */ -+ IFX_PMCU_MODULE_ID_MAX = 23, -+} IFX_PMCU_MODULE_t; -+ -+ -+/** IFX_PMCU_STATE_t -+ Definition of power management state -+*/ -+typedef enum { -+ /* ATTENTION: Keep in mind that this list correspond to the ifx_pmcu_stateMap[][] array. -+ If you have to change this list for any reason, ifx_pmcu_stateMap[][] must be adapted too. */ -+ -+ /** State Invalid. */ -+ IFX_PMCU_STATE_INVALID = 0, -+ /** State D0. Fully on */ -+ IFX_PMCU_STATE_D0 = 1, -+ /** State D1. Device dependent */ -+ IFX_PMCU_STATE_D1 = 2, -+ /** State D2. Device dependent */ -+ IFX_PMCU_STATE_D2 = 3, -+ /** State D3. Off */ -+ IFX_PMCU_STATE_D3 = 4, -+ /** don't care state */ -+ IFX_PMCU_STATE_D0D3 = 5, -+} IFX_PMCU_STATE_t; -+ -+ -+//################################################# -+typedef enum { -+ /** State Invalid. */ -+ IFX_PMCU_PWR_STATE_INVALID = 0, -+ /** Features State on */ -+ IFX_PMCU_PWR_STATE_ON = 1, -+ /** Features State off */ -+ IFX_PMCU_PWR_STATE_OFF = 2, -+} IFX_PMCU_PWR_STATE_ENA_t; -+//################################################# -+ -+ -+ -+/** IFX_PMCU_TRANSITION_t -+ Event passed to the PMCU -+ \remarks Reserved for future use. -+*/ -+typedef enum { -+ /** No event to be reported */ -+ IFX_PMCU_EVENT_NONE = 0, -+ /** State change */ -+ IFX_PMCU_EVENT_STATE = 1, -+ /** Module activated */ -+ IFX_PMCU_EVENT_ACTIVATED = 2, -+ /** Module deactivated */ -+ IFX_PMCU_EVENT_DEACTIVATED = 3, -+ /** Device dependent event EXT1 */ -+ IFX_PMCU_EVENT_EXT1 = 4, -+ /** Device dependent event EXT2 */ -+ IFX_PMCU_EVENT_EXT2 = 5, -+} IFX_PMCU_TRANSITION_t; -+ -+ -+/** IFX_PMCU_RETURN_t -+ Return value for PMCU functions and callbacks -+*/ -+typedef enum { -+ /** Operation success */ -+ IFX_PMCU_RETURN_SUCCESS = 0, -+ /** Operation denied */ -+ IFX_PMCU_RETURN_DENIED = 1, -+ /** Error condition */ -+ IFX_PMCU_RETURN_ERROR = 2, -+ /** called function just return without doing anything; used only in callback functions */ -+ IFX_PMCU_RETURN_NOACTIVITY = 3, -+ /** is used if callback function is not defined */ -+ IFX_PMCU_RETURN_NOTDEFINED = 4, -+} IFX_PMCU_RETURN_t; -+ -+ -+/*=============================================================================*/ -+/* PMCU STRUCTURES */ -+/*=============================================================================*/ -+/** IFX_PMCU_MODULE_STATE_t -+ Structure hold the module-ID, the moduleSub-ID and the PowerState of one module. -+*/ -+typedef struct { -+ /** Module identifier */ -+ IFX_PMCU_MODULE_t pmcuModule; -+ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ -+ IFX_uint8_t pmcuModuleNr; -+ /** Module PowerState */ -+ IFX_PMCU_STATE_t pmcuState; -+} IFX_PMCU_MODULE_STATE_t; -+ -+//################################### -+/** IFX_PMCU_MODULE_PWR_FEATURE_STATE_t -+ Structure hold the module-ID and the PowerFeature_State to be set for a dedicated module. -+*/ -+typedef struct { -+ /** Module identifier */ -+ IFX_PMCU_MODULE_t pmcuModule; -+ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ -+ IFX_uint8_t pmcuModuleNr; -+ /** Module PowerFeatureState */ -+ IFX_PMCU_PWR_STATE_ENA_t pmcuPwrFeatureState; -+} IFX_PMCU_MODULE_PWR_FEATURE_STATE_t; -+//################################### -+ -+ -+/** IFX_PMCU_STATES_DEP_t -+ Structure that describes dependencies on the given power-states of the -+ given module. -+*/ -+typedef struct { -+ /** Module identifier */ -+ IFX_PMCU_MODULE_t pmcuModule; -+ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ -+ IFX_uint8_t pmcuModuleNr; -+ /** possible values: D0, D1, D2, D3 */ -+ IFX_PMCU_STATE_t onState; -+ /** possible values: D0, D1, D2, D3 */ -+ IFX_PMCU_STATE_t standBy; -+ /** possible values: D0, D1, D2, D3 */ -+ IFX_PMCU_STATE_t lpStandBy; -+ /** possible values: D0, D1, D2, D3 */ -+ IFX_PMCU_STATE_t offState; -+} IFX_PMCU_STATES_DEP_t; -+ -+ -+/** IFX_PMCU_MODULE_DEP_t -+ Structure to list dependencies on multiple modules. -+*/ -+typedef struct { -+ /** number of entries in the dependency list moduleStates[] */ -+ IFX_uint32_t nDepth; -+ /** power state dependency list(s) of one module */ -+ IFX_PMCU_STATES_DEP_t moduleStates[]; -+} IFX_PMCU_MODULE_DEP_t; -+ -+ -+/**IFX_PMCU_EVENT_t -+ Structure used to report an information to the PMCU -+ \remarks Reserved for future use. -+ */ -+typedef struct { -+ /** Module identifier */ -+ IFX_PMCU_MODULE_t pmcuModule; -+ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ -+ IFX_uint8_t pmcuModuleNr; -+ /** Current module state */ -+ IFX_PMCU_STATE_t pmcuState; -+ /** Transition passed to the PMCU */ -+ IFX_PMCU_TRANSITION_t pmcuTransition; -+} IFX_PMCU_EVENT_t; -+ -+ -+/** IFX_PMCU_REGISTER_t -+ Structure used to register/unregister a driver to the PMCU -+*/ -+typedef struct { -+ /** Module identifier */ -+ IFX_PMCU_MODULE_t pmcuModule; -+ /** instance identification of a Module; values 0,1,2,..... (0=first instance) */ -+ IFX_uint8_t pmcuModuleNr; -+ /** pointer to the module dependency list. -+ The dependency list will be copied into a static structure inside the PMCU. */ -+ IFX_PMCU_MODULE_DEP_t *pmcuModuleDep; -+ /** Callback to be called before module changes it's state to new */ -+ IFX_PMCU_RETURN_t (*pre) ( IFX_PMCU_MODULE_t pmcuModule, -+ IFX_PMCU_STATE_t newState, -+ IFX_PMCU_STATE_t oldState); -+ /** Callback used to change module's power state */ -+ IFX_PMCU_RETURN_t (*ifx_pmcu_state_change) ( IFX_PMCU_STATE_t pmcuState ); -+ /** Callback to be called after module changes it's state to new state */ -+ IFX_PMCU_RETURN_t (*post) ( IFX_PMCU_MODULE_t pmcuModule, -+ IFX_PMCU_STATE_t newState, -+ IFX_PMCU_STATE_t oldState); -+ /** Optional: Callback used to get module's power state. Set to NULL if unused */ -+ IFX_PMCU_RETURN_t (*ifx_pmcu_state_get) ( IFX_PMCU_STATE_t *pmcuState ); -+//################################### -+ /** Callback used to enable/disable the power features of the module */ -+ IFX_PMCU_RETURN_t (*ifx_pmcu_pwr_feature_switch) ( IFX_PMCU_PWR_STATE_ENA_t pmcuPwrStateEna ); -+//################################### -+ -+} IFX_PMCU_REGISTER_t; -+/* @} */ /* LQ_PMCU */ -+ -+/** -+ \defgroup LQ_PMCU_KERNEL_API Kernel API -+ \ingroup LQ_PMCU -+*/ -+/* @{ */ -+/*=============================================================================*/ -+/* PMCU FUNCTION PROTOTYPES */ -+/*=============================================================================*/ -+#ifdef __KERNEL__ -+/** -+ PMCU kernel API prototypes -+*/ -+ -+/** -+ Request module state change to PMCU -+ -+ \param [in] pmcuModule define module for state change -+ \param [in] pmcuModuleNr instance identification of a Module; values 0,1,2,..... (0=first instance) -+ \param [in] newState requested power state -+ -+ \return Returns value as follows: -+ - IFX_PMCU_RETURN_SUCCESS: if successful -+ - IFX_PMCU_RETURN_ERROR: in case of an error -+ -+*/ -+IFX_PMCU_RETURN_t ifx_pmcu_state_req (IFX_PMCU_MODULE_t pmcuModule, IFX_uint8_t pmcuModuleNr, IFX_PMCU_STATE_t newState); -+ -+ -+/** -+ Register a module, which is affected by a powerState change or initiate a powerState change, to the PMCU -+ -+ \param [in] pmcuRegister Registration Information -+ -+ \return Returns value as follows: -+ - IFX_PMCU_RETURN_SUCCESS: if successful -+ - IFX_PMCU_RETURN_ERROR: in case of an error -+ -+*/ -+IFX_PMCU_RETURN_t ifx_pmcu_register (IFX_PMCU_REGISTER_t* pmcuRegister); -+ -+ -+/** -+ Unregister a module from the PMCU. -+ -+ \param [in] pmcuUnregister Unregistration Information. Only module name is required. -+ -+ \return Returns value as follows: -+ - IFX_PMCU_RETURN_SUCCESS: if successful -+ - IFX_PMCU_RETURN_ERROR: in case of an error -+ -+*/ -+IFX_PMCU_RETURN_t ifx_pmcu_unregister (IFX_PMCU_REGISTER_t* pmcuUnregister); -+ -+#endif /* __KERNEL__ */ -+ -+/* @} */ /* LQ_PMCU_KERNEL_API */ -+ -+#endif /* _IFX_PMCU_H_ */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_pmon.h b/arch/mips/include/asm/ifx/ifx_pmon.h -new file mode 100644 -index 0000000..acccc08 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_pmon.h -@@ -0,0 +1,204 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_pmon.h -+** PROJECT : IFX UEIP -+** MODULES : PMON -+** -+** DATE : 21 July 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : IFX Performance Monitor -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 21 July 2009 Lei Chuanhua The first UEIP release -+*******************************************************************************/ -+ -+/** -+ \defgroup IFX_PMON Performance Monitor Interface Module -+ \brief ifx pmon driver module -+*/ -+ -+/*! -+ \defgroup IFX_PMON_DEFINITIONS Defintions and structures -+ \ingroup IFX_PMON -+ \brief definitions for ifx pmon driver -+*/ -+ -+/*! -+ \defgroup IFX_PMON_IOCTL User API IOCTL -+ \ingroup IFX_PMON -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \file ifx_pmon.h -+ \ingroup IFX_PMON -+ \brief ifx pmon driver header file for APIs -+*/ -+#ifndef IFX_PMON_H -+#define IFX_PMON_H -+/*! -+ \addtogroup IFX_PMON_DEFINITIONS -+ */ -+/* @{ */ -+#ifdef CONFIG_VR9 -+/*! \enum IFX_PMON_EVENT -+ \brief External PMON Event defintion -+ */ -+enum IFX_PMON_EVENT { -+ IFX_PMON_EVENT_NONE = 0, /*!< No input (default) */ -+#define IFX_PMON_EVENT_MIN IFX_PMON_EVENT_NONE -+ IFX_PMON_EVENT_DDR_READ, /*!< DDR read commands, independent of length */ -+ IFX_PMON_EVENT_DDR_WRITE, /*!< DDR write commands, independent of length */ -+ IFX_PMON_EVENT_DDR_MASK_WRITE, /*!< DDR masked write commands */ -+ IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_READ,/*!< Single-word 64-bit read commands */ -+ IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_READ,/*!< 2-beat burst 64-bit read commands */ -+ IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_READ,/*!< 4-word 64-bit read commands */ -+ IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_READ,/*!< 8-word 64-bit read commands */ -+ IFX_PMON_EVENT_DDR_ONE_WORD_64BIT_WRITE,/*!< Single 64-bit write commands */ -+ IFX_PMON_EVENT_DDR_TWO_WORD_64BIT_WRITE, /*!< 2-word 64-bit write commands */ -+ IFX_PMON_EVENT_DDR_FOUR_WORD_64BIT_WRITE,/*!< 4-word 64-bit write commands */ -+ IFX_PMON_EVENT_DDR_EIGHT_WORD_64BIT_WIRTE,/*!< 8-word 64-bit write commands */ -+ IFX_PMON_EVENT_AHB_READ_CYCLES, /*!< DMA 32-bit receive block counter */ -+ IFX_PMON_EVENT_AHB_READ_CPT, /*!< DMA 32-bit transmit block counter */ -+ IFX_PMON_EVENT_AHB_WRITE_CYCLES,/*!< AHB read completed */ -+ IFX_PMON_EVENT_AHB_WRITE_CPT, /*!< AHB write completed */ -+ IFX_PMON_EVENT_DMA_RX_BLOCK_CNT,/*!< AHB total read cycles */ -+ IFX_PMON_EVENT_DMA_TX_BLOCK_CNT,/*!< AHB total write cycles */ -+#define IFX_PMON_EVENT_MAX IFX_PMON_EVENT_DMA_TX_BLOCK_CNT -+}; -+#elif defined (CONFIG_AR10) -+#define IFX_PMON_EVENT_NONE 0 -+#define IFX_PMON_BIU0_READ_EVENT 0x04 /*!< Bus interface Unit0 read */ -+#define IFX_PMON_BIU0_WRITE_EVENT 0x05 /*!< Bus interface Unit0 write */ -+#define IFX_PMON_BIU1_READ_EVENT 0x06 /*!< Bus interface Unit1 read */ -+#define IFX_PMON_BIU1_WRITE_EVENT 0x07 /*!< Bus interface Unit1 write */ -+ -+#define IFX_PMON_EVENT_MIN IFX_PMON_EVENT_NONE -+ -+/* DMA */ -+#define IFX_PMON_DMA_READ_EVENT 0x0C /*!< DMA read */ -+#define IFX_PMON_DMA_WRITE_EVENT 0x0D /*!< DMA write */ -+#define IFX_PMON_DMA_RX_EVENT 0x0E /*!< DMA payload rx */ -+#define IFX_PMON_DMA_TX_EVENT 0x0F /*!< DMA payload tx */ -+ -+/* PPE, GPHY, ethernet */ -+#define IFX_PMON_FPI1S_READ_EVENT 0x14 /*!< FPI1 Slave bus read */ -+#define IFX_PMON_FPI1S_WRITE_EVENT 0x15 /*!< FPI1 Slave bus write */ -+ -+/* WLAN BB/MAC, CPU DMA */ -+#define IFX_PMON_AHB1S_READ_EVENT 0x18 /*!< AHB1 Slave bus read */ -+#define IFX_PMON_AHB1S_WRITE_EVENT 0x19 /*!< AHB1 Slave bus write */ -+ -+/* USB, DSL */ -+#define IFX_PMON_AHB2S_READ_EVENT 0x1C /*!< AHB2 Slave bus read */ -+#define IFX_PMON_AHB2S_WRITE_EVENT 0x1D /*!< AHB2 Slave bus write */ -+ -+/* PCIe */ -+#define IFX_PMON_AHB4S_READ_EVENT 0x20 /*!< AHB4 Slave bus read */ -+#define IFX_PMON_AHB4S_WRITE_EVENT 0x21 /*!< AHB4 Slave bus Write */ -+ -+/* DDR */ -+#define IFX_PMON_DDR_READ_EVENT 0x40 /*!< DDR single read */ -+#define IFX_PMON_DDR_WRITE_EVENT 0x41 /*!< DDR single write */ -+#define IFX_PMON_DDR_CMD_QUEUE_ALMOST_FULL 0x43 /*!< DDR Command Queue Almost Full */ -+#define IFX_PMON_DDR_CKE_STAT 0x44 /*!< DDR CKE status */ -+#define IFX_PMON_DDR_REFRESH_IN_PROGRESS 0x45 /*!< DDR Refresh in progress */ -+#define IFX_PMON_DDR_CONTROLLER_BUSY 0x46 /*!< DDR Controller Busy */ -+#define IFX_PMON_DDR_CMD_QUEUE_FULL 0x47 /*!< DDR Command Queue Full */ -+ -+/* SRAM */ -+#define IFX_PMON_SRAM_READ_EVENT 0x50 /*!< SRAM read */ -+#define IFX_PMON_SRAM_WRITE_EVENT 0x51 /*!< SRAM write */ -+ -+/* FPI2M */ -+#define IFX_PMON_FPI2M_READ_EVENT 0x58 /*!< FPI2 master read */ -+#define IFX_PMON_FPI2M_WRITE_EVENT 0x59 /*!< FPI2 master write */ -+ -+/* FPI3M */ -+#define IFX_PMON_FPI3M_READ_EVENT 0x5C /*!< FPI3 master read */ -+#define IFX_PMON_FPI3M_WRITE_EVENT 0x5D /*!< FPI3 master write */ -+ -+/* AHB3M */ -+#define IFX_PMON_AHB3M_READ_EVENT 0x60 /*!< AHB3 master read */ -+#define IFX_PMON_AHB3M_WRITE_EVENT 0x61 /*!< AHB3 master write */ -+ -+#define IFX_PMON_EVENT_MAX IFX_PMON_AHB3M_WRITE_EVENT -+#else -+#error "platform not supported" -+#endif -+ -+ -+#define IFX_PMON_XTC_COUNTER0 0 -+ -+#define IFX_PMON_XTC_COUNTER1 1 -+ -+#define IFX_PMON_MAX_PERF_CNT_PER_TC 2 -+ -+/* @} */ -+ -+/*! \enum IFX_MIPS_TC -+ \brief Multithread Index -+ */ -+enum IFX_MIPS_TC{ -+ IFX_MIPS_TC0 = 0, /*!< MT TC 0 */ -+ IFX_MIPS_TC1, /*!< MT TC 1 */ -+ IFX_MIPS_TC2, /*!< MT TC 2 */ -+ IFX_MIPS_TC3, /*!< MT TC 3 */ -+}; -+ -+/*! -+ \addtogroup IFX_PMON_IOCTL -+ */ -+/* @{ */ -+/*! -+ \brief Structure describing pmon version -+ */ -+struct ifx_pmon_ioctl_version { -+ unsigned int major; /*!< Version Major number */ -+ unsigned int mid; /*!< Version Mid number */ -+ unsigned int minor; /*!< Version Minor number */ -+}; -+ -+/*! -+ \brief Structure describing pmon event -+ */ -+struct ifx_pmon_ioctl_event { -+ unsigned int pmon_event; /*!< PMON external even id */ -+ unsigned int counter; /*!< CPU performance counter 0 or 1 */ -+ unsigned int tc; /*!< MT TC index 0~3*/ -+}; -+ -+/*! -+ * \def IFX_PMON_IOC_MAGIC -+ * \brief PMON IOCTL Magic number -+ */ -+#define IFX_PMON_IOC_MAGIC 0xef -+/*! -+ * \def IFX_PMON_IOC_VERSION -+ * \brief PMON IOCTL to get version number -+ */ -+#define IFX_PMON_IOC_VERSION _IOR( IFX_PMON_IOC_MAGIC, 0, struct ifx_pmon_ioctl_version) -+/*! -+ * \def IFX_PMON_IOC_EVENT -+ * \brief PMON IOCTL to configure external event and CPU performance counter 0/1 -+ */ -+#define IFX_PMON_IOC_EVENT _IOWR(IFX_PMON_IOC_MAGIC, 1, struct ifx_pmon_ioctl_event) -+/*! -+ * \def IFX_PMON_IOC_DISABLE -+ * \brief PMON IOCTL to disable PMON module -+ */ -+ -+#define IFX_PMON_IOC_DISABLE _IOWR(IFX_PMON_IOC_MAGIC, 2, int) -+/* @} */ -+ -+#endif /* IFX_PMON_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_pmu.h b/arch/mips/include/asm/ifx/ifx_pmu.h -new file mode 100644 -index 0000000..9f00195 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_pmu.h -@@ -0,0 +1,776 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_pmu.h -+** PROJECT : IFX UEIP -+** MODULES : PMU -+** -+** DATE : 28 May 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : IFX Cross-Platform Power Management Unit driver header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 28 May 2009 Lei Chuanhua The first UEIP release -+*******************************************************************************/ -+#ifndef IFX_PMU_H -+#define IFX_PMU_H -+ -+/*! -+ \defgroup IFX_PMU PMU driver module -+ \brief UEIP Project - PMU module. -+*/ -+ -+/*! -+ \defgroup IFX_PMU_DEFINITIONS Definition and structions -+ \ingroup IFX_PMU -+ \brief definitions for ifx pmu driver -+*/ -+ -+/*! -+ \file ifx_pmu.h -+ \ingroup IFX_PMU -+ \brief header file for PMU external interface -+*/ -+/*! -+ \addtogroup IFX_PMU_DEFINITIONS -+*/ -+/* @{ */ -+ -+/*! \def IFX_PMU_MODULE_USB0_PHY -+ \brief USB0 PHY Module -+ */ -+#define IFX_PMU_MODULE_USB0_PHY (0) -+ -+/*! \def IFX_PMU_MODULE_USB_PHY -+ \brief USB PHY Module -+ */ -+#define IFX_PMU_MODULE_USB_PHY IFX_PMU_MODULE_USB0_PHY -+ -+/*! \def IFX_PMU_MODULE_FPIS -+ \brief FPI Slave Module -+ */ -+#define IFX_PMU_MODULE_FPIS (1) -+ -+/*! \def IFX_PMU_MODULE_FPI1 -+ \brief FPI bus 1 Module -+ */ -+#define IFX_PMU_MODULE_FPI1 IFX_PMU_MODULE_FPIS -+ -+/*! \def IFX_PMU_MODULE_FPI2 -+ \brief FPI bus 2 Module -+ */ -+#define IFX_PMU_MODULE_FPI2 IFX_PMU_MODULE_FPI1 -+ -+/*! \def IFX_PMU_MODULE_DFEV0 -+ \brief DFEV 0 Module -+ */ -+#define IFX_PMU_MODULE_DFEV0 (2) -+#ifdef CONFIG_AMAZON_SE -+/*! \def IFX_PMU_MODULE_SDIO -+ \brief SDIO Module, ASE only -+ */ -+#define IFX_PMU_MODULE_SDIO IFX_PMU_MODULE_DFEV0 -+#endif -+/*! \def IFX_PMU_MODULE_DFEV1 -+ \brief DFEV 1 Module -+ */ -+#define IFX_PMU_MODULE_DFEV1 (3) -+ -+/*! \def IFX_PMU_MODULE_VO_MIPS -+ \brief Voice MIPS Module -+ */ -+#define IFX_PMU_MODULE_VO_MIPS IFX_PMU_MODULE_DFEV0 -+ -+/*! \def IFX_PMU_MODULE_VODEC -+ \brief Voice Decoder Module -+ */ -+#define IFX_PMU_MODULE_VODEC IFX_PMU_MODULE_DFEV1 -+ -+/*! \def IFX_PMU_MODULE_PCI -+ \brief PCI Module -+ */ -+#define IFX_PMU_MODULE_PCI (4) -+ -+/*! \def IFX_PMU_MODULE_DMA -+ \brief DMA Module -+ */ -+#define IFX_PMU_MODULE_DMA (5) -+ -+/*! \def IFX_PMU_MODULE_USB0_CTRL -+ \brief USB0 Controller Module -+ */ -+#define IFX_PMU_MODULE_USB0_CTRL (6) -+ -+/*! \def IFX_PMU_MODULE_USB_CTRL -+ \brief USB Controller Module -+ */ -+#define IFX_PMU_MODULE_USB_CTRL IFX_PMU_MODULE_USB0_CTRL -+ -+/*! \def IFX_PMU_MODULE_USIF -+ \brief USIF Module -+ */ -+#define IFX_PMU_MODULE_USIF (7) -+ -+/*! \def IFX_PMU_MODULE_UART0 -+ \brief UART0/ASC0 Module -+ */ -+#define IFX_PMU_MODULE_UART0 IFX_PMU_MODULE_USIF -+ -+/*! \def IFX_PMU_MODULE_EPHY -+ \brief EPHY Module -+ */ -+#define IFX_PMU_MODULE_EPHY IFX_PMU_MODULE_UART0 -+ -+/*! \def IFX_PMU_MODULE_SPI -+ \brief SSC/SPI Module -+ */ -+#define IFX_PMU_MODULE_SPI (8) -+ -+/*! \def IFX_PMU_MODULE_DSL_DFE -+ \brief DSL /DFE Module -+ */ -+#define IFX_PMU_MODULE_DSL_DFE (9) -+ -+/*! \def IFX_PMU_MODULE_EBU -+ \brief EBU Module -+ */ -+#define IFX_PMU_MODULE_EBU (10) -+ -+/*! \def IFX_PMU_MODULE_LEDC -+ \brief LEDc Controller Module -+ */ -+#define IFX_PMU_MODULE_LEDC (11) -+ -+/*! \def IFX_PMU_MODULE_GPTC -+ \brief GPTU Module -+ */ -+#define IFX_PMU_MODULE_GPTC (12) -+ -+/*! \def IFX_PMU_MODULE_AHBS -+ \brief AHB Slave Module -+ */ -+#define IFX_PMU_MODULE_AHBS (13) -+ -+/*! \def IFX_PMU_MODULE_PCIE1_PHY -+ \brief PCIe 1 PHY module -+ */ -+#define IFX_PMU_MODULE_PCIE1_PHY IFX_PMU_MODULE_AHBS -+ -+/*! \def IFX_PMU_MODULE_PPE_TPE -+ \brief PPE/TPE Module -+ */ -+#define IFX_PMU_MODULE_PPE_TPE IFX_PMU_MODULE_AHBS -+ -+/*! \def IFX_PMU_MODULE_VLYNQ -+ \brief VLYNQ Module -+ */ -+#define IFX_PMU_MODULE_VLYNQ IFX_PMU_MODULE_AHBS -+ -+/*! \def IFX_PMU_MODULE_FPIM -+ \brief FPI Master Module -+ */ -+#define IFX_PMU_MODULE_FPIM (14) -+ -+/*! \def IFX_PMU_MODULE_ADSL_AFE -+ \brief AR10 ADSL AFE Module -+ */ -+#define IFX_PMU_MODULE_ADSL_AFE IFX_PMU_MODULE_FPIM -+ -+/*! \def IFX_PMU_MODULE_FPI0 -+ \brief FPI bus 0 Module -+ */ -+#define IFX_PMU_MODULE_FPI0 IFX_PMU_MODULE_FPIM -+ -+/*! \def IFX_PMU_MODULE_AHBM -+ \brief AHB Master Module -+ */ -+#define IFX_PMU_MODULE_AHBM (15) -+ -+/*! \def IFX_PMU_MODULE_DCDC_2V5 -+ \brief AR10 DCDC 2.5V Module -+ */ -+#define IFX_PMU_MODULE_DCDC_2V5 IFX_PMU_MODULE_AHBM -+ -+/*! \def IFX_PMU_MODULE_AHB -+ \brief AHB Module -+ */ -+#define IFX_PMU_MODULE_AHB IFX_PMU_MODULE_AHBM -+#ifndef CONFIG_AMAZON_SE -+/*! \def IFX_PMU_MODULE_SDIO -+ \brief SDIO Module, ARX,Danube, VRX -+ */ -+#define IFX_PMU_MODULE_SDIO (16) -+#endif -+/*! \def IFX_PMU_MODULE_UART1 -+ \brief UART1/ASC1 module -+ */ -+#define IFX_PMU_MODULE_UART1 (17) -+ -+/*! \def IFX_PMU_MODULE_PPE_QSB -+ \brief PPE QSB module -+ */ -+#define IFX_PMU_MODULE_PPE_QSB (18) -+ -+/*! \def IFX_PMU_MODULE_DCDC_1VX -+ \brief AR10 DCDC 1.5V and 1.8V Module -+ */ -+#define IFX_PMU_MODULE_DCDC_1VX IFX_PMU_MODULE_PPE_QSB -+ -+/*! \def IFX_PMU_MODULE_PPE_SLL01 -+ \brief PPE SLL01 module -+ */ -+#define IFX_PMU_MODULE_PPE_SLL01 (19) -+ -+/*! \def IFX_PMU_MODULE_DCDC_1V0 -+ \brief AR10 DCDC 1.0V Module -+ */ -+#define IFX_PMU_MODULE_DCDC_1V0 IFX_PMU_MODULE_PPE_SLL01 -+ -+/*! \def IFX_PMU_MODULE_WDT0 -+ \brief WDT0 module -+ */ -+#define IFX_PMU_MODULE_WDT0 IFX_PMU_MODULE_PPE_QSB -+ -+/*! \def IFX_PMU_MODULE_WDT1 -+ \brief WDT1 module -+ */ -+#define IFX_PMU_MODULE_WDT1 IFX_PMU_MODULE_PPE_SLL01 -+ -+/*! \def IFX_PMU_MODULE_DEU -+ \brief DEU module -+ */ -+#define IFX_PMU_MODULE_DEU (20) -+ -+/*! \def IFX_PMU_MODULE_PPE_TC -+ \brief PPE TC module -+ */ -+#define IFX_PMU_MODULE_PPE_TC (21) -+ -+/*! \def IFX_PMU_MODULE_PPE_EMA -+ \brief PPE EMA module -+ */ -+#define IFX_PMU_MODULE_PPE_EMA (22) -+ -+/*! \def IFX_PMU_MODULE_PPE_ENET1 -+ \brief PPE ENET1 module -+ */ -+#define IFX_PMU_MODULE_PPE_ENET1 IFX_PMU_MODULE_PPE_EMA -+ -+/*! \def IFX_PMU_MODULE_PPE_DPLUSM -+ \brief Dplus Master module -+ */ -+#define IFX_PMU_MODULE_PPE_DPLUSM (23) -+ -+/*! \def IFX_PMU_MODULE_PPE_DPLUS -+ \brief Dplus module -+ */ -+#define IFX_PMU_MODULE_PPE_DPLUS IFX_PMU_MODULE_PPE_DPLUSM -+ -+/*! \def IFX_PMU_MODULE_PPE_ENET0 -+ \brief PPE ENET0 module -+ */ -+#define IFX_PMU_MODULE_PPE_ENET0 IFX_PMU_MODULE_PPE_DPLUSM -+ -+/*! \def IFX_PMU_MODULE_PPE_DPLUSS -+ \brief Dplus Slave module -+ */ -+#define IFX_PMU_MODULE_PPE_DPLUSS (24) -+ -+/*! \def IFX_PMU_MODULE_DDR_MEM -+ \brief DDR MC module -+ */ -+#define IFX_PMU_MODULE_DDR_MEM IFX_PMU_MODULE_PPE_DPLUSS -+ -+/*! \def IFX_PMU_MODULE_TDM -+ \brief TDM module -+ */ -+#define IFX_PMU_MODULE_TDM (25) -+ -+/*! \def IFX_PMU_MODULE_USB1_PHY -+ \brief USB 1 PHY module -+ */ -+#define IFX_PMU_MODULE_USB1_PHY (26) -+ -+/*! \def IFX_PMU_MODULE_USB1_CTRL -+ \brief USB1 Controller module -+ */ -+#define IFX_PMU_MODULE_USB1_CTRL (27) -+ -+/*! \def IFX_PMU_MODULE_SWITCH -+ \brief Switch module -+ */ -+#define IFX_PMU_MODULE_SWITCH (28) -+ -+/*! \def IFX_PMU_MODULE_PPE_TOP -+ \brief PPE Top module -+ */ -+#define IFX_PMU_MODULE_PPE_TOP (29) -+ -+/*! \def IFX_PMU_MODULE_DDR_DPD -+ \brief DDR DPD module -+ */ -+#define IFX_PMU_MODULE_DDR_DPD IFX_PMU_MODULE_PPE_TOP -+ -+/*! \def IFX_PMU_MODULE_GPHY0 -+ \brief GPHY0 module -+ */ -+#define IFX_PMU_MODULE_GPHY0 IFX_PMU_MODULE_PPE_TOP -+ -+ -+/*! \def IFX_PMU_MODULE_GPHY -+ \brief Internal GPHY module -+ */ -+#define IFX_PMU_MODULE_GPHY (30) -+ -+/*! \def IFX_PMU_MODULE_GPHY1 -+ \brief Internal GPHY1 module -+ */ -+#define IFX_PMU_MODULE_GPHY1 IFX_PMU_MODULE_GPHY -+ -+/*! \def IFX_PMU_MODULE_PCIE_L0_CLK -+ \brief PCIe L0 Clock module -+ */ -+#define IFX_PMU_MODULE_PCIE_L0_CLK (31) -+ -+/*! \def IFX_PMU_MODULE_GPHY2 -+ \brief Internal GPHY2 module -+ */ -+#define IFX_PMU_MODULE_GPHY2 IFX_PMU_MODULE_PCIE_L0_CLK -+ -+/*! \def IFX_PMU_MODULE_PCIE_PHY -+ \brief PCIe PHY module -+ */ -+#define IFX_PMU_MODULE_PCIE_PHY (32) -+ -+/*! \def IFX_PMU_MODULE_PCIE0_PHY -+ \brief PCIe 0 PHY module -+ */ -+#define IFX_PMU_MODULE_PCIE0_PHY IFX_PMU_MODULE_PCIE_PHY -+ -+/*! \def IFX_PMU_MODULE_PCIE_CTRL -+ \brief PCIe Controller module -+ */ -+#define IFX_PMU_MODULE_PCIE_CTRL (33) -+ -+/*! \def IFX_PMU_MODULE_PCIE0_CTRL -+ \brief PCIe Controller 0 module -+ */ -+#define IFX_PMU_MODULE_PCIE0_CTRL IFX_PMU_MODULE_PCIE_CTRL -+ -+/*! \def IFX_PMU_MODULE_AHB_ARC -+ \brief AHB ARC module -+ */ -+#define IFX_PMU_MODULE_AHB_ARC (34) /* XXX */ -+ -+/*! \def IFX_PMU_MODULE_PCIE1_CTRL -+ \brief PCIe Controller 1 module -+ */ -+#define IFX_PMU_MODULE_PCIE1_CTRL IFX_PMU_MODULE_AHB_ARC -+ -+/*! \def IFX_PMU_MODULE_HSNAND -+ \brief High Speed NAND module -+ */ -+#define IFX_PMU_MODULE_HSNAND (35) /* XXX */ -+ -+/*! \def IFX_PMU_MODULE_PDI1 -+ \brief PCIe PDI 1 module -+ */ -+#define IFX_PMU_MODULE_PDI1 IFX_PMU_MODULE_HSNAND -+ -+ -+/*! \def IFX_PMU_MODULE_PDI -+ \brief PDI module -+ */ -+#define IFX_PMU_MODULE_PDI (36) -+ -+/*! \def IFX_PMU_MODULE_PDI0 -+ \brief PCIe PDI module -+ */ -+#define IFX_PMU_MODULE_PDI0 IFX_PMU_MODULE_PDI -+ -+/*! \def IFX_PMU_MODULE_MSI -+ \brief PCIe MSI module -+ */ -+#define IFX_PMU_MODULE_MSI (37) -+ -+/*! \def IFX_PMU_MODULE_MSI0 -+ \brief PCIe MSI 0 module -+ */ -+#define IFX_PMU_MODULE_MSI0 IFX_PMU_MODULE_MSI -+ -+/*! \def IFX_PMU_MODULE_DDR_CKE -+ \brief DDR CKE module -+ */ -+#define IFX_PMU_MODULE_DDR_CKE (38) -+ -+ -+/*! \def IFX_PMU_MODULE_MSI1 -+ \brief PCIe MSI 1 module -+ */ -+#define IFX_PMU_MODULE_MSI1 (39) -+ -+/* Will be exported to user space, __ prefix is used, see linux/types.h */ -+typedef struct ifx_pmu_clk { -+ __u32 module; /* Clok module index */ -+ __u32 enable; /* enable or disable */ -+} ifx_pmu_clk_t; -+ -+/* Used by ioctl */ -+#define IFX_PMU_IOC_MAGIC 0xe0 -+ -+#define IFX_PMU_IOC_CLK_ENABLE (1) -+#define IFX_PMU_IOC_CLK_DISABLE (2) -+#define IFX_PMU_IOC_CLK_GET (3) -+ -+#define IFX_PMU_IOC_CLK_GATING_ENABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_ENABLE ,ifx_pmu_clk_t) -+#define IFX_PMU_IOC_CLK_GATING_DISABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_DISABLE ,ifx_pmu_clk_t) -+#define IFX_PMU_IOC_GET_CLK_GATING _IOR(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_CLK_GET ,ifx_pmu_clk_t) -+ -+ -+#ifdef CONFIG_IFX_PMU_POWER_GATING -+ -+/* -+ * Power Gating Power domain Index definition -+ * The underlying power domain continues to evolve and change. To maintain the -+ * forward compatibiblity with future hardware platforms. Index is better. -+ * However, every new platform has to maintain one index-to-power domain table. -+ */ -+ -+/*! \def IFX_PMU_PG_DOMAIN_USB -+ \brief USB power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_USB 0 -+ -+/*! \def IFX_PMU_PG_DOMAIN_PCIE -+ \brief PCI express power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_PCIE 1 -+ -+/*! \def IFX_PMU_PG_DOMAIN_PCIE -+ \brief SLIC plus TDM power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_SLIC_TDM 2 -+ -+/*! \def IFX_PMU_PG_DOMAIN_DEU -+ \brief DEU power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_DEU 3 -+ -+/*! \def IFX_PMU_PG_DOMAIN_FPI_TOP -+ \brief FPI Top power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_FPI_TOP 4 -+ -+/*! \def IFX_PMU_PG_DOMAIN_PPE -+ \brief PPE power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_PPE 5 -+ -+/*! \def IFX_PMU_PG_DOMAIN_SWITCH -+ \brief Switch power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_SWITCH 6 -+ -+/*! \def IFX_PMU_PG_DOMAIN_MIPS -+ \brief MIPS Core power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_MIPS 7 -+ -+/*! \def IFX_PMU_PG_DOMAIN_DSL_DFE -+ \brief DSL DFE power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_DSL_DFE 8 -+ -+/*! \def IFX_PMU_PG_DOMAIN_WLAN -+ \brief Built-in WiFi power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_WLAN 9 -+ -+/*! \def IFX_PMU_PG_DOMAIN_GPHY0 -+ \brief Giga bit PHY0 power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_GPHY0 10 -+ -+/*! \def IFX_PMU_PG_DOMAIN_GPHY1 -+ \brief Giga bit PHY1 power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_GPHY1 11 -+ -+/*! \def IFX_PMU_PG_DOMAIN_GPHY2 -+ \brief Giga bit PHY2 power domain -+ */ -+#define IFX_PMU_PG_DOMAIN_GPHY2 12 -+ -+#define IFX_PMU_PG_DOMAIN_RES0 13 -+#define IFX_PMU_PG_DOMAIN_RES1 14 -+#define IFX_PMU_PG_DOMAIN_RES2 15 -+ -+/* XXX, more definition */ -+ -+#define IFX_POWER_DOMAIN(X) IFX_PMU_PG_DOMAIN_##X -+ -+/* Will be exported to user space, __ prefix is used, see linux/types.h */ -+typedef struct ifx_pmu_pg { -+ __u32 power_domain; /* Power Domain index */ -+ __u32 flags; /* Future use */ -+} ifx_pmu_pg_t; -+ -+ -+/* XXX, don't overlap with Clock Gating */ -+#define IFX_PMU_IOC_PG_ENABLE (60) -+#define IFX_PMU_IOC_PG_DISABLE (61) -+#define IFX_PMU_IOC_PG_GET (62) -+ -+#define IFX_PMU_IOC_POWER_GATING_ENABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_ENABLE ,ifx_pmu_pg_t) -+#define IFX_PMU_IOC_POWER_GATING_DISABLE _IOW(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_DISABLE ,ifx_pmu_pg_t) -+#define IFX_PMU_IOC_GET_POWER_GATING _IOR(IFX_PMU_IOC_MAGIC, IFX_PMU_IOC_PG_GET ,ifx_pmu_pg_t) -+ -+#endif /* CONFIG_IFX_PMU_POWER_GATING */ -+/* @} */ -+ -+#ifdef __KERNEL__ -+ -+#define IFX_PMU_ENABLE 1 -+#define IFX_PMU_DISABLE 0 -+ -+#define USB0_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB0_PHY, (__x)) -+#define USB_PHY_PMU_SETUP(__x) USB0_PHY_PMU_SETUP((__x)) -+#define FPIS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_FPIS, (__x)) -+#define FPI1_PMU_SETUP(__x) FPIS_PMU_SETUP((__x)) -+#define FPI2_PMU_SETUP(__x) FPIS_PMU_SETUP((__x)) -+#define DFEV0_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DFEV0, (__x)) -+#ifdef CONFIG_AMAZON_SE -+#define SDIO_PMU_SETUP(__x) DFEV0_PMU_SETUP((__x)) -+#endif -+#define DFEV1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DFEV1, (__x)) -+#define VO_MIPS_PMU_SETUP(__x) DFEV0_PMU_SETUP((__x)) -+#define VODEC_PMU_SETUP(__x) DFEV1_PMU_SETUP((__x)) -+#define PCI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCI, (__x)) -+#define DMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DMA, (__x)) -+#define USB0_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB0_CTRL, (__x)) -+#define USIF_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USIF, (__x)) -+#define UART0_PMU_SETUP(__x) USIF_PMU_SETUP((__x)) -+#define EPHY_PMU_SETUP(__x) USIF_PMU_SETUP((__x)) -+#define SPI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SPI, (__x)) -+#define DSL_DFE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DSL_DFE, (__x)) -+#define EBU_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_EBU, (__x)) -+#define LEDC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_LEDC, (__x)) -+#define GPTC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_GPTC, (__x)) -+ -+#define AHBS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBS, (__x)) -+#define VLYNQ_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) -+#define PPE_TPE_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) -+#define PCIE1_PHY_PMU_SETUP(__x) AHBS_PMU_SETUP((__x)) -+ -+#define FPIM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_FPIM, (__x)) -+#define FPI0_PMU_SETUP(__x) FPIM_PMU_SETUP((__x)) -+#define ADSL_AFE_PMU_SETUP(__x) FPIM_PMU_SETUP((__x)) -+ -+#define AHBM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHBM, (__x)) -+#define AHB_PMU_SETUP(__x) AHBM_PMU_SETUP((__x)) -+#define DCDC_2V5_PMU_SETUP(__x) AHBM_PMU_SETUP((__x)) -+ -+#ifndef CONFIG_AMAZON_SE -+#define SDIO_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SDIO, (__x)) -+#endif -+#define UART1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_UART1, (__x)) -+#define PPE_QSB_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_QSB, (__x)) -+#define WDT0_PMU_SETUP(__x) PPE_QSB_PMU_SETUP((__x)) -+#define DCDC_1VX_PMU_SETUP(__x) PPE_QSB_PMU_SETUP((__x)) -+ -+#define PPE_SLL01_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_SLL01, (__x)) -+#define DCDC_1V0_PMU_SETUP(__x) PPE_SLL01_PMU_SETUP((__x)) -+ -+#define WDT1_PMU_SETUP(__x) PPE_SLL01_PMU_SETUP((__x)) -+#define DEU_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DEU, (__x)) -+#define PPE_TC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TC, (__x)) -+#define PPE_EMA_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_EMA, (__x)) -+#define PPE_ENET1_PMU_SETUP(__x) PPE_EMA_PMU_SETUP((__x)) -+#define PPE_DPLUSM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_DPLUSM, (__x)) -+#define PPE_DPLUS_PMU_SETUP(__x) PPE_DPLUSM_PMU_SETUP((__x)) -+#define PPE_ENET0_PMU_SETUP(__x) PPE_DPLUS_PMU_SETUP((__x)) -+#define PPE_DPLUSS_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_DPLUSS, (__x)) -+#define DDR_MEM_PMU_SETUP(__x) PPE_DPLUSS_PMU_SETUP((__x)) -+#define TDM_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_TDM, (__x)) -+#define USB1_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB1_PHY, (__x)) -+#define USB1_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_USB1_CTRL, (__x)) -+#define SWITCH_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_SWITCH, (__x)) -+ -+#define PPE_TOP_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PPE_TOP, (__x)) -+#define GPHY0_PMU_SETUP(__x) PPE_TOP_PMU_SETUP((__x)) -+#define DDR_DPD_PMU_SETUP(__x) PPE_TOP_PMU_SETUP((__x)) -+ -+#define GPHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_GPHY, (__x)) -+#define GPHY1_PMU_SETUP(__x) GPHY_PMU_SETUP((__x)) -+ -+#define PCIE_L0_CLK_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_L0_CLK, (__x)) -+#define GPHY2_PMU_SETUP(__x) PCIE_L0_CLK_PMU_SETUP((__x)) -+ -+#define PCIE_PHY_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_PHY, (__x)) -+#define PCIE0_PHY_PMU_SETUP(__x) PCIE_PHY_PMU_SETUP((__x)) -+ -+#define PCIE_CTRL_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PCIE_CTRL, (__x)) -+#define PCIE0_CTRL_PMU_SETUP(__x) PCIE_CTRL_PMU_SETUP((__x)) -+ -+#define AHB_ARC_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_AHB_ARC, (__x)) -+#define PCIE1_CTRL_PMU_SETUP(__x) AHB_ARC_PMU_SETUP((__x)) -+ -+#define HSNAND_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_HSNAND, (__x)) -+#define PDI1_PMU_SETUP(__x) HSNAND_PMU_SETUP((__x)) -+ -+#define PDI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_PDI, (__x)) -+#define PDI0_PMU_SETUP(__x) PDI_PMU_SETUP((__x)) -+ -+#define MSI_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_MSI, (__x)) -+#define MSI0_PMU_SETUP(__x) MSI_PMU_SETUP((__x)) -+ -+#define DDR_CKE_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_DDR_CKE, (__x)) -+ -+#define MSI1_PMU_SETUP(__x) ifx_pmu_set(IFX_PMU_MODULE_MSI1, (__x)) -+ -+#ifndef ifx_pmu_set -+extern int ifx_pmu_set(int module, int value); -+#endif -+extern void ifx_pmu_enable_all_modules(void); -+extern void ifx_pmu_disable_all_modules(void); -+#ifdef CONFIG_IFX_PMU_POWER_GATING -+extern int ifx_pmu_pg_enable(ifx_pmu_pg_t *pg); -+extern void ifx_pmu_pg_enable_all_domains(void); -+extern void ifx_pmu_pg_disable_all_domains(void); -+extern int ifx_pmu_pg_disable(ifx_pmu_pg_t *pg); -+extern int ifx_pmu_pg_mips_enable(void); -+extern int ifx_pmu_pg_mips_disable(void); -+extern int ifx_pmu_pg_usb_enable(void); -+extern int ifx_pmu_pg_usb_disable(void); -+extern int ifx_pmu_pg_pcie_enable(void); -+extern int ifx_pmu_pg_pcie_disable(void); -+extern int ifx_pmu_pg_switch_enable(void); -+extern int ifx_pmu_pg_switch_disable(void); -+extern int ifx_pmu_pg_deu_enable(void); -+extern int ifx_pmu_pg_deu_disable(void); -+extern int ifx_pmu_pg_ppe_enable(void); -+extern int ifx_pmu_pg_ppe_disable(void); -+extern int ifx_pmu_pg_dsl_dfe_enable(void); -+extern int ifx_pmu_pg_dsl_dfe_disable(void); -+extern int ifx_pmu_pg_fpi_top_enable(void); -+extern int ifx_pmu_pg_fpi_top_disable(void); -+extern int ifx_pmu_pg_slic_tdm_enable(void); -+extern int ifx_pmu_pg_slic_tdm_disable(void); -+extern int ifx_pmu_pg_wkup_loc_setup(void *loc); -+#else -+static inline void ifx_pmu_pg_enable_all_domains(void) -+{ -+} -+ -+static inline void ifx_pmu_pg_disable_all_domains(void) -+{ -+} -+ -+static inline int ifx_pmu_pg_mips_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_mips_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_usb_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_usb_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_pcie_enable(void) -+{ -+ return 0; -+ -+} -+ -+static inline int ifx_pmu_pg_pcie_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_switch_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_switch_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_deu_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_deu_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_ppe_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_ppe_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_dsl_dfe_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_dsl_dfe_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_fpi_top_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_fpi_top_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_slic_tdm_enable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_slic_tdm_disable(void) -+{ -+ return 0; -+} -+ -+static inline int ifx_pmu_pg_wkup_loc_setup(void *loc) -+{ -+ return 0; -+} -+#endif /* CONFIG_IFX_PMU_POWER_GATING */ -+ -+#endif /* __KERNEL__ */ -+#endif /* IFX_PMU_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_ptm.h b/arch/mips/include/asm/ifx/ifx_ptm.h -new file mode 100644 -index 0000000..698e5c3 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_ptm.h -@@ -0,0 +1,203 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ptm.h -+** PROJECT : UEIP -+** MODULES : PTM -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global PTM driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 07 JUL 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_PTM_H -+#define IFX_PTM_H -+ -+ -+ -+/*! -+ \defgroup IFX_PTM UEIP Project - PTM driver module -+ \brief UEIP Project - PTM driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_IOCTL IOCTL Commands -+ \ingroup IFX_PTM -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_PTM_STRUCT Structures -+ \ingroup IFX_PTM -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_ptm.h -+ \ingroup IFX_PTM -+ \brief PTM driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_PTM_IOCTL -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Command -+ */ -+/*! -+ \brief PTM IOCTL Command - Get codeword MIB counters. -+ -+ This command uses structure "PTM_CW_IF_ENTRY_T" to get codeword level MIB counters. -+ */ -+#define IFX_PTM_MIB_CW_GET SIOCDEVPRIVATE + 1 -+/*! -+ \brief PTM IOCTL Command - Get packet MIB counters. -+ -+ This command uses structure "PTM_FRAME_MIB_T" to get packet level MIB counters. -+ */ -+#define IFX_PTM_MIB_FRAME_GET SIOCDEVPRIVATE + 2 -+/*! -+ \brief PTM IOCTL Command - Get firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to get firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_GET SIOCDEVPRIVATE + 3 -+/*! -+ \brief PTM IOCTL Command - Set firmware configuration (CRC). -+ -+ This command uses structure "IFX_PTM_CFG_T" to set firmware configuration (CRC). -+ */ -+#define IFX_PTM_CFG_SET SIOCDEVPRIVATE + 4 -+/*! -+ \brief PTM IOCTL Command - Program priority value to TX queue mapping. -+ -+ This command uses structure "IFX_PTM_PRIO_Q_MAP_T" to program priority value to TX queue mapping. -+ */ -+#define IFX_PTM_MAP_PKT_PRIO_TO_Q SIOCDEVPRIVATE + 14 -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_PTM_STRUCT -+ */ -+/*@{*/ -+ -+/* -+ * ioctl Data Type -+ */ -+ -+/*! -+ \typedef PTM_CW_IF_ENTRY_T -+ \brief Wrapping of structure "ptm_cw_ifEntry_t". -+ */ -+/*! -+ \struct ptm_cw_ifEntry_t -+ \brief Structure used for CodeWord level MIB counters. -+ */ -+typedef struct ptm_cw_ifEntry_t { -+ uint32_t ifRxNoIdleCodewords; /*!< output, number of ingress user codeword */ -+ uint32_t ifRxIdleCodewords; /*!< output, number of ingress idle codeword */ -+ uint32_t ifRxCodingViolation; /*!< output, number of error ingress codeword */ -+ uint32_t ifTxNoIdleCodewords; /*!< output, number of egress user codeword */ -+ uint32_t ifTxIdleCodewords; /*!< output, number of egress idle codeword */ -+} PTM_CW_IF_ENTRY_T; -+ -+/*! -+ \typedef PTM_FRAME_MIB_T -+ \brief Wrapping of structure "ptm_frame_mib_t". -+ */ -+/*! -+ \struct ptm_frame_mib_t -+ \brief Structure used for packet level MIB counters. -+ */ -+typedef struct ptm_frame_mib_t { -+ uint32_t RxCorrect; /*!< output, number of ingress packet */ -+ uint32_t TC_CrcError; /*!< output, number of egress packet with CRC error */ -+ uint32_t RxDropped; /*!< output, number of dropped ingress packet */ -+ uint32_t TxSend; /*!< output, number of egress packet */ -+} PTM_FRAME_MIB_T; -+ -+/*! -+ \typedef IFX_PTM_CFG_T -+ \brief Wrapping of structure "ptm_cfg_t". -+ */ -+/*! -+ \struct ptm_cfg_t -+ \brief Structure used for ETH/TC CRC configuration. -+ */ -+typedef struct ptm_cfg_t { -+ uint32_t RxEthCrcPresent; /*!< input/output, ingress packet has ETH CRC */ -+ uint32_t RxEthCrcCheck; /*!< input/output, check ETH CRC of ingress packet */ -+ uint32_t RxTcCrcCheck; /*!< input/output, check TC CRC of ingress codeword */ -+ uint32_t RxTcCrcLen; /*!< input/output, length of TC CRC of ingress codeword */ -+ uint32_t TxEthCrcGen; /*!< input/output, generate ETH CRC for egress packet */ -+ uint32_t TxTcCrcGen; /*!< input/output, generate TC CRC for egress codeword */ -+ uint32_t TxTcCrcLen; /*!< input/output, length of TC CRC of egress codeword */ -+} IFX_PTM_CFG_T; -+ -+/*! -+ \typedef IFX_PTM_PRIO_Q_MAP_T -+ \brief Wrapping of structure "ppe_prio_q_map". -+ */ -+/*! -+ \struct ppe_prio_q_map -+ \brief Structure used for Priority Value to TX Queue mapping. -+ */ -+typedef struct ppe_prio_q_map { -+ int pkt_prio; -+ int qid; -+ int vpi; // ignored in eth interface -+ int vci; // ignored in eth interface -+} IFX_PTM_PRIO_Q_MAP_T; -+ -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+struct port_cell_info { -+ unsigned int port_num; -+ unsigned int tx_link_rate[2]; -+}; -+#endif -+ -+ -+ -+#endif // IFX_PTM_H -+ -diff --git a/arch/mips/include/asm/ifx/ifx_rcu.h b/arch/mips/include/asm/ifx/ifx_rcu.h -new file mode 100644 -index 0000000..d2dbafd ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_rcu.h -@@ -0,0 +1,298 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_rcu.h -+** PROJECT : UEIP -+** MODULES : RCU (Reset Control Unit) -+** -+** DATE : 17 Jun 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global RCU driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 17 JUN 2009 Xu Liang Init Version -+*******************************************************************************/ -+ -+#ifndef IFX_RCU_H -+#define IFX_RCU_H -+ -+ -+ -+/*! -+ \defgroup IFX_RCU UEIP Project - RCU (Reset) driver module -+ \brief UEIP Project - RCU (Reset) driver module, support Danube, Amazon-SE, AR9, VR9. -+ */ -+ -+/*! -+ \defgroup IFX_RCU_API APIs -+ \ingroup IFX_RCU -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_RCU_IOCTL IOCTL Commands -+ \ingroup IFX_RCU -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_RCU_STRUCT Structures -+ \ingroup IFX_RCU -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \file ifx_rcu.h -+ \ingroup IFX_RCU -+ \brief RCU driver header file -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+#if defined(CONFIG_HN1) -+ -+enum { -+ IFX_RCU_DOMAIN_HRST = 0, // HRST output (0: RD0) -+ IFX_RCU_DOMAIN_CPU0, // Main CPU (1: RD1) -+ IFX_RCU_DOMAIN_FPI, // FPI bus (2: RD2) -+ IFX_RCU_DOMAIN_DLLCORE, // HN DLL Core (3: RD3) -+ IFX_RCU_DOMAIN_I2C, // I2C (4: RD4) -+ IFX_RCU_DOMAIN_AHB, // AHB bus (5: RD6) -+ IFX_RCU_DOMAIN_BULKSRAM, // BULK SRAM (6: RD7) -+ IFX_RCU_DOMAIN_I2S, // I2S module (7: RD8) -+ IFX_RCU_DOMAIN_DMA, // DMA module (8: RD9) -+ IFX_RCU_DOMAIN_SDIO, // SDIO module (9: RD10) -+ IFX_RCU_DOMAIN_PHYCORE, // PHY CORE (10:RD11) -+ IFX_RCU_DOMAIN_PCIEPHY, // PCIE PHY (12:RD12) -+ IFX_RCU_DOMAIN_MC, // Memory Controller module (13:RD14) -+ IFX_RCU_DOMAIN_HSNAND, // HSNAND (14:RD16) -+ IFX_RCU_DOMAIN_TDM, // TDM interface (Voice) (15:RD19) -+ IFX_RCU_DOMAIN_SW, // ETHERNET SWITCH (16:RD21) -+ IFX_RCU_DOMAIN_PCIE, // PCIE PART (17:RD22) -+ IFX_RCU_DOMAIN_AHBDLL, // AHB DLL (18:RD23) -+ IFX_RCU_DOMAIN_GPHY0, // GPHY0 (19: RD31) -+ // add more component in the future -+ IFX_RCU_DOMAIN_MAX, -+}; -+ -+#define IFX_RCU_DECLARE_DOMAIN_NAME(var) \ -+ char *var[] = { \ -+ "HRST", \ -+ "Main CPU", \ -+ "FPI bus", \ -+ "DLL Core", \ -+ "I2C", \ -+ "AHB bus", \ -+ "BULK SRAM", \ -+ "I2S", \ -+ "DMA", \ -+ "SDIO", \ -+ "PHY CORE", \ -+ "PCIE PHY", \ -+ "Memory Controller", \ -+ "High Speed NAND", \ -+ "TDM interface", \ -+ "Internal Switch", \ -+ "PCIE", \ -+ "AHB DLL", \ -+ "GPHY0", \ -+ } -+ -+#else -+ -+enum { -+ IFX_RCU_DOMAIN_HRST = 0, -+ IFX_RCU_DOMAIN_CPU0, // Main CPU -+ IFX_RCU_DOMAIN_FPI, // FPI bus -+ IFX_RCU_DOMAIN_DSLDSP, // DSL DSP -+ IFX_RCU_DOMAIN_USB1, // USB1 & PHY -+ IFX_RCU_DOMAIN_USB0, // USB0 & PHY -+ IFX_RCU_DOMAIN_ETHMAC1, // 2nd Ethernet MAC (Danube Only) -+ IFX_RCU_DOMAIN_AHB, // AHB bus -+ IFX_RCU_DOMAIN_DSLDFE, // DSL DFE -+ IFX_RCU_DOMAIN_PPE, // PPE module -+ IFX_RCU_DOMAIN_DMA, // DMA module -+ IFX_RCU_DOMAIN_SDIO, // SDIO module -+ IFX_RCU_DOMAIN_DSLAFE, // DSL AFE -+ IFX_RCU_DOMAIN_VOICE, // Voice DFE/AFE -+ IFX_RCU_DOMAIN_PCI, // PCI bus -+ IFX_RCU_DOMAIN_MC, // Memory Controller module -+ IFX_RCU_DOMAIN_SW, // Internal Switch -+ IFX_RCU_DOMAIN_TDM, // TDM interface (Voice) -+ IFX_RCU_DOMAIN_DSLTC, // (ATM) TC module in PPE -+ IFX_RCU_DOMAIN_CPU1, // 2nd CPU (Danube only) -+ IFX_RCU_DOMAIN_EPHY, // EPHY (Amazon-SE only) -+ IFX_RCU_DOMAIN_GPHY0, // GPHY0 (VR9 only) -+ IFX_RCU_DOMAIN_GPHY1, // GPHY1 (VR9 only) -+ IFX_RCU_DOMAIN_ARC, // ARC (DSL DSP) -+ IFX_RCU_DOMAIN_PCIE_PHY, // PCIexpress PHY (VR9 only) -+ IFX_RCU_DOMAIN_PCIE, // PCIexpress core (VR9 only) -+ IFX_RCU_DOMAIN_HSNAND, // High Speed NAND Flash Interface (VR9 only) -+ // add more component in the future -+ IFX_RCU_DOMAIN_MAX, -+}; -+ -+#define IFX_RCU_DECLARE_DOMAIN_NAME(var) \ -+ char *var[] = { \ -+ "HRST", \ -+ "Main CPU", \ -+ "FPI bus", \ -+ "DSL DSP", \ -+ "USB1 & PHY", \ -+ "USB0 & PHY", \ -+ "2nd MAC", \ -+ "AHB bus", \ -+ "DSL DFE", \ -+ "PPE", \ -+ "DMA", \ -+ "SDIO", \ -+ "DSL AFE", \ -+ "Voice DFE/AFE", \ -+ "PCI bus", \ -+ "Memory Controller", \ -+ "Internal Switch", \ -+ "TDM interface", \ -+ "DSL TC", \ -+ "2nd CPU", \ -+ "EPHY", \ -+ "GPHY0", \ -+ "GPHY1", \ -+ "ARC", \ -+ "PCIe PHY", \ -+ "PCIe core", \ -+ "High Speed NAND", \ -+ } -+ -+#endif -+ -+enum { -+ IFX_RCU_MODULE_USB, -+ IFX_RCU_MODULE_ETH, -+ IFX_RCU_MODULE_ATM, -+ IFX_RCU_MODULE_PTM, -+ IFX_RCU_MODULE_PPA, -+ IFX_RCU_MODULE_DMA, -+ IFX_RCU_MODULE_SDIO, -+ IFX_RCU_MODULE_MEI, -+ IFX_RCU_MODULE_TAPI, -+ IFX_RCU_MODULE_PCI, -+ IFX_RCU_MODULE_NAND, -+ // add more component in the future -+ IFX_RCU_MODULE_MAX, -+}; -+ -+#define IFX_RCU_DECLARE_MODULE_NAME(var) \ -+ char *var[] = { \ -+ "USB", \ -+ "ETH", \ -+ "ATM", \ -+ "PTM", \ -+ "PPA", \ -+ "DMA", \ -+ "SDIO", \ -+ "MEI", \ -+ "TAPI", \ -+ "PCI", \ -+ "NAND", \ -+ } -+ -+typedef int (*ifx_rcu_callbackfn)(unsigned int reset_domain_id, unsigned int module_id, int f_after_reset, unsigned long arg); -+ -+ -+ -+/* -+ * #################################### -+ * IOCTL -+ * #################################### -+ */ -+ -+/*! -+ \addtogroup IFX_RCU_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_rcu_ioctl_version -+ \brief Structure used for query of driver version. -+ */ -+struct ifx_rcu_ioctl_version { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+}; -+ -+/*! -+ \struct ifx_rcu_ioctl_query_rst_domain -+ \brief Structure used to get reset status of given hardware module. -+ */ -+struct ifx_rcu_ioctl_query_rst_domain { -+ unsigned int domain_id; /*!< input, hardware module ID */ -+ int f_reset; /*!< output, reset status */ -+}; -+ -+/*@}*/ -+ -+ -+/*! -+ \addtogroup IFX_RCU_IOCTL -+ */ -+/*@{*/ -+#define IFX_RCU_IOC_MAGIC 0xe0 -+/*! -+ \def IFX_RCU_IOC_VERSION -+ \brief RCU IOCTL Command - Get driver version number. -+ -+ This command uses struct "ifx_rcu_ioctl_version" as parameter to RCU driver version number. -+ */ -+#define IFX_RCU_IOC_VERSION _IOR( IFX_RCU_IOC_MAGIC, 0, struct ifx_rcu_ioctl_version) -+/*! -+ \def IFX_RCU_IOC_QUERY_RST_DOMAIN -+ \brief RCU IOCTL Command - Get reset status of given hardware module. -+ -+ This command uses struct "ifx_rcu_ioctl_query_rst_domain" as parameter to get reset status of given hardware module. -+ */ -+#define IFX_RCU_IOC_QUERY_RST_DOMAIN _IOWR(IFX_RCU_IOC_MAGIC, 1, struct ifx_rcu_ioctl_query_rst_domain) -+/*@}*/ -+ -+ -+ -+/* -+ * #################################### -+ * API -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ /* -+ * RST_REQ/RST_STAT Register Access -+ * For accessing to special bits in these two registers, such as fusing, endianess -+ */ -+ unsigned int ifx_rcu_rst_req_read(void); -+ void ifx_rcu_rst_req_write(unsigned int value, unsigned int mask); -+ unsigned int ifx_rcu_rst_stat_read(void); -+ /* -+ * Reset Operation -+ */ -+ int ifx_rcu_request(unsigned int reset_domain_id, unsigned int module_id, ifx_rcu_callbackfn callbackfn, unsigned long arg); -+ int ifx_rcu_free(unsigned int reset_domain_id, unsigned int module_id); -+ int ifx_rcu_stat_get(unsigned int reset_domain_id); -+ int ifx_rcu_rst(unsigned int reset_domain_id, unsigned int module_id); -+#endif -+ -+ -+ -+#endif // IFX_RCU_H -diff --git a/arch/mips/include/asm/ifx/ifx_regs.h b/arch/mips/include/asm/ifx/ifx_regs.h -new file mode 100644 -index 0000000..678bfc3 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_regs.h -@@ -0,0 +1,262 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_regs.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : common header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_CHIP_REGS_H -+#define IFX_CHIP_REGS_H -+ -+#include <asm/io.h> -+ -+/* -+ * Register Operation -+ */ -+#define IFX_REG_R32(_r) __raw_readl((volatile unsigned int *)(_r)) -+#define IFX_REG_W32(_v, _r) __raw_writel((_v), (volatile unsigned int *)(_r)) -+#define IFX_REG_W32_MASK(_clr, _set, _r) IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) -+#define IFX_REG_R16(_r) __raw_readw((_r)) -+#define IFX_REG_W16(_v, _r) __raw_writew((_v), (_r)) -+#define IFX_REG_W16_MASK(_clr, _set, _r) IFX_REG_W16((IFX_REG_R16((_r)) & ~(_clr)) | (_set), (_r)) -+#define IFX_REG_R8(_r) __raw_readb((_r)) -+#define IFX_REG_W8(_v, _r) __raw_writeb((_v), (_r)) -+#define IFX_REG_W8_MASK(_clr, _set, _r) IFX_REG_W8((IFX_REG_R8((_r)) & ~(_clr)) | (_set), (_r)) -+ -+/* -+ * Register manipulation macros that expect bit field defines -+ * to follow the convention that an _S suffix is appended for -+ * a shift count, while the field mask has no suffix. Or can use -+ * _M as suffix -+ */ -+ -+/* Shift first, then mask, usually for write operation */ -+#define SM(_v, _f) (((_v) << _f##_S) & (_f)) -+ -+/* Mask first , then shift, usually for read operation */ -+#define MS(_v, _f) (((_v) & (_f)) >> _f##_S) -+ -+#define IFX_REG_RMW32(_set, _clr, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) & ~(_clr)) | (_set), (_r)) -+ -+#define IFX_REG_RMW32_FILED(_f, _v, _r) \ -+ IFX_REG_W32(\ -+ (IFX_REG_R32((_r)) &~ (_f)) | (((_v) << (_f##_S)) & (_f)), (_r)) -+ -+#define IFX_REG_SET_BIT(_f, _r) \ -+ IFX_REG_W32((IFX_REG_R32((_r)) &~ (_f)) | (_f), (_r)) -+ -+#define IFX_REG_CLR_BIT(_f, _r) \ -+ IFX_REG_W32(IFX_REG_R32((_r)) &~ (_f), (_r)) -+ -+#define IFX_REG_IS_BIT_SET(_f, _r) \ -+ ((IFX_REG_R32((_r)) & (_f)) != 0) -+ -+/* -+ * Bits Operation -+ */ -+#define GET_BITS(x, msb, lsb) \ -+ (((x) >> (lsb)) & ((1 << ((msb) + 1 - (lsb))) - 1)) -+#define SET_BITS(x, msb, lsb, value) \ -+ (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+ -+#if defined(CONFIG_DANUBE) -+#include "danube/danube.h" -+#elif defined(CONFIG_AMAZON_SE) -+#include "amazon_se/amazon_se.h" -+#elif defined(CONFIG_AR9) -+#include "ar9/ar9.h" -+#elif defined(CONFIG_VR9) -+#include "vr9/vr9.h" -+#elif defined(CONFIG_AR10) -+#include "ar10/ar10.h" -+#elif defined(CONFIG_HN1) -+#include "hn1/hn1.h" -+#else -+#error unknown chip -+#endif -+#include "ifx_board.h" -+ -+/* -+ * Chip ID -+ */ -+typedef struct { -+#define IFX_FAMILY_UNKNOWN 0 -+#define IFX_FAMILY_DANUBE 1 -+#define IFX_FAMILY_TWINPASS IFX_FAMILY_DANUBE -+#define IFX_FAMILY_AMAZON_SE 2 -+#define IFX_FAMILY_ASE IFX_FAMILY_AMAZON_SE -+#define IFX_FAMILY_AR9 3 -+#define IFX_FAMILY_xRX100 IFX_FAMILY_AR9 -+#define IFX_FAMILY_VR9 4 -+#define IFX_FAMILY_xRX200 IFX_FAMILY_VR9 -+#define IFX_FAMILY_AR10 5 -+#define IFX_FAMILY_xRX300 IFX_FAMILY_AR10 -+ unsigned int family_id; -+#define IFX_FAMILY_DANUBE_A1x 1 -+#define IFX_FAMILY_TWINPASS_A1x IFX_FAMILY_DANUBE_A1x -+#define IFX_FAMILY_AMAZON_SE_A1x 1 -+#define IFX_FAMILY_ASE_A1x IFX_FAMILY_AMAZON_SE_A1x -+#define IFX_FAMILY_AR9_A1x 1 -+#define IFX_FAMILY_xRX100_A1x IFX_FAMILY_AR9_A1x -+#define IFX_FAMILY_VR9_A1x 1 -+#define IFX_FAMILY_xRX200_A1x IFX_FAMILY_VR9_A1x -+#define IFX_FAMILY_VR9_A2x 2 -+#define IFX_FAMILY_xRX200_A2x IFX_FAMILY_VR9_A2x -+#define IFX_FAMILY_AR10_A1x 1 -+#define IFX_FAMILY_xRX300_A1x IFX_FAMILY_AR10_A1x -+ unsigned int family_ver; -+#define IFX_PARTNUM_DANUBE 0x00EB -+#define IFX_PARTNUM_DANUBE_S 0x00ED -+#define IFX_PARTNUM_AMAZON_S 0x00EF -+#define IFX_PARTNUM_VINAX_VE 0x013C -+#define IFX_PARTNUM_VINAX_E 0x0151 -+#define IFX_PARTNUM_AMAZON_SE_50601 0x0152 -+#define IFX_PARTNUM_AMAZON_SE_50600 0x0153 -+#define IFX_PARTNUM_ARX188 0x016C -+#define IFX_PARTNUM_ARX168 0x016D -+#define IFX_PARTNUM_GRX188 0x0170 -+#define IFX_PARTNUM_GRX168 0x0171 -+#define IFX_PARTNUM_VRX288_A1x 0x01C0 -+#define IFX_PARTNUM_VRX282_A1x 0x01C1 -+#define IFX_PARTNUM_VRX268_A1x 0x01C2 -+#define IFX_PARTNUM_GRX288_A1x 0x01C9 -+#define IFX_PARTNUM_GRX268_A1x 0x01C8 -+#define IFX_PARTNUM_VRX288_A2x 0x000B -+#define IFX_PARTNUM_VRX282_A2x 0x000E -+#define IFX_PARTNUM_VRX268_A2x 0x000C -+#define IFX_PARTNUM_GRX288_A2x 0x000D -+#define IFX_PARTNUM_ARX361 0x0003 // 1x1 Router -+#define IFX_PARTNUM_ARX362 0x0004 // 2x2 Router -+#define IFX_PARTNUM_ARX363 0x0005 // 3x3 Router -+#define IFX_PARTNUM_ARX381 0x0006 // 1x1 Gateway -+#define IFX_PARTNUM_ARX382 0x0007 // 2x2 Gateway -+#define IFX_PARTNUM_ARX383 0x0008 // 3x3 Gateway -+#define IFX_PARTNUM_GRX388 0x0009 // 3x3 Ethernet Router/Gateway -+#define IFX_PARTNUM_ARX368 0x000A // 3x3 High-end Router -+#define IFX_PARTNUM_ARX388 0x000B // 3x3 High-end Gateway -+ unsigned int part_number; -+ unsigned int chip_version; -+ unsigned int manufacturer_id; -+} ifx_chipid_t; -+static inline unsigned int ifx_get_chipid(ifx_chipid_t *p_chipid) -+{ -+ unsigned int chipid; -+ -+ chipid = IFX_REG_R32(IFX_MPS_CHIPID); -+ -+ if ( p_chipid == NULL ) -+ return chipid; -+ -+ p_chipid->part_number = GET_BITS(chipid, 27, 12); -+ p_chipid->chip_version = GET_BITS(chipid, 30, 28); -+ p_chipid->manufacturer_id = GET_BITS(chipid, 11, 1); -+ -+ switch ( p_chipid->part_number ) { -+ case IFX_PARTNUM_DANUBE: -+ case IFX_PARTNUM_DANUBE_S: -+ case IFX_PARTNUM_AMAZON_S: -+ p_chipid->family_id = IFX_FAMILY_DANUBE; -+ p_chipid->family_ver = IFX_FAMILY_DANUBE_A1x; -+ break; -+ case IFX_PARTNUM_VINAX_VE: -+ case IFX_PARTNUM_VINAX_E: -+ p_chipid->family_id = IFX_FAMILY_TWINPASS; -+ p_chipid->family_ver = IFX_FAMILY_DANUBE_A1x; -+ break; -+ case IFX_PARTNUM_AMAZON_SE_50601: -+ case IFX_PARTNUM_AMAZON_SE_50600: -+ p_chipid->family_id = IFX_FAMILY_AMAZON_SE; -+ p_chipid->family_ver = IFX_FAMILY_AMAZON_SE_A1x; -+ break; -+ case IFX_PARTNUM_ARX188: -+ case IFX_PARTNUM_ARX168: -+ case IFX_PARTNUM_GRX188: -+ case IFX_PARTNUM_GRX168: -+ p_chipid->family_id = IFX_FAMILY_xRX100; -+ p_chipid->family_ver = IFX_FAMILY_xRX100_A1x; -+ break; -+ case IFX_PARTNUM_VRX288_A1x: -+ case IFX_PARTNUM_VRX282_A1x: -+ case IFX_PARTNUM_VRX268_A1x: -+ case IFX_PARTNUM_GRX288_A1x: -+ case IFX_PARTNUM_GRX268_A1x: -+ p_chipid->family_id = IFX_FAMILY_xRX200; -+ p_chipid->family_ver = IFX_FAMILY_xRX200_A1x; -+ break; -+ case IFX_PARTNUM_VRX288_A2x: -+ case IFX_PARTNUM_VRX282_A2x: -+ case IFX_PARTNUM_VRX268_A2x: -+ case IFX_PARTNUM_GRX288_A2x: -+ p_chipid->family_id = IFX_FAMILY_xRX200; -+ p_chipid->family_ver = IFX_FAMILY_xRX200_A2x; -+ break; -+ case IFX_PARTNUM_ARX361: -+ case IFX_PARTNUM_ARX362: -+ case IFX_PARTNUM_ARX363: -+ case IFX_PARTNUM_ARX381: -+ case IFX_PARTNUM_ARX382: -+ case IFX_PARTNUM_ARX383: -+ case IFX_PARTNUM_GRX388: -+ case IFX_PARTNUM_ARX368: -+// case IFX_PARTNUM_ARX388: // conflict with VR9 -+ p_chipid->family_id = IFX_FAMILY_xRX300; -+ p_chipid->family_ver = IFX_FAMILY_xRX300_A1x; -+ break; -+ default: -+ p_chipid->family_id = IFX_FAMILY_UNKNOWN; -+ } -+ -+ return chipid; -+} -+ -+/* -+ * Clock -+ */ -+#define CLOCK_25M 25000000 -+#define CLOCK_48M 48000000 -+#define CLOCK_60M 60000000 -+#define CLOCK_62_5M 62500000 -+#define CLOCK_83M 83333333 -+#define CLOCK_83_5M 83500000 -+#define CLOCK_98_304M 98304000 -+#define CLOCK_100M 100000000 -+#define CLOCK_111M 111111111 -+#define CLOCK_125M 125000000 -+#define CLOCK_133M 133333333 -+#define CLOCK_150M 150000000 -+#define CLOCK_166M 166666666 -+#define CLOCK_167M 166666667 -+#define CLOCK_200M 200000000 -+#define CLOCK_196_608M 196608000 -+#define CLOCK_222M 222222222 -+#define CLOCK_250M 250000000 -+#define CLOCK_266M 266666666 -+#define CLOCK_300M 300000000 -+#define CLOCK_333M 333333333 -+#define CLOCK_393M 393215332 -+#define CLOCK_400M 400000000 -+#define CLOCK_500M 500000000 -+#define CLOCK_600M 600000000 -+#define CLOCK_1000M 1000000000 -+ -+#endif /* IFX_CHIP_REGS_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_si.h b/arch/mips/include/asm/ifx/ifx_si.h -new file mode 100644 -index 0000000..0afb8f6 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_si.h -@@ -0,0 +1,246 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_si.h -+** PROJECT : UEIP -+** MODULES : Serial In Controller -+** -+** DATE : 26 Apr 2010 -+** AUTHOR : Xu Liang -+** DESCRIPTION : Global Serial In Controller driver header file -+** COPYRIGHT : Copyright (c) 2006 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** Apr 26, 2010 Xu Liang Init Version -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_SI_H -+#define IFX_SI_H -+ -+/*! -+ \defgroup IFX_SI UEIP Project - SI Controller driver module -+ \brief UEIP Project - Serial In Controller driver module, support AR9, VR9, AR10. -+ */ -+ -+/*! -+ \defgroup IFX_SI_API APIs -+ \ingroup IFX_SI -+ \brief APIs used by other drivers/modules. -+ */ -+ -+/*! -+ \defgroup IFX_SI_IOCTL IOCTL Commands -+ \ingroup IFX_SI -+ \brief IOCTL Commands used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_SI_STRUCT Structures -+ \ingroup IFX_SI -+ \brief Structures used by user application. -+ */ -+ -+/*! -+ \defgroup IFX_SI_ENUM Enumerated Types -+ \ingroup IFX_SI -+ \brief Enumerated types used by user application. -+ */ -+ -+/*! -+ \file ifx_si.h -+ \ingroup IFX_SI -+ \brief SI Controller (Serial In) driver header file -+ */ -+ -+ -+ -+/*! -+ \addtogroup IFX_SI_ENUM -+ */ -+/*@{*/ -+ -+/*! -+ \enum IFX_SI_UPD_SRC_t -+ \brief enum used to configure update source. -+ */ -+typedef enum { -+ IFX_SI_UPD_SRC_SW = 0, -+ IFX_SI_UPD_SRC_GPT3 = 1, -+ IFX_SI_UPD_SRC_FPID = 2, -+ IFX_SI_UPD_SRC_ERR = 3, // no such thing. HW Error. -+} IFX_SI_UPD_SRC_t; -+ -+/*! -+ \enum IFX_SI_SYNC_MODE_t -+ \brief enum used to select either sync mode or async mode. -+ */ -+typedef enum { -+ IFX_SI_ASYNC_MODE = 0, -+ IFX_SI_SYNC_MODE = 1, -+} IFX_SI_SYNC_MODE_t; -+ -+/*! -+ \enum IFX_SI_FPI_SAMPLECLK_DIV_t -+ \brief enum used to select between FPI CLK Division for setting read interval, -+ applicable only when update source = FPID. -+ */ -+typedef enum { -+ // FPID2[26:25] For Sampling Interval Clk -+ IFX_SI_FPI_SAMPLECLK_DIV_010 = 1, -+ IFX_SI_FPI_SAMPLECLK_DIV_040 = 2, -+ IFX_SI_FPI_SAMPLECLK_DIV_080 = 3, -+ IFX_SI_FPI_SAMPLECLK_DIV_160 = 0, -+} IFX_SI_FPI_SAMPLECLK_DIV_t; -+ -+/*! -+ \enum IFX_SI_GROUP_t -+ \brief enum used to select how many input signals are supported. -+ */ -+typedef enum { -+ IFX_SI_GROUP_00 = 0, -+ IFX_SI_GROUP_08 = 1, -+ IFX_SI_GROUP_16 = 3, -+} IFX_SI_GROUP_t; -+ -+/*! -+ \enum IFX_SI_FPI_SHIFTCLK_DIV_t -+ \brief enum used to configure shift-in clock. -+ */ -+typedef enum { -+ // FPID[1:0] For Serial Input Clk -+ IFX_SI_FPI_SHIFTCLK_DIV_002 = 0, -+ IFX_SI_FPI_SHIFTCLK_DIV_004 = 1, -+ IFX_SI_FPI_SHIFTCLK_DIV_008 = 2, -+ IFX_SI_FPI_SHIFTCLK_DIV_016 = 3, -+} IFX_SI_FPI_SHIFTCLK_DIV_t; -+ -+/*! -+ \enum IFX_SI_CONFIG_OP_MASK_t -+ \brief enumerated key for field "operation_mask" of struct "ifx_si_config_param_t". -+ */ -+typedef enum { -+ IFX_SI_CFG_OP_UPDATE_SOURCE = 1 << 0, /* for setting update source. */ -+ IFX_SI_CFG_OP_UPDATE_MODE = 1 << 1, /* for setting sync/async mode. */ -+ IFX_SI_CFG_OP_UPDATE_GROUP = 1 << 2, /* for setting number of input signals. */ -+ IFX_SI_CFG_OP_UPDATE_SHIFTCLKDIV = 1 << 3, /* for setting Shift-in clock through FPI CLK DIV. */ -+} IFX_SI_CONFIG_OP_MASK_t; -+ -+/*@}*/ -+ -+ -+ -+/*! -+ \addtogroup IFX_SI_STRUCT -+ */ -+/*@{*/ -+ -+/*! -+ \struct ifx_si_ioctl_version_t -+ \brief Structure used for query of driver version. -+ */ -+typedef struct { -+ unsigned int major; /*!< output, major number of driver */ -+ unsigned int mid; /*!< output, mid number of driver */ -+ unsigned int minor; /*!< output, minor number of driver */ -+} ifx_si_ioctl_version_t; -+ -+/*! -+ \struct ifx_si_config_param_t -+ \brief Structure used for configure SI Controller (Serial In). -+ */ -+typedef struct { -+ unsigned int operation_mask; /*!< input, Select operations to be performed */ -+ IFX_SI_UPD_SRC_t update_source_type; /*!< input, Corresponding update source (SW, GPT3 or FPID) */ -+ IFX_SI_FPI_SAMPLECLK_DIV_t sampling_clk_div; /*!< input, If FPID is chosen as update source type, set the divider; */ -+ /*!< input, if GPT is chosen as update source type, set the frequency;*/ -+ /*!< input, otherwise, it is ignored. */ -+ IFX_SI_SYNC_MODE_t sync_mode; /*!< input, 0: async mode (74x165), 1: sync mode (74x166) */ -+ IFX_SI_GROUP_t input_group_type; /*!< input, 0: only one is connected and hence only inputs [7:0] are enabled; */ -+ /*!< input, 1: two is connected and both inputs [15:8] and [7:0] are enabled. */ -+ IFX_SI_FPI_SHIFTCLK_DIV_t shift_in_clk_div; /*!< input, Shift-in Clock Div setting */ -+} ifx_si_config_param_t; -+ -+/*! -+ \struct ifx_si_eiu_config -+ \brief Structure used for interrupt extension with SI Controller (Serial In). -+ */ -+struct ifx_si_eiu_config { -+ int irq; // irq triggered by serial input, negative value means no SI EIU support -+ unsigned int intsync; // 1: sync mode (74x166), 0: async mode (74x165) -+ unsigned int sampling_clk; // maximum frequency of sampling clock -+ unsigned int shift_clk; // maximum frequency of shift in clock -+ unsigned int group; // 0: disabled, 1: 8 inputs, 2: 16 inputs -+ unsigned int active_high; // bit0-15: 0 - active low, 1 - active high -+}; -+ -+/*@}*/ -+ -+ -+ -+/*! -+ \addtogroup IFX_SI_IOCTL -+ */ -+/*@{*/ -+ -+#define IFX_SI_IOC_MAGIC 0xfd -+/*! -+ \def IFX_SI_IOC_VERSION -+ \brief SI Controller IOCTL Command - Get driver version number. -+ -+ This command uses struct "ifx_si_ioctl_version" as parameter to SI Controller driver version number. -+ */ -+#define IFX_SI_IOC_VERSION _IOR(IFX_SI_IOC_MAGIC, 1, ifx_si_ioctl_version_t) -+ -+/*! -+ \def IFX_SI_IOC_SET_CONFIG -+ \brief SI Controller IOCTL Command - Config SI Controller (Serial In). -+ -+ This command uses struct "ifx_si_config_param_t" as parameter to configure SI Controller (Serial In). -+ */ -+#define IFX_SI_IOC_SET_CONFIG _IOW(IFX_SI_IOC_MAGIC, 2, ifx_si_config_param_t) -+ -+/*! -+ \def IFX_SI_IOC_GET_SHIFTIN_DATA -+ \brief SI Controller IOCTL Command - Read back shift-in data value (32-bit). -+ -+ This command uses "uint32_t" as parameter to store read-back shift-in data value. -+ */ -+#define IFX_SI_IOC_GET_SHIFTIN_DATA _IOR(IFX_SI_IOC_MAGIC, 3, uint32_t) -+ -+/*! -+ \def IFX_SI_IOC_TEST -+ \brief SI Controller IOCTL Command - Run basic driver sanity check (debug). -+ -+ No parameter is needed for this command. Only for internal sanity check purpose. -+ */ -+#define IFX_SI_IOC_TEST _IO(IFX_SI_IOC_MAGIC, 0) -+ -+/* For checking endpoint */ -+#define IFX_SI_IOC_MAXNR 4 -+ -+/*@}*/ -+ -+ -+ -+#ifdef __KERNEL__ -+ extern unsigned int ifx_si_get_data(void); -+ extern unsigned int ifx_si_get_bit(unsigned int bit); -+ extern int ifx_si_config(ifx_si_config_param_t *param); -+ extern int ifx_si_irq_active_high(unsigned int bit, int active_high); -+ extern int ifx_si_irq_enable(unsigned int bit, int enable); -+ extern unsigned int ifx_si_irq_ier(void); -+ extern unsigned int ifx_si_irq_isr(void); -+#endif -+ -+ -+ -+#endif // IFX_SI_H -diff --git a/arch/mips/include/asm/ifx/ifx_ssc.h b/arch/mips/include/asm/ifx/ifx_ssc.h -new file mode 100644 -index 0000000..ea61e72 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_ssc.h -@@ -0,0 +1,242 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ssc.h -+** PROJECT : IFX UEIP -+** MODULES : SSC -+** -+** DATE : 03 July 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : USIF for SPI Master/Slave -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 03 July,2009 Lei Chuanhua Initial UEIP version -+*******************************************************************************/ -+#ifndef IFX_SSC_H -+#define IFX_SSC_H -+ -+/*! -+ \defgroup IFX_SSC SSC bus driver module -+ \brief UEIP Project - SSC bus driver module, support all CPEs. -+*/ -+ -+/*! -+ \defgroup IFX_SSC_DEFINITIONS Definition and structions -+ \ingroup IFX_SSC -+ \brief definitions for ifx ssc driver -+*/ -+ -+/*! -+ \defgroup IFX_SSC_FUNCTIONS external APIs -+ \ingroup IFX_SSC -+ \brief IFX ssc external driver functions -+*/ -+ -+/*! -+ \defgroup IFX_SSC_INTERNAL Internal functions -+ \ingroup IFX_SSC -+ \brief IFX ssc internal driver functions -+*/ -+ -+/*! -+ \file ifx_ssc.h -+ \ingroup IFX_SSC -+ \brief header file for SSC bus driver external interface -+*/ -+ -+/*! -+ \addtogroup IFX_SSC_DEFINITIONS -+*/ -+/* @{ */ -+/*! \enum IFX_SSC_PRIO_t -+ \brief Set communication priority of SSC connection -+ -+ Three priority levels are defined. Low-level priority queue used for applications like FLASH driver -+ (ifx_ssc_prio_low). normal priority queue used for applications like display (ifx_ssc_prio_mid). -+ High priority queue used for applications like RTP packet transfer (ifx_ssc_prio_high). -+ */ -+typedef enum{ -+ IFX_SSC_PRIO_LOW = 0, /*!< Low Priority queue. For FLASH driver, etc. */ -+ IFX_SSC_PRIO_MID, /*!< Normal Priority queue. For LCD, display data, etc. */ -+ IFX_SSC_PRIO_HIGH, /*!< High priority queue. Ror RTP voice, etc. */ -+ IFX_SSC_PRIO_ASYNC, /*!< Tasklet priority (This is the highest supported priority). -+ For this priority level only the asynchronous API set -+ of the SSC driver can be called. These funtions stay unblocked and a -+ callback function is called when the request is processed. This allows -+ that the APIs are called from tasklet level. The callback function is -+ always called on tasklet level */ -+}IFX_SSC_PRIO_t; -+ -+#define IFX_SSC_PRIO_MAX IFX_SSC_PRIO_ASYNC -+ -+/*! \enum IFX_SSC_MODE_t -+ \brief Defines the Ssc hardware mode settings supported -+ -+ Because there is no official specification, what exactly SPI is and what not, it is necessary -+ to consult the data sheets of the components one wants to use. Important are the permitted clock -+ frequencies and the type of valid transitions. There are no general rules for transitions where -+ data should be latched. Although not specified by Motorola, in practice four modes are used. -+ These four modes are the combinations of CPOL and CPHA. In table 1, the four modes are listed.If -+ the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with -+ CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. -+ CPOL = 0 means falling edge, CPOL = 1 rising edge.The micro controllers from Motorola allow the polarity -+ and the phase of the clock to be adjusted. A positive polarity results in latching data at the rising -+ edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. -+ Most peripherals which can only be slaves, work with this configuration. If it should become necessary -+ to use the other polarity, transitions are reversed. -+ */ -+typedef enum { -+ IFX_SSC_MODE_0 = 0, /*!< CPOL=0,CPHA=0 */ -+ IFX_SSC_MODE_1, /*!< CPOL=0,CPHA=1 */ -+ IFX_SSC_MODE_2, /*!< CPOL=1,CPHA=0 */ -+ IFX_SSC_MODE_3, /*!< CPOL=1,CPHA=1 */ -+ IFX_SSC_MODE_UNKNOWN,/*!< Unknown SPI mode */ -+} IFX_SSC_MODE_t; -+ -+/*! \enum IFX_SSC_HANDL_TYPE_t -+ \brief Defines the SPI handler type supported -+ */ -+typedef enum { -+ IFX_SSC_HANDL_TYPE_SYNC = 0, /*!< Only SYNC handler which be used by sync application */ -+ IFX_SSC_HANDL_TYPE_ASYNC, /*!< Only ASYNC handler which be used by async application */ -+}IFX_SSC_HANDL_TYPE_t; -+ -+/*! \enum IFX_SSC_DLX_t -+ \brief Set communication duplex mode of SSC connection -+ -+ The duplex mode is used to notify SSC bus driver by SSC device driver about what kind of -+ communication mode should be used. Which duplex mode will be used depends on the SSC device -+ driver instead of SSC bus driver. -+ */ -+typedef enum{ -+ IFX_SSC_HALF_DUPLEX = 0, /*!< Half Duplex. Interface is used in half duplex when -+ calling \ref ifx_sscTxRx or \ref ifx_sscAsyncTxRx. -+ The TX path is servered before the RX path. */ -+ IFX_SSC_FULL_DUPLEX, /*!< Full Duplex. Interface is used in full duplex when -+ calling \ref ifx_sscTxRx or \ref ifx_sscAsyncTxRx. -+ The TX-and RX- path is servered simultaneously. */ -+}IFX_SSC_DLX_t; -+ -+ -+/*!< \typedef IFX_CS_DATA -+ \brief Definition of device specific data for chip select -+ */ -+typedef int IFX_CS_DATA; -+ -+enum { -+ IFX_SSC_CS_ON = 0, -+ IFX_SSC_CS_OFF, -+}; -+ -+#define IFX_SSC_WHBGPOSTAT_OUT0_POS 0 -+#define IFX_SSC_WHBGPOSTAT_OUT1_POS 1 -+#define IFX_SSC_WHBGPOSTAT_OUT2_POS 2 -+#define IFX_SSC_WHBGPOSTAT_OUT3_POS 3 -+#define IFX_SSC_WHBGPOSTAT_OUT4_POS 4 -+#define IFX_SSC_WHBGPOSTAT_OUT5_POS 5 -+#define IFX_SSC_WHBGPOSTAT_OUT6_POS 6 -+#define IFX_SSC_WHBGPOSTAT_OUT7_POS 7 -+ -+ -+/*! \typedef IFX_SSC_CS_CB_t -+ \brief Chip Select Callback function type declaration -+ -+ csq csq=0, i.e. CS low (active). csq=1, i.e.CS high (idle). -+ cs_data This is the device number in case if more than one device is using the same registered driver. -+ E.g. two VINETICs, each with it´s own CS. -+ */ -+typedef int (*IFX_SSC_CS_CB_t)(u32 csq, IFX_CS_DATA cs_data); -+ -+/*! typedef ifx_ssc_async_fkt_cb_t -+ \brief Callback definition for asynchronous SSC API calls. This callback is called -+ by the SSC driver on tasklet level after the request is completed or exit with -+ an error. -+ -+ \param handle Funktion handle that provided for callback registration -+ during the SSC asynchronous API call. -+ \param retvalue This return value describe if the asynchronous request -+ identified an error and worked successfully. -+*/ -+typedef void (*ifx_ssc_async_fkt_cb_t) (int handle, int retvalue); -+ -+/*! typedef IFX_SSC_ASYNC_CALLBACK_t -+ \brief Parameter to specify the asynchronous callback. It is called by the SSC -+ tasklet after the requested transmission or locking is done. -+*/ -+typedef struct{ -+ ifx_ssc_async_fkt_cb_t pFunction; /*!< Callback function pointer, called in the SSC tasklet -+ when the requested command is executed*/ -+ int functionHandle; /*!< Callback function handle. This parameter is -+ transparently given to the callback function without -+ any modification by the SSC driver*/ -+}IFX_SSC_ASYNC_CALLBACK_t; -+ -+/*! \brief Parameter structure used to configure an SSC connection "ConnId". -+ */ -+typedef struct { -+ IFX_SSC_MODE_t ssc_mode; /*!< Defines the hardware setup mode of the SSC */ -+ IFX_SSC_PRIO_t ssc_prio; /*!< The communication priority of SSC connection. -+ Three priority levels are defined. Low-level priority queue used for applications -+ like FLASH driver (ifx_ssc_prio_low). Normal priority queue used for applications -+ like display (ifx_ssc_prio_mid). High priority queue used for applications like RTP -+ packet transfer (ifx_ssc_prio_high). The here defined SSC priority corresponds to -+ the priority the SSC driver application and should be set just for information when -+ the driver is registered by the application. -+ */ -+ int baudrate; /*!< Baudrate used for the ConnId. -+ This parameter can be later be modified by a call of ifx_sscSetBaud -+ */ -+ int fragSize; /*!< All transmitted and received packets should be fragmented in this fragment -+ size. Size given in Bytes. A maximum of 1024 Bytes is allowed. If the client -+ uses a bigger values here, SSC returns with error. The client has to take -+ care of the fragmentation -+ */ -+ int maxFIFOSize; /*!< Maximum packet size in FIFO mode. -+ All transmitted and received packets are transmitted in DMA mode if the packet -+ size is greater than this value. A value of 148 is recommended at first. -+ Size given in Bytes -+ */ -+ IFX_SSC_CS_CB_t csset_cb; /*!< Function Callback called by SSC driver when it starts/stops to receive or transmit */ -+ IFX_CS_DATA cs_data; /*!< Parameter used for the function call of "csSet_cb". */ -+ IFX_SSC_DLX_t duplex_mode; /*!< Duplex Mode Selector. Connection used the SSC interface either in half- or full- duplex mode. */ -+} IFX_SSC_CONFIGURE_t; -+ -+/*! \typedef IFX_SSC_HANDLE -+ \brief Definition of the connection handle -+ -+ as it is used by the client kernel module that use the SSC driver -+ Inside of the SSC driver, this handle is mapped to an internal structure that contains the connection specific -+ parameter (e.g. Baudrate, Chipselect Callbacks, etc.). -+ */ -+typedef void * IFX_SSC_HANDLE; -+/* @} */ -+ -+ -+extern int ifx_ssc_cs_low(u32 pin); -+extern int ifx_ssc_cs_high(u32 pin); -+extern int ifx_sscLock(IFX_SSC_HANDLE handler); -+extern int ifx_sscUnlock(IFX_SSC_HANDLE handler); -+extern int ifx_sscSetBaud(IFX_SSC_HANDLE handler, unsigned int baud); -+extern int ifx_sscTxRx(IFX_SSC_HANDLE handler, char* tx_buf, u32 tx_len, char* rx_buf, u32 rx_len); -+extern int ifx_sscRx(IFX_SSC_HANDLE handler, char *rx_buf, u32 rx_len); -+extern int ifx_sscTx(IFX_SSC_HANDLE handler, char *tx_buf, u32 tx_len); -+extern IFX_SSC_HANDLE ifx_sscAllocConnection(char *dev_name, IFX_SSC_CONFIGURE_t *connid); -+extern int ifx_sscFreeConnection(IFX_SSC_HANDLE handler); -+extern int ifx_sscAsyncTxRx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, -+ char *txbuf, int txsize, char *rxbuf, int rxsize); -+extern int ifx_sscAsyncTx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, -+ char *txbuf, int txsize); -+extern int ifx_sscAsyncRx(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback, -+ char *rxbuf, int rxsize); -+extern int ifx_sscAsyncLock(IFX_SSC_HANDLE handler, IFX_SSC_ASYNC_CALLBACK_t *pCallback); -+extern int ifx_sscAsyncUnLock(IFX_SSC_HANDLE handler); -+ -+#endif /* IFX_SSC_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_types.h b/arch/mips/include/asm/ifx/ifx_types.h -new file mode 100644 -index 0000000..777bc75 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_types.h -@@ -0,0 +1,217 @@ -+#ifndef _IFX_TYPES_H -+#define _IFX_TYPES_H -+/******************************************************************************* -+ -+ Copyright (c) 2007-2009 -+ Infineon Technologies AG -+ Am Campeon 1-12; 81726 Munich, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+/* Determine the target type */ -+#if defined(WIN64) || defined (_WIN64) \ -+ || defined(__x86_64__) \ -+ || defined(__LP64__) || defined(_LP64) \ -+ || defined (__amd64) \ -+ || defined (powerpc64) || defined (__powerpc64__) || defined (__ppc64__) \ -+ || defined (__64BIT__) -+/* X86_64 */ -+# ifndef IFX_64 -+# define IFX_64 1 -+# endif /* IFX_64 */ -+#elif defined (__ia64__) || defined (__ia64) -+/* IA64 */ -+# ifndef IFX_64 -+# define IFX_64 1 -+# endif /* IFX_64 */ -+#else -+/* not 64 bit system */ -+#endif /* 64 bit determination */ -+ -+/** \defgroup IFX_BASIC_TYPES Basic IFX Data Types -+ This section describes the Infineon basic data type definitions */ -+/*@{*/ -+ -+/** This is the character datatype. */ -+typedef char IFX_char_t; -+/** This is the integer datatype. */ -+typedef signed int IFX_int_t; -+/** This is the unsigned integer datatype. */ -+typedef unsigned int IFX_uint_t; -+/** This is the unsigned 8-bit datatype. */ -+typedef unsigned char IFX_uint8_t; -+/** This is the signed 8-bit datatype. */ -+typedef signed char IFX_int8_t; -+/** This is the unsigned 16-bit datatype. */ -+typedef unsigned short IFX_uint16_t; -+/** This is the signed 16-bit datatype. */ -+typedef signed short IFX_int16_t; -+/** This is the unsigned 32-bit datatype. */ -+typedef unsigned int IFX_uint32_t; -+/** This is the signed 32-bit datatype. */ -+typedef signed int IFX_int32_t; -+/** This is the float datatype. */ -+typedef float IFX_float_t; -+/** This is the void datatype. */ -+typedef void IFX_void_t; -+ -+ -+#if defined(IFX_64) && (IFX_64 == 1) -+ /* NOTE: Most Unix systems use the I32LP64 standard -+ which defines a long as 64 bits and Win64 uses -+ the IL32LLP64 standard which defines a long as 32 bits. -+ */ -+ #if defined(WIN64) -+ /** This is the unsigned 64-bit datatype. */ -+ typedef unsigned long long int IFX_uint64_t; -+ /** This is the signed 64-bit datatype. */ -+ typedef signed long long int IFX_int64_t; -+ #else /* WIN64 */ -+ /** This is the unsigned 64-bit datatype. */ -+ typedef unsigned long int IFX_uint64_t; -+ /** This is the signed 64-bit datatype. */ -+ typedef signed long int IFX_int64_t; -+ #endif /* WIN64 */ -+ -+ /** This is the unsigned long datatype. -+ On 64 bit systems it is 8 byte wide. -+ */ -+ typedef IFX_uint64_t IFX_ulong_t; -+ #define HAVE_IFX_ULONG_T -+ -+ /** This is the signed long datatype. -+ On 64 bit systems it is 8 byte wide. -+ */ -+ typedef IFX_int64_t IFX_long_t; -+ #define HAVE_IFX_LONG_T -+#else -+ /** This is the unsigned 64-bit datatype. */ -+ typedef unsigned long long int IFX_uint64_t; -+ /** This is the signed 64-bit datatype. */ -+ typedef signed long long int IFX_int64_t; -+ -+ /** This is the unsigned long datatype. -+ On 32bit systems it is 4 byte wide. -+ */ -+ typedef unsigned long IFX_ulong_t; -+ #define HAVE_IFX_ULONG_T -+ -+ /** This is the signed long datatype. -+ On 32bit systems it is 4 byte wide. -+ */ -+ typedef signed long IFX_long_t; -+ #define HAVE_IFX_LONG_T -+#endif /* 32/64 bit specific types */ -+ -+ -+/** This is the size data type (32 or 64 bit) */ -+typedef IFX_ulong_t IFX_size_t; -+#define HAVE_IFX_SIZE_T -+ -+/** This is the signed size data type (32 or 64 bit) */ -+typedef IFX_long_t IFX_ssize_t; -+#define HAVE_IFX_SSIZE_T -+ -+/** This is the time data type (32 or 64 bit) */ -+typedef IFX_ulong_t IFX_time_t; -+ -+/* NOTE: (ANSI X3.159-1989) -+ While some of these architectures feature uniform pointers -+ which are the size of some integer type, maximally portable -+ code may not assume any necessary correspondence between -+ different pointer types and the integral types. -+ -+ Since pointers and integers are now considered incommensurate, -+ the only integer that can be safely converted to a pointer -+ is the constant 0. -+*/ -+/** Conversion pointer to unsigned values (32 or 64 bit) */ -+typedef IFX_ulong_t IFX_uintptr_t; -+#define HAVE_IFX_UINTPTR_T -+/** Conversion pointer to signed values (32 or 64 bit) */ -+typedef IFX_long_t IFX_intptr_t; -+#define HAVE_IFX_INTPTR_T -+ -+/** This is the volatile unsigned 8-bit datatype. */ -+typedef volatile IFX_uint8_t IFX_vuint8_t; -+/** This is the volatile signed 8-bit datatype. */ -+typedef volatile IFX_int8_t IFX_vint8_t; -+/** This is the volatile unsigned 16-bit datatype. */ -+typedef volatile IFX_uint16_t IFX_vuint16_t; -+/** This is the volatile signed 16-bit datatype. */ -+typedef volatile IFX_int16_t IFX_vint16_t; -+/** This is the volatile unsigned 32-bit datatype. */ -+typedef volatile IFX_uint32_t IFX_vuint32_t; -+/** This is the volatile signed 32-bit datatype. */ -+typedef volatile IFX_int32_t IFX_vint32_t; -+/** This is the volatile unsigned 64-bit datatype. */ -+typedef volatile IFX_uint64_t IFX_vuint64_t; -+/** This is the volatile signed 64-bit datatype. */ -+typedef volatile IFX_int64_t IFX_vint64_t; -+/** This is the volatile float datatype. */ -+typedef volatile IFX_float_t IFX_vfloat_t; -+ -+ -+/** A type for handling boolean issues. */ -+typedef enum { -+ /** false */ -+ IFX_FALSE = 0, -+ /** true */ -+ IFX_TRUE = 1 -+} IFX_boolean_t; -+ -+ -+/** -+ This type is used for parameters that should enable -+ and disable a dedicated feature. */ -+typedef enum { -+ /** disable */ -+ IFX_DISABLE = 0, -+ /** enable */ -+ IFX_ENABLE = 1 -+} IFX_enDis_t; -+ -+/** -+ This type is used for parameters that should enable -+ and disable a dedicated feature. */ -+typedef IFX_enDis_t IFX_operation_t; -+ -+/** -+ This type has two states, even and odd. -+*/ -+typedef enum { -+ /** even */ -+ IFX_EVEN = 0, -+ /** odd */ -+ IFX_ODD = 1 -+} IFX_evenOdd_t; -+ -+ -+/** -+ This type has two states, high and low. -+*/ -+typedef enum { -+ /** low */ -+ IFX_LOW = 0, -+ /** high */ -+ IFX_HIGH = 1 -+} IFX_highLow_t; -+ -+/** -+ This type has two states, success and error -+*/ -+typedef enum { -+ /** operation failed */ -+ IFX_ERROR = -1, -+ /** operation succeeded */ -+ IFX_SUCCESS = 0 -+} IFX_return_t; -+ -+/** NULL pointer */ -+#define IFX_NULL ((IFX_void_t *)0) -+/*@}*/ /* IFX_BASIC_TYPES */ -+ -+#endif /* _IFX_TYPES_H */ -diff --git a/arch/mips/include/asm/ifx/ifx_usif_spi.h b/arch/mips/include/asm/ifx/ifx_usif_spi.h -new file mode 100644 -index 0000000..a3caa8a ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_usif_spi.h -@@ -0,0 +1,247 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_usif_spi.h -+** PROJECT : IFX UEIP for VRX200 -+** MODULES : USIF for SPI Mode -+** -+** DATE : 03 Jun 2009 -+** AUTHOR : Lei Chuanhua -+** DESCRIPTION : USIF SPI mode for counterpart API -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 03 Jun,2009 Lei Chuanhua Initial version -+*******************************************************************************/ -+ -+#ifndef IFX_USIF_SPI_H -+#define IFX_USIF_SPI_H -+ -+/*! -+ \defgroup IFX_USIF_SPI IFX USIF SPI mode module -+ \brief ifx usif spi mode driver module -+*/ -+ -+/*! -+ \defgroup IFX_USIF_SPI_DEFINITIONS Defintion and structures -+ \ingroup IFX_USIF_SPI -+ \brief definitions for ifx usif spi mode driver -+*/ -+ -+/*! -+ \defgroup IFX_USIF_SPI_FUNCTIONS External APIs -+ \ingroup IFX_USIF_SPI -+ \brief usif spi external driver functions -+*/ -+ -+/*! -+ \defgroup IFX_USIF_SPI_INTERNAL Internal functions -+ \ingroup IFX_USIF_SPI -+ \brief usif spi internal driver functions -+*/ -+ -+/*! -+ \file ifx_usif_spi.h -+ \brief header file for usif spi driver -+*/ -+ -+/* @{ */ -+/*! -+ \addtogroup IFX_USIF_SPI_DEFINITIONS -+*/ -+/*! \enum IFX_USIF_SPI_PRIO_t -+ \brief Set communication priority of USIF_SPI connection -+ -+ Three priority levels are defined. Low-level priority queue used for applications like FLASH driver -+ (ifx_usif_spi_prio_low). normal priority queue used for applications like display (ifx_usif_spi_prio_mid). -+ High priority queue used for applications like RTP packet transfer (ifx_usif_spi_prio_high). -+ */ -+typedef enum{ -+ IFX_USIF_SPI_PRIO_LOW = 0, /*!< Low Priority queue. For FLASH driver, etc. */ -+ IFX_USIF_SPI_PRIO_MID, /*!< Normal Priority queue. For LCD, display data, etc. */ -+ IFX_USIF_SPI_PRIO_HIGH, /*!< High priority queue. Ror RTP voice, etc. */ -+ IFX_USIF_SPI_PRIO_ASYNC, /*!< Tasklet priority (This is the highest supported priority). -+ For this priority level only the asynchronous API set -+ of the SSC driver can be called. These funtions stay unblocked and a -+ callback function is called when the request is processed. This allows -+ that the APIs are called from tasklet level. The callback function is -+ always called on tasklet level */ -+}IFX_USIF_SPI_PRIO_t; -+ -+#define IFX_USIF_SPI_PRIO_MAX IFX_USIF_SPI_PRIO_ASYNC -+ -+ -+/*! \enum IFX_USIF_SPI_MODE_t -+ \brief Defines the Ssc hardware mode settings supported -+ -+ Because there is no official specification, what exactly SPI is and what not, it is necessary -+ to consult the data sheets of the components one wants to use. Important are the permitted clock -+ frequencies and the type of valid transitions. There are no general rules for transitions where -+ data should be latched. Although not specified by Motorola, in practice four modes are used. -+ These four modes are the combinations of CPOL and CPHA. In table 1, the four modes are listed.If -+ the phase of the clock is zero, i.e. CPHA = 0, data is latched at the rising edge of the clock with -+ CPOL = 0, and at the falling edge of the clock with CPOL = 1. If CPHA = 1, the polarities are reversed. -+ CPOL = 0 means falling edge, CPOL = 1 rising edge.The micro controllers from Motorola allow the polarity -+ and the phase of the clock to be adjusted. A positive polarity results in latching data at the rising -+ edge of the clock. However data is put on the data line already at the falling edge in order to stabilize. -+ Most peripherals which can only be slaves, work with this configuration. If it should become necessary -+ to use the other polarity, transitions are reversed. -+ */ -+typedef enum { -+ IFX_USIF_SPI_MODE_0 = 0, /*!< CPOL=0,CPHA=0 */ -+ IFX_USIF_SPI_MODE_1, /*!< CPOL=0,CPHA=1 */ -+ IFX_USIF_SPI_MODE_2, /*!< CPOL=1,CPHA=0 */ -+ IFX_USIF_SPI_MODE_3, /*!< CPOL=1,CPHA=1 */ -+ IFX_USIF_SPI_MODE_UNKNOWN,/*!< Unknown SPI mode */ -+} IFX_USIF_SPI_MODE_t; -+ -+/*! \enum IFX_USIF_SPI_HANDL_TYPE_t -+ \brief Defines the USIF SPI handler type supported -+ */ -+typedef enum { -+ IFX_USIF_SPI_HANDL_TYPE_SYNC = 0, /*!< Only SYNC handler which be used by sync application */ -+ IFX_USIF_SPI_HANDL_TYPE_ASYNC, /*!< Only ASYNC handler which be used by async application */ -+}IFX_USIF_SPI_HANDL_TYPE_t; -+ -+/*! \enum IFX_USIF_SPI_DLX_t -+ \brief Set communication duplex mode of USIF SPI connection -+ -+ The duplex mode is used to notify USIF SPI bus driver by USIF SPI device driver about what kind of -+ communication mode should be used. Which duplex mode will be used depends on the USIF SPI device -+ driver instead of USIF SPI bus driver. -+ */ -+typedef enum{ -+ IFX_USIF_SPI_HALF_DUPLEX = 0, /*!< Half Duplex. Interface is used in half duplex when -+ calling \ref ifx_usif_spiTxRx or \ref ifx_usif_spiAsyncTxRx -+ The TX path is servered before the RX path. */ -+ IFX_USIF_SPI_FULL_DUPLEX, /*!< Full Duplex. Interface is used in full duplex when -+ calling \ref ifx_usif_spiTxRx or \ref ifx_usif_spiAsyncTxRx. -+ The TX-and RX- path is servered simultaneously. */ -+}IFX_USIF_SPI_DLX_t; -+ -+ -+ -+/*!< \typedef IFX_USIF_SPI_CS_DATA_t -+ \brief Definition of device specific data for chip select -+ */ -+typedef int IFX_USIF_SPI_CS_DATA_t; -+ -+/* chip select number */ -+#define IFX_USIF_SPI_CS0 0 -+#define IFX_USIF_SPI_CS1 1 -+#define IFX_USIF_SPI_CS2 2 -+#define IFX_USIF_SPI_CS3 3 -+#define IFX_USIF_SPI_CS4 4 -+#define IFX_USIF_SPI_CS5 5 -+#define IFX_USIF_SPI_CS6 6 -+#define IFX_USIF_SPI_CS7 7 -+ -+enum { -+ IFX_USIF_SPI_CS_ON = 0, -+ IFX_USIF_SPI_CS_OFF, -+}; -+ -+/*! \typedef IFX_USIF_SPI_CS_CB_t -+ \brief Chip Select Callback function type declaration -+ -+ csq csq=0, i.e. CS low (active). csq=1, i.e.CS high (idle). -+ cs_data This is the device number in case if more than one device is using the same registered driver. -+ E.g. two VINETICs, each with it´s own CS. -+ */ -+typedef int (*IFX_USIF_SPI_CS_CB_t)(u32 csq, IFX_USIF_SPI_CS_DATA_t cs_data); -+ -+/*! typedef ifx_usif_spi_async_fkt_cb_t -+ \brief Callback definition for asynchronous SSC API calls. This callback is called -+ by the SSC driver on tasklet level after the request is completed or exit with -+ an error. -+ -+ \param handle Funktion handle that provided for callback registration -+ during the SSC asynchronous API call. -+ \param retvalue This return value describe if the asynchronous request -+ identified an error and worked successfully. -+*/ -+typedef void (*ifx_usif_spi_async_fkt_cb_t)(int handle, int retvalue); -+ -+/*! typedef IFX_SSC_ASYNC_CALLBACK_t -+ \brief Parameter to specify the asynchronous callback. It is called by the SSC -+ tasklet after the requested transmission or locking is done. -+*/ -+typedef struct{ -+ ifx_usif_spi_async_fkt_cb_t pFunction; /*!< Callback function pointer, called in the SSC tasklet -+ when the requested command is executed*/ -+ int functionHandle; /*!< Callback function handle. This parameter is -+ transparently given to the callback function without -+ any modification by the SSC driver*/ -+}IFX_USIF_SPI_ASYNC_CALLBACK_t; -+ -+ -+/*! \brief Parameter structure used to configure an USIF_SPI connection "ConnId". -+ */ -+typedef struct{ -+ IFX_USIF_SPI_MODE_t spi_mode; /*!< Defines the hardware setup mode of the USIF_SPI */ -+ IFX_USIF_SPI_PRIO_t spi_prio; /*!< The communication priority of USIF_SPI connection. -+ Three priority levels are defined. Low-level priority queue used for applications -+ like FLASH driver (ifx_usif_spi_prio_low). Normal priority queue used for applications -+ like display (ifx_usif_spi_prio_mid). High priority queue used for applications like RTP -+ packet transfer (ifx_usif_spi_prio_high). The here defined USIF_SPI priority corresponds to -+ the priority the USIF_SPI driver application and should be set just for information when -+ the driver is registered by the application. -+ */ -+ int baudrate; /*!< Baudrate used for the ConnId. -+ This parameter can be later be modified by a call of ifx_usif_spiSetBaud -+ */ -+ int fragSize; /*!< All transmitted and received packets should be fragmented in this fragment -+ size. Size given in Bytes. A maximum of 1024 Bytes is allowed. If the client -+ uses a bigger values here, USIF_SPI returns with error. The client has to take -+ care of the fragmentation -+ */ -+ int maxFIFOSize; /*!< Maximum packet size in FIFO mode. -+ All transmitted and received packets are transmitted in DMA mode if the packet -+ size is greater than this value. A value of 148 is recommended at first. -+ Size given in Bytes -+ */ -+ IFX_USIF_SPI_CS_CB_t csset_cb; /*!< Function Callback called by USIF_SPI driver when it starts/stops to receive or transmit */ -+ IFX_USIF_SPI_CS_DATA_t cs_data; /*!< Parameter used for the function call of "csSet_cb". */ -+ IFX_USIF_SPI_DLX_t duplex_mode; /*!< Duplex Mode Selector. Connection used the USIF SPI interface either in half- or full- duplex mode. */ -+ -+} IFX_USIF_SPI_CONFIGURE_t; -+ -+/*! \typedef IFX_USIF_SPI_HANDLE_t -+ \brief Definition of the connection handle -+ -+ as it is used by the client kernel module that use the USIF_SPI driver -+ Inside of the USIF_SPI driver, this handle is mapped to an internal structure that contains the connection specific -+ parameter (e.g. Baudrate, Chipselect Callbacks, etc.). -+ */ -+typedef void * IFX_USIF_SPI_HANDLE_t; -+/* @} */ -+ -+extern int ifx_usif_spi_cs_low(u32 pin); -+extern int ifx_usif_spi_cs_high(u32 pin); -+extern int ifx_usif_spiLock(IFX_USIF_SPI_HANDLE_t handler); -+extern int ifx_usif_spiUnlock(IFX_USIF_SPI_HANDLE_t handler); -+extern int ifx_usif_spiSetBaud(IFX_USIF_SPI_HANDLE_t handler, unsigned int baud); -+extern int ifx_usif_spiTxRx(IFX_USIF_SPI_HANDLE_t handler, char* txbuf, -+ u32 txlen,char* rxbuf, u32 rxlen); -+extern int ifx_usif_spiRx(IFX_USIF_SPI_HANDLE_t handler, char *rxbuf, u32 rxlen); -+extern int ifx_usif_spiTx(IFX_USIF_SPI_HANDLE_t handler, char *txbuf, u32 txlen); -+extern IFX_USIF_SPI_HANDLE_t ifx_usif_spiAllocConnection (char *dev_name, IFX_USIF_SPI_CONFIGURE_t *connid); -+extern int ifx_usif_spiFreeConnection (IFX_USIF_SPI_HANDLE_t handler); -+extern int ifx_usif_spiAsyncTxRx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, -+ char *txbuf, int txsize, char *rxbuf, int rxsize); -+extern int ifx_usif_spiAsyncTx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, -+ char *txbuf, int txsize); -+extern int ifx_usif_spiAsyncRx(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback, -+ char *rxbuf, int rxsize); -+ -+extern int ifx_usif_spiAsyncLock(IFX_USIF_SPI_HANDLE_t handler, IFX_USIF_SPI_ASYNC_CALLBACK_t *pCallback); -+extern int ifx_usif_spiAsyncUnLock(IFX_USIF_SPI_HANDLE_t handler); -+ -+#endif /* IFX_USIF_SPI_H */ -+ -diff --git a/arch/mips/include/asm/ifx/ifx_wdt.h b/arch/mips/include/asm/ifx/ifx_wdt.h -new file mode 100644 -index 0000000..8424507 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/ifx_wdt.h -@@ -0,0 +1,118 @@ -+/****************************************************************************** -+** -+** FILE NAME : ifx_wdt.h -+** PROJECT : IFX UEIP -+** MODULES : WDT -+** -+** DATE : 12 Aug 2009 -+** AUTHOR : Lee Yao Chye -+** DESCRIPTION : Watchdog Timer -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** HISTORY -+** $Date $Author $Comment -+** 12 Aug 2009 Lee Yao Chye Initial UEIP version -+** 19 Oct 2009 Lee Yao Chye Add Linux style ioctls -+*******************************************************************************/ -+#ifndef IFX_WDT_H -+#define IFX_WDT_H -+ -+/*! -+ \defgroup IFX_WDT_IOCTL IOCTL Commands -+ \ingroup IFX_WDT -+ \brief IOCTL Commands used by user application. -+ */ -+ -+ -+#include <linux/watchdog.h> -+ -+/*! -+ \addtogroup IFX_WDT_IOCTL -+ */ -+/*@{*/ -+ -+/* wdt ioctl control */ -+#define IFX_WDT_IOC_MAGIC 0xc0 -+ -+/*! -+ \def IFX_WDT_IOC_START -+ \brief wdt IOCTL Command - similar to WDIOC_SETTIMEOUT -+ -+ This command is used to configure the watchdog timeout and start the watchdog. -+ */ -+#define IFX_WDT_IOC_START _IOW(IFX_WDT_IOC_MAGIC, 0, int) -+ -+/*! -+ \def IFX_WDT_IOC_STOP -+ \brief wdt IOCTL Command - stop the watchdog -+ -+ This command is used to stop the watchdog. -+ */ -+#define IFX_WDT_IOC_STOP _IO(IFX_WDT_IOC_MAGIC, 1) -+ -+/*! -+ \def IFX_WDT_IOC_PING -+ \brief wdt IOCTL Command - similar to WDIOC_KEEPALIVE -+ -+ This command is used to keep the watchdog alive. -+ */ -+#define IFX_WDT_IOC_PING _IO(IFX_WDT_IOC_MAGIC, 2) -+ -+/*! -+ \def IFX_WDT_IOC_SET_PWL -+ \brief wdt IOCTL Command - set prewarning level -+ -+ This command is used to configure the prewarning level. -+ 0 for 1/2 of the max WDT period -+ 1 for 1/4 of the max WDT period -+ 2 for 1/8 of the max WDT period -+ 3 for 1/16 of the max WDT period -+ */ -+#define IFX_WDT_IOC_SET_PWL _IOW(IFX_WDT_IOC_MAGIC, 3, int) -+ -+/*! -+ \def IFX_WDT_IOC_SET_DSEN -+ \brief wdt IOCTL Command - configure debug suspend -+ -+ This command is used to configure debug suspend. -+ */ -+#define IFX_WDT_IOC_SET_DSEN _IOW(IFX_WDT_IOC_MAGIC, 4, int) -+ -+/*! -+ \def IFX_WDT_IOC_SET_LPEN -+ \brief wdt IOCTL Command - configure low power clock freeze mode -+ -+ This command is used to configure low power clock freeze mode. -+ */ -+#define IFX_WDT_IOC_SET_LPEN _IOW(IFX_WDT_IOC_MAGIC, 5, int) -+ -+/*! -+ \def IFX_WDT_IOC_GET_STATUS -+ \brief wdt IOCTL Command - reads the watchdog status register -+ -+ This command is used to read the watchdog status register. -+ */ -+#define IFX_WDT_IOC_GET_STATUS _IOR(IFX_WDT_IOC_MAGIC, 6, int) -+ -+/*! -+ \def IFX_WDT_IOC_SET_CLKDIV -+ \brief wdt IOCTL Command - configures the watchdog clock divider -+ -+ This command is used to configure the watchdog clock divider. -+ 0 for CLK_WDT = 1 x CLK_TIMER -+ 1 for CLK_WDT = 64 x CLK_TIMER -+ 2 for CLK_WDT = 4096 x CLK_TIMER -+ 3 for CLK_WDT = 262144 x CLK_TIMER -+ */ -+#define IFX_WDT_IOC_SET_CLKDIV _IOW(IFX_WDT_IOC_MAGIC, 7, int) -+ -+/*@}*/ -+ -+ -+#endif /* IFX_WDT_H */ -diff --git a/arch/mips/include/asm/ifx/irq.h b/arch/mips/include/asm/ifx/irq.h -new file mode 100644 -index 0000000..6a66f96 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/irq.h -@@ -0,0 +1,256 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : common header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_IRQ_H -+#define IFX_IRQ_H -+ -+ -+#include <linux/version.h> -+#include <linux/types.h> -+ -+unsigned int ltq_irq_create_mapping(unsigned int irq); -+ -+/* these vectors are to handle the interrupts from the internal DANUBE -+ * interrupt controller. THe INT_NUM values are really just indices into -+ * an array and are set up so that we can use the INT_NUM as a shift -+ * to calculate a mask value. -+ */ -+//#define INT_NUM_IRQ0 0x00 -+#define INT_NUM_IM0_IRL0 (INT_NUM_IRQ0 + 0) -+#define INT_NUM_IM0_IRL1 (INT_NUM_IRQ0 + 1) -+#define INT_NUM_IM0_IRL2 (INT_NUM_IRQ0 + 2) -+#define INT_NUM_IM0_IRL3 (INT_NUM_IRQ0 + 3) -+#define INT_NUM_IM0_IRL4 (INT_NUM_IRQ0 + 4) -+#define INT_NUM_IM0_IRL5 (INT_NUM_IRQ0 + 5) -+#define INT_NUM_IM0_IRL6 (INT_NUM_IRQ0 + 6) -+#define INT_NUM_IM0_IRL7 (INT_NUM_IRQ0 + 7) -+#define INT_NUM_IM0_IRL8 (INT_NUM_IRQ0 + 8) -+#define INT_NUM_IM0_IRL9 (INT_NUM_IRQ0 + 9) -+#define INT_NUM_IM0_IRL10 (INT_NUM_IRQ0 + 10) -+#define INT_NUM_IM0_IRL11 (INT_NUM_IRQ0 + 11) -+#define INT_NUM_IM0_IRL12 (INT_NUM_IRQ0 + 12) -+#define INT_NUM_IM0_IRL13 (INT_NUM_IRQ0 + 13) -+#define INT_NUM_IM0_IRL14 (INT_NUM_IRQ0 + 14) -+#define INT_NUM_IM0_IRL15 (INT_NUM_IRQ0 + 15) -+#define INT_NUM_IM0_IRL16 (INT_NUM_IRQ0 + 16) -+#define INT_NUM_IM0_IRL17 (INT_NUM_IRQ0 + 17) -+#define INT_NUM_IM0_IRL18 (INT_NUM_IRQ0 + 18) -+#define INT_NUM_IM0_IRL19 (INT_NUM_IRQ0 + 19) -+#define INT_NUM_IM0_IRL20 (INT_NUM_IRQ0 + 20) -+#define INT_NUM_IM0_IRL21 (INT_NUM_IRQ0 + 21) -+#define INT_NUM_IM0_IRL22 (INT_NUM_IRQ0 + 22) -+#define INT_NUM_IM0_IRL23 (INT_NUM_IRQ0 + 23) -+#define INT_NUM_IM0_IRL24 (INT_NUM_IRQ0 + 24) -+#define INT_NUM_IM0_IRL25 (INT_NUM_IRQ0 + 25) -+#define INT_NUM_IM0_IRL26 (INT_NUM_IRQ0 + 26) -+#define INT_NUM_IM0_IRL27 (INT_NUM_IRQ0 + 27) -+#define INT_NUM_IM0_IRL28 (INT_NUM_IRQ0 + 28) -+#define INT_NUM_IM0_IRL29 (INT_NUM_IRQ0 + 29) -+#define INT_NUM_IM0_IRL30 (INT_NUM_IRQ0 + 30) -+#define INT_NUM_IM0_IRL31 (INT_NUM_IRQ0 + 31) -+ -+#define INT_NUM_IM1_IRL0 (INT_NUM_IRQ0 + 32) -+#define INT_NUM_IM1_IRL1 (INT_NUM_IM1_IRL0 + 1) -+#define INT_NUM_IM1_IRL2 (INT_NUM_IM1_IRL0 + 2) -+#define INT_NUM_IM1_IRL3 (INT_NUM_IM1_IRL0 + 3) -+#define INT_NUM_IM1_IRL4 (INT_NUM_IM1_IRL0 + 4) -+#define INT_NUM_IM1_IRL5 (INT_NUM_IM1_IRL0 + 5) -+#define INT_NUM_IM1_IRL6 (INT_NUM_IM1_IRL0 + 6) -+#define INT_NUM_IM1_IRL7 (INT_NUM_IM1_IRL0 + 7) -+#define INT_NUM_IM1_IRL8 (INT_NUM_IM1_IRL0 + 8) -+#define INT_NUM_IM1_IRL9 (INT_NUM_IM1_IRL0 + 9) -+#define INT_NUM_IM1_IRL10 (INT_NUM_IM1_IRL0 + 10) -+#define INT_NUM_IM1_IRL11 (INT_NUM_IM1_IRL0 + 11) -+#define INT_NUM_IM1_IRL12 (INT_NUM_IM1_IRL0 + 12) -+#define INT_NUM_IM1_IRL13 (INT_NUM_IM1_IRL0 + 13) -+#define INT_NUM_IM1_IRL14 (INT_NUM_IM1_IRL0 + 14) -+#define INT_NUM_IM1_IRL15 (INT_NUM_IM1_IRL0 + 15) -+#define INT_NUM_IM1_IRL16 (INT_NUM_IM1_IRL0 + 16) -+#define INT_NUM_IM1_IRL17 (INT_NUM_IM1_IRL0 + 17) -+#define INT_NUM_IM1_IRL18 (INT_NUM_IM1_IRL0 + 18) -+#define INT_NUM_IM1_IRL19 (INT_NUM_IM1_IRL0 + 19) -+#define INT_NUM_IM1_IRL20 (INT_NUM_IM1_IRL0 + 20) -+#define INT_NUM_IM1_IRL21 (INT_NUM_IM1_IRL0 + 21) -+#define INT_NUM_IM1_IRL22 (INT_NUM_IM1_IRL0 + 22) -+#define INT_NUM_IM1_IRL23 (INT_NUM_IM1_IRL0 + 23) -+#define INT_NUM_IM1_IRL24 (INT_NUM_IM1_IRL0 + 24) -+#define INT_NUM_IM1_IRL25 (INT_NUM_IM1_IRL0 + 25) -+#define INT_NUM_IM1_IRL26 (INT_NUM_IM1_IRL0 + 26) -+#define INT_NUM_IM1_IRL27 (INT_NUM_IM1_IRL0 + 27) -+#define INT_NUM_IM1_IRL28 (INT_NUM_IM1_IRL0 + 28) -+#define INT_NUM_IM1_IRL29 (INT_NUM_IM1_IRL0 + 29) -+#define INT_NUM_IM1_IRL30 (INT_NUM_IM1_IRL0 + 30) -+#define INT_NUM_IM1_IRL31 (INT_NUM_IM1_IRL0 + 31) -+ -+#define INT_NUM_IM2_IRL0 (INT_NUM_IRQ0 + 64) -+#define INT_NUM_IM2_IRL1 (INT_NUM_IM2_IRL0 + 1) -+#define INT_NUM_IM2_IRL2 (INT_NUM_IM2_IRL0 + 2) -+#define INT_NUM_IM2_IRL3 (INT_NUM_IM2_IRL0 + 3) -+#define INT_NUM_IM2_IRL4 (INT_NUM_IM2_IRL0 + 4) -+#define INT_NUM_IM2_IRL5 (INT_NUM_IM2_IRL0 + 5) -+#define INT_NUM_IM2_IRL6 (INT_NUM_IM2_IRL0 + 6) -+#define INT_NUM_IM2_IRL7 (INT_NUM_IM2_IRL0 + 7) -+#define INT_NUM_IM2_IRL8 (INT_NUM_IM2_IRL0 + 8) -+#define INT_NUM_IM2_IRL9 (INT_NUM_IM2_IRL0 + 9) -+#define INT_NUM_IM2_IRL10 (INT_NUM_IM2_IRL0 + 10) -+#define INT_NUM_IM2_IRL11 (INT_NUM_IM2_IRL0 + 11) -+#define INT_NUM_IM2_IRL12 (INT_NUM_IM2_IRL0 + 12) -+#define INT_NUM_IM2_IRL13 (INT_NUM_IM2_IRL0 + 13) -+#define INT_NUM_IM2_IRL14 (INT_NUM_IM2_IRL0 + 14) -+#define INT_NUM_IM2_IRL15 (INT_NUM_IM2_IRL0 + 15) -+#define INT_NUM_IM2_IRL16 (INT_NUM_IM2_IRL0 + 16) -+#define INT_NUM_IM2_IRL17 (INT_NUM_IM2_IRL0 + 17) -+#define INT_NUM_IM2_IRL18 (INT_NUM_IM2_IRL0 + 18) -+#define INT_NUM_IM2_IRL19 (INT_NUM_IM2_IRL0 + 19) -+#define INT_NUM_IM2_IRL20 (INT_NUM_IM2_IRL0 + 20) -+#define INT_NUM_IM2_IRL21 (INT_NUM_IM2_IRL0 + 21) -+#define INT_NUM_IM2_IRL22 (INT_NUM_IM2_IRL0 + 22) -+#define INT_NUM_IM2_IRL23 (INT_NUM_IM2_IRL0 + 23) -+#define INT_NUM_IM2_IRL24 (INT_NUM_IM2_IRL0 + 24) -+#define INT_NUM_IM2_IRL25 (INT_NUM_IM2_IRL0 + 25) -+#define INT_NUM_IM2_IRL26 (INT_NUM_IM2_IRL0 + 26) -+#define INT_NUM_IM2_IRL27 (INT_NUM_IM2_IRL0 + 27) -+#define INT_NUM_IM2_IRL28 (INT_NUM_IM2_IRL0 + 28) -+#define INT_NUM_IM2_IRL29 (INT_NUM_IM2_IRL0 + 29) -+#define INT_NUM_IM2_IRL30 (INT_NUM_IM2_IRL0 + 30) -+#define INT_NUM_IM2_IRL31 (INT_NUM_IM2_IRL0 + 31) -+ -+#define INT_NUM_IM3_IRL0 (INT_NUM_IRQ0 + 96) -+#define INT_NUM_IM3_IRL1 (INT_NUM_IM3_IRL0 + 1) -+#define INT_NUM_IM3_IRL2 (INT_NUM_IM3_IRL0 + 2) -+#define INT_NUM_IM3_IRL3 (INT_NUM_IM3_IRL0 + 3) -+#define INT_NUM_IM3_IRL4 (INT_NUM_IM3_IRL0 + 4) -+#define INT_NUM_IM3_IRL5 (INT_NUM_IM3_IRL0 + 5) -+#define INT_NUM_IM3_IRL6 (INT_NUM_IM3_IRL0 + 6) -+#define INT_NUM_IM3_IRL7 (INT_NUM_IM3_IRL0 + 7) -+#define INT_NUM_IM3_IRL8 (INT_NUM_IM3_IRL0 + 8) -+#define INT_NUM_IM3_IRL9 (INT_NUM_IM3_IRL0 + 9) -+#define INT_NUM_IM3_IRL10 (INT_NUM_IM3_IRL0 + 10) -+#define INT_NUM_IM3_IRL11 (INT_NUM_IM3_IRL0 + 11) -+#define INT_NUM_IM3_IRL12 (INT_NUM_IM3_IRL0 + 12) -+#define INT_NUM_IM3_IRL13 (INT_NUM_IM3_IRL0 + 13) -+#define INT_NUM_IM3_IRL14 (INT_NUM_IM3_IRL0 + 14) -+#define INT_NUM_IM3_IRL15 (INT_NUM_IM3_IRL0 + 15) -+#define INT_NUM_IM3_IRL16 (INT_NUM_IM3_IRL0 + 16) -+#define INT_NUM_IM3_IRL17 (INT_NUM_IM3_IRL0 + 17) -+#define INT_NUM_IM3_IRL18 (INT_NUM_IM3_IRL0 + 18) -+#define INT_NUM_IM3_IRL19 (INT_NUM_IM3_IRL0 + 19) -+#define INT_NUM_IM3_IRL20 (INT_NUM_IM3_IRL0 + 20) -+#define INT_NUM_IM3_IRL21 (INT_NUM_IM3_IRL0 + 21) -+#define INT_NUM_IM3_IRL22 (INT_NUM_IM3_IRL0 + 22) -+#define INT_NUM_IM3_IRL23 (INT_NUM_IM3_IRL0 + 23) -+#define INT_NUM_IM3_IRL24 (INT_NUM_IM3_IRL0 + 24) -+#define INT_NUM_IM3_IRL25 (INT_NUM_IM3_IRL0 + 25) -+#define INT_NUM_IM3_IRL26 (INT_NUM_IM3_IRL0 + 26) -+#define INT_NUM_IM3_IRL27 (INT_NUM_IM3_IRL0 + 27) -+#define INT_NUM_IM3_IRL28 (INT_NUM_IM3_IRL0 + 28) -+#define INT_NUM_IM3_IRL29 (INT_NUM_IM3_IRL0 + 29) -+#define INT_NUM_IM3_IRL30 (INT_NUM_IM3_IRL0 + 30) -+#define INT_NUM_IM3_IRL31 (INT_NUM_IM3_IRL0 + 31) -+ -+#define INT_NUM_IM4_IRL0 (INT_NUM_IRQ0 + 128) -+#define INT_NUM_IM4_IRL1 (INT_NUM_IM4_IRL0 + 1) -+#define INT_NUM_IM4_IRL2 (INT_NUM_IM4_IRL0 + 2) -+#define INT_NUM_IM4_IRL3 (INT_NUM_IM4_IRL0 + 3) -+#define INT_NUM_IM4_IRL4 (INT_NUM_IM4_IRL0 + 4) -+#define INT_NUM_IM4_IRL5 (INT_NUM_IM4_IRL0 + 5) -+#define INT_NUM_IM4_IRL6 (INT_NUM_IM4_IRL0 + 6) -+#define INT_NUM_IM4_IRL7 (INT_NUM_IM4_IRL0 + 7) -+#define INT_NUM_IM4_IRL8 (INT_NUM_IM4_IRL0 + 8) -+#define INT_NUM_IM4_IRL9 (INT_NUM_IM4_IRL0 + 9) -+#define INT_NUM_IM4_IRL10 (INT_NUM_IM4_IRL0 + 10) -+#define INT_NUM_IM4_IRL11 (INT_NUM_IM4_IRL0 + 11) -+#define INT_NUM_IM4_IRL12 (INT_NUM_IM4_IRL0 + 12) -+#define INT_NUM_IM4_IRL13 (INT_NUM_IM4_IRL0 + 13) -+#define INT_NUM_IM4_IRL14 (INT_NUM_IM4_IRL0 + 14) -+#define INT_NUM_IM4_IRL15 (INT_NUM_IM4_IRL0 + 15) -+#define INT_NUM_IM4_IRL16 (INT_NUM_IM4_IRL0 + 16) -+#define INT_NUM_IM4_IRL17 (INT_NUM_IM4_IRL0 + 17) -+#define INT_NUM_IM4_IRL18 (INT_NUM_IM4_IRL0 + 18) -+#define INT_NUM_IM4_IRL19 (INT_NUM_IM4_IRL0 + 19) -+#define INT_NUM_IM4_IRL20 (INT_NUM_IM4_IRL0 + 20) -+#define INT_NUM_IM4_IRL21 (INT_NUM_IM4_IRL0 + 21) -+#define INT_NUM_IM4_IRL22 (INT_NUM_IM4_IRL0 + 22) -+#define INT_NUM_IM4_IRL23 (INT_NUM_IM4_IRL0 + 23) -+#define INT_NUM_IM4_IRL24 (INT_NUM_IM4_IRL0 + 24) -+#define INT_NUM_IM4_IRL25 (INT_NUM_IM4_IRL0 + 25) -+#define INT_NUM_IM4_IRL26 (INT_NUM_IM4_IRL0 + 26) -+#define INT_NUM_IM4_IRL27 (INT_NUM_IM4_IRL0 + 27) -+#define INT_NUM_IM4_IRL28 (INT_NUM_IM4_IRL0 + 28) -+#define INT_NUM_IM4_IRL29 (INT_NUM_IM4_IRL0 + 29) -+#define INT_NUM_IM4_IRL30 (INT_NUM_IM4_IRL0 + 30) -+#define INT_NUM_IM4_IRL31 (INT_NUM_IM4_IRL0 + 31) -+ -+#define INT_NUM_SI_EIU_IR0 (INT_NUM_IRQ0 + 160) -+#define INT_NUM_SI_EIU_IR1 (INT_NUM_SI_EIU_IR0 + 1) -+#define INT_NUM_SI_EIU_IR2 (INT_NUM_SI_EIU_IR0 + 2) -+#define INT_NUM_SI_EIU_IR3 (INT_NUM_SI_EIU_IR0 + 3) -+#define INT_NUM_SI_EIU_IR4 (INT_NUM_SI_EIU_IR0 + 4) -+#define INT_NUM_SI_EIU_IR5 (INT_NUM_SI_EIU_IR0 + 5) -+#define INT_NUM_SI_EIU_IR6 (INT_NUM_SI_EIU_IR0 + 6) -+#define INT_NUM_SI_EIU_IR7 (INT_NUM_SI_EIU_IR0 + 7) -+#define INT_NUM_SI_EIU_IR8 (INT_NUM_SI_EIU_IR0 + 8) -+#define INT_NUM_SI_EIU_IR9 (INT_NUM_SI_EIU_IR0 + 9) -+#define INT_NUM_SI_EIU_IR10 (INT_NUM_SI_EIU_IR0 + 10) -+#define INT_NUM_SI_EIU_IR11 (INT_NUM_SI_EIU_IR0 + 11) -+#define INT_NUM_SI_EIU_IR12 (INT_NUM_SI_EIU_IR0 + 12) -+#define INT_NUM_SI_EIU_IR13 (INT_NUM_SI_EIU_IR0 + 13) -+#define INT_NUM_SI_EIU_IR14 (INT_NUM_SI_EIU_IR0 + 14) -+#define INT_NUM_SI_EIU_IR15 (INT_NUM_SI_EIU_IR0 + 15) -+ -+#define MIPS_CPU_CPUCTR_IRQ INT_NUM_IM4_IRL31 -+//#define MIPS_CPU_TIMER_IRQ (INT_NUM_SI_EIU_IR15 + 1) -+#define MIPSCPU_INT_BASE (MIPS_CPU_TIMER_IRQ + 1) -+ -+#ifdef CONFIG_MIPS_MT_SMTC -+#define MIPSCPU_INT_CPUCTR 7 -+#endif -+ -+ -+#if defined(CONFIG_DANUBE) -+#include "danube/irq.h" -+#elif defined(CONFIG_AMAZON_SE) -+#include "amazon_se/irq.h" -+#elif defined(CONFIG_AR9) -+#include "ar9/irq.h" -+#elif defined(CONFIG_VR9) -+#include "vr9/irq.h" -+#elif defined(CONFIG_AR10) -+#include "ar10/irq.h" -+#elif defined(CONFIG_HN1) -+#include "hn1/irq.h" -+#else -+#error unknown chip -+#endif -+ -+ -+extern void bsp_mask_and_ack_irq(u32 irq_nr); -+extern void bsp_enable_irq(u32 irq_nr); -+extern void bsp_disable_irq(u32 irq_nr); -+extern void ifx_icu_irsr_set(u32 irq); -+extern void ifx_icu_irsr_clr(u32 irq); -+ -+ -+#endif /* IFX_IRQ_H */ -diff --git a/arch/mips/include/asm/ifx/model.h b/arch/mips/include/asm/ifx/model.h -new file mode 100644 -index 0000000..d3b9fab ---- /dev/null -+++ b/arch/mips/include/asm/ifx/model.h -@@ -0,0 +1,50 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : common header file -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef IFX_MODEL_H -+#define IFX_MODEL_H -+ -+ -+ -+#if defined(CONFIG_DANUBE) -+# include "danube/model.h" -+#elif defined(CONFIG_AMAZON_SE) -+# include "amazon_se/model.h" -+#elif defined(CONFIG_AR9) -+# include "ar9/model.h" -+#elif defined(CONFIG_VR9) -+# include "vr9/model.h" -+#elif defined(CONFIG_AR10) -+# include "ar10/model.h" -+#elif defined(CONFIG_HN1) -+# include "hn1/model.h" -+#else -+# error unknown chip -+#endif -+ -+ -+ -+#endif // IFX_MODEL_H -+ -diff --git a/arch/mips/include/asm/ifx/vr9/emulation.h b/arch/mips/include/asm/ifx/vr9/emulation.h -new file mode 100644 -index 0000000..819523a ---- /dev/null -+++ b/arch/mips/include/asm/ifx/vr9/emulation.h -@@ -0,0 +1,46 @@ -+/****************************************************************************** -+** -+** FILE NAME : emulation.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Lei Chuan Hua -+** DESCRIPTION : header file for VR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Lei Chuan Hua The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef EMULATION_H -+#define EMULATION_H -+ -+#ifdef CONFIG_USE_EMULATOR -+ -+#ifdef CONFIG_USE_VENUS -+ #define EMULATOR_CPU_SPEED 3000000 -+ #define PLL0_CLK_SPEED 2500000 -+#elif defined(CONFIG_USE_PALLADIUM) -+ #define EMULATOR_CPU_SPEED 214000 -+ #define PLL0_CLK_SPEED 214000 -+#else -+ #define EMULATOR_CPU_SPEED 25000 -+ #define PLL0_CLK_SPEED 25000 -+#endif /* CONFIG_USE_VENUS */ -+#else /* Real chip */ -+ #define PLL0_CLK_SPEED 1000000000 -+#endif /* CONFIG_USE_EMULATOR */ -+#endif /* */ -+ /* EMULATION_H */ -+ -diff --git a/arch/mips/include/asm/ifx/vr9/irq.h b/arch/mips/include/asm/ifx/vr9/irq.h -new file mode 100644 -index 0000000..35b3d4b ---- /dev/null -+++ b/arch/mips/include/asm/ifx/vr9/irq.h -@@ -0,0 +1,196 @@ -+/****************************************************************************** -+** -+** FILE NAME : irq.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for VR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef VR9_IRQ_H -+#define VR9_IRQ_H -+ -+ -+ -+/****** Interrupt Assigments ***********/ -+ -+#define IFX_ASC1_TIR INT_NUM_IM3_IRL7 /* TX interrupt */ -+#define IFX_ASC1_TBIR INT_NUM_IM3_IRL8 /* TX buffer interrupt */ -+#define IFX_ASC1_RIR INT_NUM_IM3_IRL9 /* RX interrupt */ -+#define IFX_ASC1_EIR INT_NUM_IM3_IRL10 /* ERROR interrupt */ -+#define IFX_ASC1_ABSTIR INT_NUM_IM3_IRL11 -+#define IFX_ASC1_ABDETIR INT_NUM_IM3_IRL12 -+#define IFX_ASC1_SFCIR INT_NUM_IM3_IRL13 -+ -+#define IFX_FPI_SLAVE_BCU0_IR INT_NUM_IM1_IRL25 -+#define IFX_FPI_MASTER_COSBCU_IR INT_NUM_IM0_IRL25 -+#define IFX_CROSSBAR_ERR_IR INT_NUM_IM4_IRL23 -+#define IFX_FPI_SLAVE_BCU_IRQ IFX_FPI_SLAVE_BCU0_IR -+#define IFX_FPI_MASTER_BCU_IRQ IFX_FPI_MASTER_COSBCU_IR -+ -+#define IFX_DSL_DFE_IR INT_NUM_IM1_IRL23 -+#define IFX_DSL_AFEOVL_IR INT_NUM_IM1_IRL24 -+#define IFX_DSL_DYING_GASP_INT INT_NUM_IM1_IRL21 -+#define IFX_DSL_DFE_INT0IR INT_NUM_IM2_IRL12 -+#define IFX_DSL_DFE_INT1IR INT_NUM_IM2_IRL13 -+#define IFX_DSL_DFE_INT2IR INT_NUM_IM2_IRL14 -+#define IFX_DSL_DFE_INT3IR INT_NUM_IM2_IRL15 -+#define IFX_DSL_SI INT_NUM_IM2_IRL20 -+#define IFX_DSL_WAKEUP INT_NUM_IM2_IRL22 -+#define IFX_MEI_INT IFX_DSL_DFE_IR -+#define IFX_MEI_DYING_GASP_INT IFX_DSL_DYING_GASP_INT -+#define IFX_DSL_DFE_TXIR IFX_DSL_DFE_INT0IR -+#define IFX_DSL_DFE_RXIR IFX_DSL_DFE_INT1IR -+ -+#define IFX_PCIE_INTA INT_NUM_IM4_IRL8 -+#define IFX_PCIE_INTB INT_NUM_IM4_IRL9 -+#define IFX_PCIE_INTC INT_NUM_IM4_IRL10 -+#define IFX_PCIE_INTD INT_NUM_IM4_IRL11 -+#define IFX_PCIE_IR INT_NUM_IM4_IRL25 -+#define IFX_PCIE_WAKE INT_NUM_IM4_IRL26 -+#define IFX_PCIE_MSI_IR0 INT_NUM_IM4_IRL27 -+#define IFX_PCIE_MSI_IR1 INT_NUM_IM4_IRL28 -+#define IFX_PCIE_MSI_IR2 INT_NUM_IM4_IRL29 -+#define IFX_PCIE_MSI_IR3 INT_NUM_IM0_IRL30 -+#define IFX_PCIE_L3_INT INT_NUM_IM3_IRL16 -+ -+#define IFX_DEU_DESIR INT_NUM_IM0_IRL27 -+#define IFX_DEU_AESIR INT_NUM_IM0_IRL28 -+#define IFX_DEU_HASHIR INT_NUM_IM0_IRL29 -+#define IFX_DEU_ARCIR INT_NUM_IM0_IRL26 -+ -+#define IFX_DMA_CH0_INT INT_NUM_IM2_IRL0 -+#define IFX_DMA_CH1_INT INT_NUM_IM2_IRL1 -+#define IFX_DMA_CH2_INT INT_NUM_IM2_IRL2 -+#define IFX_DMA_CH3_INT INT_NUM_IM2_IRL3 -+#define IFX_DMA_CH4_INT INT_NUM_IM2_IRL4 -+#define IFX_DMA_CH5_INT INT_NUM_IM2_IRL5 -+#define IFX_DMA_CH6_INT INT_NUM_IM2_IRL6 -+#define IFX_DMA_CH7_INT INT_NUM_IM2_IRL7 -+#define IFX_DMA_CH8_INT INT_NUM_IM2_IRL8 -+#define IFX_DMA_CH9_INT INT_NUM_IM2_IRL9 -+#define IFX_DMA_CH10_INT INT_NUM_IM2_IRL10 -+#define IFX_DMA_CH11_INT INT_NUM_IM2_IRL11 -+#define IFX_DMA_CH12_INT INT_NUM_IM2_IRL25 -+#define IFX_DMA_CH13_INT INT_NUM_IM2_IRL26 -+#define IFX_DMA_CH14_INT INT_NUM_IM2_IRL27 -+#define IFX_DMA_CH15_INT INT_NUM_IM2_IRL28 -+#define IFX_DMA_CH16_INT INT_NUM_IM2_IRL29 -+#define IFX_DMA_CH17_INT INT_NUM_IM1_IRL30 -+#define IFX_DMA_CH18_INT INT_NUM_IM2_IRL16 -+#define IFX_DMA_CH19_INT INT_NUM_IM2_IRL21 -+#define IFX_DMA_CH20_INT INT_NUM_IM4_IRL0 -+#define IFX_DMA_CH21_INT INT_NUM_IM4_IRL1 -+#define IFX_DMA_CH22_INT INT_NUM_IM4_IRL2 -+#define IFX_DMA_CH23_INT INT_NUM_IM4_IRL3 -+#define IFX_DMA_CH24_INT INT_NUM_IM4_IRL4 -+#define IFX_DMA_CH25_INT INT_NUM_IM4_IRL5 -+#define IFX_DMA_CH26_INT INT_NUM_IM4_IRL6 -+#define IFX_DMA_CH27_INT INT_NUM_IM4_IRL7 -+#define IFX_DMA_FCC_INT INT_NUM_IM0_IRL13 -+ -+#define IFX_PPE_MBOX_INT0 INT_NUM_IM2_IRL23 -+#define IFX_PPE_MBOX_INT1 INT_NUM_IM2_IRL24 -+#define IFX_PPE_MBOX_INT2 INT_NUM_IM1_IRL29 -+#define IFX_PPE_QSB_INT INT_NUM_IM1_IRL31 -+ -+#define IFX_GE_SW_INT INT_NUM_IM1_IRL16 -+ -+#define IFX_GPHY_CD_INT INT_NUM_IM3_IRL17 -+#define IFX_GPHY_INT INT_NUM_IM3_IRL18 -+ -+#define IFX_EIU_IR0 INT_NUM_IM4_IRL30 /* 158 */ -+#define IFX_EIU_IR1 INT_NUM_IM3_IRL31 /* 127 */ -+#define IFX_EIU_IR2 INT_NUM_IM1_IRL26 /* 58 */ -+#define IFX_EIU_IR3 INT_NUM_IM1_IRL0 /* 32 */ -+#define IFX_EIU_IR4 INT_NUM_IM1_IRL1 /* 33 */ -+#define IFX_EIU_IR5 INT_NUM_IM1_IRL2 /* 34 */ -+ -+#define IFX_EIU_IR6 INT_NUM_IM2_IRL30 /* 94 */ -+#define IFX_SI_EIU_IR IFX_EIU_IR6 -+ -+#define IFX_MPS_IR0 INT_NUM_IM4_IRL14 -+#define IFX_MPS_IR1 INT_NUM_IM4_IRL15 -+#define IFX_MPS_IR2 INT_NUM_IM4_IRL16 -+#define IFX_MPS_IR3 INT_NUM_IM4_IRL17 -+#define IFX_MPS_IR4 INT_NUM_IM4_IRL18 -+#define IFX_MPS_IR5 INT_NUM_IM4_IRL19 -+#define IFX_MPS_IR6 INT_NUM_IM4_IRL20 -+#define IFX_MPS_IR7 INT_NUM_IM4_IRL21 -+#define IFX_MPS_IR8 INT_NUM_IM4_IRL22 -+#define IFX_MPS_SEMAPHORE_IR IFX_MPS_IR7 -+#define IFX_MPS_GLOBAL_IR IFX_MPS_IR8 -+ -+#define IFX_RTI_8KHZ_IR INT_NUM_IM2_IRL31 -+ -+#define IFX_GPTU_TC1A INT_NUM_IM3_IRL22 -+#define IFX_GPTU_TC1B INT_NUM_IM3_IRL23 -+#define IFX_GPTU_TC2A INT_NUM_IM3_IRL24 -+#define IFX_GPTU_TC2B INT_NUM_IM3_IRL25 -+#define IFX_GPTU_TC3A INT_NUM_IM3_IRL26 -+#define IFX_GPTU_TC3B INT_NUM_IM3_IRL27 -+ -+#define IFX_MC_IR INT_NUM_IM3_IRL28 -+ -+#define IFX_EBU_IR INT_NUM_IM0_IRL22 -+ -+#define IFX_PCI_IR INT_NUM_IM1_IRL17 -+#define IFX_PCI_WRIR INT_NUM_IM1_IRL18 -+ -+#define IFX_PCM_TXIR INT_NUM_IM1_IRL19 -+#define IFX_PCM_RXIR INT_NUM_IM1_IRL20 -+ -+#define IFX_PMCIR INT_NUM_IM4_IRL31 -+ -+#define IFX_SBIU_ERRIR INT_NUM_IM1_IRL27 -+ -+#define IFX_SSC_RIR INT_NUM_IM0_IRL14 -+#define IFX_SSC_TIR INT_NUM_IM0_IRL15 -+#define IFX_SSC_EIR INT_NUM_IM0_IRL16 -+#define IFX_SSC_FIR INT_NUM_IM0_IRL17 -+ -+#define IFX_MMC_CONTROLLER_INTR0_IRQ INT_NUM_IM0_IRL18 -+#define IFX_MMC_CONTROLLER_INTR1_IRQ INT_NUM_IM0_IRL19 -+#define IFX_MMC_CONTROLLER_SDIO_I_IRQ INT_NUM_IM0_IRL20 -+ -+#define IFX_USB0_IR INT_NUM_IM1_IRL22 -+#define IFX_USB1_IR INT_NUM_IM1_IRL16 -+#define IFX_USB0_OCIR INT_NUM_IM1_IRL28 -+#define IFX_USB1_OCIR INT_NUM_IM1_IRL24 // same as IFX_DSL_AFEOVL_IR -+#define IFX_USB_INT IFX_USB0_IR -+#define IFX_USB_OC_INT IFX_USB0_OCIR -+ -+#define IFX_WDT_AEIR INT_NUM_IM4_IRL24 -+ -+#define IFX_OVD_INT INT_NUM_IM3_IRL15 -+#define IFX_PSU_INT INT_NUM_IM3_IRL30 -+ -+#define IFX_USIF_EIR_INT INT_NUM_IM3_IRL3 -+#define IFX_USIF_STA_INT INT_NUM_IM3_IRL4 -+#define IFX_USIF_AB_INT INT_NUM_IM3_IRL5 -+#define IFX_USIF_WKP_INT INT_NUM_IM3_IRL6 -+#define IFX_USIF_TX_INT INT_NUM_IM0_IRL21 -+#define IFX_USIF_RX_INT INT_NUM_IM3_IRL21 -+ -+#define IFX_AHB1S_BUS_ERROR INT_NUM_IM3_IRL1 -+ -+ -+ -+#endif // VR9_IRQ_H -+ -diff --git a/arch/mips/include/asm/ifx/vr9/model.h b/arch/mips/include/asm/ifx/vr9/model.h -new file mode 100644 -index 0000000..ba11b36 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/vr9/model.h -@@ -0,0 +1,54 @@ -+/****************************************************************************** -+** -+** FILE NAME : model.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for VR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef VR9_MODEL_H -+#define VR9_MODEL_H -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define BOARD_SYSTEM_TYPE "VR9" -+#define SYSTEM_MODEL_NAME "VR9 First Version" -+#endif -diff --git a/arch/mips/include/asm/ifx/vr9/vr9.h b/arch/mips/include/asm/ifx/vr9/vr9.h -new file mode 100644 -index 0000000..bca6f00 ---- /dev/null -+++ b/arch/mips/include/asm/ifx/vr9/vr9.h -@@ -0,0 +1,1785 @@ -+/****************************************************************************** -+** -+** FILE NAME : vr9.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for VR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef VR9_H -+#define VR9_H -+ -+#include <asm/bootinfo.h> -+ -+/****************************************************************************** -+ Copyright (c) 2002, Infineon Technologies. All rights reserved. -+ -+ No Warranty -+ Because the program is licensed free of charge, there is no warranty for -+ the program, to the extent permitted by applicable law. Except when -+ otherwise stated in writing the copyright holders and/or other parties -+ provide the program "as is" without warranty of any kind, either -+ expressed or implied, including, but not limited to, the implied -+ warranties of merchantability and fitness for a particular purpose. The -+ entire risk as to the quality and performance of the program is with -+ you. should the program prove defective, you assume the cost of all -+ necessary servicing, repair or correction. -+ -+ In no event unless required by applicable law or agreed to in writing -+ will any copyright holder, or any other party who may modify and/or -+ redistribute the program as permitted above, be liable to you for -+ damages, including any general, special, incidental or consequential -+ damages arising out of the use or inability to use the program -+ (including but not limited to loss of data or data being rendered -+ inaccurate or losses sustained by you or third parties or a failure of -+ the program to operate with any other programs), even if such holder or -+ other party has been advised of the possibility of such damages. -+******************************************************************************/ -+#define MACH_GROUP_IFX MACH_GROUP_VR9 -+#define MACH_TYPE_IFX MACH_VR9 -+ -+ -+/***********************************************************************/ -+/* Module : WDT register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_WDT (KSEG1 | 0x1F880000) -+ -+/***Watchdog Timer Control Register ***/ -+#define IFX_WDT_CR ((volatile u32*)(IFX_WDT + 0x03F0)) -+#define IFX_WDT_CR_GEN (1 << 31) -+#define IFX_WDT_CR_DSEN (1 << 30) -+#define IFX_WDT_CR_LPEN (1 << 29) -+#define IFX_WDT_CR_PWL_GET(value) (((value) >> 26) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_PWL_SET(value) (((( 1 << 2) - 1) & (value)) << 26) -+#define IFX_WDT_CR_CLKDIV_GET(value) (((value) >> 24) & ((1 << 2) - 1)) -+#define IFX_WDT_CR_CLKDIV_SET(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_WDT_CR_PW_GET(value) (((value) >> 16) & ((1 << 8) - 1)) -+#define IFX_WDT_CR_PW_SET(value) (((( 1 << 8) - 1) & (value)) << 16) -+#define IFX_WDT_CR_RELOAD_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_CR_RELOAD_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***Watchdog Timer Status Register***/ -+#define IFX_WDT_SR ((volatile u32*)(IFX_WDT + 0x03F8)) -+#define IFX_WDT_SR_EN (1 << 31) -+#define IFX_WDT_SR_AE (1 << 30) -+#define IFX_WDT_SR_PRW (1 << 29) -+#define IFX_WDT_SR_EXP (1 << 28) -+#define IFX_WDT_SR_PWD (1 << 27) -+#define IFX_WDT_SR_DS (1 << 26) -+#define IFX_WDT_SR_VALUE_GET(value) (((value) >> 0) & ((1 << 16) - 1)) -+#define IFX_WDT_SR_VALUE_SET(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+ -+/***********************************************************************/ -+/* Module : RCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_RCU (KSEG1 | 0x1F203000) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ ((volatile u32*)(IFX_RCU + 0x0010)) -+#define IFX_RCU_RST_REQ_HOT_RST 0x00000001 /* Hot reset, domain 0*/ -+ -+#define IFX_RCU_RST_STAT ((volatile u32*)(IFX_RCU + 0x0014)) -+#define IFX_RCU_USB0_CFG ((volatile u32*)(IFX_RCU + 0x0018)) -+#define IFX_RCU_GPIO_STRAP ((volatile u32*)(IFX_RCU + 0x001C)) -+#define IFX_RCU_GPHY0_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0020)) -+#define IFX_RCU_SLIC_USB_RST_STAT ((volatile u32*)(IFX_RCU + 0x0024)) -+#define IFX_RCU_PCI_BOOT_READY ((volatile u32*)(IFX_RCU + 0x0028)) -+#define IFX_RCU_PPE_CONF ((volatile u32*)(IFX_RCU + 0x002C)) -+#define IFX_RCU_PCIE_PHY_CON_STAT ((volatile u32*)(IFX_RCU + 0x0030)) -+#define IFX_RCU_USB1_CFG ((volatile u32*)(IFX_RCU + 0x0034)) -+#define IFX_RCU_USB_AFE_CFG_1A ((volatile u32*)(IFX_RCU + 0x0038)) -+#define IFX_RCU_USB_AFE_CFG_1B ((volatile u32*)(IFX_RCU + 0x003C)) -+#define IFX_RCU_USB_AFE_CFG_2A ((volatile u32*)(IFX_RCU + 0x0040)) -+#define IFX_RCU_USB_AFE_CFG_2B ((volatile u32*)(IFX_RCU + 0x0044)) -+#define IFX_RCU_SLIC_USB_RST_REQ ((volatile u32*)(IFX_RCU + 0x0048)) -+ -+/* AHB Endian Register */ -+#define IFX_RCU_AHB_ENDIAN ((volatile u32*)(IFX_RCU + 0x004C)) -+ -+#define IFX_RCU_AHB_BE_PCIE_M 0x00000001 /* Configure AHB master port that connects to PCIe RC in big endian */ -+#define IFX_RCU_AHB_BE_XBAR_M 0x00000002 /* Configure AHB master port that connects to XBAR in big endian */ -+#define IFX_RCU_AHB_BE_USIF 0x00000004 /* Configure AHB slave port that connects to USIF in big endian */ -+#define IFX_RCU_AHB_BE_XBAR_S 0x00000008 /* Configure AHB slave port that connects to XBAR in big endian */ -+#define IFX_RCU_AHB_BE_PCIE_S 0x00000010 /* Configure AHB slave port that connects to PCIe RC in little endian */ -+#define IFX_RCU_AHB_BE_PCIE_DBI 0x00000020 /* Configure DBI module in big endian*/ -+#define IFX_RCU_AHB_BE_DC_PDI 0x00000040 /* Configure DC PDI module in big endian*/ -+#define IFX_RCU_AHB_BE_PCIE_PDI 0x00000080 /* Configure PCIE PDI module in big endian*/ -+ -+#define IFX_RCU_CPU_CFG ((volatile u32*)(IFX_RCU + 0x0060)) -+#define IFX_RCU_GPHY1_FW_ADDR ((volatile u32*)(IFX_RCU + 0x0068)) -+ -+/* Reset Request Register */ -+#define IFX_RCU_RST_REQ_GPHY0 (1 << 31) -+#define IFX_RCU_RST_REQ_SRST (1 << 30) -+#define IFX_RCU_RST_REQ_GPHY1 (1 << 29) -+#define IFX_RCU_RST_REQ_SWITCH (1 << 21) -+#define IFX_RCU_RST_REQ_MIPS0 (1 << 1) -+ -+/* CPU0, CPU1, CPUSUB, HRST, WDT0, WDT1, DMA, ETHPHY1, ETHPHY0 */ -+#define IFX_RCU_RST_REQ_ALL (IFX_RCU_RST_REQ_SRST | IFX_RCU_RST_REQ_GPHY0 | IFX_RCU_RST_REQ_GPHY1 | IFX_RCU_RST_REQ_MIPS0) -+ -+#define IFX_RCU_RST_REQ_DFE (1 << 7) -+#define IFX_RCU_RST_REQ_AFE (1 << 11) -+#define IFX_RCU_RST_REQ_ARC_JTAG (1 << 20) -+ -+ -+/***********************************************************************/ -+/* Module : BCU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_BCU_BASE_ADDR (KSEG1 | 0x1E100000) -+#define IFX_SLAVE_BCU_BASE_ADDR (KSEG1 | 0x1C200400) -+ -+/***BCU Control Register (0010H)***/ -+#define IFX_BCU_CON ((volatile u32*)(0x0010 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_CON ((volatile u32*)(0x0010 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_STARVATION_MASK (0xFF << 24) -+#define IFX_BCU_STARVATION_SHIFT 24 -+#define IFX_BCU_TOUT_MASK 0xFFFF -+#define IFX_BCU_CON_SPC(value) (((( 1 << 8) - 1) & (value)) << 24) -+#define IFX_BCU_CON_SPE (1 << 19) -+#define IFX_BCU_CON_PSE (1 << 18) -+#define IFX_BCU_CON_DBG (1 << 16) -+#define IFX_BCU_CON_TOUT(value) (((( 1 << 16) - 1) & (value)) << 0) -+ -+/***BCU Error Control Capture Register (0020H)***/ -+#define IFX_BCU_ECON ((volatile u32*)(0x0020 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_ECON ((volatile u32*)(0x0020 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_ECON_TAG(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_BCU_ECON_RDN (1 << 23) -+#define IFX_BCU_ECON_WRN (1 << 22) -+#define IFX_BCU_ECON_SVM (1 << 21) -+#define IFX_BCU_ECON_ACK(value) (((( 1 << 2) - 1) & (value)) << 19) -+#define IFX_BCU_ECON_ABT (1 << 18) -+#define IFX_BCU_ECON_RDY (1 << 17) -+#define IFX_BCU_ECON_TOUT (1 << 16) -+#define IFX_BCU_ECON_ERRCNT(value) (((( 1 << 16) - 1) & (value)) << 0) -+#define IFX_BCU_ECON_OPC(value) (((( 1 << 4) - 1) & (value)) << 28) -+ -+/***BCU Error Address Capture Register (0024 H)***/ -+#define IFX_BCU_EADD ((volatile u32*)(0x0024 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EADD ((volatile u32*)(0x0024 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+/***BCU Error Data Capture Register (0028H)***/ -+#define IFX_BCU_EDAT ((volatile u32*)(0x0028 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_EDAT ((volatile u32*)(0x0028 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNEN ((volatile u32*)(0x00F4 + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNICR ((volatile u32*)(0x00FC + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNICR ((volatile u32*)(0x00FC + IFX_SLAVE_BCU_BASE_ADDR)) -+#define IFX_BCU_IRNCR ((volatile u32*)(0x00F8 + IFX_BCU_BASE_ADDR)) -+#define IFX_SLAVE_BCU_IRNCR ((volatile u32*)(0x00F8 + IFX_SLAVE_BCU_BASE_ADDR)) -+ -+ -+/***********************************************************************/ -+/* Module : HSNAND register address and bits */ -+/***********************************************************************/ -+#define IFX_HSNAND_BASE (KSEG1 | 0x1E100400) -+ -+/****** HSNAND REGISTERS *******/ -+#define IFX_NDAC_CTL1 ((volatile u32*)(0x0010 + IFX_HSNAND_BASE)) -+#define IFX_NDAC_CTL2 ((volatile u32*)(0x0014 + IFX_HSNAND_BASE)) -+#define IFX_BASE_A ((volatile u32*)(0x0018 + IFX_HSNAND_BASE)) -+#define IFX_RX_CNT ((volatile u32*)(0x001C + IFX_HSNAND_BASE)) -+#define IFX_DPLUS_CTRL ((volatile u32*)(0x0020 + IFX_HSNAND_BASE)) -+#define IFX_HSNAND_INTR_MASK_CTRL ((volatile u32*)(0x0024 + IFX_HSNAND_BASE)) -+#define IFX_HSNAND_INTR_STAT ((volatile u32*)(0x0028 + IFX_HSNAND_BASE)) -+#define IFX_HSMD_CTRL ((volatile u32*)(0x0030 + IFX_HSNAND_BASE)) -+#define IFX_CS_BASE_A ((volatile u32*)(0x0034 + IFX_HSNAND_BASE)) -+#define IFX_NAND_INFO ((volatile u32*)(0X0038 + IFX_HSNAND_BASE)) -+ -+#define IFX_HSNAND_CE_SEL (0xF<<3) -+#define IFX_HSNAND_CE_SEL_S 3 -+#define IFX_HSNAND_CE_SEL_NONE 0 -+#define IFX_HSNAND_CE_SEL_CS0 1 -+#define IFX_HSNAND_CE_SEL_CS1 2 -+#define IFX_HSNAND_CE_SEL_CS2 4 -+#define IFX_HSNAND_CE_SEL_CS3 8 -+ -+#define IFX_HSNAND_FSM (1<<2) -+#define IFX_HSNAND_FSM_S 2 -+enum { -+ IFX_HSNAND_FSM_DISABLED = 0, -+ IFX_HSNAND_FSM_ENABLED, -+}; -+ -+#define IFX_HSNAND_ENR (3<<0) -+#define IFX_HSNAND_ENR_S 0 -+enum { -+ IFX_HSNAND_ENR_XIP = 0, -+ IFX_HSNAND_ENR_HSDMA, -+ IFX_HSNAND_ENR_IO, -+ IFX_HSNAND_ENR_NONE -+}; -+ -+#define IFX_HSNAND_XFER_SEL (7<<0) -+#define IFX_HSNAND_XFER_SEL_S 7 -+enum { -+ IFX_HSNAND_NO_XFER = 0, -+ IFX_HSNAND_START_XFER -+}; -+ -+/***********************************************************************/ -+/* Module : MEI register address and bits */ -+/***********************************************************************/ -+ -+#define IFXMIPS_MEI_BASE_ADDR (KSEG1 | 0x1E116000) -+#define IFX_DFE_LDST_BASE_ADDR (KSEG1 | 0x1EF00000) -+ -+/*** Register address offsets, relative to MEI_SPACE_ADDRESS ***/ -+#if 0 -+#define MEI_DATA_XFR ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_VERSION ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_ARC_GP_STAT ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DATA_XFR_STAT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XFR_ADDR ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_MAX_WAIT ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_TO_ARC_INT ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) -+#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) -+#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_WAD ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_RAD ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_DATA ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_DEC ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_CONFIG ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_RST_CONTROL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DBG_MASTER ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_CLK_CONTROL ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_BIST_CONTROL ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_BIST_STAT ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XDATA_BASE_SH ((volatile u32*)(0x004c + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XDATA_BASE ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR0 ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR1 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR2 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR3 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR4 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR5 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR6 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR7 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR8 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR9 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR10 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR11 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR12 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR13 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR14 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR15 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR16 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) -+ -+ -+#define MEI_VERSION ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) -+#define ARC_TO_MEI_INT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) -+#define ARC_TO_MEI_INT_MASK ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_TO_ARC_INT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_CLK_CONTROL ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_RST_CONTROL ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DBG_MASTER ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_DEC ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_RAD ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_WAD ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DEBUG_DATA ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XFR_ADDR ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DATA_XFR ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_DATA_XFR_STAT ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_MAX_WAIT ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_ARC_GP_STAT ((volatile u32*)(0x004C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XDATA_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR0 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR1 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR2 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR3 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR4 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR5 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR6 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR7 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR8 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR9 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR10 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR11 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR12 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR13 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR14 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR15 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) -+#define MEI_XMEM_BAR16 ((volatile u32*)(0x0098 + IFXMIPS_MEI_BASE_ADDR)) -+//#else -+#define ME_VERSION ((volatile u32*)(0x0000 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ARC2ME_STAT ((volatile u32*)(0x0004 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ARC2ME_MASK ((volatile u32*)(0x0008 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ME2ARC_INT ((volatile u32*)(0x000C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ME2ARC_STAT ((volatile u32*)(0x0010 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_CLK_CTRL ((volatile u32*)(0x0014 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_RST_CTRL ((volatile u32*)(0x0018 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_CHIP_CONFIG ((volatile u32*)(0x001C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_MASTER ((volatile u32*)(0x0020 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_DECODE ((volatile u32*)(0x0024 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_PORT_SEL ((volatile u32*)(0x0028 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_RD_AD ((volatile u32*)(0x002C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_WR_AD ((volatile u32*)(0x0030 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DBG_DATA ((volatile u32*)(0x0034 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_PORT_SEL ((volatile u32*)(0x0038 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_AD ((volatile u32*)(0x003C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_DATA ((volatile u32*)(0x0040 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_STAT ((volatile u32*)(0x0044 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_DX_MWS ((volatile u32*)(0x0048 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_ARC_GP_STAT ((volatile u32*)(0x004C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XDATA_BASE_SH ((volatile u32*)(0x0050 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XDATA_BASE ((volatile u32*)(0x0054 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR_BASE ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR0 ((volatile u32*)(0x0058 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR1 ((volatile u32*)(0x005C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR2 ((volatile u32*)(0x0060 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR3 ((volatile u32*)(0x0064 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR4 ((volatile u32*)(0x0068 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR5 ((volatile u32*)(0x006C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR6 ((volatile u32*)(0x0070 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR7 ((volatile u32*)(0x0074 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR8 ((volatile u32*)(0x0078 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR9 ((volatile u32*)(0x007C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR10 ((volatile u32*)(0x0080 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR11 ((volatile u32*)(0x0084 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR12 ((volatile u32*)(0x0088 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR13 ((volatile u32*)(0x008C + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR14 ((volatile u32*)(0x0090 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR15 ((volatile u32*)(0x0094 + IFXMIPS_MEI_BASE_ADDR)) -+#define ME_XMEM_BAR16 ((volatile u32*)(0x0098 + IFXMIPS_MEI_BASE_ADDR)) -+#endif -+ -+ -+/***********************************************************************/ -+/* Module : GPIO register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_GPIO (KSEG1 | 0x1E100B00) -+ -+/***Port 0 Data Output Register (0010H)***/ -+#define IFX_GPIO_P0_OUT ((volatile u32 *)(IFX_GPIO + 0x0010)) -+/***Port 1 Data Output Register (0040H)***/ -+#define IFX_GPIO_P1_OUT ((volatile u32 *)(IFX_GPIO + 0x0040)) -+/***Port 2 Data Output Register (0070H)***/ -+#define IFX_GPIO_P2_OUT ((volatile u32 *)(IFX_GPIO + 0x0070)) -+/***Port 3 Data Output Register (00A0H)***/ -+#define IFX_GPIO_P3_OUT ((volatile u32 *)(IFX_GPIO + 0x00A0)) -+/***Port 0 Data Input Register (0014H)***/ -+#define IFX_GPIO_P0_IN ((volatile u32 *)(IFX_GPIO + 0x0014)) -+/***Port 1 Data Input Register (0044H)***/ -+#define IFX_GPIO_P1_IN ((volatile u32 *)(IFX_GPIO + 0x0044)) -+/***Port 2 Data Input Register (0074H)***/ -+#define IFX_GPIO_P2_IN ((volatile u32 *)(IFX_GPIO + 0x0074)) -+/***Port 3 Data Input Register (00A4H)***/ -+#define IFX_GPIO_P3_IN ((volatile u32 *)(IFX_GPIO + 0x00A4)) -+/***Port 0 Direction Register (0018H)***/ -+#define IFX_GPIO_P0_DIR ((volatile u32 *)(IFX_GPIO + 0x0018)) -+/***Port 1 Direction Register (0048H)***/ -+#define IFX_GPIO_P1_DIR ((volatile u32 *)(IFX_GPIO + 0x0048)) -+/***Port 2 Direction Register (0078H)***/ -+#define IFX_GPIO_P2_DIR ((volatile u32 *)(IFX_GPIO + 0x0078)) -+/***Port 3 Direction Register (0048H)***/ -+#define IFX_GPIO_P3_DIR ((volatile u32 *)(IFX_GPIO + 0x00A8)) -+/***Port 0 Alternate Function Select Register 0 (001C H) ***/ -+#define IFX_GPIO_P0_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x001C)) -+/***Port 1 Alternate Function Select Register 0 (004C H) ***/ -+#define IFX_GPIO_P1_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x004C)) -+/***Port 2 Alternate Function Select Register 0 (007C H) ***/ -+#define IFX_GPIO_P2_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x007C)) -+/***Port 3 Alternate Function Select Register 0 (00AC H) ***/ -+#define IFX_GPIO_P3_ALTSEL0 ((volatile u32 *)(IFX_GPIO + 0x00AC)) -+/***Port 0 Alternate Function Select Register 1 (0020 H) ***/ -+#define IFX_GPIO_P0_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0020)) -+/***Port 1 Alternate Function Select Register 0 (0050 H) ***/ -+#define IFX_GPIO_P1_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0050)) -+/***Port 2 Alternate Function Select Register 0 (0080 H) ***/ -+#define IFX_GPIO_P2_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0080)) -+/***Port 3 Alternate Function Select Register 0 (0064 H) ***/ -+#define IFX_GPIO_P3_ALTSEL1 ((volatile u32 *)(IFX_GPIO + 0x0064)) -+/***Port 0 Open Drain Control Register (0024H)***/ -+#define IFX_GPIO_P0_OD ((volatile u32 *)(IFX_GPIO + 0x0024)) -+/***Port 1 Open Drain Control Register (0054H)***/ -+#define IFX_GPIO_P1_OD ((volatile u32 *)(IFX_GPIO + 0x0054)) -+/***Port 2 Open Drain Control Register (0084H)***/ -+#define IFX_GPIO_P2_OD ((volatile u32 *)(IFX_GPIO + 0x0084)) -+/***Port 3 Open Drain Control Register (0034H)***/ -+#define IFX_GPIO_P3_OD ((volatile u32 *)(IFX_GPIO + 0x0034)) -+/***Port 0 Input Schmitt-Trigger Off Register (0028 H) ***/ -+#define IFX_GPIO_P0_STOFF ((volatile u32 *)(IFX_GPIO + 0x0028)) -+/***Port 1 Input Schmitt-Trigger Off Register (0058 H) ***/ -+#define IFX_GPIO_P1_STOFF ((volatile u32 *)(IFX_GPIO + 0x0058)) -+/***Port 2 Input Schmitt-Trigger Off Register (0088 H) ***/ -+#define IFX_GPIO_P2_STOFF ((volatile u32 *)(IFX_GPIO + 0x0088)) -+/***Port 3 Input Schmitt-Trigger Off Register (0094 H) ***/ -+ -+/***Port 0 Pull Up/Pull Down Select Register (002C H)***/ -+#define IFX_GPIO_P0_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x002C)) -+/***Port 1 Pull Up/Pull Down Select Register (005C H)***/ -+#define IFX_GPIO_P1_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x005C)) -+/***Port 2 Pull Up/Pull Down Select Register (008C H)***/ -+#define IFX_GPIO_P2_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x008C)) -+/***Port 3 Pull Up/Pull Down Select Register (0038 H)***/ -+#define IFX_GPIO_P3_PUDSEL ((volatile u32 *)(IFX_GPIO + 0x0038)) -+/***Port 0 Pull Up Device Enable Register (0030 H)***/ -+#define IFX_GPIO_P0_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0030)) -+/***Port 1 Pull Up Device Enable Register (0060 H)***/ -+#define IFX_GPIO_P1_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0060)) -+/***Port 2 Pull Up Device Enable Register (0090 H)***/ -+#define IFX_GPIO_P2_PUDEN ((volatile u32 *)(IFX_GPIO + 0x0090)) -+/***Port 3 Pull Up Device Enable Register (003c H)***/ -+#define IFX_GPIO_P3_PUDEN ((volatile u32 *)(IFX_GPIO + 0x003C)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : CGU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_CGU (KSEG1 | 0x1F103000) -+ -+/***CGU Clock PLL0 ***/ -+#define IFX_CGU_PLL0_CFG ((volatile u32*)(IFX_CGU + 0x0004)) -+/***CGU Clock PLL1 ***/ -+#define IFX_CGU_PLL1_CFG ((volatile u32*)(IFX_CGU + 0x0008)) -+/***CGU Clock PLL2 ***/ -+#define IFX_CGU_PLL2_CFG ((volatile u32*)(IFX_CGU + 0x0060)) -+/***CGU Clock SYS Mux Register***/ -+#define IFX_CGU_SYS ((volatile u32*)(IFX_CGU + 0x000C)) -+/***CGU CGU Clock Frequency Select Register***/ -+#define IFX_CGU_CLKFSR ((volatile u32*)(IFX_CGU + 0x0010)) -+/**Update CGU Register***/ -+#define IFX_CGU_UPDATE ((volatile u32*)(IFX_CGU + 0x0020)) -+/***CGU Interface Clock Control Register***/ -+#define IFX_CGU_IF_CLK ((volatile u32*)(IFX_CGU + 0x0024)) -+/***CGU PCI Clock Control Register**/ -+#define IFX_CGU_PCI_CR ((volatile u32*)(IFX_CGU + 0x0038)) -+ -+#define IFX_PCI_CLK_SHIFT 20 -+#define IFX_PCI_CLK_MASK (0x1F << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_33MHZ (0xe << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_60MHZ (0x7 << IFX_PCI_CLK_SHIFT) -+#define IFX_PCI_INTERNAL_CLK_SRC 0x00010000 /* Internal means output */ -+ -+#define IFX_PCI_CLK_FROM_CGU 0x80000000 -+#define IFX_PCI_CLK_RESET_FROM_CGU 0x40000000 -+#define IFX_PCI_DELAY_SHIFT 21 -+#define IFX_PCI_DELAY_MASK (0x7 << IFX_PCI_DELAY_SHIFT) -+ -+/***GPHY1 Configuration Register**/ -+#define IFX_GPHY1_CFG ((volatile u32*)(IFX_CGU + 0x0040)) -+#define IFX_SSC_HIGH_BAUD_DELAY_MASK 0x00000060 -+#define IFX_SSC_HIGH_BAUD_DELAY_TWO_HALF_CLOCK 0x00000020 -+#define IFX_SSC_HIGH_BAUD_DELAY_THREE_CLOCK 0x00000040 -+#define IFX_SSC_HIGH_BAUD_DELAY_THREE_HALF_CLOCK 0x00000060 -+ -+ -+/***********************************************************************/ -+/* Module : MCD register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MCD (KSEG1 | 0x1F106000) -+ -+/***Manufacturer Identification Register***/ -+#define IFX_MCD_MANID ((volatile u32*)(IFX_MCD + 0x0024)) -+#define IFX_MCD_MANID_MANUF(value) (((( 1 << 11) - 1) & (value)) << 5) -+ -+/***Chip Identification Register***/ -+#define IFX_MCD_CHIPID ((volatile u32*)(IFX_MCD + 0x0028)) -+#define IFX_MCD_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MCD_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MCD_CHIPID_PART_NUMBER_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MCD_CHIPID_PART_NUMBER_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MCD_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 11) - 1)) -+#define IFX_MCD_CHIPID_MANID_SET(value) (((( 1 << 11) - 1) & (value)) << 1) -+ -+#define IFX_CHIPID_STANDARD 0x00EB -+#define IFX_CHIPID_YANGTSE 0x00ED -+ -+/***Redesign Tracing Identification Register***/ -+#define IFX_MCD_RTID ((volatile u32*)(IFX_MCD + 0x002C)) -+#define IFX_MCD_RTID_LC (1 << 15) -+#define IFX_MCD_RTID_RIX(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : EBU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_EBU (KSEG1 | 0x1E105300) -+ -+/***EBU Clock Control Register***/ -+#define IFX_EBU_CLC ((volatile u32*)(IFX_EBU + 0x0000)) -+#define IFX_EBU_CLC_DISS (1 << 1) -+#define IFX_EBU_CLC_DISR (1 << 0) -+ -+#define IFX_EBU_ID ((volatile u32*)(IFX_EBU + 0x0008)) -+ -+/***EBU Global Control Register***/ -+#define IFX_EBU_CON ((volatile u32*)(IFX_EBU + 0x0010)) -+#define IFX_EBU_CON_DTACS(value) (((( 1 << 3) - 1) & (value)) << 20) -+#define IFX_EBU_CON_DTARW(value) (((( 1 << 3) - 1) & (value)) << 16) -+#define IFX_EBU_CON_TOUTC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_EBU_CON_ARBMODE(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_CON_ARBSYNC (1 << 5) -+ -+/***EBU Address Select Register 0***/ -+#define IFX_EBU_ADDSEL0 ((volatile u32*)(IFX_EBU + 0x0020)) -+#define IFX_EBU_ADDSEL0_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL0_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL0_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL0_REGEN (1 << 0) -+ -+/***EBU Address Select Register 1***/ -+#define IFX_EBU_ADDSEL1 ((volatile u32*)(IFX_EBU + 0x0024)) -+#define IFX_EBU_ADDSEL1_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL1_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL1_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL1_REGEN (1 << 0) -+ -+/***EBU Address Select Register 2***/ -+#define IFX_EBU_ADDSEL2 ((volatile u32*)(IFX_EBU + 0x0028)) -+#define IFX_EBU_ADDSEL2_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL2_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL2_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL2_REGEN (1 << 0) -+ -+/***EBU Address Select Register 3***/ -+#define IFX_EBU_ADDSEL3 ((volatile u32*)(IFX_EBU + 0x002C)) -+#define IFX_EBU_ADDSEL3_BASE(value) (((( 1 << 20) - 1) & (value)) << 12) -+#define IFX_EBU_ADDSEL3_MASK(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_EBU_ADDSEL3_MIRRORE (1 << 1) -+#define IFX_EBU_ADDSEL3_REGEN (1 << 0) -+ -+/***EBU Bus Configuration Register 0***/ -+#define IFX_EBU_BUSCON0 ((volatile u32*)(IFX_EBU+ 0x0060)) -+ -+#define IFX_EBU_BUSCON0_CMULT 0x00000003 -+#define IFX_EBU_BUSCON0_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON0_CMULT1 = 0, -+ IFX_EBU_BUSCON0_CMULT4, -+ IFX_EBU_BUSCON0_CMULT8, -+ IFX_EBU_BUSCON0_CMULT16, /* Default after reset */ -+}; -+ -+#define IFX_EBU_BUSCON0_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON0_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON0_RECOVC0 = 0, -+ IFX_EBU_BUSCON0_RECOVC1, -+ IFX_EBU_BUSCON0_RECOVC2, -+ IFX_EBU_BUSCON0_RECOVC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON0_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON0_HOLDC0 = 0, -+ IFX_EBU_BUSCON0_HOLDC1, -+ IFX_EBU_BUSCON0_HOLDC2, -+ IFX_EBU_BUSCON0_HOLDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON0_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON0_WAITRDC0 = 0, -+ IFX_EBU_BUSCON0_WAITRDC1, -+ IFX_EBU_BUSCON0_WAITRDC2, -+ IFX_EBU_BUSCON0_WAITRDC3, /* Default */ -+}; -+#define IFX_EBU_BUSCON0_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON0_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON0_WAITWRC0 = 0, -+ IFX_EBU_BUSCON0_WAITWRC1, -+ IFX_EBU_BUSCON0_WAITWRC2, -+ IFX_EBU_BUSCON0_WAITWRC3, -+ IFX_EBU_BUSCON0_WAITWRC4, -+ IFX_EBU_BUSCON0_WAITWRC5, -+ IFX_EBU_BUSCON0_WAITWRC6, -+ IFX_EBU_BUSCON0_WAITWRC7, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON0_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON0_BCGEN_CS = 0, -+ IFX_EBU_BUSCON0_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON0_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON0_BCGEN_RES, -+}; -+ -+#define IFX_EBU_BUSCON0_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON0_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON0_ALEC0 = 0, -+ IFX_EBU_BUSCON0_ALEC1, -+ IFX_EBU_BUSCON0_ALEC2, -+ IFX_EBU_BUSCON0_ALEC3, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_XDM 0x00030000 -+#define IFX_EBU_BUSCON0_XDM_S 16 -+enum { -+ IFX_EBU_BUSCON0_XDM8 = 0, -+ IFX_EBU_BUSCON0_XDM16, /* Default */ -+}; -+ -+#define IFX_EBU_BUSCON0_VN_EN 0x00040000 -+ -+#define IFX_EBU_BUSCON0_WAITINV_HI 0x00080000 /* low by default */ -+ -+#define IFX_EBU_BUSCON0_WAIT 0x00300000 -+#define IFX_EBU_BUSCON0_WAIT_S 20 -+enum { -+ IFX_EBU_BUSCON0_WAIT_DISABLE = 0, -+ IFX_EBU_BUSCON0_WAIT_ASYNC, -+ IFX_EBU_BUSCON0_WAIT_SYNC, -+}; -+#define IFX_EBU_BUSCON0_SETUP_EN 0x00400000 /* Disable by default */ -+ -+#define IFX_EBU_BUSCON0_AGEN 0x07000000 -+#define IFX_EBU_BUSCON0_AGEN_S 24 -+enum { -+ IFX_EBU_BUSCON0_AGEN_DEMUX = 0, /* Default */ -+ IFX_EBU_BUSCON0_AGEN_RES, -+ IFX_EBU_BUSCON0_AGEN_MUX, -+}; -+ -+#define IFX_EBU_BUSCON0_PG_EN 0x20000000 -+#define IFX_EBU_BUSCON0_ADSWP 0x40000000 /* Disable by default */ -+#define IFX_EBU_BUSCON0_WRDIS 0x80000000 /* Disable by default */ -+ -+/***EBU Bus Configuration Register 1***/ -+#define IFX_EBU_BUSCON1 ((volatile u32*)(IFX_EBU + 0x0064)) -+#define IFX_EBU_BUSCON1_CMULT 0x00000003 -+#define IFX_EBU_BUSCON1_CMULT_S 0 -+enum { -+ IFX_EBU_BUSCON1_CMULT1 = 0, -+ IFX_EBU_BUSCON1_CMULT4, -+ IFX_EBU_BUSCON1_CMULT8, -+ IFX_EBU_BUSCON1_CMULT16, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_BUSCON1_RECOVC 0x00000000c -+#define IFX_EBU_BUSCON1_RECOVC_S 2 -+enum { -+ IFX_EBU_BUSCON1_RECOVC0 = 0, -+ IFX_EBU_BUSCON1_RECOVC1, -+ IFX_EBU_BUSCON1_RECOVC2, -+ IFX_EBU_BUSCON1_RECOVC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_HOLDC 0x00000030 -+#define IFX_EBU_BUSCON1_HOLDC_S 4 -+enum { -+ IFX_EBU_BUSCON1_HOLDC0 = 0, -+ IFX_EBU_BUSCON1_HOLDC1, -+ IFX_EBU_BUSCON1_HOLDC2, -+ IFX_EBU_BUSCON1_HOLDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITRDC 0x000000c0 -+#define IFX_EBU_BUSCON1_WAITRDC_S 6 -+enum { -+ IFX_EBU_BUSCON1_WAITRDC0 = 0, -+ IFX_EBU_BUSCON1_WAITRDC1, -+ IFX_EBU_BUSCON1_WAITRDC2, -+ IFX_EBU_BUSCON1_WAITRDC3, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_WAITWRC 0x00000700 -+#define IFX_EBU_BUSCON1_WAITWRC_S 8 -+enum { -+ IFX_EBU_BUSCON1_WAITWRC0 = 0, -+ IFX_EBU_BUSCON1_WAITWRC1, -+ IFX_EBU_BUSCON1_WAITWRC2, -+ IFX_EBU_BUSCON1_WAITWRC3, -+ IFX_EBU_BUSCON1_WAITWRC4, -+ IFX_EBU_BUSCON1_WAITWRC5, -+ IFX_EBU_BUSCON1_WAITWRC6, -+ IFX_EBU_BUSCON1_WAITWRC7, /* Default */ -+ }; -+#define IFX_EBU_BUSCON1_BCGEN 0x00003000 -+#define IFX_EBU_BUSCON1_BCGEN_S 12 -+enum { -+ IFX_EBU_BUSCON1_BCGEN_CS = 0, -+ IFX_EBU_BUSCON1_BCGEN_INTEL, /* Default */ -+ IFX_EBU_BUSCON1_BCGEN_MOTOROLA, -+ IFX_EBU_BUSCON1_BCGEN_RES, -+ }; -+#define IFX_EBU_BUSCON1_ALEC 0x0000c000 -+#define IFX_EBU_BUSCON1_ALEC_S 14 -+enum { -+ IFX_EBU_BUSCON1_ALEC0 = 0, -+ IFX_EBU_BUSCON1_ALEC1, -+ IFX_EBU_BUSCON1_ALEC2, -+ IFX_EBU_BUSCON1_ALEC3, /* Default */ -+ }; -+ -+#define IFX_EBU_BUSCON1_SETUP (1 << 22) -+ -+#define IFX_EBU_BUSCON1_WRDIS (1 << 31) -+//#define IFX_EBU_BUSCON1_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+//#define IFX_EBU_BUSCON1_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+//#define IFX_EBU_BUSCON1_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+//#define IFX_EBU_BUSCON1_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+//#define IFX_EBU_BUSCON1_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+//#define IFX_EBU_BUSCON1_WAITINV (1 << 19) -+//#define IFX_EBU_BUSCON1_SETUP (1 << 18) -+//#define IFX_EBU_BUSCON1_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+//#define IFX_EBU_BUSCON1_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+//#define IFX_EBU_BUSCON1_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+//#define IFX_EBU_BUSCON1_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+//#define IFX_EBU_BUSCON1_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+//#define IFX_EBU_BUSCON1_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON2 ((volatile u32*)(IFX_EBU + 0x0068)) -+#define IFX_EBU_BUSCON2_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON2_ALEC(value) (((( 1 << 2) - 1) & (value)) << 29) -+#define IFX_EBU_BUSCON2_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 27) -+#define IFX_EBU_BUSCON2_AGEN(value) (((( 1 << 2) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON2_CMULTR(value) (((( 1 << 2) - 1) & (value)) << 22) -+#define IFX_EBU_BUSCON2_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON2_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON2_SETUP (1 << 18) -+#define IFX_EBU_BUSCON2_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON2_WAITRDC(value) (((( 1 << 7) - 1) & (value)) << 9) -+#define IFX_EBU_BUSCON2_WAITWRC(value) (((( 1 << 3) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON2_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON2_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON2_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/***EBU Bus Configuration Register 2***/ -+#define IFX_EBU_BUSCON3 ((volatile u32*)(IFX_EBU + 0x006C)) -+#define IFX_EBU_BUSCON3_WRDIS (1 << 31) -+#define IFX_EBU_BUSCON3_ADSWP(value) (1 << 30) -+#define IFX_EBU_BUSCON3_PG_EN(value) (1 << 29) -+#define IFX_EBU_BUSCON3_AGEN(value) (((( 1 << 3) - 1) & (value)) << 24) -+#define IFX_EBU_BUSCON3_SETUP (1 << 22) -+#define IFX_EBU_BUSCON3_WAIT(value) (((( 1 << 2) - 1) & (value)) << 20) -+#define IFX_EBU_BUSCON3_WAITINV (1 << 19) -+#define IFX_EBU_BUSCON3_VN_EN (1 << 18) -+#define IFX_EBU_BUSCON3_PORTW(value) (((( 1 << 2) - 1) & (value)) << 16) -+#define IFX_EBU_BUSCON3_ALEC(value) (((( 1 << 2) - 1) & (value)) << 14) -+#define IFX_EBU_BUSCON3_BCGEN(value) (((( 1 << 2) - 1) & (value)) << 12) -+#define IFX_EBU_BUSCON3_WAITWDC(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_EBU_BUSCON3_WAITRRC(value) (((( 1 << 2) - 1) & (value)) << 6) -+#define IFX_EBU_BUSCON3_HOLDC(value) (((( 1 << 2) - 1) & (value)) << 4) -+#define IFX_EBU_BUSCON3_RECOVC(value) (((( 1 << 2) - 1) & (value)) << 2) -+#define IFX_EBU_BUSCON3_CMULT(value) (((( 1 << 2) - 1) & (value)) << 0) -+ -+/* PC-Card Configuration */ -+#define IFX_EBU_PCC_CON ((volatile u32*)(IFX_EBU+ 0x0090)) -+#define IFX_EBU_PCC_CON_PCCARD_ON 0x00000001 -+#define IFX_EBU_PCC_CON_IREQ_RISING_EDGE 0x00000002 -+#define IFX_EBU_PCC_CON_IREQ_FALLING_EDGE 0x00000004 -+#define IFX_EBU_PCC_CON_IREQ_BOTH_EDGE 0x00000006 -+#define IFX_EBU_PCC_CON_IREQ_DIS 0x00000008 -+#define IFX_EBU_PCC_CON_IREQ_HIGH_LEVEL_DETECT 0x0000000A -+#define IFX_EBU_PCC_CON_IREQ_LOW_LEVEL_DETECT 0x0000000C -+ -+#define IFX_EBU_PCC_STAT ((volatile u32*)(IFX_EBU+ 0x0094)) -+#define IFX_EBU_PCC_ISTAT ((volatile u32*)(IFX_EBU+ 0x00A0)) -+#define IFX_EBU_PCC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) -+#define IFX_EBU_PCC_IEN_PCI_EN 0x00000010 -+ -+#define IFX_EBU_PCC_INT_OUT ((volatile u32*)(IFX_EBU+ 0x00A8)) -+#define IFX_EBU_PCC_IRS ((volatile u32*)(IFX_EBU+ 0x00AC)) -+ -+#define IFX_EBU_ECC_IEN ((volatile u32*)(IFX_EBU+ 0x00A4)) -+#define IFX_EBU_NAND_CON (volatile u32*)(IFX_EBU + 0xB0) -+#define IFX_EBU_NAND_WAIT (volatile u32*)(IFX_EBU + 0xB4) -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+#define IFX_EBU_NAND_ECC_CR (volatile u32*)(IFX_EBU + 0xC0) -+#define IFX_EBU_NAND_CON_NANDM (1<<0) -+#define IFX_EBU_NAND_CON_NANDM_S 0 -+enum { -+ IFX_EBU_NAND_CON_NANDM_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_NANDM_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_CSMUX_E (1<<1) -+#define IFX_EBU_NAND_CON_CSMUX_E_S 1 -+enum { -+ IFX_EBU_NAND_CON_CSMUX_E_DISABLE = 0,/* Default after reset */ -+ IFX_EBU_NAND_CON_CSMUX_E_ENABLE, -+ }; -+ -+#define IFX_EBU_NAND_CON_ALE_P (1<<2) -+#define IFX_EBU_NAND_CON_ALE_P_S 2 -+enum { -+ IFX_EBU_NAND_CON_ALE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_ALE_P_LOW, -+}; -+ -+#define IFX_EBU_NAND_CON_CLE_P (1<<3) -+#define IFX_EBU_NAND_CON_CLE_P_S 3 -+enum { -+ IFX_EBU_NAND_CON_CLE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CLE_P_LOW, -+}; -+ -+#define IFX_EBU_NAND_CON_CS_P (1<<4) -+#define IFX_EBU_NAND_CON_CS_P_S 4 -+enum { -+ IFX_EBU_NAND_CON_CS_P_HIGH = 0, -+ IFX_EBU_NAND_CON_CS_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_SE_P (1<<5) -+#define IFX_EBU_NAND_CON_SE_P_S 5 -+enum { -+ IFX_EBU_NAND_CON_SE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_SE_P_LOW, /* Default after reset */ -+ }; -+#define IFX_EBU_NAND_CON_WP_P (1<<6) -+#define IFX_EBU_NAND_CON_WP_P_S 6 -+enum { -+ IFX_EBU_NAND_CON_WP_P_HIGH = 0, -+ IFX_EBU_NAND_CON_WP_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_PRE_P (1<<7) -+#define IFX_EBU_NAND_CON_PRE_P_S 7 -+enum { -+ IFX_EBU_NAND_CON_PRE_P_HIGH = 0, -+ IFX_EBU_NAND_CON_PRE_P_LOW, /* Default after reset */ -+ }; -+ -+#define IFX_EBU_NAND_CON_IN_CS (3<<8) -+#define IFX_EBU_NAND_CON_IN_CS_S 8 -+enum { -+ IFX_EBU_NAND_CON_IN_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_IN_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_OUT_CS (3<<10) -+#define IFX_EBU_NAND_CON_OUT_CS_S 10 -+enum { -+ IFX_EBU_NAND_CON_OUT_CS0 = 0, /* Default after reset */ -+ IFX_EBU_NAND_CON_OUT_CS1, -+ }; -+ -+#define IFX_EBU_NAND_CON_ECC (1<<31) -+#define IFX_EBU_NAND_CON_ECC_S 31 -+enum { -+ IFX_EBU_NAND_CON_ECC_OFF = 0, -+ IFX_EBU_NAND_CON_ECC_ON, -+}; -+ -+#define IFX_EBU_NAND_CON_LAT_EN (0x3F << 18) -+#define IFX_EBU_NAND_CON_LAT_EN_S 18 -+enum { -+ IFX_EBU_NAND_CON_LAT_EN_DEF = 0x3D, -+}; -+ -+#define IFX_EBU_NAND_ECC_CRM (1<<31) -+#define IFX_EBU_NAND_ECC_CRM_S 31 -+enum { -+ IFX_EBU_NAND_ECC_CRM_DISABLE = 0, -+ IFX_EBU_NAND_ECC_CRM_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_ECC_PAGE (3<<14) -+#define IFX_EBU_NAND_ECC_PAGE_S 14 -+enum { -+ IFX_EBU_NAND_ECC_PAGE_256 = 0, -+ IFX_EBU_NAND_ECC_PAGE_512, -+ IFX_EBU_NAND_ECC_PAGE_RES, -+}; -+ -+#define IFX_EBU_ECC_IEN_IR (1<<5) -+#define IFX_EBU_ECC_IEN_IR_S 5 -+enum { -+ IFX_EBU_ECC_IEN_DISABLE = 0, -+ IFX_EBU_ECC_IEN_ENABLE, -+}; -+ -+#define IFX_EBU_NAND_ECC_STATE (3<<0) -+#define IFX_EBU_NAND_ECC_STATE_S 0 -+ -+#define IFX_EBU_NAND_ECC_ROW_VAL (0x1FF<<5) -+#define IFX_EBU_NAND_ECC_ROW_VAL_S 5 -+ -+#define IFX_EBU_NAND_ECC_BIT_POS (7<<2) -+#define IFX_EBU_NAND_ECC_BIT_POS_S 2 -+ -+#define IFX_EBU_NAND_WAIT_RD (0x1) -+#define IFX_EBU_NAND_WAIT_BY_E (1<<1) -+#define IFX_EBU_NAND_WAIT_RD_E (1<<2) -+#define IFX_EBU_NAND_WAIT_WR_C (1<<3) -+ -+#define IFX_EBU_NAND_ECC0 (volatile u32*)(IFX_EBU + 0xB8) -+#define IFX_EBU_NAND_ECC_AC (volatile u32*)(IFX_EBU + 0xBC) -+ -+ -+ -+/***********************************************************************/ -+/* Module : SDRAM register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_SDRAM (KSEG1 | 0x1F800000) -+ -+/***MC Access Error Cause Register***/ -+#define IFX_SDRAM_MC_ERRCAUSE ((volatile u32*)(IFX_SDRAM + 0x0100)) -+#define IFX_SDRAM_MC_ERRCAUSE_ERR (1 << 31) -+#define IFX_SDRAM_MC_ERRCAUSE_PORT(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_ERRCAUSE_CAUSE(value) (((( 1 << 2) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_ERRCAUSE_Res(value) (((( 1 << NaN) - 1) & (value)) << NaN) -+ -+/***MC Access Error Address Register***/ -+#define IFX_SDRAM_MC_ERRADDR ((volatile u32*)(IFX_SDRAM + 0x0108)) -+ -+/***MC I/O General Purpose Register***/ -+#define IFX_SDRAM_MC_IOGP ((volatile u32*)(IFX_SDRAM + 0x0800)) -+#define IFX_SDRAM_MC_IOGP_GPR6(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_SDRAM_MC_IOGP_GPR5(value) (((( 1 << 4) - 1) & (value)) << 24) -+#define IFX_SDRAM_MC_IOGP_GPR4(value) (((( 1 << 4) - 1) & (value)) << 20) -+#define IFX_SDRAM_MC_IOGP_GPR3(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_IOGP_GPR2(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_IOGP_CPS (1 << 11) -+#define IFX_SDRAM_MC_IOGP_CLKDELAY(value) (((( 1 << 3) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_IOGP_CLKRAT(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_IOGP_RDDEL(value) (((( 1 << 4) - 1) & (value)) << 0) -+ -+/***MC Self Refresh Register***/ -+#define IFX_SDRAM_MC_SELFRFSH ((volatile u32*)(IFX_SDRAM + 0x0A00)) -+#define IFX_SDRAM_MC_SELFRFSH_PWDS (1 << 1) -+#define IFX_SDRAM_MC_SELFRFSH_PWD (1 << 0) -+#define IFX_SDRAM_MC_SELFRFSH_Res(value) (((( 1 << 30) - 1) & (value)) << 2) -+ -+/***MC Enable Register***/ -+#define IFX_SDRAM_MC_CTRLENA ((volatile u32*)(IFX_SDRAM + 0x1000)) -+#define IFX_SDRAM_MC_CTRLENA_ENA (1 << 0) -+#define IFX_SDRAM_MC_CTRLENA_Res(value) (((( 1 << 31) - 1) & (value)) << 1) -+ -+/***MC Mode Register Setup Code***/ -+#define IFX_SDRAM_MC_MRSCODE ((volatile u32*)(IFX_SDRAM + 0x1008)) -+#define IFX_SDRAM_MC_MRSCODE_UMC(value) (((( 1 << 5) - 1) & (value)) << 7) -+#define IFX_SDRAM_MC_MRSCODE_CL(value) (((( 1 << 3) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_MRSCODE_WT (1 << 3) -+#define IFX_SDRAM_MC_MRSCODE_BL(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***MC Configuration Data-word Width Register***/ -+#define IFX_SDRAM_MC_CFGDW ((volatile u32*)(IFX_SDRAM + 0x1010)) -+#define IFX_SDRAM_MC_CFGDW_DW(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGDW_Res(value) (((( 1 << 28) - 1) & (value)) << 4) -+ -+/***MC Configuration Physical Bank 0 Register***/ -+#define IFX_SDRAM_MC_CFGPB0 ((volatile u32*)(IFX_SDRAM + 0x1018)) -+#define IFX_SDRAM_MC_CFGPB0_MCSEN0(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_CFGPB0_BANKN0(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_CFGPB0_ROWW0(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_CFGPB0_COLW0(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_CFGPB0_Res(value) (((( 1 << 16) - 1) & (value)) << 16) -+ -+/***MC Latency Register***/ -+#define IFX_SDRAM_MC_LATENCY ((volatile u32*)(IFX_SDRAM + 0x1038)) -+#define IFX_SDRAM_MC_LATENCY_TRP(value) (((( 1 << 4) - 1) & (value)) << 16) -+#define IFX_SDRAM_MC_LATENCY_TRAS(value) (((( 1 << 4) - 1) & (value)) << 12) -+#define IFX_SDRAM_MC_LATENCY_TRCD(value) (((( 1 << 4) - 1) & (value)) << 8) -+#define IFX_SDRAM_MC_LATENCY_TDPL(value) (((( 1 << 4) - 1) & (value)) << 4) -+#define IFX_SDRAM_MC_LATENCY_TDAL(value) (((( 1 << 4) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_LATENCY_Res(value) (((( 1 << 12) - 1) & (value)) << 20) -+ -+/***MC Refresh Cycle Time Register***/ -+#define IFX_SDRAM_MC_TREFRESH ((volatile u32*)(IFX_SDRAM + 0x1040)) -+#define IFX_SDRAM_MC_TREFRESH_TREF(value) (((( 1 << 13) - 1) & (value)) << 0) -+#define IFX_SDRAM_MC_TREFRESH_Res(value) (((( 1 << 19) - 1) & (value)) << 13) -+ -+/***MC Status Register***/ -+#define IFX_SDRAM_MC_STAT ((volatile u32*)(IFX_SDRAM + 0x0070)) -+ -+/***MC DDR Control Register 00***/ -+#define IFX_DDR_MC_DC00 ((volatile u32*)(IFX_SDRAM + 0x1000)) -+/***MC DDR Control Register 03***/ -+#define IFX_DDR_MC_DC03 ((volatile u32*)(IFX_SDRAM + 0x1030)) -+/***MC DDR Control Register 17***/ -+#define IFX_DDR_MC_DC17 ((volatile u32*)(IFX_SDRAM + 0x1110)) -+ -+/***********************************************************************/ -+/* Module : ASC1 register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ASC1 (KSEG1 | 0x1E100C00) -+ -+/***ASC Clock Control Register***/ -+#define IFX_ASC1_CLC ((volatile u32*)(IFX_ASC1 + 0x0000)) -+#define IFX_ASC1_CLC_RMC(value) (((( 1 << 8) - 1) & (value)) << 8) -+#define IFX_ASC1_CLC_DISS (1 << 1) -+#define IFX_ASC1_CLC_DISR (1 << 0) -+ -+/***ASC Port Input Select Register***/ -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL ((volatile u32*)(IFX_ASC1 + 0x0004)) -+#define IFX_ASC1_PISEL_RIS (1 << 0) -+ -+/***ASC Control Register***/ -+#define IFX_ASC1_CON ((volatile u32*)(IFX_ASC1 + 0x0010)) -+#define IFX_ASC1_CON_BEN (1 << 20) -+#define IFX_ASC1_CON_TOEN (1 << 20) -+#define IFX_ASC1_CON_ROEN (1 << 19) -+#define IFX_ASC1_CON_RUEN (1 << 18) -+#define IFX_ASC1_CON_FEN (1 << 17) -+#define IFX_ASC1_CON_PAL (1 << 16) -+#define IFX_ASC1_CON_R (1 << 15) -+#define IFX_ASC1_CON_ACO (1 << 14) -+#define IFX_ASC1_CON_LB (1 << 13) -+#define IFX_ASC1_CON_ERCLK (1 << 10) -+#define IFX_ASC1_CON_FDE (1 << 9) -+#define IFX_ASC1_CON_BRS (1 << 8) -+#define IFX_ASC1_CON_STP (1 << 7) -+#define IFX_ASC1_CON_SP (1 << 6) -+#define IFX_ASC1_CON_ODD (1 << 5) -+#define IFX_ASC1_CON_PEN (1 << 4) -+#define IFX_ASC1_CON_M(value) (((( 1 << 3) - 1) & (value)) << 0) -+ -+/***ASC Staus Register***/ -+#define IFX_ASC1_STATE ((volatile u32*)(IFX_ASC1 + 0x0014)) -+/***ASC Write Hardware Modified Control Register***/ -+#define IFX_ASC1_WHBSTATE ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_WHBSTATE_SETBE (1 << 113) -+#define IFX_ASC1_WHBSTATE_SETTOE (1 << 12) -+#define IFX_ASC1_WHBSTATE_SETROE (1 << 11) -+#define IFX_ASC1_WHBSTATE_SETRUE (1 << 10) -+#define IFX_ASC1_WHBSTATE_SETFE (1 << 19) -+#define IFX_ASC1_WHBSTATE_SETPE (1 << 18) -+#define IFX_ASC1_WHBSTATE_CLRBE (1 << 17) -+#define IFX_ASC1_WHBSTATE_CLRTOE (1 << 6) -+#define IFX_ASC1_WHBSTATE_CLRROE (1 << 5) -+#define IFX_ASC1_WHBSTATE_CLRRUE (1 << 4) -+#define IFX_ASC1_WHBSTATE_CLRFE (1 << 3) -+#define IFX_ASC1_WHBSTATE_CLRPE (1 << 2) -+#define IFX_ASC1_WHBSTATE_SETREN (1 << 1) -+#define IFX_ASC1_WHBSTATE_CLRREN (1 << 0) -+ -+/***ASC Baudrate Timer/Reload Register***/ -+#define IFX_ASC1_BG ((volatile u32*)(IFX_ASC1 + 0x0050)) -+#define IFX_ASC1_BG_BR_VALUE(value) (((( 1 << 13) - 1) & (value)) << 0) -+ -+/***ASC Fractional Divider Register***/ -+#define IFX_ASC1_FDV ((volatile u32*)(IFX_ASC1 + 0x0018)) -+#define IFX_ASC1_FDV_FD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Transmit Buffer Register***/ -+#define IFX_ASC1_TBUF ((volatile u32*)(IFX_ASC1 + 0x0020)) -+#define IFX_ASC1_TBUF_TD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Receive Buffer Register***/ -+#define IFX_ASC1_RBUF ((volatile u32*)(IFX_ASC1 + 0x0024)) -+#define IFX_ASC1_RBUF_RD_VALUE(value) (((( 1 << 9) - 1) & (value)) << 0) -+ -+/***ASC Autobaud Control Register***/ -+#define IFX_ASC1_ABCON ((volatile u32*)(IFX_ASC1 + 0x0030)) -+#define IFX_ASC1_ABCON_RXINV (1 << 11) -+#define IFX_ASC1_ABCON_TXINV (1 << 10) -+#define IFX_ASC1_ABCON_ABEM(value) (((( 1 << 2) - 1) & (value)) << 8) -+#define IFX_ASC1_ABCON_FCDETEN (1 << 4) -+#define IFX_ASC1_ABCON_ABDETEN (1 << 3) -+#define IFX_ASC1_ABCON_ABSTEN (1 << 2) -+#define IFX_ASC1_ABCON_AUREN (1 << 1) -+#define IFX_ASC1_ABCON_ABEN (1 << 0) -+ -+/***Receive FIFO Control Register***/ -+#define IFX_ASC1_RXFCON ((volatile u32*)(IFX_ASC1 + 0x0040)) -+#define IFX_ASC1_RXFCON_RXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_RXFCON_RXFFLU (1 << 1) -+#define IFX_ASC1_RXFCON_RXFEN (1 << 0) -+ -+/***Transmit FIFO Control Register***/ -+#define IFX_ASC1_TXFCON ((volatile u32*)(IFX_ASC1 + 0x0044)) -+#define IFX_ASC1_TXFCON_TXFITL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_TXFCON_TXFFLU (1 << 1) -+#define IFX_ASC1_TXFCON_TXFEN (1 << 0) -+ -+/***FIFO Status Register***/ -+#define IFX_ASC1_FSTAT ((volatile u32*)(IFX_ASC1 + 0x0048)) -+#define IFX_ASC1_FSTAT_TXFFL(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL(value) (((( 1 << 6) - 1) & (value)) << 0) -+#define IFX_ASC1_FSTAT_TXFREE_GET(value) (((value) >> 24) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 24) -+#define IFX_ASC1_FSTAT_RXFREE_GET(value) (((value) >> 16) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFREE_SET(value) (((( 1 << 6) - 1) & (value)) << 16) -+#define IFX_ASC1_FSTAT_TXFFL_GET(value) (((value) >> 8) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_TXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 8) -+#define IFX_ASC1_FSTAT_RXFFL_GET(value) (((value) >> 0) & ((1 << 6) - 1)) -+#define IFX_ASC1_FSTAT_RXFFL_SET(value) (((( 1 << 6) - 1) & (value)) << 0) -+ -+ -+/***ASC Autobaud Status Register***/ -+#define IFX_ASC1_ABSTAT ((volatile u32*)(IFX_ASC1 + 0x0034)) -+#define IFX_ASC1_ABSTAT_DETWAIT (1 << 4) -+#define IFX_ASC1_ABSTAT_SCCDET (1 << 3) -+#define IFX_ASC1_ABSTAT_SCSDET (1 << 2) -+#define IFX_ASC1_ABSTAT_FCCDET (1 << 1) -+#define IFX_ASC1_ABSTAT_FCSDET (1 << 0) -+ -+/***ASC Write HW Modified Autobaud Status Register***/ -+#define IFX_ASC1_WHBABSTAT ((volatile u32*)(IFX_ASC1 + 0x003C)) -+#define IFX_ASC1_WHBABSTAT_SETDETWAIT (1 << 9) -+#define IFX_ASC1_WHBABSTAT_CLRDETWAIT (1 << 8) -+#define IFX_ASC1_WHBABSTAT_SETSCCDET (1 << 7) -+#define IFX_ASC1_WHBABSTAT_CLRSCCDET (1 << 6) -+#define IFX_ASC1_WHBABSTAT_SETSCSDET (1 << 5) -+#define IFX_ASC1_WHBABSTAT_CLRSCSDET (1 << 4) -+#define IFX_ASC1_WHBABSTAT_SETFCCDET (1 << 3) -+#define IFX_ASC1_WHBABSTAT_CLRFCCDET (1 << 2) -+#define IFX_ASC1_WHBABSTAT_SETFCSDET (1 << 1) -+#define IFX_ASC1_WHBABSTAT_CLRFCSDET (1 << 0) -+ -+/***ASC IRNCR0 **/ -+#define IFX_ASC1_IRNREN ((volatile u32*)(IFX_ASC1 + 0x00F4)) -+#define IFX_ASC1_IRNICR ((volatile u32*)(IFX_ASC1 + 0x00FC)) -+/***ASC IRNCR1 **/ -+#define IFX_ASC1_IRNCR ((volatile u32*)(IFX_ASC1 + 0x00F8)) -+#define IFX_ASC_IRNCR_TIR 0x1 -+#define IFX_ASC_IRNCR_RIR 0x2 -+#define IFX_ASC_IRNCR_EIR 0x4 -+ -+ -+ -+/***********************************************************************/ -+/* Module : DMA register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_DMA (KSEG1 | 0x1E104100) -+ -+#define IFX_DMA_BASE IFX_DMA -+#define IFX_DMA_CLC (volatile u32*)(IFX_DMA_BASE + 0x00) -+#define IFX_DMA_ID (volatile u32*)(IFX_DMA_BASE + 0x08) -+#define IFX_DMA_CTRL (volatile u32*)(IFX_DMA_BASE + 0x10) -+#define IFX_DMA_CPOLL (volatile u32*)(IFX_DMA_BASE + 0x14) -+ -+#define IFX_DMA_CS(i) (volatile u32*)(IFX_DMA_BASE + 0x18 + 0x38 * (i)) -+#define IFX_DMA_CCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x1C + 0x38 * (i)) -+#define IFX_DMA_CDBA(i) (volatile u32*)(IFX_DMA_BASE + 0x20 + 0x38 * (i)) -+#define IFX_DMA_CDLEN(i) (volatile u32*)(IFX_DMA_BASE + 0x24 + 0x38 * (i)) -+#define IFX_DMA_CIS(i) (volatile u32*)(IFX_DMA_BASE + 0x28 + 0x38 * (i)) -+#define IFX_DMA_CIE(i) (volatile u32*)(IFX_DMA_BASE + 0x2C + 0x38 * (i)) -+ -+#define IFX_DMA_CGBL (volatile u32*)(IFX_DMA_BASE + 0x30) -+ -+#define IFX_DMA_CDPTNRD(i) (volatile u32*)(IFX_DMA_BASE + 0x34 + 0x04 * (i)) -+ -+#define IFX_DMA_PS(i) (volatile u32*)(IFX_DMA_BASE + 0x40 + 0x30 * (i)) -+#define IFX_DMA_PCTRL(i) (volatile u32*)(IFX_DMA_BASE + 0x44 + 0x30 * (i)) -+ -+#define IFX_DMA_IRNEN (volatile u32*)(IFX_DMA_BASE + 0xf4) -+#define IFX_DMA_IRNCR (volatile u32*)(IFX_DMA_BASE + 0xf8) -+#define IFX_DMA_IRNICR (volatile u32*)(IFX_DMA_BASE + 0xfc) -+/* Global Software Reset (0) */ -+#define IFX_DMA_CTRL_RST (0x1) -+ -+/* Channel Polling Register */ -+ -+/* Enable (31) */ -+#define IFX_DMA_CPOLL_EN (0x1 << 31) -+#define IFX_DMA_CPOLL_EN_VAL(val) (((val) & 0x1) << 31) -+ -+/* Counter (15:4) */ -+#define IFX_DMA_CPOLL_CNT (0xfff << 4) -+#define IFX_DMA_CPOLL_CNT_VAL(val) (((val) & 0xfff) << 4) -+ -+/* Channel Control Register */ -+ -+/* Peripheral to Peripheral Copy (24) */ -+#define IFX_DMA_CCTRL_P2PCPY (0x1 << 24) -+#define IFX_DMA_CCTRL_P2PCPY_VAL(val) (((val) & 0x1) << 24) -+#define IFX_DMA_CCTRL_P2PCPY_GET(val) ((((val) & IFX_DMA_CCTRL_P2PCPY) >> 24) & 0x1) -+ -+/* Channel Weight for Transmit Direction (17:16) */ -+#define IFX_DMA_CCTRL_TXWGT (0x3 << 16) -+#define IFX_DMA_CCTRL_TXWGT_VAL(val) (((val) & 0x3) << 16) -+#define IFX_DMA_CCTRL_TXWGT_GET(val) ((((val) & IFX_DMA_CCTRL_TXWGT) >> 16) & 0x3) -+ -+/* Port Assignment (13:11) */ -+#define IFX_DMA_CCTRL_PRTNR (0x7 << 11) -+#define IFX_DMA_CCTRL_PRTNR_GET(val) ((((val) & IFX_DMA_CCTRL_PRTNR) >> 11) & 0x7) -+ -+/* Class (10:9) */ -+#define IFX_DMA_CCTRL_CLASS (0x3 << 9) -+#define IFX_DMA_CCTRL_CLASS_VAL(val) (((val) & 0x3) << 9) -+#define IFX_DMA_CCTRL_CLASS_GET(val) ((((val) & IFX_DMA_CCTRL_CLASS) >> 9) & 0x3) -+ -+/* Direction (8) */ -+#define IFX_DMA_CCTRL_DIR (0x1 << 8) -+/* Reset (1) */ -+#define IFX_DMA_CCTRL_RST (0x1 << 1) -+/* Channel On or Off (0) */ -+#define IFX_DMA_CCTRL_ON (0x1) -+ -+/* Channel Interrupt Status Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIS_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIS_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt (3) */ -+#define IFX_DMA_CIS_DESCPT (0x1 << 3) -+/* Descriptor Under-Run Interrupt (2) */ -+#define IFX_DMA_CIS_DUR (0x1 << 2) -+/* End of Packet Interrupt (1) */ -+#define IFX_DMA_CIS_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIS_ALL (IFX_DMA_CIS_RDERR | IFX_DMA_CIS_CHOFF| \ -+ IFX_DMA_CIS_DESCPT | IFX_DMA_CIS_DUR | \ -+ IFX_DMA_CIS_EOP) -+ -+/* Channel Interrupt Enable Register */ -+ -+/* SAI Read Error Interrupt (5) */ -+#define IFX_DMA_CIE_RDERR (0x1 << 5) -+/* Channel Off Interrupt (4) */ -+#define IFX_DMA_CIE_CHOFF (0x1 << 4) -+/* Descriptor Complete Interrupt Enable (3) */ -+#define IFX_DMA_CIE_DESCPT (0x1 << 3) -+/* Descriptor Under Run Interrupt Enable (2) */ -+#define IFX_DMA_CIE_DUR (0x1 << 2) -+/* End of Packet Interrupt Enable (1) */ -+#define IFX_DMA_CIE_EOP (0x1 << 1) -+ -+#define IFX_DMA_CIE_DEFAULT (IFX_DMA_CIE_DESCPT | IFX_DMA_CIE_EOP) -+ -+/* Port Select Register */ -+ -+/* Port Selection (2:0) */ -+#define IFX_DMA_PS_PS (0x7) -+#define IFX_DMA_PS_PS_VAL(val) (((val) & 0x7) << 0) -+ -+/* Port Control Register */ -+ -+/* General Purpose Control (16) */ -+#define IFX_DMA_PCTRL_GPC (0x1 << 16) -+#define IFX_DMA_PCTRL_GPC_VAL(val) (((val) & 0x1) << 16) -+ -+/* Port Weight for Transmit Direction (14:12) */ -+#define IFX_DMA_PCTRL_TXWGT (0x7 << 12) -+#define IFX_DMA_PCTRL_TXWGT_VAL(val) (((val) & 0x7) << 12) -+/* Endianness for Transmit Direction (11:10) */ -+#define IFX_DMA_PCTRL_TXENDI (0x3 << 10) -+#define IFX_DMA_PCTRL_TXENDI_VAL(val) (((val) & 0x3) << 10) -+/* Endianness for Receive Direction (9:8) */ -+#define IFX_DMA_PCTRL_RXENDI (0x3 << 8) -+#define IFX_DMA_PCTRL_RXENDI_VAL(val) (((val) & 0x3) << 8) -+/* Packet Drop Enable (6) */ -+#define IFX_DMA_PCTRL_PDEN (0x1 << 6) -+#define IFX_DMA_PCTRL_PDEN_VAL(val) (((val) & 0x1) << 6) -+/* Burst Length for Transmit Direction (5:4) */ -+#define IFX_DMA_PCTRL_TXBL (0x3 << 4) -+#define IFX_DMA_PCTRL_TXBL_VAL(val) (((val) & 0x3) << 4) -+/* Burst Length for Receive Direction (3:2) */ -+#define IFX_DMA_PCTRL_RXBL (0x3 << 2) -+#define IFX_DMA_PCTRL_RXBL_VAL(val) (((val) & 0x3) << 2) -+ -+ -+ -+/***********************************************************************/ -+/* Module : Debug register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_Debug (KSEG1 | 0x1F106000) -+ -+/***MCD Break Bus Switch Register***/ -+#define IFX_Debug_MCD_BBS ((volatile u32*)(IFX_Debug + 0x0000)) -+#define IFX_Debug_MCD_BBS_BTP1 (1 << 19) -+#define IFX_Debug_MCD_BBS_BTP0 (1 << 18) -+#define IFX_Debug_MCD_BBS_BSP1 (1 << 17) -+#define IFX_Debug_MCD_BBS_BSP0 (1 << 16) -+#define IFX_Debug_MCD_BBS_BT5EN (1 << 15) -+#define IFX_Debug_MCD_BBS_BT4EN (1 << 14) -+#define IFX_Debug_MCD_BBS_BT5 (1 << 13) -+#define IFX_Debug_MCD_BBS_BT4 (1 << 12) -+#define IFX_Debug_MCD_BBS_BS5EN (1 << 7) -+#define IFX_Debug_MCD_BBS_BS4EN (1 << 6) -+#define IFX_Debug_MCD_BBS_BS5 (1 << 5) -+#define IFX_Debug_MCD_BBS_BS4 (1 << 4) -+ -+/***MCD Multiplexer Control Register***/ -+#define IFX_Debug_MCD_MCR ((volatile u32*)(IFX_Debug+ 0x0008)) -+#define IFX_Debug_MCD_MCR_MUX5 (1 << 4) -+#define IFX_Debug_MCD_MCR_MUX4 (1 << 3) -+#define IFX_Debug_MCD_MCR_MUX1 (1 << 0) -+ -+ -+ -+/***********************************************************************/ -+/* Module : ICU register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_ICU (KSEG1 | 0x1F880200) -+ -+#define IFX_ICU_IM0_ISR ((volatile u32*)(IFX_ICU + 0x0000)) -+#define IFX_ICU_IM0_IER ((volatile u32*)(IFX_ICU + 0x0008)) -+#define IFX_ICU_IM0_IOSR ((volatile u32*)(IFX_ICU + 0x0010)) -+#define IFX_ICU_IM0_IRSR ((volatile u32*)(IFX_ICU + 0x0018)) -+#define IFX_ICU_IM0_IMR ((volatile u32*)(IFX_ICU + 0x0020)) -+ -+#define IFX_ICU_IM1_ISR ((volatile u32*)(IFX_ICU + 0x0028)) -+#define IFX_ICU_IM1_IER ((volatile u32*)(IFX_ICU + 0x0030)) -+#define IFX_ICU_IM1_IOSR ((volatile u32*)(IFX_ICU + 0x0038)) -+#define IFX_ICU_IM1_IRSR ((volatile u32*)(IFX_ICU + 0x0040)) -+#define IFX_ICU_IM1_IMR ((volatile u32*)(IFX_ICU + 0x0048)) -+ -+#define IFX_ICU_IM2_ISR ((volatile u32*)(IFX_ICU + 0x0050)) -+#define IFX_ICU_IM2_IER ((volatile u32*)(IFX_ICU + 0x0058)) -+#define IFX_ICU_IM2_IOSR ((volatile u32*)(IFX_ICU + 0x0060)) -+#define IFX_ICU_IM2_IRSR ((volatile u32*)(IFX_ICU + 0x0068)) -+#define IFX_ICU_IM2_IMR ((volatile u32*)(IFX_ICU + 0x0070)) -+ -+#define IFX_ICU_IM3_ISR ((volatile u32*)(IFX_ICU + 0x0078)) -+#define IFX_ICU_IM3_IER ((volatile u32*)(IFX_ICU + 0x0080)) -+#define IFX_ICU_IM3_IOSR ((volatile u32*)(IFX_ICU + 0x0088)) -+#define IFX_ICU_IM3_IRSR ((volatile u32*)(IFX_ICU + 0x0090)) -+#define IFX_ICU_IM3_IMR ((volatile u32*)(IFX_ICU + 0x0098)) -+ -+#define IFX_ICU_IM4_ISR ((volatile u32*)(IFX_ICU + 0x00A0)) -+#define IFX_ICU_IM4_IER ((volatile u32*)(IFX_ICU + 0x00A8)) -+#define IFX_ICU_IM4_IOSR ((volatile u32*)(IFX_ICU + 0x00B0)) -+#define IFX_ICU_IM4_IRSR ((volatile u32*)(IFX_ICU + 0x00B8)) -+#define IFX_ICU_IM4_IMR ((volatile u32*)(IFX_ICU + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_IM_VEC_5 ((volatile u32*)(IFX_ICU + 0x00C8)) -+#define IFX_ICU_IM_VEC ((volatile u32*)(IFX_ICU + 0x00D0)) -+ -+/***********************************************************************/ -+ -+#define IFX_ICU_VPE1 (KSEG1 | 0x1F880300) -+#define IFX_ICU1 IFX_ICU_VPE1 -+ -+#define IFX_ICU_VPE1_IM0_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0000)) -+#define IFX_ICU_VPE1_IM0_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0008)) -+#define IFX_ICU_VPE1_IM0_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0010)) -+#define IFX_ICU_VPE1_IM0_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0018)) -+#define IFX_ICU_VPE1_IM0_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0020)) -+ -+#define IFX_ICU_VPE1_IM1_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0028)) -+#define IFX_ICU_VPE1_IM1_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0030)) -+#define IFX_ICU_VPE1_IM1_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0038)) -+#define IFX_ICU_VPE1_IM1_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0040)) -+#define IFX_ICU_VPE1_IM1_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0048)) -+ -+#define IFX_ICU_VPE1_IM2_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0050)) -+#define IFX_ICU_VPE1_IM2_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0058)) -+#define IFX_ICU_VPE1_IM2_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0060)) -+#define IFX_ICU_VPE1_IM2_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0068)) -+#define IFX_ICU_VPE1_IM2_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0070)) -+ -+#define IFX_ICU_VPE1_IM3_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x0078)) -+#define IFX_ICU_VPE1_IM3_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x0080)) -+#define IFX_ICU_VPE1_IM3_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0088)) -+#define IFX_ICU_VPE1_IM3_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x0090)) -+#define IFX_ICU_VPE1_IM3_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x0098)) -+ -+#define IFX_ICU_VPE1_IM4_ISR ((volatile u32*)(IFX_ICU_VPE1 + 0x00A0)) -+#define IFX_ICU_VPE1_IM4_IER ((volatile u32*)(IFX_ICU_VPE1 + 0x00A8)) -+#define IFX_ICU_VPE1_IM4_IOSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B0)) -+#define IFX_ICU_VPE1_IM4_IRSR ((volatile u32*)(IFX_ICU_VPE1 + 0x00B8)) -+#define IFX_ICU_VPE1_IM4_IMR ((volatile u32*)(IFX_ICU_VPE1 + 0x00C0)) -+ -+/***Interrupt Vector Value Register***/ -+#define IFX_ICU_VPE1_IM_VEC_5 ((volatile u32*)(IFX_ICU_VPE1 + 0x00C8)) -+#define IFX_ICU_VPE1_IM_VEC ((volatile u32*)(IFX_ICU_VPE1 + 0x00D0)) -+#define IFX_ICU_IM_VEC1 IFX_ICU_VPE1_IM_VEC -+ -+/* MSI PIC */ -+#define IFX_MSI_PIC_REG_BASE (KSEG1 | 0x1F700000) -+ -+#define IFX_MSI_PIC_BIG_ENDIAN 1 -+#define IFX_MSI_PIC_LITTLE_ENDIAN 0 -+ -+#define IFX_MSI_PCI_INT_DISABLE 0x80000000 -+#define IFX_MSI_PIC_INT_LINE 0x30000000 -+#define IFX_MSI_PIC_INT_LINE_S 28 -+#define IFX_MSI_PIC_MSG_ADDR 0x0FFF0000 -+#define IFX_MSI_PIC_MSG_ADDR_S 16 -+#define IFX_MSI_PIC_MSG_DATA 0x0000FFFF -+#define IFX_MSI_PIC_MSG_DATA_S 0x0 -+ -+/***Interrupt Vector Value Mask***/ -+#define IFX_ICU_IM0_VEC_MASK (0x3F << 0) -+#define IFX_ICU_IM1_VEC_MASK (0x3F << 6) -+#define IFX_ICU_IM2_VEC_MASK (0x3F << 12) -+#define IFX_ICU_IM3_VEC_MASK (0x3F << 18) -+#define IFX_ICU_IM4_VEC_MASK (0x3F << 24) -+ -+/***External Interrupt Control Register***/ -+#define IFX_ICU_EIU (KSEG1 | 0x1F101000) -+#define IFX_ICU_EIU_EXIN_C ((volatile u32 *)(IFX_ICU_EIU + 0x0000)) -+#define IFX_ICU_EIU_INIC ((volatile u32 *)(IFX_ICU_EIU + 0x0004)) -+#define IFX_ICU_EIU_INC ((volatile u32 *)(IFX_ICU_EIU + 0x0008)) -+#define IFX_ICU_EIU_INEN ((volatile u32 *)(IFX_ICU_EIU + 0x000C)) -+#define IFX_YIELDEN(n) ((volatile u32 *)(IFX_ICU_EIU + 0x0010 + (n) * 4) -+#define IFX_NMI_CR ((volatile u32 *)(IFX_ICU_EIU + 0x00F0)) -+#define IFX_NMI_SR ((volatile u32 *)(IFX_ICU_EIU + 0x00F4)) -+ -+ -+ -+/***********************************************************************/ -+/* Module : MPS register address and bits */ -+/***********************************************************************/ -+ -+#define IFX_MPS (KSEG1 | 0x1F107000) -+ -+#define IFX_MPS_CHIPID ((volatile u32*)(IFX_MPS + 0x0344)) -+#define IFX_MPS_CHIPID_VERSION_GET(value) (((value) >> 28) & ((1 << 4) - 1)) -+#define IFX_MPS_CHIPID_VERSION_SET(value) (((( 1 << 4) - 1) & (value)) << 28) -+#define IFX_MPS_CHIPID_PARTNUM_GET(value) (((value) >> 12) & ((1 << 16) - 1)) -+#define IFX_MPS_CHIPID_PARTNUM_SET(value) (((( 1 << 16) - 1) & (value)) << 12) -+#define IFX_MPS_CHIPID_MANID_GET(value) (((value) >> 1) & ((1 << 10) - 1)) -+#define IFX_MPS_CHIPID_MANID_SET(value) (((( 1 << 10) - 1) & (value)) << 1) -+ -+ -+/* voice channel 0 ... 3 interrupt enable register */ -+#define IFX_MPS_VC0ENR ((volatile u32*)(IFX_MPS + 0x0000)) -+#define IFX_MPS_VC1ENR ((volatile u32*)(IFX_MPS + 0x0004)) -+#define IFX_MPS_VC2ENR ((volatile u32*)(IFX_MPS + 0x0008)) -+#define IFX_MPS_VC3ENR ((volatile u32*)(IFX_MPS + 0x000C)) -+/* voice channel 0 ... 3 interrupt status read register */ -+#define IFX_MPS_RVC0SR ((volatile u32*)(IFX_MPS + 0x0010)) -+#define IFX_MPS_RVC1SR ((volatile u32*)(IFX_MPS + 0x0014)) -+#define IFX_MPS_RVC2SR ((volatile u32*)(IFX_MPS + 0x0018)) -+#define IFX_MPS_RVC3SR ((volatile u32*)(IFX_MPS + 0x001C)) -+/* voice channel 0 ... 3 interrupt status set register */ -+#define IFX_MPS_SVC0SR ((volatile u32*)(IFX_MPS + 0x0020)) -+#define IFX_MPS_SVC1SR ((volatile u32*)(IFX_MPS + 0x0024)) -+#define IFX_MPS_SVC2SR ((volatile u32*)(IFX_MPS + 0x0028)) -+#define IFX_MPS_SVC3SR ((volatile u32*)(IFX_MPS + 0x002C)) -+/* voice channel 0 ... 3 interrupt status clear register */ -+#define IFX_MPS_CVC0SR ((volatile u32*)(IFX_MPS + 0x0030)) -+#define IFX_MPS_CVC1SR ((volatile u32*)(IFX_MPS + 0x0034)) -+#define IFX_MPS_CVC2SR ((volatile u32*)(IFX_MPS + 0x0038)) -+#define IFX_MPS_CVC3SR ((volatile u32*)(IFX_MPS + 0x003C)) -+/* common status 0 and 1 read register */ -+#define IFX_MPS_RAD0SR ((volatile u32*)(IFX_MPS + 0x0040)) -+#define IFX_MPS_RAD1SR ((volatile u32*)(IFX_MPS + 0x0044)) -+/* common status 0 and 1 set register */ -+#define IFX_MPS_SAD0SR ((volatile u32*)(IFX_MPS + 0x0048)) -+#define IFX_MPS_SAD1SR ((volatile u32*)(IFX_MPS + 0x004C)) -+/* common status 0 and 1 clear register */ -+#define IFX_MPS_CAD0SR ((volatile u32*)(IFX_MPS + 0x0050)) -+#define IFX_MPS_CAD1SR ((volatile u32*)(IFX_MPS + 0x0054)) -+/* common status 0 and 1 enable register */ -+#define IFX_MPS_AD0ENR ((volatile u32*)(IFX_MPS + 0x0058)) -+#define IFX_MPS_AD1ENR ((volatile u32*)(IFX_MPS + 0x005C)) -+/* notification enable register */ -+#define IFX_MPS_CPU0_NFER ((volatile u32*)(IFX_MPS + 0x0060)) -+#define IFX_MPS_CPU1_NFER ((volatile u32*)(IFX_MPS + 0x0064)) -+/* CPU to CPU interrup request register */ -+#define IFX_MPS_CPU0_2_CPU1_IRR ((volatile u32*)(IFX_MPS + 0x0070)) -+#define IFX_MPS_CPU0_2_CPU1_IER ((volatile u32*)(IFX_MPS + 0x0074)) -+/* Global interrupt request and request enable register */ -+#define IFX_MPS_GIRR ((volatile u32*)(IFX_MPS + 0x0078)) -+#define IFX_MPS_GIER ((volatile u32*)(IFX_MPS + 0x007C)) -+ -+#define IFX_MPS_SRAM ((volatile u32*)(KSEG1 | 0x1F200000)) -+ -+#define IFX_MPS_VCPU_FW_AD ((volatile u32*)(KSEG1 | 0x1F2001E0)) -+ -+#define IFX_FUSE_ID_CFG ((volatile u32*)(KSEG1 | 0x1F107350)) -+#define IFX_FUSE_BASE_ADDR (KSEG1 | 0x1F107354) -+ -+ -+ -+/************************************************************************/ -+/* Module : DEU register address and bits */ -+/************************************************************************/ -+ -+#define IFX_DEU_BASE_ADDR (KSEG1 | 0x1E103100) -+ -+/* DEU Control Register */ -+#define IFX_DEU_CLK ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0000)) -+#define IFX_DEU_ID ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0008)) -+ -+/* DEU control register */ -+#define IFX_DES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0010)) -+#define IFX_DES_IHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0014)) -+#define IFX_DES_ILR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0018)) -+#define IFX_DES_K1HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x001C)) -+#define IFX_DES_K1LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0020)) -+#define IFX_DES_K3HR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0024)) -+#define IFX_DES_K3LR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0028)) -+#define IFX_DES_IVHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x002C)) -+#define IFX_DES_IVLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0030)) -+#define IFX_DES_OHR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0040)) -+#define IFX_DES_OLR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+ -+/* AES DEU register */ -+#define IFX_AES_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0050)) -+#define IFX_AES_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0054)) -+#define IFX_AES_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0058)) -+#define IFX_AES_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x005C)) -+#define IFX_AES_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0060)) -+ -+/* AES Key register */ -+#define IFX_AES_K7R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0064)) -+#define IFX_AES_K6R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0068)) -+#define IFX_AES_K5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x006C)) -+#define IFX_AES_K4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0070)) -+#define IFX_AES_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0074)) -+#define IFX_AES_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0078)) -+#define IFX_AES_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x007C)) -+#define IFX_AES_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0080)) -+ -+/* AES vector register */ -+#define IFX_AES_IV3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0084)) -+#define IFX_AES_IV2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0088)) -+#define IFX_AES_IV1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x008C)) -+#define IFX_AES_IV0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0090)) -+#define IFX_AES_0D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0094)) -+#define IFX_AES_0D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0098)) -+#define IFX_AES_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x009C)) -+#define IFX_AES_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00A0)) -+ -+/* ARC4 DEU register */ -+#define IFX_ARC4_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0100)) -+#define IFX_ARC4_IDLEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0114)) -+#define IFX_ARC4_ID3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0118)) -+#define IFX_ARC4_ID2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x011C)) -+#define IFX_ARC4_ID1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0120)) -+#define IFX_ARC4_ID0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0124)) -+ -+/* ARC4 Key register */ -+#define IFX_ARC4_K3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0104)) -+#define IFX_ARC4_K2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0108)) -+#define IFX_ARC4_K1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x010C)) -+#define IFX_ARC4_K0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0110)) -+ -+/* ARC4 vector register */ -+#define IFX_ARC4_OD3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0128)) -+#define IFX_ARC4_OD2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x012C)) -+#define IFX_ARC4_OD1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0130)) -+#define IFX_ARC4_OD0R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x0134)) -+ -+/* hash control register */ -+#define IFX_HASH_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B0)) -+#define IFX_HASH_MR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B4)) -+#define IFX_HASH_D1R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00B8)) -+#define IFX_HASH_D2R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00BC)) -+#define IFX_HASH_D3R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C0)) -+#define IFX_HASH_D4R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C4)) -+#define IFX_HASH_D5R ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00C8)) -+ -+#define IFX_HMAC_KIDX ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D0)) -+#define IFX_HMAC_KEY ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D4)) -+#define IFX_HMAC_DBN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00D8)) -+ -+#define IFX_DEU_DMA_CON ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00EC)) -+ -+#define IFX_DEU_IRNEN ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F4)) -+#define IFX_DEU_IRNCR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00F8)) -+#define IFX_DEU_IRNICR ((volatile u32 *)(IFX_DEU_BASE_ADDR + 0x00FC)) -+ -+ -+ -+/************************************************************************/ -+/* Module : PPE register address and bits */ -+/************************************************************************/ -+ -+#define IFX_PPE32_BASE (KSEG1 | 0x1E200000) -+#define IFX_PPE32_DEBUG_BREAK_TRACE_REG (IFX_PPE32_BASE + (0x0000 * 4)) -+#define IFX_PPE32_INT_MASK_STATUS_REG (IFX_PPE32_BASE + (0x0030 * 4)) -+#define IFX_PPE32_INT_RESOURCE_REG (IFX_PPE32_BASE + (0x0040 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B0 (IFX_PPE32_BASE + (0x1000 * 4)) -+#define IFX_PPE32_CDM_CODE_MEM_B1 (IFX_PPE32_BASE + (0x2000 * 4)) -+#define IFX_PPE32_DATA_MEM_MAP_REG_BASE (IFX_PPE32_BASE + (0x4000 * 4)) -+ -+#define IFX_PPE32_SRST (IFX_PPE32_BASE + 0x10080) -+ -+/* -+ * ETOP MDIO Registers -+ */ -+#define IFX_PP32_ETOP_MDIO_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0600 * 4))) -+#define IFX_PP32_ETOP_MDIO_ACC ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0601 * 4))) -+#define IFX_PP32_ETOP_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0602 * 4))) -+#define IFX_PP32_ETOP_IG_VLAN_COS ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0603 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0604 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0605 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0606 * 4))) -+#define IFX_PP32_ETOP_IG_DSCP_COS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0607 * 4))) -+#define IFX_PP32_ETOP_IG_PLEN_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0608 * 4))) -+#define IFX_PP32_ETOP_ISR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060A * 4))) -+#define IFX_PP32_ETOP_IER ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060B * 4))) -+#define IFX_PP32_ETOP_VPID ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x060C * 4))) -+#define IFX_PP32_ENET_MAC_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0610 * 4))) -+#define IFX_PP32_ENETS_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0612 * 4))) -+#define IFX_PP32_ENETS_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0613 * 4))) -+#define IFX_PP32_ENETS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0614 * 4))) -+#define IFX_PP32_ENETS_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0615 * 4))) -+#define IFX_PP32_ENETS_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0616 * 4))) -+#define IFX_PP32_ENETS_BUF_CTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0617 * 4))) -+#define IFX_PP32_ENETS_COS_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0618 * 4))) -+#define IFX_PP32_ENETS_IGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0619 * 4))) -+#define IFX_PP32_ENETS_IGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061A * 4))) -+#define IFX_PP32_ENET_MAC_DA0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061B * 4))) -+#define IFX_PP32_ENET_MAC_DA1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x061C * 4))) -+ -+#define IFX_PP32_ENETF_DBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0630 * 4))) -+#define IFX_PP32_ENETF_CBA ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0631 * 4))) -+#define IFX_PP32_ENETF_CFG ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0632 * 4))) -+#define IFX_PP32_ENETF_PGCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0633 * 4))) -+#define IFX_PP32_ENETF_PKTCNT ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0634 * 4))) -+#define IFX_PP32_ENETF_HFCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0635 * 4))) -+#define IFX_PP32_ENETF_TXCTRL ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0636 * 4))) -+ -+#define IFX_PP32_ENETF_VLCOS0 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0638 * 4))) -+#define IFX_PP32_ENETF_VLCOS1 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x0639 * 4))) -+#define IFX_PP32_ENETF_VLCOS2 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063A * 4))) -+#define IFX_PP32_ENETF_VLCOS3 ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063B * 4))) -+#define IFX_PP32_ENETF_EGERR ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063C * 4))) -+#define IFX_PP32_ENETF_EGDROP ((volatile u32 *)(IFX_PPE32_DATA_MEM_MAP_REG_BASE + (0x063D * 4))) -+ -+ -+/* Sharebuff SB RAM2 control data */ -+#define IFX_PP32_SB2_DATABASE ((IFX_PPE32_BASE + (0x8C00 * 4))) -+#define IFX_PP32_SB2_CTRLBASE ((IFX_PPE32_BASE + (0x92E0 * 4))) -+ -+ -+ -+/************************************************************************/ -+/* Module : 3-port Switch register address and bits */ -+/************************************************************************/ -+ -+#define IFX_SW (KSEG1 | 0x1E108000) -+ -+#define IFX_SW_PS (IFX_SW + 0x000) -+#define IFX_SW_P0_CTL (IFX_SW + 0x004) -+#define IFX_SW_P1_CTL (IFX_SW + 0x008) -+#define IFX_SW_P2_CTL (IFX_SW + 0x00C) -+#define IFX_SW_P0_VLAN (IFX_SW + 0x010) -+#define IFX_SW_P1_VLAN (IFX_SW + 0x014) -+#define IFX_SW_P2_VLAN (IFX_SW + 0x018) -+#define IFX_SW_P0_INCTL (IFX_SW + 0x020) -+#define IFX_SW_P1_INCTL (IFX_SW + 0x024) -+#define IFX_SW_P2_INCTL (IFX_SW + 0x028) -+#define IFX_SW_DF_PORTMAP (IFX_SW + 0x02C) -+#define IFX_SW_P0_ECS_Q32 (IFX_SW + 0x030) -+#define IFX_SW_P0_ECS_Q10 (IFX_SW + 0x034) -+#define IFX_SW_P0_ECW_Q32 (IFX_SW + 0x038) -+#define IFX_SW_P0_ECW_Q10 (IFX_SW + 0x03C) -+#define IFX_SW_P1_ECS_Q32 (IFX_SW + 0x040) -+#define IFX_SW_P1_ECS_Q10 (IFX_SW + 0x044) -+#define IFX_SW_P1_ECW_Q32 (IFX_SW + 0x048) -+#define IFX_SW_P1_ECW_Q10 (IFX_SW + 0x04C) -+#define IFX_SW_P2_ECS_Q32 (IFX_SW + 0x050) -+#define IFX_SW_P2_ECS_Q10 (IFX_SW + 0x054) -+#define IFX_SW_P2_ECW_Q32 (IFX_SW + 0x058) -+#define IFX_SW_P2_ECW_Q10 (IFX_SW + 0x05C) -+#define IFX_SW_INT_ENA (IFX_SW + 0x060) -+#define IFX_SW_INT_ST (IFX_SW + 0x064) -+#define IFX_SW_GCTL0 (IFX_SW + 0x068) -+#define IFX_SW_GCTL1 (IFX_SW + 0x06C) -+#define IFX_SW_ARP (IFX_SW + 0x070) -+#define IFX_SW_STRM_CTL (IFX_SW + 0x074) -+#define IFX_SW_RGMII_CTL (IFX_SW + 0x078) -+#define IFX_SW_1P_PRT (IFX_SW + 0x07C) -+#define IFX_SW_GBKT_SZBS (IFX_SW + 0x080) -+#define IFX_SW_GBKT_SZEBS (IFX_SW + 0x084) -+#define IFX_SW_BF_TH (IFX_SW + 0x088) -+#define IFX_SW_PMAC_HD_CTL (IFX_SW + 0x08C) -+#define IFX_SW_PMAC_SA1 (IFX_SW + 0x090) -+#define IFX_SW_PMAC_SA2 (IFX_SW + 0x094) -+#define IFX_SW_PMAC_DA1 (IFX_SW + 0x098) -+#define IFX_SW_PMAC_DA2 (IFX_SW + 0x09C) -+#define IFX_SW_PMAC_VLAN (IFX_SW + 0x0A0) -+#define IFX_SW_PMAC_TX_IPG (IFX_SW + 0x0A4) -+#define IFX_SW_PMAC_RX_IPG (IFX_SW + 0x0A8) -+#define IFX_SW_ADR_TB_CTL0 (IFX_SW + 0x0AC) -+#define IFX_SW_ADR_TB_CTL1 (IFX_SW + 0x0B0) -+#define IFX_SW_ADR_TB_CTL2 (IFX_SW + 0x0B4) -+#define IFX_SW_ADR_TB_ST0 (IFX_SW + 0x0B8) -+#define IFX_SW_ADR_TB_ST1 (IFX_SW + 0x0BC) -+#define IFX_SW_ADR_TB_ST2 (IFX_SW + 0x0C0) -+#define IFX_SW_RMON_CTL (IFX_SW + 0x0C4) -+#define IFX_SW_RMON_ST (IFX_SW + 0x0C8) -+#define IFX_SW_MDIO_CTL (IFX_SW + 0x0CC) -+#define IFX_SW_MDIO_DATA (IFX_SW + 0x0D0) -+#define IFX_SW_TP_FLT_ACT (IFX_SW + 0x0D4) -+#define IFX_SW_PRTCL_FLT_ACT (IFX_SW + 0x0D8) -+#define IFX_SW_VLAN_FLT0 (IFX_SW + 0x100) -+#define IFX_SW_VLAN_FLT1 (IFX_SW + 0x104) -+#define IFX_SW_VLAN_FLT2 (IFX_SW + 0x108) -+#define IFX_SW_VLAN_FLT3 (IFX_SW + 0x10C) -+#define IFX_SW_VLAN_FLT4 (IFX_SW + 0x110) -+#define IFX_SW_VLAN_FLT5 (IFX_SW + 0x114) -+#define IFX_SW_VLAN_FLT6 (IFX_SW + 0x118) -+#define IFX_SW_VLAN_FLT7 (IFX_SW + 0x11C) -+#define IFX_SW_VLAN_FLT8 (IFX_SW + 0x120) -+#define IFX_SW_VLAN_FLT9 (IFX_SW + 0x124) -+#define IFX_SW_VLAN_FLT10 (IFX_SW + 0x128) -+#define IFX_SW_VLAN_FLT11 (IFX_SW + 0x12C) -+#define IFX_SW_VLAN_FLT12 (IFX_SW + 0x130) -+#define IFX_SW_VLAN_FLT13 (IFX_SW + 0x134) -+#define IFX_SW_VLAN_FLT14 (IFX_SW + 0x138) -+#define IFX_SW_VLAN_FLT15 (IFX_SW + 0x13C) -+#define IFX_SW_TP_FLT10 (IFX_SW + 0x140) -+#define IFX_SW_TP_FLT32 (IFX_SW + 0x144) -+#define IFX_SW_TP_FLT54 (IFX_SW + 0x148) -+#define IFX_SW_TP_FLT76 (IFX_SW + 0x14C) -+#define IFX_SW_DFSRV_MAP0 (IFX_SW + 0x150) -+#define IFX_SW_DFSRV_MAP1 (IFX_SW + 0x154) -+#define IFX_SW_DFSRV_MAP2 (IFX_SW + 0x158) -+#define IFX_SW_DFSRV_MAP3 (IFX_SW + 0x15C) -+#define IFX_SW_TCP_PF0 (IFX_SW + 0x160) -+#define IFX_SW_TCP_PF1 (IFX_SW + 0x164) -+#define IFX_SW_TCP_PF2 (IFX_SW + 0x168) -+#define IFX_SW_TCP_PF3 (IFX_SW + 0x16C) -+#define IFX_SW_TCP_PF4 (IFX_SW + 0x170) -+#define IFX_SW_TCP_PF5 (IFX_SW + 0x174) -+#define IFX_SW_TCP_PF6 (IFX_SW + 0x178) -+#define IFX_SW_TCP_PF7 (IFX_SW + 0x17C) -+#define IFX_SW_RA_03_00 (IFX_SW + 0x180) -+#define IFX_SW_RA_07_04 (IFX_SW + 0x184) -+#define IFX_SW_RA_0B_08 (IFX_SW + 0x188) -+#define IFX_SW_RA_0F_0C (IFX_SW + 0x18C) -+#define IFX_SW_RA_13_10 (IFX_SW + 0x190) -+#define IFX_SW_RA_17_14 (IFX_SW + 0x194) -+#define IFX_SW_RA_1B_18 (IFX_SW + 0x198) -+#define IFX_SW_RA_1F_1C (IFX_SW + 0x19C) -+#define IFX_SW_RA_23_20 (IFX_SW + 0x1A0) -+#define IFX_SW_RA_27_24 (IFX_SW + 0x1A4) -+#define IFX_SW_RA_2B_28 (IFX_SW + 0x1A8) -+#define IFX_SW_RA_2F_2C (IFX_SW + 0x1AC) -+#define IFX_SW_F0 (IFX_SW + 0x1B0) -+#define IFX_SW_F1 (IFX_SW + 0x1B4) -+ -+/************************************************************************/ -+/* Module : XBAR Register definition */ -+/************************************************************************/ -+#define IFX_XBAR_REG_BASE (KSEG1 | 0x1F400000) -+ -+#define IFX_XBAR_ALWAYS_LAST (volatile u32*)(IFX_XBAR_REG_BASE + 0x430) -+#define IFX_XBAR_FPI_BURST_EN 0x00000002 -+#define IFX_XBAR_AHB_BURST_EN 0x00000004 -+#define IFX_XBAR_DDR_SEL_EN 0x00000001 -+ -+/* -+ * Routine for Voice -+ */ -+extern const void (*ifx_bsp_basic_mps_decrypt)(unsigned int addr, int n); -+extern int ifx_is_vr9_a21_chip(void); -+ -+#endif /* VR9_H */ -diff --git a/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h b/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h -new file mode 100644 -index 0000000..4dfe3dc ---- /dev/null -+++ b/arch/mips/include/asm/ifx/vr9/vr9_ref_board.h -@@ -0,0 +1,46 @@ -+/****************************************************************************** -+** -+** FILE NAME : vr9_ref_board.h -+** PROJECT : IFX UEIP -+** MODULES : BSP Basic -+** -+** DATE : 27 May 2009 -+** AUTHOR : Xu Liang -+** DESCRIPTION : header file for VR9 -+** COPYRIGHT : Copyright (c) 2009 -+** Infineon Technologies AG -+** Am Campeon 1-12, 85579 Neubiberg, Germany -+** -+** This program is free software; you can redistribute it and/or modify -+** it under the terms of the GNU General Public License as published by -+** the Free Software Foundation; either version 2 of the License, or -+** (at your option) any later version. -+** -+** HISTORY -+** $Date $Author $Comment -+** 27 May 2009 Xu Liang The first UEIP release -+*******************************************************************************/ -+ -+ -+ -+#ifndef VR9_REF_BOARD_H -+#define VR9_REF_BOARD_H -+ -+#if defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) \ -+ || defined(CONFIG_IFX_USIF_SPI_FLASH) || defined (CONFIG_IFX_USIF_SPI_FLASH_MODULE) -+#define IFX_MTD_SPI_PART_NB 3 -+#define IFX_SPI_FLASH_MAX 8 -+#endif /* defined(CONFIG_IFX_SPI_FLASH) || defined (CONFIG_IFX_SPI_FLASH_MODULE) */ -+ -+#if defined(CONFIG_USB_HOST_IFX) || defined(CONFIG_USB_HOST_IFX_MODULE) -+ #if 1 -+// #define IFX_GPIO_USB_VBUS IFX_GPIO_PIN_ID(2, 1) -+ #else -+ #define IFX_GPIO_USB_VBUS1 IFX_GPIO_PIN_ID(1, 13) -+ #define IFX_GPIO_USB_VBUS2 IFX_GPIO_PIN_ID(3, 0) -+ #endif -+#endif -+ -+ -+#endif /* VR9_REF_BOARD_H */ -+ -diff --git a/arch/mips/include/asm/ifx/war.h b/arch/mips/include/asm/ifx/war.h -new file mode 100644 -index 0000000..958d04d ---- /dev/null -+++ b/arch/mips/include/asm/ifx/war.h -@@ -0,0 +1,25 @@ -+/* -+ * This file is subject to the terms and conditions of the GNU General Public -+ * License. See the file "COPYING" in the main directory of this archive -+ * for more details. -+ * -+ * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org> -+ */ -+#ifndef __ASM_MIPS_IFX_WAR_H -+#define __ASM_MIPS_IFX_WAR_H -+ -+#define R4600_V1_INDEX_ICACHEOP_WAR 0 -+#define R4600_V1_HIT_CACHEOP_WAR 0 -+#define R4600_V2_HIT_CACHEOP_WAR 0 -+#define R5432_CP0_INTERRUPT_WAR 0 -+#define BCM1250_M3_WAR 0 -+#define SIBYTE_1956_WAR 0 -+#define MIPS4K_ICACHE_REFILL_WAR 0 -+#define MIPS_CACHE_SYNC_WAR 0 -+#define TX49XX_ICACHE_INDEX_INV_WAR 0 -+#define RM9000_CDEX_SMP_WAR 0 -+#define ICACHE_REFILLS_WORKAROUND_WAR 0 -+#define R10000_LLSC_WAR 0 -+#define MIPS34K_MISSED_ITLB_WAR 0 -+ -+#endif /* __ASM_MIPS_IFX_WAR_H */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h -new file mode 100644 -index 0000000..c094e5d ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/cpu-feature-overrides.h -@@ -0,0 +1,58 @@ -+/* -+ * Lantiq FALCON specific CPU feature overrides -+ * -+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland -+ * -+ * This file was derived from: include/asm-mips/cpu-features.h -+ * Copyright (C) 2003, 2004 Ralf Baechle -+ * Copyright (C) 2004 Maciej W. Rozycki -+ * -+ * This program is free software; you can redistribute it and/or modify it -+ * under the terms of the GNU General Public License version 2 as published -+ * by the Free Software Foundation. -+ * -+ */ -+#ifndef __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H -+#define __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H -+ -+#define cpu_has_tlb 1 -+#define cpu_has_4kex 1 -+#define cpu_has_3k_cache 0 -+#define cpu_has_4k_cache 1 -+#define cpu_has_tx39_cache 0 -+#define cpu_has_sb1_cache 0 -+#define cpu_has_fpu 0 -+#define cpu_has_32fpr 0 -+#define cpu_has_counter 1 -+#define cpu_has_watch 1 -+#define cpu_has_divec 1 -+ -+#define cpu_has_prefetch 1 -+#define cpu_has_ejtag 1 -+#define cpu_has_llsc 1 -+ -+#define cpu_has_mips16 1 -+#define cpu_has_mdmx 0 -+#define cpu_has_mips3d 0 -+#define cpu_has_smartmips 0 -+ -+#define cpu_has_mips32r1 1 -+#define cpu_has_mips32r2 1 -+#define cpu_has_mips64r1 0 -+#define cpu_has_mips64r2 0 -+ -+#define cpu_has_dsp 1 -+#define cpu_has_mipsmt 1 -+ -+#define cpu_has_vint 1 -+#define cpu_has_veic 1 -+ -+#define cpu_has_64bits 0 -+#define cpu_has_64bit_zero_reg 0 -+#define cpu_has_64bit_gp_regs 0 -+#define cpu_has_64bit_addresses 0 -+ -+#define cpu_dcache_line_size() 32 -+#define cpu_icache_line_size() 32 -+ -+#endif /* __ASM_MACH_FALCON_CPU_FEATURE_OVERRIDES_H */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h -new file mode 100644 -index 0000000..c47f5e1 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/ebu_reg.h -@@ -0,0 +1,1520 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _ebu_reg_h -+#define _ebu_reg_h -+ -+/** \addtogroup EBU_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define ebu_r32(reg) reg_r32(&ebu->reg) -+#define ebu_w32(val, reg) reg_w32(val, &ebu->reg) -+#define ebu_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &ebu->reg) -+#define ebu_r32_table(reg, idx) reg_r32_table(ebu->reg, idx) -+#define ebu_w32_table(val, reg, idx) reg_w32_table(val, ebu->reg, idx) -+#define ebu_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, ebu->reg, idx) -+#define ebu_adr_table(reg, idx) adr_table(ebu->reg, idx) -+ -+ -+/** EBU register structure */ -+struct gpon_reg_ebu -+{ -+ /** Reserved */ -+ unsigned int res_0[2]; /* 0x00000000 */ -+ /** Module ID Register -+ Module type and version identifier */ -+ unsigned int modid; /* 0x00000008 */ -+ /** Module Control Register -+ This register contains general configuration information observed for all CS regions or dealing with EBU functionality that is not directly related to external memory access. */ -+ unsigned int modcon; /* 0x0000000C */ -+ /** Bus Read Configuration Register0 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int busrcon0; /* 0x00000010 */ -+ /** Bus Read Parameters Register0 */ -+ unsigned int busrp0; /* 0x00000014 */ -+ /** Bus Write Configuration Register0 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int buswcon0; /* 0x00000018 */ -+ /** Bus Write Parameters Register0 */ -+ unsigned int buswp0; /* 0x0000001C */ -+ /** Bus Read Configuration Register1 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int busrcon1; /* 0x00000020 */ -+ /** Bus Read Parameters Register1 */ -+ unsigned int busrp1; /* 0x00000024 */ -+ /** Bus Write Configuration Register1 -+ Note: The actual length of field enable depends on the number of bus ports connected to the EBU. For the GPON it is a single port (the bridge to the Asynchronous Xbar) so only bit 0 is implemented with all other bits tied to '0'. */ -+ unsigned int buswcon1; /* 0x00000028 */ -+ /** Bus Write Parameters Register1 */ -+ unsigned int buswp1; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[8]; /* 0x00000030 */ -+ /** Bus Protocol Configuration Extension Register 0 */ -+ unsigned int busconext0; /* 0x00000050 */ -+ /** Bus Protocol Configuration Extension Register 1 */ -+ unsigned int busconext1; /* 0x00000054 */ -+ /** Reserved */ -+ unsigned int res_2[10]; /* 0x00000058 */ -+ /** Serial Flash Configuration Register -+ The content of this register configures the EBU's Serial Flash protocol engine. */ -+ unsigned int sfcon; /* 0x00000080 */ -+ /** Serial Flash Timing Register -+ This register defines the signal timing for the Serial Flash Access. See Section 3.18.3 on page 112 for details. */ -+ unsigned int sftime; /* 0x00000084 */ -+ /** Serial Flash Status Register -+ This register holds status information on the Serial Flash device(s) attached and the EBU's Serial Flash protocol engine. */ -+ unsigned int sfstat; /* 0x00000088 */ -+ /** Serial Flash Command Register -+ When writing to this register's opcode field, a command is started in the EBU's Serial Flash controller. */ -+ unsigned int sfcmd; /* 0x0000008C */ -+ /** Serial Flash Address Register -+ This register holds the address to be sent (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 3.18.2.4.1 on page 103). */ -+ unsigned int sfaddr; /* 0x00000090 */ -+ /** Serial Flash Data Register -+ This register holds the data being transferred (if any) with accesses to/from a Serial Flash started by writing to EBU_SFCMD (Indirect Access Mode, see Section 4.18.2.4.1 on page 116). */ -+ unsigned int sfdata; /* 0x00000094 */ -+ /** Serial Flash I/O Control Register -+ This register provides additional configuration for controlling the IO pads of the Serial Flash interface. */ -+ unsigned int sfio; /* 0x00000098 */ -+ /** Reserved */ -+ unsigned int res_3[25]; /* 0x0000009C */ -+}; -+ -+ -+/* Fields of "Module ID Register" */ -+/** Feature Select -+ This field indicates the types of external devices/protocols supported by the GPON version of the EBU. */ -+#define MODID_FSEL_MASK 0xE0000000 -+/** field offset */ -+#define MODID_FSEL_OFFSET 29 -+/** Support for SRAM, NAND/NOR/OneNand Flash and Cellular RAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM 0x00000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR SDRAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_SDR 0x20000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM and SDR/DDR SDRAM is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR 0x40000000 -+/** Support for SRAM, NAND/NOR/OneNand Flash, Cellular RAM, SDR/DDR SDRAM 0nd LPDDR-Flash is implemented. */ -+#define MODID_FSEL_SRAM_FLASH_CRAM_DDR_LPNVM 0x60000000 -+/** Serial Flash Support -+ Indicates whether or not the support of Serial Flash devices is available. */ -+#define MODID_SF 0x10000000 -+/* Not Available -+#define MODID_SF_NAV 0x00000000 */ -+/** Available */ -+#define MODID_SF_AV 0x10000000 -+/** AAD-mux Support -+ Indicates whether or not the GPON EBU supports AAD-mux protocol for Burst Flash and Cellular RAM. */ -+#define MODID_AAD 0x08000000 -+/* Not Available -+#define MODID_AAD_NAV 0x00000000 */ -+/** Available */ -+#define MODID_AAD_AV 0x08000000 -+/** Indicates whether or not the GPON EBU implements a DLL which is e.g. used for 50% duty cycle external clock generation. Note that a DLL is always implemented if DDR-SDRAM support is selected. */ -+#define MODID_DLL 0x04000000 -+/* Not Available -+#define MODID_DLL_NAV 0x00000000 */ -+/** Available */ -+#define MODID_DLL_AV 0x04000000 -+/** Pad Multiplexing Scheme */ -+#define MODID_PMS_MASK 0x03000000 -+/** field offset */ -+#define MODID_PMS_OFFSET 24 -+/** The EBU comprises of dedicated address pins A[EXTAW-1=:16]. */ -+#define MODID_PMS_PMS_CLASSIC 0x00000000 -+/** Revision -+ Revision Number */ -+#define MODID_REV_MASK 0x000F0000 -+/** field offset */ -+#define MODID_REV_OFFSET 16 -+/** Module ID -+ This field contains the EBU's unique peripheral ID. */ -+#define MODID_ID_MASK 0x0000FF00 -+/** field offset */ -+#define MODID_ID_OFFSET 8 -+/** Version -+ This field gives the EBU version number. */ -+#define MODID_VERSION_MASK 0x000000FF -+/** field offset */ -+#define MODID_VERSION_OFFSET 0 -+ -+/* Fields of "Module Control Register" */ -+/** Reserved */ -+#define MODCON_DLLUPDINT_MASK 0xC0000000 -+/** field offset */ -+#define MODCON_DLLUPDINT_OFFSET 30 -+/** Access Inhibit Acknowledge -+ After suspension of all accesses to the External Bus has been requested by setting bit acc_inh, acc_inh_ack acknowledges the request and inidcates that access suspension is now in effect. The bit is cleared when acc_inh gets deasserted. */ -+#define MODCON_AIA 0x02000000 -+/* no access restriction are active in the EBU subsystem -+#define MODCON_AIA_NO_INHIBIT 0x00000000 */ -+/** accesses are restricted to selected (configuration) system bus port(s) */ -+#define MODCON_AIA_INHIBIT 0x02000000 -+/** Access Inhibit request -+ Setting this bit will suspend all non-CPU system bus ports and the EBU itself from accessing the External Bus. This feature is usually used when the CPU needs to reconfigure protocol parameters in the EBU in order to avoid external accesses with invalid settings. The EBU acknowledges that the access suspension is in effect by asserting acc_inh_ack. */ -+#define MODCON_AI 0x01000000 -+/* no access restriction are active in the EBU subsystem -+#define MODCON_AI_NO_INHIBIT 0x00000000 */ -+/** accesses are restricted to selected (configuration) system bus port(s) */ -+#define MODCON_AI_INHIBIT 0x01000000 -+/** Lock Timeout */ -+#define MODCON_LTO_MASK 0x00FF0000 -+/** field offset */ -+#define MODCON_LTO_OFFSET 16 -+/** Reserved */ -+#define MODCON_DDREN 0x00008000 -+/** Pad Drive Control -+ Intended to be used to control the EBU pad''s drive strength. Refer to the GPON chip specification to see which drive strnegth options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_PEXT 0x00004000 -+/* Normal drive -+#define MODCON_PEXT_NORMAL 0x00000000 */ -+/** Strong drive */ -+#define MODCON_PEXT_STRONG 0x00004000 -+/** Pad Slew Falling Edge Control -+ Intended to be used to trim the External Bus pad's falling edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_SLF 0x00002000 -+/* Slow slew rate -+#define MODCON_SLF_SLOW 0x00000000 */ -+/** Fast slew rate */ -+#define MODCON_SLF_FAST 0x00002000 -+/** Pad Slew Rising Edge Control -+ Intended to be used to trim the External Bus pad's rising edge slew rate. Refer to the GPON chip specification to see which slew rate options are available and whether they are actually controlled by the EBU's register bit. The value stored in this register bit is directly connected to the corresponding output of the EBU module and takes no functional effect within the EBU itself. */ -+#define MODCON_SLR 0x00001000 -+/* Slow slew rate -+#define MODCON_SLR_SLOW 0x00000000 */ -+/** Fast slew rate */ -+#define MODCON_SLR_FAST 0x00001000 -+/** Write Buffering Mode -+ This bit controls when the EBU starts a new write burst transaction from the Memport interface. */ -+#define MODCON_WBM 0x00000040 -+/* The EBU starts a write transaction on the External Bus as early as possible, expecting that the n beats of the write burst will be transferred within n or n+1 clock cycles over the EBU's Memport interface. Use this mode if the EBU is clocked at the same or a slower frequency than the system bus interconnect. -+#define MODCON_WBM_START_WRITE_EARLY 0x00000000 */ -+/** The EBU start a write transaction only after all data of a write burst have been received over the EBU's Memport interface. Use this mode if the EBU is clocked at a higher frequency than the system bus interrconnect. */ -+#define MODCON_WBM_START_WRITE_LATE 0x00000040 -+/** Reserved */ -+#define MODCON_SDCLKEN 0x00000020 -+/** Standby Mode Enable -+ When set allows the EBU subsystem to enter standby mode in response to a rising edge on input signal standby_req_i. See Section 3.9.3 for details. */ -+#define MODCON_STBYEN 0x00000010 -+/* Disable -+#define MODCON_STBYEN_DIS 0x00000000 */ -+/** Enable */ -+#define MODCON_STBYEN_EN 0x00000010 -+/** Enable BFCLK1 -+ This field will enables or disables mirroring the clock that is output on BFCLKO_0 also on pad BFCLKO_1 to double the drive strength. See also Section 3.17.3) */ -+#define MODCON_BFCLK1EN 0x00000008 -+/* Disable -+#define MODCON_BFCLK1EN_DIS 0x00000000 */ -+/** Enable */ -+#define MODCON_BFCLK1EN_EN 0x00000008 -+/** Ready/Busy Status Edge -+ This is a read-only bit which shows a change of the logic level shown in the sts field since last read. It is reset by a read access. */ -+#define MODCON_STSEDGE 0x00000004 -+/** Ready/Busy Status -+ This is a read-only bit which reflects the current logic level present on the RDY/BSY or STS input pin which is (optionally) fed-in from a General Purpose I/O pad which is not part of the EBU via the EBU's input pin signal gpio_nand_rdy_ */ -+#define MODCON_STS 0x00000002 -+/** External Bus Arbitration Mode -+ This bit allows to disconnect the EBU from the External Bus. While EBU_MODCON.acc_inh_ack is 0, the value of arb_mode is forced to OWN_BUS. */ -+#define MODCON_AM 0x00000001 -+/* The EBU does not own the bus (multi-master) -+#define MODCON_AM_SHAREDBUS 0x00000000 */ -+/** The EBU owns the external bus. */ -+#define MODCON_AM_OWNBUS 0x00000001 -+ -+/* Fields of "Bus Read Configuration Register0" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSRCON0_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSRCON0_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSRCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSRCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSRCON0_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSRCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSRCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSRCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSRCON0_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSRCON0_PORTW_OFFSET 26 -+/** 8-bit multiplexed */ -+#define BUSRCON0_PORTW_8_BIT_MUX 0x00000000 -+/** 16-bit multiplexed */ -+#define BUSRCON0_PORTW_16_BIT_MUX 0x04000000 -+/** Twin, 16-bit multiplexed */ -+#define BUSRCON0_PORTW_TWIN_16_BIT_MUX 0x08000000 -+/** 32-bit multiplexed */ -+#define BUSRCON0_PORTW_32_BIT_MUX 0x0C000000 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSRCON0_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSRCON0_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSRCON0_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSRCON0_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSRCON0_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSRCON0_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSRCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSRCON0_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Disable Burst Address Wrapping */ -+#define BUSRCON0_DBA 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSRCON0_WAITINV 0x00400000 -+/* Low active. -+#define BUSRCON0_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSRCON0_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSRCON0_EBSE 0x00200000 -+/* Low active. -+#define BUSRCON0_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON0_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSRCON0_ECSE 0x00100000 -+/* Low active. -+#define BUSRCON0_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON0_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSRCON0_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSRCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSRCON0_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSRCON0_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSRCON0_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSRCON0_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSRCON0_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSRCON0_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSRCON0_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON0_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSRCON0_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSRCON0_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSRCON0_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSRCON0_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSRCON0_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSRCON0_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSRCON0_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSRCON0_AAP_LATE 0x00001000 -+/** Burst Flash Read Single Stage Synchronisation */ -+#define BUSRCON0_BFSSS 0x00000800 -+/* Two stages of synchronisation used. -+#define BUSRCON0_BFSSS_TWO_STAGE 0x00000000 */ -+/** Single stage of synchronisation used. */ -+#define BUSRCON0_BFSSS_SINGLE_STAGE 0x00000800 -+/** Burst Flash Clock Feedback Enable */ -+#define BUSRCON0_FDBKEN 0x00000400 -+/* Disable -+#define BUSRCON0_FDBKEN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_FDBKEN_EN 0x00000400 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSRCON0_CSA 0x00000200 -+/* Disable -+#define BUSRCON0_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSRCON0_NAA 0x00000100 -+/* Disable -+#define BUSRCON0_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSRCON0_ENABLE 0x00000001 -+/* Disable -+#define BUSRCON0_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON0_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Read Parameters Register0" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSRP0_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSRP0_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSRP0_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSRP0_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSRP0_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSRP0_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSRP0_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSRP0_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSRP0_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSRP0_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSRP0_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSRP0_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSRP0_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSRP0_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSRP0_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSRP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For read Accesses -+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ -+#define BUSRP0_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSRP0_DATAC_OFFSET 12 -+/** Programmed Wait States for read accesses -+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSRP0_WAITRDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSRP0_WAITRDC_OFFSET 7 -+/** Recovery Cycles After read Accesses, same CS -+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP0_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSRP0_RECOVC_OFFSET 4 -+/** Recovery Cycles After read Accesses, other CS -+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP0_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSRP0_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Write Configuration Register0" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSWCON0_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSWCON0_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSWCON0_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSWCON0_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSWCON0_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSWCON0_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSWCON0_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSWCON0_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSWCON0_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSWCON0_PORTW_OFFSET 26 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSWCON0_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSWCON0_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSWCON0_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSWCON0_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSWCON0_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSWCON0_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSWCON0_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSWCON0_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Reserved */ -+#define BUSWCON0_LOCKCS 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSWCON0_WAITINV 0x00400000 -+/* Low active. -+#define BUSWCON0_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSWCON0_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSWCON0_EBSE 0x00200000 -+/* Low active. -+#define BUSWCON0_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON0_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSWCON0_ECSE 0x00100000 -+/* Low active. -+#define BUSWCON0_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON0_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSWCON0_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSWCON0_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSWCON0_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSWCON0_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSWCON0_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSWCON0_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSWCON0_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSWCON0_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSWCON0_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON0_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON0_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSWCON0_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSWCON0_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSWCON0_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSWCON0_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSWCON0_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSWCON0_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSWCON0_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSWCON0_AAP_LATE 0x00001000 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSWCON0_CSA 0x00000200 -+/* Disable -+#define BUSWCON0_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSWCON0_NAA 0x00000100 -+/* Disable -+#define BUSWCON0_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSWCON0_ENABLE 0x00000001 -+/* Disable -+#define BUSWCON0_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON0_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Write Parameters Register0" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSWP0_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSWP0_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSWP0_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSWP0_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSWP0_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSWP0_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSWP0_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSWP0_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSWP0_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSWP0_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSWP0_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSWP0_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSWP0_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSWP0_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSWP0_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSWP0_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For write Accesses -+ Number of data hold cycles during write accesses. */ -+#define BUSWP0_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSWP0_DATAC_OFFSET 12 -+/** Programmed Wait States For write Accesses -+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSWP0_WAITWDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSWP0_WAITWDC_OFFSET 7 -+/** Recovery Cycles After write Accesses, same CS -+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP0_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSWP0_RECOVC_OFFSET 4 -+/** Recovery Cycles After write Accesses, other CS -+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP0_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSWP0_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Read Configuration Register1" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSRCON1_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSRCON1_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSRCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSRCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSRCON1_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSRCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSRCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSRCON1_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSRCON1_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSRCON1_PORTW_OFFSET 26 -+/** 8-bit multiplexed */ -+#define BUSRCON1_PORTW_8_BIT_MUX 0x00000000 -+/** 16-bit multiplexed */ -+#define BUSRCON1_PORTW_16_BIT_MUX 0x04000000 -+/** Twin, 16-bit multiplexed */ -+#define BUSRCON1_PORTW_TWIN_16_BIT_MUX 0x08000000 -+/** 32-bit multiplexed */ -+#define BUSRCON1_PORTW_32_BIT_MUX 0x0C000000 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSRCON1_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSRCON1_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSRCON1_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSRCON1_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSRCON1_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSRCON1_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSRCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSRCON1_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Disable Burst Address Wrapping */ -+#define BUSRCON1_DBA 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSRCON1_WAITINV 0x00400000 -+/* Low active. -+#define BUSRCON1_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSRCON1_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSRCON1_EBSE 0x00200000 -+/* Low active. -+#define BUSRCON1_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON1_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSRCON1_ECSE 0x00100000 -+/* Low active. -+#define BUSRCON1_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSRCON1_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSRCON1_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSRCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSRCON1_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSRCON1_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSRCON1_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSRCON1_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSRCON1_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSRCON1_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSRCON1_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON1_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSRCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSRCON1_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSRCON1_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSRCON1_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSRCON1_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSRCON1_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSRCON1_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSRCON1_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSRCON1_AAP_LATE 0x00001000 -+/** Burst Flash Read Single Stage Synchronisation */ -+#define BUSRCON1_BFSSS 0x00000800 -+/* Two stages of synchronisation used. -+#define BUSRCON1_BFSSS_TWO_STAGE 0x00000000 */ -+/** Single stage of synchronisation used. */ -+#define BUSRCON1_BFSSS_SINGLE_STAGE 0x00000800 -+/** Burst Flash Clock Feedback Enable */ -+#define BUSRCON1_FDBKEN 0x00000400 -+/* Disable -+#define BUSRCON1_FDBKEN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_FDBKEN_EN 0x00000400 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSRCON1_CSA 0x00000200 -+/* Disable -+#define BUSRCON1_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSRCON1_NAA 0x00000100 -+/* Disable -+#define BUSRCON1_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSRCON1_ENABLE 0x00000001 -+/* Disable -+#define BUSRCON1_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSRCON1_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Read Parameters Register1" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSRP1_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSRP1_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSRP1_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSRP1_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSRP1_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSRP1_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSRP1_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSRP1_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSRP1_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSRP1_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSRP1_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSRP1_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSRP1_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSRP1_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSRP1_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSRP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For read Accesses -+ Number of data hold cycles during read accesses. Applies to spinner support only where the address is guaranteed stable for datac clocks after RD high */ -+#define BUSRP1_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSRP1_DATAC_OFFSET 12 -+/** Programmed Wait States for read accesses -+ Number of programmed wait states for read accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSRP1_WAITRDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSRP1_WAITRDC_OFFSET 7 -+/** Recovery Cycles After read Accesses, same CS -+ Number of idle cycles after read accesses when the next access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP1_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSRP1_RECOVC_OFFSET 4 -+/** Recovery Cycles After read Accesses, other CS -+ Number of idle cycles after read accesses when the next access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSRCON. */ -+#define BUSRP1_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSRP1_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Write Configuration Register1" */ -+/** Device Type For Region -+ After reset, the CS region is configured for a slow Asynchronous access protocol which is compatible with read access from an external multiplexed or demultiplexed 16-Bit Burst Flash in asynchronous mode. Reset: 0000B */ -+#define BUSWCON1_AGEN_MASK 0xF0000000 -+/** field offset */ -+#define BUSWCON1_AGEN_OFFSET 28 -+/** Muxed Asynchronous Type External Memory */ -+#define BUSWCON1_AGEN_MUXED_ASYNC_TYPE_EXT_MEM 0x00000000 -+/** Muxed Burst Type External Memory */ -+#define BUSWCON1_AGEN_MUXED_BURST_TYPE_EXT_MEM 0x10000000 -+/** NAND Flash (page optimised) */ -+#define BUSWCON1_AGEN_NAND_FLASH 0x20000000 -+/** Muxed Cellular RAM External Memory */ -+#define BUSWCON1_AGEN_MUXED_CELLULAR_RAM_EXT_MEM 0x30000000 -+/** Demuxed Asynchronous Type External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_ASYNC_TYPE_EXT_MEM 0x40000000 -+/** Demuxed Burst Type External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_BURST_TYPE_EXT_MEM 0x50000000 -+/** Demuxed Page Mode External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_PAGE_MODE_EXT_MEM 0x60000000 -+/** Demuxed Cellular RAM External Memory */ -+#define BUSWCON1_AGEN_DEMUXED_CELLULAR_RAM_EXT_MEM 0x70000000 -+/** Serial Flash */ -+#define BUSWCON1_AGEN_SERIAL_FLASH 0xF0000000 -+/** Device Addressing Mode -+ t.b.d. */ -+#define BUSWCON1_PORTW_MASK 0x0C000000 -+/** field offset */ -+#define BUSWCON1_PORTW_OFFSET 26 -+/** External Wait Control -+ Function of the WAIT input. This is specific to the device type (i.e. the agen field). */ -+#define BUSWCON1_WAIT_MASK 0x03000000 -+/** field offset */ -+#define BUSWCON1_WAIT_OFFSET 24 -+/** WAIT is ignored (default after reset). */ -+#define BUSWCON1_WAIT_OFF 0x00000000 -+/** Synchronous Burst Devices: WAIT signal is provided one cycle ahead of the data cycle it applies to. */ -+#define BUSWCON1_WAIT_EARLY_WAIT 0x01000000 -+/** Asynchronous Devices: WAIT input passes through a two-stage synchronizer before being evaluated. */ -+#define BUSWCON1_WAIT_TWO_STAGE_SYNC 0x01000000 -+/** Synchronous Burst Devices: WAIT signal is provided in the same data cycle it applies to. */ -+#define BUSWCON1_WAIT_WAIT_WITH_DATA 0x02000000 -+/** Asynchronous Devices: WAIT input passes through a single-stage synchronizer before being evaluated. */ -+#define BUSWCON1_WAIT_SINGLE_STAGE_SYNC 0x02000000 -+/** Synchronous Burst Devices: Abort and retry access if WAIT asserted */ -+#define BUSWCON1_WAIT_ABORT_AND_RETRY 0x03000000 -+/** Reserved */ -+#define BUSWCON1_LOCKCS 0x00800000 -+/** Reversed polarity at wait */ -+#define BUSWCON1_WAITINV 0x00400000 -+/* Low active. -+#define BUSWCON1_WAITINV_ACTLOW 0x00000000 */ -+/** High active */ -+#define BUSWCON1_WAITINV_ACTHI 0x00400000 -+/** Early ADV Enable for Synchronous Bursts */ -+#define BUSWCON1_EBSE 0x00200000 -+/* Low active. -+#define BUSWCON1_EBSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON1_EBSE_NOT_DELAYED 0x00200000 -+/** Early Control Signals for Synchronous Bursts */ -+#define BUSWCON1_ECSE 0x00100000 -+/* Low active. -+#define BUSWCON1_ECSE_DELAYED 0x00000000 */ -+/** High active */ -+#define BUSWCON1_ECSE_NOT_DELAYED 0x00100000 -+/** Synchronous Burst Buffer Mode Select */ -+#define BUSWCON1_FBBMSEL 0x00080000 -+/* FIXED_LENGTH -+#define BUSWCON1_FBBMSEL_FIXED_LENGTH 0x00000000 */ -+/** CONTINUOUS */ -+#define BUSWCON1_FBBMSEL_CONTINUOUS 0x00080000 -+/** Burst Length for Synchronous Burst */ -+#define BUSWCON1_FETBLEN_MASK 0x00070000 -+/** field offset */ -+#define BUSWCON1_FETBLEN_OFFSET 16 -+/** Up to 1 data cycle (default after reset). */ -+#define BUSWCON1_FETBLEN_SINGLE 0x00000000 -+/** Up to 2 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST2 0x00010000 -+/** Up to 4 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST4 0x00020000 -+/** Up to 8 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST8 0x00030000 -+/** Up to 16 data cycles. */ -+#define BUSWCON1_FETBLEN_BURST16 0x00040000 -+/** Reserved -+ This field allows to configure how the EBU generates the CLE and ALE signals for a NAND Flash device. The following options are available */ -+#define BUSWCON1_NANDAMAP_MASK 0x0000C000 -+/** field offset */ -+#define BUSWCON1_NANDAMAP_OFFSET 14 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON1_NANDAMAP_NAND_A17_16 0x00000000 -+/** is taken from AMemport[18] and ALE from AMemport[17] and are output on pins A[17:16] on the External Bus (default after reset). */ -+#define BUSWCON1_NANDAMAP_NAND_WAIT_ADV 0x00004000 -+/** CLE is taken from AMemport[18] and ALE from AMemport[17] and are output on pins AD[9:8] and A[9:8] on the External Bus. This mode may only be used with a 8-Bit NAND-Flash device. */ -+#define BUSWCON1_NANDAMAP_NAND_AD9_8 0x00008000 -+/** Reserved for future use. Do not use or unpredictable results may occur. */ -+#define BUSWCON1_NANDAMAP_NAND_RFU 0x0000C000 -+/** AAD-mux Protocol -+ If this bit is set and the device is configured for a multiplexed access protocol in agen then the device is accessed in read mode using the AAD-mux protocol. If a non-multiplexed device type is selected in agen, field aadmux is ignored. */ -+#define BUSWCON1_AADMUX 0x00002000 -+/* Muxed device is write accessed in AD-mux mode. -+#define BUSWCON1_AADMUX_AD_MUX 0x00000000 */ -+/** Muxed device is write accessed in AAD-mux mode. */ -+#define BUSWCON1_AADMUX_AAD_MUX 0x00002000 -+/** Asynchronous Address Phase */ -+#define BUSWCON1_AAP 0x00001000 -+/* Clock is enabled at beginning of access. -+#define BUSWCON1_AAP_EARLY 0x00000000 */ -+/** Clock is enabled after address phase. */ -+#define BUSWCON1_AAP_LATE 0x00001000 -+/** Auxiliary Chip Select Enable -+ Not supported in GPON-EBU, field must be set to 0. */ -+#define BUSWCON1_CSA 0x00000200 -+/* Disable -+#define BUSWCON1_CSA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_CSA_EN 0x00000200 -+/** Flash Non-Array Access Enable -+ Set to logic one to enable workaround when region is accessed with internal address bit 28 set. See Section 3.17.13 on page 90 for details. */ -+#define BUSWCON1_NAA 0x00000100 -+/* Disable -+#define BUSWCON1_NAA_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_NAA_EN 0x00000100 -+/** Module Enable */ -+#define BUSWCON1_ENABLE 0x00000001 -+/* Disable -+#define BUSWCON1_ENABLE_DIS 0x00000000 */ -+/** Enable */ -+#define BUSWCON1_ENABLE_EN 0x00000001 -+ -+/* Fields of "Bus Write Parameters Register1" */ -+/** Address Cycles -+ Number of cycles for address phase. */ -+#define BUSWP1_ADDRC_MASK 0xF0000000 -+/** field offset */ -+#define BUSWP1_ADDRC_OFFSET 28 -+/** Address Hold Cycles For Multiplexed Address -+ Number of address hold cycles during multiplexed accesses. */ -+#define BUSWP1_ADHOLC_MASK 0x0F000000 -+/** field offset */ -+#define BUSWP1_ADHOLC_OFFSET 24 -+/** Programmed Command Delay Cycles -+ Number of delay cycles during command delay phase. */ -+#define BUSWP1_CMDDELAY_MASK 0x00F00000 -+/** field offset */ -+#define BUSWP1_CMDDELAY_OFFSET 20 -+/** Extended Data */ -+#define BUSWP1_EXTDATA_MASK 0x000C0000 -+/** field offset */ -+#define BUSWP1_EXTDATA_OFFSET 18 -+/** External device outputs data every BFCLK cycle */ -+#define BUSWP1_EXTDATA_ONE 0x00000000 -+/** External device outputs data every 2nd BFCLK cycles */ -+#define BUSWP1_EXTDATA_TWO 0x00040000 -+/** External device outputs data every 4th BFCLK cycles */ -+#define BUSWP1_EXTDATA_FOUR 0x00080000 -+/** External device outputs data every 8th BFCLK cycles */ -+#define BUSWP1_EXTDATA_EIGHT 0x000C0000 -+/** Frequency of external clock at pin BFCLKO */ -+#define BUSWP1_EXTCLOCK_MASK 0x00030000 -+/** field offset */ -+#define BUSWP1_EXTCLOCK_OFFSET 16 -+/** Equal to ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_ONE 0x00000000 -+/** 1/2 of ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_TWO 0x00010000 -+/** 1/3 of ebu_clk frequency. */ -+#define BUSWP1_EXTCLOCK_ONE_TO_THREE 0x00020000 -+/** 1/4 of ebu_clk frequency (default after reset). */ -+#define BUSWP1_EXTCLOCK_ONE_TO_FOUR 0x00030000 -+/** Data Hold Cycles For write Accesses -+ Number of data hold cycles during write accesses. */ -+#define BUSWP1_DATAC_MASK 0x0000F000 -+/** field offset */ -+#define BUSWP1_DATAC_OFFSET 12 -+/** Programmed Wait States For write Accesses -+ Number of programmed wait states for write accesses. For synchronous accesses, this will always be adjusted so that the phase exits on a rising edge of the external clock. */ -+#define BUSWP1_WAITWDC_MASK 0x00000F80 -+/** field offset */ -+#define BUSWP1_WAITWDC_OFFSET 7 -+/** Recovery Cycles After write Accesses, same CS -+ Number of idle cycles after write accesses when following access is to the same chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP1_RECOVC_MASK 0x00000070 -+/** field offset */ -+#define BUSWP1_RECOVC_OFFSET 4 -+/** Recovery Cycles After write Accesses, other CS -+ Number of idle cycles after write accesses when the following access is to a different chip select. For synchronous accesses, this will always be adjusted so that the phase exits on a rising clock edge. Note that at least one recovery cycle must be programmed in case the region is configured for delayed control signals in field ecse of register EBU_BUSWCON. */ -+#define BUSWP1_DTACS_MASK 0x0000000F -+/** field offset */ -+#define BUSWP1_DTACS_OFFSET 0 -+ -+/* Fields of "Bus Protocol Configuration Extension Register 0" */ -+/** Byte Control Mapping -+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ -+#define BUSCONEXT0_BCMAP_MASK 0x00030000 -+/** field offset */ -+#define BUSCONEXT0_BCMAP_OFFSET 16 -+/** No mirroring of byte enables. */ -+#define BUSCONEXT0_BCMAP_NOBCMAP 0x00000000 -+/** Asynchronous Early Write -+ This bit is obsolete and must be set to 0 or unpredictable results may result. */ -+#define BUSCONEXT0_AEW 0x00008000 -+/** AAD-mux Consecutive Address Cycles -+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ -+#define BUSCONEXT0_ACAC 0x00004000 -+/* ADV is deasserted between high and low address phase. -+#define BUSCONEXT0_ACAC_SEPERATED 0x00000000 */ -+/** ADV is not deasserted between high and low address phase. */ -+#define BUSCONEXT0_ACAC_CONSECUTIVE 0x00004000 -+/** AAD-mux Write Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ -+#define BUSCONEXT0_WAAC_MASK 0x00003800 -+/** field offset */ -+#define BUSCONEXT0_WAAC_OFFSET 11 -+/** AAD-mux Read Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ -+#define BUSCONEXT0_RAAC_MASK 0x00000700 -+/** field offset */ -+#define BUSCONEXT0_RAAC_OFFSET 8 -+/** AAD-mux Paging Enable for CS0 -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT0_PAGE_EN 0x00000080 -+/* Disable -+#define BUSCONEXT0_PAGE_EN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSCONEXT0_PAGE_EN_EN 0x00000080 -+/** AAD-mux Address Extension Bit Generation Mode -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT0_AEBM_MASK 0x00000070 -+/** field offset */ -+#define BUSCONEXT0_AEBM_OFFSET 4 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU0 0x00000000 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_RFU1 0x00000010 -+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ -+#define BUSCONEXT0_AEBM_AMAP_CRE_AND_RFU 0x00000020 -+/** Do not use */ -+#define BUSCONEXT0_AEBM_reserved 0x00000030 -+/** A[15:14] in the high address cycle is set to 00B. */ -+#define BUSCONEXT0_AEBM_DIRECT_00 0x00000040 -+/** A[15:14] in the high address cycle is set to 01B */ -+#define BUSCONEXT0_AEBM_DIRECT_01 0x00000050 -+/** A[15:14] in the high address cycle is set to 10B */ -+#define BUSCONEXT0_AEBM_DIRECT_10 0x00000060 -+/** A[15:14] in the high address cycle is set to 11B. */ -+#define BUSCONEXT0_AEBM_DIRECT_11 0x00000070 -+/** Most Significant Address Bit of External Device -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ -+#define BUSCONEXT0_AMSB_MASK 0x0000000F -+/** field offset */ -+#define BUSCONEXT0_AMSB_OFFSET 0 -+ -+/* Fields of "Bus Protocol Configuration Extension Register 1" */ -+/** Byte Control Mapping -+ Remapping of byte enable signals on address lines is not supported in the GPON-EBU. */ -+#define BUSCONEXT1_BCMAP_MASK 0x00030000 -+/** field offset */ -+#define BUSCONEXT1_BCMAP_OFFSET 16 -+/** No mirroring of byte enables. */ -+#define BUSCONEXT1_BCMAP_NOBCMAP 0x00000000 -+/** Asynchronous Early Write -+ This bit is obsolete and must be set to 0 or unpredictable results may result. */ -+#define BUSCONEXT1_AEW 0x00008000 -+/** AAD-mux Consecutive Address Cycles -+ This bit selects whether ADV gets deasserted between the high and the low address phase of a synchronous AAD-mux access or the two address cycles are consecutive. See Figure 32 for a waveform example that results when acac is set. acac only takes effect if the CS region is configured for synchronous AADmux access (agen = 1 or 3, aadmux = 1) and is ignored otherwise. */ -+#define BUSCONEXT1_ACAC 0x00004000 -+/* ADV is deasserted between high and low address phase. -+#define BUSCONEXT1_ACAC_SEPERATED 0x00000000 */ -+/** ADV is not deasserted between high and low address phase. */ -+#define BUSCONEXT1_ACAC_CONSECUTIVE 0x00004000 -+/** AAD-mux Write Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when writing to the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSWCON, fields agen and aadmux. */ -+#define BUSCONEXT1_WAAC_MASK 0x00003800 -+/** field offset */ -+#define BUSCONEXT1_WAAC_OFFSET 11 -+/** AAD-mux Read Address-to-Address Delay -+ Gives the length of the AA-Phase (in multiples of the ebu_clk cycle) to be used when reading from the CS region. The parameter is only observed if the CS region is configured for use of the AAD-mux protocol in register EBU_BUSRCON, fields agen and aadmux. */ -+#define BUSCONEXT1_RAAC_MASK 0x00000700 -+/** field offset */ -+#define BUSCONEXT1_RAAC_OFFSET 8 -+/** AAD-mux Paging Enable for CS0 -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field selects whether or not to use paging. If paging is enabled, the EBU skips the high address cycle in case the upper address that would be sent are the same as in the most recent access to the device.configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT1_PAGE_EN 0x00000080 -+/* Disable -+#define BUSCONEXT1_PAGE_EN_DIS 0x00000000 */ -+/** Enable */ -+#define BUSCONEXT1_PAGE_EN_EN 0x00000080 -+/** AAD-mux Address Extension Bit Generation Mode -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then this field configures how to set the AD[15:14] in the high address cycle of an access with the following encoding: */ -+#define BUSCONEXT1_AEBM_MASK 0x00000070 -+/** field offset */ -+#define BUSCONEXT1_AEBM_OFFSET 4 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 0 */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU0 0x00000000 -+/** A[15] in the high address cycle is set to AMemport[amsb+17], A[14] is set to 1 */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_RFU1 0x00000010 -+/** A[15] in the high address cycle is set to AMemport[amsb+18], A[14] is set to AMemport[amsb+17] */ -+#define BUSCONEXT1_AEBM_AMAP_CRE_AND_RFU 0x00000020 -+/** Do not use */ -+#define BUSCONEXT1_AEBM_reserved 0x00000030 -+/** A[15:14] in the high address cycle is set to 00B. */ -+#define BUSCONEXT1_AEBM_DIRECT_00 0x00000040 -+/** A[15:14] in the high address cycle is set to 01B */ -+#define BUSCONEXT1_AEBM_DIRECT_01 0x00000050 -+/** A[15:14] in the high address cycle is set to 10B */ -+#define BUSCONEXT1_AEBM_DIRECT_10 0x00000060 -+/** A[15:14] in the high address cycle is set to 11B. */ -+#define BUSCONEXT1_AEBM_DIRECT_11 0x00000070 -+/** Most Significant Address Bit of External Device -+ If the external device is configured for AAD-mux protocol in register EBU_BUSRCON, then for amsb < 14 the EBU always sets A[13:amsb] = 0 in the high address cycle of an access. The value of A[15:14] is defined in field aebm. A value of amsb > 13 therefore has no effect. It is recommended to set amsb that it matches the addressable range of the external device according to the following formula: amsb = n - 16 for a device with 2n addressable words. */ -+#define BUSCONEXT1_AMSB_MASK 0x0000000F -+/** field offset */ -+#define BUSCONEXT1_AMSB_OFFSET 0 -+ -+/* Fields of "Serial Flash Configuration Register" */ -+/** Direct Access Device Port Width -+ DA_PORTW Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode rd_opc. Depending on thedevice type and/or command, the number of used signal lines might differbetween command, address, and data phase of the transaction. */ -+#define SFCON_DA_PORTW_MASK 0xE0000000 -+/** field offset */ -+#define SFCON_DA_PORTW_OFFSET 29 -+/** One signal line used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_1 0x00000000 -+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and two signal lines used in the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_2 0x20000000 -+/** One signal used in the COMMAND phase of the transaction and two signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_2_2 0x40000000 -+/** Two signal lines used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_2_2_2 0x60000000 -+/** One signal line used in the COMMAND and ADDRESS phase of the transaction and four signal lines used in the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_1_4 0x80000000 -+/** One signal used in the COMMAND phase of the transaction and four signal lines used in the ADDRESS/DUMMY phase and the DATA phase. */ -+#define SFCON_DA_PORTW_WIDTH_1_4_4 0xA0000000 -+/** Four signal lines used in all phases of the transaction. */ -+#define SFCON_DA_PORTW_WIDTH_4_4_4 0xC0000000 -+/** for future use. */ -+#define SFCON_DA_PORTW_WIDTH_reserved 0xE0000000 -+/** Read Abort Enable -+ If set, a read access from the external device can be aborted via signal sf_rd_abort_i. See Section 3.18.2.9 for details. */ -+#define SFCON_RD_ABORT_EN 0x10000000 -+/** Device Size -+ Defines the number of significant address bits for the Serial Flash device(s). All address bits above the MSB are forced to 0. The configuration in this field also defines for the address auto-increment feature when to wrap around from the upper most address to 0. */ -+#define SFCON_DEV_SIZE_MASK 0x0F000000 -+/** field offset */ -+#define SFCON_DEV_SIZE_OFFSET 24 -+/** 16 MBit device */ -+#define SFCON_DEV_SIZE_A20_0 0x00000000 -+/** 32 MBit device */ -+#define SFCON_DEV_SIZE_A21_0 0x01000000 -+/** 64 MBit device */ -+#define SFCON_DEV_SIZE_A22_0 0x02000000 -+/** 128 MBit device */ -+#define SFCON_DEV_SIZE_A23_0 0x03000000 -+/** 256 MBit device */ -+#define SFCON_DEV_SIZE_A24_0 0x04000000 -+/** 512 MBit device */ -+#define SFCON_DEV_SIZE_A25_0 0x05000000 -+/** 1 GBit device */ -+#define SFCON_DEV_SIZE_A26_0 0x06000000 -+/** 2 GBit device */ -+#define SFCON_DEV_SIZE_A27_0 0x07000000 -+/** 4 GBit device */ -+#define SFCON_DEV_SIZE_A28_0 0x08000000 -+/** 8 GBit device */ -+#define SFCON_DEV_SIZE_A29_0 0x09000000 -+/** 16 GBit device */ -+#define SFCON_DEV_SIZE_A30_0 0x0A000000 -+/** 32 GBit device */ -+#define SFCON_DEV_SIZE_A31_0 0x0B000000 -+/** Device Page Size -+ Defines the page size employed by all connected Serial Flash devices. The device page size is used to determine the address wrap-around for the write address auto-increment feature. */ -+#define SFCON_DPS_MASK 0x00C00000 -+/** field offset */ -+#define SFCON_DPS_OFFSET 22 -+/** Device page size is 256 Bytes */ -+#define SFCON_DPS_DPS_256 0x00000000 -+/** Device page size is 512 Bytes */ -+#define SFCON_DPS_DPS_512 0x00400000 -+/** Page Buffer Size -+ Defines the size of the EBU's page buffer used in Buffered Access. Page buffer size configured here must be less than or equal to the maximum page buffer size which is a built option of the EBU (256 Bytes for GPON). */ -+#define SFCON_PB_SIZE_MASK 0x00300000 -+/** field offset */ -+#define SFCON_PB_SIZE_OFFSET 20 -+/** No read buffer is available/used. */ -+#define SFCON_PB_SIZE_NONE 0x00000000 -+/** 128 Bytes */ -+#define SFCON_PB_SIZE_SIZE_128 0x00100000 -+/** 256 Bytes */ -+#define SFCON_PB_SIZE_SIZE_256 0x00200000 -+/** Bidirectional Data Bus -+ Defines whether the Serial Flash uses a unidirectional or a bidirectional data bus. */ -+#define SFCON_BIDIR 0x00080000 -+/* The Serial Flash interface uses a pair of two unidirectional busses (one for write, one for read) -+#define SFCON_BIDIR_UNIDIRECTIONAL 0x00000000 */ -+/** The Serial Flash interface uses a bidirectional data bus. */ -+#define SFCON_BIDIR_BIDIRECTIONAL 0x00080000 -+/** No Busy Error termination -+ By default, the EBU error-terminates all direct access to a Serial Flash while EBU_SFSTAT.busy is set. By setting NO_BUSY_ERR, the EBU can be configured to permit direct accesses to proceed to the Serial Flash, e.g. for devices that support a read-while-write functionality. */ -+#define SFCON_NO_BUSY_ERR 0x00040000 -+/** End-of-Busy Detection Mode -+ Defines how the EBU detects the end of a busy phase in the Serial Flash device. The current version of the EBU requires the software to explicitly poll the device's status register and then inform the EBU on the end of the busy status by clearing the corresponding bit in register EBU_SF_STAT. */ -+#define SFCON_EOBDM_MASK 0x00030000 -+/** field offset */ -+#define SFCON_EOBDM_OFFSET 16 -+/** No read buffer is available/used. */ -+#define SFCON_EOBDM_SOFTWARE 0x00000000 -+/** Poll device status register (not supported yet) */ -+#define SFCON_EOBDM_POLL_SR 0x00010000 -+/** Poll devices busy/ready pin fed into EBU via WAIT pin (not supported yet). */ -+#define SFCON_EOBDM_POLL_RDY 0x00020000 -+/** Same as POLL_RDY, but CS must be asserted to have the device output its busy/ready status (not supported yet). */ -+#define SFCON_EOBDM_POLL_RDY_WITH_CS 0x00030000 -+/** Direct Access Keep Chip Select -+ Defines whether the Serial Flash remains selected after a direct access transaction has been finished. */ -+#define SFCON_DA_KEEP_CS 0x00008000 -+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCON_DA_KEEP_CS_DESELECT 0x00000000 */ -+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ -+#define SFCON_DA_KEEP_CS_KEEP_SELECTED 0x00008000 -+/** Early Read Abort Enable -+ When aborting a Serial Flash Read is enabled in bit EBU_SFCON.rd_abort_en, bit early_abort selects at what point in the protocol an external access might be aborted. Datasheets of many Serial Flash devices are not explicit on what happens (and whether it is allowed) when a read access is cut-short by deselecting the device during the CMD, ADDR or DUMMY phase of the protocol. */ -+#define SFCON_EARLY_ABORT 0x00004000 -+/* DISABLE Early abortion is disabled (default after reset). Once the EBU has started the access on the External Bus (first bit time slot), the EBU continues the external transfer until the first data byte has been received. After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCON_EARLY_ABORT_DISABLE 0x00000000 */ -+/** Early abortion is not yet supported in the current version of the EBU. Do not use. The feature is a late improvement to the EBU and could not be verified completely before the final release. After proven to work, it should be made officially available to reduce access latency after aborted Serial Flash reads. Setting early_abort to ENABLE alters the read abort handling in the following way: Once the EBU has started the access on the External Bus, the transfer is cut-short after transferring the CMD byte, the three address bytes, any DUMMY bits or at the end of the next data byte - whatever comes first. */ -+#define SFCON_EARLY_ABORT_ENABLE 0x00004000 -+/** Direct Access Address Length -+ Defines the number of address bytes to be sent (MSB first) to the device with a direct read access transaction. Other values than listed below are not supported and have unpredictable results. */ -+#define SFCON_DA_ALEN_MASK 0x00003000 -+/** field offset */ -+#define SFCON_DA_ALEN_OFFSET 12 -+/** 3 address bytes (bits 23:0 of the internal address) */ -+#define SFCON_DA_ALEN_THREE 0x00000000 -+/** Read Access Dummy Bytes -+ This field defines the number of dummy bytes to send between the last address byte before the EBU starts capturing read data from the bus for a direct read access. The number of dummy bytes depends on the data access command being used (see field), the clock frequency and the type of device being used. */ -+#define SFCON_RD_DUMLEN_MASK 0x00000F00 -+/** field offset */ -+#define SFCON_RD_DUMLEN_OFFSET 8 -+/** Direct Read Access Command Opcode -+ This byte defines the command opcode to send when performing a data read from the Serial Flash in Direct Access Mode. Any value can be set (the EBU does not interpret the value, but directly uses the contents of this register field in the command phase of the transaction). Common opcodes to be used and understood by most devices are READ (03H) and FAST_READ (0BH), but some devices might provide additional opcodes, e.g. to support higher clock frequencies requiring additional dummy bytes or to define a wider interface bus. */ -+#define SFCON_RD_OPC_MASK 0x000000FF -+/** field offset */ -+#define SFCON_RD_OPC_OFFSET 0 -+/** READ */ -+#define SFCON_RD_OPC_READ 0x00000003 -+/** FAST_READ */ -+#define SFCON_RD_OPC_FAST_READ 0x0000000B -+ -+/* Fields of "Serial Flash Timing Register" */ -+/** CS Idle time -+ This field defines the minimum time the device's Chip Select has to be deasserted in between accesses. Most devices require a minimum deselect time between 50 and 100 ns. See Table 43 for the encoding used in this field. */ -+#define SFTIME_CS_IDLE_MASK 0xF0000000 -+/** field offset */ -+#define SFTIME_CS_IDLE_OFFSET 28 -+/** 1 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_0 0x00000000 -+/** 2 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_1 0x10000000 -+/** 3 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_2 0x20000000 -+/** 4 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_3 0x30000000 -+/** 6 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_4 0x40000000 -+/** 8 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_5 0x50000000 -+/** 10 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_6 0x60000000 -+/** 12 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_7 0x70000000 -+/** 14 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_8 0x80000000 -+/** 16 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_9 0x90000000 -+/** 20 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_10 0xA0000000 -+/** 24 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_11 0xB0000000 -+/** 32 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_12 0xC0000000 -+/** 40 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_13 0xD0000000 -+/** 48 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_14 0xE0000000 -+/** 64 EBU clock cycles */ -+#define SFTIME_CS_IDLE_CLKC_15 0xF0000000 -+/** CS Hold time -+ This field defines (in multiples of the EBU internal clock's period) the minimum time the device's Chip Select must remain asserted after transfer of the last bit of a write transaction. This CS hold time does not apply to read accesses */ -+#define SFTIME_CS_HOLD_MASK 0x0C000000 -+/** field offset */ -+#define SFTIME_CS_HOLD_OFFSET 26 -+/** CS Setup time -+ This field defines (in multiples of the EBU internal clock's period) when to assert the device's Chip Select before the first SCK clock period for transferring the command is started on the External Bus */ -+#define SFTIME_CS_SETUP_MASK 0x03000000 -+/** field offset */ -+#define SFTIME_CS_SETUP_OFFSET 24 -+/** Write-to-Read Pause -+ This field defines the length of the optional pause when switching from write to read direction in the transaction. During this pause, SCK is held stable. */ -+#define SFTIME_WR2RD_PAUSE_MASK 0x00300000 -+/** field offset */ -+#define SFTIME_WR2RD_PAUSE_OFFSET 20 -+/** Read Data Position -+ This field defines when to capture valid read data bit(s) (in multiples of half of the EBU internal clock's period) relative to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. RD_POS must be less than or equal to EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. */ -+#define SFTIME_RD_POS_MASK 0x000F0000 -+/** field offset */ -+#define SFTIME_RD_POS_OFFSET 16 -+/** SCK Fall-edge Position -+ This field defines the positioning of the SCK fall edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKF_POS must be less than or equal to SCK_PER (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKF_POS defines the positioning of the falling instead of the rising edge of SCK. In the current version of the EBU, SCKF_POS must be set 0 or unpredictable results may occur. */ -+#define SFTIME_SCKF_POS_MASK 0x0000F000 -+/** field offset */ -+#define SFTIME_SCKF_POS_OFFSET 12 -+/** SCK Rise-edge Position -+ This field defines the positioning of the SCK rise edge (in multiples of half of the EBU internal clock's period) with respect to the beginning of the SCK clock's period defined in EBU_SFTIME.sck_per. SCKR_POS must be less than EBU_SFTIME.sck_per (not checked in hardware) or unpredictable results may occur. If EBU_SFTIME.sck_inv is set, SCKR_POS defines the positioning of the falling instead of the rising edge of SCK. */ -+#define SFTIME_SCKR_POS_MASK 0x00000F00 -+/** field offset */ -+#define SFTIME_SCKR_POS_OFFSET 8 -+/** SCK Feedback Clock Inversion -+ If set, read data gets captured with the falling instead of the rising edge of SCK if clock feedback is enabled in EBU_SFTIME.sck_fdbk_en. */ -+#define SFTIME_SCK_FDBK_INV 0x00000040 -+/** SCK Clock Feedback -+ If set, read data is captured using the external SCK clock feedback into the chip instead of the EBU's internal clock. Using the feedback clock compensate for the high delay over the pads and its use is required at higher frequencies. A penalty for synchronizing the read data from the SCK into the ebu_clk domain applies to the read access latency. */ -+#define SFTIME_SCK_FDBK_EN 0x00000020 -+/** Inverted SCK -+ If set, the clock to the Serial Flash devices is inverted. This also results in SCK high while a Serial Flash remains selected between transactions (keep_cs feature). In the current version of the EBU, clock inversion is not supported. SCK_INV must be set to 0 or unpredictable results may occur. */ -+#define SFTIME_SCK_INV 0x00000010 -+/** SCK Period -+ This field defines the period of the SCK clock in multiples of half of the EBU clock period. The EBU supports values between 2 and 14, corresponding to a frequency ratio range from 1:1. to 1:7 between SCK and the internal clock. Other values are prohibited and result in unpredictable behaviour. In the current version of the EBU, odd values for SCK_PER are not supported. */ -+#define SFTIME_SCK_PER_MASK 0x0000000F -+/** field offset */ -+#define SFTIME_SCK_PER_OFFSET 0 -+ -+/* Fields of "Serial Flash Status Register" */ -+/** Command Overwrite Error -+ This bit is set on an attempt to start an indirect access while a previous indirect access has not finished. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ -+#define SFSTAT_CMD_OVWRT_ERR 0x40000000 -+/** Command Error -+ This bit is set when the EBU discards an indirect or direct access to/from a Serial Flash. The bit remains unaltered when the software writes a '0' and is toggled when a '1' is written. This toggle-by-write-1 behavior allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit to clear after it has been set by the Serial Flash protocol engine. */ -+#define SFSTAT_CMD_ERR 0x20000000 -+/** Access Command Pending -+ If set, indicates that access from/to a Serial Flash device has not finished yet. */ -+#define SFSTAT_CMD_PEND 0x00400000 -+/** External Device Selected -+ If set, indicates that the Chip Select of a Serial Flash device is currently active on the External Bus. */ -+#define SFSTAT_SELECTED 0x00200000 -+/** Protocol Engine Active -+ If set, indicates that the EBU's Serial Flash protocol engine is active. */ -+#define SFSTAT_ACTIVE 0x00100000 -+/** Page Buffer Invalidate -+ When writing a one to this bit, bits PB_VALID and PB_UPDATE are both cleared, thereby invalidating the page buffer for access to/from the Serial Flash device. After invalidating the buffer, PB_INVALID is automatically cleared so that it always reads as 0. */ -+#define SFSTAT_PB_INVALID 0x00010000 -+/** Page Buffer Update -+ This bit is set when data in the page buffer gets modified. It is cleared when new data gets loaded to the page buffer, when it is written back to the device (WRITE_PAGE command) or when PB_VALID gets cleared. */ -+#define SFSTAT_PB_UPDATE 0x00002000 -+/** Page Buffer Valid -+ This bit is set after the last data byte of a LOAD_PAGE command has been stored in the page buffer or when the page buffer is explicitely validated via a VALIDATE_PAGE special command. It remains set until the page buffer gets invalidated by writing a 1 to PB_INVALID or any of the LOAD_PAGE special commands. While PB_VALID is set, all accesses to the buffered address range are diverted to the page buffer with no access being performed on the External Bus. */ -+#define SFSTAT_PB_VALID 0x00001000 -+/** Page Buffer Busy -+ The bit is set when the EBU starts executing a LOAD_PAGE or a WRITE_PAGE command and cleared when the last byte of the requested page has been transferred from/to the external device. The inverted value of PB_BUSY is output on the EBU interface and may trigger a system interrupt. */ -+#define SFSTAT_PB_BUSY 0x00000100 -+/** Device Busy -+ This bit is set by the Serial Flash protocol engine when an indirect access is performed via register EBU_SFCMD with SET_BUSY being set. While busy is set, access to the Serial Flash is very limited and all transactions are error-terminated except when explicitly marked to ignore the busy status. If the EBU is configured in EBU_SFCON.EOBDM to automatically poll the busy status of the device, busy is cleared as soon as the device is found to be idle again. On a software write, busy remains unaltered when written with a '0' and is toggled when written with a '1', respectively.This toggle-by-write-1 behaviour allows to also set the bit for testing purposes. In normal operation, the software is supposed to only write a '1' to this bit after it got set by the Serial Flash protocol engine and no automatic busy detection is configured in EBU_SFCON.EOBDM Then the software has to clear busy when it finds the device to be no longer busy by either polling the device's status register via the EBU or by waiting for the maximum busy time of the operation started in the device. */ -+#define SFSTAT_BUSY 0x00000001 -+ -+/* Fields of "Serial Flash Command Register" */ -+/** Command Type -+ This field is a qualifier of the command opcode in EBU_SFCMD.opc. Two types */ -+#define SFCMD_CMDTYPE 0x80000000 -+/* The opcode in EBU_SFCMD.opc is directly used in the command phase of a single transaction to the Serial Flash device. -+#define SFCMD_CMDTYPE_ACCESS_CMD 0x00000000 */ -+/** The opcode in EBU_SFCMD.opc is used to start a special command in the Serial Flash Controller which might include any number of external transactions to/from the Serial Flash device. */ -+#define SFCMD_CMDTYPE_SPECIAL_CMD 0x80000000 -+/** Device Port Width -+ Defines the number of signal lines to be used with direct read access from a Serial Flash as defined for the command with opcode opc. The encoding of this field is the same as forDA_PORTW. */ -+#define SFCMD_PORTW_MASK 0x70000000 -+/** field offset */ -+#define SFCMD_PORTW_OFFSET 28 -+/** Bidirectional Signal Lines -+ If set selects bidirectional signal lines to be used for the data transfer. */ -+#define SFCMD_BIDIR 0x08000000 -+/** Chip Select -+ This field selects which of the EBU's Chip Selects to activated for the command that is written to EBU_SFCMD.opc. A value between 0 and 3 selects one of the EBU's main CSs while 4 to 7 chooses one of the Auxiliary Chip Selects CSA[3:0], respectively. */ -+#define SFCMD_CS_MASK 0x07000000 -+/** field offset */ -+#define SFCMD_CS_OFFSET 24 -+/** Disable Auto Address Increment -+ By default, the address in register EBU_SFADDR is automatically incremented with each data byte being transferred. By setting this bit, the auto-increment can be disabled. */ -+#define SFCMD_DIS_AAI 0x00800000 -+/** Address Length -+ Defines the number of address bytes from register EBU_SFADDR to sent in the address phase of the transaction to/from the Serial Flash. Note: Address bytes are also sent when the command has no data. */ -+#define SFCMD_ALEN_MASK 0x00700000 -+/** field offset */ -+#define SFCMD_ALEN_OFFSET 20 -+/** Dummy Phase Length -+ Defines the number of dummy bytes to send to the device between the command/address phase and the data phase of a transaction. Note:Dummy bytes are also sent when the command has no address and/or no data. */ -+#define SFCMD_DUMLEN_MASK 0x000F0000 -+/** field offset */ -+#define SFCMD_DUMLEN_OFFSET 16 -+/** Keep Chip Select -+ Defines whether the Serial Flash remains selected after the indirect access transaction has been finished. */ -+#define SFCMD_KEEP_CS 0x00008000 -+/* After a direct read access, the Serial Flash device is always deselected (CS deasserted). Follow-up read accesses always require sending command opcode and address. -+#define SFCMD_KEEP_CS_DESELECT 0x00000000 */ -+/** Chip Select of device is kept active after direct read access so that device is ready for follow-up read of next sequential byte without the need to send command and address. If the next command is to another Chip Select, is a different command or accesses a different address, the EBU first deactivates the kept Chip Select before it starts the new transaction with sending the command opcode and address. */ -+#define SFCMD_KEEP_CS_KEEP_SELECTED 0x00008000 -+/** Set Busy Flag -+ If set, starting the command sets EBU_SFSTAT.busy. */ -+#define SFCMD_SET_BUSY 0x00004000 -+/** Ignore Busy -+ By default, the EBU error terminates all attempts to access a Serial Flash while EBU_SFSTAT.busy is set. Setting this bit overrules this error termination and permits the command written to EBU_SFCMD.opc to proceed to the External Bus. Normally, this bit is only set to execute a Read Status Register command to the Serial Flash, but may also be used for any other type of access the device is able to handle while it is busy. */ -+#define SFCMD_IGNORE_BUSY 0x00002000 -+/** Skip Opcode -+ If this bit is set, the opcode in field OPC is not sent to the External Bus, but the external transaction starts with sending the first address byte (if ALEN 0), the first dummy byte (if alen = 0 and DUMLEN 0), or directly with transferring the data bytes (if ALEN = DUMLEN = 0 and DLEN 0). Limiting the external transfer to just the data phase - together with the keep_cs feature - allow to transfer any number of data bytes for a device command sent via EBU_SFCMD by keeping the device selected between accesses and chaining multiple indirect access commands each transferring up to 4 data bytes from/to register EBU_SFDATA. */ -+#define SFCMD_SKIP_OPC 0x00001000 -+/** Data Length -+ This field defines the number of data bytes to transfer in the data phase of the command. For a read command, the data bytes are stored in register EBU_SFDATA, for a write transfer they are taken from that register. As the data register can hold at most 4 bytes, DLEN is restricted to the range [0..4]. */ -+#define SFCMD_DLEN_MASK 0x00000E00 -+/** field offset */ -+#define SFCMD_DLEN_OFFSET 9 -+/** Direction -+ Defines the direction of the data transfer (if any) in the data phase of the transaction to/from the serial bus. */ -+#define SFCMD_DIR 0x00000100 -+/* dlen bytes of data are read from the Serial Flash during the data phase of the transaction and stored in register EBU_SFDATA. -+#define SFCMD_DIR_READ 0x00000000 */ -+/** dlen bytes of data are read from register EBU_SFDATA and written to the Serial Flash during the data phase of the transactione */ -+#define SFCMD_DIR_WRITE 0x00000100 -+/** Command Opcode -+ A write access to this field starts an Indirect Access command in the EBU's Serial Flash controller. Two types of commands are supported (selected in EBU_SFCMD.cmdtype) and determine how the EBU interprets the opcode:- - For a ACCESS_CMD, a single transaction is executed to/from the Serial Flash device and the OPC is sent to the device in the command phase of the protocol. The number of address, dummy and data bytes to transfer with the command are given in fields ALEN, DUMLEN, and DLEN of register EBU_SFCMD, respectively. - For a SPECIAL_CMD, the EBU starts a complex operation that usually involves multiple transactions to/from the Serial Flash device. See Section 3.18.2.5 for an overview of the complex commands currently supported. */ -+#define SFCMD_OPC_MASK 0x000000FF -+/** field offset */ -+#define SFCMD_OPC_OFFSET 0 -+ -+/* Fields of "Serial Flash Address Register" */ -+/** Address -+ Before writing to register EBU_SFCMD to start a command that requires the transfer of an address, the address to use must be stored in this register. If not disabled in EBU_SFCMD.dis_aai, ADDR is incremented automatically with each data byte transferred between the EBU and the Serial Flash for an indirect access. Note:Register EBU_SFADDR is only used for access in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ -+#define SFADDR_ADDR_MASK 0xFFFFFFFF -+/** field offset */ -+#define SFADDR_ADDR_OFFSET 0 -+ -+/* Fields of "Serial Flash Data Register" */ -+/** Data Bytes -+ Before writing to register EBU_SFCMD to start a command that requires the transfer of data from the EBU to the Serial Flash device (write access), the data to send must be stored in this register. The data bytes have to be right-aligned in this register, that is, the last byte to send must be placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc.. Similarly, for a read access with data being transferred from the Serial Flash to the EBU, this register collects the read data received from the device. The read data is right-aligned, that is, the last byte received gets placed in bits DATA[7:0], the second-to-last byte in bits DATA[15:8], etc... The number of data bytes to be transferred between EBU and the Serial Flash is defined in EBU_SFCMD.DLEN. Note:Register EBU_SFDATA is only used for accesses in Indirect Access Mode and is ignored/remains unaltered for all accesses in Direct Access Mode. */ -+#define SFDATA_DATA_MASK 0xFFFFFFFF -+/** field offset */ -+#define SFDATA_DATA_OFFSET 0 -+ -+/* Fields of "Serial Flash I/O Control Register" */ -+/** Start of Write Delay -+ By default, the EBU starts driving to AD[3:0] two EBU clock cycles before asserting the CS for an external Serial Flash access. For write accesses, this delay can be increased via field SOWD. */ -+#define SFIO_SOWD_MASK 0x0000F000 -+/** field offset */ -+#define SFIO_SOWD_OFFSET 12 -+/** End of Write Delay -+ This field defines the time (in number of EBU clock cycles) for which the EBU keeps driving the External Bus AD[3:0] after deassertion of the device's CS. */ -+#define SFIO_EOWD_MASK 0x00000F00 -+/** field offset */ -+#define SFIO_EOWD_OFFSET 8 -+/** Data Output -+ The EBU always controls the AD[3:0] pins while a CS for a Serial Flash device is asserted. Field UNUSED_WD defines the values being driven to these pins while the Serial Flash controller is not writing data to or is reading data from the device via the respective line. See Section 3.18.6 for details. */ -+#define SFIO_UNUSED_WD_MASK 0x0000000F -+/** field offset */ -+#define SFIO_UNUSED_WD_OFFSET 0 -+ -+/*! @} */ /* EBU_REGISTER */ -+ -+#endif /* _ebu_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h -new file mode 100644 -index 0000000..d575082 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/gpon_reg_base.h -@@ -0,0 +1,376 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _gpon_reg_base_h -+#define _gpon_reg_base_h -+ -+/** \addtogroup GPON_BASE -+ @{ -+*/ -+ -+#ifndef KSEG1 -+#define KSEG1 0xA0000000 -+#endif -+ -+/** address range for ebu -+ 0x18000000--0x180000FF */ -+#define GPON_EBU_BASE (KSEG1 | 0x18000000) -+#define GPON_EBU_END (KSEG1 | 0x180000FF) -+#define GPON_EBU_SIZE 0x00000100 -+/** address range for gpearb -+ 0x1D400100--0x1D4001FF */ -+#define GPON_GPEARB_BASE (KSEG1 | 0x1D400100) -+#define GPON_GPEARB_END (KSEG1 | 0x1D4001FF) -+#define GPON_GPEARB_SIZE 0x00000100 -+/** address range for tmu -+ 0x1D404000--0x1D404FFF */ -+#define GPON_TMU_BASE (KSEG1 | 0x1D404000) -+#define GPON_TMU_END (KSEG1 | 0x1D404FFF) -+#define GPON_TMU_SIZE 0x00001000 -+/** address range for iqm -+ 0x1D410000--0x1D41FFFF */ -+#define GPON_IQM_BASE (KSEG1 | 0x1D410000) -+#define GPON_IQM_END (KSEG1 | 0x1D41FFFF) -+#define GPON_IQM_SIZE 0x00010000 -+/** address range for octrlg -+ 0x1D420000--0x1D42FFFF */ -+#define GPON_OCTRLG_BASE (KSEG1 | 0x1D420000) -+#define GPON_OCTRLG_END (KSEG1 | 0x1D42FFFF) -+#define GPON_OCTRLG_SIZE 0x00010000 -+/** address range for octrll0 -+ 0x1D440000--0x1D4400FF */ -+#define GPON_OCTRLL0_BASE (KSEG1 | 0x1D440000) -+#define GPON_OCTRLL0_END (KSEG1 | 0x1D4400FF) -+#define GPON_OCTRLL0_SIZE 0x00000100 -+/** address range for octrll1 -+ 0x1D440100--0x1D4401FF */ -+#define GPON_OCTRLL1_BASE (KSEG1 | 0x1D440100) -+#define GPON_OCTRLL1_END (KSEG1 | 0x1D4401FF) -+#define GPON_OCTRLL1_SIZE 0x00000100 -+/** address range for octrll2 -+ 0x1D440200--0x1D4402FF */ -+#define GPON_OCTRLL2_BASE (KSEG1 | 0x1D440200) -+#define GPON_OCTRLL2_END (KSEG1 | 0x1D4402FF) -+#define GPON_OCTRLL2_SIZE 0x00000100 -+/** address range for octrll3 -+ 0x1D440300--0x1D4403FF */ -+#define GPON_OCTRLL3_BASE (KSEG1 | 0x1D440300) -+#define GPON_OCTRLL3_END (KSEG1 | 0x1D4403FF) -+#define GPON_OCTRLL3_SIZE 0x00000100 -+/** address range for octrlc -+ 0x1D441000--0x1D4410FF */ -+#define GPON_OCTRLC_BASE (KSEG1 | 0x1D441000) -+#define GPON_OCTRLC_END (KSEG1 | 0x1D4410FF) -+#define GPON_OCTRLC_SIZE 0x00000100 -+/** address range for ictrlg -+ 0x1D450000--0x1D45FFFF */ -+#define GPON_ICTRLG_BASE (KSEG1 | 0x1D450000) -+#define GPON_ICTRLG_END (KSEG1 | 0x1D45FFFF) -+#define GPON_ICTRLG_SIZE 0x00010000 -+/** address range for ictrll0 -+ 0x1D460000--0x1D4601FF */ -+#define GPON_ICTRLL0_BASE (KSEG1 | 0x1D460000) -+#define GPON_ICTRLL0_END (KSEG1 | 0x1D4601FF) -+#define GPON_ICTRLL0_SIZE 0x00000200 -+/** address range for ictrll1 -+ 0x1D460200--0x1D4603FF */ -+#define GPON_ICTRLL1_BASE (KSEG1 | 0x1D460200) -+#define GPON_ICTRLL1_END (KSEG1 | 0x1D4603FF) -+#define GPON_ICTRLL1_SIZE 0x00000200 -+/** address range for ictrll2 -+ 0x1D460400--0x1D4605FF */ -+#define GPON_ICTRLL2_BASE (KSEG1 | 0x1D460400) -+#define GPON_ICTRLL2_END (KSEG1 | 0x1D4605FF) -+#define GPON_ICTRLL2_SIZE 0x00000200 -+/** address range for ictrll3 -+ 0x1D460600--0x1D4607FF */ -+#define GPON_ICTRLL3_BASE (KSEG1 | 0x1D460600) -+#define GPON_ICTRLL3_END (KSEG1 | 0x1D4607FF) -+#define GPON_ICTRLL3_SIZE 0x00000200 -+/** address range for ictrlc0 -+ 0x1D461000--0x1D4610FF */ -+#define GPON_ICTRLC0_BASE (KSEG1 | 0x1D461000) -+#define GPON_ICTRLC0_END (KSEG1 | 0x1D4610FF) -+#define GPON_ICTRLC0_SIZE 0x00000100 -+/** address range for ictrlc1 -+ 0x1D461100--0x1D4611FF */ -+#define GPON_ICTRLC1_BASE (KSEG1 | 0x1D461100) -+#define GPON_ICTRLC1_END (KSEG1 | 0x1D4611FF) -+#define GPON_ICTRLC1_SIZE 0x00000100 -+/** address range for fsqm -+ 0x1D500000--0x1D5FFFFF */ -+#define GPON_FSQM_BASE (KSEG1 | 0x1D500000) -+#define GPON_FSQM_END (KSEG1 | 0x1D5FFFFF) -+#define GPON_FSQM_SIZE 0x00100000 -+/** address range for pctrl -+ 0x1D600000--0x1D6001FF */ -+#define GPON_PCTRL_BASE (KSEG1 | 0x1D600000) -+#define GPON_PCTRL_END (KSEG1 | 0x1D6001FF) -+#define GPON_PCTRL_SIZE 0x00000200 -+/** address range for link0 -+ 0x1D600200--0x1D6002FF */ -+#define GPON_LINK0_BASE (KSEG1 | 0x1D600200) -+#define GPON_LINK0_END (KSEG1 | 0x1D6002FF) -+#define GPON_LINK0_SIZE 0x00000100 -+/** address range for link1 -+ 0x1D600300--0x1D6003FF */ -+#define GPON_LINK1_BASE (KSEG1 | 0x1D600300) -+#define GPON_LINK1_END (KSEG1 | 0x1D6003FF) -+#define GPON_LINK1_SIZE 0x00000100 -+/** address range for link2 -+ 0x1D600400--0x1D6004FF */ -+#define GPON_LINK2_BASE (KSEG1 | 0x1D600400) -+#define GPON_LINK2_END (KSEG1 | 0x1D6004FF) -+#define GPON_LINK2_SIZE 0x00000100 -+/** address range for disp -+ 0x1D600500--0x1D6005FF */ -+#define GPON_DISP_BASE (KSEG1 | 0x1D600500) -+#define GPON_DISP_END (KSEG1 | 0x1D6005FF) -+#define GPON_DISP_SIZE 0x00000100 -+/** address range for merge -+ 0x1D600600--0x1D6006FF */ -+#define GPON_MERGE_BASE (KSEG1 | 0x1D600600) -+#define GPON_MERGE_END (KSEG1 | 0x1D6006FF) -+#define GPON_MERGE_SIZE 0x00000100 -+/** address range for tbm -+ 0x1D600700--0x1D6007FF */ -+#define GPON_TBM_BASE (KSEG1 | 0x1D600700) -+#define GPON_TBM_END (KSEG1 | 0x1D6007FF) -+#define GPON_TBM_SIZE 0x00000100 -+/** address range for pe0 -+ 0x1D610000--0x1D61FFFF */ -+#define GPON_PE0_BASE (KSEG1 | 0x1D610000) -+#define GPON_PE0_END (KSEG1 | 0x1D61FFFF) -+#define GPON_PE0_SIZE 0x00010000 -+/** address range for pe1 -+ 0x1D620000--0x1D62FFFF */ -+#define GPON_PE1_BASE (KSEG1 | 0x1D620000) -+#define GPON_PE1_END (KSEG1 | 0x1D62FFFF) -+#define GPON_PE1_SIZE 0x00010000 -+/** address range for pe2 -+ 0x1D630000--0x1D63FFFF */ -+#define GPON_PE2_BASE (KSEG1 | 0x1D630000) -+#define GPON_PE2_END (KSEG1 | 0x1D63FFFF) -+#define GPON_PE2_SIZE 0x00010000 -+/** address range for pe3 -+ 0x1D640000--0x1D64FFFF */ -+#define GPON_PE3_BASE (KSEG1 | 0x1D640000) -+#define GPON_PE3_END (KSEG1 | 0x1D64FFFF) -+#define GPON_PE3_SIZE 0x00010000 -+/** address range for pe4 -+ 0x1D650000--0x1D65FFFF */ -+#define GPON_PE4_BASE (KSEG1 | 0x1D650000) -+#define GPON_PE4_END (KSEG1 | 0x1D65FFFF) -+#define GPON_PE4_SIZE 0x00010000 -+/** address range for pe5 -+ 0x1D660000--0x1D66FFFF */ -+#define GPON_PE5_BASE (KSEG1 | 0x1D660000) -+#define GPON_PE5_END (KSEG1 | 0x1D66FFFF) -+#define GPON_PE5_SIZE 0x00010000 -+/** address range for sys_gpe -+ 0x1D700000--0x1D7000FF */ -+#define GPON_SYS_GPE_BASE (KSEG1 | 0x1D700000) -+#define GPON_SYS_GPE_END (KSEG1 | 0x1D7000FF) -+#define GPON_SYS_GPE_SIZE 0x00000100 -+/** address range for eim -+ 0x1D800000--0x1D800FFF */ -+#define GPON_EIM_BASE (KSEG1 | 0x1D800000) -+#define GPON_EIM_END (KSEG1 | 0x1D800FFF) -+#define GPON_EIM_SIZE 0x00001000 -+/** address range for sxgmii -+ 0x1D808800--0x1D8088FF */ -+#define GPON_SXGMII_BASE (KSEG1 | 0x1D808800) -+#define GPON_SXGMII_END (KSEG1 | 0x1D8088FF) -+#define GPON_SXGMII_SIZE 0x00000100 -+/** address range for sgmii -+ 0x1D808C00--0x1D808CFF */ -+#define GPON_SGMII_BASE (KSEG1 | 0x1D808C00) -+#define GPON_SGMII_END (KSEG1 | 0x1D808CFF) -+#define GPON_SGMII_SIZE 0x00000100 -+/** address range for gpio0 -+ 0x1D810000--0x1D81007F */ -+#define GPON_GPIO0_BASE (KSEG1 | 0x1D810000) -+#define GPON_GPIO0_END (KSEG1 | 0x1D81007F) -+#define GPON_GPIO0_SIZE 0x00000080 -+/** address range for gpio2 -+ 0x1D810100--0x1D81017F */ -+#define GPON_GPIO2_BASE (KSEG1 | 0x1D810100) -+#define GPON_GPIO2_END (KSEG1 | 0x1D81017F) -+#define GPON_GPIO2_SIZE 0x00000080 -+/** address range for sys_eth -+ 0x1DB00000--0x1DB000FF */ -+#define GPON_SYS_ETH_BASE (KSEG1 | 0x1DB00000) -+#define GPON_SYS_ETH_END (KSEG1 | 0x1DB000FF) -+#define GPON_SYS_ETH_SIZE 0x00000100 -+/** address range for padctrl0 -+ 0x1DB01000--0x1DB010FF */ -+#define GPON_PADCTRL0_BASE (KSEG1 | 0x1DB01000) -+#define GPON_PADCTRL0_END (KSEG1 | 0x1DB010FF) -+#define GPON_PADCTRL0_SIZE 0x00000100 -+/** address range for padctrl2 -+ 0x1DB02000--0x1DB020FF */ -+#define GPON_PADCTRL2_BASE (KSEG1 | 0x1DB02000) -+#define GPON_PADCTRL2_END (KSEG1 | 0x1DB020FF) -+#define GPON_PADCTRL2_SIZE 0x00000100 -+/** address range for gtc -+ 0x1DC05000--0x1DC052D4 */ -+#define GPON_GTC_BASE (KSEG1 | 0x1DC05000) -+#define GPON_GTC_END (KSEG1 | 0x1DC052D4) -+#define GPON_GTC_SIZE 0x000002D5 -+/** address range for pma -+ 0x1DD00000--0x1DD003FF */ -+#define GPON_PMA_BASE (KSEG1 | 0x1DD00000) -+#define GPON_PMA_END (KSEG1 | 0x1DD003FF) -+#define GPON_PMA_SIZE 0x00000400 -+/** address range for fcsic -+ 0x1DD00600--0x1DD0061F */ -+#define GPON_FCSIC_BASE (KSEG1 | 0x1DD00600) -+#define GPON_FCSIC_END (KSEG1 | 0x1DD0061F) -+#define GPON_FCSIC_SIZE 0x00000020 -+/** address range for pma_int200 -+ 0x1DD00700--0x1DD0070F */ -+#define GPON_PMA_INT200_BASE (KSEG1 | 0x1DD00700) -+#define GPON_PMA_INT200_END (KSEG1 | 0x1DD0070F) -+#define GPON_PMA_INT200_SIZE 0x00000010 -+/** address range for pma_inttx -+ 0x1DD00720--0x1DD0072F */ -+#define GPON_PMA_INTTX_BASE (KSEG1 | 0x1DD00720) -+#define GPON_PMA_INTTX_END (KSEG1 | 0x1DD0072F) -+#define GPON_PMA_INTTX_SIZE 0x00000010 -+/** address range for pma_intrx -+ 0x1DD00740--0x1DD0074F */ -+#define GPON_PMA_INTRX_BASE (KSEG1 | 0x1DD00740) -+#define GPON_PMA_INTRX_END (KSEG1 | 0x1DD0074F) -+#define GPON_PMA_INTRX_SIZE 0x00000010 -+/** address range for gtc_pma -+ 0x1DEFFF00--0x1DEFFFFF */ -+#define GPON_GTC_PMA_BASE (KSEG1 | 0x1DEFFF00) -+#define GPON_GTC_PMA_END (KSEG1 | 0x1DEFFFFF) -+#define GPON_GTC_PMA_SIZE 0x00000100 -+/** address range for sys -+ 0x1DF00000--0x1DF000FF */ -+#define GPON_SYS_BASE (KSEG1 | 0x1DF00000) -+#define GPON_SYS_END (KSEG1 | 0x1DF000FF) -+#define GPON_SYS_SIZE 0x00000100 -+/** address range for asc1 -+ 0x1E100B00--0x1E100BFF */ -+#define GPON_ASC1_BASE (KSEG1 | 0x1E100B00) -+#define GPON_ASC1_END (KSEG1 | 0x1E100BFF) -+#define GPON_ASC1_SIZE 0x00000100 -+/** address range for asc0 -+ 0x1E100C00--0x1E100CFF */ -+#define GPON_ASC0_BASE (KSEG1 | 0x1E100C00) -+#define GPON_ASC0_END (KSEG1 | 0x1E100CFF) -+#define GPON_ASC0_SIZE 0x00000100 -+/** address range for i2c -+ 0x1E200000--0x1E20FFFF */ -+#define GPON_I2C_BASE (KSEG1 | 0x1E200000) -+#define GPON_I2C_END (KSEG1 | 0x1E20FFFF) -+#define GPON_I2C_SIZE 0x00010000 -+/** address range for gpio1 -+ 0x1E800100--0x1E80017F */ -+#define GPON_GPIO1_BASE (KSEG1 | 0x1E800100) -+#define GPON_GPIO1_END (KSEG1 | 0x1E80017F) -+#define GPON_GPIO1_SIZE 0x00000080 -+/** address range for gpio3 -+ 0x1E800200--0x1E80027F */ -+#define GPON_GPIO3_BASE (KSEG1 | 0x1E800200) -+#define GPON_GPIO3_END (KSEG1 | 0x1E80027F) -+#define GPON_GPIO3_SIZE 0x00000080 -+/** address range for gpio4 -+ 0x1E800300--0x1E80037F */ -+#define GPON_GPIO4_BASE (KSEG1 | 0x1E800300) -+#define GPON_GPIO4_END (KSEG1 | 0x1E80037F) -+#define GPON_GPIO4_SIZE 0x00000080 -+/** address range for padctrl1 -+ 0x1E800400--0x1E8004FF */ -+#define GPON_PADCTRL1_BASE (KSEG1 | 0x1E800400) -+#define GPON_PADCTRL1_END (KSEG1 | 0x1E8004FF) -+#define GPON_PADCTRL1_SIZE 0x00000100 -+/** address range for padctrl3 -+ 0x1E800500--0x1E8005FF */ -+#define GPON_PADCTRL3_BASE (KSEG1 | 0x1E800500) -+#define GPON_PADCTRL3_END (KSEG1 | 0x1E8005FF) -+#define GPON_PADCTRL3_SIZE 0x00000100 -+/** address range for padctrl4 -+ 0x1E800600--0x1E8006FF */ -+#define GPON_PADCTRL4_BASE (KSEG1 | 0x1E800600) -+#define GPON_PADCTRL4_END (KSEG1 | 0x1E8006FF) -+#define GPON_PADCTRL4_SIZE 0x00000100 -+/** address range for status -+ 0x1E802000--0x1E80207F */ -+#define GPON_STATUS_BASE (KSEG1 | 0x1E802000) -+#define GPON_STATUS_END (KSEG1 | 0x1E80207F) -+#define GPON_STATUS_SIZE 0x00000080 -+/** address range for dcdc_1v0 -+ 0x1E803000--0x1E8033FF */ -+#define GPON_DCDC_1V0_BASE (KSEG1 | 0x1E803000) -+#define GPON_DCDC_1V0_END (KSEG1 | 0x1E8033FF) -+#define GPON_DCDC_1V0_SIZE 0x00000400 -+/** address range for dcdc_ddr -+ 0x1E804000--0x1E8043FF */ -+#define GPON_DCDC_DDR_BASE (KSEG1 | 0x1E804000) -+#define GPON_DCDC_DDR_END (KSEG1 | 0x1E8043FF) -+#define GPON_DCDC_DDR_SIZE 0x00000400 -+/** address range for dcdc_apd -+ 0x1E805000--0x1E8053FF */ -+#define GPON_DCDC_APD_BASE (KSEG1 | 0x1E805000) -+#define GPON_DCDC_APD_END (KSEG1 | 0x1E8053FF) -+#define GPON_DCDC_APD_SIZE 0x00000400 -+/** address range for sys1 -+ 0x1EF00000--0x1EF000FF */ -+#define GPON_SYS1_BASE (KSEG1 | 0x1EF00000) -+#define GPON_SYS1_END (KSEG1 | 0x1EF000FF) -+#define GPON_SYS1_SIZE 0x00000100 -+/** address range for sbs0ctrl -+ 0x1F080000--0x1F0801FF */ -+#define GPON_SBS0CTRL_BASE (KSEG1 | 0x1F080000) -+#define GPON_SBS0CTRL_END (KSEG1 | 0x1F0801FF) -+#define GPON_SBS0CTRL_SIZE 0x00000200 -+/** address range for sbs0red -+ 0x1F080200--0x1F08027F */ -+#define GPON_SBS0RED_BASE (KSEG1 | 0x1F080200) -+#define GPON_SBS0RED_END (KSEG1 | 0x1F08027F) -+#define GPON_SBS0RED_SIZE 0x00000080 -+/** address range for sbs0ram -+ 0x1F200000--0x1F32FFFF */ -+#define GPON_SBS0RAM_BASE (KSEG1 | 0x1F200000) -+#define GPON_SBS0RAM_END (KSEG1 | 0x1F32FFFF) -+#define GPON_SBS0RAM_SIZE 0x00130000 -+/** address range for ddrdb -+ 0x1F701000--0x1F701FFF */ -+#define GPON_DDRDB_BASE (KSEG1 | 0x1F701000) -+#define GPON_DDRDB_END (KSEG1 | 0x1F701FFF) -+#define GPON_DDRDB_SIZE 0x00001000 -+/** address range for sbiu -+ 0x1F880000--0x1F8800FF */ -+#define GPON_SBIU_BASE (KSEG1 | 0x1F880000) -+#define GPON_SBIU_END (KSEG1 | 0x1F8800FF) -+#define GPON_SBIU_SIZE 0x00000100 -+/** address range for icu0 -+ 0x1F880200--0x1F8802DF */ -+#define GPON_ICU0_BASE (KSEG1 | 0x1F880200) -+#define GPON_ICU0_END (KSEG1 | 0x1F8802DF) -+#define GPON_ICU0_SIZE 0x000000E0 -+/** address range for icu1 -+ 0x1F880300--0x1F8803DF */ -+#define GPON_ICU1_BASE (KSEG1 | 0x1F880300) -+#define GPON_ICU1_END (KSEG1 | 0x1F8803DF) -+#define GPON_ICU1_SIZE 0x000000E0 -+/** address range for wdt -+ 0x1F8803F0--0x1F8803FF */ -+#define GPON_WDT_BASE (KSEG1 | 0x1F8803F0) -+#define GPON_WDT_END (KSEG1 | 0x1F8803FF) -+#define GPON_WDT_SIZE 0x00000010 -+ -+/*! @} */ /* GPON_BASE */ -+ -+#endif /* _gpon_reg_base_h */ -+ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h -new file mode 100644 -index 0000000..5c94618 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/i2c_reg.h -@@ -0,0 +1,830 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _i2c_reg_h -+#define _i2c_reg_h -+ -+/** \addtogroup I2C_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define i2c_r32(reg) reg_r32(&i2c->reg) -+#define i2c_w32(val, reg) reg_w32(val, &i2c->reg) -+#define i2c_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &i2c->reg) -+#define i2c_r32_table(reg, idx) reg_r32_table(i2c->reg, idx) -+#define i2c_w32_table(val, reg, idx) reg_w32_table(val, i2c->reg, idx) -+#define i2c_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, i2c->reg, idx) -+#define i2c_adr_table(reg, idx) adr_table(i2c->reg, idx) -+ -+ -+/** I2C register structure */ -+struct gpon_reg_i2c -+{ -+ /** I2C Kernel Clock Control Register */ -+ unsigned int clc; /* 0x00000000 */ -+ /** Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /** I2C Identification Register */ -+ unsigned int id; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /** I2C RUN Control Register -+ This register enables and disables the I2C peripheral. Before enabling, the I2C has to be configured properly. After enabling no configuration is possible */ -+ unsigned int run_ctrl; /* 0x00000010 */ -+ /** I2C End Data Control Register -+ This register is used to either turn around the data transmission direction or to address another slave without sending a stop condition. Also the software can stop the slave-transmitter by sending a not-accolade when working as master-receiver or even stop data transmission immediately when operating as master-transmitter. The writing to the bits of this control register is only effective when in MASTER RECEIVES BYTES, MASTER TRANSMITS BYTES, MASTER RESTART or SLAVE RECEIVE BYTES state */ -+ unsigned int endd_ctrl; /* 0x00000014 */ -+ /** I2C Fractional Divider Configuration Register -+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_HIGH_CFG has the same layout as I2C_FDIV_CFG. */ -+ unsigned int fdiv_cfg; /* 0x00000018 */ -+ /** I2C Fractional Divider (highspeed mode) Configuration Register -+ These register is used to program the fractional divider of the I2C bus. Before the peripheral is switched on by setting the RUN-bit the two (fixed) values for the two operating frequencies are programmed into these (configuration) registers. The Register FDIV_CFG has the same layout as I2C_FDIV_CFG. */ -+ unsigned int fdiv_high_cfg; /* 0x0000001C */ -+ /** I2C Address Configuration Register */ -+ unsigned int addr_cfg; /* 0x00000020 */ -+ /** I2C Bus Status Register -+ This register gives a status information of the I2C. This additional information can be used by the software to start proper actions. */ -+ unsigned int bus_stat; /* 0x00000024 */ -+ /** I2C FIFO Configuration Register */ -+ unsigned int fifo_cfg; /* 0x00000028 */ -+ /** I2C Maximum Received Packet Size Register */ -+ unsigned int mrps_ctrl; /* 0x0000002C */ -+ /** I2C Received Packet Size Status Register */ -+ unsigned int rps_stat; /* 0x00000030 */ -+ /** I2C Transmit Packet Size Register */ -+ unsigned int tps_ctrl; /* 0x00000034 */ -+ /** I2C Filled FIFO Stages Status Register */ -+ unsigned int ffs_stat; /* 0x00000038 */ -+ /** Reserved */ -+ unsigned int res_2; /* 0x0000003C */ -+ /** I2C Timing Configuration Register */ -+ unsigned int tim_cfg; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_3[7]; /* 0x00000044 */ -+ /** I2C Error Interrupt Request Source Mask Register */ -+ unsigned int err_irqsm; /* 0x00000060 */ -+ /** I2C Error Interrupt Request Source Status Register */ -+ unsigned int err_irqss; /* 0x00000064 */ -+ /** I2C Error Interrupt Request Source Clear Register */ -+ unsigned int err_irqsc; /* 0x00000068 */ -+ /** Reserved */ -+ unsigned int res_4; /* 0x0000006C */ -+ /** I2C Protocol Interrupt Request Source Mask Register */ -+ unsigned int p_irqsm; /* 0x00000070 */ -+ /** I2C Protocol Interrupt Request Source Status Register */ -+ unsigned int p_irqss; /* 0x00000074 */ -+ /** I2C Protocol Interrupt Request Source Clear Register */ -+ unsigned int p_irqsc; /* 0x00000078 */ -+ /** Reserved */ -+ unsigned int res_5; /* 0x0000007C */ -+ /** I2C Raw Interrupt Status Register */ -+ unsigned int ris; /* 0x00000080 */ -+ /** I2C Interrupt Mask Control Register */ -+ unsigned int imsc; /* 0x00000084 */ -+ /** I2C Masked Interrupt Status Register */ -+ unsigned int mis; /* 0x00000088 */ -+ /** I2C Interrupt Clear Register */ -+ unsigned int icr; /* 0x0000008C */ -+ /** I2C Interrupt Set Register */ -+ unsigned int isr; /* 0x00000090 */ -+ /** I2C DMA Enable Register */ -+ unsigned int dmae; /* 0x00000094 */ -+ /** Reserved */ -+ unsigned int res_6[8154]; /* 0x00000098 */ -+ /** I2C Transmit Data Register */ -+ unsigned int txd; /* 0x00008000 */ -+ /** Reserved */ -+ unsigned int res_7[4095]; /* 0x00008004 */ -+ /** I2C Receive Data Register */ -+ unsigned int rxd; /* 0x0000C000 */ -+ /** Reserved */ -+ unsigned int res_8[4095]; /* 0x0000C004 */ -+}; -+ -+ -+/* Fields of "I2C Kernel Clock Control Register" */ -+/** Clock Divider for Optional Run Mode (AHB peripherals) -+ Max 8-bit divider value. Note: As long as the new divider value ORMC is not valid, the register returns 0x0000 00xx on reading. */ -+#define I2C_CLC_ORMC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_CLC_ORMC_OFFSET 16 -+/** Clock Divider for Normal Run Mode -+ Max 8-bit divider value. IF RMC is 0 the module is disabled. Note: As long as the new divider value RMC is not valid, the register returns 0x0000 00xx on reading. */ -+#define I2C_CLC_RMC_MASK 0x0000FF00 -+/** field offset */ -+#define I2C_CLC_RMC_OFFSET 8 -+/** Fast Shut-Off Enable Bit */ -+#define I2C_CLC_FSOE 0x00000020 -+/* Disable -+#define I2C_CLC_FSOE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_FSOE_EN 0x00000020 -+/** Suspend Bit Write Enable for OCDS */ -+#define I2C_CLC_SBWE 0x00000010 -+/* Disable -+#define I2C_CLC_SBWE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_SBWE_EN 0x00000010 -+/** Disable External Request Disable */ -+#define I2C_CLC_EDIS 0x00000008 -+/* Enable -+#define I2C_CLC_EDIS_EN 0x00000000 */ -+/** Disable */ -+#define I2C_CLC_EDIS_DIS 0x00000008 -+/** Suspend Enable Bit for OCDS */ -+#define I2C_CLC_SPEN 0x00000004 -+/* Disable -+#define I2C_CLC_SPEN_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_CLC_SPEN_EN 0x00000004 -+/** Disable Status Bit -+ Bit DISS can be modified only by writing to bit DISR */ -+#define I2C_CLC_DISS 0x00000002 -+/* Enable -+#define I2C_CLC_DISS_EN 0x00000000 */ -+/** Disable */ -+#define I2C_CLC_DISS_DIS 0x00000002 -+/** Disable Request Bit */ -+#define I2C_CLC_DISR 0x00000001 -+/* Module disable not requested -+#define I2C_CLC_DISR_OFF 0x00000000 */ -+/** Module disable requested */ -+#define I2C_CLC_DISR_ON 0x00000001 -+ -+/* Fields of "I2C Identification Register" */ -+/** Module ID */ -+#define I2C_ID_ID_MASK 0x0000FF00 -+/** field offset */ -+#define I2C_ID_ID_OFFSET 8 -+/** Revision */ -+#define I2C_ID_REV_MASK 0x000000FF -+/** field offset */ -+#define I2C_ID_REV_OFFSET 0 -+ -+/* Fields of "I2C RUN Control Register" */ -+/** Enabling I2C Interface -+ Only when this bit is set to zero, the configuration registers of the I2C peripheral are writable by SW. */ -+#define I2C_RUN_CTRL_RUN 0x00000001 -+/* Disable -+#define I2C_RUN_CTRL_RUN_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_RUN_CTRL_RUN_EN 0x00000001 -+ -+/* Fields of "I2C End Data Control Register" */ -+/** Set End of Transmission -+ Note:Do not write '1' to this bit when bus is free. This will cause an abort after the first byte when a new transfer is started. */ -+#define I2C_ENDD_CTRL_SETEND 0x00000002 -+/* No-Operation -+#define I2C_ENDD_CTRL_SETEND_NOP 0x00000000 */ -+/** Master Receives Bytes */ -+#define I2C_ENDD_CTRL_SETEND_MRB 0x00000002 -+/** Set Restart Condition */ -+#define I2C_ENDD_CTRL_SETRSC 0x00000001 -+/* No-Operation -+#define I2C_ENDD_CTRL_SETRSC_NOP 0x00000000 */ -+/** Master Restart */ -+#define I2C_ENDD_CTRL_SETRSC_RESTART 0x00000001 -+ -+/* Fields of "I2C Fractional Divider Configuration Register" */ -+/** Decrement Value of fractional divider */ -+#define I2C_FDIV_CFG_INC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_FDIV_CFG_INC_OFFSET 16 -+/** Increment Value of fractional divider */ -+#define I2C_FDIV_CFG_DEC_MASK 0x000007FF -+/** field offset */ -+#define I2C_FDIV_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Fractional Divider (highspeed mode) Configuration Register" */ -+/** Decrement Value of fractional divider */ -+#define I2C_FDIV_HIGH_CFG_INC_MASK 0x00FF0000 -+/** field offset */ -+#define I2C_FDIV_HIGH_CFG_INC_OFFSET 16 -+/** Increment Value of fractional divider */ -+#define I2C_FDIV_HIGH_CFG_DEC_MASK 0x000007FF -+/** field offset */ -+#define I2C_FDIV_HIGH_CFG_DEC_OFFSET 0 -+ -+/* Fields of "I2C Address Configuration Register" */ -+/** Stop on Packet End -+ If device works as receiver a not acknowledge is generated in both cases. After successful transmission of a master code (during high speed mode) SOPE is not considered till a stop condition is manually generated by SETEND. */ -+#define I2C_ADDR_CFG_SOPE 0x00200000 -+/* Disable -+#define I2C_ADDR_CFG_SOPE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_SOPE_EN 0x00200000 -+/** Stop on Not Acknowledge -+ After successful transmission of a master code (during high speed mode) SONA is not considered till a stop condition is manually generated by SETEND. */ -+#define I2C_ADDR_CFG_SONA 0x00100000 -+/* Disable -+#define I2C_ADDR_CFG_SONA_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_SONA_EN 0x00100000 -+/** Master Enable */ -+#define I2C_ADDR_CFG_MnS 0x00080000 -+/* Disable -+#define I2C_ADDR_CFG_MnS_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_MnS_EN 0x00080000 -+/** Master Code Enable */ -+#define I2C_ADDR_CFG_MCE 0x00040000 -+/* Disable -+#define I2C_ADDR_CFG_MCE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_MCE_EN 0x00040000 -+/** General Call Enable */ -+#define I2C_ADDR_CFG_GCE 0x00020000 -+/* Disable -+#define I2C_ADDR_CFG_GCE_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ADDR_CFG_GCE_EN 0x00020000 -+/** Ten Bit Address Mode */ -+#define I2C_ADDR_CFG_TBAM 0x00010000 -+/* 7-bit address mode enabled. -+#define I2C_ADDR_CFG_TBAM_7bit 0x00000000 */ -+/** 10-bit address mode enabled. */ -+#define I2C_ADDR_CFG_TBAM_10bit 0x00010000 -+/** I2C Bus device address -+ This is the address of this device. (Watch out for reserved addresses by referring to Phillips Spec V2.1) This could either be a 7bit- address (bits [7:1]) or a 10bit- address (bits [9:0]). Note:The validity of the bits are in accordance with the TBAM bit. Bit-1 (Bit-0) is the LSB of the device address. */ -+#define I2C_ADDR_CFG_ADR_MASK 0x000003FF -+/** field offset */ -+#define I2C_ADDR_CFG_ADR_OFFSET 0 -+ -+/* Fields of "I2C Bus Status Register" */ -+/** Read / not Write */ -+#define I2C_BUS_STAT_RNW 0x00000004 -+/* Write to I2C Bus. -+#define I2C_BUS_STAT_RNW_WRITE 0x00000000 */ -+/** Read from I2C Bus. */ -+#define I2C_BUS_STAT_RNW_READ 0x00000004 -+/** Bus Status */ -+#define I2C_BUS_STAT_BS_MASK 0x00000003 -+/** field offset */ -+#define I2C_BUS_STAT_BS_OFFSET 0 -+/** I2C Bus is free. */ -+#define I2C_BUS_STAT_BS_FREE 0x00000000 -+/** A start condition has been detected on the bus (bus busy). */ -+#define I2C_BUS_STAT_BS_SC 0x00000001 -+/** The device is working as master and has claimed the control on the I2C-bus (busy master). */ -+#define I2C_BUS_STAT_BS_BM 0x00000002 -+/** A remote master has accessed this device as slave. */ -+#define I2C_BUS_STAT_BS_RM 0x00000003 -+ -+/* Fields of "I2C FIFO Configuration Register" */ -+/** TX FIFO Flow Control */ -+#define I2C_FIFO_CFG_TXFC 0x00020000 -+/* TX FIFO not as Flow Controller -+#define I2C_FIFO_CFG_TXFC_TXNFC 0x00000000 */ -+/** RX FIFO Flow Control */ -+#define I2C_FIFO_CFG_RXFC 0x00010000 -+/* RX FIFO not as Flow Controller -+#define I2C_FIFO_CFG_RXFC_RXNFC 0x00000000 */ -+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ -+#define I2C_FIFO_CFG_TXFA_MASK 0x00003000 -+/** field offset */ -+#define I2C_FIFO_CFG_TXFA_OFFSET 12 -+/** Byte aligned (character alignment) */ -+#define I2C_FIFO_CFG_TXFA_TXFA0 0x00000000 -+/** Half word aligned (character alignment of two characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA1 0x00001000 -+/** Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_TXFA_TXFA2 0x00002000 -+/** Double word aligned (character alignment of eight */ -+#define I2C_FIFO_CFG_TXFA_TXFA3 0x00003000 -+/** The reset value depends on the used character sizes of the peripheral. The maximum selectable alignment depends on the maximum number of characters per stage. */ -+#define I2C_FIFO_CFG_RXFA_MASK 0x00000300 -+/** field offset */ -+#define I2C_FIFO_CFG_RXFA_OFFSET 8 -+/** Byte aligned (character alignment) */ -+#define I2C_FIFO_CFG_RXFA_RXFA0 0x00000000 -+/** Half word aligned (character alignment of two characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA1 0x00000100 -+/** Word aligned (character alignment of four characters) */ -+#define I2C_FIFO_CFG_RXFA_RXFA2 0x00000200 -+/** Double word aligned (character alignment of eight */ -+#define I2C_FIFO_CFG_RXFA_RXFA3 0x00000300 -+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ -+#define I2C_FIFO_CFG_TXBS_MASK 0x00000030 -+/** field offset */ -+#define I2C_FIFO_CFG_TXBS_OFFSET 4 -+/** 1 word */ -+#define I2C_FIFO_CFG_TXBS_TXBS0 0x00000000 -+/** 2 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS1 0x00000010 -+/** 4 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS2 0x00000020 -+/** 8 words */ -+#define I2C_FIFO_CFG_TXBS_TXBS3 0x00000030 -+/** DMA controller does not support a burst size of 2 words. The reset value is the half of the FIFO size. The maximum selectable burst size is smaller than the FIFO size. */ -+#define I2C_FIFO_CFG_RXBS_MASK 0x00000003 -+/** field offset */ -+#define I2C_FIFO_CFG_RXBS_OFFSET 0 -+/** 1 word */ -+#define I2C_FIFO_CFG_RXBS_RXBS0 0x00000000 -+/** 2 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS1 0x00000001 -+/** 4 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS2 0x00000002 -+/** 8 words */ -+#define I2C_FIFO_CFG_RXBS_RXBS3 0x00000003 -+ -+/* Fields of "I2C Maximum Received Packet Size Register" */ -+/** MRPS */ -+#define I2C_MRPS_CTRL_MRPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_MRPS_CTRL_MRPS_OFFSET 0 -+ -+/* Fields of "I2C Received Packet Size Status Register" */ -+/** RPS */ -+#define I2C_RPS_STAT_RPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_RPS_STAT_RPS_OFFSET 0 -+ -+/* Fields of "I2C Transmit Packet Size Register" */ -+/** TPS */ -+#define I2C_TPS_CTRL_TPS_MASK 0x00003FFF -+/** field offset */ -+#define I2C_TPS_CTRL_TPS_OFFSET 0 -+ -+/* Fields of "I2C Filled FIFO Stages Status Register" */ -+/** FFS */ -+#define I2C_FFS_STAT_FFS_MASK 0x0000000F -+/** field offset */ -+#define I2C_FFS_STAT_FFS_OFFSET 0 -+ -+/* Fields of "I2C Timing Configuration Register" */ -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_HS_SDA_DEL_MASK 0x00070000 -+/** field offset */ -+#define I2C_TIM_CFG_HS_SDA_DEL_OFFSET 16 -+/** Enable Fast Mode SCL Low period timing */ -+#define I2C_TIM_CFG_FS_SCL_LOW 0x00008000 -+/* Disable -+#define I2C_TIM_CFG_FS_SCL_LOW_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_TIM_CFG_FS_SCL_LOW_EN 0x00008000 -+/** SCL Delay Stages for Hold Time Start (Restart) Bit. -+ The actual delay is calculated as the value of this field + 2 */ -+#define I2C_TIM_CFG_SCL_DEL_HD_STA_MASK 0x00000E00 -+/** field offset */ -+#define I2C_TIM_CFG_SCL_DEL_HD_STA_OFFSET 9 -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_MASK 0x000001C0 -+/** field offset */ -+#define I2C_TIM_CFG_HS_SDA_DEL_HD_DAT_OFFSET 6 -+/** SDA Delay Stages for Start/Stop bit in High Speed Mode -+ The actual delay is calculated as the value of this field + 3 */ -+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_MASK 0x0000003F -+/** field offset */ -+#define I2C_TIM_CFG_SDA_DEL_HD_DAT_OFFSET 0 -+ -+/* Fields of "I2C Error Interrupt Request Source Mask Register" */ -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_TXF_OFL 0x00000008 -+/* Disable -+#define I2C_ERR_IRQSM_TXF_OFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_TXF_OFL_EN 0x00000008 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_TXF_UFL 0x00000004 -+/* Disable -+#define I2C_ERR_IRQSM_TXF_UFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_TXF_UFL_EN 0x00000004 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_RXF_OFL 0x00000002 -+/* Disable -+#define I2C_ERR_IRQSM_RXF_OFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_RXF_OFL_EN 0x00000002 -+/** Enables the corresponding error interrupt. */ -+#define I2C_ERR_IRQSM_RXF_UFL 0x00000001 -+/* Disable -+#define I2C_ERR_IRQSM_RXF_UFL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_ERR_IRQSM_RXF_UFL_EN 0x00000001 -+ -+/* Fields of "I2C Error Interrupt Request Source Status Register" */ -+/** TXF_OFL */ -+#define I2C_ERR_IRQSS_TXF_OFL 0x00000008 -+/* Nothing -+#define I2C_ERR_IRQSS_TXF_OFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_TXF_OFL_INTOCC 0x00000008 -+/** TXF_UFL */ -+#define I2C_ERR_IRQSS_TXF_UFL 0x00000004 -+/* Nothing -+#define I2C_ERR_IRQSS_TXF_UFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_TXF_UFL_INTOCC 0x00000004 -+/** RXF_OFL */ -+#define I2C_ERR_IRQSS_RXF_OFL 0x00000002 -+/* Nothing -+#define I2C_ERR_IRQSS_RXF_OFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_RXF_OFL_INTOCC 0x00000002 -+/** RXF_UFL */ -+#define I2C_ERR_IRQSS_RXF_UFL 0x00000001 -+/* Nothing -+#define I2C_ERR_IRQSS_RXF_UFL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_ERR_IRQSS_RXF_UFL_INTOCC 0x00000001 -+ -+/* Fields of "I2C Error Interrupt Request Source Clear Register" */ -+/** TXF_OFL */ -+#define I2C_ERR_IRQSC_TXF_OFL 0x00000008 -+/* No-Operation -+#define I2C_ERR_IRQSC_TXF_OFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_TXF_OFL_CLR 0x00000008 -+/** TXF_UFL */ -+#define I2C_ERR_IRQSC_TXF_UFL 0x00000004 -+/* No-Operation -+#define I2C_ERR_IRQSC_TXF_UFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_TXF_UFL_CLR 0x00000004 -+/** RXF_OFL */ -+#define I2C_ERR_IRQSC_RXF_OFL 0x00000002 -+/* No-Operation -+#define I2C_ERR_IRQSC_RXF_OFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_RXF_OFL_CLR 0x00000002 -+/** RXF_UFL */ -+#define I2C_ERR_IRQSC_RXF_UFL 0x00000001 -+/* No-Operation -+#define I2C_ERR_IRQSC_RXF_UFL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ERR_IRQSC_RXF_UFL_CLR 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Mask Register" */ -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_RX 0x00000040 -+/* Disable -+#define I2C_P_IRQSM_RX_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_RX_EN 0x00000040 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_TX_END 0x00000020 -+/* Disable -+#define I2C_P_IRQSM_TX_END_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_TX_END_EN 0x00000020 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_NACK 0x00000010 -+/* Disable -+#define I2C_P_IRQSM_NACK_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_NACK_EN 0x00000010 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_AL 0x00000008 -+/* Disable -+#define I2C_P_IRQSM_AL_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_AL_EN 0x00000008 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_MC 0x00000004 -+/* Disable -+#define I2C_P_IRQSM_MC_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_MC_EN 0x00000004 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_GC 0x00000002 -+/* Disable -+#define I2C_P_IRQSM_GC_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_GC_EN 0x00000002 -+/** Enables the corresponding interrupt. */ -+#define I2C_P_IRQSM_AM 0x00000001 -+/* Disable -+#define I2C_P_IRQSM_AM_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_P_IRQSM_AM_EN 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Status Register" */ -+/** RX */ -+#define I2C_P_IRQSS_RX 0x00000040 -+/* Nothing -+#define I2C_P_IRQSS_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_RX_INTOCC 0x00000040 -+/** TX_END */ -+#define I2C_P_IRQSS_TX_END 0x00000020 -+/* Nothing -+#define I2C_P_IRQSS_TX_END_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_TX_END_INTOCC 0x00000020 -+/** NACK */ -+#define I2C_P_IRQSS_NACK 0x00000010 -+/* Nothing -+#define I2C_P_IRQSS_NACK_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_NACK_INTOCC 0x00000010 -+/** AL */ -+#define I2C_P_IRQSS_AL 0x00000008 -+/* Nothing -+#define I2C_P_IRQSS_AL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_AL_INTOCC 0x00000008 -+/** MC */ -+#define I2C_P_IRQSS_MC 0x00000004 -+/* Nothing -+#define I2C_P_IRQSS_MC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_MC_INTOCC 0x00000004 -+/** GC */ -+#define I2C_P_IRQSS_GC 0x00000002 -+/* Nothing -+#define I2C_P_IRQSS_GC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_GC_INTOCC 0x00000002 -+/** AM */ -+#define I2C_P_IRQSS_AM 0x00000001 -+/* Nothing -+#define I2C_P_IRQSS_AM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_P_IRQSS_AM_INTOCC 0x00000001 -+ -+/* Fields of "I2C Protocol Interrupt Request Source Clear Register" */ -+/** RX */ -+#define I2C_P_IRQSC_RX 0x00000040 -+/* No-Operation -+#define I2C_P_IRQSC_RX_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_RX_CLR 0x00000040 -+/** TX_END */ -+#define I2C_P_IRQSC_TX_END 0x00000020 -+/* No-Operation -+#define I2C_P_IRQSC_TX_END_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_TX_END_CLR 0x00000020 -+/** NACK */ -+#define I2C_P_IRQSC_NACK 0x00000010 -+/* No-Operation -+#define I2C_P_IRQSC_NACK_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_NACK_CLR 0x00000010 -+/** AL */ -+#define I2C_P_IRQSC_AL 0x00000008 -+/* No-Operation -+#define I2C_P_IRQSC_AL_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_AL_CLR 0x00000008 -+/** MC */ -+#define I2C_P_IRQSC_MC 0x00000004 -+/* No-Operation -+#define I2C_P_IRQSC_MC_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_MC_CLR 0x00000004 -+/** GC */ -+#define I2C_P_IRQSC_GC 0x00000002 -+/* No-Operation -+#define I2C_P_IRQSC_GC_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_GC_CLR 0x00000002 -+/** AM */ -+#define I2C_P_IRQSC_AM 0x00000001 -+/* No-Operation -+#define I2C_P_IRQSC_AM_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_P_IRQSC_AM_CLR 0x00000001 -+ -+/* Fields of "I2C Raw Interrupt Status Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_RIS_I2C_P_INT 0x00000020 -+/* Nothing -+#define I2C_RIS_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_P_INT_INTOCC 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_RIS_I2C_ERR_INT 0x00000010 -+/* Nothing -+#define I2C_RIS_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_I2C_ERR_INT_INTOCC 0x00000010 -+/** BREQ_INT */ -+#define I2C_RIS_BREQ_INT 0x00000008 -+/* Nothing -+#define I2C_RIS_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_BREQ_INT_INTOCC 0x00000008 -+/** LBREQ_INT */ -+#define I2C_RIS_LBREQ_INT 0x00000004 -+/* Nothing -+#define I2C_RIS_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_LBREQ_INT_INTOCC 0x00000004 -+/** SREQ_INT */ -+#define I2C_RIS_SREQ_INT 0x00000002 -+/* Nothing -+#define I2C_RIS_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_SREQ_INT_INTOCC 0x00000002 -+/** LSREQ_INT */ -+#define I2C_RIS_LSREQ_INT 0x00000001 -+/* Nothing -+#define I2C_RIS_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_RIS_LSREQ_INT_INTOCC 0x00000001 -+ -+/* Fields of "I2C Interrupt Mask Control Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_IMSC_I2C_P_INT 0x00000020 -+/* Disable -+#define I2C_IMSC_I2C_P_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_I2C_P_INT_EN 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_IMSC_I2C_ERR_INT 0x00000010 -+/* Disable -+#define I2C_IMSC_I2C_ERR_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_I2C_ERR_INT_EN 0x00000010 -+/** BREQ_INT */ -+#define I2C_IMSC_BREQ_INT 0x00000008 -+/* Disable -+#define I2C_IMSC_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_BREQ_INT_EN 0x00000008 -+/** LBREQ_INT */ -+#define I2C_IMSC_LBREQ_INT 0x00000004 -+/* Disable -+#define I2C_IMSC_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_LBREQ_INT_EN 0x00000004 -+/** SREQ_INT */ -+#define I2C_IMSC_SREQ_INT 0x00000002 -+/* Disable -+#define I2C_IMSC_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_SREQ_INT_EN 0x00000002 -+/** LSREQ_INT */ -+#define I2C_IMSC_LSREQ_INT 0x00000001 -+/* Disable -+#define I2C_IMSC_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_IMSC_LSREQ_INT_EN 0x00000001 -+ -+/* Fields of "I2C Masked Interrupt Status Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_MIS_I2C_P_INT 0x00000020 -+/* Nothing -+#define I2C_MIS_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_I2C_P_INT_INTOCC 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_MIS_I2C_ERR_INT 0x00000010 -+/* Nothing -+#define I2C_MIS_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_I2C_ERR_INT_INTOCC 0x00000010 -+/** BREQ_INT */ -+#define I2C_MIS_BREQ_INT 0x00000008 -+/* Nothing -+#define I2C_MIS_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_BREQ_INT_INTOCC 0x00000008 -+/** LBREQ_INT */ -+#define I2C_MIS_LBREQ_INT 0x00000004 -+/* Nothing -+#define I2C_MIS_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_LBREQ_INT_INTOCC 0x00000004 -+/** SREQ_INT */ -+#define I2C_MIS_SREQ_INT 0x00000002 -+/* Nothing -+#define I2C_MIS_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_SREQ_INT_INTOCC 0x00000002 -+/** LSREQ_INT */ -+#define I2C_MIS_LSREQ_INT 0x00000001 -+/* Nothing -+#define I2C_MIS_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define I2C_MIS_LSREQ_INT_INTOCC 0x00000001 -+ -+/* Fields of "I2C Interrupt Clear Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_ICR_I2C_P_INT 0x00000020 -+/* No-Operation -+#define I2C_ICR_I2C_P_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_I2C_P_INT_CLR 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_ICR_I2C_ERR_INT 0x00000010 -+/* No-Operation -+#define I2C_ICR_I2C_ERR_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_I2C_ERR_INT_CLR 0x00000010 -+/** BREQ_INT */ -+#define I2C_ICR_BREQ_INT 0x00000008 -+/* No-Operation -+#define I2C_ICR_BREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_BREQ_INT_CLR 0x00000008 -+/** LBREQ_INT */ -+#define I2C_ICR_LBREQ_INT 0x00000004 -+/* No-Operation -+#define I2C_ICR_LBREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_LBREQ_INT_CLR 0x00000004 -+/** SREQ_INT */ -+#define I2C_ICR_SREQ_INT 0x00000002 -+/* No-Operation -+#define I2C_ICR_SREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_SREQ_INT_CLR 0x00000002 -+/** LSREQ_INT */ -+#define I2C_ICR_LSREQ_INT 0x00000001 -+/* No-Operation -+#define I2C_ICR_LSREQ_INT_NOP 0x00000000 */ -+/** Clear */ -+#define I2C_ICR_LSREQ_INT_CLR 0x00000001 -+ -+/* Fields of "I2C Interrupt Set Register" */ -+/** This is the combined interrupt bit for indication of an protocol event in the I2C kernel. */ -+#define I2C_ISR_I2C_P_INT 0x00000020 -+/* No-Operation -+#define I2C_ISR_I2C_P_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_I2C_P_INT_SET 0x00000020 -+/** This is the combined interrupt bit for indication of FIFO errors due to overflow and underrun. */ -+#define I2C_ISR_I2C_ERR_INT 0x00000010 -+/* No-Operation -+#define I2C_ISR_I2C_ERR_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_I2C_ERR_INT_SET 0x00000010 -+/** BREQ_INT */ -+#define I2C_ISR_BREQ_INT 0x00000008 -+/* No-Operation -+#define I2C_ISR_BREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_BREQ_INT_SET 0x00000008 -+/** LBREQ_INT */ -+#define I2C_ISR_LBREQ_INT 0x00000004 -+/* No-Operation -+#define I2C_ISR_LBREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_LBREQ_INT_SET 0x00000004 -+/** SREQ_INT */ -+#define I2C_ISR_SREQ_INT 0x00000002 -+/* No-Operation -+#define I2C_ISR_SREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_SREQ_INT_SET 0x00000002 -+/** LSREQ_INT */ -+#define I2C_ISR_LSREQ_INT 0x00000001 -+/* No-Operation -+#define I2C_ISR_LSREQ_INT_NOP 0x00000000 */ -+/** Set */ -+#define I2C_ISR_LSREQ_INT_SET 0x00000001 -+ -+/* Fields of "I2C DMA Enable Register" */ -+/** BREQ_INT */ -+#define I2C_DMAE_BREQ_INT 0x00000008 -+/* Disable -+#define I2C_DMAE_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_BREQ_INT_EN 0x00000008 -+/** LBREQ_INT */ -+#define I2C_DMAE_LBREQ_INT 0x00000004 -+/* Disable -+#define I2C_DMAE_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_LBREQ_INT_EN 0x00000004 -+/** SREQ_INT */ -+#define I2C_DMAE_SREQ_INT 0x00000002 -+/* Disable -+#define I2C_DMAE_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_SREQ_INT_EN 0x00000002 -+/** LSREQ_INT */ -+#define I2C_DMAE_LSREQ_INT 0x00000001 -+/* Disable -+#define I2C_DMAE_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define I2C_DMAE_LSREQ_INT_EN 0x00000001 -+ -+/* Fields of "I2C Transmit Data Register" */ -+/** Characters to be transmitted */ -+#define I2C_TXD_TXD_MASK 0xFFFFFFFF -+/** field offset */ -+#define I2C_TXD_TXD_OFFSET 0 -+ -+/* Fields of "I2C Receive Data Register" */ -+/** Received characters */ -+#define I2C_RXD_RXD_MASK 0xFFFFFFFF -+/** field offset */ -+#define I2C_RXD_RXD_OFFSET 0 -+ -+/*! @} */ /* I2C_REGISTER */ -+ -+#endif /* _i2c_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h -new file mode 100644 -index 0000000..d68c22e ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/icu0_reg.h -@@ -0,0 +1,4324 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _icu0_reg_h -+#define _icu0_reg_h -+ -+/** \addtogroup ICU0_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define icu0_r32(reg) reg_r32(&icu0->reg) -+#define icu0_w32(val, reg) reg_w32(val, &icu0->reg) -+#define icu0_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &icu0->reg) -+#define icu0_r32_table(reg, idx) reg_r32_table(icu0->reg, idx) -+#define icu0_w32_table(val, reg, idx) reg_w32_table(val, icu0->reg, idx) -+#define icu0_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, icu0->reg, idx) -+#define icu0_adr_table(reg, idx) adr_table(icu0->reg, idx) -+ -+ -+/** ICU0 register structure */ -+struct gpon_reg_icu0 -+{ -+ /** IM0 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im0_isr; /* 0x00000000 */ -+ /** Reserved */ -+ unsigned int res_0; /* 0x00000004 */ -+ /** IM0 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM0_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im0_ier; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_1; /* 0x0000000C */ -+ /** IM0 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM0_IER register. */ -+ unsigned int im0_iosr; /* 0x00000010 */ -+ /** Reserved */ -+ unsigned int res_2; /* 0x00000014 */ -+ /** IM0 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im0_irsr; /* 0x00000018 */ -+ /** Reserved */ -+ unsigned int res_3; /* 0x0000001C */ -+ /** IM0 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im0_imr; /* 0x00000020 */ -+ /** Reserved */ -+ unsigned int res_4; /* 0x00000024 */ -+ /** IM1 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im1_isr; /* 0x00000028 */ -+ /** Reserved */ -+ unsigned int res_5; /* 0x0000002C */ -+ /** IM1 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM1_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im1_ier; /* 0x00000030 */ -+ /** Reserved */ -+ unsigned int res_6; /* 0x00000034 */ -+ /** IM1 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM1_IER register. */ -+ unsigned int im1_iosr; /* 0x00000038 */ -+ /** Reserved */ -+ unsigned int res_7; /* 0x0000003C */ -+ /** IM1 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im1_irsr; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_8; /* 0x00000044 */ -+ /** IM1 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im1_imr; /* 0x00000048 */ -+ /** Reserved */ -+ unsigned int res_9; /* 0x0000004C */ -+ /** IM2 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im2_isr; /* 0x00000050 */ -+ /** Reserved */ -+ unsigned int res_10; /* 0x00000054 */ -+ /** IM2 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM2_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im2_ier; /* 0x00000058 */ -+ /** Reserved */ -+ unsigned int res_11; /* 0x0000005C */ -+ /** IM2 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM2_IER register. */ -+ unsigned int im2_iosr; /* 0x00000060 */ -+ /** Reserved */ -+ unsigned int res_12; /* 0x00000064 */ -+ /** IM2 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im2_irsr; /* 0x00000068 */ -+ /** Reserved */ -+ unsigned int res_13; /* 0x0000006C */ -+ /** IM2 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im2_imr; /* 0x00000070 */ -+ /** Reserved */ -+ unsigned int res_14; /* 0x00000074 */ -+ /** IM3 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im3_isr; /* 0x00000078 */ -+ /** Reserved */ -+ unsigned int res_15; /* 0x0000007C */ -+ /** IM3 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM3_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im3_ier; /* 0x00000080 */ -+ /** Reserved */ -+ unsigned int res_16; /* 0x00000084 */ -+ /** IM3 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM3_IER register. */ -+ unsigned int im3_iosr; /* 0x00000088 */ -+ /** Reserved */ -+ unsigned int res_17; /* 0x0000008C */ -+ /** IM3 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im3_irsr; /* 0x00000090 */ -+ /** Reserved */ -+ unsigned int res_18; /* 0x00000094 */ -+ /** IM3 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im3_imr; /* 0x00000098 */ -+ /** Reserved */ -+ unsigned int res_19; /* 0x0000009C */ -+ /** IM4 Interrupt Status Register -+ A read action to this register delivers the unmasked captured status of the interrupt request lines. Each bit can be cleared by a write operation. */ -+ unsigned int im4_isr; /* 0x000000A0 */ -+ /** Reserved */ -+ unsigned int res_20; /* 0x000000A4 */ -+ /** IM4 Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IM4_IOSR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int im4_ier; /* 0x000000A8 */ -+ /** Reserved */ -+ unsigned int res_21; /* 0x000000AC */ -+ /** IM4 Interrupt Output Status Register -+ This register shows the currently active interrupt requests masked with the corresponding enable bits of the IM4_IER register. */ -+ unsigned int im4_iosr; /* 0x000000B0 */ -+ /** Reserved */ -+ unsigned int res_22; /* 0x000000B4 */ -+ /** IM4 Interrupt Request Set Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int im4_irsr; /* 0x000000B8 */ -+ /** Reserved */ -+ unsigned int res_23; /* 0x000000BC */ -+ /** IM4 Interrupt Mode Register -+ This register shows the type of interrupt for each bit. */ -+ unsigned int im4_imr; /* 0x000000C0 */ -+ /** Reserved */ -+ unsigned int res_24; /* 0x000000C4 */ -+ /** ICU Interrupt Vector Register (5 bit variant) -+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ -+ unsigned int icu_ivec; /* 0x000000C8 */ -+ /** Reserved */ -+ unsigned int res_25; /* 0x000000CC */ -+ /** ICU Interrupt Vector Register (6 bit variant) -+ Shows the leftmost pending interrupt request. If e.g. bit 14 of the IOSR register is set, 15 is reported, because the 15th interrupt request is active. */ -+ unsigned int icu_ivec_6; /* 0x000000D0 */ -+ /** Reserved */ -+ unsigned int res_26[3]; /* 0x000000D4 */ -+}; -+ -+ -+/* Fields of "IM0 Interrupt Status Register" */ -+/** PCM Transmit Crash Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH 0x80000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_HW2_CRASH_INTOCC 0x80000000 -+/** PCM Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_TX 0x40000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_TX_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_TX_INTOCC 0x40000000 -+/** PCM Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_PCM_RX 0x20000000 -+/* Nothing -+#define ICU0_IM0_ISR_PCM_RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_PCM_RX_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_PCM_RX_INTOCC 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SHA1_HASH 0x10000000 -+/* Nothing -+#define ICU0_IM0_ISR_SHA1_HASH_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SHA1_HASH_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SHA1_HASH_INTOCC 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_AES_AES 0x08000000 -+/* Nothing -+#define ICU0_IM0_ISR_AES_AES_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_AES_AES_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_AES_AES_INTOCC 0x08000000 -+/** SSC Frame Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_F 0x00020000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_F_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_F_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_F_INTOCC 0x00020000 -+/** SSC Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_E 0x00010000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_E_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_E_INTOCC 0x00010000 -+/** SSC Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_R 0x00008000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_R_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_R_INTOCC 0x00008000 -+/** SSC Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM0_ISR_SSC0_T 0x00004000 -+/* Nothing -+#define ICU0_IM0_ISR_SSC0_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_SSC0_T_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_SSC0_T_INTOCC 0x00004000 -+/** I2C Peripheral Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT 0x00002000 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_I2C_P_INT_INTOCC 0x00002000 -+/** I2C Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT 0x00001000 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_I2C_ERR_INT_INTOCC 0x00001000 -+/** I2C Burst Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT 0x00000800 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_BREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_BREQ_INT_INTOCC 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT 0x00000400 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_LBREQ_INT_INTOCC 0x00000400 -+/** I2C Single Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT 0x00000200 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_SREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_SREQ_INT_INTOCC 0x00000200 -+/** I2C Last Single Data Transfer Request -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT 0x00000100 -+/* Nothing -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_I2C_LSREQ_INT_INTOCC 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR 0x00000010 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB1_TIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB1_TIR_INTOCC 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR 0x00000008 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB1_RIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB1_RIR_INTOCC 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR 0x00000004 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB0_TIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB0_TIR_INTOCC 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR 0x00000002 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_MB0_RIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_MB0_RIR_INTOCC 0x00000002 -+/** HOST IF Event Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM0_ISR_HOST_EIR 0x00000001 -+/* Nothing -+#define ICU0_IM0_ISR_HOST_EIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM0_ISR_HOST_EIR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_ISR_HOST_EIR_INTOCC 0x00000001 -+ -+/* Fields of "IM0 Interrupt Enable Register" */ -+/** PCM Transmit Crash Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_HW2_CRASH 0x80000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_HW2_CRASH_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_HW2_CRASH_EN 0x80000000 -+/** PCM Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_TX 0x40000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_TX_EN 0x40000000 -+/** PCM Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_PCM_RX 0x20000000 -+/* Disable -+#define ICU0_IM0_IER_PCM_RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_PCM_RX_EN 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SHA1_HASH 0x10000000 -+/* Disable -+#define ICU0_IM0_IER_SHA1_HASH_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SHA1_HASH_EN 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_AES_AES 0x08000000 -+/* Disable -+#define ICU0_IM0_IER_AES_AES_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_AES_AES_EN 0x08000000 -+/** SSC Frame Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_F 0x00020000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_F_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_F_EN 0x00020000 -+/** SSC Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_E 0x00010000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_E_EN 0x00010000 -+/** SSC Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_R 0x00008000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_R_EN 0x00008000 -+/** SSC Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_SSC0_T 0x00004000 -+/* Disable -+#define ICU0_IM0_IER_SSC0_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_SSC0_T_EN 0x00004000 -+/** I2C Peripheral Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_I2C_P_INT 0x00002000 -+/* Disable -+#define ICU0_IM0_IER_I2C_I2C_P_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_I2C_P_INT_EN 0x00002000 -+/** I2C Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT 0x00001000 -+/* Disable -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_I2C_ERR_INT_EN 0x00001000 -+/** I2C Burst Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_BREQ_INT 0x00000800 -+/* Disable -+#define ICU0_IM0_IER_I2C_BREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_BREQ_INT_EN 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_LBREQ_INT 0x00000400 -+/* Disable -+#define ICU0_IM0_IER_I2C_LBREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_LBREQ_INT_EN 0x00000400 -+/** I2C Single Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_SREQ_INT 0x00000200 -+/* Disable -+#define ICU0_IM0_IER_I2C_SREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_SREQ_INT_EN 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_I2C_LSREQ_INT 0x00000100 -+/* Disable -+#define ICU0_IM0_IER_I2C_LSREQ_INT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_I2C_LSREQ_INT_EN 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB1_TIR 0x00000010 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB1_TIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB1_TIR_EN 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB1_RIR 0x00000008 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB1_RIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB1_RIR_EN 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB0_TIR 0x00000004 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB0_TIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB0_TIR_EN 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_MB0_RIR 0x00000002 -+/* Disable -+#define ICU0_IM0_IER_HOST_MB0_RIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_MB0_RIR_EN 0x00000002 -+/** HOST IF Event Interrupt -+ Interrupt enable bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IER_HOST_EIR 0x00000001 -+/* Disable -+#define ICU0_IM0_IER_HOST_EIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM0_IER_HOST_EIR_EN 0x00000001 -+ -+/* Fields of "IM0 Interrupt Output Status Register" */ -+/** PCM Transmit Crash Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH 0x80000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_HW2_CRASH_INTOCC 0x80000000 -+/** PCM Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_TX 0x40000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_TX_INTOCC 0x40000000 -+/** PCM Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_PCM_RX 0x20000000 -+/* Nothing -+#define ICU0_IM0_IOSR_PCM_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_PCM_RX_INTOCC 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SHA1_HASH 0x10000000 -+/* Nothing -+#define ICU0_IM0_IOSR_SHA1_HASH_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SHA1_HASH_INTOCC 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_AES_AES 0x08000000 -+/* Nothing -+#define ICU0_IM0_IOSR_AES_AES_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_AES_AES_INTOCC 0x08000000 -+/** SSC Frame Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_F 0x00020000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_F_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_F_INTOCC 0x00020000 -+/** SSC Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_E 0x00010000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_E_INTOCC 0x00010000 -+/** SSC Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_R 0x00008000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_R_INTOCC 0x00008000 -+/** SSC Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_SSC0_T 0x00004000 -+/* Nothing -+#define ICU0_IM0_IOSR_SSC0_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_SSC0_T_INTOCC 0x00004000 -+/** I2C Peripheral Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT 0x00002000 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_I2C_P_INT_INTOCC 0x00002000 -+/** I2C Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT 0x00001000 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_I2C_ERR_INT_INTOCC 0x00001000 -+/** I2C Burst Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_BREQ_INT 0x00000800 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_BREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_BREQ_INT_INTOCC 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT 0x00000400 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_LBREQ_INT_INTOCC 0x00000400 -+/** I2C Single Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_SREQ_INT 0x00000200 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_SREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_SREQ_INT_INTOCC 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT 0x00000100 -+/* Nothing -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_I2C_LSREQ_INT_INTOCC 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB1_TIR 0x00000010 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB1_TIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB1_TIR_INTOCC 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB1_RIR 0x00000008 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB1_RIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB1_RIR_INTOCC 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB0_TIR 0x00000004 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB0_TIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB0_TIR_INTOCC 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_MB0_RIR 0x00000002 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_MB0_RIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_MB0_RIR_INTOCC 0x00000002 -+/** HOST IF Event Interrupt -+ Masked interrupt bit for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IOSR_HOST_EIR 0x00000001 -+/* Nothing -+#define ICU0_IM0_IOSR_HOST_EIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM0_IOSR_HOST_EIR_INTOCC 0x00000001 -+ -+/* Fields of "IM0 Interrupt Request Set Register" */ -+/** PCM Transmit Crash Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_HW2_CRASH 0x80000000 -+/** PCM Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_TX 0x40000000 -+/** PCM Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_PCM_RX 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SHA1_HASH 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_AES_AES 0x08000000 -+/** SSC Frame Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_F 0x00020000 -+/** SSC Error Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_E 0x00010000 -+/** SSC Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_R 0x00008000 -+/** SSC Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_SSC0_T 0x00004000 -+/** I2C Peripheral Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_I2C_P_INT 0x00002000 -+/** I2C Error Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_I2C_ERR_INT 0x00001000 -+/** I2C Burst Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_BREQ_INT 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_LBREQ_INT 0x00000400 -+/** I2C Single Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_SREQ_INT 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_I2C_LSREQ_INT 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB1_TIR 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB1_RIR 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB0_TIR 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_MB0_RIR 0x00000002 -+/** HOST IF Event Interrupt -+ Software control for the corresponding bit in the IM0_ISR register. */ -+#define ICU0_IM0_IRSR_HOST_EIR 0x00000001 -+ -+/* Fields of "IM0 Interrupt Mode Register" */ -+/** PCM Transmit Crash Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_HW2_CRASH 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_HW2_CRASH_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_HW2_CRASH_DIR 0x80000000 -+/** PCM Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_TX 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_TX_DIR 0x40000000 -+/** PCM Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_PCM_RX 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_PCM_RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_PCM_RX_DIR 0x20000000 -+/** Secure Hash Algorithm Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SHA1_HASH 0x10000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SHA1_HASH_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SHA1_HASH_DIR 0x10000000 -+/** Advanced Encryption Standard Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_AES_AES 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_AES_AES_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_AES_AES_DIR 0x08000000 -+/** SSC Frame Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_F 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_F_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_F_DIR 0x00020000 -+/** SSC Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_E 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_E_DIR 0x00010000 -+/** SSC Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_R 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_R_DIR 0x00008000 -+/** SSC Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_SSC0_T 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_SSC0_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_SSC0_T_DIR 0x00004000 -+/** I2C Peripheral Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_P_INT 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_I2C_P_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_P_INT_DIR 0x00002000 -+/** I2C Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_I2C_ERR_INT_DIR 0x00001000 -+/** I2C Burst Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_BREQ_INT 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_BREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_BREQ_INT_DIR 0x00000800 -+/** I2C Last Burst Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_LBREQ_INT 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_LBREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_LBREQ_INT_DIR 0x00000400 -+/** I2C Single Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_SREQ_INT 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_SREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_SREQ_INT_DIR 0x00000200 -+/** I2C Last Single Data Transfer Request -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_I2C_LSREQ_INT 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_I2C_LSREQ_INT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_I2C_LSREQ_INT_DIR 0x00000100 -+/** HOST IF Mailbox1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_TIR 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB1_TIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_TIR_DIR 0x00000010 -+/** HOST IF Mailbox1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_RIR 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB1_RIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB1_RIR_DIR 0x00000008 -+/** HOST IF Mailbox0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_TIR 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB0_TIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_TIR_DIR 0x00000004 -+/** HOST IF Mailbox0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_RIR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_MB0_RIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_MB0_RIR_DIR 0x00000002 -+/** HOST IF Event Interrupt -+ Type of interrupt. */ -+#define ICU0_IM0_IMR_HOST_EIR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM0_IMR_HOST_EIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM0_IMR_HOST_EIR_DIR 0x00000001 -+ -+/* Fields of "IM1 Interrupt Status Register" */ -+/** Crossbar Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_XBAR_ERROR 0x80000000 -+/* Nothing -+#define ICU0_IM1_ISR_XBAR_ERROR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_XBAR_ERROR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_XBAR_ERROR_INTOCC 0x80000000 -+/** DDR Controller Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_DDR 0x40000000 -+/* Nothing -+#define ICU0_IM1_ISR_DDR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_DDR_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_DDR_INTOCC 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_BCU0 0x20000000 -+/* Nothing -+#define ICU0_IM1_ISR_BCU0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_BCU0_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_BCU0_INTOCC 0x20000000 -+/** SBIU interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SBIU0 0x08000000 -+/* Nothing -+#define ICU0_IM1_ISR_SBIU0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SBIU0_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SBIU0_INTOCC 0x08000000 -+/** Watchdog Prewarning Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_WDT_PIR 0x02000000 -+/* Nothing -+#define ICU0_IM1_ISR_WDT_PIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_WDT_PIR_INTACK 0x02000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_WDT_PIR_INTOCC 0x02000000 -+/** Watchdog Access Error Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_WDT_AEIR 0x01000000 -+/* Nothing -+#define ICU0_IM1_ISR_WDT_AEIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_WDT_AEIR_INTACK 0x01000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_WDT_AEIR_INTOCC 0x01000000 -+/** SYS GPE Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SYS_GPE 0x00200000 -+/* Nothing -+#define ICU0_IM1_ISR_SYS_GPE_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SYS_GPE_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SYS_GPE_INTOCC 0x00200000 -+/** SYS1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_SYS1 0x00100000 -+/* Nothing -+#define ICU0_IM1_ISR_SYS1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_SYS1_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_SYS1_INTOCC 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_RX 0x00020000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_RX_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_RX_INTOCC 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_TX 0x00010000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_TX_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_TX_INTOCC 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_PMA_200M 0x00008000 -+/* Nothing -+#define ICU0_IM1_ISR_PMA_200M_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_PMA_200M_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_PMA_200M_INTOCC 0x00008000 -+/** Time of Day -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_TOD 0x00004000 -+/* Nothing -+#define ICU0_IM1_ISR_TOD_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_TOD_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_TOD_INTOCC 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSC_ROOT 0x00002000 -+/* Nothing -+#define ICU0_IM1_ISR_FSC_ROOT_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSC_ROOT_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSC_ROOT_INTOCC 0x00002000 -+/** FSC Timer Interrupt 1 -+ Delayed version of FSCROOT. This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP1 0x00001000 -+/* Nothing -+#define ICU0_IM1_ISR_FSCT_CMP1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP1_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSCT_CMP1_INTOCC 0x00001000 -+/** FSC Timer Interrupt 0 -+ Delayed version of FSCROOT. This bit is a direct interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP0 0x00000800 -+/* Nothing -+#define ICU0_IM1_ISR_FSCT_CMP0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSCT_CMP0_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSCT_CMP0_INTOCC 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_FSC_BKP 0x00000400 -+/* Nothing -+#define ICU0_IM1_ISR_FSC_BKP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_FSC_BKP_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_FSC_BKP_INTOCC 0x00000400 -+/** External Interrupt from GPIO P4 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P4 0x00000100 -+/* Nothing -+#define ICU0_IM1_ISR_P4_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P4_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P4_INTOCC 0x00000100 -+/** External Interrupt from GPIO P3 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P3 0x00000080 -+/* Nothing -+#define ICU0_IM1_ISR_P3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P3_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P3_INTOCC 0x00000080 -+/** External Interrupt from GPIO P2 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P2 0x00000040 -+/* Nothing -+#define ICU0_IM1_ISR_P2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P2_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P2_INTOCC 0x00000040 -+/** External Interrupt from GPIO P1 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P1 0x00000020 -+/* Nothing -+#define ICU0_IM1_ISR_P1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P1_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P1_INTOCC 0x00000020 -+/** External Interrupt from GPIO P0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_P0 0x00000010 -+/* Nothing -+#define ICU0_IM1_ISR_P0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_P0_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_P0_INTOCC 0x00000010 -+/** EBU Serial Flash Busy -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY 0x00000004 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_BUSY_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_BUSY_INTOCC 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR 0x00000002 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_COVERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_COVERR_INTOCC 0x00000002 -+/** EBU Serial Flash Command Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR 0x00000001 -+/* Nothing -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_ISR_EBU_SF_CMDERR_INTOCC 0x00000001 -+ -+/* Fields of "IM1 Interrupt Enable Register" */ -+/** Crossbar Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_XBAR_ERROR 0x80000000 -+/* Disable -+#define ICU0_IM1_IER_XBAR_ERROR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_XBAR_ERROR_EN 0x80000000 -+/** DDR Controller Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_DDR 0x40000000 -+/* Disable -+#define ICU0_IM1_IER_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_DDR_EN 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_BCU0 0x20000000 -+/* Disable -+#define ICU0_IM1_IER_BCU0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_BCU0_EN 0x20000000 -+/** SBIU interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SBIU0 0x08000000 -+/* Disable -+#define ICU0_IM1_IER_SBIU0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SBIU0_EN 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_WDT_PIR 0x02000000 -+/* Disable -+#define ICU0_IM1_IER_WDT_PIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_WDT_PIR_EN 0x02000000 -+/** Watchdog Access Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_WDT_AEIR 0x01000000 -+/* Disable -+#define ICU0_IM1_IER_WDT_AEIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_WDT_AEIR_EN 0x01000000 -+/** SYS GPE Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SYS_GPE 0x00200000 -+/* Disable -+#define ICU0_IM1_IER_SYS_GPE_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SYS_GPE_EN 0x00200000 -+/** SYS1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_SYS1 0x00100000 -+/* Disable -+#define ICU0_IM1_IER_SYS1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_SYS1_EN 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_RX 0x00020000 -+/* Disable -+#define ICU0_IM1_IER_PMA_RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_RX_EN 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_TX 0x00010000 -+/* Disable -+#define ICU0_IM1_IER_PMA_TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_TX_EN 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_PMA_200M 0x00008000 -+/* Disable -+#define ICU0_IM1_IER_PMA_200M_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_PMA_200M_EN 0x00008000 -+/** Time of Day -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_TOD 0x00004000 -+/* Disable -+#define ICU0_IM1_IER_TOD_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_TOD_EN 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSC_ROOT 0x00002000 -+/* Disable -+#define ICU0_IM1_IER_FSC_ROOT_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSC_ROOT_EN 0x00002000 -+/** FSC Timer Interrupt 1 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSCT_CMP1 0x00001000 -+/* Disable -+#define ICU0_IM1_IER_FSCT_CMP1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSCT_CMP1_EN 0x00001000 -+/** FSC Timer Interrupt 0 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSCT_CMP0 0x00000800 -+/* Disable -+#define ICU0_IM1_IER_FSCT_CMP0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSCT_CMP0_EN 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_FSC_BKP 0x00000400 -+/* Disable -+#define ICU0_IM1_IER_FSC_BKP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_FSC_BKP_EN 0x00000400 -+/** External Interrupt from GPIO P4 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P4 0x00000100 -+/* Disable -+#define ICU0_IM1_IER_P4_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P4_EN 0x00000100 -+/** External Interrupt from GPIO P3 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P3 0x00000080 -+/* Disable -+#define ICU0_IM1_IER_P3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P3_EN 0x00000080 -+/** External Interrupt from GPIO P2 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P2 0x00000040 -+/* Disable -+#define ICU0_IM1_IER_P2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P2_EN 0x00000040 -+/** External Interrupt from GPIO P1 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P1 0x00000020 -+/* Disable -+#define ICU0_IM1_IER_P1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P1_EN 0x00000020 -+/** External Interrupt from GPIO P0 -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_P0 0x00000010 -+/* Disable -+#define ICU0_IM1_IER_P0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_P0_EN 0x00000010 -+/** EBU Serial Flash Busy -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_BUSY 0x00000004 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_BUSY_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_BUSY_EN 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_COVERR 0x00000002 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_COVERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_COVERR_EN 0x00000002 -+/** EBU Serial Flash Command Error -+ Interrupt enable bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IER_EBU_SF_CMDERR 0x00000001 -+/* Disable -+#define ICU0_IM1_IER_EBU_SF_CMDERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM1_IER_EBU_SF_CMDERR_EN 0x00000001 -+ -+/* Fields of "IM1 Interrupt Output Status Register" */ -+/** Crossbar Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_XBAR_ERROR 0x80000000 -+/* Nothing -+#define ICU0_IM1_IOSR_XBAR_ERROR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_XBAR_ERROR_INTOCC 0x80000000 -+/** DDR Controller Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_DDR 0x40000000 -+/* Nothing -+#define ICU0_IM1_IOSR_DDR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_DDR_INTOCC 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_BCU0 0x20000000 -+/* Nothing -+#define ICU0_IM1_IOSR_BCU0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_BCU0_INTOCC 0x20000000 -+/** SBIU interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SBIU0 0x08000000 -+/* Nothing -+#define ICU0_IM1_IOSR_SBIU0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SBIU0_INTOCC 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_WDT_PIR 0x02000000 -+/* Nothing -+#define ICU0_IM1_IOSR_WDT_PIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_WDT_PIR_INTOCC 0x02000000 -+/** Watchdog Access Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_WDT_AEIR 0x01000000 -+/* Nothing -+#define ICU0_IM1_IOSR_WDT_AEIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_WDT_AEIR_INTOCC 0x01000000 -+/** SYS GPE Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SYS_GPE 0x00200000 -+/* Nothing -+#define ICU0_IM1_IOSR_SYS_GPE_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SYS_GPE_INTOCC 0x00200000 -+/** SYS1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_SYS1 0x00100000 -+/* Nothing -+#define ICU0_IM1_IOSR_SYS1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_SYS1_INTOCC 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_RX 0x00020000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_RX_INTOCC 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_TX 0x00010000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_TX_INTOCC 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_PMA_200M 0x00008000 -+/* Nothing -+#define ICU0_IM1_IOSR_PMA_200M_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_PMA_200M_INTOCC 0x00008000 -+/** Time of Day -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_TOD 0x00004000 -+/* Nothing -+#define ICU0_IM1_IOSR_TOD_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_TOD_INTOCC 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSC_ROOT 0x00002000 -+/* Nothing -+#define ICU0_IM1_IOSR_FSC_ROOT_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSC_ROOT_INTOCC 0x00002000 -+/** FSC Timer Interrupt 1 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSCT_CMP1 0x00001000 -+/* Nothing -+#define ICU0_IM1_IOSR_FSCT_CMP1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSCT_CMP1_INTOCC 0x00001000 -+/** FSC Timer Interrupt 0 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSCT_CMP0 0x00000800 -+/* Nothing -+#define ICU0_IM1_IOSR_FSCT_CMP0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSCT_CMP0_INTOCC 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_FSC_BKP 0x00000400 -+/* Nothing -+#define ICU0_IM1_IOSR_FSC_BKP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_FSC_BKP_INTOCC 0x00000400 -+/** External Interrupt from GPIO P4 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P4 0x00000100 -+/* Nothing -+#define ICU0_IM1_IOSR_P4_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P4_INTOCC 0x00000100 -+/** External Interrupt from GPIO P3 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P3 0x00000080 -+/* Nothing -+#define ICU0_IM1_IOSR_P3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P3_INTOCC 0x00000080 -+/** External Interrupt from GPIO P2 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P2 0x00000040 -+/* Nothing -+#define ICU0_IM1_IOSR_P2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P2_INTOCC 0x00000040 -+/** External Interrupt from GPIO P1 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P1 0x00000020 -+/* Nothing -+#define ICU0_IM1_IOSR_P1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P1_INTOCC 0x00000020 -+/** External Interrupt from GPIO P0 -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_P0 0x00000010 -+/* Nothing -+#define ICU0_IM1_IOSR_P0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_P0_INTOCC 0x00000010 -+/** EBU Serial Flash Busy -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_BUSY 0x00000004 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_BUSY_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_BUSY_INTOCC 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_COVERR 0x00000002 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_COVERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_COVERR_INTOCC 0x00000002 -+/** EBU Serial Flash Command Error -+ Masked interrupt bit for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR 0x00000001 -+/* Nothing -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM1_IOSR_EBU_SF_CMDERR_INTOCC 0x00000001 -+ -+/* Fields of "IM1 Interrupt Request Set Register" */ -+/** Crossbar Error Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_XBAR_ERROR 0x80000000 -+/** DDR Controller Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_DDR 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_BCU0 0x20000000 -+/** SBIU interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SBIU0 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_WDT_PIR 0x02000000 -+/** Watchdog Access Error Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_WDT_AEIR 0x01000000 -+/** SYS GPE Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SYS_GPE 0x00200000 -+/** SYS1 Interrupt -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_SYS1 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_RX 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_TX 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_PMA_200M 0x00008000 -+/** Time of Day -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_TOD 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSC_ROOT 0x00002000 -+/** FSC Timer Interrupt 1 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSCT_CMP1 0x00001000 -+/** FSC Timer Interrupt 0 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSCT_CMP0 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_FSC_BKP 0x00000400 -+/** External Interrupt from GPIO P4 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P4 0x00000100 -+/** External Interrupt from GPIO P3 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P3 0x00000080 -+/** External Interrupt from GPIO P2 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P2 0x00000040 -+/** External Interrupt from GPIO P1 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P1 0x00000020 -+/** External Interrupt from GPIO P0 -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_P0 0x00000010 -+/** EBU Serial Flash Busy -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_BUSY 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_COVERR 0x00000002 -+/** EBU Serial Flash Command Error -+ Software control for the corresponding bit in the IM1_ISR register. */ -+#define ICU0_IM1_IRSR_EBU_SF_CMDERR 0x00000001 -+ -+/* Fields of "IM1 Interrupt Mode Register" */ -+/** Crossbar Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_XBAR_ERROR 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_XBAR_ERROR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_XBAR_ERROR_DIR 0x80000000 -+/** DDR Controller Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_DDR 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_DDR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_DDR_DIR 0x40000000 -+/** FPI Bus Control Unit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_BCU0 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_BCU0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_BCU0_DIR 0x20000000 -+/** SBIU interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SBIU0 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SBIU0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SBIU0_DIR 0x08000000 -+/** Watchdog Prewarning Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_WDT_PIR 0x02000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_WDT_PIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_WDT_PIR_DIR 0x02000000 -+/** Watchdog Access Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_WDT_AEIR 0x01000000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_WDT_AEIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_WDT_AEIR_DIR 0x01000000 -+/** SYS GPE Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SYS_GPE 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SYS_GPE_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SYS_GPE_DIR 0x00200000 -+/** SYS1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_SYS1 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_SYS1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_SYS1_DIR 0x00100000 -+/** PMA Interrupt from IntNode of the RX Clk Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_RX 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_RX_DIR 0x00020000 -+/** PMA Interrupt from IntNode of the TX Clk Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_TX 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_TX_DIR 0x00010000 -+/** PMA Interrupt from IntNode of the 200MHz Domain -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_PMA_200M 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_PMA_200M_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_PMA_200M_DIR 0x00008000 -+/** Time of Day -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_TOD 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_TOD_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_TOD_DIR 0x00004000 -+/** 8kHz root interrupt derived from GPON interface -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSC_ROOT 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSC_ROOT_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSC_ROOT_DIR 0x00002000 -+/** FSC Timer Interrupt 1 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP1 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSCT_CMP1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP1_DIR 0x00001000 -+/** FSC Timer Interrupt 0 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP0 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSCT_CMP0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSCT_CMP0_DIR 0x00000800 -+/** 8kHz backup interrupt derived from core-PLL -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_FSC_BKP 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_FSC_BKP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_FSC_BKP_DIR 0x00000400 -+/** External Interrupt from GPIO P4 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P4 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P4_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P4_DIR 0x00000100 -+/** External Interrupt from GPIO P3 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P3 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P3_DIR 0x00000080 -+/** External Interrupt from GPIO P2 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P2 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P2_DIR 0x00000040 -+/** External Interrupt from GPIO P1 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P1 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P1_DIR 0x00000020 -+/** External Interrupt from GPIO P0 -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_P0 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_P0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_P0_DIR 0x00000010 -+/** EBU Serial Flash Busy -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_BUSY 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_BUSY_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_BUSY_DIR 0x00000004 -+/** EBU Serial Flash Command Overwrite Error -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_COVERR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_COVERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_COVERR_DIR 0x00000002 -+/** EBU Serial Flash Command Error -+ Type of interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_CMDERR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM1_IMR_EBU_SF_CMDERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM1_IMR_EBU_SF_CMDERR_DIR 0x00000001 -+ -+/* Fields of "IM2 Interrupt Status Register" */ -+/** EIM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_EIM 0x80000000 -+/* Nothing -+#define ICU0_IM2_ISR_EIM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_EIM_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_EIM_INTOCC 0x80000000 -+/** GTC Upstream Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_GTC_US 0x40000000 -+/* Nothing -+#define ICU0_IM2_ISR_GTC_US_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_GTC_US_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_GTC_US_INTOCC 0x40000000 -+/** GTC Downstream Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_GTC_DS 0x20000000 -+/* Nothing -+#define ICU0_IM2_ISR_GTC_DS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_GTC_DS_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_GTC_DS_INTOCC 0x20000000 -+/** TBM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_TBM 0x00400000 -+/* Nothing -+#define ICU0_IM2_ISR_TBM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_TBM_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_TBM_INTOCC 0x00400000 -+/** Dispatcher Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_DISP 0x00200000 -+/* Nothing -+#define ICU0_IM2_ISR_DISP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_DISP_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_DISP_INTOCC 0x00200000 -+/** CONFIG Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_CONFIG 0x00100000 -+/* Nothing -+#define ICU0_IM2_ISR_CONFIG_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_CONFIG_INTOCC 0x00100000 -+/** CONFIG Break Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK 0x00080000 -+/* Nothing -+#define ICU0_IM2_ISR_CONFIG_BREAK_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_CONFIG_BREAK_INTOCC 0x00080000 -+/** OCTRLC Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLC 0x00040000 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLC_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLC_INTOCC 0x00040000 -+/** ICTRLC 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC1 0x00020000 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLC1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC1_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLC1_INTOCC 0x00020000 -+/** ICTRLC 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC0 0x00010000 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLC0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLC0_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLC0_INTOCC 0x00010000 -+/** LINK 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_LINK1 0x00004000 -+/* Nothing -+#define ICU0_IM2_ISR_LINK1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_LINK1_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_LINK1_INTOCC 0x00004000 -+/** TMU Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_TMU 0x00001000 -+/* Nothing -+#define ICU0_IM2_ISR_TMU_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_TMU_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_TMU_INTOCC 0x00001000 -+/** FSQM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_FSQM 0x00000800 -+/* Nothing -+#define ICU0_IM2_ISR_FSQM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_FSQM_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_FSQM_INTOCC 0x00000800 -+/** IQM Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_IQM 0x00000400 -+/* Nothing -+#define ICU0_IM2_ISR_IQM_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_IQM_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_IQM_INTOCC 0x00000400 -+/** OCTRLG Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLG 0x00000200 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLG_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLG_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLG_INTOCC 0x00000200 -+/** OCTRLL 3 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL3 0x00000080 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL3_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL3_INTOCC 0x00000080 -+/** OCTRLL 2 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL2 0x00000040 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL2_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL2_INTOCC 0x00000040 -+/** OCTRLL 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL1 0x00000020 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL1_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL1_INTOCC 0x00000020 -+/** OCTRLL 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL0 0x00000010 -+/* Nothing -+#define ICU0_IM2_ISR_OCTRLL0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_OCTRLL0_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_OCTRLL0_INTOCC 0x00000010 -+/** ICTRLL 3 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL3 0x00000008 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL3_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL3_INTOCC 0x00000008 -+/** ICTRLL 2 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL2 0x00000004 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL2_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL2_INTOCC 0x00000004 -+/** ICTRLL 1 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL1 0x00000002 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL1_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL1_INTOCC 0x00000002 -+/** ICTRLL 0 Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL0 0x00000001 -+/* Nothing -+#define ICU0_IM2_ISR_ICTRLL0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM2_ISR_ICTRLL0_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_ISR_ICTRLL0_INTOCC 0x00000001 -+ -+/* Fields of "IM2 Interrupt Enable Register" */ -+/** EIM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_EIM 0x80000000 -+/* Disable -+#define ICU0_IM2_IER_EIM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_EIM_EN 0x80000000 -+/** GTC Upstream Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_GTC_US 0x40000000 -+/* Disable -+#define ICU0_IM2_IER_GTC_US_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_GTC_US_EN 0x40000000 -+/** GTC Downstream Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_GTC_DS 0x20000000 -+/* Disable -+#define ICU0_IM2_IER_GTC_DS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_GTC_DS_EN 0x20000000 -+/** TBM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_TBM 0x00400000 -+/* Disable -+#define ICU0_IM2_IER_TBM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_TBM_EN 0x00400000 -+/** Dispatcher Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_DISP 0x00200000 -+/* Disable -+#define ICU0_IM2_IER_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_DISP_EN 0x00200000 -+/** CONFIG Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_CONFIG 0x00100000 -+/* Disable -+#define ICU0_IM2_IER_CONFIG_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_CONFIG_EN 0x00100000 -+/** CONFIG Break Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_CONFIG_BREAK 0x00080000 -+/* Disable -+#define ICU0_IM2_IER_CONFIG_BREAK_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_CONFIG_BREAK_EN 0x00080000 -+/** OCTRLC Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLC 0x00040000 -+/* Disable -+#define ICU0_IM2_IER_OCTRLC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLC_EN 0x00040000 -+/** ICTRLC 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLC1 0x00020000 -+/* Disable -+#define ICU0_IM2_IER_ICTRLC1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLC1_EN 0x00020000 -+/** ICTRLC 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLC0 0x00010000 -+/* Disable -+#define ICU0_IM2_IER_ICTRLC0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLC0_EN 0x00010000 -+/** LINK 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_LINK1 0x00004000 -+/* Disable -+#define ICU0_IM2_IER_LINK1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_LINK1_EN 0x00004000 -+/** TMU Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_TMU 0x00001000 -+/* Disable -+#define ICU0_IM2_IER_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_TMU_EN 0x00001000 -+/** FSQM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_FSQM 0x00000800 -+/* Disable -+#define ICU0_IM2_IER_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_FSQM_EN 0x00000800 -+/** IQM Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_IQM 0x00000400 -+/* Disable -+#define ICU0_IM2_IER_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_IQM_EN 0x00000400 -+/** OCTRLG Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLG 0x00000200 -+/* Disable -+#define ICU0_IM2_IER_OCTRLG_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLG_EN 0x00000200 -+/** OCTRLL 3 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL3 0x00000080 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL3_EN 0x00000080 -+/** OCTRLL 2 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL2 0x00000040 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL2_EN 0x00000040 -+/** OCTRLL 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL1 0x00000020 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL1_EN 0x00000020 -+/** OCTRLL 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_OCTRLL0 0x00000010 -+/* Disable -+#define ICU0_IM2_IER_OCTRLL0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_OCTRLL0_EN 0x00000010 -+/** ICTRLL 3 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL3 0x00000008 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL3_EN 0x00000008 -+/** ICTRLL 2 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL2 0x00000004 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL2_EN 0x00000004 -+/** ICTRLL 1 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL1 0x00000002 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL1_EN 0x00000002 -+/** ICTRLL 0 Interrupt -+ Interrupt enable bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IER_ICTRLL0 0x00000001 -+/* Disable -+#define ICU0_IM2_IER_ICTRLL0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM2_IER_ICTRLL0_EN 0x00000001 -+ -+/* Fields of "IM2 Interrupt Output Status Register" */ -+/** EIM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_EIM 0x80000000 -+/* Nothing -+#define ICU0_IM2_IOSR_EIM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_EIM_INTOCC 0x80000000 -+/** GTC Upstream Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_GTC_US 0x40000000 -+/* Nothing -+#define ICU0_IM2_IOSR_GTC_US_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_GTC_US_INTOCC 0x40000000 -+/** GTC Downstream Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_GTC_DS 0x20000000 -+/* Nothing -+#define ICU0_IM2_IOSR_GTC_DS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_GTC_DS_INTOCC 0x20000000 -+/** TBM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_TBM 0x00400000 -+/* Nothing -+#define ICU0_IM2_IOSR_TBM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_TBM_INTOCC 0x00400000 -+/** Dispatcher Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_DISP 0x00200000 -+/* Nothing -+#define ICU0_IM2_IOSR_DISP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_DISP_INTOCC 0x00200000 -+/** CONFIG Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_CONFIG 0x00100000 -+/* Nothing -+#define ICU0_IM2_IOSR_CONFIG_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_CONFIG_INTOCC 0x00100000 -+/** CONFIG Break Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_CONFIG_BREAK 0x00080000 -+/* Nothing -+#define ICU0_IM2_IOSR_CONFIG_BREAK_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_CONFIG_BREAK_INTOCC 0x00080000 -+/** OCTRLC Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLC 0x00040000 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLC_INTOCC 0x00040000 -+/** ICTRLC 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLC1 0x00020000 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLC1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLC1_INTOCC 0x00020000 -+/** ICTRLC 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLC0 0x00010000 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLC0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLC0_INTOCC 0x00010000 -+/** LINK 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_LINK1 0x00004000 -+/* Nothing -+#define ICU0_IM2_IOSR_LINK1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_LINK1_INTOCC 0x00004000 -+/** TMU Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_TMU 0x00001000 -+/* Nothing -+#define ICU0_IM2_IOSR_TMU_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_TMU_INTOCC 0x00001000 -+/** FSQM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_FSQM 0x00000800 -+/* Nothing -+#define ICU0_IM2_IOSR_FSQM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_FSQM_INTOCC 0x00000800 -+/** IQM Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_IQM 0x00000400 -+/* Nothing -+#define ICU0_IM2_IOSR_IQM_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_IQM_INTOCC 0x00000400 -+/** OCTRLG Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLG 0x00000200 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLG_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLG_INTOCC 0x00000200 -+/** OCTRLL 3 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL3 0x00000080 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL3_INTOCC 0x00000080 -+/** OCTRLL 2 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL2 0x00000040 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL2_INTOCC 0x00000040 -+/** OCTRLL 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL1 0x00000020 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL1_INTOCC 0x00000020 -+/** OCTRLL 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_OCTRLL0 0x00000010 -+/* Nothing -+#define ICU0_IM2_IOSR_OCTRLL0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_OCTRLL0_INTOCC 0x00000010 -+/** ICTRLL 3 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL3 0x00000008 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL3_INTOCC 0x00000008 -+/** ICTRLL 2 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL2 0x00000004 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL2_INTOCC 0x00000004 -+/** ICTRLL 1 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL1 0x00000002 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL1_INTOCC 0x00000002 -+/** ICTRLL 0 Interrupt -+ Masked interrupt bit for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IOSR_ICTRLL0 0x00000001 -+/* Nothing -+#define ICU0_IM2_IOSR_ICTRLL0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM2_IOSR_ICTRLL0_INTOCC 0x00000001 -+ -+/* Fields of "IM2 Interrupt Request Set Register" */ -+/** EIM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_EIM 0x80000000 -+/** GTC Upstream Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_GTC_US 0x40000000 -+/** GTC Downstream Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_GTC_DS 0x20000000 -+/** TBM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_TBM 0x00400000 -+/** Dispatcher Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_DISP 0x00200000 -+/** CONFIG Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_CONFIG 0x00100000 -+/** CONFIG Break Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_CONFIG_BREAK 0x00080000 -+/** OCTRLC Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLC 0x00040000 -+/** ICTRLC 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLC1 0x00020000 -+/** ICTRLC 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLC0 0x00010000 -+/** LINK 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_LINK1 0x00004000 -+/** TMU Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_TMU 0x00001000 -+/** FSQM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_FSQM 0x00000800 -+/** IQM Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_IQM 0x00000400 -+/** OCTRLG Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLG 0x00000200 -+/** OCTRLL 3 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL3 0x00000080 -+/** OCTRLL 2 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL2 0x00000040 -+/** OCTRLL 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL1 0x00000020 -+/** OCTRLL 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_OCTRLL0 0x00000010 -+/** ICTRLL 3 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL3 0x00000008 -+/** ICTRLL 2 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL2 0x00000004 -+/** ICTRLL 1 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL1 0x00000002 -+/** ICTRLL 0 Interrupt -+ Software control for the corresponding bit in the IM2_ISR register. */ -+#define ICU0_IM2_IRSR_ICTRLL0 0x00000001 -+ -+/* Fields of "IM2 Interrupt Mode Register" */ -+/** EIM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_EIM 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_EIM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_EIM_DIR 0x80000000 -+/** GTC Upstream Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_GTC_US 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_GTC_US_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_GTC_US_DIR 0x40000000 -+/** GTC Downstream Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_GTC_DS 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_GTC_DS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_GTC_DS_DIR 0x20000000 -+/** TBM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_TBM 0x00400000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_TBM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_TBM_DIR 0x00400000 -+/** Dispatcher Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_DISP 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_DISP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_DISP_DIR 0x00200000 -+/** CONFIG Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_CONFIG 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_CONFIG_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_DIR 0x00100000 -+/** CONFIG Break Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_BREAK 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_CONFIG_BREAK_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_CONFIG_BREAK_DIR 0x00080000 -+/** OCTRLC Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLC 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLC_DIR 0x00040000 -+/** ICTRLC 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC1 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLC1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC1_DIR 0x00020000 -+/** ICTRLC 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC0 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLC0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLC0_DIR 0x00010000 -+/** LINK 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_LINK1 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_LINK1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_LINK1_DIR 0x00004000 -+/** TMU Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_TMU 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_TMU_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_TMU_DIR 0x00001000 -+/** FSQM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_FSQM 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_FSQM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_FSQM_DIR 0x00000800 -+/** IQM Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_IQM 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_IQM_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_IQM_DIR 0x00000400 -+/** OCTRLG Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLG 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLG_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLG_DIR 0x00000200 -+/** OCTRLL 3 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL3 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL3_DIR 0x00000080 -+/** OCTRLL 2 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL2 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL2_DIR 0x00000040 -+/** OCTRLL 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL1 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL1_DIR 0x00000020 -+/** OCTRLL 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL0 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_OCTRLL0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_OCTRLL0_DIR 0x00000010 -+/** ICTRLL 3 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL3 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL3_DIR 0x00000008 -+/** ICTRLL 2 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL2 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL2_DIR 0x00000004 -+/** ICTRLL 1 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL1 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL1_DIR 0x00000002 -+/** ICTRLL 0 Interrupt -+ Type of interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL0 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM2_IMR_ICTRLL0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM2_IMR_ICTRLL0_DIR 0x00000001 -+ -+/* Fields of "IM3 Interrupt Status Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1GP 0x80000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1GP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1GP_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1GP_INTOCC 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1RX 0x40000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1RX_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1RX_INTOCC 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1TX 0x20000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_1TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_1TX_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_1TX_INTOCC 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2GP 0x10000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2GP_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2GP_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2GP_INTOCC 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2RX 0x08000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2RX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2RX_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2RX_INTOCC 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2TX 0x04000000 -+/* Nothing -+#define ICU0_IM3_ISR_DFEV0_2TX_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_DFEV0_2TX_INTACK 0x04000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_DFEV0_2TX_INTOCC 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3B 0x00200000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC3B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3B_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC3B_INTOCC 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3A 0x00100000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC3A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC3A_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC3A_INTOCC 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2B 0x00080000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC2B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2B_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC2B_INTOCC 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2A 0x00040000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC2A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC2A_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC2A_INTOCC 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1B 0x00020000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC1B_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1B_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC1B_INTOCC 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1A 0x00010000 -+/* Nothing -+#define ICU0_IM3_ISR_GPTC_TC1A_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_GPTC_TC1A_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_GPTC_TC1A_INTOCC 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_SFC 0x00008000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_SFC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_SFC_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_SFC_INTOCC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_MS 0x00004000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_MS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_MS_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_MS_INTOCC 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABDET 0x00002000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_ABDET_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABDET_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_ABDET_INTOCC 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABST 0x00001000 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_ABST_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_ABST_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_ABST_INTOCC 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_TB 0x00000800 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_TB_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_TB_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_TB_INTOCC 0x00000800 -+/** ASC1 Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_E 0x00000400 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_E_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_E_INTOCC 0x00000400 -+/** ASC1 Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_R 0x00000200 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_R_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_R_INTOCC 0x00000200 -+/** ASC1 Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC1_T 0x00000100 -+/* Nothing -+#define ICU0_IM3_ISR_ASC1_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC1_T_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC1_T_INTOCC 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_SFC 0x00000080 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_SFC_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_SFC_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_SFC_INTOCC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_MS 0x00000040 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_MS_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_MS_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_MS_INTOCC 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABDET 0x00000020 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_ABDET_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABDET_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_ABDET_INTOCC 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABST 0x00000010 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_ABST_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_ABST_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_ABST_INTOCC 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_TB 0x00000008 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_TB_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_TB_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_TB_INTOCC 0x00000008 -+/** ASC0 Error Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_E 0x00000004 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_E_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_E_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_E_INTOCC 0x00000004 -+/** ASC0 Receive Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_R 0x00000002 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_R_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_R_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_R_INTOCC 0x00000002 -+/** ASC0 Transmit Interrupt -+ This bit is a direct interrupt. */ -+#define ICU0_IM3_ISR_ASC0_T 0x00000001 -+/* Nothing -+#define ICU0_IM3_ISR_ASC0_T_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM3_ISR_ASC0_T_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_ISR_ASC0_T_INTOCC 0x00000001 -+ -+/* Fields of "IM3 Interrupt Enable Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1GP 0x80000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1GP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1GP_EN 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1RX 0x40000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1RX_EN 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_1TX 0x20000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_1TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_1TX_EN 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2GP 0x10000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2GP_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2GP_EN 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2RX 0x08000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2RX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2RX_EN 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_DFEV0_2TX 0x04000000 -+/* Disable -+#define ICU0_IM3_IER_DFEV0_2TX_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_DFEV0_2TX_EN 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC3B 0x00200000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC3B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC3B_EN 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC3A 0x00100000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC3A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC3A_EN 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC2B 0x00080000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC2B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC2B_EN 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC2A 0x00040000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC2A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC2A_EN 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC1B 0x00020000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC1B_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC1B_EN 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_GPTC_TC1A 0x00010000 -+/* Disable -+#define ICU0_IM3_IER_GPTC_TC1A_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_GPTC_TC1A_EN 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_SFC 0x00008000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_SFC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_SFC_EN 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_MS 0x00004000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_MS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_MS_EN 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_ABDET 0x00002000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_ABDET_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_ABDET_EN 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_ABST 0x00001000 -+/* Disable -+#define ICU0_IM3_IER_ASC1_ABST_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_ABST_EN 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_TB 0x00000800 -+/* Disable -+#define ICU0_IM3_IER_ASC1_TB_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_TB_EN 0x00000800 -+/** ASC1 Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_E 0x00000400 -+/* Disable -+#define ICU0_IM3_IER_ASC1_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_E_EN 0x00000400 -+/** ASC1 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_R 0x00000200 -+/* Disable -+#define ICU0_IM3_IER_ASC1_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_R_EN 0x00000200 -+/** ASC1 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC1_T 0x00000100 -+/* Disable -+#define ICU0_IM3_IER_ASC1_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC1_T_EN 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_SFC 0x00000080 -+/* Disable -+#define ICU0_IM3_IER_ASC0_SFC_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_SFC_EN 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_MS 0x00000040 -+/* Disable -+#define ICU0_IM3_IER_ASC0_MS_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_MS_EN 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_ABDET 0x00000020 -+/* Disable -+#define ICU0_IM3_IER_ASC0_ABDET_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_ABDET_EN 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_ABST 0x00000010 -+/* Disable -+#define ICU0_IM3_IER_ASC0_ABST_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_ABST_EN 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_TB 0x00000008 -+/* Disable -+#define ICU0_IM3_IER_ASC0_TB_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_TB_EN 0x00000008 -+/** ASC0 Error Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_E 0x00000004 -+/* Disable -+#define ICU0_IM3_IER_ASC0_E_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_E_EN 0x00000004 -+/** ASC0 Receive Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_R 0x00000002 -+/* Disable -+#define ICU0_IM3_IER_ASC0_R_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_R_EN 0x00000002 -+/** ASC0 Transmit Interrupt -+ Interrupt enable bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IER_ASC0_T 0x00000001 -+/* Disable -+#define ICU0_IM3_IER_ASC0_T_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM3_IER_ASC0_T_EN 0x00000001 -+ -+/* Fields of "IM3 Interrupt Output Status Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1GP 0x80000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1GP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1GP_INTOCC 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1RX 0x40000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1RX_INTOCC 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_1TX 0x20000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_1TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_1TX_INTOCC 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2GP 0x10000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2GP_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2GP_INTOCC 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2RX 0x08000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2RX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2RX_INTOCC 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_DFEV0_2TX 0x04000000 -+/* Nothing -+#define ICU0_IM3_IOSR_DFEV0_2TX_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_DFEV0_2TX_INTOCC 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC3B 0x00200000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC3B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC3B_INTOCC 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC3A 0x00100000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC3A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC3A_INTOCC 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC2B 0x00080000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC2B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC2B_INTOCC 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC2A 0x00040000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC2A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC2A_INTOCC 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC1B 0x00020000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC1B_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC1B_INTOCC 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_GPTC_TC1A 0x00010000 -+/* Nothing -+#define ICU0_IM3_IOSR_GPTC_TC1A_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_GPTC_TC1A_INTOCC 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_SFC 0x00008000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_SFC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_SFC_INTOCC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_MS 0x00004000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_MS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_MS_INTOCC 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_ABDET 0x00002000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_ABDET_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_ABDET_INTOCC 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_ABST 0x00001000 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_ABST_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_ABST_INTOCC 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_TB 0x00000800 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_TB_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_TB_INTOCC 0x00000800 -+/** ASC1 Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_E 0x00000400 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_E_INTOCC 0x00000400 -+/** ASC1 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_R 0x00000200 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_R_INTOCC 0x00000200 -+/** ASC1 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC1_T 0x00000100 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC1_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC1_T_INTOCC 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_SFC 0x00000080 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_SFC_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_SFC_INTOCC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_MS 0x00000040 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_MS_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_MS_INTOCC 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_ABDET 0x00000020 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_ABDET_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_ABDET_INTOCC 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_ABST 0x00000010 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_ABST_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_ABST_INTOCC 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_TB 0x00000008 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_TB_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_TB_INTOCC 0x00000008 -+/** ASC0 Error Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_E 0x00000004 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_E_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_E_INTOCC 0x00000004 -+/** ASC0 Receive Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_R 0x00000002 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_R_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_R_INTOCC 0x00000002 -+/** ASC0 Transmit Interrupt -+ Masked interrupt bit for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IOSR_ASC0_T 0x00000001 -+/* Nothing -+#define ICU0_IM3_IOSR_ASC0_T_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM3_IOSR_ASC0_T_INTOCC 0x00000001 -+ -+/* Fields of "IM3 Interrupt Request Set Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1GP 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1RX 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_1TX 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2GP 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2RX 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_DFEV0_2TX 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC3B 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC3A 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC2B 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC2A 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC1B 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_GPTC_TC1A 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_SFC 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_MS 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_ABDET 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_ABST 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_TB 0x00000800 -+/** ASC1 Error Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_E 0x00000400 -+/** ASC1 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_R 0x00000200 -+/** ASC1 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC1_T 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_SFC 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_MS 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_ABDET 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_ABST 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_TB 0x00000008 -+/** ASC0 Error Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_E 0x00000004 -+/** ASC0 Receive Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_R 0x00000002 -+/** ASC0 Transmit Interrupt -+ Software control for the corresponding bit in the IM3_ISR register. */ -+#define ICU0_IM3_IRSR_ASC0_T 0x00000001 -+ -+/* Fields of "IM3 Interrupt Mode Register" */ -+/** DFEV0, Channel 0 General Purpose Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1GP 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1GP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1GP_DIR 0x80000000 -+/** DFEV0, Channel 0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1RX 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1RX_DIR 0x40000000 -+/** DFEV0, Channel 0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1TX 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_1TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_1TX_DIR 0x20000000 -+/** DFEV0, Channel 1 General Purpose Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2GP 0x10000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2GP_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2GP_DIR 0x10000000 -+/** DFEV0, Channel 1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2RX 0x08000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2RX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2RX_DIR 0x08000000 -+/** DFEV0, Channel 1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2TX 0x04000000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_DFEV0_2TX_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_DFEV0_2TX_DIR 0x04000000 -+/** GPTC Timer/Counter 3B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3B 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC3B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3B_DIR 0x00200000 -+/** GPTC Timer/Counter 3A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3A 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC3A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC3A_DIR 0x00100000 -+/** GPTC Timer/Counter 2B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2B 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC2B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2B_DIR 0x00080000 -+/** GPTC Timer/Counter 2A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2A 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC2A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC2A_DIR 0x00040000 -+/** GPTC Timer/Counter 1B Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1B 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC1B_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1B_DIR 0x00020000 -+/** GPTC Timer/Counter 1A Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1A 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_GPTC_TC1A_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_GPTC_TC1A_DIR 0x00010000 -+/** ASC1 Soft Flow Control Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_SFC 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_SFC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_SFC_DIR 0x00008000 -+/** ASC1 Modem Status Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_MS 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_MS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_MS_DIR 0x00004000 -+/** ASC1 Autobaud Detection Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABDET 0x00002000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_ABDET_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABDET_DIR 0x00002000 -+/** ASC1 Autobaud Start Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABST 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_ABST_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_ABST_DIR 0x00001000 -+/** ASC1 Transmit Buffer Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_TB 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_TB_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_TB_DIR 0x00000800 -+/** ASC1 Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_E 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_E_DIR 0x00000400 -+/** ASC1 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_R 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_R_DIR 0x00000200 -+/** ASC1 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC1_T 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC1_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC1_T_DIR 0x00000100 -+/** ASC0 Soft Flow Control Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_SFC 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_SFC_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_SFC_DIR 0x00000080 -+/** ASC1 Modem Status Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_MS 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_MS_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_MS_DIR 0x00000040 -+/** ASC0 Autobaud Detection Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABDET 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_ABDET_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABDET_DIR 0x00000020 -+/** ASC0 Autobaud Start Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABST 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_ABST_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_ABST_DIR 0x00000010 -+/** ASC0 Transmit Buffer Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_TB 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_TB_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_TB_DIR 0x00000008 -+/** ASC0 Error Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_E 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_E_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_E_DIR 0x00000004 -+/** ASC0 Receive Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_R 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_R_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_R_DIR 0x00000002 -+/** ASC0 Transmit Interrupt -+ Type of interrupt. */ -+#define ICU0_IM3_IMR_ASC0_T 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM3_IMR_ASC0_T_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM3_IMR_ASC0_T_DIR 0x00000001 -+ -+/* Fields of "IM4 Interrupt Status Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR 0x80000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_PMCIR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_PMCIR_INTOCC 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_ERL 0x40000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_ERL_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_ERL_INTACK 0x40000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_ERL_INTOCC 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_VPE0_EXL 0x20000000 -+/* Nothing -+#define ICU0_IM4_ISR_VPE0_EXL_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_VPE0_EXL_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_VPE0_EXL_INTOCC 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR8 0x00400000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR8_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR8_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR8_INTOCC 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR7 0x00200000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR7_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR7_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR7_INTOCC 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR6 0x00100000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR6_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR6_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR6_INTOCC 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR5 0x00080000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR5_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR5_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR5_INTOCC 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR4 0x00040000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR4_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR4_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR4_INTOCC 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR3 0x00020000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR3_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR3_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR3_INTOCC 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR2 0x00010000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR2_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR2_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR2_INTOCC 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR1 0x00008000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR1_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR1_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR1_INTOCC 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR0 0x00004000 -+/* Nothing -+#define ICU0_IM4_ISR_MPS_IR0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_MPS_IR0_INTACK 0x00004000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_MPS_IR0_INTOCC 0x00004000 -+/** TMU Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_TMU_ERR 0x00001000 -+/* Nothing -+#define ICU0_IM4_ISR_TMU_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_TMU_ERR_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_TMU_ERR_INTOCC 0x00001000 -+/** FSQM Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_FSQM_ERR 0x00000800 -+/* Nothing -+#define ICU0_IM4_ISR_FSQM_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_FSQM_ERR_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_FSQM_ERR_INTOCC 0x00000800 -+/** IQM Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_IQM_ERR 0x00000400 -+/* Nothing -+#define ICU0_IM4_ISR_IQM_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_IQM_ERR_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_IQM_ERR_INTOCC 0x00000400 -+/** OCTRLG Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR 0x00000200 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLG_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLG_ERR_INTOCC 0x00000200 -+/** ICTRLG Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR 0x00000100 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLG_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLG_ERR_INTOCC 0x00000100 -+/** OCTRLL 3 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR 0x00000080 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL3_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTACK 0x00000080 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL3_ERR_INTOCC 0x00000080 -+/** OCTRLL 2 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR 0x00000040 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL2_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTACK 0x00000040 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL2_ERR_INTOCC 0x00000040 -+/** OCTRLL 1 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR 0x00000020 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL1_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTACK 0x00000020 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL1_ERR_INTOCC 0x00000020 -+/** OCTRLL 0 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR 0x00000010 -+/* Nothing -+#define ICU0_IM4_ISR_OCTRLL0_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_OCTRLL0_ERR_INTOCC 0x00000010 -+/** ICTRLL 3 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR 0x00000008 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL3_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL3_ERR_INTOCC 0x00000008 -+/** ICTRLL 2 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR 0x00000004 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL2_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL2_ERR_INTOCC 0x00000004 -+/** ICTRLL 1 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR 0x00000002 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL1_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL1_ERR_INTOCC 0x00000002 -+/** ICTRLL 0 Error -+ This bit is an indirect interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR 0x00000001 -+/* Nothing -+#define ICU0_IM4_ISR_ICTRLL0_ERR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_ISR_ICTRLL0_ERR_INTOCC 0x00000001 -+ -+/* Fields of "IM4 Interrupt Enable Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_PMCIR 0x80000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_PMCIR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_PMCIR_EN 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_ERL 0x40000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_ERL_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_ERL_EN 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_VPE0_EXL 0x20000000 -+/* Disable -+#define ICU0_IM4_IER_VPE0_EXL_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_VPE0_EXL_EN 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR8 0x00400000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR8_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR8_EN 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR7 0x00200000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR7_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR7_EN 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR6 0x00100000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR6_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR6_EN 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR5 0x00080000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR5_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR5_EN 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR4 0x00040000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR4_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR4_EN 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR3 0x00020000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR3_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR3_EN 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR2 0x00010000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR2_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR2_EN 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR1 0x00008000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR1_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR1_EN 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_MPS_IR0 0x00004000 -+/* Disable -+#define ICU0_IM4_IER_MPS_IR0_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_MPS_IR0_EN 0x00004000 -+/** TMU Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_TMU_ERR 0x00001000 -+/* Disable -+#define ICU0_IM4_IER_TMU_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_TMU_ERR_EN 0x00001000 -+/** FSQM Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_FSQM_ERR 0x00000800 -+/* Disable -+#define ICU0_IM4_IER_FSQM_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_FSQM_ERR_EN 0x00000800 -+/** IQM Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_IQM_ERR 0x00000400 -+/* Disable -+#define ICU0_IM4_IER_IQM_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_IQM_ERR_EN 0x00000400 -+/** OCTRLG Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLG_ERR 0x00000200 -+/* Disable -+#define ICU0_IM4_IER_OCTRLG_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLG_ERR_EN 0x00000200 -+/** ICTRLG Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLG_ERR 0x00000100 -+/* Disable -+#define ICU0_IM4_IER_ICTRLG_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLG_ERR_EN 0x00000100 -+/** OCTRLL 3 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL3_ERR 0x00000080 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL3_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL3_ERR_EN 0x00000080 -+/** OCTRLL 2 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL2_ERR 0x00000040 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL2_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL2_ERR_EN 0x00000040 -+/** OCTRLL 1 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL1_ERR 0x00000020 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL1_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL1_ERR_EN 0x00000020 -+/** OCTRLL 0 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_OCTRLL0_ERR 0x00000010 -+/* Disable -+#define ICU0_IM4_IER_OCTRLL0_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_OCTRLL0_ERR_EN 0x00000010 -+/** ICTRLL 3 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL3_ERR 0x00000008 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL3_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL3_ERR_EN 0x00000008 -+/** ICTRLL 2 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL2_ERR 0x00000004 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL2_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL2_ERR_EN 0x00000004 -+/** ICTRLL 1 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL1_ERR 0x00000002 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL1_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL1_ERR_EN 0x00000002 -+/** ICTRLL 0 Error -+ Interrupt enable bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IER_ICTRLL0_ERR 0x00000001 -+/* Disable -+#define ICU0_IM4_IER_ICTRLL0_ERR_DIS 0x00000000 */ -+/** Enable */ -+#define ICU0_IM4_IER_ICTRLL0_ERR_EN 0x00000001 -+ -+/* Fields of "IM4 Interrupt Output Status Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_PMCIR 0x80000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_PMCIR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_PMCIR_INTOCC 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_ERL 0x40000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_ERL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_ERL_INTOCC 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_VPE0_EXL 0x20000000 -+/* Nothing -+#define ICU0_IM4_IOSR_VPE0_EXL_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_VPE0_EXL_INTOCC 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR8 0x00400000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR8_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR8_INTOCC 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR7 0x00200000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR7_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR7_INTOCC 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR6 0x00100000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR6_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR6_INTOCC 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR5 0x00080000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR5_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR5_INTOCC 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR4 0x00040000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR4_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR4_INTOCC 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR3 0x00020000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR3_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR3_INTOCC 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR2 0x00010000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR2_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR2_INTOCC 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR1 0x00008000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR1_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR1_INTOCC 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_MPS_IR0 0x00004000 -+/* Nothing -+#define ICU0_IM4_IOSR_MPS_IR0_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_MPS_IR0_INTOCC 0x00004000 -+/** TMU Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_TMU_ERR 0x00001000 -+/* Nothing -+#define ICU0_IM4_IOSR_TMU_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_TMU_ERR_INTOCC 0x00001000 -+/** FSQM Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_FSQM_ERR 0x00000800 -+/* Nothing -+#define ICU0_IM4_IOSR_FSQM_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_FSQM_ERR_INTOCC 0x00000800 -+/** IQM Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_IQM_ERR 0x00000400 -+/* Nothing -+#define ICU0_IM4_IOSR_IQM_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_IQM_ERR_INTOCC 0x00000400 -+/** OCTRLG Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLG_ERR 0x00000200 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLG_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLG_ERR_INTOCC 0x00000200 -+/** ICTRLG Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLG_ERR 0x00000100 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLG_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLG_ERR_INTOCC 0x00000100 -+/** OCTRLL 3 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL3_ERR 0x00000080 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL3_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL3_ERR_INTOCC 0x00000080 -+/** OCTRLL 2 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL2_ERR 0x00000040 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL2_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL2_ERR_INTOCC 0x00000040 -+/** OCTRLL 1 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL1_ERR 0x00000020 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL1_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL1_ERR_INTOCC 0x00000020 -+/** OCTRLL 0 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_OCTRLL0_ERR 0x00000010 -+/* Nothing -+#define ICU0_IM4_IOSR_OCTRLL0_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_OCTRLL0_ERR_INTOCC 0x00000010 -+/** ICTRLL 3 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL3_ERR 0x00000008 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL3_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL3_ERR_INTOCC 0x00000008 -+/** ICTRLL 2 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL2_ERR 0x00000004 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL2_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL2_ERR_INTOCC 0x00000004 -+/** ICTRLL 1 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL1_ERR 0x00000002 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL1_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL1_ERR_INTOCC 0x00000002 -+/** ICTRLL 0 Error -+ Masked interrupt bit for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IOSR_ICTRLL0_ERR 0x00000001 -+/* Nothing -+#define ICU0_IM4_IOSR_ICTRLL0_ERR_NULL 0x00000000 */ -+/** Read: Interrupt occurred. */ -+#define ICU0_IM4_IOSR_ICTRLL0_ERR_INTOCC 0x00000001 -+ -+/* Fields of "IM4 Interrupt Request Set Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_PMCIR 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_ERL 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_VPE0_EXL 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR8 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR7 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR6 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR5 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR4 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR3 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR2 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR1 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_MPS_IR0 0x00004000 -+/** TMU Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_TMU_ERR 0x00001000 -+/** FSQM Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_FSQM_ERR 0x00000800 -+/** IQM Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_IQM_ERR 0x00000400 -+/** OCTRLG Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLG_ERR 0x00000200 -+/** ICTRLG Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLG_ERR 0x00000100 -+/** OCTRLL 3 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL3_ERR 0x00000080 -+/** OCTRLL 2 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL2_ERR 0x00000040 -+/** OCTRLL 1 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL1_ERR 0x00000020 -+/** OCTRLL 0 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_OCTRLL0_ERR 0x00000010 -+/** ICTRLL 3 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL3_ERR 0x00000008 -+/** ICTRLL 2 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL2_ERR 0x00000004 -+/** ICTRLL 1 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL1_ERR 0x00000002 -+/** ICTRLL 0 Error -+ Software control for the corresponding bit in the IM4_ISR register. */ -+#define ICU0_IM4_IRSR_ICTRLL0_ERR 0x00000001 -+ -+/* Fields of "IM4 Interrupt Mode Register" */ -+/** VPE0 Performance Monitoring Counter Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_PMCIR 0x80000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_PMCIR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_PMCIR_DIR 0x80000000 -+/** VPE0 Error Level Flag Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_ERL 0x40000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_ERL_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_ERL_DIR 0x40000000 -+/** VPE0 Exception Level Flag Interrupt -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_VPE0_EXL 0x20000000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_VPE0_EXL_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_VPE0_EXL_DIR 0x20000000 -+/** MPS Bin. Sem Interrupt to VPE0 -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR8 0x00400000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR8_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR8_DIR 0x00400000 -+/** MPS Global Interrupt to VPE0 -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR7 0x00200000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR7_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR7_DIR 0x00200000 -+/** MPS Status Interrupt #6 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR6 0x00100000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR6_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR6_DIR 0x00100000 -+/** MPS Status Interrupt #5 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR5 0x00080000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR5_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR5_DIR 0x00080000 -+/** MPS Status Interrupt #4 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR4 0x00040000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR4_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR4_DIR 0x00040000 -+/** MPS Status Interrupt #3 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR3 0x00020000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR3_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR3_DIR 0x00020000 -+/** MPS Status Interrupt #2 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR2 0x00010000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR2_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR2_DIR 0x00010000 -+/** MPS Status Interrupt #1 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR1 0x00008000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR1_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR1_DIR 0x00008000 -+/** MPS Status Interrupt #0 (VPE1 to VPE0) -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR0 0x00004000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_MPS_IR0_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_MPS_IR0_DIR 0x00004000 -+/** TMU Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_TMU_ERR 0x00001000 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_TMU_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_TMU_ERR_DIR 0x00001000 -+/** FSQM Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_FSQM_ERR 0x00000800 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_FSQM_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_FSQM_ERR_DIR 0x00000800 -+/** IQM Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_IQM_ERR 0x00000400 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_IQM_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_IQM_ERR_DIR 0x00000400 -+/** OCTRLG Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLG_ERR 0x00000200 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLG_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLG_ERR_DIR 0x00000200 -+/** ICTRLG Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLG_ERR 0x00000100 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLG_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLG_ERR_DIR 0x00000100 -+/** OCTRLL 3 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL3_ERR 0x00000080 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL3_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL3_ERR_DIR 0x00000080 -+/** OCTRLL 2 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL2_ERR 0x00000040 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL2_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL2_ERR_DIR 0x00000040 -+/** OCTRLL 1 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL1_ERR 0x00000020 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL1_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL1_ERR_DIR 0x00000020 -+/** OCTRLL 0 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL0_ERR 0x00000010 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_OCTRLL0_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_OCTRLL0_ERR_DIR 0x00000010 -+/** ICTRLL 3 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL3_ERR 0x00000008 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL3_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL3_ERR_DIR 0x00000008 -+/** ICTRLL 2 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL2_ERR 0x00000004 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL2_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL2_ERR_DIR 0x00000004 -+/** ICTRLL 1 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL1_ERR 0x00000002 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL1_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL1_ERR_DIR 0x00000002 -+/** ICTRLL 0 Error -+ Type of interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL0_ERR 0x00000001 -+/* Indirect Interrupt. -+#define ICU0_IM4_IMR_ICTRLL0_ERR_IND 0x00000000 */ -+/** Direct Interrupt. */ -+#define ICU0_IM4_IMR_ICTRLL0_ERR_DIR 0x00000001 -+ -+/* Fields of "ICU Interrupt Vector Register (5 bit variant)" */ -+/** IM4 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM4_vec_MASK 0x01F00000 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM4_vec_OFFSET 20 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM4_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT0 0x00100000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT1 0x00200000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM4_vec_BIT30 0x01F00000 -+/** IM3 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM3_vec_MASK 0x000F8000 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM3_vec_OFFSET 15 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM3_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT0 0x00008000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT1 0x00010000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM3_vec_BIT30 0x000F8000 -+/** IM2 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM2_vec_MASK 0x00007C00 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM2_vec_OFFSET 10 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM2_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT0 0x00000400 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT1 0x00000800 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM2_vec_BIT30 0x00007C00 -+/** IM1 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM1_vec_MASK 0x000003E0 -+/** field offset */ -+#define ICU0_ICU_IVEC_IM1_vec_OFFSET 5 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM1_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT0 0x00000020 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT1 0x00000040 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM1_vec_BIT30 0x000003E0 -+/** IM0 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_IM0_vec_MASK 0x0000001F -+/** field offset */ -+#define ICU0_ICU_IVEC_IM0_vec_OFFSET 0 -+/** Interrupt pending at bit 31 or no pending interrupt */ -+#define ICU0_ICU_IVEC_IM0_vec_NOINTorBit31 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT0 0x00000001 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT1 0x00000002 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_IM0_vec_BIT30 0x0000001F -+ -+/* Fields of "ICU Interrupt Vector Register (6 bit variant)" */ -+/** IM4 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_MASK 0x3F000000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM4_vec_OFFSET 24 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM4_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT0 0x01000000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT1 0x02000000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT30 0x1F000000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM4_vec_BIT31 0x20000000 -+/** IM3 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_MASK 0x00FC0000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM3_vec_OFFSET 18 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM3_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT0 0x00040000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT1 0x00080000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT30 0x007C0000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM3_vec_BIT31 0x00800000 -+/** IM2 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_MASK 0x0003F000 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM2_vec_OFFSET 12 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM2_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT0 0x00001000 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT1 0x00002000 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT30 0x0001F000 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM2_vec_BIT31 0x00020000 -+/** IM1 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_MASK 0x00000FC0 -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM1_vec_OFFSET 6 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM1_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT0 0x00000040 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT1 0x00000080 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT30 0x000007C0 -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM1_vec_BIT31 0x00000800 -+/** IM0 Interrupt Vector Value -+ Returns the highest priority pending interrupt vector. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_MASK 0x0000003F -+/** field offset */ -+#define ICU0_ICU_IVEC_6_IM0_vec_OFFSET 0 -+/** No pending interrupt */ -+#define ICU0_ICU_IVEC_6_IM0_vec_NOINT 0x00000000 -+/** Interrupt pending at bit 0. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT0 0x00000001 -+/** Interrupt pending at bit 1. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT1 0x00000002 -+/** Interrupt pending at bit 30. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT30 0x0000001F -+/** Interrupt pending at bit 31. */ -+#define ICU0_ICU_IVEC_6_IM0_vec_BIT31 0x00000020 -+ -+/*! @} */ /* ICU0_REGISTER */ -+ -+#endif /* _icu0_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h -new file mode 100644 -index 0000000..dfab030 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/status_reg.h -@@ -0,0 +1,529 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _status_reg_h -+#define _status_reg_h -+ -+/** \addtogroup STATUS_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define status_r32(reg) reg_r32(&status->reg) -+#define status_w32(val, reg) reg_w32(val, &status->reg) -+#define status_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &status->reg) -+#define status_r32_table(reg, idx) reg_r32_table(status->reg, idx) -+#define status_w32_table(val, reg, idx) reg_w32_table(val, status->reg, idx) -+#define status_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, status->reg, idx) -+#define status_adr_table(reg, idx) adr_table(status->reg, idx) -+ -+ -+/** STATUS register structure */ -+struct gpon_reg_status -+{ -+ /** Reserved */ -+ unsigned int res_0[3]; /* 0x00000000 */ -+ /** Chip Identification Register */ -+ unsigned int chipid; /* 0x0000000C */ -+ /** Chip Location Register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int chiploc; /* 0x00000010 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red0; /* 0x00000014 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red1; /* 0x00000018 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red2; /* 0x0000001C */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red3; /* 0x00000020 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red4; /* 0x00000024 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red5; /* 0x00000028 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red6; /* 0x0000002C */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red7; /* 0x00000030 */ -+ /** Redundancy register -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int red8; /* 0x00000034 */ -+ /** SPARE fuse register 0 -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int fuse0; /* 0x00000038 */ -+ /** Fuses for Analog modules -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int analog; /* 0x0000003C */ -+ /** Configuration fuses for drivers and pll -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int config; /* 0x00000040 */ -+ /** SPARE fuse register 1 -+ Note: All fuse-bits have a default value of 0 that can be changed to 1 during production test (unfused = 0, fused = 1).The reset-values stated for these bits is 0 even though SW will never be able to read 0 if it was set to 1 during production test. */ -+ unsigned int fuse1; /* 0x00000044 */ -+ /** Configuration for sbs0 rambist */ -+ unsigned int mbcfg; /* 0x00000048 */ -+ /** sbs0 bist result and debug data */ -+ unsigned int mbdata; /* 0x0000004C */ -+ /** Reserved */ -+ unsigned int res_1[12]; /* 0x00000050 */ -+}; -+ -+ -+/* Fields of "Chip Identification Register" */ -+/** Chip Version Number -+ Version number */ -+#define STATUS_CHIPID_VERSION_MASK 0xF0000000 -+/** field offset */ -+#define STATUS_CHIPID_VERSION_OFFSET 28 -+/** Part Number, Constant Part -+ The Part Number is fixed to 016Bhex. */ -+#define STATUS_CHIPID_PARTNR_MASK 0x0FFFF000 -+/** field offset */ -+#define STATUS_CHIPID_PARTNR_OFFSET 12 -+/** Manufacturer ID -+ The value of bit field MANID is fixed to 41hex as configured in the JTAG ID register. The JEDEC normalized manufacturer code for Infineon Technologies is C1hex */ -+#define STATUS_CHIPID_MANID_MASK 0x00000FFE -+/** field offset */ -+#define STATUS_CHIPID_MANID_OFFSET 1 -+/** Constant bit -+ The value of bit field CONST1 is fixed to 1hex */ -+#define STATUS_CHIPID_CONST1 0x00000001 -+ -+/* Fields of "Chip Location Register" */ -+/** Chip Lot ID */ -+#define STATUS_CHIPLOC_CHIPLOT_MASK 0xFFFF0000 -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPLOT_OFFSET 16 -+/** Chip X Coordinate */ -+#define STATUS_CHIPLOC_CHIPX_MASK 0x0000FF00 -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPX_OFFSET 8 -+/** Chip Y Coordinate */ -+#define STATUS_CHIPLOC_CHIPY_MASK 0x000000FF -+/** field offset */ -+#define STATUS_CHIPLOC_CHIPY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED0_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED0_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED1_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED1_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED2_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED2_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED3_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED3_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED4_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED4_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED5_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED5_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED6_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED6_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED7_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED7_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "Redundancy register" */ -+/** Redundancy -+ redundancy information stored in eFuses. MSB + MEM_ADDR - MSB = 1 defines a valid address */ -+#define STATUS_RED8_REDUNDANCY_MASK 0x0003FFFF -+/** field offset */ -+#define STATUS_RED8_REDUNDANCY_OFFSET 0 -+ -+/* Fields of "SPARE fuse register 0" */ -+/** Soft fuse control -+ Controls whether the status block is in its softfused state or not. In the softfused state the values written via software are active effective. */ -+#define STATUS_FUSE0_SFC 0x80000000 -+/* Not selected -+#define STATUS_FUSE0_SFC_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_FUSE0_SFC_SEL 0x80000000 -+/** Soft control MBCFG -+ Controls whether mbist configuration can be overwritten or not from subsystem. If not selected jtag mbcfg register is source for software mbist configuration */ -+#define STATUS_FUSE0_SC_MBCFG 0x40000000 -+/* Not selected -+#define STATUS_FUSE0_SC_MBCFG_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_FUSE0_SC_MBCFG_SEL 0x40000000 -+/** spare fuse0 -+ eFuses not assigned to hw/sw, can be used for future applications */ -+#define STATUS_FUSE0_F0_MASK 0x3C000000 -+/** field offset */ -+#define STATUS_FUSE0_F0_OFFSET 26 -+/** VCALMM20 Voltage Reference -+ Voltage Reference for calibration via R and constant current (20 uA) */ -+#define STATUS_FUSE0_VCALMM20_MASK 0x03F00000 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM20_OFFSET 20 -+/** VCALMM100 Voltage Reference -+ Voltage Reference for calibration via R and constant current (100 uA) */ -+#define STATUS_FUSE0_VCALMM100_MASK 0x000FC000 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM100_OFFSET 14 -+/** VCALMM400 Voltage Reference -+ Voltage Reference for calibration via R and constant current (400 uA) */ -+#define STATUS_FUSE0_VCALMM400_MASK 0x00003F00 -+/** field offset */ -+#define STATUS_FUSE0_VCALMM400_OFFSET 8 -+/** RCALMM R error correction -+ The resistance deviation from ideal R (1000 Ohm) */ -+#define STATUS_FUSE0_RCALMM_MASK 0x000000FF -+/** field offset */ -+#define STATUS_FUSE0_RCALMM_OFFSET 0 -+ -+/* Fields of "Fuses for Analog modules" */ -+/** reserved Analog eFuses -+ Reserved Register contains information stored in eFuses needed for the analog modules */ -+#define STATUS_ANALOG_A0_MASK 0xFF000000 -+/** field offset */ -+#define STATUS_ANALOG_A0_OFFSET 24 -+/** Absolut Temperature -+ Temperature ERROR */ -+#define STATUS_ANALOG_TEMPMM_MASK 0x00FC0000 -+/** field offset */ -+#define STATUS_ANALOG_TEMPMM_OFFSET 18 -+/** Bias Voltage Generation -+ temperature dependency */ -+#define STATUS_ANALOG_TBGP_MASK 0x00038000 -+/** field offset */ -+#define STATUS_ANALOG_TBGP_OFFSET 15 -+/** Bias Voltage Generation -+ voltage dependency */ -+#define STATUS_ANALOG_VBGP_MASK 0x00007000 -+/** field offset */ -+#define STATUS_ANALOG_VBGP_OFFSET 12 -+/** Bias Current Generation */ -+#define STATUS_ANALOG_IREFBGP_MASK 0x00000F00 -+/** field offset */ -+#define STATUS_ANALOG_IREFBGP_OFFSET 8 -+/** Drive DAC Gain */ -+#define STATUS_ANALOG_GAINDRIVEDAC_MASK 0x000000F0 -+/** field offset */ -+#define STATUS_ANALOG_GAINDRIVEDAC_OFFSET 4 -+/** BIAS DAC Gain */ -+#define STATUS_ANALOG_GAINBIASDAC_MASK 0x0000000F -+/** field offset */ -+#define STATUS_ANALOG_GAINBIASDAC_OFFSET 0 -+ -+/* Fields of "Configuration fuses for drivers and pll" */ -+/** ddr PU driver -+ ddr pullup driver strength adjustment */ -+#define STATUS_CONFIG_DDRPU_MASK 0xC0000000 -+/** field offset */ -+#define STATUS_CONFIG_DDRPU_OFFSET 30 -+/** ddr PD driver -+ ddr pulldown driver strength adjustment */ -+#define STATUS_CONFIG_DDRPD_MASK 0x30000000 -+/** field offset */ -+#define STATUS_CONFIG_DDRPD_OFFSET 28 -+/** Authentification Unit enable -+ This bit can only be set via eFuse and enables the authentification unit. */ -+#define STATUS_CONFIG_SHA1EN 0x08000000 -+/* Not selected -+#define STATUS_CONFIG_SHA1EN_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_SHA1EN_SEL 0x08000000 -+/** Encryption Unit enable -+ This bit can only be set via eFuse and enables the encryption unit. */ -+#define STATUS_CONFIG_AESEN 0x04000000 -+/* Not selected -+#define STATUS_CONFIG_AESEN_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_AESEN_SEL 0x04000000 -+/** Subversion Number -+ The subversion number has no direct effect on hardware functions. It is used to provide another chip version number that is fixed in hardware and can be read out by software. In this way different product packages consisting of GPON_MODEM and software can be defined for example */ -+#define STATUS_CONFIG_SUBVERS_MASK 0x03C00000 -+/** field offset */ -+#define STATUS_CONFIG_SUBVERS_OFFSET 22 -+/** PLL settings -+ PLL settings for infrastructure block */ -+#define STATUS_CONFIG_PLLINFRA_MASK 0x003FF000 -+/** field offset */ -+#define STATUS_CONFIG_PLLINFRA_OFFSET 12 -+/** GPE frequency selection -+ Scaling down the GPE frequency for debugging purpose */ -+#define STATUS_CONFIG_GPEFREQ_MASK 0x00000C00 -+/** field offset */ -+#define STATUS_CONFIG_GPEFREQ_OFFSET 10 -+/** RM enable -+ Activates the Read Margin Settings defined in the RM Field, for all VIRAGE Memories except GPE */ -+#define STATUS_CONFIG_RME 0x00000200 -+/* Not selected -+#define STATUS_CONFIG_RME_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_RME_SEL 0x00000200 -+/** RM settings -+ Read Marging Settings for all VIRAGE Memories except GPE */ -+#define STATUS_CONFIG_RM_MASK 0x000001E0 -+/** field offset */ -+#define STATUS_CONFIG_RM_OFFSET 5 -+/** RM enable for GPE Memories -+ Activates the Read Margin Settings defined in the RM Field */ -+#define STATUS_CONFIG_RMEGPE 0x00000010 -+/* Not selected -+#define STATUS_CONFIG_RMEGPE_NSEL 0x00000000 */ -+/** Selected */ -+#define STATUS_CONFIG_RMEGPE_SEL 0x00000010 -+/** RM settings for GPE Memories -+ Read Marging Settings for VIRAGE Memories in GPE module */ -+#define STATUS_CONFIG_RMGPE_MASK 0x0000000F -+/** field offset */ -+#define STATUS_CONFIG_RMGPE_OFFSET 0 -+ -+/* Fields of "SPARE fuse register 1" */ -+/** spare fuse1 -+ eFuses not assigned to hw/sw, can be used for future applications */ -+#define STATUS_FUSE1_F1_MASK 0xFFF00000 -+/** field offset */ -+#define STATUS_FUSE1_F1_OFFSET 20 -+/** DCDC DDR OFFSET -+ offset error sense path */ -+#define STATUS_FUSE1_OFFSETDDRDCDC_MASK 0x000F0000 -+/** field offset */ -+#define STATUS_FUSE1_OFFSETDDRDCDC_OFFSET 16 -+/** DCDC DDR GAIN -+ gain error sense path */ -+#define STATUS_FUSE1_GAINDDRDCDC_MASK 0x0000FC00 -+/** field offset */ -+#define STATUS_FUSE1_GAINDDRDCDC_OFFSET 10 -+/** DCDC APD OFFSET -+ offset error sense path */ -+#define STATUS_FUSE1_OFFSETAPDDCDC_MASK 0x000003C0 -+/** field offset */ -+#define STATUS_FUSE1_OFFSETAPDDCDC_OFFSET 6 -+/** DCDC APD GAIN -+ gain error sense path */ -+#define STATUS_FUSE1_GAINAPDDCDC_MASK 0x0000003F -+/** field offset */ -+#define STATUS_FUSE1_GAINAPDDCDC_OFFSET 0 -+ -+/* Fields of "Configuration for sbs0 rambist" */ -+/** Disable asc monitoring during boot-up -+ Bit is used to avoid asc output for reducing pattern count on testsystem */ -+#define STATUS_MBCFG_ASC_DBGDIS 0x01000000 -+/* Disable -+#define STATUS_MBCFG_ASC_DBGDIS_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_ASC_DBGDIS_EN 0x01000000 -+/** Descrambling Enable/Disable -+ Enables Address and Data Descrambling for internal Memory Test */ -+#define STATUS_MBCFG_DSC 0x00800000 -+/* Disable -+#define STATUS_MBCFG_DSC_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_DSC_EN 0x00800000 -+/** Enable repair mode -+ When bit is set redundancy repair mode is activated */ -+#define STATUS_MBCFG_REPAIR 0x00400000 -+/* Disable -+#define STATUS_MBCFG_REPAIR_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_REPAIR_EN 0x00400000 -+/** DEBUG Mode */ -+#define STATUS_MBCFG_DBG 0x00200000 -+/* Disable -+#define STATUS_MBCFG_DBG_DIS 0x00000000 */ -+/** Enable */ -+#define STATUS_MBCFG_DBG_EN 0x00200000 -+/** Retention Time -+ Length oft the Retention Time */ -+#define STATUS_MBCFG_RTIME_MASK 0x001C0000 -+/** field offset */ -+#define STATUS_MBCFG_RTIME_OFFSET 18 -+/** retention mode is switched off */ -+#define STATUS_MBCFG_RTIME_RET0 0x00000000 -+/** Retention time 50 ms */ -+#define STATUS_MBCFG_RTIME_RET50 0x00040000 -+/** Retention time 60 ms */ -+#define STATUS_MBCFG_RTIME_RET60 0x00080000 -+/** Retention time 70 ms */ -+#define STATUS_MBCFG_RTIME_RET70 0x000C0000 -+/** Retention time 80 ms */ -+#define STATUS_MBCFG_RTIME_RET80 0x00100000 -+/** Retention time 90 ms */ -+#define STATUS_MBCFG_RTIME_RET90 0x00140000 -+/** Retention time 1000 ms */ -+#define STATUS_MBCFG_RTIME_RET1000 0x00180000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_5_MASK 0x00038000 -+/** field offset */ -+#define STATUS_MBCFG_TID_5_OFFSET 15 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_5_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_5_MARCH 0x00008000 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_5_CHCK 0x00010000 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_5_HAM 0x00018000 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_5_ADEC 0x00020000 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_5_WMBYTE 0x00028000 -+/** Reserved */ -+#define STATUS_MBCFG_TID_5_RES 0x00030000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_4_MASK 0x00007000 -+/** field offset */ -+#define STATUS_MBCFG_TID_4_OFFSET 12 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_4_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_4_MARCH 0x00001000 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_4_CHCK 0x00002000 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_4_HAM 0x00003000 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_4_ADEC 0x00004000 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_4_WMBYTE 0x00005000 -+/** Reserved */ -+#define STATUS_MBCFG_TID_4_RES 0x00006000 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_3_MASK 0x00000E00 -+/** field offset */ -+#define STATUS_MBCFG_TID_3_OFFSET 9 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_3_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_3_MARCH 0x00000200 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_3_CHCK 0x00000400 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_3_HAM 0x00000600 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_3_ADEC 0x00000800 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_3_WMBYTE 0x00000A00 -+/** Reserved */ -+#define STATUS_MBCFG_TID_3_RES 0x00000C00 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_2_MASK 0x000001C0 -+/** field offset */ -+#define STATUS_MBCFG_TID_2_OFFSET 6 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_2_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_2_MARCH 0x00000040 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_2_CHCK 0x00000080 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_2_HAM 0x000000C0 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_2_ADEC 0x00000100 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_2_WMBYTE 0x00000140 -+/** Reserved */ -+#define STATUS_MBCFG_TID_2_RES 0x00000180 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_1_MASK 0x00000038 -+/** field offset */ -+#define STATUS_MBCFG_TID_1_OFFSET 3 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_1_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_1_MARCH 0x00000008 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_1_CHCK 0x00000010 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_1_HAM 0x00000018 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_1_ADEC 0x00000020 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_1_WMBYTE 0x00000028 -+/** Reserved */ -+#define STATUS_MBCFG_TID_1_RES 0x00000030 -+/** Test ID -+ Defines the test to execute. In which order the tests are executed can be defined via TID_n (TID_1 1st execution, TID_2 2nd execution ..) */ -+#define STATUS_MBCFG_TID_0_MASK 0x00000007 -+/** field offset */ -+#define STATUS_MBCFG_TID_0_OFFSET 0 -+/** No test is performed */ -+#define STATUS_MBCFG_TID_0_NONE 0x00000000 -+/** March test */ -+#define STATUS_MBCFG_TID_0_MARCH 0x00000001 -+/** Checkerboard test */ -+#define STATUS_MBCFG_TID_0_CHCK 0x00000002 -+/** Hammer test */ -+#define STATUS_MBCFG_TID_0_HAM 0x00000003 -+/** Address decoder test */ -+#define STATUS_MBCFG_TID_0_ADEC 0x00000004 -+/** Write mask byte test */ -+#define STATUS_MBCFG_TID_0_WMBYTE 0x00000005 -+/** Reserved */ -+#define STATUS_MBCFG_TID_0_RES 0x00000006 -+ -+/* Fields of "sbs0 bist result and debug data" */ -+/** BIST result and debug data -+ Stores additional debug information */ -+#define STATUS_MBDATA_DATA_MASK 0xFFFFFFF8 -+/** field offset */ -+#define STATUS_MBDATA_DATA_OFFSET 3 -+/** MBIST NOGO -+ The BIST failed and cannot be repaired due to many failure locations */ -+#define STATUS_MBDATA_MBNOGO 0x00000004 -+/** MBIST FAILED -+ The BIST failed but can be repaired */ -+#define STATUS_MBDATA_MBFAIL 0x00000002 -+/** MBIST PASSED -+ The BIST passed without any Failures */ -+#define STATUS_MBDATA_MBPASS 0x00000001 -+ -+/*! @} */ /* STATUS_REGISTER */ -+ -+#endif /* _status_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h -new file mode 100644 -index 0000000..d29007f ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys1_reg.h -@@ -0,0 +1,2008 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys1_reg_h -+#define _sys1_reg_h -+ -+/** \addtogroup SYS1_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys1_r32(reg) reg_r32(&sys1->reg) -+#define sys1_w32(val, reg) reg_w32(val, &sys1->reg) -+#define sys1_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys1->reg) -+#define sys1_r32_table(reg, idx) reg_r32_table(sys1->reg, idx) -+#define sys1_w32_table(val, reg, idx) reg_w32_table(val, sys1->reg, idx) -+#define sys1_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys1->reg, idx) -+#define sys1_adr_table(reg, idx) adr_table(sys1->reg, idx) -+ -+ -+/** SYS1 register structure */ -+struct gpon_reg_sys1 -+{ -+ /** Clock Status Register */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[4]; /* 0x00000030 */ -+ /** CPU0 Clock Control Register -+ Clock control register for CPU0 */ -+ unsigned int cpu0cc; /* 0x00000040 */ -+ /** Reserved */ -+ unsigned int res_2[7]; /* 0x00000044 */ -+ /** CPU0 Reset Source Register -+ Via this register the CPU can find the the root cause for the boot it currently goes through, and take the appropriate measures. */ -+ unsigned int cpu0rs; /* 0x00000060 */ -+ /** Reserved */ -+ unsigned int res_3[7]; /* 0x00000064 */ -+ /** CPU0 Wakeup Configuration Register -+ Controls the wakeup condition for CPU0. Note: The upper 16 bit of this register have to be set to the same value as the mask bits within the yield-resume interface block. If the yield-resume interface is not used at all, set the upper 16 bit to 0. */ -+ unsigned int cpu0wcfg; /* 0x00000080 */ -+ /** Reserved */ -+ unsigned int res_4[7]; /* 0x00000084 */ -+ /** Bootmode Control Register -+ Reflects the bootmode for the CPU and provides means to manipulate it. */ -+ unsigned int bmc; /* 0x000000A0 */ -+ /** Reserved */ -+ unsigned int res_5[3]; /* 0x000000A4 */ -+ /** Sleep Configuration Register */ -+ unsigned int scfg; /* 0x000000B0 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be switched off. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** CLKO Pad Control Register -+ Controls the behaviour of the CLKO pad/ball. */ -+ unsigned int clkoc; /* 0x000000B8 */ -+ /** Infrastructure Control Register -+ Controls the behaviour of the components of the infrastructure block. */ -+ unsigned int infrac; /* 0x000000BC */ -+ /** HRST_OUT_N Control Register -+ Controls the behaviour of the HRST_OUT_N pin. */ -+ unsigned int hrstoutc; /* 0x000000C0 */ -+ /** EBU Clock Control Register -+ Clock control register for the EBU. */ -+ unsigned int ebucc; /* 0x000000C4 */ -+ /** Reserved */ -+ unsigned int res_6[2]; /* 0x000000C8 */ -+ /** NMI Status Register -+ The Test NMI source is the GPTC counter 1A overflow bit. */ -+ unsigned int nmis; /* 0x000000D0 */ -+ /** NMI Set Register */ -+ unsigned int nmiset; /* 0x000000D4 */ -+ /** NMI Clear Register */ -+ unsigned int nmiclr; /* 0x000000D8 */ -+ /** NMI Test Configuration Register */ -+ unsigned int nmitcfg; /* 0x000000DC */ -+ /** NMI VPE1 Control Register */ -+ unsigned int nmivpe1c; /* 0x000000E0 */ -+ /** Reserved */ -+ unsigned int res_7[3]; /* 0x000000E4 */ -+ /** IRN Capture Register -+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNEN register. The interrupts can be acknowledged by a write operation. */ -+ unsigned int irncr; /* 0x000000F0 */ -+ /** IRN Interrupt Control Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int irnicr; /* 0x000000F4 */ -+ /** IRN Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int irnen; /* 0x000000F8 */ -+ /** Reserved */ -+ unsigned int res_8; /* 0x000000FC */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** STATUS Clock Enable -+ Shows the clock enable bit for the STATUS domain. This domain contains the STATUS block. */ -+#define CLKS_STATUS 0x80000000 -+/* Disable -+#define CLKS_STATUS_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_STATUS_EN 0x80000000 -+/** SHA1 Clock Enable -+ Shows the clock enable bit for the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKS_SHA1 0x40000000 -+/* Disable -+#define CLKS_SHA1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_SHA1_EN 0x40000000 -+/** AES Clock Enable -+ Shows the clock enable bit for the AES domain. This domain contains the AES block. */ -+#define CLKS_AES 0x20000000 -+/* Disable -+#define CLKS_AES_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_AES_EN 0x20000000 -+/** PCM Clock Enable -+ Shows the clock enable bit for the PCM domain. This domain contains the PCM interface block. */ -+#define CLKS_PCM 0x10000000 -+/* Disable -+#define CLKS_PCM_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PCM_EN 0x10000000 -+/** FSCT Clock Enable -+ Shows the clock enable bit for the FSCT domain. This domain contains the FSCT block. */ -+#define CLKS_FSCT 0x08000000 -+/* Disable -+#define CLKS_FSCT_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_FSCT_EN 0x08000000 -+/** GPTC Clock Enable -+ Shows the clock enable bit for the GPTC domain. This domain contains the GPTC block. */ -+#define CLKS_GPTC 0x04000000 -+/* Disable -+#define CLKS_GPTC_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_GPTC_EN 0x04000000 -+/** MPS Clock Enable -+ Shows the clock enable bit for the MPS domain. This domain contains the MPS block. */ -+#define CLKS_MPS 0x02000000 -+/* Disable -+#define CLKS_MPS_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_MPS_EN 0x02000000 -+/** DFEV0 Clock Enable -+ Shows the clock enable bit for the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKS_DFEV0 0x01000000 -+/* Disable -+#define CLKS_DFEV0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DFEV0_EN 0x01000000 -+/** PADCTRL4 Clock Enable -+ Shows the clock enable bit for the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKS_PADCTRL4 0x00400000 -+/* Disable -+#define CLKS_PADCTRL4_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL4_EN 0x00400000 -+/** PADCTRL3 Clock Enable -+ Shows the clock enable bit for the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKS_PADCTRL3 0x00200000 -+/* Disable -+#define CLKS_PADCTRL3_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL3_EN 0x00200000 -+/** PADCTRL1 Clock Enable -+ Shows the clock enable bit for the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKS_PADCTRL1 0x00100000 -+/* Disable -+#define CLKS_PADCTRL1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_PADCTRL1_EN 0x00100000 -+/** P4 Clock Enable -+ Shows the clock enable bit for the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKS_P4 0x00040000 -+/* Disable -+#define CLKS_P4_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P4_EN 0x00040000 -+/** P3 Clock Enable -+ Shows the clock enable bit for the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKS_P3 0x00020000 -+/* Disable -+#define CLKS_P3_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P3_EN 0x00020000 -+/** P1 Clock Enable -+ Shows the clock enable bit for the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKS_P1 0x00010000 -+/* Disable -+#define CLKS_P1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_P1_EN 0x00010000 -+/** HOST Clock Enable -+ Shows the clock enable bit for the HOST domain. This domain contains the HOST interface block. */ -+#define CLKS_HOST 0x00008000 -+/* Disable -+#define CLKS_HOST_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_HOST_EN 0x00008000 -+/** I2C Clock Enable -+ Shows the clock enable bit for the I2C domain. This domain contains the I2C interface block. */ -+#define CLKS_I2C 0x00004000 -+/* Disable -+#define CLKS_I2C_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_I2C_EN 0x00004000 -+/** SSC0 Clock Enable -+ Shows the clock enable bit for the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKS_SSC0 0x00002000 -+/* Disable -+#define CLKS_SSC0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_SSC0_EN 0x00002000 -+/** ASC0 Clock Enable -+ Shows the clock enable bit for the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKS_ASC0 0x00001000 -+/* Disable -+#define CLKS_ASC0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_ASC0_EN 0x00001000 -+/** ASC1 Clock Enable -+ Shows the clock enable bit for the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKS_ASC1 0x00000800 -+/* Disable -+#define CLKS_ASC1_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_ASC1_EN 0x00000800 -+/** DCDCAPD Clock Enable -+ Shows the clock enable bit for the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKS_DCDCAPD 0x00000400 -+/* Disable -+#define CLKS_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDCAPD_EN 0x00000400 -+/** DCDCDDR Clock Enable -+ Shows the clock enable bit for the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKS_DCDCDDR 0x00000200 -+/* Disable -+#define CLKS_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDCDDR_EN 0x00000200 -+/** DCDC1V0 Clock Enable -+ Shows the clock enable bit for the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKS_DCDC1V0 0x00000100 -+/* Disable -+#define CLKS_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DCDC1V0_EN 0x00000100 -+/** TRC2MEM Clock Enable -+ Shows the clock enable bit for the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKS_TRC2MEM 0x00000040 -+/* Disable -+#define CLKS_TRC2MEM_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_TRC2MEM_EN 0x00000040 -+/** DDR Clock Enable -+ Shows the clock enable bit for the DDR domain. This domain contains the DDR interface block. */ -+#define CLKS_DDR 0x00000020 -+/* Disable -+#define CLKS_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_DDR_EN 0x00000020 -+/** EBU Clock Enable -+ Shows the clock enable bit for the EBU domain. This domain contains the EBU interface block. */ -+#define CLKS_EBU 0x00000010 -+/* Disable -+#define CLKS_EBU_DIS 0x00000000 */ -+/** Enable */ -+#define CLKS_EBU_EN 0x00000010 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable STATUS -+ Sets the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ -+#define CLKEN_STATUS 0x80000000 -+/* No-Operation -+#define CLKEN_STATUS_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_STATUS_SET 0x80000000 -+/** Set Clock Enable SHA1 -+ Sets the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKEN_SHA1 0x40000000 -+/* No-Operation -+#define CLKEN_SHA1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_SHA1_SET 0x40000000 -+/** Set Clock Enable AES -+ Sets the clock enable bit of the AES domain. This domain contains the AES block. */ -+#define CLKEN_AES 0x20000000 -+/* No-Operation -+#define CLKEN_AES_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_AES_SET 0x20000000 -+/** Set Clock Enable PCM -+ Sets the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ -+#define CLKEN_PCM 0x10000000 -+/* No-Operation -+#define CLKEN_PCM_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PCM_SET 0x10000000 -+/** Set Clock Enable FSCT -+ Sets the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ -+#define CLKEN_FSCT 0x08000000 -+/* No-Operation -+#define CLKEN_FSCT_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_FSCT_SET 0x08000000 -+/** Set Clock Enable GPTC -+ Sets the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ -+#define CLKEN_GPTC 0x04000000 -+/* No-Operation -+#define CLKEN_GPTC_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_GPTC_SET 0x04000000 -+/** Set Clock Enable MPS -+ Sets the clock enable bit of the MPS domain. This domain contains the MPS block. */ -+#define CLKEN_MPS 0x02000000 -+/* No-Operation -+#define CLKEN_MPS_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_MPS_SET 0x02000000 -+/** Set Clock Enable DFEV0 -+ Sets the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKEN_DFEV0 0x01000000 -+/* No-Operation -+#define CLKEN_DFEV0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DFEV0_SET 0x01000000 -+/** Set Clock Enable PADCTRL4 -+ Sets the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKEN_PADCTRL4 0x00400000 -+/* No-Operation -+#define CLKEN_PADCTRL4_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL4_SET 0x00400000 -+/** Set Clock Enable PADCTRL3 -+ Sets the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKEN_PADCTRL3 0x00200000 -+/* No-Operation -+#define CLKEN_PADCTRL3_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL3_SET 0x00200000 -+/** Set Clock Enable PADCTRL1 -+ Sets the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKEN_PADCTRL1 0x00100000 -+/* No-Operation -+#define CLKEN_PADCTRL1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_PADCTRL1_SET 0x00100000 -+/** Set Clock Enable P4 -+ Sets the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKEN_P4 0x00040000 -+/* No-Operation -+#define CLKEN_P4_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P4_SET 0x00040000 -+/** Set Clock Enable P3 -+ Sets the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKEN_P3 0x00020000 -+/* No-Operation -+#define CLKEN_P3_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P3_SET 0x00020000 -+/** Set Clock Enable P1 -+ Sets the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKEN_P1 0x00010000 -+/* No-Operation -+#define CLKEN_P1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_P1_SET 0x00010000 -+/** Set Clock Enable HOST -+ Sets the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ -+#define CLKEN_HOST 0x00008000 -+/* No-Operation -+#define CLKEN_HOST_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_HOST_SET 0x00008000 -+/** Set Clock Enable I2C -+ Sets the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ -+#define CLKEN_I2C 0x00004000 -+/* No-Operation -+#define CLKEN_I2C_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_I2C_SET 0x00004000 -+/** Set Clock Enable SSC0 -+ Sets the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKEN_SSC0 0x00002000 -+/* No-Operation -+#define CLKEN_SSC0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_SSC0_SET 0x00002000 -+/** Set Clock Enable ASC0 -+ Sets the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKEN_ASC0 0x00001000 -+/* No-Operation -+#define CLKEN_ASC0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_ASC0_SET 0x00001000 -+/** Set Clock Enable ASC1 -+ Sets the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKEN_ASC1 0x00000800 -+/* No-Operation -+#define CLKEN_ASC1_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_ASC1_SET 0x00000800 -+/** Set Clock Enable DCDCAPD -+ Sets the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKEN_DCDCAPD 0x00000400 -+/* No-Operation -+#define CLKEN_DCDCAPD_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDCAPD_SET 0x00000400 -+/** Set Clock Enable DCDCDDR -+ Sets the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKEN_DCDCDDR 0x00000200 -+/* No-Operation -+#define CLKEN_DCDCDDR_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDCDDR_SET 0x00000200 -+/** Set Clock Enable DCDC1V0 -+ Sets the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKEN_DCDC1V0 0x00000100 -+/* No-Operation -+#define CLKEN_DCDC1V0_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DCDC1V0_SET 0x00000100 -+/** Set Clock Enable TRC2MEM -+ Sets the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKEN_TRC2MEM 0x00000040 -+/* No-Operation -+#define CLKEN_TRC2MEM_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_TRC2MEM_SET 0x00000040 -+/** Set Clock Enable DDR -+ Sets the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ -+#define CLKEN_DDR 0x00000020 -+/* No-Operation -+#define CLKEN_DDR_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_DDR_SET 0x00000020 -+/** Set Clock Enable EBU -+ Sets the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ -+#define CLKEN_EBU 0x00000010 -+/* No-Operation -+#define CLKEN_EBU_NOP 0x00000000 */ -+/** Set */ -+#define CLKEN_EBU_SET 0x00000010 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable STATUS -+ Clears the clock enable bit of the STATUS domain. This domain contains the STATUS block. */ -+#define CLKCLR_STATUS 0x80000000 -+/* No-Operation -+#define CLKCLR_STATUS_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_STATUS_CLR 0x80000000 -+/** Clear Clock Enable SHA1 -+ Clears the clock enable bit of the SHA1 domain. This domain contains the SHA1 block. */ -+#define CLKCLR_SHA1 0x40000000 -+/* No-Operation -+#define CLKCLR_SHA1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_SHA1_CLR 0x40000000 -+/** Clear Clock Enable AES -+ Clears the clock enable bit of the AES domain. This domain contains the AES block. */ -+#define CLKCLR_AES 0x20000000 -+/* No-Operation -+#define CLKCLR_AES_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_AES_CLR 0x20000000 -+/** Clear Clock Enable PCM -+ Clears the clock enable bit of the PCM domain. This domain contains the PCM interface block. */ -+#define CLKCLR_PCM 0x10000000 -+/* No-Operation -+#define CLKCLR_PCM_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PCM_CLR 0x10000000 -+/** Clear Clock Enable FSCT -+ Clears the clock enable bit of the FSCT domain. This domain contains the FSCT block. */ -+#define CLKCLR_FSCT 0x08000000 -+/* No-Operation -+#define CLKCLR_FSCT_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_FSCT_CLR 0x08000000 -+/** Clear Clock Enable GPTC -+ Clears the clock enable bit of the GPTC domain. This domain contains the GPTC block. */ -+#define CLKCLR_GPTC 0x04000000 -+/* No-Operation -+#define CLKCLR_GPTC_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_GPTC_CLR 0x04000000 -+/** Clear Clock Enable MPS -+ Clears the clock enable bit of the MPS domain. This domain contains the MPS block. */ -+#define CLKCLR_MPS 0x02000000 -+/* No-Operation -+#define CLKCLR_MPS_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_MPS_CLR 0x02000000 -+/** Clear Clock Enable DFEV0 -+ Clears the clock enable bit of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define CLKCLR_DFEV0 0x01000000 -+/* No-Operation -+#define CLKCLR_DFEV0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DFEV0_CLR 0x01000000 -+/** Clear Clock Enable PADCTRL4 -+ Clears the clock enable bit of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define CLKCLR_PADCTRL4 0x00400000 -+/* No-Operation -+#define CLKCLR_PADCTRL4_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL4_CLR 0x00400000 -+/** Clear Clock Enable PADCTRL3 -+ Clears the clock enable bit of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define CLKCLR_PADCTRL3 0x00200000 -+/* No-Operation -+#define CLKCLR_PADCTRL3_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL3_CLR 0x00200000 -+/** Clear Clock Enable PADCTRL1 -+ Clears the clock enable bit of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define CLKCLR_PADCTRL1 0x00100000 -+/* No-Operation -+#define CLKCLR_PADCTRL1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_PADCTRL1_CLR 0x00100000 -+/** Clear Clock Enable P4 -+ Clears the clock enable bit of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define CLKCLR_P4 0x00040000 -+/* No-Operation -+#define CLKCLR_P4_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P4_CLR 0x00040000 -+/** Clear Clock Enable P3 -+ Clears the clock enable bit of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define CLKCLR_P3 0x00020000 -+/* No-Operation -+#define CLKCLR_P3_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P3_CLR 0x00020000 -+/** Clear Clock Enable P1 -+ Clears the clock enable bit of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define CLKCLR_P1 0x00010000 -+/* No-Operation -+#define CLKCLR_P1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_P1_CLR 0x00010000 -+/** Clear Clock Enable HOST -+ Clears the clock enable bit of the HOST domain. This domain contains the HOST interface block. */ -+#define CLKCLR_HOST 0x00008000 -+/* No-Operation -+#define CLKCLR_HOST_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_HOST_CLR 0x00008000 -+/** Clear Clock Enable I2C -+ Clears the clock enable bit of the I2C domain. This domain contains the I2C interface block. */ -+#define CLKCLR_I2C 0x00004000 -+/* No-Operation -+#define CLKCLR_I2C_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_I2C_CLR 0x00004000 -+/** Clear Clock Enable SSC0 -+ Clears the clock enable bit of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define CLKCLR_SSC0 0x00002000 -+/* No-Operation -+#define CLKCLR_SSC0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_SSC0_CLR 0x00002000 -+/** Clear Clock Enable ASC0 -+ Clears the clock enable bit of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define CLKCLR_ASC0 0x00001000 -+/* No-Operation -+#define CLKCLR_ASC0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_ASC0_CLR 0x00001000 -+/** Clear Clock Enable ASC1 -+ Clears the clock enable bit of the ASC1 domain. This domain contains the ASC1 block. */ -+#define CLKCLR_ASC1 0x00000800 -+/* No-Operation -+#define CLKCLR_ASC1_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_ASC1_CLR 0x00000800 -+/** Clear Clock Enable DCDCAPD -+ Clears the clock enable bit of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define CLKCLR_DCDCAPD 0x00000400 -+/* No-Operation -+#define CLKCLR_DCDCAPD_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDCAPD_CLR 0x00000400 -+/** Clear Clock Enable DCDCDDR -+ Clears the clock enable bit of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define CLKCLR_DCDCDDR 0x00000200 -+/* No-Operation -+#define CLKCLR_DCDCDDR_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDCDDR_CLR 0x00000200 -+/** Clear Clock Enable DCDC1V0 -+ Clears the clock enable bit of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define CLKCLR_DCDC1V0 0x00000100 -+/* No-Operation -+#define CLKCLR_DCDC1V0_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DCDC1V0_CLR 0x00000100 -+/** Clear Clock Enable TRC2MEM -+ Clears the clock enable bit of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define CLKCLR_TRC2MEM 0x00000040 -+/* No-Operation -+#define CLKCLR_TRC2MEM_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_TRC2MEM_CLR 0x00000040 -+/** Clear Clock Enable DDR -+ Clears the clock enable bit of the DDR domain. This domain contains the DDR interface block. */ -+#define CLKCLR_DDR 0x00000020 -+/* No-Operation -+#define CLKCLR_DDR_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_DDR_CLR 0x00000020 -+/** Clear Clock Enable EBU -+ Clears the clock enable bit of the EBU domain. This domain contains the EBU interface block. */ -+#define CLKCLR_EBU 0x00000010 -+/* No-Operation -+#define CLKCLR_EBU_NOP 0x00000000 */ -+/** Clear */ -+#define CLKCLR_EBU_CLR 0x00000010 -+ -+/* Fields of "Activation Status Register" */ -+/** STATUS Status -+ Shows the activation status of the STATUS domain. This domain contains the STATUS block. */ -+#define ACTS_STATUS 0x80000000 -+/* The block is inactive. -+#define ACTS_STATUS_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_STATUS_ACT 0x80000000 -+/** SHA1 Status -+ Shows the activation status of the SHA1 domain. This domain contains the SHA1 block. */ -+#define ACTS_SHA1 0x40000000 -+/* The block is inactive. -+#define ACTS_SHA1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_SHA1_ACT 0x40000000 -+/** AES Status -+ Shows the activation status of the AES domain. This domain contains the AES block. */ -+#define ACTS_AES 0x20000000 -+/* The block is inactive. -+#define ACTS_AES_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_AES_ACT 0x20000000 -+/** PCM Status -+ Shows the activation status of the PCM domain. This domain contains the PCM interface block. */ -+#define ACTS_PCM 0x10000000 -+/* The block is inactive. -+#define ACTS_PCM_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PCM_ACT 0x10000000 -+/** FSCT Status -+ Shows the activation status of the FSCT domain. This domain contains the FSCT block. */ -+#define ACTS_FSCT 0x08000000 -+/* The block is inactive. -+#define ACTS_FSCT_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_FSCT_ACT 0x08000000 -+/** GPTC Status -+ Shows the activation status of the GPTC domain. This domain contains the GPTC block. */ -+#define ACTS_GPTC 0x04000000 -+/* The block is inactive. -+#define ACTS_GPTC_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_GPTC_ACT 0x04000000 -+/** MPS Status -+ Shows the activation status of the MPS domain. This domain contains the MPS block. */ -+#define ACTS_MPS 0x02000000 -+/* The block is inactive. -+#define ACTS_MPS_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_MPS_ACT 0x02000000 -+/** DFEV0 Status -+ Shows the activation status of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define ACTS_DFEV0 0x01000000 -+/* The block is inactive. -+#define ACTS_DFEV0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DFEV0_ACT 0x01000000 -+/** PADCTRL4 Status -+ Shows the activation status of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define ACTS_PADCTRL4 0x00400000 -+/* The block is inactive. -+#define ACTS_PADCTRL4_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL4_ACT 0x00400000 -+/** PADCTRL3 Status -+ Shows the activation status of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define ACTS_PADCTRL3 0x00200000 -+/* The block is inactive. -+#define ACTS_PADCTRL3_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL3_ACT 0x00200000 -+/** PADCTRL1 Status -+ Shows the activation status of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define ACTS_PADCTRL1 0x00100000 -+/* The block is inactive. -+#define ACTS_PADCTRL1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_PADCTRL1_ACT 0x00100000 -+/** P4 Status -+ Shows the activation status of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define ACTS_P4 0x00040000 -+/* The block is inactive. -+#define ACTS_P4_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P4_ACT 0x00040000 -+/** P3 Status -+ Shows the activation status of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define ACTS_P3 0x00020000 -+/* The block is inactive. -+#define ACTS_P3_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P3_ACT 0x00020000 -+/** P1 Status -+ Shows the activation status of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define ACTS_P1 0x00010000 -+/* The block is inactive. -+#define ACTS_P1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_P1_ACT 0x00010000 -+/** HOST Status -+ Shows the activation status of the HOST domain. This domain contains the HOST interface block. */ -+#define ACTS_HOST 0x00008000 -+/* The block is inactive. -+#define ACTS_HOST_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_HOST_ACT 0x00008000 -+/** I2C Status -+ Shows the activation status of the I2C domain. This domain contains the I2C interface block. */ -+#define ACTS_I2C 0x00004000 -+/* The block is inactive. -+#define ACTS_I2C_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_I2C_ACT 0x00004000 -+/** SSC0 Status -+ Shows the activation status of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define ACTS_SSC0 0x00002000 -+/* The block is inactive. -+#define ACTS_SSC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_SSC0_ACT 0x00002000 -+/** ASC0 Status -+ Shows the activation status of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define ACTS_ASC0 0x00001000 -+/* The block is inactive. -+#define ACTS_ASC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_ASC0_ACT 0x00001000 -+/** ASC1 Status -+ Shows the activation status of the ASC1 domain. This domain contains the ASC1 block. */ -+#define ACTS_ASC1 0x00000800 -+/* The block is inactive. -+#define ACTS_ASC1_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_ASC1_ACT 0x00000800 -+/** DCDCAPD Status -+ Shows the activation status of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define ACTS_DCDCAPD 0x00000400 -+/* The block is inactive. -+#define ACTS_DCDCAPD_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDCAPD_ACT 0x00000400 -+/** DCDCDDR Status -+ Shows the activation status of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define ACTS_DCDCDDR 0x00000200 -+/* The block is inactive. -+#define ACTS_DCDCDDR_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDCDDR_ACT 0x00000200 -+/** DCDC1V0 Status -+ Shows the activation status of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define ACTS_DCDC1V0 0x00000100 -+/* The block is inactive. -+#define ACTS_DCDC1V0_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DCDC1V0_ACT 0x00000100 -+/** TRC2MEM Status -+ Shows the activation status of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define ACTS_TRC2MEM 0x00000040 -+/* The block is inactive. -+#define ACTS_TRC2MEM_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_TRC2MEM_ACT 0x00000040 -+/** DDR Status -+ Shows the activation status of the DDR domain. This domain contains the DDR interface block. */ -+#define ACTS_DDR 0x00000020 -+/* The block is inactive. -+#define ACTS_DDR_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_DDR_ACT 0x00000020 -+/** EBU Status -+ Shows the activation status of the EBU domain. This domain contains the EBU interface block. */ -+#define ACTS_EBU 0x00000010 -+/* The block is inactive. -+#define ACTS_EBU_INACT 0x00000000 */ -+/** The block is active. */ -+#define ACTS_EBU_ACT 0x00000010 -+ -+/* Fields of "Activation Register" */ -+/** Activate STATUS -+ Sets the activation flag of the STATUS domain. This domain contains the STATUS block. */ -+#define ACT_STATUS 0x80000000 -+/* No-Operation -+#define ACT_STATUS_NOP 0x00000000 */ -+/** Set */ -+#define ACT_STATUS_SET 0x80000000 -+/** Activate SHA1 -+ Sets the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ -+#define ACT_SHA1 0x40000000 -+/* No-Operation -+#define ACT_SHA1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_SHA1_SET 0x40000000 -+/** Activate AES -+ Sets the activation flag of the AES domain. This domain contains the AES block. */ -+#define ACT_AES 0x20000000 -+/* No-Operation -+#define ACT_AES_NOP 0x00000000 */ -+/** Set */ -+#define ACT_AES_SET 0x20000000 -+/** Activate PCM -+ Sets the activation flag of the PCM domain. This domain contains the PCM interface block. */ -+#define ACT_PCM 0x10000000 -+/* No-Operation -+#define ACT_PCM_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PCM_SET 0x10000000 -+/** Activate FSCT -+ Sets the activation flag of the FSCT domain. This domain contains the FSCT block. */ -+#define ACT_FSCT 0x08000000 -+/* No-Operation -+#define ACT_FSCT_NOP 0x00000000 */ -+/** Set */ -+#define ACT_FSCT_SET 0x08000000 -+/** Activate GPTC -+ Sets the activation flag of the GPTC domain. This domain contains the GPTC block. */ -+#define ACT_GPTC 0x04000000 -+/* No-Operation -+#define ACT_GPTC_NOP 0x00000000 */ -+/** Set */ -+#define ACT_GPTC_SET 0x04000000 -+/** Activate MPS -+ Sets the activation flag of the MPS domain. This domain contains the MPS block. */ -+#define ACT_MPS 0x02000000 -+/* No-Operation -+#define ACT_MPS_NOP 0x00000000 */ -+/** Set */ -+#define ACT_MPS_SET 0x02000000 -+/** Activate DFEV0 -+ Sets the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define ACT_DFEV0 0x01000000 -+/* No-Operation -+#define ACT_DFEV0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DFEV0_SET 0x01000000 -+/** Activate PADCTRL4 -+ Sets the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define ACT_PADCTRL4 0x00400000 -+/* No-Operation -+#define ACT_PADCTRL4_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL4_SET 0x00400000 -+/** Activate PADCTRL3 -+ Sets the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define ACT_PADCTRL3 0x00200000 -+/* No-Operation -+#define ACT_PADCTRL3_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL3_SET 0x00200000 -+/** Activate PADCTRL1 -+ Sets the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define ACT_PADCTRL1 0x00100000 -+/* No-Operation -+#define ACT_PADCTRL1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_PADCTRL1_SET 0x00100000 -+/** Activate P4 -+ Sets the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define ACT_P4 0x00040000 -+/* No-Operation -+#define ACT_P4_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P4_SET 0x00040000 -+/** Activate P3 -+ Sets the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define ACT_P3 0x00020000 -+/* No-Operation -+#define ACT_P3_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P3_SET 0x00020000 -+/** Activate P1 -+ Sets the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define ACT_P1 0x00010000 -+/* No-Operation -+#define ACT_P1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_P1_SET 0x00010000 -+/** Activate HOST -+ Sets the activation flag of the HOST domain. This domain contains the HOST interface block. */ -+#define ACT_HOST 0x00008000 -+/* No-Operation -+#define ACT_HOST_NOP 0x00000000 */ -+/** Set */ -+#define ACT_HOST_SET 0x00008000 -+/** Activate I2C -+ Sets the activation flag of the I2C domain. This domain contains the I2C interface block. */ -+#define ACT_I2C 0x00004000 -+/* No-Operation -+#define ACT_I2C_NOP 0x00000000 */ -+/** Set */ -+#define ACT_I2C_SET 0x00004000 -+/** Activate SSC0 -+ Sets the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define ACT_SSC0 0x00002000 -+/* No-Operation -+#define ACT_SSC0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_SSC0_SET 0x00002000 -+/** Activate ASC0 -+ Sets the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define ACT_ASC0 0x00001000 -+/* No-Operation -+#define ACT_ASC0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_ASC0_SET 0x00001000 -+/** Activate ASC1 -+ Sets the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ -+#define ACT_ASC1 0x00000800 -+/* No-Operation -+#define ACT_ASC1_NOP 0x00000000 */ -+/** Set */ -+#define ACT_ASC1_SET 0x00000800 -+/** Activate DCDCAPD -+ Sets the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define ACT_DCDCAPD 0x00000400 -+/* No-Operation -+#define ACT_DCDCAPD_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDCAPD_SET 0x00000400 -+/** Activate DCDCDDR -+ Sets the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define ACT_DCDCDDR 0x00000200 -+/* No-Operation -+#define ACT_DCDCDDR_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDCDDR_SET 0x00000200 -+/** Activate DCDC1V0 -+ Sets the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define ACT_DCDC1V0 0x00000100 -+/* No-Operation -+#define ACT_DCDC1V0_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DCDC1V0_SET 0x00000100 -+/** Activate TRC2MEM -+ Sets the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define ACT_TRC2MEM 0x00000040 -+/* No-Operation -+#define ACT_TRC2MEM_NOP 0x00000000 */ -+/** Set */ -+#define ACT_TRC2MEM_SET 0x00000040 -+/** Activate DDR -+ Sets the activation flag of the DDR domain. This domain contains the DDR interface block. */ -+#define ACT_DDR 0x00000020 -+/* No-Operation -+#define ACT_DDR_NOP 0x00000000 */ -+/** Set */ -+#define ACT_DDR_SET 0x00000020 -+/** Activate EBU -+ Sets the activation flag of the EBU domain. This domain contains the EBU interface block. */ -+#define ACT_EBU 0x00000010 -+/* No-Operation -+#define ACT_EBU_NOP 0x00000000 */ -+/** Set */ -+#define ACT_EBU_SET 0x00000010 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate STATUS -+ Clears the activation flag of the STATUS domain. This domain contains the STATUS block. */ -+#define DEACT_STATUS 0x80000000 -+/* No-Operation -+#define DEACT_STATUS_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_STATUS_CLR 0x80000000 -+/** Deactivate SHA1 -+ Clears the activation flag of the SHA1 domain. This domain contains the SHA1 block. */ -+#define DEACT_SHA1 0x40000000 -+/* No-Operation -+#define DEACT_SHA1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_SHA1_CLR 0x40000000 -+/** Deactivate AES -+ Clears the activation flag of the AES domain. This domain contains the AES block. */ -+#define DEACT_AES 0x20000000 -+/* No-Operation -+#define DEACT_AES_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_AES_CLR 0x20000000 -+/** Deactivate PCM -+ Clears the activation flag of the PCM domain. This domain contains the PCM interface block. */ -+#define DEACT_PCM 0x10000000 -+/* No-Operation -+#define DEACT_PCM_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PCM_CLR 0x10000000 -+/** Deactivate FSCT -+ Clears the activation flag of the FSCT domain. This domain contains the FSCT block. */ -+#define DEACT_FSCT 0x08000000 -+/* No-Operation -+#define DEACT_FSCT_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_FSCT_CLR 0x08000000 -+/** Deactivate GPTC -+ Clears the activation flag of the GPTC domain. This domain contains the GPTC block. */ -+#define DEACT_GPTC 0x04000000 -+/* No-Operation -+#define DEACT_GPTC_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_GPTC_CLR 0x04000000 -+/** Deactivate MPS -+ Clears the activation flag of the MPS domain. This domain contains the MPS block. */ -+#define DEACT_MPS 0x02000000 -+/* No-Operation -+#define DEACT_MPS_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_MPS_CLR 0x02000000 -+/** Deactivate DFEV0 -+ Clears the activation flag of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define DEACT_DFEV0 0x01000000 -+/* No-Operation -+#define DEACT_DFEV0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DFEV0_CLR 0x01000000 -+/** Deactivate PADCTRL4 -+ Clears the activation flag of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define DEACT_PADCTRL4 0x00400000 -+/* No-Operation -+#define DEACT_PADCTRL4_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL4_CLR 0x00400000 -+/** Deactivate PADCTRL3 -+ Clears the activation flag of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define DEACT_PADCTRL3 0x00200000 -+/* No-Operation -+#define DEACT_PADCTRL3_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL3_CLR 0x00200000 -+/** Deactivate PADCTRL1 -+ Clears the activation flag of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define DEACT_PADCTRL1 0x00100000 -+/* No-Operation -+#define DEACT_PADCTRL1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_PADCTRL1_CLR 0x00100000 -+/** Deactivate P4 -+ Clears the activation flag of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define DEACT_P4 0x00040000 -+/* No-Operation -+#define DEACT_P4_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P4_CLR 0x00040000 -+/** Deactivate P3 -+ Clears the activation flag of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define DEACT_P3 0x00020000 -+/* No-Operation -+#define DEACT_P3_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P3_CLR 0x00020000 -+/** Deactivate P1 -+ Clears the activation flag of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define DEACT_P1 0x00010000 -+/* No-Operation -+#define DEACT_P1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_P1_CLR 0x00010000 -+/** Deactivate HOST -+ Clears the activation flag of the HOST domain. This domain contains the HOST interface block. */ -+#define DEACT_HOST 0x00008000 -+/* No-Operation -+#define DEACT_HOST_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_HOST_CLR 0x00008000 -+/** Deactivate I2C -+ Clears the activation flag of the I2C domain. This domain contains the I2C interface block. */ -+#define DEACT_I2C 0x00004000 -+/* No-Operation -+#define DEACT_I2C_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_I2C_CLR 0x00004000 -+/** Deactivate SSC0 -+ Clears the activation flag of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define DEACT_SSC0 0x00002000 -+/* No-Operation -+#define DEACT_SSC0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_SSC0_CLR 0x00002000 -+/** Deactivate ASC0 -+ Clears the activation flag of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define DEACT_ASC0 0x00001000 -+/* No-Operation -+#define DEACT_ASC0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_ASC0_CLR 0x00001000 -+/** Deactivate ASC1 -+ Clears the activation flag of the ASC1 domain. This domain contains the ASC1 block. */ -+#define DEACT_ASC1 0x00000800 -+/* No-Operation -+#define DEACT_ASC1_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_ASC1_CLR 0x00000800 -+/** Deactivate DCDCAPD -+ Clears the activation flag of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define DEACT_DCDCAPD 0x00000400 -+/* No-Operation -+#define DEACT_DCDCAPD_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDCAPD_CLR 0x00000400 -+/** Deactivate DCDCDDR -+ Clears the activation flag of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define DEACT_DCDCDDR 0x00000200 -+/* No-Operation -+#define DEACT_DCDCDDR_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDCDDR_CLR 0x00000200 -+/** Deactivate DCDC1V0 -+ Clears the activation flag of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define DEACT_DCDC1V0 0x00000100 -+/* No-Operation -+#define DEACT_DCDC1V0_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DCDC1V0_CLR 0x00000100 -+/** Deactivate TRC2MEM -+ Clears the activation flag of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define DEACT_TRC2MEM 0x00000040 -+/* No-Operation -+#define DEACT_TRC2MEM_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_TRC2MEM_CLR 0x00000040 -+/** Deactivate DDR -+ Clears the activation flag of the DDR domain. This domain contains the DDR interface block. */ -+#define DEACT_DDR 0x00000020 -+/* No-Operation -+#define DEACT_DDR_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_DDR_CLR 0x00000020 -+/** Deactivate EBU -+ Clears the activation flag of the EBU domain. This domain contains the EBU interface block. */ -+#define DEACT_EBU 0x00000010 -+/* No-Operation -+#define DEACT_EBU_NOP 0x00000000 */ -+/** Clear */ -+#define DEACT_EBU_CLR 0x00000010 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot STATUS -+ Triggers a reboot of the STATUS domain. This domain contains the STATUS block. */ -+#define RBT_STATUS 0x80000000 -+/* No-Operation -+#define RBT_STATUS_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_STATUS_TRIG 0x80000000 -+/** Reboot SHA1 -+ Triggers a reboot of the SHA1 domain. This domain contains the SHA1 block. */ -+#define RBT_SHA1 0x40000000 -+/* No-Operation -+#define RBT_SHA1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_SHA1_TRIG 0x40000000 -+/** Reboot AES -+ Triggers a reboot of the AES domain. This domain contains the AES block. */ -+#define RBT_AES 0x20000000 -+/* No-Operation -+#define RBT_AES_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_AES_TRIG 0x20000000 -+/** Reboot PCM -+ Triggers a reboot of the PCM domain. This domain contains the PCM interface block. */ -+#define RBT_PCM 0x10000000 -+/* No-Operation -+#define RBT_PCM_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PCM_TRIG 0x10000000 -+/** Reboot FSCT -+ Triggers a reboot of the FSCT domain. This domain contains the FSCT block. */ -+#define RBT_FSCT 0x08000000 -+/* No-Operation -+#define RBT_FSCT_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_FSCT_TRIG 0x08000000 -+/** Reboot GPTC -+ Triggers a reboot of the GPTC domain. This domain contains the GPTC block. */ -+#define RBT_GPTC 0x04000000 -+/* No-Operation -+#define RBT_GPTC_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_GPTC_TRIG 0x04000000 -+/** Reboot MPS -+ Triggers a reboot of the MPS domain. This domain contains the MPS block. */ -+#define RBT_MPS 0x02000000 -+/* No-Operation -+#define RBT_MPS_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_MPS_TRIG 0x02000000 -+/** Reboot DFEV0 -+ Triggers a reboot of the DFEV0 domain. This domain contains the DFEV0 block. */ -+#define RBT_DFEV0 0x01000000 -+/* No-Operation -+#define RBT_DFEV0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DFEV0_TRIG 0x01000000 -+/** Reboot PADCTRL4 -+ Triggers a reboot of the PADCTRL4 domain. This domain contains the PADCTRL4 block. */ -+#define RBT_PADCTRL4 0x00400000 -+/* No-Operation -+#define RBT_PADCTRL4_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL4_TRIG 0x00400000 -+/** Reboot PADCTRL3 -+ Triggers a reboot of the PADCTRL3 domain. This domain contains the PADCTRL3 block. */ -+#define RBT_PADCTRL3 0x00200000 -+/* No-Operation -+#define RBT_PADCTRL3_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL3_TRIG 0x00200000 -+/** Reboot PADCTRL1 -+ Triggers a reboot of the PADCTRL1 domain. This domain contains the PADCTRL1 block. */ -+#define RBT_PADCTRL1 0x00100000 -+/* No-Operation -+#define RBT_PADCTRL1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_PADCTRL1_TRIG 0x00100000 -+/** Reboot P4 -+ Triggers a reboot of the P4 domain. This domain contains the P4 instance of the GPIO block. */ -+#define RBT_P4 0x00040000 -+/* No-Operation -+#define RBT_P4_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P4_TRIG 0x00040000 -+/** Reboot P3 -+ Triggers a reboot of the P3 domain. This domain contains the P3 instance of the GPIO block. */ -+#define RBT_P3 0x00020000 -+/* No-Operation -+#define RBT_P3_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P3_TRIG 0x00020000 -+/** Reboot P1 -+ Triggers a reboot of the P1 domain. This domain contains the P1 instance of the GPIO block. */ -+#define RBT_P1 0x00010000 -+/* No-Operation -+#define RBT_P1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_P1_TRIG 0x00010000 -+/** Reboot HOST -+ Triggers a reboot of the HOST domain. This domain contains the HOST interface block. */ -+#define RBT_HOST 0x00008000 -+/* No-Operation -+#define RBT_HOST_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_HOST_TRIG 0x00008000 -+/** Reboot I2C -+ Triggers a reboot of the I2C domain. This domain contains the I2C interface block. */ -+#define RBT_I2C 0x00004000 -+/* No-Operation -+#define RBT_I2C_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_I2C_TRIG 0x00004000 -+/** Reboot SSC0 -+ Triggers a reboot of the SSC0 domain. This domain contains the SSC0 interface block. */ -+#define RBT_SSC0 0x00002000 -+/* No-Operation -+#define RBT_SSC0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_SSC0_TRIG 0x00002000 -+/** Reboot ASC0 -+ Triggers a reboot of the ASC0 domain. This domain contains the ASC0 interface block. */ -+#define RBT_ASC0 0x00001000 -+/* No-Operation -+#define RBT_ASC0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_ASC0_TRIG 0x00001000 -+/** Reboot ASC1 -+ Triggers a reboot of the ASC1 domain. This domain contains the ASC1 block. */ -+#define RBT_ASC1 0x00000800 -+/* No-Operation -+#define RBT_ASC1_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_ASC1_TRIG 0x00000800 -+/** Reboot DCDCAPD -+ Triggers a reboot of the DCDCAPD domain. This domain contains the digital part of the 60 volts DCDC converter. */ -+#define RBT_DCDCAPD 0x00000400 -+/* No-Operation -+#define RBT_DCDCAPD_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDCAPD_TRIG 0x00000400 -+/** Reboot DCDCDDR -+ Triggers a reboot of the DCDCDDR domain. This domain contains the digital part of the DCDC converter dedicated to the DDR interface. */ -+#define RBT_DCDCDDR 0x00000200 -+/* No-Operation -+#define RBT_DCDCDDR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDCDDR_TRIG 0x00000200 -+/** Reboot DCDC1V0 -+ Triggers a reboot of the DCDC1V0 domain. This domain contains the digital part of the 1.0 volts DCDC converter. */ -+#define RBT_DCDC1V0 0x00000100 -+/* No-Operation -+#define RBT_DCDC1V0_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DCDC1V0_TRIG 0x00000100 -+/** Reboot TRC2MEM -+ Triggers a reboot of the TRC2MEM domain. This domain contains the TRC2MEM block. */ -+#define RBT_TRC2MEM 0x00000040 -+/* No-Operation -+#define RBT_TRC2MEM_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_TRC2MEM_TRIG 0x00000040 -+/** Reboot DDR -+ Triggers a reboot of the DDR domain. This domain contains the DDR interface block. */ -+#define RBT_DDR 0x00000020 -+/* No-Operation -+#define RBT_DDR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_DDR_TRIG 0x00000020 -+/** Reboot EBU -+ Triggers a reboot of the EBU domain. This domain contains the EBU interface block. */ -+#define RBT_EBU 0x00000010 -+/* No-Operation -+#define RBT_EBU_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_EBU_TRIG 0x00000010 -+/** Reboot XBAR -+ Triggers a reboot of the XBAR. */ -+#define RBT_XBAR 0x00000002 -+/* No-Operation -+#define RBT_XBAR_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_XBAR_TRIG 0x00000002 -+/** Reboot CPU -+ Triggers a reboot of the CPU. */ -+#define RBT_CPU 0x00000001 -+/* No-Operation -+#define RBT_CPU_NOP 0x00000000 */ -+/** Trigger */ -+#define RBT_CPU_TRIG 0x00000001 -+ -+/* Fields of "CPU0 Clock Control Register" */ -+/** CPU Clock Divider -+ Via this bit the divider and therefore the frequency of the clock of CPU0 can be selected. */ -+#define CPU0CC_CPUDIV 0x00000001 -+/* Frequency set to the nominal value. -+#define CPU0CC_CPUDIV_SELFNOM 0x00000000 */ -+/** Frequency set to half of its nominal value. */ -+#define CPU0CC_CPUDIV_SELFHALF 0x00000001 -+ -+/* Fields of "CPU0 Reset Source Register" */ -+/** Software Reboot Request Occurred -+ This bit can be acknowledged by a write operation. */ -+#define CPU0RS_SWRRO 0x00000004 -+/* Nothing -+#define CPU0RS_SWRRO_NULL 0x00000000 */ -+/** Write: Acknowledge the event. */ -+#define CPU0RS_SWRRO_EVACK 0x00000004 -+/** Read: Event occurred. */ -+#define CPU0RS_SWRRO_EVOCC 0x00000004 -+/** Hardware Reset Source -+ Reflects the root cause for the last hardware reset. The infrastructure-block is only reset in case of POR. For all other blocks there is no difference between the three HW-reset sources. */ -+#define CPU0RS_HWRS_MASK 0x00000003 -+/** field offset */ -+#define CPU0RS_HWRS_OFFSET 0 -+/** Power-on reset. */ -+#define CPU0RS_HWRS_POR 0x00000000 -+/** RST pin. */ -+#define CPU0RS_HWRS_RST 0x00000001 -+/** Watchdog reset request. */ -+#define CPU0RS_HWRS_WDT 0x00000002 -+ -+/* Fields of "CPU0 Wakeup Configuration Register" */ -+/** Wakeup Request Source Yield Resume 15 -+ Select the signal connected to the yield/resume interface pin 15 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR15 0x80000000 -+/* Not selected -+#define CPU0WCFG_WRSYR15_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR15_SEL 0x80000000 -+/** Wakeup Request Source Yield Resume 14 -+ Select the signal connected to the yield/resume interface pin 14 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR14 0x40000000 -+/* Not selected -+#define CPU0WCFG_WRSYR14_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR14_SEL 0x40000000 -+/** Wakeup Request Source Yield Resume 13 -+ Select the signal connected to the yield/resume interface pin 13 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR13 0x20000000 -+/* Not selected -+#define CPU0WCFG_WRSYR13_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR13_SEL 0x20000000 -+/** Wakeup Request Source Yield Resume 12 -+ Select the signal connected to the yield/resume interface pin 12 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR12 0x10000000 -+/* Not selected -+#define CPU0WCFG_WRSYR12_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR12_SEL 0x10000000 -+/** Wakeup Request Source Yield Resume 11 -+ Select the signal connected to the yield/resume interface pin 11 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR11 0x08000000 -+/* Not selected -+#define CPU0WCFG_WRSYR11_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR11_SEL 0x08000000 -+/** Wakeup Request Source Yield Resume 10 -+ Select the signal connected to the yield/resume interface pin 10 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR10 0x04000000 -+/* Not selected -+#define CPU0WCFG_WRSYR10_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR10_SEL 0x04000000 -+/** Wakeup Request Source Yield Resume 9 -+ Select the signal connected to the yield/resume interface pin 9 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR9 0x02000000 -+/* Not selected -+#define CPU0WCFG_WRSYR9_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR9_SEL 0x02000000 -+/** Wakeup Request Source Yield Resume 8 -+ Select the signal connected to the yield/resume interface pin 8 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR8 0x01000000 -+/* Not selected -+#define CPU0WCFG_WRSYR8_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR8_SEL 0x01000000 -+/** Wakeup Request Source Yield Resume 7 -+ Select the signal connected to the yield/resume interface pin 7 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR7 0x00800000 -+/* Not selected -+#define CPU0WCFG_WRSYR7_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR7_SEL 0x00800000 -+/** Wakeup Request Source Yield Resume 6 -+ Select the signal connected to the yield/resume interface pin 6 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR6 0x00400000 -+/* Not selected -+#define CPU0WCFG_WRSYR6_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR6_SEL 0x00400000 -+/** Wakeup Request Source Yield Resume 5 -+ Select the signal connected to the yield/resume interface pin 5 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR5 0x00200000 -+/* Not selected -+#define CPU0WCFG_WRSYR5_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR5_SEL 0x00200000 -+/** Wakeup Request Source Yield Resume 4 -+ Select the signal connected to the yield/resume interface pin 4 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR4 0x00100000 -+/* Not selected -+#define CPU0WCFG_WRSYR4_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR4_SEL 0x00100000 -+/** Wakeup Request Source Yield Resume 3 -+ Select the signal connected to the yield/resume interface pin 3 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR3 0x00080000 -+/* Not selected -+#define CPU0WCFG_WRSYR3_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR3_SEL 0x00080000 -+/** Wakeup Request Source Yield Resume 2 -+ Select the signal connected to the yield/resume interface pin 2 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR2 0x00040000 -+/* Not selected -+#define CPU0WCFG_WRSYR2_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR2_SEL 0x00040000 -+/** Wakeup Request Source Yield Resume 1 -+ Select the signal connected to the yield/resume interface pin 1 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR1 0x00020000 -+/* Not selected -+#define CPU0WCFG_WRSYR1_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR1_SEL 0x00020000 -+/** Wakeup Request Source Yield Resume 0 -+ Select the signal connected to the yield/resume interface pin 0 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSYR0 0x00010000 -+/* Not selected -+#define CPU0WCFG_WRSYR0_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSYR0_SEL 0x00010000 -+/** Wakeup Request Source Debug -+ Select signal EJ_DINT as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSDBG 0x00000100 -+/* Not selected -+#define CPU0WCFG_WRSDBG_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSDBG_SEL 0x00000100 -+/** Wakeup Request Source ICU of VPE1 -+ Select signal ICU_IRQ of VPE1 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSICUVPE1 0x00000002 -+/* Not selected -+#define CPU0WCFG_WRSICUVPE1_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSICUVPE1_SEL 0x00000002 -+/** Wakeup Request Source ICU of VPE0 -+ Select signal ICU_IRQ of VPE0 as source for wakeup from sleep state. */ -+#define CPU0WCFG_WRSICUVPE0 0x00000001 -+/* Not selected -+#define CPU0WCFG_WRSICUVPE0_NSEL 0x00000000 */ -+/** Selected */ -+#define CPU0WCFG_WRSICUVPE0_SEL 0x00000001 -+ -+/* Fields of "Bootmode Control Register" */ -+/** Software Bootmode Select -+ Enables SW writing of Bootmode and shows whether or not the SW-programmed bootmode is reflected in field Bootmode instead of the hardware given value. */ -+#define BMC_BMSW 0x80000000 -+/* Disable -+#define BMC_BMSW_DIS 0x00000000 */ -+/** Enable */ -+#define BMC_BMSW_EN 0x80000000 -+/** Bootmode -+ Initially this field holds the value of the pinstraps LED_BMODEx on positions 5:0, and the value of the corresponding JTAG register bit on position 6. Writing is enabled by setting Software Bootmode Select to 1 during the write cycle. */ -+#define BMC_BM_MASK 0x0000007F -+/** field offset */ -+#define BMC_BM_OFFSET 0 -+ -+/* Fields of "Sleep Configuration Register" */ -+/** Enable XBAR Clockoff When All XBAR masters Clockoff -+ Enable XBAR clock shutdown in case all XBAR masters are in clockoff mode. This bit has no effect if bit CPU0 is not enabled. */ -+#define SCFG_XBAR 0x00010000 -+/* Disable -+#define SCFG_XBAR_DIS 0x00000000 */ -+/** Enable */ -+#define SCFG_XBAR_EN 0x00010000 -+/** CPU0 Clockoff On Sleep -+ Enable CPU0 clock shutdown in case its SI_SLEEP signal becomes active. */ -+#define SCFG_CPU0 0x00000001 -+/* Disable -+#define SCFG_CPU0_DIS 0x00000000 */ -+/** Enable */ -+#define SCFG_CPU0_EN 0x00000001 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down STATUS -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_STATUS 0x80000000 -+/* Disable -+#define PDCFG_STATUS_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_STATUS_EN 0x80000000 -+/** Enable Power Down SHA1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_SHA1 0x40000000 -+/* Disable -+#define PDCFG_SHA1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_SHA1_EN 0x40000000 -+/** Enable Power Down AES -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_AES 0x20000000 -+/* Disable -+#define PDCFG_AES_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_AES_EN 0x20000000 -+/** Enable Power Down PCM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PCM 0x10000000 -+/* Disable -+#define PDCFG_PCM_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PCM_EN 0x10000000 -+/** Enable Power Down FSCT -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_FSCT 0x08000000 -+/* Disable -+#define PDCFG_FSCT_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_FSCT_EN 0x08000000 -+/** Enable Power Down GPTC -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_GPTC 0x04000000 -+/* Disable -+#define PDCFG_GPTC_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_GPTC_EN 0x04000000 -+/** Enable Power Down MPS -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_MPS 0x02000000 -+/* Disable -+#define PDCFG_MPS_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_MPS_EN 0x02000000 -+/** Enable Power Down DFEV0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DFEV0 0x01000000 -+/* Disable -+#define PDCFG_DFEV0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DFEV0_EN 0x01000000 -+/** Enable Power Down PADCTRL4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL4 0x00400000 -+/* Disable -+#define PDCFG_PADCTRL4_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL4_EN 0x00400000 -+/** Enable Power Down PADCTRL3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL3 0x00200000 -+/* Disable -+#define PDCFG_PADCTRL3_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL3_EN 0x00200000 -+/** Enable Power Down PADCTRL1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_PADCTRL1 0x00100000 -+/* Disable -+#define PDCFG_PADCTRL1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_PADCTRL1_EN 0x00100000 -+/** Enable Power Down P4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P4 0x00040000 -+/* Disable -+#define PDCFG_P4_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P4_EN 0x00040000 -+/** Enable Power Down P3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P3 0x00020000 -+/* Disable -+#define PDCFG_P3_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P3_EN 0x00020000 -+/** Enable Power Down P1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_P1 0x00010000 -+/* Disable -+#define PDCFG_P1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_P1_EN 0x00010000 -+/** Enable Power Down HOST -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_HOST 0x00008000 -+/* Disable -+#define PDCFG_HOST_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_HOST_EN 0x00008000 -+/** Enable Power Down I2C -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_I2C 0x00004000 -+/* Disable -+#define PDCFG_I2C_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_I2C_EN 0x00004000 -+/** Enable Power Down SSC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_SSC0 0x00002000 -+/* Disable -+#define PDCFG_SSC0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_SSC0_EN 0x00002000 -+/** Enable Power Down ASC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_ASC0 0x00001000 -+/* Disable -+#define PDCFG_ASC0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_ASC0_EN 0x00001000 -+/** Enable Power Down ASC1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_ASC1 0x00000800 -+/* Disable -+#define PDCFG_ASC1_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_ASC1_EN 0x00000800 -+/** Enable Power Down DCDCAPD -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDCAPD 0x00000400 -+/* Disable -+#define PDCFG_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDCAPD_EN 0x00000400 -+/** Enable Power Down DCDCDDR -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDCDDR 0x00000200 -+/* Disable -+#define PDCFG_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDCDDR_EN 0x00000200 -+/** Enable Power Down DCDC1V0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DCDC1V0 0x00000100 -+/* Disable -+#define PDCFG_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DCDC1V0_EN 0x00000100 -+/** Enable Power Down TRC2MEM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_TRC2MEM 0x00000040 -+/* Disable -+#define PDCFG_TRC2MEM_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_TRC2MEM_EN 0x00000040 -+/** Enable Power Down DDR -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_DDR 0x00000020 -+/* Disable -+#define PDCFG_DDR_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_DDR_EN 0x00000020 -+/** Enable Power Down EBU -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define PDCFG_EBU 0x00000010 -+/* Disable -+#define PDCFG_EBU_DIS 0x00000000 */ -+/** Enable */ -+#define PDCFG_EBU_EN 0x00000010 -+ -+/* Fields of "CLKO Pad Control Register" */ -+/** Ethernet Reference Clock CLKO Select -+ Selects the CLKO pad's input as source for the GPHY, SGMII PLLs. */ -+#define CLKOC_ETHREF 0x00000002 -+/* Not selected -+#define CLKOC_ETHREF_NSEL 0x00000000 */ -+/** Selected */ -+#define CLKOC_ETHREF_SEL 0x00000002 -+/** Output Enable -+ Enables the output driver of the CLKO pad. */ -+#define CLKOC_OEN 0x00000001 -+/* Disable -+#define CLKOC_OEN_DIS 0x00000000 */ -+/** Enable */ -+#define CLKOC_OEN_EN 0x00000001 -+ -+/* Fields of "Infrastructure Control Register" */ -+/** General Purpose Control -+ Backup bits. Currently they are connected as: bit 0 : connected to the configmode_on pin of the pinstrapping block. bit 1 : clock enable of the GPE primary clock. bits 3:2 : frequency select of the GPE primary clock. 00 = 769.2MHz, 01 = 625MHz, 10 = 555.6MHz, 11 = 500MHz All other bits are unconnected. */ -+#define INFRAC_GP_MASK 0x1F000000 -+/** field offset */ -+#define INFRAC_GP_OFFSET 24 -+/** CMOS2CML Ethernet Control -+ CMOS2CML Ethernet Control. */ -+#define INFRAC_CMOS2CML_GPON_MASK 0x0000F000 -+/** field offset */ -+#define INFRAC_CMOS2CML_GPON_OFFSET 12 -+/** CMOS2CML Ethernet Control -+ CMOS2CML Ethernet Control. */ -+#define INFRAC_CMOS2CML_ETH_MASK 0x00000F00 -+/** field offset */ -+#define INFRAC_CMOS2CML_ETH_OFFSET 8 -+/** Dying Gasp Enable -+ Enables the dying gasp detector. */ -+#define INFRAC_DGASPEN 0x00000040 -+/* Disable -+#define INFRAC_DGASPEN_DIS 0x00000000 */ -+/** Enable */ -+#define INFRAC_DGASPEN_EN 0x00000040 -+/** Dying Gasp Hysteresis Control -+ Dying Gasp Hysteresis Control. */ -+#define INFRAC_DGASPHYS_MASK 0x00000030 -+/** field offset */ -+#define INFRAC_DGASPHYS_OFFSET 4 -+/** Linear Regulator 1.5V Enable -+ Enables 1.5V linear regulator. */ -+#define INFRAC_LIN1V5EN 0x00000008 -+/* Disable -+#define INFRAC_LIN1V5EN_DIS 0x00000000 */ -+/** Enable */ -+#define INFRAC_LIN1V5EN_EN 0x00000008 -+/** Linear Regulator 1.5V Control -+ Linear regulator 1.5V control. */ -+#define INFRAC_LIN1V5C_MASK 0x00000007 -+/** field offset */ -+#define INFRAC_LIN1V5C_OFFSET 0 -+ -+/* Fields of "HRST_OUT_N Control Register" */ -+/** HRST_OUT_N Pin Value -+ Controls the value of the HRST_OUT_N pin. */ -+#define HRSTOUTC_VALUE 0x00000001 -+ -+/* Fields of "EBU Clock Control Register" */ -+/** EBU Clock Divider -+ Via this bit the frequency of the clock of the EBU can be selected. */ -+#define EBUCC_EBUDIV 0x00000001 -+/* Frequency set to 50MHz. -+#define EBUCC_EBUDIV_SELF50 0x00000000 */ -+/** Frequency set to 100MHz. */ -+#define EBUCC_EBUDIV_SELF100 0x00000001 -+ -+/* Fields of "NMI Status Register" */ -+/** NMI Status Flag TEST -+ Shows whether the event NMI TEST occurred. */ -+#define NMIS_TEST 0x00000100 -+/* Nothing -+#define NMIS_TEST_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_TEST_EVOCC 0x00000100 -+/** NMI Status Flag DGASP -+ Shows whether the event NMI DGASP occurred. */ -+#define NMIS_DGASP 0x00000004 -+/* Nothing -+#define NMIS_DGASP_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_DGASP_EVOCC 0x00000004 -+/** NMI Status Flag HOST -+ Shows whether the event NMI HOST occurred. */ -+#define NMIS_HOST 0x00000002 -+/* Nothing -+#define NMIS_HOST_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_HOST_EVOCC 0x00000002 -+/** NMI Status Flag PIN -+ Shows whether the event NMI PIN occurred. */ -+#define NMIS_PIN 0x00000001 -+/* Nothing -+#define NMIS_PIN_NULL 0x00000000 */ -+/** Read: Event occurred. */ -+#define NMIS_PIN_EVOCC 0x00000001 -+ -+/* Fields of "NMI Set Register" */ -+/** Set NMI Status Flag TEST -+ Sets the corresponding NMI status flag. */ -+#define NMISET_TEST 0x00000100 -+/* Nothing -+#define NMISET_TEST_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_TEST_SET 0x00000100 -+/** Set NMI Status Flag DGASP -+ Sets the corresponding NMI status flag. */ -+#define NMISET_DGASP 0x00000004 -+/* Nothing -+#define NMISET_DGASP_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_DGASP_SET 0x00000004 -+/** Set NMI Status Flag HOST -+ Sets the corresponding NMI status flag. */ -+#define NMISET_HOST 0x00000002 -+/* Nothing -+#define NMISET_HOST_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_HOST_SET 0x00000002 -+/** Set NMI Status Flag PIN -+ Sets the corresponding NMI status flag. */ -+#define NMISET_PIN 0x00000001 -+/* Nothing -+#define NMISET_PIN_NULL 0x00000000 */ -+/** Set */ -+#define NMISET_PIN_SET 0x00000001 -+ -+/* Fields of "NMI Clear Register" */ -+/** Clear NMI Status Flag TEST -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_TEST 0x00000100 -+/* Nothing -+#define NMICLR_TEST_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_TEST_CLR 0x00000100 -+/** Clear NMI Status Flag DGASP -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_DGASP 0x00000004 -+/* Nothing -+#define NMICLR_DGASP_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_DGASP_CLR 0x00000004 -+/** Clear NMI Status Flag HOST -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_HOST 0x00000002 -+/* Nothing -+#define NMICLR_HOST_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_HOST_CLR 0x00000002 -+/** Clear NMI Status Flag PIN -+ Clears the corresponding NMI status flag. */ -+#define NMICLR_PIN 0x00000001 -+/* Nothing -+#define NMICLR_PIN_NULL 0x00000000 */ -+/** Clear */ -+#define NMICLR_PIN_CLR 0x00000001 -+ -+/* Fields of "NMI Test Configuration Register" */ -+/** Enable NMI Test Feature -+ Enables the operation of the NMI TEST flag. This is the mask for the Non-Maskable-Interrupt dedicated to SW tests. All others cannot be masked. */ -+#define NMITCFG_TEN 0x00000100 -+/* Disable -+#define NMITCFG_TEN_DIS 0x00000000 */ -+/** Enable */ -+#define NMITCFG_TEN_EN 0x00000100 -+ -+/* Fields of "NMI VPE1 Control Register" */ -+/** NMI VPE1 State -+ Reflects the state of the NMI signal towards VPE1. This bit is controlled by software only, there is no hardware NMI source dedicated to VPE1. So VPE0 could trigger an NMI at VPE1 using this bit in its own NMI-routine. */ -+#define NMIVPE1C_NMI 0x00000001 -+/* False -+#define NMIVPE1C_NMI_FALSE 0x00000000 */ -+/** True */ -+#define NMIVPE1C_NMI_TRUE 0x00000001 -+ -+/* Fields of "IRN Capture Register" */ -+/** DCDCAPD Alarm -+ The DCDC Converter for the APD Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDCAPD 0x00400000 -+/* Nothing -+#define IRNCR_DCDCAPD_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDCAPD_INTACK 0x00400000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDCAPD_INTOCC 0x00400000 -+/** DCDCDDR Alarm -+ The DCDC Converter for the DDR Supply submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDCDDR 0x00200000 -+/* Nothing -+#define IRNCR_DCDCDDR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDCDDR_INTACK 0x00200000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDCDDR_INTOCC 0x00200000 -+/** DCDC1V0 Alarm -+ The DCDC Converter for the 1.0 Volts submitted an alarm. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_DCDC1V0 0x00100000 -+/* Nothing -+#define IRNCR_DCDC1V0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_DCDC1V0_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_DCDC1V0_INTOCC 0x00100000 -+/** SIF0 wakeup request -+ SmartSlic Interface 0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define IRNCR_SIF0 0x00010000 -+/* Nothing -+#define IRNCR_SIF0_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define IRNCR_SIF0_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define IRNCR_SIF0_INTOCC 0x00010000 -+ -+/* Fields of "IRN Interrupt Control Register" */ -+/** DCDCAPD Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDCAPD 0x00400000 -+/** DCDCDDR Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDCDDR 0x00200000 -+/** DCDC1V0 Alarm -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_DCDC1V0 0x00100000 -+/** SIF0 wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCR register. */ -+#define IRNICR_SIF0 0x00010000 -+ -+/* Fields of "IRN Interrupt Enable Register" */ -+/** DCDCAPD Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDCAPD 0x00400000 -+/* Disable -+#define IRNEN_DCDCAPD_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDCAPD_EN 0x00400000 -+/** DCDCDDR Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDCDDR 0x00200000 -+/* Disable -+#define IRNEN_DCDCDDR_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDCDDR_EN 0x00200000 -+/** DCDC1V0 Alarm -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_DCDC1V0 0x00100000 -+/* Disable -+#define IRNEN_DCDC1V0_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_DCDC1V0_EN 0x00100000 -+/** SIF0 wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCR register. */ -+#define IRNEN_SIF0 0x00010000 -+/* Disable -+#define IRNEN_SIF0_DIS 0x00000000 */ -+/** Enable */ -+#define IRNEN_SIF0_EN 0x00010000 -+ -+/*! @} */ /* SYS1_REGISTER */ -+ -+#endif /* _sys1_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h -new file mode 100644 -index 0000000..e1777e5 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_eth_reg.h -@@ -0,0 +1,1132 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys_eth_reg_h -+#define _sys_eth_reg_h -+ -+/** \addtogroup SYS_ETH_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys_eth_r32(reg) reg_r32(&sys_eth->reg) -+#define sys_eth_w32(val, reg) reg_w32(val, &sys_eth->reg) -+#define sys_eth_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_eth->reg) -+#define sys_eth_r32_table(reg, idx) reg_r32_table(sys_eth->reg, idx) -+#define sys_eth_w32_table(val, reg, idx) reg_w32_table(val, sys_eth->reg, idx) -+#define sys_eth_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_eth->reg, idx) -+#define sys_eth_adr_table(reg, idx) adr_table(sys_eth->reg, idx) -+ -+ -+/** SYS_ETH register structure */ -+struct gpon_reg_sys_eth -+{ -+ /** Clock Status Register */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[32]; /* 0x00000030 */ -+ /** External PHY Control Register */ -+ unsigned int extphyc; /* 0x000000B0 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** Datarate Control Register -+ Controls the datarate of the various physical layers. The contents of the writeable fields of this register shall not be changed during operation. */ -+ unsigned int drc; /* 0x000000B8 */ -+ /** GMAC Multiplexer Control Register -+ Controls the interconnect between GMACs and the various physical layers. All fields need to have a different content. If two GMACs are muxed to the same PHY unpredictable results may occur. The contents of this register shall not be changed during operation. */ -+ unsigned int gmuxc; /* 0x000000BC */ -+ /** Datarate Status Register -+ Shows the datarate of the GMACs. The datarate of a GMAC is derived from the datarate of the physical layer it is multiplexed to. This register is for debugging only. */ -+ unsigned int drs; /* 0x000000C0 */ -+ /** SGMII Control Register */ -+ unsigned int sgmiic; /* 0x000000C4 */ -+ /** Reserved */ -+ unsigned int res_2[14]; /* 0x000000C8 */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** GPHY1MII2 Clock Enable -+ Shows the clock enable bit for GPHY1MII2. */ -+#define SYS_ETH_CLKS_GPHY1MII2 0x02000000 -+/* Disable -+#define SYS_ETH_CLKS_GPHY1MII2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY1MII2_EN 0x02000000 -+/** GPHY0MII2 Clock Enable -+ Shows the clock enable bit for GPHY0MII2. */ -+#define SYS_ETH_CLKS_GPHY0MII2 0x01000000 -+/* Disable -+#define SYS_ETH_CLKS_GPHY0MII2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY0MII2_EN 0x01000000 -+/** PADCTRL2 Clock Enable -+ Shows the clock enable bit for the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKS_PADCTRL2 0x00200000 -+/* Disable -+#define SYS_ETH_CLKS_PADCTRL2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_PADCTRL2_EN 0x00200000 -+/** PADCTRL0 Clock Enable -+ Shows the clock enable bit for the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKS_PADCTRL0 0x00100000 -+/* Disable -+#define SYS_ETH_CLKS_PADCTRL0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_PADCTRL0_EN 0x00100000 -+/** P2 Clock Enable -+ Shows the clock enable bit for the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKS_P2 0x00020000 -+/* Disable -+#define SYS_ETH_CLKS_P2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_P2_EN 0x00020000 -+/** P0 Clock Enable -+ Shows the clock enable bit for the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKS_P0 0x00010000 -+/* Disable -+#define SYS_ETH_CLKS_P0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_P0_EN 0x00010000 -+/** xMII Clock Enable -+ Shows the clock enable bit for the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKS_xMII 0x00000800 -+/* Disable -+#define SYS_ETH_CLKS_xMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_xMII_EN 0x00000800 -+/** SGMII Clock Enable -+ Shows the clock enable bit for the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_SGMII 0x00000400 -+/* Disable -+#define SYS_ETH_CLKS_SGMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_SGMII_EN 0x00000400 -+/** GPHY1 Clock Enable -+ Shows the clock enable bit for the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_GPHY1 0x00000200 -+/* Disable -+#define SYS_ETH_CLKS_GPHY1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY1_EN 0x00000200 -+/** GPHY0 Clock Enable -+ Shows the clock enable bit for the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKS_GPHY0 0x00000100 -+/* Disable -+#define SYS_ETH_CLKS_GPHY0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GPHY0_EN 0x00000100 -+/** MDIO Clock Enable -+ Shows the clock enable bit for the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKS_MDIO 0x00000080 -+/* Disable -+#define SYS_ETH_CLKS_MDIO_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_MDIO_EN 0x00000080 -+/** GMAC3 Clock Enable -+ Shows the clock enable bit for the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKS_GMAC3 0x00000008 -+/* Disable -+#define SYS_ETH_CLKS_GMAC3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC3_EN 0x00000008 -+/** GMAC2 Clock Enable -+ Shows the clock enable bit for the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKS_GMAC2 0x00000004 -+/* Disable -+#define SYS_ETH_CLKS_GMAC2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC2_EN 0x00000004 -+/** GMAC1 Clock Enable -+ Shows the clock enable bit for the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKS_GMAC1 0x00000002 -+/* Disable -+#define SYS_ETH_CLKS_GMAC1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC1_EN 0x00000002 -+/** GMAC0 Clock Enable -+ Shows the clock enable bit for the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKS_GMAC0 0x00000001 -+/* Disable -+#define SYS_ETH_CLKS_GMAC0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_CLKS_GMAC0_EN 0x00000001 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable GPHY1MII2 -+ Sets the clock enable bit of the GPHY1MII2. */ -+#define SYS_ETH_CLKEN_GPHY1MII2 0x02000000 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY1MII2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY1MII2_SET 0x02000000 -+/** Set Clock Enable GPHY0MII2 -+ Sets the clock enable bit of the GPHY0MII2. */ -+#define SYS_ETH_CLKEN_GPHY0MII2 0x01000000 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY0MII2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY0MII2_SET 0x01000000 -+/** Set Clock Enable PADCTRL2 -+ Sets the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKEN_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_CLKEN_PADCTRL2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_PADCTRL2_SET 0x00200000 -+/** Set Clock Enable PADCTRL0 -+ Sets the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKEN_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_CLKEN_PADCTRL0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_PADCTRL0_SET 0x00100000 -+/** Set Clock Enable P2 -+ Sets the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKEN_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_CLKEN_P2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_P2_SET 0x00020000 -+/** Set Clock Enable P0 -+ Sets the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKEN_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_CLKEN_P0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_P0_SET 0x00010000 -+/** Set Clock Enable xMII -+ Sets the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKEN_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_CLKEN_xMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_xMII_SET 0x00000800 -+/** Set Clock Enable SGMII -+ Sets the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_CLKEN_SGMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_SGMII_SET 0x00000400 -+/** Set Clock Enable GPHY1 -+ Sets the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY1_SET 0x00000200 -+/** Set Clock Enable GPHY0 -+ Sets the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKEN_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_CLKEN_GPHY0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GPHY0_SET 0x00000100 -+/** Set Clock Enable MDIO -+ Sets the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKEN_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_CLKEN_MDIO_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_MDIO_SET 0x00000080 -+/** Set Clock Enable GMAC3 -+ Sets the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKEN_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC3_SET 0x00000008 -+/** Set Clock Enable GMAC2 -+ Sets the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKEN_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC2_SET 0x00000004 -+/** Set Clock Enable GMAC1 -+ Sets the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKEN_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC1_SET 0x00000002 -+/** Set Clock Enable GMAC0 -+ Sets the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKEN_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_CLKEN_GMAC0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_CLKEN_GMAC0_SET 0x00000001 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable GPHY1MII2 -+ Clears the clock enable bit of the GPHY1MII2. */ -+#define SYS_ETH_CLKCLR_GPHY1MII2 0x02000000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY1MII2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY1MII2_CLR 0x02000000 -+/** Clear Clock Enable GPHY0MII2 -+ Clears the clock enable bit of the GPHY0MII2. */ -+#define SYS_ETH_CLKCLR_GPHY0MII2 0x01000000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY0MII2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY0MII2_CLR 0x01000000 -+/** Clear Clock Enable PADCTRL2 -+ Clears the clock enable bit of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_CLKCLR_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_PADCTRL2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_PADCTRL2_CLR 0x00200000 -+/** Clear Clock Enable PADCTRL0 -+ Clears the clock enable bit of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_CLKCLR_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_PADCTRL0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_PADCTRL0_CLR 0x00100000 -+/** Clear Clock Enable P2 -+ Clears the clock enable bit of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_CLKCLR_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_P2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_P2_CLR 0x00020000 -+/** Clear Clock Enable P0 -+ Clears the clock enable bit of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_CLKCLR_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_CLKCLR_P0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_P0_CLR 0x00010000 -+/** Clear Clock Enable xMII -+ Clears the clock enable bit of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_CLKCLR_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_CLKCLR_xMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_xMII_CLR 0x00000800 -+/** Clear Clock Enable SGMII -+ Clears the clock enable bit of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_CLKCLR_SGMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_SGMII_CLR 0x00000400 -+/** Clear Clock Enable GPHY1 -+ Clears the clock enable bit of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY1_CLR 0x00000200 -+/** Clear Clock Enable GPHY0 -+ Clears the clock enable bit of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_CLKCLR_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GPHY0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GPHY0_CLR 0x00000100 -+/** Clear Clock Enable MDIO -+ Clears the clock enable bit of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_CLKCLR_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_CLKCLR_MDIO_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_MDIO_CLR 0x00000080 -+/** Clear Clock Enable GMAC3 -+ Clears the clock enable bit of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_CLKCLR_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC3_CLR 0x00000008 -+/** Clear Clock Enable GMAC2 -+ Clears the clock enable bit of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_CLKCLR_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC2_CLR 0x00000004 -+/** Clear Clock Enable GMAC1 -+ Clears the clock enable bit of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_CLKCLR_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC1_CLR 0x00000002 -+/** Clear Clock Enable GMAC0 -+ Clears the clock enable bit of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_CLKCLR_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_CLKCLR_GMAC0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_CLKCLR_GMAC0_CLR 0x00000001 -+ -+/* Fields of "Activation Status Register" */ -+/** PADCTRL2 Status -+ Shows the activation status of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_ACTS_PADCTRL2 0x00200000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_PADCTRL2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_PADCTRL2_ACT 0x00200000 -+/** PADCTRL0 Status -+ Shows the activation status of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_ACTS_PADCTRL0 0x00100000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_PADCTRL0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_PADCTRL0_ACT 0x00100000 -+/** P2 Status -+ Shows the activation status of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_ACTS_P2 0x00020000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_P2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_P2_ACT 0x00020000 -+/** P0 Status -+ Shows the activation status of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_ACTS_P0 0x00010000 -+/* The block is inactive. -+#define SYS_ETH_ACTS_P0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_P0_ACT 0x00010000 -+/** xMII Status -+ Shows the activation status of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_ACTS_xMII 0x00000800 -+/* The block is inactive. -+#define SYS_ETH_ACTS_xMII_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_xMII_ACT 0x00000800 -+/** SGMII Status -+ Shows the activation status of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_SGMII 0x00000400 -+/* The block is inactive. -+#define SYS_ETH_ACTS_SGMII_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_SGMII_ACT 0x00000400 -+/** GPHY1 Status -+ Shows the activation status of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_GPHY1 0x00000200 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GPHY1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GPHY1_ACT 0x00000200 -+/** GPHY0 Status -+ Shows the activation status of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACTS_GPHY0 0x00000100 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GPHY0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GPHY0_ACT 0x00000100 -+/** MDIO Status -+ Shows the activation status of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_ACTS_MDIO 0x00000080 -+/* The block is inactive. -+#define SYS_ETH_ACTS_MDIO_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_MDIO_ACT 0x00000080 -+/** GMAC3 Status -+ Shows the activation status of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_ACTS_GMAC3 0x00000008 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC3_ACT 0x00000008 -+/** GMAC2 Status -+ Shows the activation status of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_ACTS_GMAC2 0x00000004 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC2_ACT 0x00000004 -+/** GMAC1 Status -+ Shows the activation status of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_ACTS_GMAC1 0x00000002 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC1_ACT 0x00000002 -+/** GMAC0 Status -+ Shows the activation status of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_ACTS_GMAC0 0x00000001 -+/* The block is inactive. -+#define SYS_ETH_ACTS_GMAC0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_ETH_ACTS_GMAC0_ACT 0x00000001 -+ -+/* Fields of "Activation Register" */ -+/** Activate PADCTRL2 -+ Sets the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_ACT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_ACT_PADCTRL2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_PADCTRL2_SET 0x00200000 -+/** Activate PADCTRL0 -+ Sets the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_ACT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_ACT_PADCTRL0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_PADCTRL0_SET 0x00100000 -+/** Activate P2 -+ Sets the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_ACT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_ACT_P2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_P2_SET 0x00020000 -+/** Activate P0 -+ Sets the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_ACT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_ACT_P0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_P0_SET 0x00010000 -+/** Activate xMII -+ Sets the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_ACT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_ACT_xMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_xMII_SET 0x00000800 -+/** Activate SGMII -+ Sets the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_ACT_SGMII_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_SGMII_SET 0x00000400 -+/** Activate GPHY1 -+ Sets the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_ACT_GPHY1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GPHY1_SET 0x00000200 -+/** Activate GPHY0 -+ Sets the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_ACT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_ACT_GPHY0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GPHY0_SET 0x00000100 -+/** Activate MDIO -+ Sets the activation flag of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_ACT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_ACT_MDIO_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_MDIO_SET 0x00000080 -+/** Activate GMAC3 -+ Sets the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_ACT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC3_SET 0x00000008 -+/** Activate GMAC2 -+ Sets the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_ACT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC2_SET 0x00000004 -+/** Activate GMAC1 -+ Sets the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_ACT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC1_SET 0x00000002 -+/** Activate GMAC0 -+ Sets the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_ACT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_ACT_GMAC0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_ETH_ACT_GMAC0_SET 0x00000001 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate PADCTRL2 -+ Clears the activation flag of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_DEACT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_DEACT_PADCTRL2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_PADCTRL2_CLR 0x00200000 -+/** Deactivate PADCTRL0 -+ Clears the activation flag of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_DEACT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_DEACT_PADCTRL0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_PADCTRL0_CLR 0x00100000 -+/** Deactivate P2 -+ Clears the activation flag of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_DEACT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_DEACT_P2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_P2_CLR 0x00020000 -+/** Deactivate P0 -+ Clears the activation flag of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_DEACT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_DEACT_P0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_P0_CLR 0x00010000 -+/** Deactivate xMII -+ Clears the activation flag of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_DEACT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_DEACT_xMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_xMII_CLR 0x00000800 -+/** Deactivate SGMII -+ Clears the activation flag of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_DEACT_SGMII_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_SGMII_CLR 0x00000400 -+/** Deactivate GPHY1 -+ Clears the activation flag of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_DEACT_GPHY1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GPHY1_CLR 0x00000200 -+/** Deactivate GPHY0 -+ Clears the activation flag of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_DEACT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_DEACT_GPHY0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GPHY0_CLR 0x00000100 -+/** Deactivate MDIO -+ Clears the activation flag of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_DEACT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_DEACT_MDIO_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_MDIO_CLR 0x00000080 -+/** Deactivate GMAC3 -+ Clears the activation flag of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_DEACT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC3_CLR 0x00000008 -+/** Deactivate GMAC2 -+ Clears the activation flag of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_DEACT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC2_CLR 0x00000004 -+/** Deactivate GMAC1 -+ Clears the activation flag of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_DEACT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC1_CLR 0x00000002 -+/** Deactivate GMAC0 -+ Clears the activation flag of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_DEACT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_DEACT_GMAC0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_ETH_DEACT_GMAC0_CLR 0x00000001 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot PADCTRL2 -+ Triggers a reboot of the PADCTRL2 domain. This domain contains the PADCTRL2 block. */ -+#define SYS_ETH_RBT_PADCTRL2 0x00200000 -+/* No-Operation -+#define SYS_ETH_RBT_PADCTRL2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_PADCTRL2_TRIG 0x00200000 -+/** Reboot PADCTRL0 -+ Triggers a reboot of the PADCTRL0 domain. This domain contains the PADCTRL0 block. */ -+#define SYS_ETH_RBT_PADCTRL0 0x00100000 -+/* No-Operation -+#define SYS_ETH_RBT_PADCTRL0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_PADCTRL0_TRIG 0x00100000 -+/** Reboot P2 -+ Triggers a reboot of the P2 domain. This domain contains the P2 instance of the GPIO block. */ -+#define SYS_ETH_RBT_P2 0x00020000 -+/* No-Operation -+#define SYS_ETH_RBT_P2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_P2_TRIG 0x00020000 -+/** Reboot P0 -+ Triggers a reboot of the P0 domain. This domain contains the P0 instance of the GPIO block. */ -+#define SYS_ETH_RBT_P0 0x00010000 -+/* No-Operation -+#define SYS_ETH_RBT_P0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_P0_TRIG 0x00010000 -+/** Reboot xMII -+ Triggers a reboot of the xMII domain. This domain contains the XMII block. If any of the digital LAN interfaces shall be used, this domain has to be active. */ -+#define SYS_ETH_RBT_xMII 0x00000800 -+/* No-Operation -+#define SYS_ETH_RBT_xMII_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_xMII_TRIG 0x00000800 -+/** Reboot SGMII -+ Triggers a reboot of the SGMII domain. This domain contains all parts of the EIM related to the SGMII block. The SGMII block itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_SGMII 0x00000400 -+/* No-Operation -+#define SYS_ETH_RBT_SGMII_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_SGMII_TRIG 0x00000400 -+/** Reboot GPHY1 -+ Triggers a reboot of the GPHY1 domain. This domain contains all parts of the EIM related to GPHY1. The GPHY1 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_GPHY1 0x00000200 -+/* No-Operation -+#define SYS_ETH_RBT_GPHY1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GPHY1_TRIG 0x00000200 -+/** Reboot GPHY0 -+ Triggers a reboot of the GPHY0 domain. This domain contains all parts of the EIM related to GPHY0. The GPHY0 itself is not contained, as it has its own clock/reset/power management. */ -+#define SYS_ETH_RBT_GPHY0 0x00000100 -+/* No-Operation -+#define SYS_ETH_RBT_GPHY0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GPHY0_TRIG 0x00000100 -+/** Reboot MDIO -+ Triggers a reboot of the MDIO domain. This domain contains the MDIO block. */ -+#define SYS_ETH_RBT_MDIO 0x00000080 -+/* No-Operation -+#define SYS_ETH_RBT_MDIO_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_MDIO_TRIG 0x00000080 -+/** Reboot GMAC3 -+ Triggers a reboot of the GMAC3 domain. This domain contains the GMAC3 block. */ -+#define SYS_ETH_RBT_GMAC3 0x00000008 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC3_TRIG 0x00000008 -+/** Reboot GMAC2 -+ Triggers a reboot of the GMAC2 domain. This domain contains the GMAC2 block. */ -+#define SYS_ETH_RBT_GMAC2 0x00000004 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC2_TRIG 0x00000004 -+/** Reboot GMAC1 -+ Triggers a reboot of the GMAC1 domain. This domain contains the GMAC1 block. */ -+#define SYS_ETH_RBT_GMAC1 0x00000002 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC1_TRIG 0x00000002 -+/** Reboot GMAC0 -+ Triggers a reboot of the GMAC0 domain. This domain contains the GMAC0 block. */ -+#define SYS_ETH_RBT_GMAC0 0x00000001 -+/* No-Operation -+#define SYS_ETH_RBT_GMAC0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_ETH_RBT_GMAC0_TRIG 0x00000001 -+ -+/* Fields of "External PHY Control Register" */ -+/** PHY_CLKO Output Enable -+ Enables the output driver of the PHY_CLKO pin. */ -+#define SYS_ETH_EXTPHYC_CLKEN 0x80000000 -+/* Disable -+#define SYS_ETH_EXTPHYC_CLKEN_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_EXTPHYC_CLKEN_EN 0x80000000 -+/** PHY_CLKO Frequency Select -+ Selects the frequency of the PHY_CLKO pin. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_EXTPHYC_CLKSEL_OFFSET 0 -+/** 25 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F25 0x00000001 -+/** 125 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F125 0x00000002 -+/** 50 MHz. */ -+#define SYS_ETH_EXTPHYC_CLKSEL_F50 0x00000005 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down PADCTRL2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_PADCTRL2 0x00200000 -+/* Disable -+#define SYS_ETH_PDCFG_PADCTRL2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_PADCTRL2_EN 0x00200000 -+/** Enable Power Down PADCTRL0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_PADCTRL0 0x00100000 -+/* Disable -+#define SYS_ETH_PDCFG_PADCTRL0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_PADCTRL0_EN 0x00100000 -+/** Enable Power Down P2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_P2 0x00020000 -+/* Disable -+#define SYS_ETH_PDCFG_P2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_P2_EN 0x00020000 -+/** Enable Power Down P0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_P0 0x00010000 -+/* Disable -+#define SYS_ETH_PDCFG_P0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_P0_EN 0x00010000 -+/** Enable Power Down xMII -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_xMII 0x00000800 -+/* Disable -+#define SYS_ETH_PDCFG_xMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_xMII_EN 0x00000800 -+/** Enable Power Down SGMII -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_SGMII 0x00000400 -+/* Disable -+#define SYS_ETH_PDCFG_SGMII_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_SGMII_EN 0x00000400 -+/** Enable Power Down GPHY1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GPHY1 0x00000200 -+/* Disable -+#define SYS_ETH_PDCFG_GPHY1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GPHY1_EN 0x00000200 -+/** Enable Power Down GPHY0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GPHY0 0x00000100 -+/* Disable -+#define SYS_ETH_PDCFG_GPHY0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GPHY0_EN 0x00000100 -+/** Enable Power Down MDIO -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_MDIO 0x00000080 -+/* Disable -+#define SYS_ETH_PDCFG_MDIO_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_MDIO_EN 0x00000080 -+/** Enable Power Down GMAC3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC3 0x00000008 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC3_EN 0x00000008 -+/** Enable Power Down GMAC2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC2 0x00000004 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC2_EN 0x00000004 -+/** Enable Power Down GMAC1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC1 0x00000002 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC1_EN 0x00000002 -+/** Enable Power Down GMAC0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_ETH_PDCFG_GMAC0 0x00000001 -+/* Disable -+#define SYS_ETH_PDCFG_GMAC0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_ETH_PDCFG_GMAC0_EN 0x00000001 -+ -+/* Fields of "Datarate Control Register" */ -+/** MDC Clockrate -+ Selects the clockrate of the MDIO interface. */ -+#define SYS_ETH_DRC_MDC_MASK 0x30000000 -+/** field offset */ -+#define SYS_ETH_DRC_MDC_OFFSET 28 -+/** 312.5/128 = appr. 2.44 MHz. */ -+#define SYS_ETH_DRC_MDC_F2M44 0x00000000 -+/** 312.5/64 = appr. 4.88 MHz. */ -+#define SYS_ETH_DRC_MDC_F4M88 0x10000000 -+/** 312.5/32 = appr. 9.77 MHz. */ -+#define SYS_ETH_DRC_MDC_F9M77 0x20000000 -+/** 312.5/16 = appr. 19.5 MHz. */ -+#define SYS_ETH_DRC_MDC_F19M5 0x30000000 -+/** xMII1 Datarate -+ Selects the datarate of the xMII1 interface. */ -+#define SYS_ETH_DRC_xMII1_MASK 0x07000000 -+/** field offset */ -+#define SYS_ETH_DRC_xMII1_OFFSET 24 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR100 0x01000000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR1000 0x02000000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRC_xMII1_DR200 0x05000000 -+/** xMII0 Datarate -+ Selects the datarate of the xMII0 interface. */ -+#define SYS_ETH_DRC_xMII0_MASK 0x00700000 -+/** field offset */ -+#define SYS_ETH_DRC_xMII0_OFFSET 20 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR100 0x00100000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR1000 0x00200000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRC_xMII0_DR200 0x00500000 -+/** SGMII Datarate -+ Selects the datarate of the SGMII interface. */ -+#define SYS_ETH_DRC_SGMII_MASK 0x00070000 -+/** field offset */ -+#define SYS_ETH_DRC_SGMII_OFFSET 16 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR100 0x00010000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR1000 0x00020000 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRC_SGMII_DR2500 0x00040000 -+/** GPHY1_MII2 Datarate -+ Shows the datarate of the GPHY1_MII2 interface. */ -+#define SYS_ETH_DRC_GPHY1_MII2_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY1_MII2_OFFSET 12 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_MII2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_MII2_DR100 0x00001000 -+/** GPHY1_GMII Datarate -+ Shows the datarate of the GPHY1_GMII interface. */ -+#define SYS_ETH_DRC_GPHY1_GMII_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY1_GMII_OFFSET 8 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR100 0x00000100 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_GPHY1_GMII_DR1000 0x00000200 -+/** GPHY0_MII2 Datarate -+ Shows the datarate of the GPHY0_MII2 interface. */ -+#define SYS_ETH_DRC_GPHY0_MII2_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY0_MII2_OFFSET 4 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_MII2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_MII2_DR100 0x00000010 -+/** GPHY0_GMII Datarate -+ Shows the datarate of the GPHY0_GMII interface. */ -+#define SYS_ETH_DRC_GPHY0_GMII_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_DRC_GPHY0_GMII_OFFSET 0 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR100 0x00000001 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRC_GPHY0_GMII_DR1000 0x00000002 -+ -+/* Fields of "GMAC Multiplexer Control Register" */ -+/** GMAC 3 MUX setting -+ Selects the physical layer to be connected to GMAC3 */ -+#define SYS_ETH_GMUXC_GMAC3_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC3_OFFSET 12 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY0_MII2 0x00001000 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY1_GMII 0x00002000 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC3_GPHY1_MII2 0x00003000 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC3_SGMII 0x00004000 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC3_xMII0 0x00005000 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC3_xMII1 0x00006000 -+/** GMAC 2 MUX setting -+ Selects the physical layer to be connected to GMAC2 */ -+#define SYS_ETH_GMUXC_GMAC2_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC2_OFFSET 8 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY0_MII2 0x00000100 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY1_GMII 0x00000200 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC2_GPHY1_MII2 0x00000300 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC2_SGMII 0x00000400 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC2_xMII0 0x00000500 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC2_xMII1 0x00000600 -+/** GMAC 1 MUX setting -+ Selects the physical layer to be connected to GMAC1 */ -+#define SYS_ETH_GMUXC_GMAC1_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC1_OFFSET 4 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY0_MII2 0x00000010 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY1_GMII 0x00000020 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC1_GPHY1_MII2 0x00000030 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC1_SGMII 0x00000040 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC1_xMII0 0x00000050 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC1_xMII1 0x00000060 -+/** GMAC 0 MUX setting -+ Selects the physical layer to be connected to GMAC0 */ -+#define SYS_ETH_GMUXC_GMAC0_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_GMUXC_GMAC0_OFFSET 0 -+/** GMAC connects to GPHY0_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY0_GMII 0x00000000 -+/** GMAC connects to GPHY0_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY0_MII2 0x00000001 -+/** GMAC connects to GPHY1_GMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY1_GMII 0x00000002 -+/** GMAC connects to GPHY1_MII2 interface */ -+#define SYS_ETH_GMUXC_GMAC0_GPHY1_MII2 0x00000003 -+/** GMAC connects to SGMII interface */ -+#define SYS_ETH_GMUXC_GMAC0_SGMII 0x00000004 -+/** GMAC connects to xMII0 interface */ -+#define SYS_ETH_GMUXC_GMAC0_xMII0 0x00000005 -+/** GMAC connects to xMII1 interface */ -+#define SYS_ETH_GMUXC_GMAC0_xMII1 0x00000006 -+ -+/* Fields of "Datarate Status Register" */ -+/** GMAC 3 datarate -+ Shows the datarate of GMAC3 */ -+#define SYS_ETH_DRS_GMAC3_MASK 0x00007000 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC3_OFFSET 12 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR100 0x00001000 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR1000 0x00002000 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR2500 0x00004000 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC3_DR200 0x00005000 -+/** GMAC 2 datarate -+ Shows the datarate of GMAC2 */ -+#define SYS_ETH_DRS_GMAC2_MASK 0x00000700 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC2_OFFSET 8 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR100 0x00000100 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR1000 0x00000200 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR2500 0x00000400 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC2_DR200 0x00000500 -+/** GMAC 1 datarate -+ Shows the datarate of GMAC1 */ -+#define SYS_ETH_DRS_GMAC1_MASK 0x00000070 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC1_OFFSET 4 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR100 0x00000010 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR1000 0x00000020 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR2500 0x00000040 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC1_DR200 0x00000050 -+/** GMAC 0 datarate -+ Shows the datarate of GMAC0 */ -+#define SYS_ETH_DRS_GMAC0_MASK 0x00000007 -+/** field offset */ -+#define SYS_ETH_DRS_GMAC0_OFFSET 0 -+/** 10 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR10 0x00000000 -+/** 100 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR100 0x00000001 -+/** 1000 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR1000 0x00000002 -+/** 2500 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR2500 0x00000004 -+/** 200 MBit/s. */ -+#define SYS_ETH_DRS_GMAC0_DR200 0x00000005 -+ -+/* Fields of "SGMII Control Register" */ -+/** Auto Negotiation Protocol -+ Selects the TBX/SGMII mode for the autonegotiation of the SGMII interface. */ -+#define SYS_ETH_SGMIIC_ANP 0x00000002 -+/* TBX Mode (IEEE 802.3 Clause 37 ANEG) -+#define SYS_ETH_SGMIIC_ANP_TBXM 0x00000000 */ -+/** SGMII Mode (Cisco Aneg) */ -+#define SYS_ETH_SGMIIC_ANP_SGMIIM 0x00000002 -+/** Auto Negotiation MAC/PHY -+ Selects the MAC/PHY mode for the autonegotiation of the SGMII interface. */ -+#define SYS_ETH_SGMIIC_ANMP 0x00000001 -+/* MAC Mode -+#define SYS_ETH_SGMIIC_ANMP_MAC 0x00000000 */ -+/** PHY Mode */ -+#define SYS_ETH_SGMIIC_ANMP_PHY 0x00000001 -+ -+/*! @} */ /* SYS_ETH_REGISTER */ -+ -+#endif /* _sys_eth_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h -new file mode 100644 -index 0000000..a9a1b1b ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sys_gpe_reg.h -@@ -0,0 +1,2829 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _sys_gpe_reg_h -+#define _sys_gpe_reg_h -+ -+/** \addtogroup SYS_GPE_REGISTER -+ @{ -+*/ -+/* access macros */ -+#define sys_gpe_r32(reg) reg_r32(&sys_gpe->reg) -+#define sys_gpe_w32(val, reg) reg_w32(val, &sys_gpe->reg) -+#define sys_gpe_w32_mask(clear, set, reg) reg_w32_mask(clear, set, &sys_gpe->reg) -+#define sys_gpe_r32_table(reg, idx) reg_r32_table(sys_gpe->reg, idx) -+#define sys_gpe_w32_table(val, reg, idx) reg_w32_table(val, sys_gpe->reg, idx) -+#define sys_gpe_w32_table_mask(clear, set, reg, idx) reg_w32_table_mask(clear, set, sys_gpe->reg, idx) -+#define sys_gpe_adr_table(reg, idx) adr_table(sys_gpe->reg, idx) -+ -+ -+/** SYS_GPE register structure */ -+struct gpon_reg_sys_gpe -+{ -+ /** Clock Status Register -+ The clock status reflects the actual clocking mode as a function of the SW settings and the hardware sleep mode. */ -+ unsigned int clks; /* 0x00000000 */ -+ /** Clock Enable Register -+ Via this register the clocks for the domains can be enabled. */ -+ unsigned int clken; /* 0x00000004 */ -+ /** Clock Clear Register -+ Via this register the clocks for the domains can be disabled. */ -+ unsigned int clkclr; /* 0x00000008 */ -+ /** Reserved */ -+ unsigned int res_0[5]; /* 0x0000000C */ -+ /** Activation Status Register */ -+ unsigned int acts; /* 0x00000020 */ -+ /** Activation Register -+ Via this register the domains can be activated. */ -+ unsigned int act; /* 0x00000024 */ -+ /** Deactivation Register -+ Via this register the domains can be deactivated. */ -+ unsigned int deact; /* 0x00000028 */ -+ /** Reboot Trigger Register -+ Via this register the domains can be rebooted (sent through reset). */ -+ unsigned int rbt; /* 0x0000002C */ -+ /** Reserved */ -+ unsigned int res_1[33]; /* 0x00000030 */ -+ /** Power Down Configuration Register -+ Via this register the configuration is done whether in case of deactivation the power supply of the domain shall be removed. */ -+ unsigned int pdcfg; /* 0x000000B4 */ -+ /** Sleep Source Configuration Register -+ All sleep/wakeup conditions selected in this register contribute to the generation of the hardware sleep/wakeup request. Unselected conditions are ignored for sleep and wakeup. If no bit is selected, HW sleep is disabled. */ -+ unsigned int sscfg; /* 0x000000B8 */ -+ /** Sleep Source Timer Register */ -+ unsigned int sst; /* 0x000000BC */ -+ /** Sleep Destination Status Register -+ Shows the status of the sleep destination vector. All clock domains selected in this register will be shutoff in case of a hardware sleep request. These clocks will be automatically reenabled in case of a hardware wakeup request. */ -+ unsigned int sds; /* 0x000000C0 */ -+ /** Sleep Destination Set Register -+ Via this register the the domains to be shutoff in case of a hardware sleep request can be selected. */ -+ unsigned int sdset; /* 0x000000C4 */ -+ /** Sleep Destination Clear Register -+ Via this register the the domains to be shutoff in case of a hardware sleep request can be deselected. */ -+ unsigned int sdclr; /* 0x000000C8 */ -+ /** Reserved */ -+ unsigned int res_2[9]; /* 0x000000CC */ -+ /** IRNCS Capture Register -+ This register shows the currently active interrupt events masked with the corresponding enable bits of the IRNCSEN register. The interrupts can be acknowledged by a write operation. */ -+ unsigned int irncscr; /* 0x000000F0 */ -+ /** IRNCS Interrupt Control Register -+ A write operation directly effects the interrupts. This can be used to trigger events under software control for testing purposes. A read operation returns the unmasked interrupt events. */ -+ unsigned int irncsicr; /* 0x000000F4 */ -+ /** IRNCS Interrupt Enable Register -+ This register contains the enable (or mask) bits for the interrupts. Disabled interrupts are not visible in the IRNCSCR register and are not signalled via the interrupt line towards the controller. */ -+ unsigned int irncsen; /* 0x000000F8 */ -+ /** Reserved */ -+ unsigned int res_3; /* 0x000000FC */ -+}; -+ -+ -+/* Fields of "Clock Status Register" */ -+/** COP7 Clock Enable -+ Shows the clock enable bit for the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKS_COP7 0x80000000 -+/* Disable -+#define SYS_GPE_CLKS_COP7_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP7_EN 0x80000000 -+/** COP6 Clock Enable -+ Shows the clock enable bit for the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKS_COP6 0x40000000 -+/* Disable -+#define SYS_GPE_CLKS_COP6_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP6_EN 0x40000000 -+/** COP5 Clock Enable -+ Shows the clock enable bit for the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKS_COP5 0x20000000 -+/* Disable -+#define SYS_GPE_CLKS_COP5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP5_EN 0x20000000 -+/** COP4 Clock Enable -+ Shows the clock enable bit for the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKS_COP4 0x10000000 -+/* Disable -+#define SYS_GPE_CLKS_COP4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP4_EN 0x10000000 -+/** COP3 Clock Enable -+ Shows the clock enable bit for the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKS_COP3 0x08000000 -+/* Disable -+#define SYS_GPE_CLKS_COP3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP3_EN 0x08000000 -+/** COP2 Clock Enable -+ Shows the clock enable bit for the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKS_COP2 0x04000000 -+/* Disable -+#define SYS_GPE_CLKS_COP2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP2_EN 0x04000000 -+/** COP1 Clock Enable -+ Shows the clock enable bit for the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKS_COP1 0x02000000 -+/* Disable -+#define SYS_GPE_CLKS_COP1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP1_EN 0x02000000 -+/** COP0 Clock Enable -+ Shows the clock enable bit for the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKS_COP0 0x01000000 -+/* Disable -+#define SYS_GPE_CLKS_COP0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_COP0_EN 0x01000000 -+/** PE5 Clock Enable -+ Shows the clock enable bit for the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKS_PE5 0x00200000 -+/* Disable -+#define SYS_GPE_CLKS_PE5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE5_EN 0x00200000 -+/** PE4 Clock Enable -+ Shows the clock enable bit for the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKS_PE4 0x00100000 -+/* Disable -+#define SYS_GPE_CLKS_PE4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE4_EN 0x00100000 -+/** PE3 Clock Enable -+ Shows the clock enable bit for the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKS_PE3 0x00080000 -+/* Disable -+#define SYS_GPE_CLKS_PE3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE3_EN 0x00080000 -+/** PE2 Clock Enable -+ Shows the clock enable bit for the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKS_PE2 0x00040000 -+/* Disable -+#define SYS_GPE_CLKS_PE2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE2_EN 0x00040000 -+/** PE1 Clock Enable -+ Shows the clock enable bit for the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKS_PE1 0x00020000 -+/* Disable -+#define SYS_GPE_CLKS_PE1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE1_EN 0x00020000 -+/** PE0 Clock Enable -+ Shows the clock enable bit for the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKS_PE0 0x00010000 -+/* Disable -+#define SYS_GPE_CLKS_PE0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_PE0_EN 0x00010000 -+/** ARB Clock Enable -+ Shows the clock enable bit for the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKS_ARB 0x00002000 -+/* Disable -+#define SYS_GPE_CLKS_ARB_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_ARB_EN 0x00002000 -+/** FSQM Clock Enable -+ Shows the clock enable bit for the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKS_FSQM 0x00001000 -+/* Disable -+#define SYS_GPE_CLKS_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_FSQM_EN 0x00001000 -+/** TMU Clock Enable -+ Shows the clock enable bit for the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKS_TMU 0x00000800 -+/* Disable -+#define SYS_GPE_CLKS_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_TMU_EN 0x00000800 -+/** MRG Clock Enable -+ Shows the clock enable bit for the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKS_MRG 0x00000400 -+/* Disable -+#define SYS_GPE_CLKS_MRG_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_MRG_EN 0x00000400 -+/** DISP Clock Enable -+ Shows the clock enable bit for the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKS_DISP 0x00000200 -+/* Disable -+#define SYS_GPE_CLKS_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_DISP_EN 0x00000200 -+/** IQM Clock Enable -+ Shows the clock enable bit for the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKS_IQM 0x00000100 -+/* Disable -+#define SYS_GPE_CLKS_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_IQM_EN 0x00000100 -+/** CPUE Clock Enable -+ Shows the clock enable bit for the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKS_CPUE 0x00000080 -+/* Disable -+#define SYS_GPE_CLKS_CPUE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_CPUE_EN 0x00000080 -+/** CPUI Clock Enable -+ Shows the clock enable bit for the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKS_CPUI 0x00000040 -+/* Disable -+#define SYS_GPE_CLKS_CPUI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_CPUI_EN 0x00000040 -+/** GPONE Clock Enable -+ Shows the clock enable bit for the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKS_GPONE 0x00000020 -+/* Disable -+#define SYS_GPE_CLKS_GPONE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_GPONE_EN 0x00000020 -+/** GPONI Clock Enable -+ Shows the clock enable bit for the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKS_GPONI 0x00000010 -+/* Disable -+#define SYS_GPE_CLKS_GPONI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_GPONI_EN 0x00000010 -+/** LAN3 Clock Enable -+ Shows the clock enable bit for the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKS_LAN3 0x00000008 -+/* Disable -+#define SYS_GPE_CLKS_LAN3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN3_EN 0x00000008 -+/** LAN2 Clock Enable -+ Shows the clock enable bit for the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKS_LAN2 0x00000004 -+/* Disable -+#define SYS_GPE_CLKS_LAN2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN2_EN 0x00000004 -+/** LAN1 Clock Enable -+ Shows the clock enable bit for the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKS_LAN1 0x00000002 -+/* Disable -+#define SYS_GPE_CLKS_LAN1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN1_EN 0x00000002 -+/** LAN0 Clock Enable -+ Shows the clock enable bit for the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKS_LAN0 0x00000001 -+/* Disable -+#define SYS_GPE_CLKS_LAN0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_CLKS_LAN0_EN 0x00000001 -+ -+/* Fields of "Clock Enable Register" */ -+/** Set Clock Enable COP7 -+ Sets the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKEN_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP7_SET 0x80000000 -+/** Set Clock Enable COP6 -+ Sets the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKEN_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP6_SET 0x40000000 -+/** Set Clock Enable COP5 -+ Sets the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKEN_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP5_SET 0x20000000 -+/** Set Clock Enable COP4 -+ Sets the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKEN_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP4_SET 0x10000000 -+/** Set Clock Enable COP3 -+ Sets the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKEN_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP3_SET 0x08000000 -+/** Set Clock Enable COP2 -+ Sets the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKEN_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP2_SET 0x04000000 -+/** Set Clock Enable COP1 -+ Sets the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKEN_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP1_SET 0x02000000 -+/** Set Clock Enable COP0 -+ Sets the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKEN_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_CLKEN_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_COP0_SET 0x01000000 -+/** Set Clock Enable PE5 -+ Sets the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKEN_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE5_SET 0x00200000 -+/** Set Clock Enable PE4 -+ Sets the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKEN_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE4_SET 0x00100000 -+/** Set Clock Enable PE3 -+ Sets the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKEN_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE3_SET 0x00080000 -+/** Set Clock Enable PE2 -+ Sets the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKEN_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE2_SET 0x00040000 -+/** Set Clock Enable PE1 -+ Sets the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKEN_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE1_SET 0x00020000 -+/** Set Clock Enable PE0 -+ Sets the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKEN_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_CLKEN_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_PE0_SET 0x00010000 -+/** Set Clock Enable ARB -+ Sets the clock enable bit of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKEN_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_CLKEN_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_ARB_SET 0x00002000 -+/** Set Clock Enable FSQM -+ Sets the clock enable bit of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKEN_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_CLKEN_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_FSQM_SET 0x00001000 -+/** Set Clock Enable TMU -+ Sets the clock enable bit of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKEN_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_CLKEN_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_TMU_SET 0x00000800 -+/** Set Clock Enable MRG -+ Sets the clock enable bit of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKEN_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_CLKEN_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_MRG_SET 0x00000400 -+/** Set Clock Enable DISP -+ Sets the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKEN_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_CLKEN_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_DISP_SET 0x00000200 -+/** Set Clock Enable IQM -+ Sets the clock enable bit of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKEN_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_CLKEN_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_IQM_SET 0x00000100 -+/** Set Clock Enable CPUE -+ Sets the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKEN_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_CLKEN_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_CPUE_SET 0x00000080 -+/** Set Clock Enable CPUI -+ Sets the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKEN_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_CLKEN_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_CPUI_SET 0x00000040 -+/** Set Clock Enable GPONE -+ Sets the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKEN_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_CLKEN_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_GPONE_SET 0x00000020 -+/** Set Clock Enable GPONI -+ Sets the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKEN_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_CLKEN_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_GPONI_SET 0x00000010 -+/** Set Clock Enable LAN3 -+ Sets the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKEN_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN3_SET 0x00000008 -+/** Set Clock Enable LAN2 -+ Sets the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKEN_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN2_SET 0x00000004 -+/** Set Clock Enable LAN1 -+ Sets the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKEN_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN1_SET 0x00000002 -+/** Set Clock Enable LAN0 -+ Sets the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKEN_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_CLKEN_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_CLKEN_LAN0_SET 0x00000001 -+ -+/* Fields of "Clock Clear Register" */ -+/** Clear Clock Enable COP7 -+ Clears the clock enable bit of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP7_CLR 0x80000000 -+/** Clear Clock Enable COP6 -+ Clears the clock enable bit of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP6_CLR 0x40000000 -+/** Clear Clock Enable COP5 -+ Clears the clock enable bit of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP5_CLR 0x20000000 -+/** Clear Clock Enable COP4 -+ Clears the clock enable bit of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP4_CLR 0x10000000 -+/** Clear Clock Enable COP3 -+ Clears the clock enable bit of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP3_CLR 0x08000000 -+/** Clear Clock Enable COP2 -+ Clears the clock enable bit of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP2_CLR 0x04000000 -+/** Clear Clock Enable COP1 -+ Clears the clock enable bit of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP1_CLR 0x02000000 -+/** Clear Clock Enable COP0 -+ Clears the clock enable bit of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_CLKCLR_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_COP0_CLR 0x01000000 -+/** Clear Clock Enable PE5 -+ Clears the clock enable bit of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE5_CLR 0x00200000 -+/** Clear Clock Enable PE4 -+ Clears the clock enable bit of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE4_CLR 0x00100000 -+/** Clear Clock Enable PE3 -+ Clears the clock enable bit of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE3_CLR 0x00080000 -+/** Clear Clock Enable PE2 -+ Clears the clock enable bit of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE2_CLR 0x00040000 -+/** Clear Clock Enable PE1 -+ Clears the clock enable bit of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE1_CLR 0x00020000 -+/** Clear Clock Enable PE0 -+ Clears the clock enable bit of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_CLKCLR_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_PE0_CLR 0x00010000 -+/** Clear Clock Enable ARB -+ Clears the clock enable bit of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_CLKCLR_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_ARB_CLR 0x00002000 -+/** Clear Clock Enable FSQM -+ Clears the clock enable bit of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_CLKCLR_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_CLKCLR_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_FSQM_CLR 0x00001000 -+/** Clear Clock Enable TMU -+ Clears the clock enable bit of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_CLKCLR_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_CLKCLR_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_TMU_CLR 0x00000800 -+/** Clear Clock Enable MRG -+ Clears the clock enable bit of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_CLKCLR_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_CLKCLR_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_MRG_CLR 0x00000400 -+/** Clear Clock Enable DISP -+ Clears the clock enable bit of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_CLKCLR_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_CLKCLR_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_DISP_CLR 0x00000200 -+/** Clear Clock Enable IQM -+ Clears the clock enable bit of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_CLKCLR_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_CLKCLR_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_IQM_CLR 0x00000100 -+/** Clear Clock Enable CPUE -+ Clears the clock enable bit of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_CLKCLR_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_CLKCLR_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_CPUE_CLR 0x00000080 -+/** Clear Clock Enable CPUI -+ Clears the clock enable bit of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_CLKCLR_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_CLKCLR_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_CPUI_CLR 0x00000040 -+/** Clear Clock Enable GPONE -+ Clears the clock enable bit of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_CLKCLR_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_CLKCLR_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_GPONE_CLR 0x00000020 -+/** Clear Clock Enable GPONI -+ Clears the clock enable bit of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_CLKCLR_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_CLKCLR_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_GPONI_CLR 0x00000010 -+/** Clear Clock Enable LAN3 -+ Clears the clock enable bit of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_CLKCLR_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN3_CLR 0x00000008 -+/** Clear Clock Enable LAN2 -+ Clears the clock enable bit of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_CLKCLR_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN2_CLR 0x00000004 -+/** Clear Clock Enable LAN1 -+ Clears the clock enable bit of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_CLKCLR_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN1_CLR 0x00000002 -+/** Clear Clock Enable LAN0 -+ Clears the clock enable bit of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_CLKCLR_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_CLKCLR_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_CLKCLR_LAN0_CLR 0x00000001 -+ -+/* Fields of "Activation Status Register" */ -+/** COP7 Status -+ Shows the activation status of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_ACTS_COP7 0x80000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP7_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP7_ACT 0x80000000 -+/** COP6 Status -+ Shows the activation status of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_ACTS_COP6 0x40000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP6_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP6_ACT 0x40000000 -+/** COP5 Status -+ Shows the activation status of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_ACTS_COP5 0x20000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP5_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP5_ACT 0x20000000 -+/** COP4 Status -+ Shows the activation status of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_ACTS_COP4 0x10000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP4_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP4_ACT 0x10000000 -+/** COP3 Status -+ Shows the activation status of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_ACTS_COP3 0x08000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP3_ACT 0x08000000 -+/** COP2 Status -+ Shows the activation status of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_ACTS_COP2 0x04000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP2_ACT 0x04000000 -+/** COP1 Status -+ Shows the activation status of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_ACTS_COP1 0x02000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP1_ACT 0x02000000 -+/** COP0 Status -+ Shows the activation status of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_ACTS_COP0 0x01000000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_COP0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_COP0_ACT 0x01000000 -+/** PE5 Status -+ Shows the activation status of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_ACTS_PE5 0x00200000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE5_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE5_ACT 0x00200000 -+/** PE4 Status -+ Shows the activation status of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_ACTS_PE4 0x00100000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE4_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE4_ACT 0x00100000 -+/** PE3 Status -+ Shows the activation status of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_ACTS_PE3 0x00080000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE3_ACT 0x00080000 -+/** PE2 Status -+ Shows the activation status of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_ACTS_PE2 0x00040000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE2_ACT 0x00040000 -+/** PE1 Status -+ Shows the activation status of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_ACTS_PE1 0x00020000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE1_ACT 0x00020000 -+/** PE0 Status -+ Shows the activation status of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_ACTS_PE0 0x00010000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_PE0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_PE0_ACT 0x00010000 -+/** ARB Status -+ Shows the activation status of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_ACTS_ARB 0x00002000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_ARB_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_ARB_ACT 0x00002000 -+/** FSQM Status -+ Shows the activation status of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_ACTS_FSQM 0x00001000 -+/* The block is inactive. -+#define SYS_GPE_ACTS_FSQM_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_FSQM_ACT 0x00001000 -+/** TMU Status -+ Shows the activation status of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_ACTS_TMU 0x00000800 -+/* The block is inactive. -+#define SYS_GPE_ACTS_TMU_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_TMU_ACT 0x00000800 -+/** MRG Status -+ Shows the activation status of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_ACTS_MRG 0x00000400 -+/* The block is inactive. -+#define SYS_GPE_ACTS_MRG_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_MRG_ACT 0x00000400 -+/** DISP Status -+ Shows the activation status of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_ACTS_DISP 0x00000200 -+/* The block is inactive. -+#define SYS_GPE_ACTS_DISP_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_DISP_ACT 0x00000200 -+/** IQM Status -+ Shows the activation status of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_ACTS_IQM 0x00000100 -+/* The block is inactive. -+#define SYS_GPE_ACTS_IQM_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_IQM_ACT 0x00000100 -+/** CPUE Status -+ Shows the activation status of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_ACTS_CPUE 0x00000080 -+/* The block is inactive. -+#define SYS_GPE_ACTS_CPUE_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_CPUE_ACT 0x00000080 -+/** CPUI Status -+ Shows the activation status of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_ACTS_CPUI 0x00000040 -+/* The block is inactive. -+#define SYS_GPE_ACTS_CPUI_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_CPUI_ACT 0x00000040 -+/** GPONE Status -+ Shows the activation status of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_ACTS_GPONE 0x00000020 -+/* The block is inactive. -+#define SYS_GPE_ACTS_GPONE_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_GPONE_ACT 0x00000020 -+/** GPONI Status -+ Shows the activation status of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_ACTS_GPONI 0x00000010 -+/* The block is inactive. -+#define SYS_GPE_ACTS_GPONI_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_GPONI_ACT 0x00000010 -+/** LAN3 Status -+ Shows the activation status of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_ACTS_LAN3 0x00000008 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN3_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN3_ACT 0x00000008 -+/** LAN2 Status -+ Shows the activation status of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_ACTS_LAN2 0x00000004 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN2_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN2_ACT 0x00000004 -+/** LAN1 Status -+ Shows the activation status of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_ACTS_LAN1 0x00000002 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN1_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN1_ACT 0x00000002 -+/** LAN0 Status -+ Shows the activation status of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_ACTS_LAN0 0x00000001 -+/* The block is inactive. -+#define SYS_GPE_ACTS_LAN0_INACT 0x00000000 */ -+/** The block is active. */ -+#define SYS_GPE_ACTS_LAN0_ACT 0x00000001 -+ -+/* Fields of "Activation Register" */ -+/** Activate COP7 -+ Sets the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_ACT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP7_SET 0x80000000 -+/** Activate COP6 -+ Sets the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_ACT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP6_SET 0x40000000 -+/** Activate COP5 -+ Sets the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_ACT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP5_SET 0x20000000 -+/** Activate COP4 -+ Sets the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_ACT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP4_SET 0x10000000 -+/** Activate COP3 -+ Sets the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_ACT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP3_SET 0x08000000 -+/** Activate COP2 -+ Sets the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_ACT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP2_SET 0x04000000 -+/** Activate COP1 -+ Sets the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_ACT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP1_SET 0x02000000 -+/** Activate COP0 -+ Sets the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_ACT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_ACT_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_COP0_SET 0x01000000 -+/** Activate PE5 -+ Sets the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_ACT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_ACT_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE5_SET 0x00200000 -+/** Activate PE4 -+ Sets the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_ACT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_ACT_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE4_SET 0x00100000 -+/** Activate PE3 -+ Sets the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_ACT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_ACT_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE3_SET 0x00080000 -+/** Activate PE2 -+ Sets the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_ACT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_ACT_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE2_SET 0x00040000 -+/** Activate PE1 -+ Sets the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_ACT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_ACT_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE1_SET 0x00020000 -+/** Activate PE0 -+ Sets the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_ACT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_ACT_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_PE0_SET 0x00010000 -+/** Activate ARB -+ Sets the activation flag of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_ACT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_ACT_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_ARB_SET 0x00002000 -+/** Activate FSQM -+ Sets the activation flag of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_ACT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_ACT_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_FSQM_SET 0x00001000 -+/** Activate TMU -+ Sets the activation flag of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_ACT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_ACT_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_TMU_SET 0x00000800 -+/** Activate MRG -+ Sets the activation flag of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_ACT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_ACT_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_MRG_SET 0x00000400 -+/** Activate DISP -+ Sets the activation flag of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_ACT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_ACT_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_DISP_SET 0x00000200 -+/** Activate IQM -+ Sets the activation flag of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_ACT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_ACT_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_IQM_SET 0x00000100 -+/** Activate CPUE -+ Sets the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_ACT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_ACT_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_CPUE_SET 0x00000080 -+/** Activate CPUI -+ Sets the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_ACT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_ACT_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_CPUI_SET 0x00000040 -+/** Activate GPONE -+ Sets the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_ACT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_ACT_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_GPONE_SET 0x00000020 -+/** Activate GPONI -+ Sets the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_ACT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_ACT_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_GPONI_SET 0x00000010 -+/** Activate LAN3 -+ Sets the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_ACT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_ACT_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN3_SET 0x00000008 -+/** Activate LAN2 -+ Sets the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_ACT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_ACT_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN2_SET 0x00000004 -+/** Activate LAN1 -+ Sets the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_ACT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_ACT_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN1_SET 0x00000002 -+/** Activate LAN0 -+ Sets the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_ACT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_ACT_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_ACT_LAN0_SET 0x00000001 -+ -+/* Fields of "Deactivation Register" */ -+/** Deactivate COP7 -+ Clears the activation flag of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_DEACT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP7_CLR 0x80000000 -+/** Deactivate COP6 -+ Clears the activation flag of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_DEACT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP6_CLR 0x40000000 -+/** Deactivate COP5 -+ Clears the activation flag of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_DEACT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP5_CLR 0x20000000 -+/** Deactivate COP4 -+ Clears the activation flag of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_DEACT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP4_CLR 0x10000000 -+/** Deactivate COP3 -+ Clears the activation flag of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_DEACT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP3_CLR 0x08000000 -+/** Deactivate COP2 -+ Clears the activation flag of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_DEACT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP2_CLR 0x04000000 -+/** Deactivate COP1 -+ Clears the activation flag of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_DEACT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP1_CLR 0x02000000 -+/** Deactivate COP0 -+ Clears the activation flag of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_DEACT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_DEACT_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_COP0_CLR 0x01000000 -+/** Deactivate PE5 -+ Clears the activation flag of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_DEACT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE5_CLR 0x00200000 -+/** Deactivate PE4 -+ Clears the activation flag of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_DEACT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE4_CLR 0x00100000 -+/** Deactivate PE3 -+ Clears the activation flag of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_DEACT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE3_CLR 0x00080000 -+/** Deactivate PE2 -+ Clears the activation flag of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_DEACT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE2_CLR 0x00040000 -+/** Deactivate PE1 -+ Clears the activation flag of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_DEACT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE1_CLR 0x00020000 -+/** Deactivate PE0 -+ Clears the activation flag of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_DEACT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_DEACT_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_PE0_CLR 0x00010000 -+/** Deactivate ARB -+ Clears the activation flag of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_DEACT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_DEACT_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_ARB_CLR 0x00002000 -+/** Deactivate FSQM -+ Clears the activation flag of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_DEACT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_DEACT_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_FSQM_CLR 0x00001000 -+/** Deactivate TMU -+ Clears the activation flag of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_DEACT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_DEACT_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_TMU_CLR 0x00000800 -+/** Deactivate MRG -+ Clears the activation flag of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_DEACT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_DEACT_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_MRG_CLR 0x00000400 -+/** Deactivate DISP -+ Clears the activation flag of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_DEACT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_DEACT_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_DISP_CLR 0x00000200 -+/** Deactivate IQM -+ Clears the activation flag of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_DEACT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_DEACT_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_IQM_CLR 0x00000100 -+/** Deactivate CPUE -+ Clears the activation flag of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_DEACT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_DEACT_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_CPUE_CLR 0x00000080 -+/** Deactivate CPUI -+ Clears the activation flag of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_DEACT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_DEACT_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_CPUI_CLR 0x00000040 -+/** Deactivate GPONE -+ Clears the activation flag of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_DEACT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_DEACT_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_GPONE_CLR 0x00000020 -+/** Deactivate GPONI -+ Clears the activation flag of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_DEACT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_DEACT_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_GPONI_CLR 0x00000010 -+/** Deactivate LAN3 -+ Clears the activation flag of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_DEACT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN3_CLR 0x00000008 -+/** Deactivate LAN2 -+ Clears the activation flag of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_DEACT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN2_CLR 0x00000004 -+/** Deactivate LAN1 -+ Clears the activation flag of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_DEACT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN1_CLR 0x00000002 -+/** Deactivate LAN0 -+ Clears the activation flag of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_DEACT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_DEACT_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_DEACT_LAN0_CLR 0x00000001 -+ -+/* Fields of "Reboot Trigger Register" */ -+/** Reboot COP7 -+ Triggers a reboot of the COP7 domain. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_RBT_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP7_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP7_TRIG 0x80000000 -+/** Reboot COP6 -+ Triggers a reboot of the COP6 domain. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_RBT_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP6_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP6_TRIG 0x40000000 -+/** Reboot COP5 -+ Triggers a reboot of the COP5 domain. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_RBT_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP5_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP5_TRIG 0x20000000 -+/** Reboot COP4 -+ Triggers a reboot of the COP4 domain. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_RBT_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP4_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP4_TRIG 0x10000000 -+/** Reboot COP3 -+ Triggers a reboot of the COP3 domain. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_RBT_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP3_TRIG 0x08000000 -+/** Reboot COP2 -+ Triggers a reboot of the COP2 domain. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_RBT_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP2_TRIG 0x04000000 -+/** Reboot COP1 -+ Triggers a reboot of the COP1 domain. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_RBT_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP1_TRIG 0x02000000 -+/** Reboot COP0 -+ Triggers a reboot of the COP0 domain. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_RBT_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_RBT_COP0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_COP0_TRIG 0x01000000 -+/** Reboot PE5 -+ Triggers a reboot of the PE5 domain. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_RBT_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_RBT_PE5_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE5_TRIG 0x00200000 -+/** Reboot PE4 -+ Triggers a reboot of the PE4 domain. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_RBT_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_RBT_PE4_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE4_TRIG 0x00100000 -+/** Reboot PE3 -+ Triggers a reboot of the PE3 domain. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_RBT_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_RBT_PE3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE3_TRIG 0x00080000 -+/** Reboot PE2 -+ Triggers a reboot of the PE2 domain. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_RBT_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_RBT_PE2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE2_TRIG 0x00040000 -+/** Reboot PE1 -+ Triggers a reboot of the PE1 domain. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_RBT_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_RBT_PE1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE1_TRIG 0x00020000 -+/** Reboot PE0 -+ Triggers a reboot of the PE0 domain. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_RBT_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_RBT_PE0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_PE0_TRIG 0x00010000 -+/** Reboot ARB -+ Triggers a reboot of the ARB domain. This domain contains the Arbiter. */ -+#define SYS_GPE_RBT_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_RBT_ARB_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_ARB_TRIG 0x00002000 -+/** Reboot FSQM -+ Triggers a reboot of the FSQM domain. This domain contains the FSQM. */ -+#define SYS_GPE_RBT_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_RBT_FSQM_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_FSQM_TRIG 0x00001000 -+/** Reboot TMU -+ Triggers a reboot of the TMU domain. This domain contains the TMU. */ -+#define SYS_GPE_RBT_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_RBT_TMU_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_TMU_TRIG 0x00000800 -+/** Reboot MRG -+ Triggers a reboot of the MRG domain. This domain contains the Merger. */ -+#define SYS_GPE_RBT_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_RBT_MRG_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_MRG_TRIG 0x00000400 -+/** Reboot DISP -+ Triggers a reboot of the DISP domain. This domain contains the Dispatcher. */ -+#define SYS_GPE_RBT_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_RBT_DISP_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_DISP_TRIG 0x00000200 -+/** Reboot IQM -+ Triggers a reboot of the IQM domain. This domain contains the IQM. */ -+#define SYS_GPE_RBT_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_RBT_IQM_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_IQM_TRIG 0x00000100 -+/** Reboot CPUE -+ Triggers a reboot of the CPUE domain. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_RBT_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_RBT_CPUE_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_CPUE_TRIG 0x00000080 -+/** Reboot CPUI -+ Triggers a reboot of the CPUI domain. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_RBT_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_RBT_CPUI_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_CPUI_TRIG 0x00000040 -+/** Reboot GPONE -+ Triggers a reboot of the GPONE domain. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_RBT_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_RBT_GPONE_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_GPONE_TRIG 0x00000020 -+/** Reboot GPONI -+ Triggers a reboot of the GPONI domain. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_RBT_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_RBT_GPONI_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_GPONI_TRIG 0x00000010 -+/** Reboot LAN3 -+ Triggers a reboot of the LAN3 domain. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_RBT_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_RBT_LAN3_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN3_TRIG 0x00000008 -+/** Reboot LAN2 -+ Triggers a reboot of the LAN2 domain. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_RBT_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_RBT_LAN2_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN2_TRIG 0x00000004 -+/** Reboot LAN1 -+ Triggers a reboot of the LAN1 domain. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_RBT_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_RBT_LAN1_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN1_TRIG 0x00000002 -+/** Reboot LAN0 -+ Triggers a reboot of the LAN0 domain. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_RBT_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_RBT_LAN0_NOP 0x00000000 */ -+/** Trigger */ -+#define SYS_GPE_RBT_LAN0_TRIG 0x00000001 -+ -+/* Fields of "Power Down Configuration Register" */ -+/** Enable Power Down COP7 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP7 0x80000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP7_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP7_EN 0x80000000 -+/** Enable Power Down COP6 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP6 0x40000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP6_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP6_EN 0x40000000 -+/** Enable Power Down COP5 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP5 0x20000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP5_EN 0x20000000 -+/** Enable Power Down COP4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP4 0x10000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP4_EN 0x10000000 -+/** Enable Power Down COP3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP3 0x08000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP3_EN 0x08000000 -+/** Enable Power Down COP2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP2 0x04000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP2_EN 0x04000000 -+/** Enable Power Down COP1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP1 0x02000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP1_EN 0x02000000 -+/** Enable Power Down COP0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_COP0 0x01000000 -+/* Disable -+#define SYS_GPE_PDCFG_COP0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_COP0_EN 0x01000000 -+/** Enable Power Down PE5 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE5 0x00200000 -+/* Disable -+#define SYS_GPE_PDCFG_PE5_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE5_EN 0x00200000 -+/** Enable Power Down PE4 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE4 0x00100000 -+/* Disable -+#define SYS_GPE_PDCFG_PE4_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE4_EN 0x00100000 -+/** Enable Power Down PE3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE3 0x00080000 -+/* Disable -+#define SYS_GPE_PDCFG_PE3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE3_EN 0x00080000 -+/** Enable Power Down PE2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE2 0x00040000 -+/* Disable -+#define SYS_GPE_PDCFG_PE2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE2_EN 0x00040000 -+/** Enable Power Down PE1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE1 0x00020000 -+/* Disable -+#define SYS_GPE_PDCFG_PE1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE1_EN 0x00020000 -+/** Enable Power Down PE0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_PE0 0x00010000 -+/* Disable -+#define SYS_GPE_PDCFG_PE0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_PE0_EN 0x00010000 -+/** Enable Power Down ARB -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_ARB 0x00002000 -+/* Disable -+#define SYS_GPE_PDCFG_ARB_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_ARB_EN 0x00002000 -+/** Enable Power Down FSQM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_FSQM 0x00001000 -+/* Disable -+#define SYS_GPE_PDCFG_FSQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_FSQM_EN 0x00001000 -+/** Enable Power Down TMU -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_TMU 0x00000800 -+/* Disable -+#define SYS_GPE_PDCFG_TMU_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_TMU_EN 0x00000800 -+/** Enable Power Down MRG -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_MRG 0x00000400 -+/* Disable -+#define SYS_GPE_PDCFG_MRG_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_MRG_EN 0x00000400 -+/** Enable Power Down DISP -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_DISP 0x00000200 -+/* Disable -+#define SYS_GPE_PDCFG_DISP_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_DISP_EN 0x00000200 -+/** Enable Power Down IQM -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_IQM 0x00000100 -+/* Disable -+#define SYS_GPE_PDCFG_IQM_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_IQM_EN 0x00000100 -+/** Enable Power Down CPUE -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_CPUE 0x00000080 -+/* Disable -+#define SYS_GPE_PDCFG_CPUE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_CPUE_EN 0x00000080 -+/** Enable Power Down CPUI -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_CPUI 0x00000040 -+/* Disable -+#define SYS_GPE_PDCFG_CPUI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_CPUI_EN 0x00000040 -+/** Enable Power Down GPONE -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_GPONE 0x00000020 -+/* Disable -+#define SYS_GPE_PDCFG_GPONE_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_GPONE_EN 0x00000020 -+/** Enable Power Down GPONI -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_GPONI 0x00000010 -+/* Disable -+#define SYS_GPE_PDCFG_GPONI_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_GPONI_EN 0x00000010 -+/** Enable Power Down LAN3 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN3 0x00000008 -+/* Disable -+#define SYS_GPE_PDCFG_LAN3_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN3_EN 0x00000008 -+/** Enable Power Down LAN2 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN2 0x00000004 -+/* Disable -+#define SYS_GPE_PDCFG_LAN2_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN2_EN 0x00000004 -+/** Enable Power Down LAN1 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN1 0x00000002 -+/* Disable -+#define SYS_GPE_PDCFG_LAN1_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN1_EN 0x00000002 -+/** Enable Power Down LAN0 -+ Ignore this bit as power-gating is not supported for this chip. */ -+#define SYS_GPE_PDCFG_LAN0 0x00000001 -+/* Disable -+#define SYS_GPE_PDCFG_LAN0_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_PDCFG_LAN0_EN 0x00000001 -+ -+/* Fields of "Sleep Source Configuration Register" */ -+/** Sleep/Wakeup Source CPU -+ Selects the CPU access signal as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_CPU 0x00020000 -+/* Not selected -+#define SYS_GPE_SSCFG_CPU_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_CPU_SEL 0x00020000 -+/** Sleep/Wakeup Source FSQM -+ Selects the FSQM signal as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_FSQM 0x00008000 -+/* Not selected -+#define SYS_GPE_SSCFG_FSQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_FSQM_SEL 0x00008000 -+/** Sleep/Wakeup Source GPONT -+ Selects the FIFO empty signal of the TCONT Request FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONT 0x00002000 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONT_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONT_SEL 0x00002000 -+/** Sleep/Wakeup Source GPONE -+ Selects the FIFO empty signal of the EGRESS FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONE 0x00001000 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONE_SEL 0x00001000 -+/** Sleep/Wakeup Source LAN3E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN3 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN3E 0x00000800 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN3E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN3E_SEL 0x00000800 -+/** Sleep/Wakeup Source LAN2E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN2 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN2E 0x00000400 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN2E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN2E_SEL 0x00000400 -+/** Sleep/Wakeup Source LAN1E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN1 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN1E 0x00000200 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN1E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN1E_SEL 0x00000200 -+/** Sleep/Wakeup Source LAN0E -+ Selects the FIFO empty signal of the EGRESS FIFO of port LAN0 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN0E 0x00000100 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN0E_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN0E_SEL 0x00000100 -+/** Sleep/Wakeup Source GPONI -+ Selects the FIFO empty signal of the INGRESS FIFO of port GPON as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_GPONI 0x00000010 -+/* Not selected -+#define SYS_GPE_SSCFG_GPONI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_GPONI_SEL 0x00000010 -+/** Sleep/Wakeup Source LAN3I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN3 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN3I 0x00000008 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN3I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN3I_SEL 0x00000008 -+/** Sleep/Wakeup Source LAN2I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN2 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN2I 0x00000004 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN2I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN2I_SEL 0x00000004 -+/** Sleep/Wakeup Source LAN1I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN1 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN1I 0x00000002 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN1I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN1I_SEL 0x00000002 -+/** Sleep/Wakeup Source LAN0I -+ Selects the FIFO empty signal of the INGRESS FIFO of port LAN0 as sleep/wakeup source. */ -+#define SYS_GPE_SSCFG_LAN0I 0x00000001 -+/* Not selected -+#define SYS_GPE_SSCFG_LAN0I_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SSCFG_LAN0I_SEL 0x00000001 -+ -+/* Fields of "Sleep Source Timer Register" */ -+/** Sleep Delay Value -+ A HW sleep request is delayed by this value multiplied by 3.2ns before it takes effect. A wakeup request is not delayed but takes effect immediately. Values lower than 256 are limited to 256. */ -+#define SYS_GPE_SST_SDV_MASK 0x7FFFFFFF -+/** field offset */ -+#define SYS_GPE_SST_SDV_OFFSET 0 -+ -+/* Fields of "Sleep Destination Status Register" */ -+/** Shutoff COP7 on HW Sleep -+ If selected the domain COP7 is shutoff on a hardware sleep request. This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDS_COP7 0x80000000 -+/* Not selected -+#define SYS_GPE_SDS_COP7_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP7_SEL 0x80000000 -+/** Shutoff COP6 on HW Sleep -+ If selected the domain COP6 is shutoff on a hardware sleep request. This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDS_COP6 0x40000000 -+/* Not selected -+#define SYS_GPE_SDS_COP6_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP6_SEL 0x40000000 -+/** Shutoff COP5 on HW Sleep -+ If selected the domain COP5 is shutoff on a hardware sleep request. This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDS_COP5 0x20000000 -+/* Not selected -+#define SYS_GPE_SDS_COP5_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP5_SEL 0x20000000 -+/** Shutoff COP4 on HW Sleep -+ If selected the domain COP4 is shutoff on a hardware sleep request. This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDS_COP4 0x10000000 -+/* Not selected -+#define SYS_GPE_SDS_COP4_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP4_SEL 0x10000000 -+/** Shutoff COP3 on HW Sleep -+ If selected the domain COP3 is shutoff on a hardware sleep request. This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDS_COP3 0x08000000 -+/* Not selected -+#define SYS_GPE_SDS_COP3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP3_SEL 0x08000000 -+/** Shutoff COP2 on HW Sleep -+ If selected the domain COP2 is shutoff on a hardware sleep request. This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDS_COP2 0x04000000 -+/* Not selected -+#define SYS_GPE_SDS_COP2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP2_SEL 0x04000000 -+/** Shutoff COP1 on HW Sleep -+ If selected the domain COP1 is shutoff on a hardware sleep request. This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDS_COP1 0x02000000 -+/* Not selected -+#define SYS_GPE_SDS_COP1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP1_SEL 0x02000000 -+/** Shutoff COP0 on HW Sleep -+ If selected the domain COP0 is shutoff on a hardware sleep request. This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDS_COP0 0x01000000 -+/* Not selected -+#define SYS_GPE_SDS_COP0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_COP0_SEL 0x01000000 -+/** Shutoff PE5 on HW Sleep -+ If selected the domain PE5 is shutoff on a hardware sleep request. This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDS_PE5 0x00200000 -+/* Not selected -+#define SYS_GPE_SDS_PE5_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE5_SEL 0x00200000 -+/** Shutoff PE4 on HW Sleep -+ If selected the domain PE4 is shutoff on a hardware sleep request. This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDS_PE4 0x00100000 -+/* Not selected -+#define SYS_GPE_SDS_PE4_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE4_SEL 0x00100000 -+/** Shutoff PE3 on HW Sleep -+ If selected the domain PE3 is shutoff on a hardware sleep request. This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDS_PE3 0x00080000 -+/* Not selected -+#define SYS_GPE_SDS_PE3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE3_SEL 0x00080000 -+/** Shutoff PE2 on HW Sleep -+ If selected the domain PE2 is shutoff on a hardware sleep request. This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDS_PE2 0x00040000 -+/* Not selected -+#define SYS_GPE_SDS_PE2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE2_SEL 0x00040000 -+/** Shutoff PE1 on HW Sleep -+ If selected the domain PE1 is shutoff on a hardware sleep request. This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDS_PE1 0x00020000 -+/* Not selected -+#define SYS_GPE_SDS_PE1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE1_SEL 0x00020000 -+/** Shutoff PE0 on HW Sleep -+ If selected the domain PE0 is shutoff on a hardware sleep request. This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDS_PE0 0x00010000 -+/* Not selected -+#define SYS_GPE_SDS_PE0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_PE0_SEL 0x00010000 -+/** Shutoff ARB on HW Sleep -+ If selected the domain ARB is shutoff on a hardware sleep request. This domain contains the Arbiter. */ -+#define SYS_GPE_SDS_ARB 0x00002000 -+/* Not selected -+#define SYS_GPE_SDS_ARB_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_ARB_SEL 0x00002000 -+/** Shutoff FSQM on HW Sleep -+ If selected the domain FSQM is shutoff on a hardware sleep request. This domain contains the FSQM. */ -+#define SYS_GPE_SDS_FSQM 0x00001000 -+/* Not selected -+#define SYS_GPE_SDS_FSQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_FSQM_SEL 0x00001000 -+/** Shutoff TMU on HW Sleep -+ If selected the domain TMU is shutoff on a hardware sleep request. This domain contains the TMU. */ -+#define SYS_GPE_SDS_TMU 0x00000800 -+/* Not selected -+#define SYS_GPE_SDS_TMU_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_TMU_SEL 0x00000800 -+/** Shutoff MRG on HW Sleep -+ If selected the domain MRG is shutoff on a hardware sleep request. This domain contains the Merger. */ -+#define SYS_GPE_SDS_MRG 0x00000400 -+/* Not selected -+#define SYS_GPE_SDS_MRG_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_MRG_SEL 0x00000400 -+/** Shutoff DISP on HW Sleep -+ If selected the domain DISP is shutoff on a hardware sleep request. This domain contains the Dispatcher. */ -+#define SYS_GPE_SDS_DISP 0x00000200 -+/* Not selected -+#define SYS_GPE_SDS_DISP_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_DISP_SEL 0x00000200 -+/** Shutoff IQM on HW Sleep -+ If selected the domain IQM is shutoff on a hardware sleep request. This domain contains the IQM. */ -+#define SYS_GPE_SDS_IQM 0x00000100 -+/* Not selected -+#define SYS_GPE_SDS_IQM_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_IQM_SEL 0x00000100 -+/** Shutoff CPUE on HW Sleep -+ If selected the domain CPUE is shutoff on a hardware sleep request. This domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDS_CPUE 0x00000080 -+/* Not selected -+#define SYS_GPE_SDS_CPUE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_CPUE_SEL 0x00000080 -+/** Shutoff CPUI on HW Sleep -+ If selected the domain CPUI is shutoff on a hardware sleep request. This domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDS_CPUI 0x00000040 -+/* Not selected -+#define SYS_GPE_SDS_CPUI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_CPUI_SEL 0x00000040 -+/** Shutoff GPONE on HW Sleep -+ If selected the domain GPONE is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDS_GPONE 0x00000020 -+/* Not selected -+#define SYS_GPE_SDS_GPONE_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_GPONE_SEL 0x00000020 -+/** Shutoff GPONI on HW Sleep -+ If selected the domain GPONI is shutoff on a hardware sleep request. This domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDS_GPONI 0x00000010 -+/* Not selected -+#define SYS_GPE_SDS_GPONI_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_GPONI_SEL 0x00000010 -+/** Shutoff LAN3 on HW Sleep -+ If selected the domain LAN3 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDS_LAN3 0x00000008 -+/* Not selected -+#define SYS_GPE_SDS_LAN3_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN3_SEL 0x00000008 -+/** Shutoff LAN2 on HW Sleep -+ If selected the domain LAN2 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDS_LAN2 0x00000004 -+/* Not selected -+#define SYS_GPE_SDS_LAN2_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN2_SEL 0x00000004 -+/** Shutoff LAN1 on HW Sleep -+ If selected the domain LAN1 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDS_LAN1 0x00000002 -+/* Not selected -+#define SYS_GPE_SDS_LAN1_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN1_SEL 0x00000002 -+/** Shutoff LAN0 on HW Sleep -+ If selected the domain LAN0 is shutoff on a hardware sleep request. This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDS_LAN0 0x00000001 -+/* Not selected -+#define SYS_GPE_SDS_LAN0_NSEL 0x00000000 */ -+/** Selected */ -+#define SYS_GPE_SDS_LAN0_SEL 0x00000001 -+ -+/* Fields of "Sleep Destination Set Register" */ -+/** Set Sleep Selection COP7 -+ Sets the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDSET_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP7_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP7_SET 0x80000000 -+/** Set Sleep Selection COP6 -+ Sets the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDSET_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP6_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP6_SET 0x40000000 -+/** Set Sleep Selection COP5 -+ Sets the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDSET_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP5_SET 0x20000000 -+/** Set Sleep Selection COP4 -+ Sets the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDSET_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP4_SET 0x10000000 -+/** Set Sleep Selection COP3 -+ Sets the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDSET_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP3_SET 0x08000000 -+/** Set Sleep Selection COP2 -+ Sets the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDSET_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP2_SET 0x04000000 -+/** Set Sleep Selection COP1 -+ Sets the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDSET_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP1_SET 0x02000000 -+/** Set Sleep Selection COP0 -+ Sets the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDSET_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_SDSET_COP0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_COP0_SET 0x01000000 -+/** Set Sleep Selection PE5 -+ Sets the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDSET_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE5_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE5_SET 0x00200000 -+/** Set Sleep Selection PE4 -+ Sets the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDSET_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE4_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE4_SET 0x00100000 -+/** Set Sleep Selection PE3 -+ Sets the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDSET_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE3_SET 0x00080000 -+/** Set Sleep Selection PE2 -+ Sets the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDSET_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE2_SET 0x00040000 -+/** Set Sleep Selection PE1 -+ Sets the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDSET_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE1_SET 0x00020000 -+/** Set Sleep Selection PE0 -+ Sets the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDSET_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_SDSET_PE0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_PE0_SET 0x00010000 -+/** Set Sleep Selection ARB -+ Sets the selection bit for domain ARBThis domain contains the Arbiter. */ -+#define SYS_GPE_SDSET_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_SDSET_ARB_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_ARB_SET 0x00002000 -+/** Set Sleep Selection FSQM -+ Sets the selection bit for domain FSQMThis domain contains the FSQM. */ -+#define SYS_GPE_SDSET_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_SDSET_FSQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_FSQM_SET 0x00001000 -+/** Set Sleep Selection TMU -+ Sets the selection bit for domain TMUThis domain contains the TMU. */ -+#define SYS_GPE_SDSET_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_SDSET_TMU_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_TMU_SET 0x00000800 -+/** Set Sleep Selection MRG -+ Sets the selection bit for domain MRGThis domain contains the Merger. */ -+#define SYS_GPE_SDSET_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_SDSET_MRG_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_MRG_SET 0x00000400 -+/** Set Sleep Selection DISP -+ Sets the selection bit for domain DISPThis domain contains the Dispatcher. */ -+#define SYS_GPE_SDSET_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_SDSET_DISP_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_DISP_SET 0x00000200 -+/** Set Sleep Selection IQM -+ Sets the selection bit for domain IQMThis domain contains the IQM. */ -+#define SYS_GPE_SDSET_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_SDSET_IQM_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_IQM_SET 0x00000100 -+/** Set Sleep Selection CPUE -+ Sets the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDSET_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_SDSET_CPUE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_CPUE_SET 0x00000080 -+/** Set Sleep Selection CPUI -+ Sets the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDSET_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_SDSET_CPUI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_CPUI_SET 0x00000040 -+/** Set Sleep Selection GPONE -+ Sets the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDSET_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_SDSET_GPONE_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_GPONE_SET 0x00000020 -+/** Set Sleep Selection GPONI -+ Sets the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDSET_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_SDSET_GPONI_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_GPONI_SET 0x00000010 -+/** Set Sleep Selection LAN3 -+ Sets the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDSET_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN3_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN3_SET 0x00000008 -+/** Set Sleep Selection LAN2 -+ Sets the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDSET_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN2_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN2_SET 0x00000004 -+/** Set Sleep Selection LAN1 -+ Sets the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDSET_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN1_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN1_SET 0x00000002 -+/** Set Sleep Selection LAN0 -+ Sets the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDSET_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_SDSET_LAN0_NOP 0x00000000 */ -+/** Set */ -+#define SYS_GPE_SDSET_LAN0_SET 0x00000001 -+ -+/* Fields of "Sleep Destination Clear Register" */ -+/** Clear Sleep Selection COP7 -+ Clears the selection bit for domain COP7This domain contains the Coprocessor 7 of the SCE. */ -+#define SYS_GPE_SDCLR_COP7 0x80000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP7_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP7_CLR 0x80000000 -+/** Clear Sleep Selection COP6 -+ Clears the selection bit for domain COP6This domain contains the Coprocessor 6 of the SCE. */ -+#define SYS_GPE_SDCLR_COP6 0x40000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP6_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP6_CLR 0x40000000 -+/** Clear Sleep Selection COP5 -+ Clears the selection bit for domain COP5This domain contains the Coprocessor 5 of the SCE. */ -+#define SYS_GPE_SDCLR_COP5 0x20000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP5_CLR 0x20000000 -+/** Clear Sleep Selection COP4 -+ Clears the selection bit for domain COP4This domain contains the Coprocessor 4 of the SCE. */ -+#define SYS_GPE_SDCLR_COP4 0x10000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP4_CLR 0x10000000 -+/** Clear Sleep Selection COP3 -+ Clears the selection bit for domain COP3This domain contains the Coprocessor 3 of the SCE. */ -+#define SYS_GPE_SDCLR_COP3 0x08000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP3_CLR 0x08000000 -+/** Clear Sleep Selection COP2 -+ Clears the selection bit for domain COP2This domain contains the Coprocessor 2 of the SCE. */ -+#define SYS_GPE_SDCLR_COP2 0x04000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP2_CLR 0x04000000 -+/** Clear Sleep Selection COP1 -+ Clears the selection bit for domain COP1This domain contains the Coprocessor 1 of the SCE. */ -+#define SYS_GPE_SDCLR_COP1 0x02000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP1_CLR 0x02000000 -+/** Clear Sleep Selection COP0 -+ Clears the selection bit for domain COP0This domain contains the Coprocessor 0 of the SCE. */ -+#define SYS_GPE_SDCLR_COP0 0x01000000 -+/* No-Operation -+#define SYS_GPE_SDCLR_COP0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_COP0_CLR 0x01000000 -+/** Clear Sleep Selection PE5 -+ Clears the selection bit for domain PE5This domain contains the Processing Element 5 of the SCE. */ -+#define SYS_GPE_SDCLR_PE5 0x00200000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE5_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE5_CLR 0x00200000 -+/** Clear Sleep Selection PE4 -+ Clears the selection bit for domain PE4This domain contains the Processing Element 4 of the SCE. */ -+#define SYS_GPE_SDCLR_PE4 0x00100000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE4_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE4_CLR 0x00100000 -+/** Clear Sleep Selection PE3 -+ Clears the selection bit for domain PE3This domain contains the Processing Element 3 of the SCE. */ -+#define SYS_GPE_SDCLR_PE3 0x00080000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE3_CLR 0x00080000 -+/** Clear Sleep Selection PE2 -+ Clears the selection bit for domain PE2This domain contains the Processing Element 2 of the SCE. */ -+#define SYS_GPE_SDCLR_PE2 0x00040000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE2_CLR 0x00040000 -+/** Clear Sleep Selection PE1 -+ Clears the selection bit for domain PE1This domain contains the Processing Element 1 of the SCE. */ -+#define SYS_GPE_SDCLR_PE1 0x00020000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE1_CLR 0x00020000 -+/** Clear Sleep Selection PE0 -+ Clears the selection bit for domain PE0This domain contains the Processing Element 0 of the SCE. */ -+#define SYS_GPE_SDCLR_PE0 0x00010000 -+/* No-Operation -+#define SYS_GPE_SDCLR_PE0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_PE0_CLR 0x00010000 -+/** Clear Sleep Selection ARB -+ Clears the selection bit for domain ARBThis domain contains the Arbiter. */ -+#define SYS_GPE_SDCLR_ARB 0x00002000 -+/* No-Operation -+#define SYS_GPE_SDCLR_ARB_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_ARB_CLR 0x00002000 -+/** Clear Sleep Selection FSQM -+ Clears the selection bit for domain FSQMThis domain contains the FSQM. */ -+#define SYS_GPE_SDCLR_FSQM 0x00001000 -+/* No-Operation -+#define SYS_GPE_SDCLR_FSQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_FSQM_CLR 0x00001000 -+/** Clear Sleep Selection TMU -+ Clears the selection bit for domain TMUThis domain contains the TMU. */ -+#define SYS_GPE_SDCLR_TMU 0x00000800 -+/* No-Operation -+#define SYS_GPE_SDCLR_TMU_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_TMU_CLR 0x00000800 -+/** Clear Sleep Selection MRG -+ Clears the selection bit for domain MRGThis domain contains the Merger. */ -+#define SYS_GPE_SDCLR_MRG 0x00000400 -+/* No-Operation -+#define SYS_GPE_SDCLR_MRG_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_MRG_CLR 0x00000400 -+/** Clear Sleep Selection DISP -+ Clears the selection bit for domain DISPThis domain contains the Dispatcher. */ -+#define SYS_GPE_SDCLR_DISP 0x00000200 -+/* No-Operation -+#define SYS_GPE_SDCLR_DISP_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_DISP_CLR 0x00000200 -+/** Clear Sleep Selection IQM -+ Clears the selection bit for domain IQMThis domain contains the IQM. */ -+#define SYS_GPE_SDCLR_IQM 0x00000100 -+/* No-Operation -+#define SYS_GPE_SDCLR_IQM_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_IQM_CLR 0x00000100 -+/** Clear Sleep Selection CPUE -+ Clears the selection bit for domain CPUEThis domain contains all parts related to the CPU EGRESS interface. */ -+#define SYS_GPE_SDCLR_CPUE 0x00000080 -+/* No-Operation -+#define SYS_GPE_SDCLR_CPUE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_CPUE_CLR 0x00000080 -+/** Clear Sleep Selection CPUI -+ Clears the selection bit for domain CPUIThis domain contains all parts related to the CPU INGRESS interface. */ -+#define SYS_GPE_SDCLR_CPUI 0x00000040 -+/* No-Operation -+#define SYS_GPE_SDCLR_CPUI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_CPUI_CLR 0x00000040 -+/** Clear Sleep Selection GPONE -+ Clears the selection bit for domain GPONEThis domain contains all parts related to the GPON (GTC) EGRESS interface. */ -+#define SYS_GPE_SDCLR_GPONE 0x00000020 -+/* No-Operation -+#define SYS_GPE_SDCLR_GPONE_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_GPONE_CLR 0x00000020 -+/** Clear Sleep Selection GPONI -+ Clears the selection bit for domain GPONIThis domain contains all parts related to the GPON (GTC) INGRESS interface. */ -+#define SYS_GPE_SDCLR_GPONI 0x00000010 -+/* No-Operation -+#define SYS_GPE_SDCLR_GPONI_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_GPONI_CLR 0x00000010 -+/** Clear Sleep Selection LAN3 -+ Clears the selection bit for domain LAN3This domain contains all parts related to the LAN3 interface. */ -+#define SYS_GPE_SDCLR_LAN3 0x00000008 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN3_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN3_CLR 0x00000008 -+/** Clear Sleep Selection LAN2 -+ Clears the selection bit for domain LAN2This domain contains all parts related to the LAN2 interface. */ -+#define SYS_GPE_SDCLR_LAN2 0x00000004 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN2_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN2_CLR 0x00000004 -+/** Clear Sleep Selection LAN1 -+ Clears the selection bit for domain LAN1This domain contains all parts related to the LAN1 interface. */ -+#define SYS_GPE_SDCLR_LAN1 0x00000002 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN1_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN1_CLR 0x00000002 -+/** Clear Sleep Selection LAN0 -+ Clears the selection bit for domain LAN0This domain contains all parts related to the LAN0 interface. */ -+#define SYS_GPE_SDCLR_LAN0 0x00000001 -+/* No-Operation -+#define SYS_GPE_SDCLR_LAN0_NOP 0x00000000 */ -+/** Clear */ -+#define SYS_GPE_SDCLR_LAN0_CLR 0x00000001 -+ -+/* Fields of "IRNCS Capture Register" */ -+/** FSQM wakeup request -+ The FSQM submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMWR 0x80000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_FSQMWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMWR_INTACK 0x80000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_FSQMWR_INTOCC 0x80000000 -+/** GPONT wakeup request -+ The TCONT Request FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTWR 0x20000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONTWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTWR_INTACK 0x20000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONTWR_INTOCC 0x20000000 -+/** GPONE wakeup request -+ The EGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONEWR 0x10000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONEWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONEWR_INTACK 0x10000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONEWR_INTOCC 0x10000000 -+/** LAN3E wakeup request -+ The EGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR 0x08000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR_INTACK 0x08000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3EWR_INTOCC 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR 0x04000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR_INTACK 0x04000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2EWR_INTOCC 0x04000000 -+/** LAN1E wakeup request -+ The EGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR 0x02000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR_INTACK 0x02000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1EWR_INTOCC 0x02000000 -+/** LAN0E wakeup request -+ The EGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR 0x01000000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0EWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR_INTACK 0x01000000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0EWR_INTOCC 0x01000000 -+/** GPONI wakeup request -+ The INGRESS FIFO of port GPON submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONIWR 0x00100000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONIWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONIWR_INTACK 0x00100000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONIWR_INTOCC 0x00100000 -+/** LAN3I wakeup request -+ The INGRESS FIFO of port LAN3 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR 0x00080000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR_INTACK 0x00080000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3IWR_INTOCC 0x00080000 -+/** LAN2I wakeup request -+ The INGRESS FIFO of port LAN2 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR 0x00040000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR_INTACK 0x00040000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2IWR_INTOCC 0x00040000 -+/** LAN1I wakeup request -+ The INGRESS FIFO of port LAN1 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR 0x00020000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR_INTACK 0x00020000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1IWR_INTOCC 0x00020000 -+/** LAN0I wakeup request -+ The INGRESS FIFO of port LAN0 submitted a wakeup request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR 0x00010000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0IWR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR_INTACK 0x00010000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0IWR_INTOCC 0x00010000 -+/** FSQM sleep request -+ The FSQM submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMSR 0x00008000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_FSQMSR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_FSQMSR_INTACK 0x00008000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_FSQMSR_INTOCC 0x00008000 -+/** GPONT sleep request -+ The TCONT Request FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTSR 0x00002000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONTSR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONTSR_INTACK 0x00002000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONTSR_INTOCC 0x00002000 -+/** GPONE sleep request -+ The EGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONESR 0x00001000 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONESR_INTACK 0x00001000 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONESR_INTOCC 0x00001000 -+/** LAN3E sleep request -+ The EGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR 0x00000800 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR_INTACK 0x00000800 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3ESR_INTOCC 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR 0x00000400 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR_INTACK 0x00000400 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2ESR_INTOCC 0x00000400 -+/** LAN1E sleep request -+ The EGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR 0x00000200 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR_INTACK 0x00000200 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1ESR_INTOCC 0x00000200 -+/** LAN0E sleep request -+ The EGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR 0x00000100 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0ESR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR_INTACK 0x00000100 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0ESR_INTOCC 0x00000100 -+/** GPONI sleep request -+ The INGRESS FIFO of port GPON submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONISR 0x00000010 -+/* Nothing -+#define SYS_GPE_IRNCSCR_GPONISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_GPONISR_INTACK 0x00000010 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_GPONISR_INTOCC 0x00000010 -+/** LAN3I sleep request -+ The INGRESS FIFO of port LAN3 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR 0x00000008 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN3ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR_INTACK 0x00000008 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN3ISR_INTOCC 0x00000008 -+/** LAN2I sleep request -+ The INGRESS FIFO of port LAN2 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR 0x00000004 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN2ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR_INTACK 0x00000004 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN2ISR_INTOCC 0x00000004 -+/** LAN1I sleep request -+ The INGRESS FIFO of port LAN1 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR 0x00000002 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN1ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR_INTACK 0x00000002 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN1ISR_INTOCC 0x00000002 -+/** LAN0I sleep request -+ The INGRESS FIFO of port LAN0 submitted a sleep request. This bit is edge-sensitive. This bit contributes to the indirect interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR 0x00000001 -+/* Nothing -+#define SYS_GPE_IRNCSCR_LAN0ISR_NULL 0x00000000 */ -+/** Write: Acknowledge the interrupt. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR_INTACK 0x00000001 -+/** Read: Interrupt occurred. */ -+#define SYS_GPE_IRNCSCR_LAN0ISR_INTOCC 0x00000001 -+ -+/* Fields of "IRNCS Interrupt Control Register" */ -+/** FSQM wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_FSQMWR 0x80000000 -+/** GPONT wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONTWR 0x20000000 -+/** GPONE wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONEWR 0x10000000 -+/** LAN3E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3EWR 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2EWR 0x04000000 -+/** LAN1E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1EWR 0x02000000 -+/** LAN0E wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0EWR 0x01000000 -+/** GPONI wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONIWR 0x00100000 -+/** LAN3I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3IWR 0x00080000 -+/** LAN2I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2IWR 0x00040000 -+/** LAN1I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1IWR 0x00020000 -+/** LAN0I wakeup request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0IWR 0x00010000 -+/** FSQM sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_FSQMSR 0x00008000 -+/** GPONT sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONTSR 0x00002000 -+/** GPONE sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONESR 0x00001000 -+/** LAN3E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3ESR 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2ESR 0x00000400 -+/** LAN1E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1ESR 0x00000200 -+/** LAN0E sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0ESR 0x00000100 -+/** GPONI sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_GPONISR 0x00000010 -+/** LAN3I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN3ISR 0x00000008 -+/** LAN2I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN2ISR 0x00000004 -+/** LAN1I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN1ISR 0x00000002 -+/** LAN0I sleep request -+ Interrupt control bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSICR_LAN0ISR 0x00000001 -+ -+/* Fields of "IRNCS Interrupt Enable Register" */ -+/** FSQM wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_FSQMWR 0x80000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_FSQMWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_FSQMWR_EN 0x80000000 -+/** GPONT wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONTWR 0x20000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONTWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONTWR_EN 0x20000000 -+/** GPONE wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONEWR 0x10000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONEWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONEWR_EN 0x10000000 -+/** LAN3E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3EWR 0x08000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3EWR_EN 0x08000000 -+/** LAN2E wakeup requestThe ENGRESS FIFO of port LAN2 submitted a wakeup request. -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2EWR 0x04000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2EWR_EN 0x04000000 -+/** LAN1E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1EWR 0x02000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1EWR_EN 0x02000000 -+/** LAN0E wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0EWR 0x01000000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0EWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0EWR_EN 0x01000000 -+/** GPONI wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONIWR 0x00100000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONIWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONIWR_EN 0x00100000 -+/** LAN3I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3IWR 0x00080000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3IWR_EN 0x00080000 -+/** LAN2I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2IWR 0x00040000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2IWR_EN 0x00040000 -+/** LAN1I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1IWR 0x00020000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1IWR_EN 0x00020000 -+/** LAN0I wakeup request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0IWR 0x00010000 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0IWR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0IWR_EN 0x00010000 -+/** FSQM sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_FSQMSR 0x00008000 -+/* Disable -+#define SYS_GPE_IRNCSEN_FSQMSR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_FSQMSR_EN 0x00008000 -+/** GPONT sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONTSR 0x00002000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONTSR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONTSR_EN 0x00002000 -+/** GPONE sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONESR 0x00001000 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONESR_EN 0x00001000 -+/** LAN3E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3ESR 0x00000800 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3ESR_EN 0x00000800 -+/** LAN2E sleep requestThe ENGRESS FIFO of port LAN2 submitted a sleep request. -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2ESR 0x00000400 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2ESR_EN 0x00000400 -+/** LAN1E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1ESR 0x00000200 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1ESR_EN 0x00000200 -+/** LAN0E sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0ESR 0x00000100 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0ESR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0ESR_EN 0x00000100 -+/** GPONI sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_GPONISR 0x00000010 -+/* Disable -+#define SYS_GPE_IRNCSEN_GPONISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_GPONISR_EN 0x00000010 -+/** LAN3I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN3ISR 0x00000008 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN3ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN3ISR_EN 0x00000008 -+/** LAN2I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN2ISR 0x00000004 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN2ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN2ISR_EN 0x00000004 -+/** LAN1I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN1ISR 0x00000002 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN1ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN1ISR_EN 0x00000002 -+/** LAN0I sleep request -+ Interrupt enable bit for the corresponding bit in the IRNCSCR register. */ -+#define SYS_GPE_IRNCSEN_LAN0ISR 0x00000001 -+/* Disable -+#define SYS_GPE_IRNCSEN_LAN0ISR_DIS 0x00000000 */ -+/** Enable */ -+#define SYS_GPE_IRNCSEN_LAN0ISR_EN 0x00000001 -+ -+/*! @} */ /* SYS_GPE_REGISTER */ -+ -+#endif /* _sys_gpe_reg_h */ -diff --git a/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h -new file mode 100644 -index 0000000..8fa3ea0 ---- /dev/null -+++ b/arch/mips/include/asm/mach-lantiq/falcon/sysctrl.h -@@ -0,0 +1,60 @@ -+/* -+ * This program is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This program is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public License -+ * along with this program; if not, write to the Free Software -+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, -+ * MA 02111-1307 USA -+ * -+ * Copyright (C) 2010 Thomas Langer, Lantiq Deutschland -+ */ -+ -+#ifndef __FALCON_SYSCTRL_H -+#define __FALCON_SYSCTRL_H -+ -+#include <falcon/lantiq_soc.h> -+ -+static inline void sys1_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYS1, mask); } -+static inline void sys1_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYS1, mask); } -+ -+static inline void sys_eth_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYSETH, mask); } -+static inline void sys_eth_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYSETH, mask); } -+ -+static inline void sys_gpe_hw_activate(u32 mask) -+{ ltq_sysctl_activate(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_deactivate(u32 mask) -+{ ltq_sysctl_deactivate(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_clk_enable(u32 mask) -+{ ltq_sysctl_clken(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_clk_disable(u32 mask) -+{ ltq_sysctl_clkdis(SYSCTL_SYSGPE, mask); } -+static inline void sys_gpe_hw_activate_or_reboot(u32 mask) -+{ ltq_sysctl_reboot(SYSCTL_SYSGPE, mask); } -+static inline int sys_gpe_hw_is_activated(u32 mask) -+{ return 1; } -+ -+#endif /* __FALCON_SYSCTRL_H */ -diff --git a/include/linux/atm.h b/include/linux/atm.h -index 2c63d27..47396c4 100644 ---- a/include/linux/atm.h -+++ b/include/linux/atm.h -@@ -130,6 +130,11 @@ - #define ATM_ABR 4 - #define ATM_ANYCLASS 5 /* compatible with everything */ - -+#define ATM_VBR_NRT ATM_VBR -+#define ATM_VBR_RT 6 -+#define ATM_UBR_PLUS 7 -+#define ATM_GFR 8 -+ - #define ATM_MAX_PCR -1 /* maximum available PCR */ - - struct atm_trafprm { -diff --git a/include/linux/pci.h b/include/linux/pci.h -index a16b1df..135fd2d 100644 ---- a/include/linux/pci.h -+++ b/include/linux/pci.h -@@ -964,6 +964,7 @@ int pci_cfg_space_size_ext(struct pci_dev *dev); - int pci_cfg_space_size(struct pci_dev *dev); - unsigned char pci_bus_max_busnr(struct pci_bus *bus); - void pci_setup_bridge(struct pci_bus *bus); -+int pci_find_preexist_bus_nr(const struct pci_bus *from); - - #define PCI_VGA_STATE_CHANGE_BRIDGE (1 << 0) - #define PCI_VGA_STATE_CHANGE_DECODES (1 << 1) -diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h -index 31d77af..146694b 100644 ---- a/include/linux/pci_ids.h -+++ b/include/linux/pci_ids.h -@@ -2904,3 +2904,11 @@ - #define PCI_DEVICE_ID_XEN_PLATFORM 0x0001 - - #define PCI_VENDOR_ID_OCZ 0x1b85 -+ -+#define PCI_VENDOR_ID_INFINEON 0x15D1 -+#define PCI_DEVICE_ID_INFINEON_DANUBE 0x000F -+#define PCI_DEVICE_ID_INFINEON_PCIE 0x0011 -+ -+#define PCI_VENDOR_ID_LANTIQ 0x1BEF -+#define PCI_DEVICE_ID_LANTIQ_PCIE 0x0011 -+ -diff --git a/include/net/ifx_ppa_api.h b/include/net/ifx_ppa_api.h -new file mode 100644 -index 0000000..ee22832 ---- /dev/null -+++ b/include/net/ifx_ppa_api.h -@@ -0,0 +1,2606 @@ -+#ifndef __IFX_PPA_API_H__20081031_1913__ -+#define __IFX_PPA_API_H__20081031_1913__ -+ -+ -+/******************************************************************************* -+** -+** FILE NAME : ifx_ppa_api.h -+** PROJECT : PPA -+** MODULES : PPA API (Routing/Bridging Acceleration APIs) -+** -+** DATE : 31 OCT 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA Protocol Stack Hook API Header File -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 31 OCT 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+/*! \file ifx_ppa_api.h -+ \brief This file contains es. -+ provide PPA API. -+*/ -+ -+/** \defgroup PPA_API PPA Kernel Hook and Userspace Function API -+ \brief PPA is a loadable network module. Hence, it exports its API though function pointer hooks. Callers need to check that hooks are non-NULL before invoking them. The hooks are initialized when the PPA is initialized. Certain API which are control / configuration related are also exposed to user space applications through the ioctl API. The PPA Kernel and Userspace API are discussed in the following sections: -+*/ -+/* @{*/ -+/** \defgroup PPA_IOCTL PPA Userspace API -+ \brief The subset of PPA API which is exposed to userspace for control and configuration of the PPA is invoked through -+ an ioctls()/system call interface as described in this section. -+ The API is defined in the following two source files: -+ - ifx_ppa_api.h: Header file for PPA API -+ - ifx_ppa_api.c: C Implementation file for PPA API -+*/ -+ -+/** \defgroup PPA_HOOK_API PPA Hook API -+ \brief PPA is a loadable network module. Hence, it exports its API though function pointer hooks. Callers need to check that hooks are non-NULL before invoking them. The hooks are initialized when the PPA is initialized. -+ - ifx_ppa_hook.h: Header file for PPA API -+ - ifx_ppa_hook.c: C Implementation file for PPA API -+*/ -+ -+/** \defgroup PPA_PWM_API PPA Power Management API -+ \brief PPA Power Management API provide PPA Power Management and IOCTL API -+ The API is defined in the following two source files -+ - ifx_ppa_api_pwm.h: Header file for PPA API -+ - ifx_ppa_api_pwm.c: C Implementation file for PPA Power management API -+ - ifx_ppa_api_pwm_logic.c: C impelementation file for Powr management Logic and interface with PPE driver -+*/ -+ /** \defgroup PPA_API_DIRECTPATH PPA Direct Path API -+ \brief This section describes the PPA DirectPath API that allows a driver on a CPU to bypass the protocol stack and send and receive packets directly from the PPA acceleration function. For a 2-CPU system, this API is used to communicate with devices whose drivers are running on the 2nd CPU (or Core 1) - usually Core 1 is not running any protocol stack, and all protocol stack intelligence is on Core 0. This API is not yet implemented for PPE D4 or A4 firmware. It is provided as advance information on the DirectPath interfaces.The PPA DirectPath aims to accelerate packet processing by reducing CPU load when the protocol stack processes the packet. It allows a CPU-bound driver to directly talk to the PPA and to the PPE engine bypassing the stack path and providing a short-cut. -+ - ifx_ppa_api_directpath.h: Header file for PPA API -+ - ifx_ppa_api_directpath.c: C Implementation file for PPA API -+*/ -+ -+/** \defgroup PPA_ADAPTATION_LAYER PPA Stack Adaptation API -+ \brief PPA module aims for OS and Protocol stack independence, and the -+ core PPA logic does not access any OS or Protocol stack implementation -+ specific structures directly. The PPA Protocol Stack Adaptation layer -+ provides API that allows for straight-forward and structured OS / protocol -+ stack porting of the PPA just by porting the Adaptation Layer (AL) API. -+ The AL API is defined in the following two source files -+ - ifx_ppa_stack_al.h: Header file for AL layer -+ - ifx_ppa_stack_al.c: C Implementation file for AL API -+*/ -+/* @}*/ -+ -+ -+ -+#include <net/ifx_ppa_api_common.h> -+#include <net/ifx_ppa_stack_al.h> -+#ifdef __KERNEL__ -+ #include <net/ifx_ppa_api_directpath.h> -+#endif -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+/*! -+ \brief PPA_MAX_IFS_NUM -+*/ -+#define PPA_MAX_IFS_NUM 10 /*!< Maximum interface number supported */ -+ -+ -+ -+/*! -+ \brief PPA_MAX_MC_IFS_NUM -+*/ -+#define PPA_MAX_MC_IFS_NUM 8 /*!< Maximum number of Multicast supporting interfaces */ -+ -+/*! -+ \brief PPA_MAX_VLAN_FILTER -+*/ -+#define PPA_MAX_VLAN_FILTER 32 /*!< Maximum number of VLAN fitler */ -+ -+ -+/*! -+ \brief PPA_IOC_MAGIC -+*/ -+#define PPA_IOC_MAGIC ((uint32_t)'p') /*!< Magic number to differentiate PPA ioctl commands */ -+ -+/*! -+ \brief IFX_SUCCESS -+*/ -+#define IFX_SUCCESS 0 /*!< Operation was successful. */ -+ -+/*! -+ \brief IFX_FAILURE -+*/ -+#define IFX_FAILURE -1 /*!< Operation failed */ -+ -+/*! -+ \brief IFX_EPERM -+*/ -+#define IFX_EPERM -2 /*!< not permitted */ -+ -+/*! -+ \brief IFX_EIO -+*/ -+#define IFX_EIO -5 /*!< I/O/Hardware/Firmware error */ -+ -+/*! -+ \brief IFX_EAGAIN -+*/ -+#define IFX_EAGAIN -11 /*!< try again later */ -+ -+/*! -+ \brief IFX_ENOMEM -+*/ -+#define IFX_ENOMEM -12 /*!< out of memory */ -+ -+/*! -+ \brief IFX_EACCESS -+*/ -+#define IFX_EACCESS IFX_EPERM -+ -+/*! -+ \brief IFX_EFAULT -+*/ -+#define IFX_EFAULT -14 /*!< bad address */ -+ -+/*! -+ \brief IFX_EBUSY -+*/ -+#define IFX_EBUSY -16 /*!< busy */ -+ -+/*! -+ \brief IFX_EINVAL -+*/ -+#define IFX_EINVAL -22 /*!< invalid argument */ -+ -+/*! -+ \brief IFX_ENOTAVAIL -+*/ -+#define IFX_ENOTAVAIL -97 -+ -+/*! -+ \brief IFX_ENOTPOSSIBLE -+*/ -+#define IFX_ENOTPOSSIBLE -98 -+ -+/*! -+ \brief IFX_ENOTIMPL -+*/ -+#define IFX_ENOTIMPL -99 /*!< not implemented */ -+ -+/*! -+ \brief IFX_ENABLED -+*/ -+#define IFX_ENABLED 1 /*!< Status enabled / Device was enabled */ -+ -+/*! -+ \brief IFX_DISABLED -+*/ -+#define IFX_DISABLED 0 /*!< Status disabled / Device was disabled. */ -+ -+/* -+ * flags -+ */ -+ -+/*! -+ \brief PPA_F_BEFORE_NAT_TRANSFORM -+ \note PPA Routing Session add hook is called before NAT transform has taken place. \n -+ In Linux OS, this NSFORM corresponds to the netfilter PREROUTING hook -+*/ -+#define PPA_F_BEFORE_NAT_TRANSFORM 0x00000001 -+ -+/*! -+ \brief PPA_F_ACCEL_MODE -+ \note notify PPA to enable or disable acceleration for one routing session. It is only for Hook/ioctl, not for PPE FW usage -+*/ -+#define PPA_F_ACCEL_MODE 0x00000002 -+ -+/*! -+ \brief PPA_F_SESSION_ORG_DIR -+ \note Packet in original direction of session i.e. the direction in which the session was established -+*/ -+#define PPA_F_SESSION_ORG_DIR 0x00000010 -+ -+/*! -+ \brief PPA_F_SESSION_REPLY_DIR -+ \note Packet in reply direction of session i.e. opposite to the direction in which session was initiated. -+*/ -+#define PPA_F_SESSION_REPLY_DIR 0x00000020 -+ -+/*! -+ \brief PPA_F_SESSION_BIDIRECTIONAL -+ \note For PPA Session add, add a bidirectional session, else unidirection session is assumed. -+*/ -+#define PPA_F_SESSION_BIDIRECTIONAL (PPA_F_SESSION_ORG_DIR | PPA_F_SESSION_REPLY_DIR) -+ -+/*! -+ \brief PPA_F_BRIDGED_SESSION -+ \note Denotes that the PPA session is bridged -+*/ -+#define PPA_F_BRIDGED_SESSION 0x00000100 -+ -+/*! -+ \brief PPA_F_SESSION_NEW_DSCP -+ \note Denotes that the PPA session has DSCP remarking enabled -+*/ -+#define PPA_F_SESSION_NEW_DSCP 0x00001000 -+ -+/*! -+ \brief PPA_F_SESSION_VLAN -+ \note Denotes that the PPA session has VLAN tagging enabled. -+*/ -+#define PPA_F_SESSION_VLAN 0x00002000 -+ -+/*! -+ \brief PPA_F_MTU -+ \note Denotes that the PPA session has a MTU limit specified -+*/ -+#define PPA_F_MTU 0x00004000 -+ -+/*! -+ \brief PPA_F_SESSION_OUT_VLAN -+ \note Denotes that the PPA session has Outer VLAN tagging enable -+*/ -+#define PPA_F_SESSION_OUT_VLAN 0x00008000 -+ -+/*! -+ \brief PPA_F_BRIDGE_LOCAL -+ \note Denotes that the PPA bridge session is for a flow terminated at the CPE (i.e. not bridged out). Such an entry will not be accelerated -+*/ -+#define PPA_F_BRIDGE_LOCAL 0x00010000 -+ -+/*! -+ \brief PPA_F_LAN_IF -+ \note Indicates that the interface is a LAN interface -+*/ -+#define PPA_F_LAN_IF 0x01000000 -+ -+/*! -+ \brief PPA_F_STATIC_ENTRY -+ \note Indicates that it is a static entry -+*/ -+#define PPA_F_STATIC_ENTRY 0x20000000 -+ -+/*! -+ \brief PPA_F_DROP_PACKET -+ \note Denotes that the PPA session has a drop action specified. In other words, this acts as a fast path \n -+ packet filter drop action -+*/ -+#define PPA_F_DROP_PACKET 0x40000000 -+ -+/*! -+ \brief PPA_F_BRIDGE_ACCEL_MODE -+ \note Flag denoting that the PPA should accelerate bridging sessions. Reserved currently -+*/ -+#define PPA_F_BRIDGE_ACCEL_MODE 0x80000000 -+ -+/* -+ * interface flags -+ */ -+ -+/*! -+ \brief IFX_PPA_SESSION_NOT_ADDED -+*/ -+#define IFX_PPA_SESSION_NOT_ADDED -1 /*!< PPA Session Add failed. This can happen either because the Session is not yet ready for addition or \n -+ that PPA cannot accelerate the session because the packet is looped back */ -+ -+/*! -+ \brief IFX_PPA_SESSION_ADDED -+*/ -+#define IFX_PPA_SESSION_ADDED 0 /*!< Indicates PPA was able to successfully add the session */ -+ -+/*! -+ \brief IFX_PPA_SESSION_EXISTS -+*/ -+#define IFX_PPA_SESSION_EXISTS 1 /*!< Indicates PPA already has the session added. This is also a success indication */ -+ -+ -+/* -+ * ifx_ppa_inactivity_status return value -+ */ -+/*! -+ \brief IFX_PPA_HIT -+ \note PPA Session is active i.e. was hit with packets within the configured inactivity time inter -+*/ -+ #define IFX_PPA_HIT 0 -+ -+/*! -+ \brief IFX_PPA_TIMEOUT -+ \note PPA Session is inactive and hence has timed out -+*/ -+#define IFX_PPA_TIMEOUT 1 -+ -+/*! -+ \brief PPA_F_VLAN_FILTER_IFNAME -+*/ -+#define PPA_F_VLAN_FILTER_IFNAME 0 /*!< Port based VLAN */ -+ -+/*! -+ \brief PPA_F_VLAN_FILTER_IP_SRC -+*/ -+#define PPA_F_VLAN_FILTER_IP_SRC 1 /*!< SRC IP based VLAN */ -+ -+/*! -+ \brief PPA_F_VLAN_FILTER_ETH_PROTO -+*/ -+#define PPA_F_VLAN_FILTER_ETH_PROTO 2 /*!< Ethernet Type based VLAN */ -+ -+/*! -+ \brief PPA_F_VLAN_FILTER_VLAN_TAG -+*/ -+#define PPA_F_VLAN_FILTER_VLAN_TAG 3 /*!< Vlan tag based VLAN */ -+ -+/*! -+ \brief PPA_INVALID_QID -+*/ -+#define PPA_INVALID_QID 0xFFFF /*!< Invalid VLAN ID. Note, it is used only in IOCTL */ -+ -+/*! -+ \brief PPA_VLAN_TAG_MASK -+*/ -+#define PPA_VLAN_TAG_MASK 0xFFFF1FFF /*!< VLAN MASK to remove VLAN priority*/ -+ -+/*! -+ \brief MAX_HOOK_NAME_LEN -+*/ -+#define MAX_HOOK_NAME_LEN 71 /*!< maximum hook name length */ -+ -+ -+/*! -+ \brief PPA_PORT_MODE_ETH -+*/ -+#define PPA_PORT_MODE_ETH 1 /*!< Ethernet Port */ -+/*! -+ \brief PPA_PORT_MODE_DSL -+*/ -+#define PPA_PORT_MODE_DSL 2 /*!< DSL Port */ -+ -+/*! -+ \brief PPA_PORT_MODE_EXT -+*/ -+#define PPA_PORT_MODE_EXT 3 /*!< Extension Port, like USB/WLAN */ -+ -+/*! -+ \brief PPA_PORT_MODE_CPU -+*/ -+#define PPA_PORT_MODE_CPU 4 /*!< CPU */ -+ -+ -+ -+#ifdef NO_DOXY -+#define VLAN_ID_SPLIT(full_id, pri, cfi, vid) pri=( (full_id) >> 13 ) & 7; cfi=( (full_id) >>12) & 1; vid= (full_id) & 0xFFF -+#define VLAN_ID_CONBINE(full_id, pri, cfi, vid) full_id =( ( (uint16_t)(pri) & 7) << 13 ) | ( ( (uint16_t)( cfi) & 1) << 12 ) | ((uint16_t) (vid) & 0xFFF ) -+ -+ -+/* -+ * internal flag -+ */ -+ -+#define SESSION_INTERNAL_FLAG_BASE 0 -+#define SESSION_IS_REPLY 0x00000001 -+#define SESSION_BRIDGING_VCI_CHECK 0x00000002 -+#define SESSION_IS_TCP 0x00000004 -+#define SESSION_BYTE_STAMPING 0x00000008 //for PPA session management purse -+#define SESSION_ADDED_IN_HW 0x00000010 -+#define SESSION_NON_ACCE_MASK ~SESSION_ADDED_IN_HW //for ioctl only -+#define SESSION_CAN_NOT_ACCEL 0x00000020 // later may need to change the naming, so far it also used for sesson management -+#define SESSION_STATIC 0x00000040 -+#define SESSION_DROP 0x00000080 -+#define SESSION_VALID_NAT_IP 0x00000100 -+#define SESSION_VALID_NAT_PORT 0x00000200 -+#define SESSION_VALID_NAT_SNAT 0x00000400 // src IP is replaced, otherwise dest IP is replaced -+#define SESSION_NOT_ACCELABLE 0x00000800 //Session cannot be accelerated at all -+#define SESSION_VALID_VLAN_INS 0x00001000 -+#define SESSION_VALID_VLAN_RM 0x00002000 -+#define SESSION_VALID_OUT_VLAN_INS 0x00004000 -+#define SESSION_VALID_OUT_VLAN_RM 0x00008000 -+#define SESSION_VALID_PPPOE 0x00010000 -+#define SESSION_VALID_NEW_SRC_MAC 0x00020000 -+#define SESSION_VALID_SRC_MAC SESSION_VALID_NEW_SRC_MAC -+#define SESSION_VALID_MTU 0x00040000 -+#define SESSION_VALID_NEW_DSCP 0x00080000 -+#define SESSION_VALID_DSLWAN_QID 0x00100000 -+#define SESSION_TX_ITF_IPOA 0x00200000 -+#define SESSION_TX_ITF_PPPOA 0x00400000 -+#define SESSION_TX_ITF_IPOA_PPPOA_MASK (SESSION_TX_ITF_IPOA | SESSION_TX_ITF_PPPOA) -+#define SESSION_SRC_MAC_DROP_EN 0x01000000 -+#define SESSION_TUNNEL_6RD 0x02000000 -+#define SESSION_TUNNEL_DSLITE 0x04000000 -+#define SESSION_LAN_ENTRY 0x10000000 -+#define SESSION_WAN_ENTRY 0x20000000 -+#define SESSION_IS_IPV6 0x40000000 -+#endif -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+ -+/* -------------------------------------------------------------------------- */ -+/* Structure and Enumeration Type Defintions */ -+/* -------------------------------------------------------------------------- */ -+ -+/** \addtogroup PPA_HOOK_API */ -+/*@{*/ -+ -+/*! -+ \brief This is the data structure for PPA Interface Info specification. -+*/ -+typedef struct { -+ PPA_IFNAME *ifname; /*!< Name of the stack interface */ -+ uint32_t if_flags; /*!< Flags for Interface. Valid values are below: PPA_F_LAN_IF and PPA_F_WAN_IF */ -+ uint32_t port; /*!< physical port id for this Interface. Valid values are below: 0 ~ */ -+} PPA_IFINFO; -+ -+/*! -+ \brief This is the data structure for PPA Packet header verification checks. -+*/ -+typedef struct ppa_verify_checks { -+ uint32_t f_ip_verify :1; /*!< Enable/Disable IP verification checks. Valid values are IFX_ENABLED or IFX_DISABLED */ -+ uint32_t f_tcp_udp_verify :1; /*!< Enable/Disable TCP/UDP verification checks. Valid values are IFX_ENABLED or IFX_DISABLED */ -+ uint32_t f_tcp_udp_err_drop :1; /*!< Enable/Disable drop packet if TCP/UDP checksum is wrong. \n -+ If packet is not dropped, then it is forwarded to the control CPU. \n -+ Valid values are IFX_ENABLED or IFX_DISABLED */ -+ uint32_t f_drop_on_no_hit :1; /*!< Drop unicast packets on no hit, forward to MIPS/Control CPU otherwise (default). Valid values are IFX_ENABLED or IFX_DISABLED */ -+ uint32_t f_mc_drop_on_no_hit :1; /*!< Drop multicast on no hit, forward to MIPS/Control CPU otherwise (default). Valid values are IFX_ENABLED or IFX_DISABLED */ -+} PPA_VERIFY_CHECKS; -+ -+/*! -+ \brief This is the data structure for PPA Initialization kernel hook function -+*/ -+typedef struct { -+ PPA_VERIFY_CHECKS lan_rx_checks; /*!< LAN Ingress packet checks */ -+ PPA_VERIFY_CHECKS wan_rx_checks; /*!< WAN Ingress packet checks */ -+ uint32_t num_lanifs; /*!< Number of LAN side interfaces */ -+ PPA_IFINFO *p_lanifs; /*!< Pointer to array of LAN Interfaces. */ -+ uint32_t num_wanifs; /*!< Number of WAN side interfaces */ -+ PPA_IFINFO *p_wanifs; /*!< Pointer to array of WAN Interfaces. */ -+ uint32_t max_lan_source_entries; /*!< Maximum Number of session entries with LAN source */ -+ uint32_t max_wan_source_entries; /*!< Maximum Number of session entries with WAN source */ -+ uint32_t max_mc_entries; /*!< Maximum Number of multicast sessions */ -+ uint32_t max_bridging_entries; /*!< Maximum Number of bridging entries */ -+ uint32_t add_requires_min_hits; /*!< Minimum number of calls to ppa_add_session() before session would be added in h/w - calls from the same hook position in stack. Currently, set to 1 */ -+} PPA_INIT_INFO; -+ -+/*! -+ \brief This is the data structure for additional session related information for the PPA. It specifies on a per session basis -+ attributes like VLAN tagging, DSCP remarking etc. This structure depends on the PPE acceleration firmware -+ capabilities. New versions of PPA will only support the capabilities as in PPE A4/D4 firmware, -+ The current PPA driver (for PPE A4/D4 firmware) supports 2-level of VLANs (or stacked VLANs). The outer VLAN is -+ the one used for separating LAN and WAN traffic on a switch (for Ethernet WAN). Inner VLAN tag is application -+ specific VLAN. In case, there is no outer VLAN tag required (for LAN/WAN separation on the switch), then this -+ field is not specified. -+*/ -+typedef struct { -+ uint32_t new_dscp :6; /*!< New DSCP code point value for the session.Valid values are 0-63. */ -+ uint32_t dscp_remark :1; /*!< DSCP remarking needs to be carried out for the session.Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint32_t vlan_insert :1; /*!< If inner VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ -+ uint32_t vlan_remove :1; /*!< If inner VLAN untagging should be performed on the received frame. Untagging, if enabled, is \n -+ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_vlan_insert :1; /*!< If outer VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_vlan_remove :1; /*!< If outer VLAN untagging should be performed on the received frame. Untagging, if enabled, is \n -+ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint16_t dslwan_qid_remark :1; /*!< if dslwan qid should be set. Valid values are: IFX_ENABLED and IFX_DISABLED */ -+ uint32_t reserved1 :4; /*!< reserved */ -+ uint32_t vlan_prio :3; /*!< 802.1p VLAN priority configuration. Valid values are 0-7. */ -+ uint32_t vlan_cfi :1; /*!< lways set to 1 for Ethernet frames */ -+ uint32_t vlan_id :12;/*!< VLAN Id to be used to tag the frame. Valid values are 0-4095. */ -+ uint16_t mtu; /*!< MTU of frames classified to this session */ -+ uint16_t dslwan_qid; /*!< dslwan_qid. Valid values are 0 ~ 16 */ -+ uint32_t session_flags; /*!< Session flags used to identify which fields in the PPA_SESSION_EXTRA structure are valid in \n -+ a call to the PPA Session Modify API. \n -+ Valid values are one or more of: \n -+ PPA_F_SESSION_NEW_DSCP \n -+ PPA_F_SESSION_VLAN \n -+ PPA_F_SESSION_OUT_VLAN \n -+ PPA_F_MTU \n -+ */ -+ uint32_t out_vlan_tag; /*!< VLAN tag value including VLAN Id */ -+ -+ -+ -+ uint16_t accel_enable:1; /*!< to enable/disable acceleartion for one specified routing session. It will be used only in PPA API level, not HAL and PPE FW level */ -+} PPA_SESSION_EXTRA; -+ -+/*! -+ \brief This is the data structure which specifies an interface and its TTL value as applicable for multicast routing. -+*/ -+typedef struct { -+ PPA_IFNAME *ifname; /*!< Pointer to interface name. */ -+ uint8_t ttl; /*!< Time to Live (TTL) value of interface which is used for multicast routing to decide if a packet can be routed onto that interface -+ Note, it is not used at present. -+ */ -+} IF_TTL_ENTRY; -+ -+/*! -+ \brief This is the data structure for basic IPV4/IPV6 address -+*/ -+typedef union { -+ uint32_t ip; /*!< ipv4 address */ -+ uint32_t ip6[4]; /*!< ipv6 address */ -+}IP_ADDR; -+ -+/*! -+ \brief This is the data structure for complex IPV4/IPV6 address -+*/ -+typedef struct { -+ uint32_t f_ipv6; /*!< flag to specify the ipv4 version: 0---IPV4, 1 -- IPV6 */ -+ IP_ADDR ip; /*!< multiple ip address format support */ -+} IP_ADDR_C; -+ -+ -+/*! -+ \brief This is the data structure for PPA Multicast Group membership. It specifies the interfaces which are members of -+ the specified IP Multicast Group address. Please see the discussion on outer and inner VLAN tags in the -+ section on PPA_SESSION_EXTRA data structure. -+*/ -+typedef struct { -+ IP_ADDR_C ip_mc_group; /*!< Multicast IP address group */ -+ int8_t num_ifs; /*!< Number of Interfaces which are member of this Multicast IP group address */ -+ IF_TTL_ENTRY array_mem_ifs[PPA_MAX_MC_IFS_NUM]; /*!< Array of interface elements of maximum PPA_MAX_MC_IFS_NUM elements. -+ Actual number of entries is specified by num_ifs */ -+ uint8_t if_mask; /*!< Mask of Interfaces corresponding to num_ifs interfaces specified in array_mem_ifs. For internaly use only. */ -+ PPA_IFNAME *src_ifname; /*!< the source interface of specified multicast IP address group */ -+ uint32_t vlan_insert :1; /*!< If inner VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ -+ uint32_t vlan_remove :1; /*!< If inner VLAN untagging should be performed on the received frame. Untagging, if enabled, is -+ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_vlan_insert :1; /*!< If outer VLAN tag should be inserted into the frame at egress. Valid values are: IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_vlan_remove :1; /*!< If outer VLAN untagging should be performed on the received frame. Untagging, if enabled, is -+ carried out before any VLAN tag insert. Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint32_t dslwan_qid_remark:1; /*!< not use at present */ -+ uint32_t reserved1 :3; /*!< valid in A4/A5 */ -+ uint32_t vlan_prio :3; /*!< 802.1p VLAN priority configuration. Valid values are 0-7. */ -+ uint32_t vlan_cfi :1; /*!< Always set to 1 for Ethernet frames */ -+ uint32_t vlan_id :12; /*!< VLAN Id to be used to tag the frame. Valid values are 0-4095 */ -+ uint32_t out_vlan_tag; /*!< Outer VLAN tag value including VLAN Id. */ -+ uint32_t new_dscp_en :1; /*!< If new dscp value should be set. Valid values are:IFX_ENABLED and IFX_DISABLED */ -+ uint32_t res :15; /*!< reserved */ -+ uint32_t new_dscp :16; /*!< New DSCP code point value for the session.Valid values are 0-63. */ -+ uint16_t dslwan_qid; /*!< not use at present */ -+ -+ uint32_t bridging_flag; /*!< 0 - routing mode/igmp proxy, 1 - bridge mode/igmp snooping. */ -+ uint8_t mac[PPA_ETH_ALEN]; /*!< reserved for future */ -+ uint8_t SSM_flag; /*!< Set the flag if source specific forwarding is required default 0*/ -+ PPA_IPADDR source_ip; /*!< source ip address */ -+} PPA_MC_GROUP; -+ -+/*! -+ \brief This data structure is an abstraction for unicast and multicast routing sessions. -+ Pointer to any kind of PPA session -+*/ -+typedef void PPA_U_SESSION; -+ -+/*! -+ \brief This is the data structure for standard packet and byte statistics for an interface. -+*/ -+typedef struct { -+ uint32_t tx_pkts; /*!< Number of transmitted packets through the interface */ -+ uint32_t rx_pkts; /*!< Number of received packets through the interface */ -+ uint32_t tx_discard_pkts; /*!< Number of packets discarded while transmitting through the interface. */ -+ uint32_t tx_error_pkts; /*!< Number of transmit errors through the interface. */ -+ uint32_t rx_discard_pkts; /*!< Number of received packets through the interface that were discarded */ -+ uint32_t rx_error_pkts; /*!< Number of received errors through the interface. */ -+ uint32_t tx_bytes; /*!< Number of transmit bytes through the interface */ -+ uint32_t rx_bytes; /*!< Number of received bytes through the interface */ -+} PPA_IF_STATS; -+ -+/*! -+ \brief This is the data structure for PPA accelerated statistics for an interface. Depending on the platform and -+ acceleration capabilities, some of the statistics may not be available. -+*/ -+typedef struct { -+ uint32_t fast_routed_tcp_pkts; /*!< Fastpath routed TCP unicast packets Tx */ -+ uint32_t fast_routed_udp_pkts; /*!< Fastpath routed UDP unicast packets Tx */ -+ uint32_t fast_routed_udp_mcast_pkts; /*!< Fastpath routed UDP multicast packets Tx */ -+ uint32_t fast_drop_pkts; /*!< Fastpath ingress pkts dropped */ -+ uint32_t fast_drop_bytes; /*!< Fastpath ingress bytes dropped */ -+ uint32_t fast_ingress_cpu_pkts; /*!< Fastpath ingress CPU pkts */ -+ uint32_t fast_ingress_cpu_bytes; /*!< Fastpath ingress CPU bytes */ -+ uint32_t rx_pkt_errors; /*!< Fastpath packet error */ -+ uint32_t fast_bridged_ucast_pkts; /*!< Fastpath bridged unicast pkts */ -+ uint32_t fast_bridged_mcast_pkts; /*!< Fastpath bridged multicast pkts */ -+ uint32_t fast_bridged_bcast_pkts; /*!< Fastpath bridged broadcast pkts */ -+ uint32_t fast_bridged_bytes; /*!< Fastpath bridged bytes */ -+} PPA_ACCEL_STATS; -+ -+/*! -+ \brief This is the data structure for VLAN tag control on a per interface basis. It is currently supported only for bridging -+ paths. For PPE A4 firmware, 2 levels of VLAN is configurable, while for older PPE D4 firmware, only inner VLAN -+ tag is configurable. Please see discussion in section PPA_SESSION_EXTRA. Briefly, couter VLAN tag -+ configuration is used for LAN and WAN isolation on the same external switch, while the other set of VLAN tag -+ configuration is driven from application needs (i.e. not stripped off when the packet hits the wire). -+*/ -+typedef struct { -+ uint32_t unmodified :1; /*!< Indicates if there is no VLAN tag modification. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t insertion :1; /*!< Indicates if there is a VLAN tag inserted. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t remove :1; /*!< Indicates if there is a VLAN tag removed. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t replace :1; /*!< Indicates if there is a VLAN tag replaced. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_unmodified :1; /*!< Indicates if there is no outer VLAN tag modification. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_insertion :1; /*!< Indicates if there is a outer VLAN tag inserted. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_remove :1; /*!< Indicates if there is a outer VLAN tag removed. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_replace :1; /*!< Indicates if there is a outerVLAN tag replaced. Valid values are IFX_ENABLED and IFX_DISABLED */ -+} PPA_VLAN_TAG_CTRL; -+ -+/*! -+ \brief This is the data structure for VLAN configuration control on a per interface basis. It is currently supported only for -+ bridging paths. -+*/ -+typedef struct { -+ uint32_t src_ip_based_vlan :1; /*!< Indicates if Source IP address filter based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t eth_type_based_vlan :1; /*!< Indicates if Ethernet header type based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t vlanid_based_vlan :1; /*!< Indicates if VLAN re-tagging is enabled based on existing VLAN Id of received frame. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t port_based_vlan :1; /*!< Indicates if port based VLAN tagging is enabled for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t vlan_aware :1; /*!< Indicates if bridge is VLAN aware and enforces VLAN based forwarding for this interface. Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t out_vlan_aware :1; /*!< Indicates if bridge is outer VLAN aware and enforces VLAN based forwarding for this -+ interface. If this field is not enabled, then outer VLAN processing is don't care. -+ interface. If this field is not enabled, then outer VLAN processing is don't care. -+ Valid values are IFX_ENABLED and IFX_DISABLED */ -+} PPA_VLAN_CFG; -+ -+/*! -+ \brief Union of PPA VLAN filter criteria. -+*/ -+typedef union -+{ -+ PPA_IFNAME *ifname; /*!< Pointer to interface name on which VLAN filter match is to be performed. */ -+ IPADDR ip_src; /*!< IP source address of ingress frame for VLAN filter matching. */ -+ uint32_t eth_protocol; /*!< Ethernet protocol as a match filter for VLAN filter matching */ -+ uint32_t ingress_vlan_tag; /*!< Ingress frame VLAN tag as match criteria for VLAN filter matching */ -+} match_criteria_vlan; -+ -+/*! -+ \brief This data structure specifies the filter or match criteria for applying VLAN transforms based on rules. It is currently supported only for bridging paths. -+*/ -+typedef struct { -+ match_criteria_vlan match_field; /*!< Union of VLAN filter criteria */ -+ uint32_t match_flags; /*!< Indicates which VLAN filter criteria is specified in this VLAN match entry. -+ Valid values are one of the following: \n -+ PPA_F_VLAN_FILTER_IFNAME \n -+ PPA_F_VLAN_FILTER_IP_SRC \n -+ PPA_F_VLAN_FILTER_ETH_PROTO \n -+ PPA_F_VLAN_FILTER_VLAN_TAG \n -+ */ -+} PPA_VLAN_MATCH_FIELD; -+ -+/*! -+ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently -+supported only for bridging paths. -+*/ -+typedef struct { -+ uint16_t vlan_vci; /*!< VLAN Information including VLAN Id, 802.1p and CFI bits. */ -+ uint16_t qid; /*!< queue index */ -+ uint32_t out_vlan_id; /*!< out vlan id */ -+ uint32_t inner_vlan_tag_ctrl;/*!< none(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ -+ uint32_t out_vlan_tag_ctrl; /*!< none(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ -+ uint16_t num_ifs; /*!< Number of interfaces in the array of PPA_IFINFO structures. */ -+ PPA_IFINFO *vlan_if_membership; /*!< Pointer to array of interface info structures for each interface which is a member of this VLAN group. The number of entries is given by num_ifs. */ -+} PPA_VLAN_INFO; -+ -+/*! -+ \brief This is the data structure for PPA VLAN filter configuration. It is currently supported only for bridging paths -+*/ -+typedef struct { -+ PPA_VLAN_MATCH_FIELD match_field; /*!< VLAN Match field information */ -+ PPA_VLAN_INFO vlan_info; /*!< VLAN Group and Membership Info */ -+} PPA_VLAN_FILTER_CONFIG; -+ -+/*! -+ \brief This is the data structure for cout information, like lan interface count, LAN acceleration count and so on -+*/ -+typedef struct { -+ uint32_t count; /*!< the number */ -+ uint32_t flag; /*!< the flag */ -+} PPA_CMD_COUNT_INFO; -+ -+/*! -+ \brief This is the data structure for get some structure size -+*/ -+typedef struct { -+ uint32_t rout_session_size; /*!< the structure size of one routing session */ -+ uint32_t mc_session_size; /*!< the structure size of one multicast session */ -+ uint32_t br_session_size; /*!< the structure size of one bridge session */ -+ uint32_t netif_size; /*!< the structure size of one network interface information*/ -+} PPA_CMD_SIZE_INFO; -+/*@}*/ /* PPA_HOOK_API */ -+ -+/* -+ * ioctl command structures -+ */ -+ -+/** \addtogroup PPA_IOCTL */ -+/*@{*/ -+ -+/*! -+ \brief This is the data structure for PPA Interface information used from the userspacef -+*/ -+typedef struct { -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< Name of the stack interface ( provide storage buffer ) */ -+ uint32_t if_flags; /*!< Flags for Interface. Valid values are below: PPA_F_LAN_IF and PPA_F_WAN_IF */ -+} PPA_CMD_IFINFO; -+ -+/*! -+ \brief This is the data structure for PPA Init used from the userspace -+*/ -+typedef struct { -+ PPA_VERIFY_CHECKS lan_rx_checks; /*!< LAN Ingress checks */ -+ PPA_VERIFY_CHECKS wan_rx_checks; /*!< WAN Ingress checks */ -+ uint32_t num_lanifs; /*!< Number of LAN side interfaces */ -+ PPA_CMD_IFINFO p_lanifs[PPA_MAX_IFS_NUM]; /*!< Array of LAN Interface Info structures (provides storage buffer). */ -+ uint32_t num_wanifs; /*!< Number of WAN side interfaces */ -+ PPA_CMD_IFINFO p_wanifs[PPA_MAX_IFS_NUM]; /*!< Array of WAN Interface Info structures (provides storage buffer). */ -+ uint32_t max_lan_source_entries; /*!< Number of session entries with LAN source */ -+ uint32_t max_wan_source_entries; /*!< Number of session entries with WAN source */ -+ uint32_t max_mc_entries; /*!< Number of multicast sessions */ -+ uint32_t max_bridging_entries; /*!< Number of bridging entries */ -+ uint32_t add_requires_min_hits; /*!< Minimum number of calls to ppa_add before session would be added in h/w */ -+ uint32_t mtu; /*!< specify PPA network internface's MTU size, default is 1500 */ -+ uint32_t flags; /*!< Flags for PPA Initialization. Currently this field is reserved. */ -+ -+} PPA_CMD_INIT_INFO; -+ -+/*! -+ \brief This is the data structure for PPA Acceleration Enable / Disable configuration -+*/ -+typedef struct { -+ uint32_t lan_rx_ppa_enable; /*!< lan Interface specific flags. Current Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t wan_rx_ppa_enable; /*!< wan Interface specific flags. Current Valid values are IFX_ENABLED and IFX_DISABLED */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_ENABLE_INFO; -+ -+/*! -+ \brief This is the data structure for MAC table entry used in PPA ioctl interface -+*/ -+typedef struct { -+ IP_ADDR_C mcast_addr; /*!< MC address of the entry */ -+ IP_ADDR source_ip; /*!< source ip */ -+ uint8_t SSM_flag; /*!< ssm flag */ -+ PPA_SESSION_EXTRA mc_extra; /*!< Pointer to PPA Multicast session parameters like VLAN configuration, DSCP remarking */ -+ uint32_t flags; /*!< Flags for the PPA Multicast entry info structure. Reserved currently. */ -+ -+} PPA_CMD_MC_ENTRY; -+ -+/*! -+ \brief This is the data structure for learned MAC address used in PPA ioctl interface -+*/ -+typedef struct { -+ uint8_t mac_addr[PPA_ETH_ALEN]; /*!< MAC address learned */ -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< The interface which learned the MAC address */ -+ uint32_t flags; /*!< for future */ -+} PPA_CMD_MAC_ENTRY; -+ -+/*! -+ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently -+ supported only for bridging paths. -+*/ -+typedef struct -+{ -+ PPA_IFNAME if_name[PPA_IF_NAME_SIZE]; /*!< Pointer to interface name for which VLAN related configuration is specified. */ -+ PPA_VLAN_TAG_CTRL vlan_tag_ctrl; /*!< VLAN Tag Control structure for the interface */ -+ PPA_VLAN_CFG vlan_cfg; /*!< VLAN Configuration control structure for the interface */ -+ uint32_t flags; /*!< Flags field. Reserved currently and omitted in implementation. */ -+} PPA_CMD_BR_IF_VLAN_CONFIG; -+ -+ -+/*! -+ \brief Union for VLAN filter matching criteria. -+*/ -+typedef union { -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< Pointer to interface name on which VLAN filter match is to be performed. */ -+ IPADDR ip_src; /*!< IP source address of ingress frame for VLAN filter matching. */ -+ uint32_t eth_protocol; /*!< Ethernet protocol as a match filter for VLAN filter matching. */ -+ uint32_t ingress_vlan_tag; /*!< Ingress frame VLAN tag as match criteria for VLAN filter matching. */ -+} filter_criteria; -+ -+ -+/*! -+ \brief This data structure specifies the filter or match criteria for applying VLAN transforms based on rules. It is currently supported only for bridging paths. -+*/ -+typedef struct { -+ filter_criteria match_field; /*!< Union for VLAN filter criteria. */ -+ uint32_t match_flags; /*!< Indicates which VLAN filter criteria is specified in this VLAN match entry. \n -+ Valid values are one of the following: \n -+ - PPA_F_VLAN_FILTER_IFNAME \n -+ - PPA_F_VLAN_FILTER_IP_SRC \n -+ - PPA_F_VLAN_FILTER_ETH_PROTO \n -+ - PPA_F_VLAN_FILTER_VLAN_TAG -+ */ -+} PPA_CMD_VLAN_MATCH_FIELD; -+ -+/*! -+ \brief This is the data structure for PPA VLAN configuration ioctl() on a per interface basis from userspace. It is currently supported only for bridging paths. -+*/ -+typedef struct { -+ uint16_t vlan_vci; /*!< VLAN Information including VLAN Id, 802.1p and CFI bits */ -+ uint16_t qid; /*!< dest_qos */ -+ uint32_t out_vlan_id; /*!< new out vlan id */ -+ uint32_t out_vlan_tag_ctrl; /*!< unmodify(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ -+ uint32_t inner_vlan_tag_ctrl;/*!< unmodify(0)/remove(1)/insert(2)/replac(3), for vlan tag based only. */ -+ uint16_t num_ifs; /*!< Number of interfaces in the array of PPA_IFINFO structures. */ -+ PPA_CMD_IFINFO vlan_if_membership[PPA_MAX_IFS_NUM]; /*!< Pointer to array of interface info structures for each interface which is a member of this VLAN group. The number of entries is given by num_ifs. */ -+} PPA_CMD_VLAN_INFO; -+ -+/*! -+ \brief This is the data structure for basic VLAN filter setting in PPA ioctl interface -+*/ -+typedef struct { -+ PPA_CMD_VLAN_MATCH_FIELD match_field; /*!< vlan filter match field */ -+ PPA_CMD_VLAN_INFO vlan_info; /*!< vlan information */ -+} _PPA_CMD_VLAN_FILTER_CONFIG; -+ -+/*! -+ \brief This is the data structure for VLAN filter configure in PPA ioctl interface -+*/ -+typedef struct { -+ _PPA_CMD_VLAN_FILTER_CONFIG vlan_filter_cfg; /*!< vlan filter basc information */ -+ uint32_t flags; /*!< flag */ -+} PPA_CMD_VLAN_FILTER_CONFIG; -+ -+/*! -+ \brief This is the data structure for PPA VLAN configuration as passed to the PPA ioctl() API from userspace. It is -+currently supported only for bridging paths. -+*/ -+typedef struct { -+ PPA_CMD_COUNT_INFO count_info; /*!< Number of filters returned in pointer to array of filters. */ -+ PPA_CMD_VLAN_FILTER_CONFIG filters[1]; /*!< it is a dummy array. Userspace should apply storage buffer for it */ -+} PPA_CMD_VLAN_ALL_FILTER_CONFIG; -+/*! -+ \brief This is the data structure for PPA accelerated statistics for an interface. Depending on the platform and -+ acceleration capabilities, some of the statistics may not be available. -+*/ -+typedef struct { -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< interface name ( provides storage buffer) */ -+ uint8_t mac[PPA_ETH_ALEN]; /*!< MAC address of the Ethernet Interface ( provides storage buffer) */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_IF_MAC_INFO; -+ -+/*! -+ \brief This is the data structure for LAN/WAN interface setting -+*/ -+typedef struct { -+ uint32_t num_ifinfos; /*!< number of interface in the list */ -+ PPA_CMD_IFINFO ifinfo[PPA_MAX_IFS_NUM]; /*!< buffer for storing network interface list */ -+} PPA_CMD_IFINFOS; -+ -+/*! -+ \brief This is the data structure for Multicast group related ioctl -+*/ -+typedef struct { -+ uint8_t mac[PPA_ETH_ALEN]; /*!< mac address of the multicast group, reserved for future */ -+ PPA_IFNAME lan_ifname[PPA_MAX_MC_IFS_NUM][PPA_IF_NAME_SIZE]; /*!< downstream interface list buffer */ -+ PPA_IFNAME src_ifname[PPA_IF_NAME_SIZE]; /*!< source interface which receive multicast streaming packet */ -+ uint32_t num_ifs; /*!< downstream interface number */ -+ uint32_t bridging_flag; /*!< IGMP Proxy/snooping flag: 0 - routing mode/igmp proxy, 1 - bring mode/igmp snooping. */ -+ -+ uint32_t new_dscp_en; /*!< dscp editing flag: 1 -- need to edit, 0 --unmodify */ -+ PPA_CMD_MC_ENTRY mc; /*!< multicast group information */ -+} PPA_CMD_MC_GROUP_INFO; -+/*! -+ \brief This is the data structure for get all Multicast group via ioctl -+*/ -+typedef struct { -+ PPA_CMD_COUNT_INFO count_info; /*!< the multicast counter */ -+ PPA_CMD_MC_GROUP_INFO mc_group_list[1]; /*!< Note, here is a dummy array, user need to malloc memory accordingly to the session number */ -+} PPA_CMD_MC_GROUPS_INFO; -+ -+/*! -+ \brief This is the data structure contains PPA session information. -+*/ -+typedef struct { -+ uint16_t ip_proto; /*!< IP portocol TCP,UDP. */ -+ uint16_t ip_tos; /*!< IP ToS value */ -+ PPA_IPADDR src_ip; /*!< source IP address */ -+ uint16_t src_port; /*!< source port */ -+ PPA_IPADDR dst_ip; /*!< destination IP address */ -+ uint16_t dst_port; /*!< destination port */ -+ PPA_IPADDR nat_ip; /*!< IP address to be replaced by NAT if NAT applies */ -+ uint16_t nat_port; /*!< Port to be replaced by NAT if NAT applies */ -+ uint32_t new_dscp; /*!< If DSCP remarking required */ -+ uint16_t new_vci; /*!< new vci ( in fact, it is new inner vlan id )*/ -+ uint32_t out_vlan_tag; /*!< Out VLAN tag */ -+ uint16_t dslwan_qid; /*!< WAN qid */ -+ uint16_t dest_ifid; /*!< Destination interface */ -+ -+ uint32_t flags; /*!< Internal flag : SESSION_IS_REPLY, SESSION_IS_TCP, \n -+ SESSION_ADDED_IN_HW, SESSION_CAN_NOT_ACCEL \n -+ SESSION_VALID_NAT_IP, SESSION_VALID_NAT_PORT, \n -+ SESSION_VALID_VLAN_INS, SESSION_VALID_VLAN_RM, \n -+ SESSION_VALID_OUT_VLAN_INS, SESSION_VALID_OUT_VLAN_RM, \n -+ SESSION_VALID_PPPOE, SESSION_VALID_NEW_SRC_MAC, \n -+ SESSION_VALID_MTU, SESSION_VALID_NEW_DSCP, \n -+ SESSION_VALID_DSLWAN_QID, \n -+ SESSION_TX_ITF_IPOA, SESSION_TX_ITF_PPPOA \n -+ SESSION_LAN_ENTRY, SESSION_WAN_ENTRY, */ -+ PPA_IFNAME rx_if_name[PPA_IF_NAME_SIZE]; /*!< receive interface name. Note, in struct session_list_item, rx_if and tx_if is a pointer, so here we have to make a workaround for it. */ -+ PPA_IFNAME tx_if_name[PPA_IF_NAME_SIZE]; /*!< txansmit interface name. */ -+ uint64_t mips_bytes; /*!< bytes processed by the mips */ -+ uint64_t hw_bytes; /*!< bytes proccesed by hareware acceleration unit*/ -+ uint64_t prev_sess_bytes; /*!< last bytes proccesed by hareware acceleration unit or */ -+ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to delete a session for ioctl*/ -+ uint32_t collision_flag; /*!< 1 mean the entry is in collsion table or none-hashed, like ASE/Danubel*/ -+ uint32_t priority; /*!< skb->priority*/ -+} PPA_CMD_SESSION_ENTRY; -+ -+/*! -+ \brief This is the data structure contains PPA session extra information. -+*/ -+typedef struct { -+ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to modify a session for ioctl*/ -+ PPA_SESSION_EXTRA session_extra; /*!< PPA SESSION extra pointer. */ -+ uint32_t flags; /*!< Internal flag : PPA_F_SESSION_NEW_DSCP \n -+ PPA_F_MTU, PPA_F_SESSION_OUT_VLAN, PPA_F_ACCEL_MODE ....\n -+ */ -+ uint32_t lan_wan_flags; /*!< Internal flag : the flag to matcn LAN only, or WAN only or both \n -+ The possible value is SESSION_WAN_ENTRY, SESSION_LAN_ENTRY -+ */ -+}PPA_CMD_SESSION_EXTRA_ENTRY; -+ -+ -+typedef struct { -+ uint32_t session; /*!< PPA SESSION pointer. Note, here we just use its address to modify a session for ioctl*/ -+ int32_t timer_in_sec; /*!< PPA SESSION polling timer in seconds. */ -+ uint32_t flags; /*!< Reserved for future */ -+}PPA_CMD_SESSION_TIMER; -+ -+ -+/*! -+ \brief This is the data structure for routing session information -+*/ -+typedef struct { -+ PPA_CMD_COUNT_INFO count_info; /*!< session count */ -+ PPA_CMD_SESSION_ENTRY session_list[1]; /*!< Note, here is a dummy array, user need to malloc memory accordingly to the session number */ -+} PPA_CMD_SESSIONS_INFO; -+ -+/*! -+ \brief This is the data structure for routing detail session information -+*/ -+typedef struct { -+ uint16_t ip_proto; /*!< IP portocol TCP,UDP. */ -+ PPA_IPADDR src_ip; /*!< source IP address */ -+ uint16_t src_port; /*!< source port */ -+ PPA_IPADDR dst_ip; /*!< destination IP address */ -+ uint16_t dst_port; /*!< destination port */ -+ PPA_IPADDR nat_ip; /*!< IP address to be replaced by NAT if NAT applies */ -+ uint16_t nat_port; /*!< Port to be replaced by NAT if NAT applies */ -+ uint32_t new_dscp; /*!< If DSCP remarking required */ -+ uint16_t in_vci_vlanid; /*!< new vci ( in fact, it is new inner vlan id )*/ -+ uint32_t out_vlan_tag; /*!< Out VLAN tag */ -+ uint16_t qid; /*!< WAN qid */ -+ uint32_t flags; /*!< Internal flag : SESSION_IS_REPLY, SESSION_IS_TCP, \n -+ SESSION_ADDED_IN_HW, SESSION_CAN_NOT_ACCEL \n -+ SESSION_VALID_NAT_IP, SESSION_VALID_NAT_PORT, \n -+ SESSION_VALID_VLAN_INS, SESSION_VALID_VLAN_RM, \n -+ SESSION_VALID_OUT_VLAN_INS, SESSION_VALID_OUT_VLAN_RM, \n -+ SESSION_VALID_PPPOE, SESSION_VALID_NEW_SRC_MAC, \n -+ SESSION_VALID_MTU, SESSION_VALID_NEW_DSCP, \n -+ SESSION_VALID_DSLWAN_QID, \n -+ SESSION_TX_ITF_IPOA, SESSION_TX_ITF_PPPOA \n -+ SESSION_LAN_ENTRY, SESSION_WAN_ENTRY, */ -+ uint32_t dest_ifid; /*!< txansmit interface name. */ -+ uint8_t src_mac[PPA_ETH_ALEN]; /*!< src mac addres */ -+ uint8_t dst_mac[PPA_ETH_ALEN]; /*!< dst mac address */ -+ uint16_t pppoe_session_id; /*!< pppoe session id */ -+ -+ uint32_t mtu; /*!< mtu */ -+}PPA_CMD_SESSIONS_DETAIL_INFO; -+ -+/*! -+ \brief This is the data structure for basic ppa Versions -+*/ -+typedef struct { -+ uint32_t index; /*!< index for PP32 */ -+ uint32_t family; /*!< ppa version hardware family */ -+ uint32_t type; /*!< ppa version hardware type */ -+ uint32_t itf;/*!< ppa version itf */ -+ uint32_t mode; /*!< ppa version mode */ -+ uint32_t major; /*!< ppa version major version number */ -+ uint32_t mid; /*!< ppa version mid version number */ -+ uint32_t minor; /*!< ppa version minor version number */ -+} PPA_VERSION; -+ -+/*! -+ \brief This is the data structure for ppa wan mode information -+*/ -+typedef struct{ -+ uint32_t wan_port_map; /*!< wan port map information*/ -+ uint32_t mixed; /*!< mixed flag */ -+} PPA_WAN_INFO; -+ -+/*! -+ \brief This is the data structure for ppa supported feature list information -+*/ -+typedef struct{ -+ uint8_t ipv6_en; /*!< ipv6 enable/disable status */ -+ uint8_t qos_en; /*!< qos enable/disable status */ -+} PPA_FEATURE_INFO; -+ -+/*! -+ \brief This is the data structure for PPA subsystem Versions, like ppa subsystem, ppe fw, ppe driver and so on -+*/ -+typedef struct { -+ PPA_VERSION ppa_api_ver; /*!< PPA API verion */ -+ PPA_VERSION ppa_stack_al_ver; /*!< PPA stack verion */ -+ PPA_VERSION ppe_hal_ver; /*!< PPA HAL verion */ -+ PPA_VERSION ppe_fw_ver[2]; /*!< PPA FW verion */ -+ PPA_VERSION ppa_subsys_ver; /*!< PPA Subsystem verion */ -+ PPA_WAN_INFO ppa_wan_info; /*!< PPA WAN INFO */ -+ PPA_FEATURE_INFO ppe_fw_feature; /*!< PPE FW feature lists */ -+ PPA_FEATURE_INFO ppa_feature; /*!< PPA Level feature lists */ -+ -+} PPA_CMD_VERSION_INFO; -+ -+/*! -+ \brief This is the data structure for basic vlan range -+*/ -+typedef struct { -+ uint32_t start_vlan_range; /*!< WAN interface start vlan id */ -+ uint32_t end_vlan_range; /*!< WAN interface end vlan id */ -+}PPA_VLAN_RANGE; -+ -+/*! -+ \brief This is the data structure VLAN range in mixed mode -+*/ -+typedef struct { -+ PPA_CMD_COUNT_INFO count_info; /*!< PPA Count info */ -+ PPA_VLAN_RANGE ranges[1]; /*!< it is dummy array, need to malloc in userspace */ -+} PPA_CMD_VLAN_RANGES; -+ -+/*! -+ \brief This is the data structure for MAC INFO -+*/ -+typedef struct { -+ PPA_CMD_COUNT_INFO count_info; /*!< PPA Count info */ -+ PPA_CMD_MAC_ENTRY session_list[1]; /*!< it is a dummy array, need to malloc bedore use it in userspace */ -+} PPA_CMD_ALL_MAC_INFO; -+ -+/*! -+ \brief This is the data structure for BRIGE MAC LEARNING ENABLE/DISABLE INFO -+*/ -+typedef struct { -+ uint32_t bridge_enable; /*!< enable/disable bridging mac address learning flag */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_BRIDGE_ENABLE_INFO; -+ -+typedef struct { -+ uint32_t t; /*!< Time Tick */ -+ uint32_t w; /*!< weight */ -+ uint32_t s; /*!< burst */ -+ uint32_t r; /*!< Replenish */ -+ uint32_t d; /*!< ppe internal variable */ -+ uint32_t tick_cnt; /*!< ppe internal variable */ -+ uint32_t b; /*!< ppe internal variable */ -+ -+ /*For PPA Level only */ -+ uint32_t reg_addr; /*!< register address */ -+ uint32_t bit_rate_kbps; /*!< rate shaping in kbps */ -+ uint32_t weight_level; /*!< internal wfq weight */ -+ -+}PPA_QOS_INTERVAL; -+ -+typedef struct { -+ //struct wtx_qos_q_desc_cfg -+ uint32_t threshold; /*!< qos wtx threshold */ -+ uint32_t length; /*!< qos wtx length */ -+ uint32_t addr; /*!< qos wtx address */ -+ uint32_t rd_ptr; /*!< qos wtx read pointer */ -+ uint32_t wr_ptr; /*!< qos wtx write pointer */ -+ -+ /*For PPA Level only */ -+ uint32_t reg_addr; /*!< register address */ -+}PPA_QOS_DESC_CFG_INTERNAL; -+ -+ -+/*! -+ \brief This is the data structure for PPA QOS to get the maximum queue number supported for one physical port -+*/ -+typedef struct { -+ uint32_t portid; /*!< the phisical port id which support qos queue */ -+ uint32_t queue_num; /*!< the maximum queue number is supported */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_QUEUE_NUM_INFO; -+ -+/*! -+ \brief This is the data structure for PPA QOS MIB Counter -+*/ -+typedef struct { -+ uint32_t total_rx_pkt; /*!< all packets received by this queue */ -+ uint32_t total_rx_bytes; /*!< all bytes received by thi queue */ -+ uint32_t total_tx_pkt; /*!< all packets trasmitted by this queue */ -+ uint32_t total_tx_bytes; /*!< all bytes trasmitted by thi queue */ -+ -+ uint32_t cpu_path_small_pkt_drop_cnt; /*!< all small packets dropped in CPU path for lack of TX DMA descriptor in the queue*/ -+ uint32_t cpu_path_total_pkt_drop_cnt; /*!< all packets dropped in CPU path for lack of TX DMA descriptor in the queue*/ -+ uint32_t fast_path_small_pkt_drop_cnt; /*!< all small packets dropped in fast path for lack of TX DMA descriptor */ -+ uint32_t fast_path_total_pkt_drop_cnt; /*!< all packets dropped in fast path for lack of TX DMA descriptor */ -+} PPA_QOS_MIB; -+ -+/*! -+ \brief This is the data structure for PPA QOS to get the maximum queue number supported for one physical port -+*/ -+typedef struct { -+ uint32_t portid; /*!< the phisical port id which support qos queue */ -+ uint32_t queueid; /*!< the queue id for the mib */ -+ PPA_QOS_MIB mib; /*!< the mib information for the current specified queue */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_QOS_MIB_INFO; -+ -+ -+ -+/*! -+ \brief This is the data structure for PPA QOS to be enabled/disabled -+*/ -+typedef struct { -+ uint32_t portid; /*!< which support qos queue. */ -+ uint32_t enable; /*!< enable/disable flag */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_QOS_CTRL_INFO; -+ -+/*! -+ \brief This is the data structure for PPA Rate Shapping Set/Get/Reset one queue's rate limit -+*/ -+typedef struct { -+ uint32_t portid; /*!< the phisical port id which support qos queue */ -+ uint32_t queueid; /*!< the queu id. Now it only support 0 ~ 7 */ -+ uint32_t rate; /*!< rate limit in kbps */ -+ uint32_t burst; /*!< rate limit in bytes. Note: it is PPE FW QOS internal value. Normally there is no need to set this value or just set to default value zero */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_RATE_INFO; -+ -+ -+ -+/*! -+ \brief This is the data structure for PPA WFQ Set/Get/Reset one queue's weight -+*/ -+typedef struct { -+ uint32_t portid; /*!< the phisical port id which support qos queue */ -+ uint32_t queueid; /*!< the queu id. Now it only support 0 ~ 7 */ -+ uint32_t weight; /*!< WFQ weight. The value is from 0 ~ 100 */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_WFQ_INFO; -+ -+#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) -+/*! -+ \brief Union of ppa power transitin watermark. -+*/ -+union watermark { -+ uint32_t ppa_pwm_wm1; /*!< Watermark value for PPE transition between D0 and D1 */ -+ uint32_t ppa_pwm_wm2; /*!< Watermark value for PPE transition between D1 and D2 */ -+ uint32_t ppa_pwm_wm3; /*!< Watermark value for PPE transition between D2 and D3 */ -+}; -+ -+/*! -+ \brief This is the data structure definition for PPA PWM states water mark -+*/ -+typedef struct { -+ int16_t flag; /*!< flag indicating if watermark type. flag=1: watermark is packet count; flag=2: watermark is byte count */ -+ int32_t time_interval; /*!< time interval of watermarks in milliseconds. */ -+ union watermark WM; /*!< Watermark value for PPE transition */ -+}WM_t; -+ -+/*! -+ \brief This is the data structure for PPA Power management basic watermark configuration -+*/ -+typedef struct { -+ WM_t ppa_pwm_wm1; /*!< Watermark value for PPE transition between D0 and D1 */ -+ WM_t ppa_pwm_wm2; /*!< Watermark value for PPE transition between D1 and D2*/ -+ WM_t ppa_pwm_wm3; /*!< Watermark value for PPE transition between D2 and D3*/ -+}PPA_PWM_WM_t; -+ -+/*! -+ \brief This is the data structure for PPA Power management configuration -+*/ -+typedef struct { -+ uint8_t ppa_pwm; /*!< PPA power management mode: 0/1-OFF/ON */ -+ PPA_PWM_WM_t ppa_pwm_wm_up; /*!< Watermark value for PPE transition for various states. */ -+ PPA_PWM_WM_t ppa_pwm_wm_down; /*!< Watermark value for PPE transition for various states. */ -+ PPA_PWM_STATE_t e_ppa_pwm_init_state; /*!< Initial power/performance state for PPE */ -+ uint32_t flag; /*!< reserved.*/ -+}PPA_PWM_CONFIG_t; -+#endif //end of CONFIG_IFX_PMCU -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment feature's basic auto-learning VLAN related information. -+*/ -+typedef struct -+{ -+ PPA_IFNAME tx_ifname[PPA_IF_NAME_SIZE]; /*!< destination interface name, like eth0.3. If blank, then match all interface */ -+ PPA_IFNAME rx_ifname[PPA_IF_NAME_SIZE]; /*!< receiving interface name, like eth1.2, If blank, then match all interface */ -+}PPA_MULTIFIELD_VLAN_INFO_AUTO; -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's manual-learning VLAN information based on default key selection. -+*/ -+typedef struct -+{ -+ uint8_t tx_if_id; /*!< physical destination interface id match, like 0 for eth0, 1 for eth1. It is part of key 14 */ -+ uint8_t rx_if_id; /*!< physical destination interface id match, like 0 for eth0, 1 for eth1. It is part of key 15 */ -+ uint8_t is_vlan; /*!< VLAN Flag match. 1: only match single vlan, 2: match double vlan, 0: match no vlan packet. It is part of key14 */ -+ uint8_t is_vlan_mask; /*!< VLAN Flag mask*/ -+ -+ uint8_t out_vlan_pri; /*!< outer vlan priority ( 3 bits only) match. Based on PPA default Key Selection, it is part of key 8/l2_off14 */ -+ uint8_t out_vlan_pri_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ uint8_t out_vlan_cfi; /*!< outer vlan cfi ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 8/l2_off14 */ -+ uint8_t out_vlan_cfi_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint16_t out_vlan_vid; /*!< outer vlan id ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 8 and 9/l2_off14-15 */ -+ uint16_t out_vlan_vid_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint8_t in_vlan_pri; /*!< inner vlan priority ( 3 bits only) match. Based on PPA default Key Selection, it is part of key 12/l2_off18 */ -+ uint8_t in_vlan_pri_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ uint8_t in_vlan_cfi; /*!< inner vlan cfi ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 12/l2_off18 */ -+ uint8_t in_vlan_cfi_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint16_t in_vlan_vid; /*!< inner vlan id ( 1 bits only) match. Based on PPA default Key Selection, it is part of key 12 and 13/l2_off18-19 */ -+ uint16_t in_vlan_vid_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint8_t action_out_vlan_insert; /*!< out vlan insert action */ -+ uint8_t action_in_vlan_insert; /*!< inner vlan insert action */ -+ uint8_t action_out_vlan_remove; /*!< out vlan remove action */ -+ uint8_t action_in_vlan_remove; /*!< inner vlan remove action */ -+ -+ uint8_t new_out_vlan_pri; /*!< action: new out vlan priority */ -+ uint8_t new_out_vlan_cfi; /*!< action:new out vlan cfi */ -+ uint8_t new_in_vlan_pri; /*!< action:new inner vlan priority */ -+ uint8_t new_in_vlan_cfi; /*!< action:new inner vlan cfi */ -+ -+ uint16_t new_out_vlan_vid; /*!< action:new out vlan id */ -+ uint16_t new_in_vlan_vid; /*!< action:new inner vlan id */ -+ -+ uint16_t new_out_vlan_tpid; /*!< action:new out vlan tpid */ -+}PPA_MULTIFIELD_VLAN_INFO_MANUAL; -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's VLAN KEY/MASK/ACTION based on default key selection. -+*/ -+typedef struct -+{ -+ uint8_t bfauto; /*!< flag to use simple autoway to add a multiple field editing flow. It is used by PPA API level and hook/ppacmd only*/ -+ PPA_MULTIFIELD_VLAN_INFO_AUTO vlan_info_auto; /*!< auto-learn vlan key/mask/action. Note, it is only for add/delete a rule, not for get commands */ -+ PPA_MULTIFIELD_VLAN_INFO_MANUAL vlan_info_manual; /*!< munually provide vlan key/mask/action. Even vlan_info_auto is used, ppa will set vlan_info_manual structure for PPE driver */ -+ -+}PPA_MULTIFIELD_VLAN_INFO; -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on default key selection. -+*/ -+typedef struct -+{ -+ uint16_t ether_type; /*!< ethernet type match, like 0x0800. Based on PPA default Key Selection, it is key0_1*/ -+ uint16_t ether_type_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint8_t dscp; /*!< dscp(tos) match. 1: key of dscp in ip header, like 0x08. Based on PPA default Key Selection, it is key2*/ -+ uint8_t dscp_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ uint8_t pkt_length; /*!< packet length ( less than) match. Its value is got from ethernet packet length /64. Based on PPA default Key Selection, it is key3*/ -+ uint8_t pkt_length_mask; /*!< packet length mask.*/ -+ -+ uint32_t s_ip; /*!< source ip match, like 0x0a000009 ( 10.0.0.9) . Based on PPA default Key Selection, it is key4 ~ Key7*/ -+ uint32_t s_ip_mask; /*!< match mask to specify the bits to match. Note, 0 means need to match and 1 means not to match*/ -+ -+ uint8_t l3_off0; /*!< L3 Offset 0 match. Baed on PPA default key selection, it is key10 */ -+ uint8_t l3_off0_mask; /*!< L3 Offset 0 mask */ -+ uint8_t l3_off1; /*!< L3 Offset 1 match. Baed on PPA default key selection, it is key11 */ -+ uint8_t l3_off1_mask; /*!< L3 Offset 1 mask */ -+ -+ uint8_t ipv4; /*!< ipv4 match ( 1 bit). 1: match only ipv4. 0: match none ipv4 packet. It is part of key15. */ -+ uint8_t ipv4_mask; /*!< ipv4 mask. 0 -need to match, 1-no need to match */ -+ uint8_t ipv6; /*!< < ipv6 match ( 1 bit). 1: match only ipv6. 0: match none ipv6 packet. 1: match only ipv6, 0: match none ipv6 packet. It is part of key15 */ -+ uint8_t ipv6_mask; /*!< ipv6 mask. 0 -need to match, 1-no need to match */ -+ -+ uint8_t pppoe_session; /*!< pppoe session flag match: 1: match pppoe session only. 0-- match none pppoe session packet. It is part of key14 */ -+ uint8_t pppoe_session_mask; /*!< pppoe session flag mask. 0 -need to match, 1-no need to match */ -+ uint8_t fwd_cpu; /*!< action: forward packet to CPU or not. \n -+ 1: forward to CPU. -+ 0: forward to its original destination port\n */ -+ -+ uint8_t queue_id; /*!< action: which queue assign for the current flow. */ -+ -+ PPA_MULTIFIELD_VLAN_INFO vlan_info; /*!< specify vlan key/mask/action. Based on PPA default Key Selection. It relates to key8/key9, key 12/key13 and key14/key15 and part of vlan action*/ -+} PPA_MULTIFIELD_DEFAULT_INFO; -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on second default key selection. -+ \note, for future only now -+*/ -+ -+typedef struct -+{ -+ -+}PPA_MULTIFIELD_DEFAULT2_INFO; -+ -+/*! -+ \brief This is the data structure for Mutiple Field Based Classification And VLAN Assigment's configuration based on different key selection. -+ \note More key selection based configuration will be implemented. Note, different key selectoin may have different configuration. \n -+ PPA should parse the cfg according to current key selection mode -+ -+*/ -+typedef union -+{ -+ PPA_MULTIFIELD_DEFAULT_INFO cfg0; /*!< multiple field configuration based on default key selection. */ -+ PPA_MULTIFIELD_DEFAULT2_INFO cfg2; /*!< multiple field configuration based on second default key selection. */ -+}PPA_MULTIFIELD_FLOW_INFO; -+ -+/*! -+ \brief This is the data structure for IOCTL of Mutiple Field Based Classification And VLAN Assigment's configuration. -+ -+*/ -+typedef struct -+{ -+ int32_t index; /*!< for get command, it is input, for add command, it is input. for del, it is input ( index must be valid in this case, -1 means delete all flow ) */ -+ int32_t last_index; /*!< for get command. It will be used in ppacmd.c only */ -+ uint32_t flag; /*!< Most time, it is input only. But for PPA_CMD_GET_MULTIFIELD_STATUS, it is input/ouput */ -+ PPA_MULTIFIELD_FLOW_INFO flow; /*!< the Mutiple Field Based Classification And VLAN Assigment configuration/information */ -+} PPA_CMD_MULTIFIELD_FLOW_INFO ; -+ -+/*! -+ \brief This is the data structure for IOCTL to enable/disable Mutiple Field Based Classification And VLAN Assigment. -+ -+*/ -+typedef struct PPA_CMD_ENABLE_MULTIFIELD_INFO -+{ -+ uint32_t enable_multifield; /*!< flag of enable/disable the Mutiple Field Based Classification And VLAN Assigment feature */ -+ uint32_t flag; /*!< reserved for future */ -+} PPA_CMD_ENABLE_MULTIFIELD_INFO; -+ -+/*! -+ \brief This is the data structure for getting all exported PPA hooks. -+*/ -+typedef struct -+{ -+ uint8_t hookname[MAX_HOOK_NAME_LEN]; /*!< hook name */ -+ uint32_t hook_addr; /*!< hook address */ -+ uint32_t real_func; /*!< hook pointer to real function*/ -+ uint8_t hook_flag; /*!< hooked flag: 0-disabled, 1-enabled */ -+}PPA_HOOK_INFO; -+ -+/*! -+ \brief This is the data structure for PPA hooks list -+*/ -+typedef struct PPA_HOOK_INFO_LIST { -+ PPA_HOOK_INFO info; /*!< ppa hook info */ -+ -+ struct PPA_HOOK_INFO_LIST *next; /*!< point to next ppa hook info */ -+} PPA_HOOK_INFO_LIST; -+ -+/*! -+ \brief This is the data structure for getting all exported PPA hooks. -+*/ -+typedef struct -+{ -+ uint32_t hook_count; /*!< hook counter */ -+ uint32_t flag; /*!< reserved for future */ -+ PPA_HOOK_INFO list[1]; /*!< it is a dummy array. Userspace should apply storage buffer for it. */ -+}PPA_CMD_HOOK_LIST_INFO; -+ -+/*! -+ \brief This is the data structure for enable/disable ppa hook -+*/ -+typedef struct -+{ -+ uint8_t hookname[MAX_HOOK_NAME_LEN]; /*!< hook name */ -+ uint32_t enable; /*!< enable/disable ppa hook */ -+ uint32_t flag; /*!< reserved for future */ -+}PPA_HOOK_ENABLE_INFO; -+ -+/*! -+ \brief This is the data structure for IOCTL to enable/disable ppa hook -+*/ -+typedef PPA_HOOK_ENABLE_INFO PPA_CMD_HOOK_ENABLE_INFO; -+ -+/*! -+ \brief This is the data structure to get the memory value. -+*/ -+typedef struct -+{ -+ uint32_t addr; /*!< The memory adddress to read */ -+ uint32_t addr_mapped; /*!< The mapped memory adddress to read */ -+ uint32_t shift; /*!< the bits to shitf */ -+ uint32_t size; /*!< size of bits to read*/ -+ uint32_t repeat; /*!< read repeat times */ -+ uint32_t flag; /*!< reserved for future */ -+ uint32_t buffer[1]; /*!< the buffer to store the value. it is a dummy array. Userspace should apply storage buffer for it. Its size should be at least size * sizeof (uint32_t) */ -+}PPA_READ_MEM_INFO; -+ -+#ifdef NO_DOXY -+typedef PPA_READ_MEM_INFO PPA_CMD_READ_MEM_INFO; -+ -+/*! -+ \brief This is the data structure to set the memory value. -+*/ -+typedef struct -+{ -+ uint32_t addr; /*!< The memory adddress to set */ -+ uint32_t addr_mapped; /*!< The mapped memory adddress to read */ -+ uint32_t shift; /*!< the bits to shitf */ -+ uint32_t size; /*!< size of bits */ -+ uint32_t value; /*!< value of the data*/ -+ uint32_t repeat; /*!< set repeat times*/ -+ uint32_t flag; /*!< reserved for future */ -+}PPA_SET_MEM_INFO; -+ -+/*! -+ \brief This is the data structure to set the memory value for IOCTL. -+*/ -+typedef PPA_SET_MEM_INFO PPA_CMD_SET_MEM_INFO; -+#endif -+ -+/*! -+ \brief This is the data structure to get the maximum entries, like lan/wan/mc/bridging -+*/ -+typedef struct -+{ -+ uint32_t max_lan_entries; /*!< Maximum LAN session entries */ -+ uint32_t max_wan_entries; /*!< Maximum WAN session entries */ -+ uint32_t max_lan_collision_entries; /*!< Maximum LAN session entries */ -+ uint32_t max_wan_collision_entries; /*!< Maximum WAN session entries */ -+ uint32_t max_mc_entries; /*!< Maximum Multicast session entries */ -+ uint32_t max_bridging_entries;/*!< Maximum Bridge session entries */ -+ uint32_t max_ipv6_addr_entries; /*!< Maximum IPV6 address entries */ -+ uint32_t max_fw_queue; /*!< Maximum PPE FW queue number */ -+ uint32_t max_6rd_entries; /*!<Maximum 6rd tunnel entries */ -+ uint32_t max_dslite_entries; /*!<Maximum dslite tunnel entries */ -+ uint32_t max_mf_flow; /*!<Maximum multiple filed flow */ -+} PPA_MAX_ENTRY_INFO; -+ -+/*! -+ \brief This is the data structure to get the maximum entries for IOCTL. -+*/ -+typedef struct{ -+ PPA_MAX_ENTRY_INFO entries; /*!< max entry info*/ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_MAX_ENTRY_INFO; -+ -+/*! -+ \brief This is the data structure to get the physical port id For IOCTL. -+*/ -+typedef struct{ -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< the interface name */ -+ uint32_t portid; /*!< the port id */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_PORTID_INFO; -+ -+ -+/*! -+ \brief This is the data structure for DSL queue mib -+*/ -+typedef struct{ -+ uint32_t queue_num; /*!< the queue number filled in the drop mib*/ -+ uint32_t drop_mib[16]; /*!< the drop mib counter */ -+ -+ //later other DSL mib counter will be added here -+ uint32_t flag; /*!< reserved for futurer */ -+} PPA_DSL_QUEUE_MIB; -+ -+/*! -+ \brief This is the data structure for general ENABLE/DISABLE INFO -+*/ -+typedef struct { -+ uint32_t enable; /*!< enable/disable flag */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_GENERAL_ENABLE_INFO; -+ -+/*! -+ \brief This is the data structure to get the DSL queue drop mib for IOCTL. -+*/ -+typedef struct{ -+ PPA_DSL_QUEUE_MIB mib; /*!< dsl queue mib coutner. */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_DSL_MIB_INFO; -+ -+/*! -+ \brief This is the data structure for PORT mib -+*/ -+typedef struct{ -+ uint32_t ig_fast_brg_pkts; /*!< fast bridge receving packets */ -+ uint32_t ig_fast_brg_bytes; /*!< the fast bridge receving bytes */ -+ -+ uint32_t ig_fast_rt_ipv4_udp_pkts; /*!< the fast ipv4 routing udp receving packets */ -+ uint32_t ig_fast_rt_ipv4_tcp_pkts; /*!< the fast ipv4 routing tcp receving packets */ -+ uint32_t ig_fast_rt_ipv4_mc_pkts; /*!< the fast ipv4 routing multicast receving packets */ -+ uint32_t ig_fast_rt_ipv4_bytes; /*!< the fast ipv4 receving bytes */ -+ -+ uint32_t ig_fast_rt_ipv6_udp_pkts; /*!< the fast ipv6 routing udp receving packets*/ -+ uint32_t ig_fast_rt_ipv6_tcp_pkts; /*!< the fast ipv6 routing tcp receving packets */ -+ uint32_t ig_fast_rt_ipv6_bytes; /*!< the fast ipv6 routing receving bytes */ -+ -+ uint32_t ig_cpu_pkts; /*!cpu packets */ -+ uint32_t ig_cpu_bytes; /*!< cpu bytes */ -+ -+ uint32_t ig_drop_pkts; /*!< drop packets */ -+ uint32_t ig_drop_bytes; /*!< drop bytes */ -+ -+ uint32_t eg_fast_pkts; /*!< the fast transmiting packets */ -+ -+ uint32_t port_flag; /*!< port flag: PORT_MODE_ETH, PORT_MODE_DSL, PORT_MODE_EXT */ -+ -+} PPA_PORT_MIB_INFO; -+ -+/*! -+ \brief This is the data structure for PORT mib -+*/ -+typedef struct{ -+ PPA_PORT_MIB_INFO mib_info[8]; /*!< mib array: eth0, eth1, DSL, DSL(IPOA/PPPOA), ext1, ext2, ext3, ext4 */ -+ uint32_t port_num; /*!< maximum port number supported */ -+ uint32_t flags; /*!< reserved for future */ -+}PPA_PORT_MIB; -+ -+ -+/*! -+ \brief This is the data structure for changing to FPI address -+*/ -+typedef struct{ -+ uint32_t addr_orig; /*!< original address */ -+ uint32_t addr_fpi; /*!< converted FPI address */ -+ uint32_t flags; /*!< reserved for future */ -+}PPA_FPI_ADDR; -+ -+ -+#ifdef NO_DOXY -+typedef struct { -+ uint32_t mtu_ix; -+ uint32_t mtu; // for add/del/get mtu entry only -+} PPE_MTU_INFO; -+ -+typedef struct { -+ uint32_t pppoe_ix; -+ uint32_t pppoe_session_id; // for add/del/get a pppoe entry only -+} PPE_PPPOE_INFO; -+ -+typedef struct { -+ uint32_t mac_ix; -+ uint8_t mac[PPA_ETH_ALEN]; // for add/del/get a MAC entry only -+} PPE_ROUTE_MAC_INFO; -+ -+typedef struct { -+ uint32_t vlan_id; -+ uint32_t vlan_entry; -+} PPE_OUT_VLAN_INFO; -+ -+typedef struct { -+ uint32_t tunnel_idx; -+ uint32_t tunnel_type; -+ struct net_device *tx_dev; -+} PPE_TUNNEL_INFO; -+ -+typedef struct { -+ uint32_t f_is_lan; -+ IP_ADDR_C src_ip; -+ uint32_t src_port; -+ IP_ADDR_C dst_ip; -+ uint32_t dst_port; -+ uint32_t f_is_tcp; // 1: TCP, 0: UDP -+ uint32_t route_type; -+ IP_ADDR_C new_ip; //NAT IP -+ uint16_t new_port; //NAT UDP/TCP Port -+ uint8_t new_dst_mac[PPA_ETH_ALEN]; -+ PPE_ROUTE_MAC_INFO src_mac; -+ PPE_MTU_INFO mtu_info; -+ uint32_t pppoe_mode; -+ PPE_PPPOE_INFO pppoe_info; -+ PPE_TUNNEL_INFO tnnl_info; -+ -+ uint32_t f_new_dscp_enable; -+ uint32_t new_dscp; -+ uint32_t f_vlan_ins_enable; -+ uint32_t new_vci; -+ uint32_t f_vlan_rm_enable; -+ -+ uint32_t f_out_vlan_ins_enable; -+ PPE_OUT_VLAN_INFO out_vlan_info; -+ uint32_t f_out_vlan_rm_enable; -+ uint32_t dslwan_qid; -+ uint32_t dest_list; -+ uint32_t entry; -+ uint32_t update_flags; //for update_routing_entry only -+ uint64_t bytes; //for MIB -+ uint32_t f_hit; //only for test_and_clear_hit_stat -+ uint8_t collision_flag; // 1 mean the entry is in collsion table or no hashed table, like ASE/Danube -+} PPE_ROUTING_INFO; -+ -+ -+/*! -+ \brief This is the data structure to get the PORT queue mib for IOCTL. -+*/ -+typedef struct{ -+ PPA_PORT_MIB mib; /*!< port mib counter. */ -+ uint32_t flags; /*!< reserved for future */ -+} PPA_CMD_PORT_MIB_INFO; -+ -+typedef struct{ -+ uint32_t f_is_lan; -+ uint32_t entry_num; -+ uint32_t mc_entry_num; -+ uint32_t f_ip_verify; -+ uint32_t f_tcpudp_verify; -+ uint32_t f_tcpudp_err_drop; -+ uint32_t f_drop_on_no_hit; -+ uint32_t f_mc_drop_on_no_hit; -+ uint32_t flags; -+} PPE_ROUTING_CFG; -+ -+typedef struct{ -+ uint32_t entry_num; -+ uint32_t br_to_src_port_mask; uint32_t br_to_src_port_en; -+ uint32_t f_dest_vlan_en; -+ uint32_t f_src_vlan_en; -+ uint32_t f_mac_change_drop; -+ uint32_t flags; -+} PPE_BRDG_CFG; -+ -+typedef struct{ -+ uint32_t mode; -+ uint32_t flags; -+} PPE_FAST_MODE_CFG; -+ -+typedef struct { -+ uint32_t f_is_lan; -+ uint32_t f_enable; -+ uint32_t flags; -+} PPE_ACC_ENABLE; -+ -+typedef struct { -+ uint32_t uc_dest_list; -+ uint32_t mc_dest_list; -+ uint32_t if_no; -+} PPE_DEST_LIST; -+ -+typedef struct { -+ uint32_t if_no; -+ uint32_t f_eg_vlan_insert; -+ uint32_t f_eg_vlan_remove; -+ uint32_t f_ig_vlan_aware; -+ uint32_t f_ig_src_ip_based; -+ uint32_t f_ig_eth_type_based; -+ uint32_t f_ig_vlanid_based; -+ uint32_t f_ig_port_based; -+ uint32_t f_eg_out_vlan_insert; -+ uint32_t f_eg_out_vlan_remove; -+ uint32_t f_ig_out_vlan_aware; -+} PPE_BRDG_VLAN_CFG; -+ -+ -+typedef struct { -+ uint32_t entry; /*so far it is only for get command*/ -+ uint32_t ig_criteria_type; -+ uint32_t ig_criteria;; -+ uint32_t new_vci; -+ uint32_t dest_qos; -+ PPE_OUT_VLAN_INFO out_vlan_info; -+ uint32_t in_out_etag_ctrl; -+ uint32_t vlan_port_map; -+} PPE_BRDG_VLAN_FILTER_MAP; -+ -+typedef struct { -+ uint32_t dest_ip_compare; -+ uint32_t f_vlan_ins_enable; -+ uint32_t new_vci; -+ uint32_t f_vlan_rm_enable; -+ uint32_t f_src_mac_enable; -+ uint32_t src_mac_ix; -+ uint32_t pppoe_mode; -+ uint32_t f_out_vlan_ins_enable; -+ PPE_OUT_VLAN_INFO out_vlan_info; -+ uint32_t f_out_vlan_rm_enable; -+ uint32_t f_new_dscp_enable; -+ uint32_t new_dscp; -+ uint32_t dest_qid; -+ uint32_t dest_list; -+ uint32_t route_type; -+ uint32_t p_entry; -+ uint32_t update_flags; //only for update only,not for new added one -+} PPE_MC_INFO; -+ -+typedef struct { -+ uint32_t port; -+ uint8_t mac[PPA_ETH_ALEN]; -+ uint32_t f_src_mac_drop; -+ uint32_t dslwan_qid; -+ uint32_t dest_list; -+ uint32_t p_entry; -+ uint32_t f_hit; //only for test_and_clear_bridging_hit_stat -+} PPE_BR_MAC_INFO; -+ -+struct ppe_itf_mib { -+ uint32_t ig_fast_brg_pkts; // 0 bridge ? -+ uint32_t ig_fast_brg_bytes; // 1 ? -+ -+ uint32_t ig_fast_rt_ipv4_udp_pkts; // 2 IPV4 routing -+ uint32_t ig_fast_rt_ipv4_tcp_pkts; // 3 -+ uint32_t ig_fast_rt_ipv4_mc_pkts; // 4 -+ uint32_t ig_fast_rt_ipv4_bytes; // 5 -+ -+ uint32_t ig_fast_rt_ipv6_udp_pkts; // 6 IPV6 routing -+ uint32_t ig_fast_rt_ipv6_tcp_pkts; // 7 -+ uint32_t res0; // 8 -+ uint32_t ig_fast_rt_ipv6_bytes; // 9 -+ -+ uint32_t res1; // A -+ uint32_t ig_cpu_pkts; -+ uint32_t ig_cpu_bytes; -+ -+ uint32_t ig_drop_pkts; -+ uint32_t ig_drop_bytes; -+ -+ uint32_t eg_fast_pkts; -+}; -+ -+ -+typedef struct { -+ uint32_t itf ; //port -+ struct ppe_itf_mib mib; -+ uint32_t flag; -+} PPE_ITF_MIB_INFO; -+ -+typedef struct { -+ uint32_t f_enable ; -+ uint32_t flags ; -+} PPE_ENABLE_CFG; -+ -+typedef struct { -+ int32_t num ; -+ uint32_t flags ; -+} PPE_COUNT_CFG; -+ -+typedef struct { -+ uint32_t vfitler_type; -+ int32_t num ; -+ uint32_t flags ; -+} PPE_VFILTER_COUNT_CFG; -+ -+typedef struct { -+ PPA_MULTIFIELD_FLOW_INFO multifield_info; -+ uint32_t entry; -+ uint32_t flag; -+} PPE_MULTIFILED_FLOW; -+ -+typedef struct { -+ uint32_t portid; -+ uint32_t num ; -+ uint32_t flags ; -+} PPE_QOS_COUNT_CFG; -+ -+typedef struct { -+ uint32_t portid; -+ uint32_t queueid; -+ PPA_QOS_MIB mib; -+ uint32_t reg_addr; -+ uint32_t flag; -+} PPE_QOS_MIB_INFO; -+ -+typedef struct { -+ uint32_t portid; -+ uint32_t queueid; -+ uint32_t weight_level; -+ uint32_t flag; -+} PPE_QOS_WFQ_CFG; -+ -+typedef struct { -+ uint32_t portid; -+ uint32_t f_enable; -+ uint32_t flag; -+} PPE_QOS_ENABLE_CFG; -+ -+typedef struct { -+ uint32_t portid; -+ uint32_t queueid; -+ uint32_t rate_in_kbps; -+ uint32_t burst; -+ uint32_t flag; -+} PPE_QOS_RATE_SHAPING_CFG; -+ -+ -+typedef struct { -+ uint32_t vid; -+} PPE_WAN_VID_RANGE; -+ -+typedef struct { -+ PPA_IFNAME ifname[PPA_IF_NAME_SIZE]; /*!< Name of the stack interface */ -+ uint32_t if_flags; /*!< Flags for Interface. Valid values are below: PPA_F_LAN_IF and PPA_F_WAN_IF */ -+ uint32_t port; /*!< physical port id for this Interface. Valid values are below: 0 ~ */ -+} PPE_IFINFO; -+ -+#endif //end of NO_DOXY -+ -+typedef struct -+{ -+ uint32_t qos_queue_portid; /*!< the port id which support qos. at present, only one port can support QOS at run time */ -+ -+ //port's qos status -+ uint32_t time_tick ; /*!< number of PP32 cycles per basic time tick */ -+ uint32_t overhd_bytes ; /*!< number of overhead bytes per packet in rate shaping */ -+ uint32_t eth1_eg_qnum ; /*!< maximum number of egress QoS queues; */ -+ uint32_t eth1_burst_chk; /*!< always 1, more accurate WFQ */ -+ uint32_t eth1_qss ; /*!< 1-FW QoS, 0-HW QoS */ -+ uint32_t shape_en ; /*!< 1-enable rate shaping, 0-disable */ -+ uint32_t wfq_en ; /*!< 1-WFQ enabled, 0-strict priority enabled */ -+ -+ uint32_t tx_qos_cfg_addr; /*!< qos cfg address */ -+ uint32_t pp32_clk; /*!< pp32 clock */ -+ uint32_t basic_time_tick; /*!< pp32 qos time tick */ -+ -+ uint32_t wfq_multiple; /*!< qos wfq multipler */ -+ uint32_t wfq_multiple_addr; /*!< qos wfq multipler address */ -+ -+ uint32_t wfq_strict_pri_weight; /*!< strict priority's weight value */ -+ uint32_t wfq_strict_pri_weight_addr; /*!< strict priority's weight address */ -+ -+ uint32_t wan_port_map; /*!< wan port interface register value */ -+ uint32_t wan_mix_map; /*!< mixed register value */ -+ -+ -+ PPA_QOS_INTERVAL qos_port_rate_internal; /*!< internal qos port parameters */ -+ -+ uint32_t max_buffer_size; /*!< must match with below arrays, ie, here set to 8 */ -+ PPE_QOS_MIB_INFO mib[8]; -+ PPA_QOS_INTERVAL queue_internal[8]; /*!< internal qos queue parameters */ -+ PPA_QOS_DESC_CFG_INTERNAL desc_cfg_interanl[8];/*!< internal desc cfg parameters */ -+ -+} PPA_QOS_STATUS; -+ -+ -+/*! -+ \brief This is the data structure for PPA QOS to get the status -+*/ -+typedef struct { -+ PPA_QOS_STATUS qstat; /*!< qos status buffer */ -+ uint32_t flags; /*!< Reserved currently */ -+} PPA_CMD_QOS_STATUS_INFO; -+ -+ -+ -+/*! -+ \brief This is the data structure for IOCTL -+*/ -+typedef union -+{ -+ PPA_CMD_INIT_INFO init_info; /*!< PPA init parameter */ -+ PPA_CMD_ENABLE_INFO ena_info; /*!< PPA enable parameter */ -+ PPA_CMD_MC_ENTRY mc_entry; /*!< PPA multicast parameter */ -+ PPA_CMD_MAC_ENTRY mac_entry; /*!< PPA mac parameter */ -+ PPA_CMD_BR_IF_VLAN_CONFIG br_vlan; /*!< PPA bridge parameter */ -+ PPA_CMD_VLAN_FILTER_CONFIG vlan_filter; /*!< PPA vlan filter parameter */ -+ PPA_CMD_VLAN_ALL_FILTER_CONFIG all_vlan_filter;/*!< PPA get all vlan filter list parameter */ -+ PPA_CMD_IF_MAC_INFO if_mac; /*!< PPA interface mac parameter */ -+ PPA_CMD_IFINFO if_info; /*!< PPA interface parameter */ -+ PPA_CMD_IFINFOS all_if_info; /*!< PPA all interface list parameter */ -+ PPA_CMD_MC_GROUP_INFO mc_add_info; /*!< PPA add multcast parameter */ -+ PPA_CMD_COUNT_INFO count_info; /*!< PPA get count parameter */ -+ PPA_CMD_SESSIONS_INFO session_info; /*!< PPA unicast session parameter */ -+ PPA_CMD_SESSION_EXTRA_ENTRY session_extra_info; /*!< PPA extra session parameter */ -+ PPA_CMD_SESSION_TIMER session_timer_info; /*!< PPA extra session timer parameter */ -+ PPA_CMD_SESSIONS_DETAIL_INFO detail_session_info; /*!< PPA unicast session detail parameter for add a testing routing acceleration entry into PPE FW directly*/ -+ PPA_CMD_VERSION_INFO ver; /*!< PPA version parameter */ -+ PPA_CMD_MC_GROUPS_INFO mc_groups; /*!< PPA multicast group parameter */ -+ PPA_CMD_ALL_MAC_INFO all_br_info; /*!< PPA all bridge list parameter */ -+ PPA_VLAN_RANGE wan_vlanid_range; /*!< PPA wan vlan range parameter */ -+ PPA_CMD_VLAN_RANGES all_wan_vlanid_range_info; /*!< PPA all wan vlan range list parameter */ -+ PPA_CMD_SIZE_INFO size_info; /*!< PPA major structure size parameter */ -+ PPA_CMD_BRIDGE_ENABLE_INFO br_enable_info; /*!< PPA enable/disable bridging mac learning parameter */ -+#ifdef CONFIG_IFX_PPA_QOS -+ PPA_CMD_QOS_STATUS_INFO qos_status_info; /*!< PPA qos status parameter */ -+ PPA_CMD_QUEUE_NUM_INFO qnum_info; /*!< PPA qos queue parameter */ -+ PPA_CMD_QOS_CTRL_INFO qos_ctrl_info; /*!< PPA qos control parameter */ -+ PPA_CMD_QOS_MIB_INFO qos_mib_info; /*!< PPA qos mib parameter */ -+#ifdef CONFIG_IFX_PPA_QOS_RATE_SHAPING -+ PPA_CMD_RATE_INFO qos_rate_info; /*!< PPA qos rate shapping parameter */ -+#endif //end of CONFIG_IFX_PPA_QOS_RATE_SHAPING -+#ifdef CONFIG_IFX_PPA_QOS_WFQ -+ PPA_CMD_WFQ_INFO qos_wfq_info; /*!< PPA qos wfq parameter */ -+#endif //end of CONFIG_IFX_PPA_QOS_WFQ -+#endif //end of CONFIG_IFX_PPA_QOS -+ PPA_CMD_HOOK_LIST_INFO hook_list_info; /*!< PPA all registered hook list */ -+ PPA_CMD_HOOK_ENABLE_INFO hook_control_info; /*!< PPA control information: enable/disable */ -+#ifdef NO_DOXY -+ PPA_CMD_READ_MEM_INFO read_mem_info; /*!< PPA read memory info */ -+ PPA_CMD_SET_MEM_INFO set_mem_info; /*!< PPA write memory info */ -+#endif -+#if defined(CONFIG_IFX_PPA_MFE) && CONFIG_IFX_PPA_MFE -+ PPA_CMD_ENABLE_MULTIFIELD_INFO mf_ctrl_info; /*!< PPA multiple field edting status info */ -+ PPA_CMD_MULTIFIELD_FLOW_INFO mf_flow_info; /*!< PPA multiple field flow info */ -+#endif //end of CONFIG_IFX_PPA_MFE -+ -+ PPA_CMD_MAX_ENTRY_INFO acc_entry_info; /*!< PPA maximum entries supported */ -+ PPA_CMD_PORTID_INFO portid_info; /*!< PPA portid from interface name */ -+ PPA_CMD_DSL_MIB_INFO dsl_mib_info; /*!< PPA DSL queue mib counter. At present only drop counter is supported */ -+ PPA_CMD_PORT_MIB_INFO port_mib_info; /*!< PPA PORT mib counter. */ -+ PPA_CMD_GENERAL_ENABLE_INFO genernal_enable_info; /*!< General PPA enable/disable info. */ -+} PPA_CMD_DATA; -+ -+ -+/*@}*/ /* PPA_IOCTL */ -+ -+ -+/* -------------------------------------------------------------------------- */ -+/* IOCTL Command Definitions */ -+/* -------------------------------------------------------------------------- */ -+/** \addtogroup PPA_IOCTL */ -+/*@{*/ -+ -+/** PPA IOCTL NR values -+*/ -+typedef enum { -+PPA_CMD_INIT_NR=0, /*!< NR for PPA_CMD_INI */ -+PPA_CMD_EXIT_NR, /*!< NR for PPA_CMD_EXIT */ -+PPA_CMD_ENABLE_NR, /*!< NR for PPA_CMD_ENABLE */ -+PPA_CMD_GET_STATUS_NR, /*!< NR for PPA_CMD_GET_STATUS */ -+PPA_CMD_MODIFY_MC_ENTRY_NR, /*!< NR for PPA_CMD_MODIFY_MC_ENTRY */ -+PPA_CMD_GET_MC_ENTRY_NR, /*!< NR for PPA_CMD_GET_MC_ENTRY */ -+PPA_CMD_ADD_MAC_ENTRY_NR, /*!< NR for PPA_CMD_ADD_MAC_ENTRY */ -+PPA_CMD_DEL_MAC_ENTRY_NR, /*!< NR for PPA_CMD_DEL_MAC_ENTRY */ -+PPA_CMD_SET_VLAN_IF_CFG_NR, /*!< NR for PPA_CMD_SET_VLAN_IF_CFG */ -+PPA_CMD_GET_VLAN_IF_CFG_NR, /*!< NR for PPA_CMD_GET_VLAN_IF_CFG */ -+PPA_CMD_ADD_VLAN_FILTER_CFG_NR, /*!< NR for PPA_CMD_ADD_VLAN_FILTER_CFG */ -+PPA_CMD_DEL_VLAN_FILTER_CFG_NR, /*!< NR for PPA_CMD_DEL_VLAN_FILTER_CFG */ -+PPA_CMD_GET_ALL_VLAN_FILTER_CFG_NR, /*!< NR for PPA_CMD_GET_ALL_VLAN_FILTER_CFG */ -+PPA_CMD_DEL_ALL_VLAN_FILTER_CFG_NR, /*!< NR for PPA_CMD_DEL_ALL_VLAN_FILTER_CFG */ -+PPA_CMD_SET_IF_MAC_NR, /*!< NR for PPA_CMD_SET_IF_MAC */ -+PPA_CMD_GET_IF_MAC_NR, /*!< NR for PPA_CMD_GET_IF_MAC */ -+PPA_CMD_ADD_LAN_IF_NR, /*!< NR for PPA_CMD_ADD_LAN_IF */ -+PPA_CMD_ADD_WAN_IF_NR, /*!< NR for PPA_CMD_ADD_WAN_IF */ -+PPA_CMD_DEL_LAN_IF_NR, /*!< NR for PPA_CMD_DEL_LAN_IF */ -+PPA_CMD_DEL_WAN_IF_NR, /*!< NR for PPA_CMD_DEL_WAN_IF */ -+PPA_CMD_GET_LAN_IF_NR, /*!< NR for PPA_CMD_GET_LAN_IF */ -+PPA_CMD_GET_WAN_IF_NR, /*!< NR for PPA_CMD_GET_WAN_IF */ -+PPA_CMD_ADD_MC_NR, /*!< NR for PPA_CMD_ADD_MC */ -+PPA_CMD_GET_MC_GROUPS_NR, /*!< NR for PPA_CMD_GET_MC_GROUPS */ -+PPA_CMD_GET_COUNT_LAN_SESSION_NR, /*!< NR for PPA_CMD_GET_COUNT_LAN_SESSION */ -+PPA_CMD_GET_COUNT_WAN_SESSION_NR, /*!< NR for PPA_CMD_GET_COUNT_WAN_SESSION */ -+PPA_CMD_GET_COUNT_MC_GROUP_NR, /*!< NR for PPA_CMD_GET_COUNT_MC_GROUP */ -+PPA_CMD_GET_COUNT_VLAN_FILTER_NR, /*!< NR for PPA_CMD_GET_COUNT_VLAN_FILTER */ -+PPA_CMD_GET_LAN_SESSIONS_NR, /*!< NR for PPA_CMD_GET_LAN_SESSIONS */ -+PPA_CMD_GET_WAN_SESSIONS_NR, /*!< NR for PPA_CMD_GET_WAN_SESSIONS */ -+PPA_CMD_GET_VERSION_NR, /*!< NR for PPA_CMD_GET_VERSION */ -+PPA_CMD_GET_COUNT_MAC_NR, /*!< NR for PPA_CMD_GET_COUNT_MAC */ -+PPA_CMD_GET_ALL_MAC_NR, /*!< NR for PPA_CMD_GET_ALL_MAC */ -+PPA_CMD_WAN_MII0_VLAN_RANGE_ADD_NR, /*!< NR for PPA_CMD_WAN_MII0_VLAN_RANGE_ADD */ -+PPA_CMD_WAN_MII0_VLAN_RANGE_GET_NR, /*!< NR for PPA_CMD_WAN_MII0_VLAN_RANGE_GET */ -+PPA_CMD_GET_COUNT_WAN_MII0_VLAN_RANGE_NR, /*!< NR for PPA_CMD_GET_COUNT_WAN_MII0_VLAN_RANGE */ -+PPA_CMD_GET_SIZE_NR, /*!< NR for PPA_CMD_GET_SIZE */ -+PPA_CMD_BRIDGE_ENABLE_NR, /*!< NR for PPA_CMD_BRIDGE_ENABLE */ -+PPA_CMD_GET_BRIDGE_STATUS_NR, /*!< NR for PPA_CMD_GET_BRIDGE_STATUS */ -+PPA_CMD_GET_QOS_QUEUE_MAX_NUM_NR, /*!< NR for PPA_CMD_GET_QOS_QUEUE_MAX_NUM */ -+PPA_CMD_SET_QOS_WFQ_NR, /*!< NR for PPA_CMD_SET_QOS_WFQ */ -+PPA_CMD_GET_QOS_WFQ_NR, /*!< NR for PPA_CMD_SET_QOS_WFQ */ -+PPA_CMD_RESET_QOS_WFQ_NR, /*!< NR for PPA_CMD_GET_QOS_WFQ */ -+PPA_CMD_ENABLE_MULTIFIELD_NR, /*!< NR for PPA_CMD_ENABLE_MULTIFIELD */ -+PPA_CMD_GET_MULTIFIELD_STATUS_NR, /*!< NR for PPA_CMD_GET_MULTIFIELD_STATUS */ -+PPA_CMD_GET_MULTIFIELD_ENTRY_MAX_NR, /*!< NR for PPA_CMD_GET_MULTIFIELD_ENTRY_MAX */ -+PPA_CMD_GET_MULTIFIELD_KEY_NUM_NR, /*!< NR for PPA_CMD_GET_MULTIFIELD_KEY_NUM */ -+PPA_CMD_ADD_MULTIFIELD_NR, /*!< NR for PPA_CMD_ADD_MULTIFIELD */ -+PPA_CMD_GET_MULTIFIELD_NR, /*!< NR for PPA_CMD_GET_MULTIFIELD */ -+PPA_CMD_DEL_MULTIFIELD_NR, /*!< NR for PPA_CMD_DEL_MULTIFIELD */ -+PPA_CMD_DEL_MULTIFIELD_VIA_INDEX_NR, /*!< NR for PPA_CMD_DEL_MULTIFIELD_VIA_INDEX */ -+PPA_CMD_GET_HOOK_COUNT_NR, /*!< NR for PPA_CMD_GET_HOOK_COUNT */ -+PPA_CMD_GET_HOOK_LIST_NR, /*!< NR for PPA_CMD_GET_HOOK_LIST */ -+PPA_CMD_SET_HOOK_NR, /*!< NR for PPA_CMD_SET_HOOK */ -+PPA_CMD_READ_MEM_NR, /*!< NR for PPA_CMD_SET_MEM */ -+PPA_CMD_SET_MEM_NR, /*!< NR for PPA_CMD_SET_MEM */ -+PPA_CMD_SET_CTRL_QOS_WFQ_NR, /*!< NR for PPA_CMD_SET_CTRL_QOS_WFQ */ -+PPA_CMD_GET_CTRL_QOS_WFQ_NR, /*!< NR for PPA_CMD_GET_CTRL_QOS_WFQ */ -+PPA_CMD_SET_CTRL_QOS_RATE_NR, /*!< NR for PPA_CMD_SET_CTRL_QOS_RATE */ -+PPA_CMD_GET_CTRL_QOS_RATE_NR, /*!< NR for PPA_CMD_GET_CTRL_QOS_RATE */ -+PPA_CMD_SET_QOS_RATE_NR, /*!< NR for PPA_CMD_SET_QOS_RATE */ -+PPA_CMD_GET_QOS_RATE_NR, /*!< NR for PPA_CMD_GET_QOS_RATE */ -+PPA_CMD_RESET_QOS_RATE_NR, /*!< NR for PPA_CMD_RESET_QOS_RATE */ -+PPA_CMD_GET_QOS_MIB_NR, /*!< NR for PPA_CMD_GET_QOS_MIB */ -+PPA_CMD_GET_MAX_ENTRY_NR, /*!< NR for PPA_CMD_GET_MAX_ENTRY */ -+PPA_CMD_GET_PORTID_NR, /*!< NR for PPA_GET_CMD_PORTID */ -+PPA_CMD_GET_DSL_MIB_NR, /*!< NR for PPA_GET_DSL_MIB */ -+PPA_CMD_CLEAR_DSL_MIB_NR, /*!< NR for PPA_CLEAR_DSL_MIB */ -+PPA_CMD_DEL_SESSION_NR, /*!< NR for PPA_CMD_DEL_SESSION */ -+PPA_CMD_ADD_SESSION_NR, /*!< NR for PPA_CMD_ADD_SESSION */ -+PPA_CMD_MODIFY_SESSION_NR, /*!< NR for PPA_CMD_MODIFY_SESSION */ -+PPA_CMD_SET_SESSION_TIMER_NR, /*!< NR for PPA_CMD_SET_SESSION_TIMER */ -+PPA_CMD_GET_SESSION_TIMER_NR, /*!< NR for PPA_CMD_GET_SESSION_TIMER */ -+PPA_CMD_GET_PORT_MIB_NR, /*!< NR for PPA_GET_PORT_MIB */ -+PPA_CMD_CLEAR_PORT_MIB_NR, /*!< NR for PPA_CLEAR_PORT_MIB */ -+PPA_CMD_SET_HAL_DBG_FLAG_NR, /*!< NR for PPA_CMD_SET_HAL_DBG_FLAG */ -+PPA_CMD_GET_QOS_STATUS_NR, /*!< NR for PPA_CMD_GET_QOS_STATUS */ -+ -+/* PPA_IOC_MAXNR should be the last one in the enumberation */ -+PPA_IOC_MAXNR /*!< NR for PPA_IOC_MAXNR */ -+}PPA_IOC_NR; -+ -+/** PPA Initialization Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_INIT_INFO The parameter points to a -+ \ref PPA_CMD_INIT_INFO structure -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#define PPA_CMD_INIT _IOW(PPA_IOC_MAGIC, PPA_CMD_INIT_NR, PPA_CMD_INIT_INFO) -+ -+ -+ -+/** PPA Un-init or exit command. Value is manipulated by _IO() macro for final value -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#define PPA_CMD_EXIT _IO(PPA_IOC_MAGIC, PPA_CMD_EXIT_NR) -+ -+/** PPA Acceleration Enable / Disable Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_ENABLE_INFO The parameter points to a -+ \ref PPA_CMD_ENABLE_INFO structure -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#define PPA_CMD_ENABLE _IOW(PPA_IOC_MAGIC, PPA_CMD_ENABLE_NR, PPA_CMD_ENABLE_INFO) -+ -+/** PPA Acceleration Get Status Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_ENABLE_INFO The parameter points to a -+ \ref PPA_CMD_ENABLE_INFO structure. Enable or disable configuration status. -+*/ -+#define PPA_CMD_GET_STATUS _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_STATUS_NR, PPA_CMD_ENABLE_INFO) -+ -+/** PPA Modify Multicast session parameters Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MC_ENTRY The parameter points to a -+ \ref PPA_CMD_MC_ENTRY structure -+*/ -+#define PPA_CMD_MODIFY_MC_ENTRY _IOW(PPA_IOC_MAGIC, PPA_CMD_MODIFY_MC_ENTRY_NR, PPA_CMD_MC_ENTRY) -+ -+/** PPA Get Multicast session parameters Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MC_ENTRY The parameter points to a -+ \ref PPA_CMD_MC_ENTRY structure -+*/ -+#define PPA_CMD_GET_MC_ENTRY _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_MC_ENTRY_NR, PPA_CMD_MC_ENTRY) -+ -+/** PPA Add a MAC entry to the bridging MAC table Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MAC_ENTRY The parameter points to a -+ \ref PPA_CMD_MAC_ENTRY structure -+*/ -+#define PPA_CMD_ADD_MAC_ENTRY _IOW(PPA_IOC_MAGIC, PPA_CMD_ADD_MAC_ENTRY_NR, PPA_CMD_MAC_ENTRY) -+ -+/** PPA Delete a MAC entry to the bridging MAC table Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MAC_ENTRY The parameter points to a -+ \ref PPA_CMD_MAC_ENTRY structure -+*/ -+#define PPA_CMD_DEL_MAC_ENTRY _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_MAC_ENTRY_NR, PPA_CMD_MAC_ENTRY) -+ -+/** PPA Set Interface VLAN configuration Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_BR_IF_VLAN_CONFIG The parameter points to a -+ \ref PPA_CMD_BR_IF_VLAN_CONFIG structure -+*/ -+#define PPA_CMD_SET_VLAN_IF_CFG _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_VLAN_IF_CFG_NR, PPA_CMD_BR_IF_VLAN_CONFIG) -+ -+/** PPA Get All VLAN Filter Configuration Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_BR_IF_VLAN_CONFIG The parameter points to a -+ \ref PPA_CMD_BR_IF_VLAN_CONFIG structure -+*/ -+#define PPA_CMD_GET_VLAN_IF_CFG _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_VLAN_IF_CFG_NR, PPA_CMD_BR_IF_VLAN_CONFIG) -+ -+/** PPA Add VLAN filter configuration Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_VLAN_FILTER_CONFIG The parameter points to a -+ \ref PPA_CMD_VLAN_FILTER_CONFIG structure -+*/ -+#define PPA_CMD_ADD_VLAN_FILTER_CFG _IOW(PPA_IOC_MAGIC, PPA_CMD_ADD_VLAN_FILTER_CFG_NR, PPA_CMD_VLAN_FILTER_CONFIG) -+ -+/** PPA Delete VLAN filter configuration Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_VLAN_FILTER_CONFIG The parameter points to a -+ \ref PPA_CMD_VLAN_FILTER_CONFIG structure -+*/ -+#define PPA_CMD_DEL_VLAN_FILTER_CFG _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_VLAN_FILTER_CFG_NR, PPA_CMD_VLAN_FILTER_CONFIG) -+ -+/** PPA Delete all VLAN Filter Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_VLAN_ALL_FILTER_CONFIG The parameter points to a -+ \ref PPA_CMD_VLAN_ALL_FILTER_CONFIG structure -+*/ -+#define PPA_CMD_GET_ALL_VLAN_FILTER_CFG _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_ALL_VLAN_FILTER_CFG_NR, PPA_CMD_VLAN_ALL_FILTER_CONFIG) -+ -+/** PPA Get All VLAN Filter Configuration Command. Value is manipulated by _IOR() macro for final value -+*/ -+#define PPA_CMD_DEL_ALL_VLAN_FILTER_CFG _IO(PPA_IOC_MAGIC, PPA_CMD_DEL_ALL_VLAN_FILTER_CFG_NR) -+ -+/** PA Set Interface MAC address Command. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_IF_MAC_INFO The parameter points to a -+ \ref PPA_CMD_IF_MAC_INFO structure -+*/ -+#define PPA_CMD_SET_IF_MAC _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_IF_MAC_NR, PPA_CMD_IF_MAC_INFO) -+ -+/** PPA Get Interface MAC address Command. Value is anipulated by _IOWR() macro for final value -+ \param PPA_CMD_IF_MAC_INFO The parameter points to a -+ \ref PPA_CMD_IF_MAC_INFO structure -+*/ -+#define PPA_CMD_GET_IF_MAC _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_IF_MAC_NR, PPA_CMD_IF_MAC_INFO) -+ -+/** PPA Add LAN Interface Command. It is used to register a LAN network interface with the PPA. Value is anipulated by _IOW() macro for final value -+ \param PPA_CMD_IFINFO The parameter points to a -+ \ref PPA_CMD_IFINFO structure -+*/ -+#define PPA_CMD_ADD_LAN_IF _IOW(PPA_IOC_MAGIC, PPA_CMD_ADD_LAN_IF_NR, PPA_CMD_IFINFO) -+ -+/** PPA Add WAN interface Command. It is used to register a WN network interface with the PPA. Value is anipulated by _IOW() macro for final value -+ \param PPA_CMD_IFINFO The parameter points to a -+ \ref PPA_CMD_IFINFO structure -+*/ -+#define PPA_CMD_ADD_WAN_IF _IOW(PPA_IOC_MAGIC, PPA_CMD_ADD_WAN_IF_NR, PPA_CMD_IFINFO) -+ -+/** A Delete LAN Interface Command. It is used to de-register a LAN network interface. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_IFINFO The parameter points to a -+ \ref PPA_CMD_IFINFO structure -+*/ -+#define PPA_CMD_DEL_LAN_IF _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_LAN_IF_NR, PPA_CMD_IFINFO) -+ -+/** PA Delete WAN Interface Command. It is used to de-register a WAN network interface. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_IFINFO The parameter points to a -+ \ref PPA_CMD_IFINFO structure -+*/ -+#define PPA_CMD_DEL_WAN_IF _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_WAN_IF_NR, PPA_CMD_IFINFO) -+ -+/** PA Get all LAN Interface Information Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_IFINFOS The parameter points to a -+ \ref PPA_CMD_IFINFOS structure -+*/ -+#define PPA_CMD_GET_LAN_IF _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_LAN_IF_NR, PPA_CMD_IFINFOS) -+ -+/** PPA Get all WAN Interface Information Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_IFINFOS The parameter points to a -+ \ref PPA_CMD_IFINFOS structure -+*/ -+#define PPA_CMD_GET_WAN_IF _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_WAN_IF_NR, PPA_CMD_IFINFOS) -+ -+/** PPA Add a Multicast session Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MC_GROUP_INFO The parameter points to a -+ \ref PPA_CMD_MC_GROUP_INFO structure -+*/ -+#define PPA_CMD_ADD_MC _IOR(PPA_IOC_MAGIC, PPA_CMD_ADD_MC_NR, PPA_CMD_MC_GROUP_INFO) -+ -+/** PPA Get a Multicast session Command. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MC_GROUPS_INFO The parameter points to a -+ \ref PPA_CMD_MC_GROUPS_INFO structure -+*/ -+#define PPA_CMD_GET_MC_GROUPS _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MC_GROUPS_NR, PPA_CMD_MC_GROUPS_INFO) -+ -+/** PPA Get LAN accelerated session counter. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_LAN_SESSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_LAN_SESSION_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA PPA Get WAN accelerated session counter. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_WAN_SESSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_WAN_SESSION_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA Get Multicast accelerated session counter. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_MC_GROUP _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_MC_GROUP_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA Get All VLAN filter count. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_VLAN_FILTER _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_VLAN_FILTER_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA PPA Get LAN accelerated session information. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_SESSIONS_INFO The parameter points to a -+ \ref PPA_CMD_SESSIONS_INFO structure -+*/ -+#define PPA_CMD_GET_LAN_SESSIONS _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_LAN_SESSIONS_NR, PPA_CMD_SESSIONS_INFO) -+ -+/** PPA Get WAN accelerated session information. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_SESSIONS_INFO The parameter points to a -+ \ref PPA_CMD_SESSIONS_INFO structure -+*/ -+#define PPA_CMD_GET_WAN_SESSIONS _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_WAN_SESSIONS_NR, PPA_CMD_SESSIONS_INFO) -+ -+/** PPA ADD routing session. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_SESSIONS_DETAIL_INFO The parameter points to a -+ \ref PPA_CMD_SESSIONS_DETAIL_INFO structure -+*/ -+#define PPA_CMD_ADD_SESSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_ADD_SESSION_NR, PPA_CMD_SESSIONS_DETAIL_INFO) -+ -+/** PPA DEL accelerated routing session. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_SESSIONS_INFO The parameter points to a -+ \ref PPA_CMD_SESSIONS_INFO structure -+*/ -+#define PPA_CMD_DEL_SESSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_DEL_SESSION_NR, PPA_CMD_SESSIONS_INFO) -+ -+ -+/** PPA DEL accelerated routing session. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_MODIFY_SESSION The parameter points to a -+ \ref PPA_CMD_MODIFY_SESSION structure -+*/ -+#define PPA_CMD_MODIFY_SESSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_MODIFY_SESSION_NR, PPA_CMD_SESSION_EXTRA_ENTRY) -+ -+/** PPA Set accelerated routing polling timer. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_SET_SESSION_TIMER The parameter points to a -+ \ref PPA_CMD_SET_SESSION_TIMER structure -+*/ -+#define PPA_CMD_SET_SESSION_TIMER _IOWR(PPA_IOC_MAGIC, PPA_CMD_SET_SESSION_TIMER_NR, PPA_CMD_SESSION_TIMER) -+ -+ -+/** PPA Get accelerated routing polling timer. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_GET_SESSION_TIMER The parameter points to a -+ \ref PPA_CMD_GET_SESSION_TIMER structure -+*/ -+#define PPA_CMD_GET_SESSION_TIMER _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_SESSION_TIMER_NR, PPA_CMD_SESSION_TIMER) -+ -+ -+ -+/** PPA Get PPA subsystem version. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_VERSION_INFO The parameter points to a -+ \ref PPA_CMD_VERSION_INFO structure -+*/ -+#define PPA_CMD_GET_VERSION _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_VERSION_NR, PPA_CMD_VERSION_INFO) -+ -+/** PPA Get bridge mac counter. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_MAC _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_MAC_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA Get all mac address value. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_ALL_MAC_INFO The parameter points to a -+ \ref PPA_CMD_ALL_MAC_INFO structure -+*/ -+#define PPA_CMD_GET_ALL_MAC _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_ALL_MAC_NR, PPA_CMD_ALL_MAC_INFO ) -+ -+/** PPA Add VLAN range for WAN interface in mixed mode. Value is manipulated by _IOR() macro for final value -+ \param PPA_VLAN_RANGE The parameter points to a -+ \ref PPA_VLAN_RANGE structure -+*/ -+#define PPA_CMD_WAN_MII0_VLAN_RANGE_ADD _IOR(PPA_IOC_MAGIC, PPA_CMD_WAN_MII0_VLAN_RANGE_ADD_NR, PPA_VLAN_RANGE) -+ -+/** PPA Get VLAN range for WAN interface in mixed mode. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_VLAN_RANGES The parameter points to a -+ \ref PPA_CMD_VLAN_RANGES structure -+*/ -+#define PPA_CMD_WAN_MII0_VLAN_RANGE_GET _IOR(PPA_IOC_MAGIC, PPA_CMD_WAN_MII0_VLAN_RANGE_GET_NR, PPA_CMD_VLAN_RANGES) -+ -+/** PPA Get VLAN range count in mixed mode. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_COUNT_WAN_MII0_VLAN_RANGE _IOWR(PPA_IOC_MAGIC, PPA_CMD_GET_COUNT_WAN_MII0_VLAN_RANGE_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA Get some information entry size. It is for internal usage. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_SIZE_INFO The parameter points to a -+ \ref PPA_CMD_SIZE_INFO structure -+*/ -+#define PPA_CMD_GET_SIZE _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_SIZE_NR, PPA_CMD_SIZE_INFO) -+ -+/** PPA enable/disable ppa bridge mac learning hooks. Value is manipulated by _IOWR() macro for final value -+ \param PPA_CMD_BRIDGE_ENABLE_INFO The parameter points to a -+ \ref PPA_CMD_BRIDGE_ENABLE_INFO structure -+*/ -+#define PPA_CMD_BRIDGE_ENABLE _IOW(PPA_IOC_MAGIC, PPA_CMD_BRIDGE_ENABLE_NR, PPA_CMD_BRIDGE_ENABLE_INFO) -+ -+/** PPA get ppa bridge mac learning hooks enable/disabe status. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_GET_BRIDGE_STATUS The parameter points to a -+ \ref PPA_CMD_GET_BRIDGE_STATUS structure -+*/ -+#define PPA_CMD_GET_BRIDGE_STATUS _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_BRIDGE_STATUS_NR, PPA_CMD_BRIDGE_ENABLE_INFO) -+ -+#ifdef CONFIG_IFX_PPA_QOS -+/** PPA GET QOS status. Value is manipulated by _IOR() macro for final value -+ \param[out] PPA_CMD_QOS_STATUS_INFO The parameter points to a -+ \ref PPA_CMD_QOS_STATUS_INFO structure -+*/ -+#define PPA_CMD_GET_QOS_STATUS _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_QOS_STATUS_NR, PPA_CMD_QOS_STATUS_INFO) -+ -+ -+/** PPA GET the maximum queue supported for WFQ/RateShapping. Value is manipulated by _IOR() macro for final value -+ \param[out] PPA_CMD_QUEUE_NUM_INFO The parameter points to a -+ \ref PPA_CMD_QUEUE_NUM_INFO structure -+ \note: portid is input parameter, and queue_num is output value . -+*/ -+#define PPA_CMD_GET_QOS_QUEUE_MAX_NUM _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_QOS_QUEUE_MAX_NUM_NR, PPA_CMD_QUEUE_NUM_INFO) -+ -+/** PPA GET the QOS mib counter. Value is manipulated by _IOR() macro for final value -+ \param[out] PPA_CMD_QUEUE_NUM_INFO The parameter points to a -+ \ref PPA_CMD_QUEUE_NUM_INFO structure -+ \note: portid is input parameter, and queue_num is output value . -+*/ -+#define PPA_CMD_GET_QOS_MIB _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_QOS_MIB_NR, PPA_CMD_QOS_MIB_INFO) -+ -+ -+ -+#ifdef CONFIG_IFX_PPA_QOS_WFQ -+/** PPA Enable/Disable QOS WFQ feature. Value is manipulated by _IOW() macro for final value -+ \param[in] PPA_CMD_QOS_CTRL_INFO The parameter points to a -+ \ref PPA_CMD_QOS_CTRL_INFO structure -+*/ -+#define PPA_CMD_SET_CTRL_QOS_WFQ _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_CTRL_QOS_WFQ_NR, PPA_CMD_QOS_CTRL_INFO) -+ -+ -+/** PPA get QOS WFQ feature status: enabled or disabled. Value is manipulated by _IOR() macro for final value -+ \param[in] PPA_CMD_QOS_CTRL_INFO The parameter points to a -+ \ref PPA_CMD_QOS_CTRL_INFO structure -+*/ -+#define PPA_CMD_GET_CTRL_QOS_WFQ _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_CTRL_QOS_WFQ_NR, PPA_CMD_QOS_CTRL_INFO) -+ -+/** PPA Set WFQ weight. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_WFQ_INFO The parameter points to a -+ \ref PPA_CMD_WFQ_INFO structure -+*/ -+#define PPA_CMD_SET_QOS_WFQ _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_QOS_WFQ_NR, PPA_CMD_WFQ_INFO) -+ -+/** PPA Get WFQ weight. Value is manipulated by _IOR() macro for final value -+ \param[out] PPA_CMD_WFQ_INFO The parameter points to a -+ \ref PPA_CMD_WFQ_INFO structure -+ \note portid, queueid and weight should be set accordingly. -+*/ -+#define PPA_CMD_GET_QOS_WFQ _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_QOS_WFQ_NR, PPA_CMD_WFQ_INFO) -+ -+/** PPA Reset WFQ weight. Value is manipulated by _IOW() macro for final value -+ \param[out] PPA_CMD_WFQ_INFO The parameter points to a -+ \ref PPA_CMD_WFQ_INFO structure -+ \note: portid/queueid is input parameter, and weight is output value. -+*/ -+#define PPA_CMD_RESET_QOS_WFQ _IOW(PPA_IOC_MAGIC, PPA_CMD_RESET_QOS_WFQ_NR, PPA_CMD_WFQ_INFO) -+ -+#endif //end of CONFIG_IFX_PPA_QOS_WFQ -+ -+#ifdef CONFIG_IFX_PPA_QOS_RATE_SHAPING -+/** PPA Enable/Disable QOS Rate Shaping feature. Value is manipulated by _IOW() macro for final value -+ \param[in] PPA_CMD_QOS_CTRL_INFO The parameter points to a -+ \ref PPA_CMD_QOS_CTRL_INFO structure -+*/ -+#define PPA_CMD_SET_CTRL_QOS_RATE _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_CTRL_QOS_RATE_NR, PPA_CMD_QOS_CTRL_INFO) -+ -+ -+/** PPA get QOS Rate Shaping feature status: enabled or disabled. Value is manipulated by _IOR() macro for final value -+ \param[in] PPA_CMD_QOS_CTRL_INFO The parameter points to a -+ \ref PPA_CMD_QOS_CTRL_INFO structure -+*/ -+#define PPA_CMD_GET_CTRL_QOS_RATE _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_CTRL_QOS_RATE_NR, PPA_CMD_QOS_CTRL_INFO) -+ -+/** PPA Set QOS rate shaping. Value is manipulated by _IOW() macro for final value -+ \param[in] PPA_CMD_RATE_INFO The parameter points to a -+ \ref PPA_CMD_RATE_INFO structure -+*/ -+#define PPA_CMD_SET_QOS_RATE _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_QOS_RATE_NR, PPA_CMD_RATE_INFO) -+ -+/** PPA Get QOS Rate shaping configuration. Value is manipulated by _IOR() macro for final value -+ \param[out] PPA_CMD_RATE_INFO The parameter points to a -+ \ref PPA_CMD_RATE_INFO structure -+ \note portid, queueid and weight should be set accordingly. -+*/ -+#define PPA_CMD_GET_QOS_RATE _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_QOS_RATE_NR, PPA_CMD_RATE_INFO) -+ -+/** PPA Reset QOS Rate shaping. Value is manipulated by _IOW() macro for final value -+ \param[in] PPA_CMD_RATE_INFO The parameter points to a -+ \ref PPA_CMD_RATE_INFO structure -+ \note: portid/queueid is input parameter, and weight is output value. -+*/ -+#define PPA_CMD_RESET_QOS_RATE _IOW(PPA_IOC_MAGIC, PPA_CMD_RESET_QOS_RATE_NR, PPA_CMD_RATE_INFO) -+ -+#endif //end of CONFIG_IFX_PPA_QOS_RATE_SHAPING -+ -+#endif //end of CONFIG_IFX_PPA_QOS -+ -+/** PPA enable multiple field feature. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_ENABLE_MULTIFIELD_INFO The parameter points to a -+ \ref PPA_CMD_ENABLE_MULTIFIELD_INFO structure -+*/ -+#define PPA_CMD_ENABLE_MULTIFIELD _IOW(PPA_IOC_MAGIC, PPA_CMD_ENABLE_MULTIFIELD_NR, PPA_CMD_ENABLE_MULTIFIELD_INFO) -+ -+/** PPA enable multiple field feature. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_ENABLE_MULTIFIELD_INFO The parameter points to a -+ \ref PPA_CMD_ENABLE_MULTIFIELD_INFO structure -+*/ -+#define PPA_CMD_GET_MULTIFIELD_STATUS _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MULTIFIELD_STATUS_NR, PPA_CMD_ENABLE_MULTIFIELD_INFO) -+ -+/** PPA get multiple field max entry number supported. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_MULTIFIELD_ENTRY_MAX _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MULTIFIELD_ENTRY_MAX_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA get multiple field key number suported per compare set. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_MULTIFIELD_KEY_NUM _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MULTIFIELD_KEY_NUM_NR, PPA_CMD_COUNT_INFO) #not use at present -+ -+/** PPA add a multiple field compare set. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MULTIFIELD_FLOW_INFO The parameter points to a -+ \ref PPA_CMD_MULTIFIELD_FLOW_INFO structure -+*/ -+#define PPA_CMD_ADD_MULTIFIELD _IOW(PPA_IOC_MAGIC, PPA_CMD_ADD_MULTIFIELD_NR, PPA_CMD_MULTIFIELD_FLOW_INFO) -+ -+/** PPA get a multiple field flow information. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MULTIFIELD_FLOW_INFO The parameter points to a -+ \ref PPA_CMD_MULTIFIELD_FLOW_INFO structure -+*/ -+#define PPA_CMD_GET_MULTIFIELD _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MULTIFIELD_NR, PPA_CMD_MULTIFIELD_FLOW_INFO) -+ -+/** PPA delete a multiple field compare set according to specified compare key/mask/key_sel information. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MULTIFIELD_FLOW_INFO The parameter points to a -+ \ref PPA_CMD_MULTIFIELD_FLOW_INFO structure -+*/ -+#define PPA_CMD_DEL_MULTIFIELD _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_MULTIFIELD_NR, PPA_CMD_MULTIFIELD_FLOW_INFO) -+ -+/** PPA delete a multiple field compare set according to specified index. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_MULTIFIELD_FLOW_INFO The parameter points to a -+ \ref PPA_CMD_MULTIFIELD_FLOW_INFO structure -+*/ -+#define PPA_CMD_DEL_MULTIFIELD_VIA_INDEX _IOW(PPA_IOC_MAGIC, PPA_CMD_DEL_MULTIFIELD_VIA_INDEX_NR, PPA_CMD_MULTIFIELD_FLOW_INFO) -+ -+ -+/** PPA get all exported hook count. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_GET_HOOK_COUNT _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_HOOK_COUNT_NR, PPA_CMD_COUNT_INFO) -+ -+/** PPA get the exported hook list. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_HOOK_LIST_INFO The parameter points to a -+ \ref PPA_CMD_HOOK_LIST_INFO structure -+*/ -+#define PPA_CMD_GET_HOOK_LIST _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_HOOK_LIST_NR, PPA_CMD_HOOK_LIST_INFO) -+ -+/** PPA to enable/disable the exported hook. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_HOOK_ENABLE_INFO The parameter points to a -+ \ref PPA_CMD_HOOK_ENABLE_INFO structure -+*/ -+#define PPA_CMD_SET_HOOK _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_HOOK_NR, PPA_CMD_HOOK_ENABLE_INFO) -+ -+#ifdef NO_DOXY -+/** PPA get the memory value. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MEM_INFO The parameter points to a -+ \ref PPA_CMD_MEM_INFO structure -+*/ -+#define PPA_CMD_READ_MEM _IOR(PPA_IOC_MAGIC, PPA_CMD_READ_MEM_NR, PPA_CMD_READ_MEM_INFO) -+ -+/** PPA to set the memory value. Value is manipulated by _IOW() macro for final value -+ \param PPA_CMD_COUNT_INFO The parameter points to a -+ \ref PPA_CMD_COUNT_INFO structure -+*/ -+#define PPA_CMD_SET_MEM _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_MEM_NR, PPA_CMD_SET_MEM_INFO) -+#endif -+ -+/** PPA to get the maximum accleration entry number. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MAX_ENTRY_INFO The parameter points to a -+ \ref PPA_CMD_MAX_ENTRY_INFO structure -+*/ -+#define PPA_CMD_GET_MAX_ENTRY _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_MAX_ENTRY_NR, PPA_CMD_MAX_ENTRY_INFO) -+ -+/** PPA to get the port id of one specified interface name. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_MAX_ENTRY_INFO The parameter points to a -+ \ref PPA_CMD_MAX_ENTRY_INFO structure -+*/ -+#define PPA_CMD_GET_PORTID _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_PORTID_NR, PPA_CMD_PORTID_INFO) -+ -+/** PPA Get DSL MIB info. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_GET_DSL_MIB The parameter points to a -+ \ref PPA_CMD_GET_DSL_MIB structure -+*/ -+#define PPA_CMD_GET_DSL_MIB _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_DSL_MIB_NR, PPA_CMD_DSL_MIB_INFO) -+ -+/** PPA Clear DSL MIB info. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_CLEAR_DSL_MIB The parameter points to a -+ \ref PPA_CMD_CLEAR_DSL_MIB structure -+*/ -+#define PPA_CMD_CLEAR_DSL_MIB _IOR(PPA_IOC_MAGIC, PPA_CMD_CLEAR_DSL_MIB_NR, PPA_CMD_DSL_MIB_INFO) -+ -+/** PPA Get PPE port MIB info. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_GET_PORT_MIB The parameter points to a -+ \ref PPA_CMD_GET_PORT_MIB structure -+*/ -+#define PPA_CMD_GET_PORT_MIB _IOR(PPA_IOC_MAGIC, PPA_CMD_GET_PORT_MIB_NR, PPA_CMD_PORT_MIB_INFO) -+ -+/** PPA Clear PORT MIB info. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_CLEAR_PORT_MIB The parameter points to a -+ \ref PPA_CMD_CLEAR_PORT_MIB structure -+*/ -+#define PPA_CMD_CLEAR_PORT_MIB _IOW(PPA_IOC_MAGIC, PPA_CMD_CLEAR_PORT_MIB_NR, PPA_CMD_PORT_MIB_INFO) -+ -+/** PPA Enable/disable HAL debug flag. Value is manipulated by _IOR() macro for final value -+ \param PPA_CMD_SET_HAL_DBG_FLAG The parameter points to a -+ \ref PPA_CMD_SET_HAL_DBG_FLAG structure -+*/ -+#define PPA_CMD_SET_HAL_DBG_FLAG _IOW(PPA_IOC_MAGIC, PPA_CMD_SET_HAL_DBG_FLAG_NR, PPA_CMD_ENABLE_INFO) -+ -+/*@}*/ /* PPA_IOCTL */ -+ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+#ifdef NO_DOXY -+ -+#ifdef CONFIG_IFX_PORT_MIRROR -+ extern struct net_device * (*ifx_get_mirror_netdev)(void); -+ extern uint32_t (*ifx_is_device_type_wireless)(void); -+ #define SKB_MIRROR_FLAG 0x2000 -+#endif -+ -+#define ENUM_STRING(x) #x -+ void ifx_ppa_subsystem_id(uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *); -+ -+ void ifx_ppa_get_api_id(uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *, -+ uint32_t *); -+ -+ int32_t ifx_ppa_is_init(void); -+ -+ int32_t ifx_ppa_init(PPA_INIT_INFO *, uint32_t); -+ void ifx_ppa_exit(void); -+ -+ int32_t ifx_ppa_enable(uint32_t, uint32_t, uint32_t); -+ int32_t ifx_ppa_get_status(uint32_t *, uint32_t *, uint32_t); -+ -+ int32_t ifx_ppa_session_add(PPA_BUF *, PPA_SESSION *, uint32_t); -+ int32_t ifx_ppa_session_delete(PPA_SESSION *, uint32_t); -+ int32_t ifx_ppa_session_modify(PPA_SESSION *, PPA_SESSION_EXTRA *, uint32_t); -+ int32_t ifx_ppa_session_get(PPA_SESSION ***, PPA_SESSION_EXTRA **, int32_t *, uint32_t); -+ -+ int32_t ifx_ppa_mc_group_update(PPA_MC_GROUP *, uint32_t); -+ int32_t ifx_ppa_mc_group_get(IP_ADDR_C, PPA_MC_GROUP *, uint32_t); -+ int32_t ifx_ppa_mc_entry_modify(IP_ADDR_C, PPA_MC_GROUP *, PPA_SESSION_EXTRA *, uint32_t); -+ int32_t ifx_ppa_mc_entry_get(IP_ADDR_C, PPA_SESSION_EXTRA *, uint32_t); -+ int32_t ifx_ppa_multicast_pkt_srcif_add(PPA_BUF *, PPA_NETIF *); -+ -+ int32_t ifx_ppa_inactivity_status(PPA_U_SESSION *); -+ int32_t ifx_ppa_set_session_inactivity(PPA_U_SESSION *, int32_t); -+ -+ int32_t ifx_ppa_bridge_entry_add(uint8_t *, PPA_NETIF *, uint32_t); -+ int32_t ifx_ppa_bridge_entry_delete(uint8_t *, uint32_t); -+ int32_t ifx_ppa_bridge_entry_hit_time(uint8_t *, uint32_t *); -+ int32_t ifx_ppa_bridge_entry_inactivity_status(uint8_t *); -+ int32_t ifx_ppa_set_bridge_entry_timeout(uint8_t *, uint32_t); -+ int32_t ifx_ppa_hook_bridge_enable(uint32_t f_enable, uint32_t flags); -+ int32_t ifx_ppa_hook_get_bridge_status(uint32_t *f_enable, uint32_t flags); -+ -+ int32_t ifx_ppa_set_bridge_if_vlan_config(PPA_NETIF *, PPA_VLAN_TAG_CTRL *, PPA_VLAN_CFG *, uint32_t); -+ int32_t ifx_ppa_get_bridge_if_vlan_config(PPA_NETIF *, PPA_VLAN_TAG_CTRL *, PPA_VLAN_CFG *, uint32_t); -+ int32_t ifx_ppa_vlan_filter_add(PPA_VLAN_MATCH_FIELD *, PPA_VLAN_INFO *, uint32_t); -+ int32_t ifx_ppa_vlan_filter_del(PPA_VLAN_MATCH_FIELD *, PPA_VLAN_INFO *, uint32_t); -+ int32_t ifx_ppa_vlan_filter_get_all(int32_t *, PPA_VLAN_FILTER_CONFIG *, uint32_t); -+ int32_t ifx_ppa_vlan_filter_del_all(uint32_t); -+ -+ int32_t ifx_ppa_get_if_stats(PPA_IFNAME *, PPA_IF_STATS *, uint32_t); -+ int32_t ifx_ppa_get_accel_stats(PPA_IFNAME *, PPA_ACCEL_STATS *, uint32_t); -+ -+ int32_t ifx_ppa_set_if_mac_address(PPA_IFNAME *, uint8_t *, uint32_t); -+ int32_t ifx_ppa_get_if_mac_address(PPA_IFNAME *, uint8_t *, uint32_t); -+ -+ int32_t ifx_ppa_add_if(PPA_IFINFO *, uint32_t); -+ int32_t ifx_ppa_del_if(PPA_IFINFO *, uint32_t); -+ int32_t ifx_ppa_get_if(int32_t *, PPA_IFINFO **, uint32_t); -+ -+ int32_t ifx_ppa_hook_wan_mii0_vlan_range_add(PPA_VLAN_RANGE *, uint32_t); -+ int32_t ifx_ppa_hook_wan_mii0_vlan_range_del(PPA_VLAN_RANGE *, int32_t); -+ int32_t ifx_ppa_hook_wan_mii0_vlan_ranges_get(int32_t *, PPA_VLAN_RANGE *, uint32_t); -+ -+ int32_t ifx_ppa_get_max_entries(PPA_MAX_ENTRY_INFO *max_entry, uint32_t flags); -+ int32_t ppa_ip_comare( PPA_IPADDR ip1, PPA_IPADDR ip2, uint32_t flag ); -+ int32_t ppa_zero_ip( PPA_IPADDR ip); -+ int32_t ppa_ip_sprintf( char *buf, PPA_IPADDR ip, uint32_t flag); -+ extern uint32_t g_ppa_ppa_mtu; -+ extern uint32_t g_ppa_min_hits; -+#endif //NO_DOXY -+ -+#endif //end of __KERNEL__ -+ -+#ifdef __KERNEL__ -+ #include <net/ifx_ppa_hook.h> -+#endif -+ -+ -+#endif // __IFX_PPA_API_H__20081031_1913__ -+ -diff --git a/include/net/ifx_ppa_api_common.h b/include/net/ifx_ppa_api_common.h -new file mode 100644 -index 0000000..5ede8b4 ---- /dev/null -+++ b/include/net/ifx_ppa_api_common.h -@@ -0,0 +1,47 @@ -+#ifndef __IFX_PPA_API_COMMON_H__20100203__1740__ -+#define __IFX_PPA_API_COMMON_H__20100203__1740__ -+ -+/******************************************************************************* -+** -+** FILE NAME : ifx_ppa_api_common.h -+** PROJECT : PPA -+** MODULES : PPA Common header file -+** -+** DATE : 3 NOV 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA Common Header File -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 03 NOV 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+ -+#define NO_DOXY 1 -+ -+#ifndef CONFIG_IFX_PPA_DSLITE //if not defined in kernel's .configure file, then use local's definition -+#define CONFIG_IFX_PPA_DSLITE 1 -+#endif -+ -+#ifndef CONFIG_IFX_PPA_MFE //if not defined in kernel's .configure file, then use local's definition -+#define CONFIG_IFX_PPA_MFE 0 -+#endif -+ -+ /*force dynamic ppe driver's module parameter */ -+#define IFX_PPA_DP_DBG_PARAM_ENABLE 1 //for PPA automation purpose. for non-linux os porting, just disable it -+ -+#if IFX_PPA_DP_DBG_PARAM_ENABLE -+ extern int ifx_ppa_drv_dp_dbg_param_enable; -+ extern int ifx_ppa_drv_dp_dbg_param_ethwan; -+ extern int ifx_ppa_drv_dp_dbg_param_wanitf; -+ extern int ifx_ppa_drv_dp_dbg_param_ipv6_acc_en; -+ extern int ifx_ppa_drv_dp_dbg_param_wanqos_en; -+#endif // end of IFX_PPA_DP_DBG_PARAM_ENABLE -+ -+#endif -+ -diff --git a/include/net/ifx_ppa_api_directpath.h b/include/net/ifx_ppa_api_directpath.h -new file mode 100644 -index 0000000..919342d ---- /dev/null -+++ b/include/net/ifx_ppa_api_directpath.h -@@ -0,0 +1,301 @@ -+#ifndef __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ -+#define __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ -+ -+ -+ -+/******************************************************************************* -+** -+** FILE NAME : ifx_ppa_api_directpath.h -+** PROJECT : PPA -+** MODULES : PPA API (Routing/Bridging Acceleration APIs) -+** -+** DATE : 19 NOV 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA Protocol Stack Hook API Directpath Functions Header -+** File -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 19 NOV 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+/*! \file ifx_ppa_api_directpath.h -+ \brief This file contains: PPA direct path api. -+*/ -+ -+ -+ -+#include <net/ifx_ppa_api_common.h> -+ -+ -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/* -+ * Directpath API Flags -+ */ -+/*! -+ \brief PPA_F_DIRECTPATH_REGISTER -+*/ -+#define PPA_F_DIRECTPATH_REGISTER 0x00100000 /*!< Directpath register flag*/ -+ -+/*! -+ \brief PPA_F_DIRECTPATH_CORE1 -+*/ -+#define PPA_F_DIRECTPATH_CORE1 0x00200000 /*!< Directpath flag: run in CPU Core 1*/ -+/*! -+ \brief PPA_F_DIRECTPATH_ETH_IF -+*/ -+#define PPA_F_DIRECTPATH_ETH_IF 0x00400000 /*!< Directpath flag: Ethernet type*/ -+ -+/* -+ * Directpath Internal Flags -+ */ -+ /*! -+ \brief PPE_DIRECTPATH_DATA_ENTRY_VALID -+*/ -+#define PPE_DIRECTPATH_DATA_ENTRY_VALID (1 << 31) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_DATA_RX_ENABLE -+*/ -+#define PPE_DIRECTPATH_DATA_RX_ENABLE (1 << 0) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_ETH -+*/ -+#define PPE_DIRECTPATH_ETH (1 << 4) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_CORE0 -+*/ -+#define PPE_DIRECTPATH_CORE0 (1 << 8) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_CORE1 -+*/ -+#define PPE_DIRECTPATH_CORE1 (1 << 9) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_ITF_TYPE_MASK -+*/ -+#define PPE_DIRECTPATH_ITF_TYPE_MASK (PPE_DIRECTPATH_ETH) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_CORE_MASK -+*/ -+#define PPE_DIRECTPATH_CORE_MASK (PPE_DIRECTPATH_CORE0 | PPE_DIRECTPATH_CORE1) /*!< define flag */ -+ /*! -+ \brief PPE_DIRECTPATH_MASK -+*/ -+#define PPE_DIRECTPATH_MASK (PPE_DIRECTPATH_ITF_TYPE_MASK | PPE_DIRECTPATH_CORE_MASK) /*!< define flag */ -+ -+ -+/** \addtogroup PPA_API_DIRECTPATH */ -+/*@{*/ -+/*! \fn PPA_FP_STOP_TX_FN -+ \brief This is the definition for the PPA DirectPath Stop Transmit function callback used for flow control when transmitting -+ packets through the PPA DirectPath. The PPA DirectPath calls this hook to indicate to the device driver that it -+ cannot receive any more packets for transmission. -+ \param[in] dev The protocol stack network interface structure on which to signal Stop Tx for flow control -+ \return The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error if the driver cannot handle flow control -+ \note This function must be provided by the CPU-bound interface driver and will be called by the PPA Directpath to pass -+ on frames directly to the driver for transmitting out of its interface. -+*/ -+typedef int32_t (*PPA_FP_STOP_TX_FN)(PPA_NETIF *dev); -+ -+/*! \fn PPA_FP_RESTART_TX_FN -+ \brief This is the definition for the PPA DirectPath Restart Transmit function callback used for flow control when -+ transmitting packets through the PPA DirectPath. The PPA DirectPath calls this hook to indicate to the device -+ driver that it is ready to receive packets for transmission after having asserted stop flow control using -+ PPA_FP_STOP_TX_FN. -+ \param[in] dev The protocol stack network interface structure on which to signal restart Tx for flow control. -+ \return The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error if the driver cannot handle flow control -+ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet -+ processing. This callback must always be used in conjunction with the PPA_FP_STOP_TX_FN callback, i.e., -+ either both callbacks or none must be configure -+*/ -+typedef int32_t (*PPA_FP_RESTART_TX_FN)(PPA_NETIF *dev); -+/*! \fn PPA_FP_RX_FN -+ \brief This is the definition for the PPA DirectPath receive function callback that passes packet from PPA DirectPath to -+ the CPU bound driver. This callback is registered for the device with the PPA module by the device driver. This is required to allow the PPA acceleration layer to directly pass packets to the relevant device driver bypassing the protocol stack. It is also the only way for the PPA to deliver packets to drivers running on Core 1. -+ The packet buffer passed to the rx_fn callback will have the data pointer point to the start of Link layer header (i.e. Ethernet header). For eg., on Linux, skb->data will point to the Ethernet header. -+ \param[in] rxif PPA Receive interface pointer on which the packet is received. -+ \param[in] txif PPA Tx interface pointer to which the packet is transmitted. -+ \param[in] skb Pointer to SKB buffer received. -+ \param[in] len Length of packet frame. -+ \return The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess. \n -+ IFX_FAILURE on error if the driver process the packet for some reason. -+ \note This function must be provided by the CPU-bound interface driver and will be called by the PPA Directpath to pass on frames directly to the driver for transmitting out of its interface. -+*/ -+typedef int32_t (*PPA_FP_RX_FN)(PPA_NETIF *rxif, PPA_NETIF *txif, PPA_BUF *skb, int32_t len); -+ -+/*@}*/ /*PPA_API_DIRECTPATH */ -+ -+ -+/** \addtogroup PPA_API_DIRECTPATH */ -+/*@{*/ -+ -+/*! -+ \brief This is the data structure for the PPA DirectPath device registration which provides the necessary callback -+ registration for receiving packets from PPA DirectPath to the driver for transmit, and for flow control to be asserted -+ by the PPA DirectPath for packets from the driver to the PPA DirectPath. -+*/ -+typedef struct { -+ PPA_FP_STOP_TX_FN stop_tx_fn; /*!< Pointer to the Driver Stop Tx function callback. Providing a NULL pointer disables the callback functionality. */ -+ PPA_FP_RESTART_TX_FN start_tx_fn; /*!< Pointer to the Driver Restart Tx function callback. Providing a NULL pointer disables the callback functionality.*/ -+ PPA_FP_RX_FN rx_fn; /*!< Device Receive Function callback for packets. Setting a value of NULL pointer disables Receive callback for the device */ -+} PPA_DIRECTPATH_CB; -+ -+/* -+ * Internal Structure of directpath -+ */ -+/*! -+ \brief This is the data structure for the PPA DirectPath device status -+*/ -+struct ppe_directpath_data { -+ PPA_DIRECTPATH_CB callback; /*!< Callback Pointer to PPA_DIRECTPATH_CB */ -+ PPA_NETIF *netif; /*!< pointer to PPA_NETIF*/ -+ uint32_t ifid; /*!< directpath interface id */ -+ uint8_t mac[(PPA_ETH_ALEN + sizeof(uint32_t) - 1) / sizeof(uint32_t) * sizeof(uint32_t)]; /*!< interface mac address */ -+ PPA_BUF *skb_list; /*!< the directpath interface's skb list */ -+ uint32_t skb_list_len; /*!< the skb list length */ -+ uint32_t skb_list_size; /*!< the skb list size */ -+ uint32_t rx_fn_rxif_pkt; /*!< received packet counter */ -+ uint32_t rx_fn_txif_pkt; /*!< transmitted packet coutner */ -+ uint32_t tx_pkt; /*!< transmitted packet counter */ -+ uint32_t tx_pkt_dropped; /*!< dropped packet counter */ -+ uint32_t tx_pkt_queued; /*!< queued packet counter */ -+ uint32_t flags; /*!< bit 0 - directpath send valid, 31 - entry valid */ -+}; -+ -+ -+/*@}*/ /* PPA_API_DIRECTPATH */ -+ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+#ifdef NO_DOXY -+extern struct ppe_directpath_data g_ppe_directpath_data[]; -+#endif -+ -+/** \addtogroup PPA_API_DIRECTPATH */ -+/*@{*/ -+#ifdef CONFIG_IFX_PPA_API_DIRECTPATH -+/*! -+ \brief This function allows a device driver to register or deregister a network device to the PPA. -+ \param[out] if_id PPA specific Interface Identifier. It is currently a number between 0 to 7. This Id is returned by the PPA module. -+ \param[in] dev Pointer to the network device structure in the protocol stack. For e.g. pointer to a struct netdevice. -+ \param[in] pDirectpathCb Pointer to the DirectPath callback structure which provides the driver callbacks for rx_fn, stop_tx_fn and restart_tx_fn. This parameter is only available on new PPA API. -+ \param[in] flags Flag to indicate if device is being registered or deregistered. Valid values are:\n -+ - PPA_F_DIRECTPATH_DEREGISTER, if de-registering, zero otherwise \n -+ - PPA_F_DIRECTPATH_CORE1 if the driver for the network interface is running on Core 1 (i.e. 2nd CPU) \n -+ - PPA_F_DIRECTPATH_ETH_IF if the network interface is an Ethernet-like interface -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE -+ \note -+*/ -+int32_t ifx_ppa_directpath_register_dev(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); -+ -+/*! \brief This function allows the device driver to transmit a packet using the PPA DirectPath interface. The packet buffer passed to the function must have its "packet data" pointer set to the IP header with the Ethernet header/Link layer header etc. preceding the IP header (For e.g., on Linux skb->data points to IP header, and doing the appropriate skb_push() will allow skb->data to move backwards and point to Ethernet header). In other words, PPA Directpath must be able to access the full frame even though the packet buffer "points" to the IP header as required by the Linux netif_rx() function. -+ \param[in] rx_if_id Receive interface Id in the protocol stack. -+ \param[in] buf Pointer to the packet buffer structure of the stack for the packet which is to be transmitted. -+ \param[in] len Size of packet in bytes. -+ \param[in] flags Currently Reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE -+ \note The DirectPath Tx API can have internal "shortcut" path to the destination or fallback to passing the packet to the protocol stack. The aim is to insulate the device driver calling the API from such details. For Linux, the driver must call this function through the hook pointer where it passes packets to the network stack by calling the "netif_rx()" or "netif_receive_skb()" functions. \n -+ Note: The CPU-bound device driver is strongly recommended to call this API from tasklet mode (or equivalent non-interrupt context on non-Linux OS) and not from IRQ context for better system dynamics. -+*/ -+ int32_t ifx_ppa_directpath_send(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); -+ -+/*! \brief This function allows the device driver to indicate to the PPA that it cannot receive any further packets from the latter. The device driver can call this function for flow control. -+ \param[in] if_id Interface Id for which to apply flow control. -+ \param[in] flags Currently Reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE -+ \note \n -+*/ -+ int32_t ifx_ppa_directpath_rx_stop(uint32_t if_id, uint32_t flags); -+ -+/*! \brief This function allows the device driver to indicate to the PPA that it can again receive packets from the latter. The device driver can call this function for flow control after it has called the "Rx Stop" function to halt supply of packets from the PPA. -+ \param[in] if_id Interface Id for which the driver requests the flow control action to restart transmission. -+ \param[in] flags Currently Reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE -+ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. This function must be used in conjunction with the PPA_FP_STOP_TX_FN. \n -+*/ -+ int32_t ifx_ppa_directpath_rx_restart(uint32_t if_id, uint32_t flags); -+ -+/*! \brief This function maps the PPA Interface Id to Protocol stack interface structure. -+ \param[in] if_id PPA Interface Identifier. -+ \return The return value can be any one of the following: \n -+ - Pointer to the interface structure in the protocol stack \n -+ - NULL -+ \note This API may not implemented on older PPA version. \n -+*/ -+ PPA_NETIF *ifx_ppa_get_netif_for_ppa_ifid(uint32_t if_id); -+ -+/*! \brief This function maps the Protocol stack interface structure to the PPA Interface Id. -+ \param[in] dev Pointer to the protocol stack network interface structure for the device. -+ \return The return value can be any one of the following: \n -+ - PPA Interface Identifier, if_id \n -+ - IFX_FAILUREPPA_NETIF. \n -+ \note This API may not implemented on older PPA version. \n -+*/ -+ int32_t ifx_ppa_get_ifid_for_netif(PPA_NETIF *dev); -+ -+/*! \brief This function is used to initialize the interation of ppe_directpath_data information -+ \param[in,out] ppos offset of current ppe_directpath_data, after call, its value will be changed to next offset -+ \param[out] info Buffer to store the ppe_directpath_data. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS, if succeed \n -+ - IFX_FAILURE, if fail to get \n -+*/ -+ int32_t ppa_directpath_data_start_iteration(uint32_t *ppos, struct ppe_directpath_data **info); -+ -+/*! \brief This function is used to ge the next ppe_directpath_data information during its iteration -+ \param[in,out] ppos offset of ppe_directpath_data, after call, its value will be changed to next offset -+ \param[out] info Buffer to store the ppe_directpath_data. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS, if succeed \n -+ - IFX_FAILURE, if fail to get \n -+*/ -+ int32_t ppa_directpath_data_iterate_next(uint32_t *ppos, struct ppe_directpath_data **info); -+ -+/*! \brief This function is used to stop ppe_directpath_data iteration -+ \return NULL -+*/ -+ void ppa_directpath_data_stop_iteration(void); -+ -+ /*! \brief This function is used to get directpath's ifid range -+ \param[out] p_start_ifid Buffer to store the directpath's start ifid -+ \param[out] p_end_ifid Buffer to store the directpath's end ifid -+ \return NULL\n -+*/ -+ void ppa_directpath_get_ifid_range(uint32_t *p_start_ifid, uint32_t *p_end_ifid); -+#endif -+ -+/* @}*/ /* PPA_API_DIRECTPATH */ -+ -+#endif // __IFX_PPA_API_DIRECTPATH_H__20081119_1144__ -diff --git a/include/net/ifx_ppa_hook.h b/include/net/ifx_ppa_hook.h -new file mode 100644 -index 0000000..41a9278 ---- /dev/null -+++ b/include/net/ifx_ppa_hook.h -@@ -0,0 +1,1150 @@ -+#ifndef __IFX_PPA_HOOK_H__20081103_1736__ -+#define __IFX_PPA_HOOK_H__20081103_1736__ -+ -+ -+ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ppa_hook.h -+** PROJECT : PPA -+** MODULES : PPA Protocol Stack Hooks -+** -+** DATE : 3 NOV 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA Protocol Stack Hook Pointers Header File -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 03 NOV 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+/*! \file ifx_ppa_hook.h -+ \brief This file contains all exported HOOK API to linux Kernel and user space via ioctl API. -+*/ -+ -+ -+ -+#include <net/ifx_ppa_api_common.h> -+ -+/** \addtogroup PPA_HOOK_API */ -+/*@{*/ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ -+ -+/*! -+ \brief This command Initialize the PPA module and the embedded acceleration functions. -+ \param[in] info Pointer to the initialization info structure passed to the API. -+ \param[in] flag Reserved currently. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+ \note p_info can be passed NULL to the init function wherein default handling will be applied by the PPA. This includes the following behavior. \n -+ - Identifying one LAN interface (eth0) and one WAN interface (eth1) \n -+ - Disabling acceleration in both LAN to WAN and WAN to LAN directions \n -+ - IP header verification enabled \n -+ - TCP/UDP header verification enabled \n -+ - Drop on no hit disabled - pass packets on matching any accelerated session entry to Control CPU \n -+ - Drop Multicast packet on no hit disable \n -+ Please refer to the PPA_INIT_INFO data structure and its members for all the information that is passed to the PPA module on initialization. -+ Specifically, the LAN and WAN interface list can be populated with all possible interfaces of either type expected in the system even if these interfaces don't exist at the time of initialization. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_init_fn)(PPA_INIT_INFO *info, uint32_t flag); -+#else -+extern int32_t ppa_hook_init_fn(PPA_INIT_INFO *info, uint32_t flag); -+#endif -+/*! -+ \brief This command un-Initialize the PPA module -+ \return void -+*/ -+#ifdef NO_DOXY -+extern void (*ppa_hook_exit_fn)(void); -+#else -+extern void ppa_hook_exit_fn(void); -+#endif -+ -+/*! -+ \brief This API exposes the PPA Enable / Disable API to userspace. -+ \param[in] lan_rx_ppa_enable Enable / Disable accelerated LAN to WAN path through PPA. \n -+ Valid values are:\n -+ IFX_ENABLED \n -+ IFX_DISABLED \n -+ \param[in] wan_rx_ppa_enable Enable / Disable accelerated WAN to LAN path through PPA. \n -+ Valid values are:\n -+ - IFX_ENABLED \n -+ - IFX_DISABLED \n -+ \param[in] flag Reserved currently. -+ -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+ \note The LAN to WAN and WAN to LAN separate acceleration disable feature is a function of the acceleration module in the system. In some cases, it maybe only possible to complete disable / enable acceleration. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_enable_fn)(uint32_t lan_rx_ppa_enable, uint32_t wan_rx_ppa_enable, uint32_t flag); -+#else -+extern int32_t ppa_hook_enable_fn(uint32_t lan_rx_ppa_enable, uint32_t wan_rx_ppa_enable, uint32_t flag); -+#endif -+/*! -+ \brief This API returns the current Enable / Disable status of the PPA to the caller. -+ \param[out] lan_rx_ppa_enable Enable / Disable accelerated LAN to WAN path through PPA. \n -+ Valid values are -+ IFX_ENABLED \n -+ IFX_DISABLED \n -+ \param[out] wan_rx_ppa_enable Enable / Disable accelerated WAN to LAN path through PPA. \n -+ Valid values are -+ - IFX_ENABLED \n -+ - IFX_DISABLED \n -+ \param[in] flag Reserved currently. -+ -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+ \note This parameter is not available on older PPA version. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_status_fn)(uint32_t *lan_rx_ppa_enable, uint32_t *wan_rx_ppa_enable, uint32_t flag); -+#else -+extern int32_t ppa_hook_get_status_fn(uint32_t *lan_rx_ppa_enable, uint32_t *wan_rx_ppa_enable, uint32_t flag); -+#endif -+/*! -+ \brief Add a PPA routing session entry -+ \param[in] skb Pointer to the packet buffer for which PPA session addition is to be done. -+ \param[in] p_session Points to the connection tracking session to which this packet belongs. It maybe passed as NULL in which case PPA will try to determine it using the PPA stack adaptation layer. -+ \param[in] flags Flags as valid for the PPA session Valid \n -+ values are one or more of: \n -+ - PPA_F_SESSION_BIDIRECTIONAL \n -+ - PPA_F_BRIDGED_SESSION \n -+ - PPA_F_STATIC_ENTRY \n -+ - PPA_F_DROP_PACKET \n -+ - PPA_F_SESSION_ORG_DIR \n -+ - PPA_F_SESSION_REPLY_DIR \n -+ - PPA_F_BEFORE_NAT_TRANSFORM \n -+ \return The return value can be any one of the following: \n -+ - IFX_PPA_SESSION_NOT_ADDED \n -+ - IFX_PPA_SESSION_ADDED \n -+ - IFX_PPA_SESSION_EXISTS \n -+ -+ \note Linux 2.4 Hook-up recommendation \n -+ Must be hooked into the stack before the PREROUTING and after the POSTROUTING hooks In ip_conntrack_in() function in file ip_conntrack_core.c, with the flag PPA_F_BEFORE_NAT_TRANSFORM specified. \n -+ 1) In ip_finish_output2(), the hook should be invoked after NAT transforms are applied and at the very beginning of function call. \n -+ Linux 2.6 Hook-up recommendation \n -+ Must be in netfilter IPV4 or IPV6 hook PREROUTRING and POSTROUTING hooks. In nf_conntrack_in for function which is common for both IPV4 and V6 connection tracking, PPA_F_BEFORE_NAT_TRANSFORM. In ip_finish_output2(), the hook should be invoked after NAT transforms are applied at netfilter POSTROUTING hooks and at the very beginning of function call. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_session_add_fn)(PPA_BUF *skb, PPA_SESSION *p_session, uint32_t flags); -+#else -+extern int32_t ppa_hook_session_add_fn(PPA_BUF *skb, PPA_SESSION *p_session, uint32_t flags); -+#endif -+ -+/*! -+ \brief Del a PPA routing session entry -+ \param[in] p_session Points to the connection tracking session to which this packet belongs. It maybe passed as NULL in which case PPA will try to determine it using the PPA stack adaptation layer. -+ \param[in] flags Reserved currently. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_session_del_fn)(PPA_SESSION *p_session, uint32_t flags); -+#else -+extern int32_t ppa_hook_session_del_fn(PPA_SESSION *p_session, uint32_t flags); -+#endif -+ -+/*! -+ \brief Modify an existing PPA session to allow handling for additional features like VLAN, DSCP and others. -+ \param[in] p_session PPA session id -+ \param[in] p_extra Extra parameters of PPA session -+ \param[in] flags Flags passed to modify session API to indicate which processing parameters are specified. Valid values are one or more of: -+ - PPA_F_SESSION_NEW_DSCP \n -+ - PPA_F_SESSION_VLAN \n -+ - PPA_F_MTU \n -+ -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE \n -+ \note Linux 2.4 Hook-up recommendation \n -+ - Called in the stack on a per session basis to set additional handling like VLAN, DSCP and MTU parameters. \n -+ - One place to hook the call is after the function ppa_hook_session_add_fn() returns IFX_PPA_SESSION_ADDED. \n -+ - Needs to evaluate the settings for VLAN, DSCP, MTU etc which are required to be used for this session. These steps need to be written for the stack and supported functionality. \n -+ - Another place for hookup is in the Configuration routines of the individual features \n -+ - For example, for a VLAN configuration, go through the list of conntrack sessions, and call ppa_hook_session_modify_fn() for each session that is impacted by the change in configuration. \n -+ - If this step is not supported, then only sessions created after the configuration change will be affected. -+ \note Linux 2.6 Hook-up recommendation \n -+ Same as 2.4. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_session_modify_fn)(PPA_SESSION *p_session, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#else -+extern int32_t ppa_hook_session_modify_fn(PPA_SESSION *p_session, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#endif -+ -+/*! -+ \brief Returns all the configured unicast PPA sessions -+ \param[out] pp_sessions Allocates and returns a pointer to an array of session data structures for all unicast sessions in PPA. \n Caller needs to free the memory after use. -+ \param[out] p_extra Allocates and returns a pointer to an array of session attributes structures for all unicast sessions in PPA.\n Caller needs to free the memory after use. -+ \param[out] p_num_entries Returns the number of session entries filled in the pp_sessions and pp_extra arrays. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_session_get_fn)(PPA_SESSION ***pp_sessions, PPA_SESSION_EXTRA **p_extra, int32_t *p_num_entries, uint32_t flags); -+#else -+extern int32_t ppa_hook_session_get_fn(PPA_SESSION ***pp_sessions, PPA_SESSION_EXTRA **p_extra, int32_t *p_num_entries, uint32_t flags); -+#endif -+ -+/*! -+ \brief Add, Modify and Delete PPA multicast group information like membership of interfaces to a multicast group address. -+ \param[in] ppa_mc_entry Pointer to multicast group entry. I -+ \param[in] flags Flags for the multicast group update operation. Valid values are:\n -+ PPA_F_DROP_PACKET: Drop packets with this multicast group address as destination. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE \n -+ -+ \note add or delete one or more interface(s) to a multicast group entry, the function ppa_hook_mc_group_update_fn() needs to be called, the PPA_MC_GROUP structure modified appropriately and passed to this function. \n -+ -> Linux 2.4 Hook-up recommendation \n -+ The function needs to be hooked up in the Linux kernel functions ipmr_mfc_add() and ipmr_mfc_del() in the IP stack multicast routing path. \n -+ For bridging path, hookup is required in the bridge forwarding path if IGMP snooping is implemented. It is also possible to make configuration entries from management interface path. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_mc_group_update_fn)(PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); -+#else -+extern int32_t ppa_hook_mc_group_update_fn(PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function gets the multicast group entry for the specified multicast group address. -+ \param[in] ip_mc_group IP multicast group address for which Multicast group information has to be returned. -+ \param[out] ppa_mc_entry Pointer to multicast group entry. Valid memory space to be passed by caller. -+ \param[in] flags Reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_mc_group_get_fn)(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); -+#else -+extern int32_t ppa_hook_mc_group_get_fn(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function modifies an existing multicast group entry for additional functionality like VLAN support -+ \param[in] ip_mc_group Pointer to IP multicast group address for which additional functionality needs to be configured. -+ \param[in] ppa_mc_entry Pointer to PPA MC group entry. -+ \param[in] p_extra Pointer to additional MC entry functional configuration. Currently, only VLAN configuration is supported -+ \param[in] flags Reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS if entry exists for multicast group address \n -+ - IFX_FAILURE otherwise \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_mc_entry_modify_fn)(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#else -+extern int32_t ppa_hook_mc_entry_modify_fn(IP_ADDR_C ip_mc_group, PPA_MC_GROUP *ppa_mc_entry, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function returns an existing multicast group entry with its additional functionality configuration like VLAN support. -+ \param[in] ip_mc_group Pointer to IP multicast group address for which additional functionality needs to be configured. -+ \param[in] p_extra Pointer to additional MC entry functional configuration. Currently, only VLAN configuration is supported -+ \param[in] flags Reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS if entry exists for multicast group address \n -+ - IFX_FAILURE otherwise \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_mc_entry_get_fn)(IP_ADDR_C ip_mc_group, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#else -+extern int32_t ppa_hook_mc_entry_get_fn(IP_ADDR_C ip_mc_group, PPA_SESSION_EXTRA *p_extra, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function is used to get a multicast source interface -+ \param[in] buf A skb buffer -+ \param[in] netif The interface pointer which received the ip packet. If NULL, it can be got from PPA_BUF *. -+ -+ \return The return value can be any one of the following: \n -+ - IFX_PPA_SESSION_ADDED if if entry exists for multicast group address \n -+ - IFX_PPA_SESSION_EXISTS if already added -+ - IFX_PPA_SESSION_NOT_ADDED otherwise \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_multicast_pkt_srcif_add_fn)(PPA_BUF *buf, PPA_NETIF *netif); -+#else -+extern int32_t ppa_hook_multicast_pkt_srcif_add_fn(PPA_BUF *buf, PPA_NETIF *netif); -+#endif -+ -+/*! -+ \brief Checks if the "accelerated" PPA session should be timed out due to inactivity. -+ \param[in] p_session Pointer to PPA unicast or multicast session. -+ \return The return value can be any one of the following: \n -+ - IFX_TIMEOUT if the PPA session inactivity timer has expired \n -+ - IFX_HIT if the PPA session has been active -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_inactivity_status_fn)(PPA_U_SESSION *p_session); -+#else -+extern int32_t ppa_hook_inactivity_status_fn(PPA_U_SESSION *p_session); -+#endif -+ -+/*! -+ \brief Update the session inactivity timeout for a PPA session as per the session inactivity configuration in the protocol stack. -+ \param[in] p_session Pointer to PPA unicast or multicast session. -+ \param[in] timeout Timeout value for session inactivity in seconds. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_set_inactivity_fn)(PPA_U_SESSION *p_session, int32_t timeout); -+#else -+extern int32_t ppa_hook_set_inactivity_fn(PPA_U_SESSION *p_session, int32_t timeout); -+#endif -+ -+/*! -+ \brief Add or update a MAC entry and its source ethernet port information in the PPA bridge table. -+ \param[in] mac_addr Pointer to MAC address to add to PPA bridge table. -+ \param[in] netif Pointer to PPA net interface which is the source of the MAC address. -+ \param[in] flags Valid values are: -+ - PPA_F_BRIDGE_LOCAL - traffic is destined for local termination. -+ - PPA_F_STATIC_ENTRY - static MAC address entry in the PPA bridge table. It will not be aged out. -+ - PPA_F_DROP_PACKET - firewall action. Always drop packets with this MAC destination. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE \n -+ \note Static MAC entry updates and MAC address drop filters can be configured from userspace. For dynamic entries, the function must be hooked from bridging code where new entries are inserted into bridge mac table (or forwarding database, fdb). -+ Linux 2.4 Hook-up recommendation \n -+ Hook in kernel function br_fdb_insert() in net/bridge/br_fdb.c. For Linux bridging code, the netif is given by fdb->dst->dev field where fdb points to a MAC entry. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_bridge_entry_add_fn)(uint8_t *mac_addr, PPA_NETIF *netif, uint32_t flags); -+#else -+extern int32_t ppa_hook_bridge_entry_add_fn(uint8_t *mac_addr, PPA_NETIF *netif, uint32_t flags); -+#endif -+ -+/*! -+ \brief Delete a MAC entry from PPA Bridge table since the MAC entry is aged out or administratively triggered. -+ \param[in] mac_addr Pointer to MAC address to delete from PPA bridge table. -+ \param[in] flags Reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_bridge_entry_delete_fn)(uint8_t *mac_addr, uint32_t flags); -+#else -+extern int32_t ppa_hook_bridge_entry_delete_fn(uint8_t *mac_addr, uint32_t flags); -+#endif -+ -+/*! -+ \brief Get latest packet arriving time for the specified MAC address entry. This is used for aging out decisions for the MAC entry. -+ \param[in] mac_addr Pointer to MAC address whose entry hit time is being queried -+ \param[out] p_hit_time Provides the latest packet arriving time in seconds from system bootup. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS \n -+ - IFX_FAILURE -+ \note Linux 2.4 Hook-up recommendation \n -+ This API can be hooked in function br_fdb_cleanup(). In Linux, there is a kernel thread (br_fdb_cleanup) polling each entry in the MAC table and removes entries without traffic for a long time. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_bridge_entry_hit_time_fn)(uint8_t *mac_addr, uint32_t *p_hit_time); -+#else -+extern int32_t ppa_hook_bridge_entry_hit_time_fn(uint8_t *mac_addr, uint32_t *p_hit_time); -+#endif -+ -+/*! -+ \brief Check if a PPA Bridge entry should be aged out due to inactivity as per the aging time configured by function \ref ppa_hook_set_bridge_entry_timeout_fn. -+ \param[in] mac_addr Pointer to MAC address whose entry hit time is being queried -+ \return The return value can be any one of the following: \n -+ - IFX_PPA_TIMEOUT if entry should be aged out \n -+ - IFX_PPA_HIT if entry should not be aged out -+ \note Linux 2.4 Hook-up recommendation \n -+ This API can be hooked in function has_expired() in br_fdb.c. \n -+ Note that the function pair of ppa_hook_bridge_entry_inactivity_status_fn and ppa_hook_set_bridge_entry_timeout_fn is an alternate aging mechanism to the use of function ppa_hook_bridge_entry_hit_time_fn. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_bridge_entry_inactivity_status_fn)(uint8_t *mac_addr); -+#else -+extern int32_t ppa_hook_bridge_entry_inactivity_status_fn(uint8_t *mac_addr); -+#endif -+ -+/*! -+ \brief Set the PPA bridge entry inactivity timeout in seconds. -+ \param[in] mac_addr Pointer to MAC address whose entry hit time is being set -+ \param[in] timeout Timeout in seconds for inactivity timeout. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+ \note This function should be called immediately after ppa_hook_bridge_entry_add_fn() and whenever timeout needs to be changed by bridge stack. \n -+ Linux 2.4 Hook-up recommendation \n For Linux, the timeout is equal to the bridge aging time and can be called from the function br_fdb_insert(). -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_set_bridge_entry_timeout_fn)(uint8_t *mac_addr, uint32_t timeout); -+#else -+extern int32_t ppa_hook_set_bridge_entry_timeout_fn(uint8_t *mac_addr, uint32_t timeout); -+#endif -+ -+/*! \brief This fucntion will enable bridging hook ?? -+ \param[in] f_enable 0--disable, 1--enable -+ \param[in] flags for future usage. -+ \return The following value: \n -+ - IFX_SUCCESS if sucessfully \n -+ - IFX_FAILURE otherwise. -+ \note It it used to enable/disable PPA bridging mac address learning. Normally it is called by network stack which want to enable/disable mac address learning. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_bridge_enable_fn)(uint32_t f_enable, uint32_t flags); -+#else -+extern int32_t ppa_hook_bridge_enable_fn(uint32_t f_enable, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function configures PPA Bridge Interface VLAN configuration behaviour. This includes functionality like whether the bridge is VLAN aware. -+ \param[in] netif Pointer to network interface structure. -+ \param[in] vlan_tag_control Pointer to VLAN Tagging control structure. This specifies whether VLAN tag, untag, replace should be carried out for the interface. -+ \param[in] vlan_cfg Pointer to network interface structure. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_set_bridge_if_vlan_config_fn)(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); -+#else -+extern int32_t ppa_hook_set_bridge_if_vlan_config_fn(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function gets the PPA Bridge Interface VLAN configuration. This includes functionality like whether the bridge is VLAN aware. -+ \param[in] netif Pointer to network interface structure -+ \param[out] vlan_tag_control Pointer to VLAN Tagging control structure. This specifies whether VLAN tag, untag, replace should be carried out for the interface. -+ \param[out] vlan_cfg Pointer to network interface structure. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_bridge_if_vlan_config_fn)(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); -+#else -+extern int32_t ppa_hook_get_bridge_if_vlan_config_fn(PPA_NETIF *netif, PPA_VLAN_TAG_CTRL *vlan_tag_control, PPA_VLAN_CFG *vlan_cfg, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function configures filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. -+ \param[in] vlan_match_field Pointer to VLAN match filter that specifies the match criteria. -+ \param[in] vlan_info Pointer to VLAN Info structure that specifies what VLAN tag action needs to be taken for traffic matching the filter -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_vlan_filter_add_fn)(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); -+#else -+extern int32_t ppa_hook_vlan_filter_add_fn(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function removes filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. -+ \param[in] vlan_match_field Pointer to VLAN match filter that specifies the match criteria. -+ \param[in] vlan_info Pointer to VLAN Info structure that specifies what VLAN tag action needs to be taken for traffic matching the filter -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_vlan_filter_del_fn)(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); -+#else -+extern int32_t ppa_hook_vlan_filter_del_fn(PPA_VLAN_MATCH_FIELD *vlan_match_field, PPA_VLAN_INFO *vlan_info, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function returns all configured filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. -+ \param[out] num_filters Pointer to number of VLAN filters returned by the PPA. -+ \param[out] vlan_filters Pointer to allocated array of VLAN filters.Caller needs to free the allocated memory -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+ \note This function is not implemented currently. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_vlan_filter_get_all_fn)(int32_t *num_filters, PPA_VLAN_FILTER_CONFIG *vlan_filters, uint32_t flags); -+#else -+extern int32_t ppa_hook_vlan_filter_get_all_fn(int32_t *num_filters, PPA_VLAN_FILTER_CONFIG *vlan_filters, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function removes all filters for VLAN tag/untag/retag actions in the PPA Bridge functionality. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_vlan_filter_del_all_fn)(uint32_t flags); -+#else -+extern int32_t ppa_hook_vlan_filter_del_all_fn(uint32_t flags); -+#endif -+ -+/*! -+ \brief Returns interface statistics from the PPA which is a subset of IfTable in SNMP MIB-II standard. -+ \param[in] ifname Pointer to the interface name -+ \param[out] p_stats Pointer to the Statistics data structure of the interface. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+ \note This function is provided to allow the fastpath packet and byte counters to be accounted in stack interface statistics. This function is only implemented for D4 firmware. -+ -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_if_stats_fn)(PPA_IFNAME *ifname, PPA_IF_STATS *p_stats, uint32_t flags); -+#else -+extern int32_t ppa_hook_get_if_stats_fn(PPA_IFNAME *ifname, PPA_IF_STATS *p_stats, uint32_t flags); -+#endif -+ -+ -+/*! -+ \brief Returns per interface statistics kept by the PPA which is a superset of the per Interface statistics above. This provides, for example, fastpath routed and bridged statistics. -+ \param[in] ifname Pointer to the interface name -+ \param[out] p_stats Pointer to the Statistics data structure of the interface. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+ \note This function is only implemented for D4 firmware. -+ -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_accel_stats_fn)(PPA_IFNAME *ifname, PPA_ACCEL_STATS *p_stats, uint32_t flags); -+#else -+extern int32_t ppa_hook_get_accel_stats_fn(PPA_IFNAME *ifname, PPA_ACCEL_STATS *p_stats, uint32_t flags); -+#endif -+ -+/*! -+ \brief Configures MAC address of the Interface (if it is an Ethernet-like interface). -+ \param[in] ifname Pointer to the interface name -+ \param[in] mac_addr Pointer to the MAC address of the interface which is to be set. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_set_if_mac_address_fn)(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); -+#else -+extern int32_t ppa_hook_set_if_mac_address_fn(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); -+#endif -+ -+/*! -+ \brief Returns MAC address of the Interface (if it is an Ethernet-like interface). -+ \param[in] ifname Pointer to the interface name -+ \param[out] mac_addr Pointer to the MAC address of the interface. -+ \param[in] flags Reserved. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_if_mac_address_fn)(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); -+#else -+extern int32_t ppa_hook_get_if_mac_address_fn(PPA_IFNAME *ifname, uint8_t *mac_addr, uint32_t flags); -+#endif -+ -+/*! -+ \brief Adds a new interface to the PPA interface list. The new interface maybe a LAN interface or a WAN interface -+ \param[in] ifinfo Pointer to the interface info structure -+ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n -+ PPA_F_LAN_IF if LAN interface -+ -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_add_if_fn)(PPA_IFINFO *ifinfo, uint32_t flags); -+#else -+extern int32_t ppa_hook_add_if_fn(PPA_IFINFO *ifinfo, uint32_t flags); -+#endif -+ -+/*! -+ \brief Deletes an interface from the PPA interface list. The new interface maybe a LAN interface or a WAN interface -+ \param[in] ifinfo Pointer to the interface info structure -+ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n -+ PPA_F_LAN_IF if LAN interface -+ -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_del_if_fn)(PPA_IFINFO *ifinfo, uint32_t flags); -+#else -+extern int32_t ppa_hook_del_if_fn(PPA_IFINFO *ifinfo, uint32_t flags); -+#endif -+ -+/*! -+ \brief Gets the list of LAN or WAN interfaces from the PPA interface list -+ \param[in] num_ifs Pointer to number of interface elements returned by the API -+ \param[out] ifinfo ointer to the allocated array of interface info structures. Caller has to free the pointer returned -+ \param[in] flags Flag indicating whether interface is LAN flags or WAN. Valid value is: \n -+ PPA_F_LAN_IF if LAN interface -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_if_fn)(int32_t *num_ifs, PPA_IFINFO **ifinfo, uint32_t flags); -+#else -+extern int32_t ppa_hook_get_if_fn(int32_t *num_ifs, PPA_IFINFO **ifinfo, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function allows a device driver to register or deregister a network device to the PPA -+ \param[out] if_id PPA specific Interface Identifier. It is currently a number between 0 to 7. This Id is returned by the PPA module -+ \param[in] dev Pointer to the network device structure in the protocol stack. For eg. pointer to a struct netdevice -+ \param[in] pDirectpathCb Pointer to the DirectPath callback structure which provides the driver callbacks for rx_fn, stop_tx_fn and restart_tx_fn. -+ -+ \param[in] flags Flag to indicate if device is being registered or deregisterd. Valid values are: \n -+ PPA_F_DIRECTPATH_DEREGISTER, if de-registering, zero otherwise -+ PPA_F_DIRECTPATH_CORE1 if the driver for the network interface is running on Core 1 (i.e. 2nd CPU) -+ PPA_F_DIRECTPATH_ETH_IF if the network interface is an Ethernet-like interface -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_directpath_register_dev_fn)(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); -+#else -+extern int32_t ppa_hook_directpath_register_dev_fn(uint32_t *if_id, PPA_NETIF *dev, PPA_DIRECTPATH_CB *pDirectpathCb, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function allows the device driver to transmit a packet using the PPA DirectPath interface. The packet buffer -+ passed to the function must have its packet data pointer set to the IP header with the Ethernet -+ header/Link layer header etc preceding the IP header (For eg., on Linux skb->data points to IP header, and -+ doing the appropriate skb_push() will allow skb->data to move backwards and point to Ethernet header). -+ In other words, PPA Directpath must be able to access the full frame even though the packet buffer points to the -+ IP header as required by the Linux netif_rx() function. -+ \param[in] rx_if_id Receive interface Id in the protocol stack -+ \param[in] buf Pointer to the packet buffer structure of the stack for the packet which is to be transmitted -+ \param[in] len Size of packet in bytes -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess \n -+ - IFX_FAILURE on error -+ \note The DirectPath Tx API can have internal shortcut path to the destination or fallback to passing the packet to the -+ protocol stack. The aim is to insulate the device driver calling the API from such details. \n -+ For Linux, the driver must call this function through the hook pointer where it passes packets to the network stack by calling the netif_rx() or netif_receive_skb() functions. \n -+ Note : The CPU-bound device driver is strongly recommended to call this API from tasklet mode (or equivalent non-interrupt context on non-Linux OS) and not from IRQ context for better system dynamics. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_directpath_send_fn)(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); -+#else -+extern int32_t ppa_hook_directpath_send_fn(uint32_t rx_if_id, PPA_BUF *buf, int32_t len, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function allows the device driver to indicate to the PPA that it cannot receive any further packets from the -+ latter. The device driver can call this function for flow control. -+ \param[in] if_id interface Id for which to apply flow control -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess\n -+ - IFX_FAILURE on fail\n -+ - IFX_EINVAL if the interface not exist -+ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_directpath_rx_stop_fn)(uint32_t if_id, uint32_t flags); -+#else -+extern int32_t ppa_hook_directpath_rx_stop_fn(uint32_t if_id, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function allows the device driver to indicate to the PPA that it can again receive packets from the latter. The -+ device driver can call this function for flow control after it has called the Rx Stop function to halt supply of packets -+ from the PPA. -+ \param[in] if_id interface Id for which the driver requests the flow control action to restart transmission. -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on sucess\n -+ - IFX_FAILURE on fail\n -+ - IFX_EINVAL if the interface not exist -+ \note It is recommended for a device driver to use the PPA DirectPath flow control functions for efficient packet processing. This function must be used in conjunction with the PPA_FP_STOP_TX_FN. -+ -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_directpath_rx_restart_fn)(uint32_t if_id, uint32_t flags); -+#else -+extern int32_t ppa_hook_directpath_rx_restart_fn(uint32_t if_id, uint32_t flags); -+#endif -+ -+/*! -+ \brief This function maps the PPA Interface Id to Protocol stack interface structure. -+ \param[in] if_id PPA Interface Identifier, if_id -+ \return The return value can be any one of the following: \n -+ - Pointer to the interface structure in the protocol stack \n -+ - NULL -+*/ -+#ifdef NO_DOXY -+extern PPA_NETIF *(*ppa_hook_get_netif_for_ppa_ifid_fn)(uint32_t if_id); -+#else -+extern PPA_NETIF *ppa_hook_get_netif_for_ppa_ifid_fn(uint32_t if_id); -+#endif -+ -+/*! -+ \brief This function maps the Protocol stack interface structure to the PPA Interface Id. -+ \param[in] netif Pointer to the protocol stack network interface structure for the device -+ \return The return value can be any one of the following: \n -+ - PPA Interface Identifier, if_id \n -+ - IFX_FAILURE -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_get_ifid_for_netif_fn)(PPA_NETIF *netif); -+#else -+extern int32_t ppa_hook_get_ifid_for_netif_fn(PPA_NETIF *netif); -+#endif -+ -+/*! -+ \brief This function add a vlan range for wan interface in mixed mode -+ \param[in] vlan_range Pointer to vlan id range -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success\n -+ - IFX_FAILURE on fail\n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_wan_mii0_vlan_range_add_fn)(PPA_VLAN_RANGE *vlan_range, uint32_t flags) ; -+#else -+extern int32_t ppa_hook_wan_mii0_vlan_range_add_fn(PPA_VLAN_RANGE *vlan_range, uint32_t flags) ; -+#endif -+ -+/*! -+ \brief This function remove a vlan range from wan interface in mixed mode/RAN -+ -+ \param[in] vlan_range Pointer to vlan id range -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success\n -+ - IFX_FAILURE on fail\n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_wan_mii0_vlan_range_del_fn)(PPA_VLAN_RANGE *vlan_range, int32_t flags); -+#else -+extern int32_t ppa_hook_wan_mii0_vlan_range_del_fn(PPA_VLAN_RANGE *vlan_range, int32_t flags); -+#endif -+ -+/*! -+ \brief This function get a vlan range list from wan interface in mixed mode -+ \param[out] vlan The vlan id range number -+ \param[out] vlan_range Pointer to vlan id range list -+ \param[in] flags reserved -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success\n -+ - IFX_FAILURE on fail\n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_hook_wan_mii0_vlan_ranges_get_fn)(int32_t *vlan, PPA_VLAN_RANGE *vlan_range, uint32_t flags); -+#else -+extern int32_t ppa_hook_wan_mii0_vlan_ranges_get_fn(int32_t *vlan, PPA_VLAN_RANGE *vlan_range, uint32_t flags); -+#endif -+ -+#ifdef CONFIG_IFX_PPA_QOS -+/*! -+ \brief This is to get the maximum queue number supported on specified port -+ \param[in] portid the physical port id which support qos queue -+ \param[in] flag reserved for future -+ \return returns the queue number supported on this port. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_qos_qnum)( uint32_t portid, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_qos_qnum( uint32_t portid, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to get the mib counter on specified port and queueid -+ \param[in] portid the physical port id which support qos queue -+ \param[in] queueid the queue id for the mib -+ \param[out] mib the buffer to store qos mib -+ \param[in] flag reserved for future -+ \return returns the queue number supported on this port. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_qos_mib)( uint32_t portid, uint32_t queueid, PPA_QOS_MIB *mib, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_qos_mib( uint32_t portid, uint32_t queueid, PPA_QOS_MIB *mib, uint32_t flag); -+#endif -+ -+ -+#ifdef CONFIG_IFX_PPA_QOS_RATE_SHAPING -+/*! -+ \brief This is to eanble/disable Rate Shaping feature -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] enable 1:enable 0: disable -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_set_ctrl_qos_rate)( uint32_t portid, uint32_t enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_set_ctrl_qos_rate( uint32_t portid, uint32_t enable, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to get Rate Shaping feature status: enabled or disabled -+ \param[in] portid the phisical port id which support qos queue -+ \param[out] enable buffer to store status: 1:enable 0: disable -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_ctrl_qos_rate)( uint32_t portid, uint32_t *enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_ctrl_qos_rate( uint32_t portid, uint32_t *enable, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to set Rate Shaping for one specified port and queue -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set rate shaping -+ \param[in] rate the maximum rate limit in kbps -+ \param[in] burst the maximun burst in bytes -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_set_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t rate, uint32_t burst, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_set_qos_rate( uint32_t portid, uint32_t queueid, uint32_t rate, uint32_t burst, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to get Rate Shaping settings for one specified port and queue -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set rate shaping -+ \param[out] rate the maximum rate limit in kbps -+ \param[out] burst the maximun burst in bytes -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t *rate, uint32_t *burst, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_qos_rate( uint32_t portid, uint32_t queueid, uint32_t *rate, uint32_t *burst, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to reset Rate Shaping for one specified port and queue ( -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set rate shaping -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_reset_qos_rate)( uint32_t portid, uint32_t queueid, uint32_t flag ); -+#else -+extern int32_t ifx_ppa_hook_reset_qos_rate( uint32_t portid, uint32_t queueid, uint32_t flag ); -+#endif -+ -+#endif /*end of CONFIG_IFX_PPA_QOS_RATE_SHAPING*/ -+ -+ -+#ifdef CONFIG_IFX_PPA_QOS_WFQ -+/*! -+ \brief This is to eanble/disable WFQ feature -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] enable 1:enable 0: disable -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_set_ctrl_qos_wfq)( uint32_t portid, uint32_t enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_set_ctrl_qos_wfq( uint32_t portid, uint32_t enable, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to get WFQ feature status: enabled or disabled -+ \param[in] portid the phisical port id which support qos queue -+ \param[out] enable 1:enable 0: disable -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_ctrl_qos_wfq)( uint32_t portid, uint32_t *enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_ctrl_qos_wfq( uint32_t portid, uint32_t *enable, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to set WFQ weight level for one specified port and queue -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set WFQ -+ \param[out] weight_level the value should be 0 ~ 100. -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_set_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t weight_level, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_set_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t weight_level, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to get WFQ settings for one specified port and queue ( default value should be 0xFFFF) -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set WFQ -+ \param[out] weight_level the value should be 0 ~ 100. -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t *weight_level, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t *weight_level, uint32_t flag); -+#endif -+ -+/*! -+ \brief This is to reset WFQ for one specified port and queue ( default value should be 0xFFFF) -+ \param[in] portid the phisical port id which support qos queue -+ \param[in] queueid the queue id need to set WFQ -+ \param[in] flag reserved for future -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS on success \n -+ - IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_reset_qos_wfq)( uint32_t portid, uint32_t queueid, uint32_t flag ); -+#else -+extern int32_t ifx_ppa_hook_reset_qos_wfq( uint32_t portid, uint32_t queueid, uint32_t flag ); -+#endif -+ -+#endif /*end of CONFIG_IFX_PPA_QOS_WFQ*/ -+#endif /*end of CONFIG_IFX_PPA_QOS*/ -+ -+#if defined(CONFIG_IFX_PPA_MFE) && CONFIG_IFX_PPA_MFE -+/*! -+ \brief This is to enable/disable multiple field function -+ \param[in] enable, 1--enable/0--disable multiple field -+ \return uint8_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_multifield_control)(uint8_t enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_multifield_control(uint8_t enable, uint32_t flag); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to get multiple field status: enable or disable -+ \param[out] enable, buffer for store the multiple filed feature stauts: 1 enabled, 0 disabled. -+ \param[in] flag, reserved for future -+ \return uint8_t The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_multifield_status)(uint8_t *enable, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_multifield_status(uint8_t *enable, uint32_t flag); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to get the maximum multiple field entry/flow number -+ \return int32_t, return the maximum multiple field entry number. For PPA 2.3 it is 32 once multiple filed feature is enabled. -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_multifield_max_flow)(uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_multifield_max_flow(uint32_t flag); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to add one multiple field flow -+ \param[in] p_multifield_info, the pointer which store the classficication set. -+ \param[out]: index return the flow index if successfully added into. \n -+ \param[in] flag, reserved for future -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error \n -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_add_multifield_flow)( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, int32_t *index, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_add_multifield_flow( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, int32_t *index, uint32_t flag); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to get one multiple field flow as specified via index -+ \param[in] p_multifield_info, the pointer which stores the classficication set configuration -+ \param[in] flag, reserved for future -+ \return int32_t, return the bytes in the compare table. It can be any one of the following now: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_multifield_flow)( int32_t index, PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); -+#else -+extern int32_t ifx_ppa_hook_get_multifield_flow( int32_t index, PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); -+#endif -+/*! -+ \brief This is to delete multiple field entry if compare/mask/key completely match -+ \param[in] p_multifield_info, the pointer to store the classficication set configuration -+ \param[in] flag, reserved for future -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error, like entry full already -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_del_multifield_flow)( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); -+#else -+extern int32_t ifx_ppa_hook_del_multifield_flow( PPA_MULTIFIELD_FLOW_INFO *p_multifield_info, uint32_t flag ); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to delete multiple field entry as specified via index -+ \param[out] index, the index of compare table to delete -+ \return int32_t, return the bytes in the compare table. It can be any one of the following now: \n -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+ \note if index is _1, it will delete all multiple field entries -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_quick_del_multifield_flow)( int32_t index, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_quick_del_multifield_flow( int32_t index, uint32_t flag); -+#endif //end of NO_DOXY -+#endif //end of CONFIG_IFX_PPA_API_MFE -+ -+/*! -+ \brief This is to get dsl mib counter -+ \param[out] mib the buffer to store dsl mib -+ \param[in/out] flag reserved for future -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_dsl_mib)( PPA_DSL_QUEUE_MIB *mib, uint32_t flag); -+#else -+extern int32_t ifx_ppa_hook_get_dsl_mib(PPA_DSL_QUEUE_MIB *mib, uint32_t flag); -+#endif //end of NO_DOXY -+ -+/*! -+ \brief This is to get port mib counter -+ \param[out] mib the buffer to store dsl mib -+ \param[in/out] flag reserved for future -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ifx_ppa_hook_get_port_mib)( PPA_PORT_MIB *mib); -+#else -+extern int32_t ifx_ppa_hook_get_port_mib(PPA_PORT_MIB *mib); -+#endif //end of NO_DOXY -+ -+ -+/*! -+ \brief This is to get 6rd tunnel's destination mac address -+ \param[in] network device pointer -+ \param[out] buffer to store ethernet mac address -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_get_6rd_dmac_fn)(PPA_NETIF *netif, uint8_t *mac); -+#else -+extern int32_t ppa_get_6rd_dmac_fn(PPA_NETIF *netif, uint8_t *mac); -+#endif -+ -+/*! -+ \brief This is to get ipv6 tunnel's destination mac address -+ \param[in] network device pointer -+ \param[out] buffer to store ethernet mac address -+ \return int32_t, The return value can be any one of the following: \n -+ IFX_SUCCESS on sucess \n -+ IFX_FAILURE on error -+*/ -+#ifdef NO_DOXY -+extern int32_t (*ppa_get_ip4ip6_dmac_fn)(PPA_NETIF *netif, uint8_t *mac); -+#else -+extern int32_t ppa_get_ip4ip6_dmac_fn(PPA_NETIF *netif, uint8_t *mac); -+#endif -+ -+ -+/*! -+ \brief This is to get 6rd tunnel's underlayer device -+ \param[in] network device pointer -+ \return int32_t, The return value can be any one of the following: \n -+ pointer to the 6rd's underlayer device \n -+ NULL on error -+*/ -+#ifdef NO_DOXY -+extern PPA_NETIF* (*ppa_get_6rd_phyif_fn)(PPA_NETIF *netif); -+#else -+extern PPA_NETIF* ppa_get_6rd_phyif_fn(PPA_NETIF *netif); -+ -+#endif -+ -+/*! -+ \brief This is to get ipv6 tunnel's underlayer device -+ \param[in] network device pointer -+ \return int32_t, The return value can be any one of the following: \n -+ pointer to the ipv6 tunnel's underlayer device \n -+ NULL on error -+*/ -+#ifdef NO_DOXY -+extern PPA_NETIF* (*ppa_get_ip4ip6_phyif_fn)(PPA_NETIF *netif); -+#else -+extern PPA_NETIF* ppa_get_ip4ip6_phyif_fn(PPA_NETIF *netif); -+ -+#endif -+ -+ -+#endif //end of __KERNEL__ -+ -+ -+/* @} */ -+#endif // __IFX_PPA_HOOK_H__20081103_1736__ -diff --git a/include/net/ifx_ppa_ppe_hal.h b/include/net/ifx_ppa_ppe_hal.h -new file mode 100644 -index 0000000..b5d3e0f ---- /dev/null -+++ b/include/net/ifx_ppa_ppe_hal.h -@@ -0,0 +1,317 @@ -+#ifndef __IFX_PPA_PPE_HAL_H__20081104_1318__ -+#define __IFX_PPA_PPE_HAL_H__20081104_1318__ -+ -+ -+ -+/******************************************************************************* -+** -+** FILE NAME : ifx_ppa_ppe_hal.h -+** PROJECT : PPA -+** MODULES : PPA API (Routing/Bridging Acceleration APIs) -+** -+** DATE : 4 NOV 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA PPE Firmware Hardware/Firmware Adaption Layer Header File -+*** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 04 NOV 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+ -+ -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+#define IFX_PPA_IF_NOT_FOUND 0 -+#define IFX_PPA_IF_TYPE_LAN 1 -+#define IFX_PPA_IF_TYPE_WAN 2 -+#define IFX_PPA_IF_TYPE_MIX 3 -+ -+#define IFX_PPA_ACC_MODE_NONE 0 -+#define IFX_PPA_ACC_MODE_BRIDGING 1 -+#define IFX_PPA_ACC_MODE_ROUTING 2 -+#define IFX_PPA_ACC_MODE_HYBRID 3 -+ -+#define IFX_PPA_SET_ROUTE_CFG_ENTRY_NUM 0x01 -+#define IFX_PPA_SET_ROUTE_CFG_MC_ENTRY_NUM 0x02 -+#define IFX_PPA_SET_ROUTE_CFG_IP_VERIFY 0x04 -+#define IFX_PPA_SET_ROUTE_CFG_TCPUDP_VERIFY 0x08 -+#define IFX_PPA_SET_ROUTE_CFG_TCPUDP_ERR_DROP 0x10 -+#define IFX_PPA_SET_ROUTE_CFG_DROP_ON_NOT_HIT 0x20 -+#define IFX_PPA_SET_ROUTE_CFG_MC_DROP_ON_NOT_HIT 0x40 -+ -+#define IFX_PPA_SET_BRIDGING_CFG_ENTRY_NUM 0x01 -+#define IFX_PPA_SET_BRIDGING_CFG_BR_TO_SRC_PORT_EN 0x02 -+#define IFX_PPA_SET_BRIDGING_CFG_DEST_VLAN_EN 0x04 -+#define IFX_PPA_SET_BRIDGING_CFG_SRC_VLAN_EN 0x08 -+#define IFX_PPA_SET_BRIDGING_CFG_MAC_CHANGE_DROP 0x10 -+ -+#define IFX_PPA_ROUTE_TYPE_NULL 0 -+#define IFX_PPA_ROUTE_TYPE_IPV4 1 -+#define IFX_PPA_ROUTE_TYPE_NAT 2 -+#define IFX_PPA_ROUTE_TYPE_NAPT 3 -+ -+//#define IFX_PPA_DEST_LIST_ETH0 0x01 -+//#define IFX_PPA_DEST_LIST_ETH1 0x02 -+//#define IFX_PPA_DEST_LIST_CPU0 0x04 -+//#define IFX_PPA_DEST_LIST_EXT_INT1 0x08 -+//#define IFX_PPA_DEST_LIST_EXT_INT2 0x10 -+//#define IFX_PPA_DEST_LIST_EXT_INT3 0x20 -+//#define IFX_PPA_DEST_LIST_EXT_INT4 0x40 -+//#define IFX_PPA_DEST_LIST_EXT_INT5 0x80 -+//#define IFX_PPA_DEST_LIST_ATM IFX_PPA_DEST_LIST_EXT_INT5 // EoA -+ -+//#define IFX_PPA_DEST_LIST_ETH0 0x0001 -+//#define IFX_PPA_DEST_LIST_ETH1 0x0002 -+//#define IFX_PPA_DEST_LIST_CPU0 0x0004 -+//#define IFX_PPA_DEST_LIST_EXT_INT1 0x0008 -+//#define IFX_PPA_DEST_LIST_EXT_INT2 0x0010 -+//#define IFX_PPA_DEST_LIST_EXT_INT3 0x0020 -+//#define IFX_PPA_DEST_LIST_EXT_INT4 0x0040 -+//#define IFX_PPA_DEST_LIST_EXT_INT5 0x0080 -+//#define IFX_PPA_DEST_LIST_ATM 0x0100 -+//#define IFX_PPA_DEST_LIST_NO_REMAP (1 << 31) -+ -+#define IFX_PPA_PHYS_PORT_FLAGS_VALID 0x0001 -+#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_CPU 0x0000 -+#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_ATM 0x0010 -+#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH 0x0020 -+#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT 0x0030 -+#define IFX_PPA_PHYS_PORT_FLAGS_TYPE_MASK 0x0030 -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN 0x0100 -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN 0x0200 -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_MIX (IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_MASK 0x0300 -+#define IFX_PPA_PHYS_PORT_FLAGS_OUTER_VLAN 0x1000 -+#define IFX_PPA_PHYS_PORT_FLAGS_EXT_CPU0 0x4000 -+#define IFX_PPA_PHYS_PORT_FLAGS_EXT_CPU1 0x8000 -+ -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_LAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ETH_MIX_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ETH | IFX_PPA_PHYS_PORT_FLAGS_MODE_MIX | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_CPU_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_CPU | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_ATM_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_ATM | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_EXT_LAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT | IFX_PPA_PHYS_PORT_FLAGS_MODE_LAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+#define IFX_PPA_PHYS_PORT_FLAGS_MODE_EXT_WAN_VALID (IFX_PPA_PHYS_PORT_FLAGS_TYPE_EXT | IFX_PPA_PHYS_PORT_FLAGS_MODE_WAN | IFX_PPA_PHYS_PORT_FLAGS_VALID) -+ -+#define IFX_PPA_PPPOE_MODE_TRANSPARENT 0 -+#define IFX_PPA_PPPOE_MODE_TERMINATION 1 -+ -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_ROUTE_TYPE 0x0001 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_IP 0x0002 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_PORT 0x0004 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_MAC 0x0008 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_SRC_MAC_IX 0x0010 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_MTU_IX 0x0020 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_DSCP_EN 0x0040 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_DSCP 0x0080 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_VLAN_INS_EN 0x0100 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_NEW_VCI 0x0200 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_VLAN_RM_EN 0x0400 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_PPPOE_MODE 0x0800 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_PPPOE_IX 0x1000 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_INS_EN 0x0100 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_IX 0x0200 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_OUT_VLAN_RM_EN 0x0400 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_DEST_LIST 0x2000 -+#define IFX_PPA_UPDATE_ROUTING_ENTRY_DEST_QID 0x4000 -+ -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_VLAN_INS_EN 0x0001 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_VCI 0x0002 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_VLAN_RM_EN 0x0004 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_SRC_MAC_EN 0x0008 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_SRC_MAC_IX 0x0010 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_LIST 0x0020 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_CHID 0x0040 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_PPPOE_MODE 0x0080 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_INS_EN 0x0100 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_IX 0x0200 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_OUT_VLAN_RM_EN 0x0400 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_DSCP_EN 0x0800 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_NEW_DSCP 0x1000 -+#define IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_QID IFX_PPA_UPDATE_WAN_MC_ENTRY_DEST_CHID -+ -+#define IFX_PPA_ADD_MAC_ENTRY_PPPOE 0x01 -+#define IFX_PPA_ADD_MAC_ENTRY_LAN 0x02 -+#define IFX_PPA_ADD_MAC_ENTRY_WAN 0x00 -+ -+#define IFX_PPA_SET_FAST_MODE_CPU1 0x01 -+#define IFX_PPA_SET_FAST_MODE_APP2 IFX_PPA_SET_FAST_MODE_CPU1 -+#define IFX_PPA_SET_FAST_MODE_ETH1 0x02 -+#define IFX_PPA_SET_FAST_MODE_ATM IFX_PPA_SET_FAST_MODE_ETH1 -+ -+#define IFX_PPA_SET_FAST_MODE_CPU1_DIRECT IFX_PPA_SET_FAST_MODE_CPU1 -+#define IFX_PPA_SET_FAST_MODE_CPU1_INDIRECT 0 -+#define IFX_PPA_SET_FAST_MODE_APP2_DIRECT IFX_PPA_SET_FAST_MODE_CPU1_DIRECT -+#define IFX_PPA_SET_FAST_MODE_APP2_INDIRECT IFX_PPA_SET_FAST_MODE_CPU1_INDIRECT -+#define IFX_PPA_SET_FAST_MODE_ETH1_DIRECT IFX_PPA_SET_FAST_MODE_ETH1 -+#define IFX_PPA_SET_FAST_MODE_ETH1_INDIRECT 0 -+#define IFX_PPA_SET_FAST_MODE_ATM_DIRECT IFX_PPA_SET_FAST_MODE_ETH1_DIRECT -+#define IFX_PPA_SET_FAST_MODE_ATM_INDIRECT IFX_PPA_SET_FAST_MODE_ETH1_INDIRECT -+ -+//#define IFX_PPA_PORT_ETH0 0x00 -+//#define IFX_PPA_PORT_ETH1 0x01 -+//#define IFX_PPA_PORT_CPU0 0x02 -+//#define IFX_PPA_PORT_CPU1_EXT_IF0 0x05 -+//#define IFX_PPA_PORT_ATM 0x07 -+//#define IFX_PPA_PORT_ANY IFX_PPA_PORT_CPU0 -+//#define IFX_PPA_PORT_NUM 0x08 -+ -+// Obsolete, for bridging only -+//#define IFX_PPA_PORT_ETH0 0x00 -+//#define IFX_PPA_PORT_ETH1 0x01 -+//#define IFX_PPA_PORT_CPU0 0x02 -+//#define IFX_PPA_PORT_CPU1_EXT_IF0 0x05 -+//#define IFX_PPA_PORT_ATM 0x08 -+//#define IFX_PPA_PORT_ANY IFX_PPA_PORT_CPU0 -+//#define IFX_PPA_PORT_NUM 0x09 -+ -+#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_DEF 0 -+#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_SRC_IP 1 -+#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_ETH_TYPE 2 -+#define IFX_PPA_BRG_VLAN_IG_COND_TYPE_VLAN 3 -+ -+typedef enum { -+ PPA_GENERIC_HAL_GET_DSL_MIB= 0, //Get dsl mib -+ PPA_GENERIC_HAL_CLEAR_DSL_MIB, //clear dsl mib -+ PPA_GENERIC_WAN_INFO, //get wan information -+ PPA_GENERIC_HAL_GET_PORT_MIB, //get alls ports mib -+ PPA_GENERIC_HAL_CLEAR_PORT_MIB, //clear all ports mib -+ PPA_GENERIC_HAL_SET_DEBUG, // turn on/off hal debug information -+ PPA_GENERIC_HAL_GET_FEATURE_LIST, //get featuer list -+ -+//Fix warning message when exports API from different PPE FW Driver--begin -+ PPA_GENERIC_HAL_GET_MAX_ENTRIES, //get maximum ipv4 routing entry number -+ PPA_GENERIC_HAL_GET_HAL_VERSION, //get hal version number -+ PPA_GENERIC_HAL_GET_PPE_FW_VERSION, //get ppe fw version number -+ PPA_GENERIC_HAL_GET_PHYS_PORT_NUM, //get maixum physical port number -+ PPA_GENERIC_HAL_GET_PHYS_PORT_INFO, //get physical port information -+ PPA_GENERIC_HAL_SET_MIX_WAN_VLAN_ID, //set WAN interface's vlan range for mixed mode -+ PPA_GENERIC_HAL_GET_MIX_WAN_VLAN_ID, //get WAN interface's vlan range for mixed mode -+ PPA_GENERIC_HAL_SET_ROUT_CFG, //set routing configuration -+ PPA_GENERIC_HAL_SET_BRDG_CFG, //set bridge confgiration -+ PPA_GENERIC_HAL_SET_FAST_MODE_CFG, //set fact mode configuration -+ PPA_GENERIC_HAL_SET_DEST_LIST, // set destion list -+ PPA_GENERIC_HAL_SET_ACC_ENABLE, // eanble/disable Lan/wan routing acceleration respectively -+ PPA_GENERIC_HAL_GET_ACC_ENABLE, //get lan/wan routing eanble flag -+ PPA_GENERIC_HAL_SET_BRDG_VLAN_CFG, //set vlan briding configuration for a4/d4/e4 only -+ PPA_GENERIC_HAL_GET_BRDG_VLAN_CFG, //get vlan briding configuration for a4/d4/e4 only -+ PPA_GENERIC_HAL_ADD_BRDG_VLAN_FITLER, //set vlan briding flow for a4/d4/e4 only -+ PPA_GENERIC_HAL_DEL_BRDG_VLAN_FITLER, //del vlan briding flow for a4/d4/e4 only -+ PPA_GENERIC_HAL_GET_BRDG_VLAN_FITLER, //get vlan briding flow for a4/d4/e4 only -+ PPA_GENERIC_HAL_DEL_BRDG_VLAN_ALL_FITLER_MAP, //delete all vlan briding filter's mapping -+ PPA_GENERIC_HAL_GET_MAX_VFILTER_ENTRY_NUM, //get the maxumum entry for vlan filter -+ PPA_GENERIC_HAL_GET_IPV6_FLAG, //get ipv6 status : enabled or disabled -+ PPA_GENERIC_HAL_ADD_ROUTE_ENTRY, //add an ipv4 routing entry -+ PPA_GENERIC_HAL_DEL_ROUTE_ENTRY, //del an ipv4 routing entry -+ PPA_GENERIC_HAL_UPDATE_ROUTE_ENTRY, //modify an ipv4 routing entry -+ PPA_GENERIC_HAL_ADD_MC_ENTRY, //add a multicast entry -+ PPA_GENERIC_HAL_DEL_MC_ENTRY, //del a multicast entry -+ PPA_GENERIC_HAL_UPDATE_MC_ENTRY, //modify a multicast entry -+ PPA_GENERIC_HAL_ADD_BR_MAC_BRIDGING_ENTRY, //add an mac address from brdging learning -+ PPA_GENERIC_HAL_DEL_BR_MAC_BRIDGING_ENTRY, //del an mac address from brdging learning -+ PPA_GENERIC_HAL_ADD_PPPOE_ENTRY, //add a pppoe entry -+ PPA_GENERIC_HAL_DEL_PPPOE_ENTRY, //del a pppoe entry -+ PPA_GENERIC_HAL_GET_PPPOE_ENTRY, //get a ppoe entry -+ PPA_GENERIC_HAL_ADD_6RD_TUNNEL_ENTRY, //add a 6rd tunnel entry -+ PPA_GENERIC_HAL_DEL_6RD_TUNNEL_ENTRY, //del a 6rd tunnel entry -+ PPA_GENERIC_HAL_GET_6RD_TUNNEL_ENTRY, //get a 6rd tunnel entry -+ PPA_GENERIC_HAL_ADD_DSLITE_TUNNEL_ENTRY, //add a dslite tunnel entry -+ PPA_GENERIC_HAL_DEL_DSLITE_TUNNEL_ENTRY, //del a dslite tunnel entry -+ PPA_GENERIC_HAL_GET_DSLITE_TUNNEL_ENTRY, //get a dslite tunnel entry -+ PPA_GENERIC_HAL_ADD_MTU_ENTRY, //and a MTU entry -+ PPA_GENERIC_HAL_DEL_MTU_ENTRY, //del a MTU entry -+ PPA_GENERIC_HAL_GET_MTU_ENTRY, //get a MUT entry -+ PPA_GENERIC_HAL_GET_ROUTE_ACC_BYTES, //get the acclerated bytes counter for a specified acceleration routing entry -+ PPA_GENERIC_HAL_ADD_MAC_ENTRY, //add a routing mac address -+ PPA_GENERIC_HAL_DEL_MAC_ENTRY, //del a routing mac address -+ PPA_GENERIC_HAL_GET_MAC_ENTRY, //get a routing mac address -+ PPA_GENERIC_HAL_ADD_OUT_VLAN_ENTRY, //add a out vlan entry -+ PPA_GENERIC_HAL_DEL_OUT_VLAN_ENTRY, //del a out vlan entry -+ PPA_GENERIC_HAL_GET_OUT_VLAN_ENTRY, //get a out vlan entry info -+ PPA_GENERIC_HAL_GET_ITF_MIB, /*get one port's mib counter. I think it should be merged with PPA_GENERIC_HAL_GET_PORT_MIB */ -+ PPA_GENERIC_HAL_MFE_CONTROL, //enable/disable multiple field vlan editing feature -+ PPA_GENERIC_HAL_MFE_STATUS, // get a multiple field vlan editing feature status: enabled/disabled -+ PPA_GENERIC_HAL_MFE_GET_FLOW_MAX_ENTRY, // get muaximum entry number for multiple field vlan editing -+ PPA_GENERIC_HAL_MFE_ADD_FLOW, //add a multiple field vlan editing entry -+ PPA_GENERIC_HAL_MFE_DEL_FLOW, //del a multiple field vlan editing entry -+ PPA_GENERIC_HAL_MFE_DEL_FLOW_VIA_ENTRY, //del a multiple field vlan editing entry -+ PPA_GENERIC_HAL_MFE_GET_FLOW, //get a multiple field vlan editing entry -+ PPA_GENERIC_HAL_TEST_CLEAR_ROUTE_HIT_STAT, //check whether a routing session is hit or not -+ PPA_GENERIC_HAL_TEST_CLEAR_BR_HIT_STAT, //check whether a routing session is hit or not -+ PPA_GENERIC_HAL_INIT, //init HAL -+ PPA_GENERIC_HAL_EXIT, //exit HAL -+ PPA_GENERIC_HAL_GET_QOS_QUEUE_NUM, //get maximum QOS queue number -+ PPA_GENERIC_HAL_GET_QOS_MIB, //get maximum QOS queue number -+ PPA_GENERIC_HAL_SET_QOS_WFQ_CTRL, //enable/disable WFQ -+ PPA_GENERIC_HAL_GET_QOS_WFQ_CTRL, //get WFQ status: enabeld/disabled -+ PPA_GENERIC_HAL_SET_QOS_WFQ_CFG, //set WFQ cfg -+ PPA_GENERIC_HAL_RESET_QOS_WFQ_CFG, //reset WFQ cfg -+ PPA_GENERIC_HAL_GET_QOS_WFQ_CFG, //get WFQ cfg -+ PPA_GENERIC_HAL_INIT_QOS_WFQ, // init QOS Rateshapping -+ PPA_GENERIC_HAL_SET_QOS_RATE_SHAPING_CTRL, //enable/disable Rate shaping -+ PPA_GENERIC_HAL_GET_QOS_RATE_SHAPING_CTRL, //get Rateshaping status: enabeld/disabled -+ PPA_GENERIC_HAL_SET_QOS_RATE_SHAPING_CFG, //set rate shaping -+ PPA_GENERIC_HAL_GET_QOS_RATE_SHAPING_CFG, //get rate shaping cfg -+ PPA_GENERIC_HAL_RESET_QOS_RATE_SHAPING_CFG, //reset rate shaping cfg -+ PPA_GENERIC_HAL_INIT_QOS_RATE_SHAPING, // init QOS Rateshapping -+ -+//Fix warning message when exports API from different PPE FW Driver--End -+ -+ PPA_GENERIC_HAL_GET_QOS_STATUS, // get QOS tatus -+ -+ -+ -+ /*make sure it is the last one */ -+ PPA_GENERIC_HAL_MAX_FLAG -+}PPA_GENERIC_HOOK_CMD; -+ -+#define IFX_PPA_PWM_LEVEL_D0 0 -+#define IFX_PPA_PWM_LEVEL_D1 1 -+#define IFX_PPA_PWM_LEVEL_D2 2 -+#define IFX_PPA_PWM_LEVEL_D3 3 -+ -+ -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+ -+ -+ -+ -+ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+ -+#ifdef __KERNEL__ -+ -+ -+ -+ /* -+ * implemented in datapath driver -+ */ -+ -+extern int32_t (*ifx_ppa_drv_hal_generic_hook)(PPA_GENERIC_HOOK_CMD cmd, void *buffer, uint32_t flag); -+ -+#endif // __KERNEL__ -+ -+ -+ -+#endif // __IFX_PPA_PPE_HAL_H__20081104_1318__ -diff --git a/include/net/ifx_ppa_stack_al.h b/include/net/ifx_ppa_stack_al.h -new file mode 100644 -index 0000000..7d28b7b ---- /dev/null -+++ b/include/net/ifx_ppa_stack_al.h -@@ -0,0 +1,1559 @@ -+#ifndef __IFX_PPA_STACK_AL_H__20081103_1153__ -+#define __IFX_PPA_STACK_AL_H__20081103_1153__ -+ -+ -+ -+/****************************************************************************** -+** -+** FILE NAME : ifx_ppa_stack_al.h -+** PROJECT : PPA -+** MODULES : PPA Protocol Stack Adaption Layer (Linux) -+** -+** DATE : 3 NOV 2008 -+** AUTHOR : Xu Liang -+** DESCRIPTION : PPA Protocol Stack Adaption Layer (Linux) Header File -+** COPYRIGHT : Copyright (c) 2009 -+** Lantiq Deutschland GmbH -+** Am Campeon 3; 85579 Neubiberg, Germany -+** -+** For licensing information, see the file 'LICENSE' in the root folder of -+** this software module. -+** -+** HISTORY -+** $Date $Author $Comment -+** 03 NOV 2008 Xu Liang Initiate Version -+*******************************************************************************/ -+ -+/*! \file ifx_ppa_stack_al.h -+ \brief This file contains es. -+ provide linux os depenent api for PPA to use -+*/ -+ -+ -+#include <net/ifx_ppa_api_common.h> -+ -+#ifdef __KERNEL__ -+ #include <linux/version.h> -+ #include <linux/if_arp.h> -+ #include <linux/if_pppox.h> -+ #if defined(CONFIG_NF_CONNTRACK_SUPPORT) || defined(CONFIG_NF_CONNTRACK) -+ #include <net/netfilter/nf_conntrack.h> /* protocol independent conntrack */ -+ #else -+ #include <linux/netfilter_ipv4/ip_conntrack.h> -+ #endif -+#endif //end of __KERNEL__ -+ -+#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) -+ //PMCU specific Head File -+ #include <asm/ifx/ifx_types.h> -+ #include <asm/ifx/ifx_pmcu.h> -+#endif //end of CONFIG_IFX_PMCU -+ -+/* -+ * #################################### -+ * Definition -+ * #################################### -+ */ -+ -+/*! \def PPA_ETH_ALEN -+ \brief Macro that specifies the maximum length of an Ethernet MAC address. -+ */ -+#define PPA_ETH_ALEN ETH_ALEN -+ -+/*! \def PPA_ETH_HLEN -+ \brief Macro that specifies the maximum length of an Ethernet MAC header. -+ */ -+#define PPA_ETH_HLEN ETH_HLEN -+ -+/*! \def PPA_ETH_CRCLEN -+ \brief Macro that specifies the maximum length of an Ethernet CRC. -+ */ -+#define PPA_ETH_CRCLEN 4 -+ -+/*! \def PPA_IF_NAME_SIZE -+ \brief Macro that specifies the maximum size of one interface name -+ */ -+#define PPA_IF_NAME_SIZE IFNAMSIZ -+ -+/*! \def IFX_IPPROTO_TCP -+ \brief Macro that specifies TCP flag -+ */ -+#define IFX_IPPROTO_TCP 6 -+ -+/*! \def IFX_IPPROTO_UDP -+ \brief Macro that specifies UDP flag -+ */ -+#define IFX_IPPROTO_UDP 17 -+ -+/*! \def PPA_USER -+ \brief Macro that specifies the flag for the buffer type from User Space via ioctl -+ */ -+#define PPA_USER __user -+ -+/* -+ * definition for application layer -+ */ -+#ifndef __KERNEL__ -+/*! \def ETH_ALEN -+ \brief Macro that specifies the maximum length of an Ethernet MAC address. -+ */ -+ #define ETH_ALEN 6 -+ -+/*! \def IFNAMSIZ -+ \brief Macro that specifies the maximum size of an interface NAME -+ */ -+ #define IFNAMSIZ 16 -+#endif -+ -+#define NIPQUAD(addr) \ -+ ((unsigned char *)&addr)[0], \ -+ ((unsigned char *)&addr)[1], \ -+ ((unsigned char *)&addr)[2], \ -+ ((unsigned char *)&addr)[3] -+ -+#undef NIP6 -+#define NIP6(addr) \ -+ ntohs(((unsigned short *)addr)[0]), \ -+ ntohs(((unsigned short *)addr)[1]), \ -+ ntohs(((unsigned short *)addr)[2]), \ -+ ntohs(((unsigned short *)addr)[3]), \ -+ ntohs(((unsigned short *)addr)[4]), \ -+ ntohs(((unsigned short *)addr)[5]), \ -+ ntohs(((unsigned short *)addr)[6]), \ -+ ntohs(((unsigned short *)addr)[7]) -+ -+/* -+ * #################################### -+ * Data Type -+ * #################################### -+ */ -+ -+/* -+ * data type for application layer -+ */ -+#ifndef __KERNEL__ -+/*! -+ \brief This is the unsigned char 32-bit data type. -+*/ -+ typedef unsigned long uint32_t; -+ -+/*! \def uint16_t -+ \brief This is the unsigned char 16-bit data type. -+*/ -+ typedef unsigned short uint16_t; -+ -+/*! -+ \brief This is the unsigned char 8-bit data type. -+*/ -+ typedef unsigned char uint8_t; -+ -+/*! -+ \brief This is the unsigned char 64-bit data type. -+*/ -+ typedef unsigned long long uint64_t; -+ -+#endif -+ -+/* -+ * data type for API -+ */ -+/*! -+ \brief Pointer to interface name -+*/ -+typedef char PPA_IFNAME; -+/*! -+ \brief This is the data structure holding the IP address. It helps to provide future compatibility for IPv6 support. -+ Currently it only supports IPv4. -+ -+*/ -+typedef uint32_t IPADDR; -+ -+/*! -+ \brief Union of PPA network address -+ */ -+ typedef union { -+ uint32_t ip; /*!< the storage buffer for ipv4 */ -+#ifdef CONFIG_IFX_PPA_IPv6_ENABLE -+ uint32_t ip6[4]; /*!< the storage buffer for ipv6 */ -+#endif -+ }PPA_IPADDR; -+ -+#ifdef __KERNEL__ -+ -+/*! -+ \brief Packet buffer structure. For Linux OS, this is the sk_buff structure. -+*/ -+ typedef struct sk_buff PPA_BUF; -+ -+/*! -+ \brief Stateful Packet inspection / connection tracking session data structure. -+ A packet is classified to such a session by SPI/NAT infrastructure. -+ In Linux, this is defined to the Linux ip_conntrack/nf_conntrack structure. -+*/ -+ #if defined(CONFIG_NF_CONNTRACK_SUPPORT) || defined(CONFIG_NF_CONNTRACK) -+ typedef struct nf_conn PPA_SESSION; -+ #else -+ typedef struct ip_conntrack PPA_SESSION; -+ #endif -+ -+ -+/*! -+ \brief Macro that specifies PPA network interface data structure -+ */ -+ typedef struct net_device PPA_NETIF; -+ -+ /*! -+ \brief Macro that specifies PPA network interface status structure -+ */ -+ typedef struct net_device_stats PPA_NETIF_STATS; -+ -+ -+/*! -+ \brief This is the data structure for the PPA ATM VC structure. In Linux, this is defined to the Linux atm_vcc structure -+ */ -+ typedef struct atm_vcc PPA_VCC; -+ -+/*! -+ \brief PPA synchronization primitive for exclusion and/or synchronization -+*/ -+ typedef struct mutex PPA_LOCK; -+ -+/*! -+ \brief PPA memory pool cache for efficient allocation of PPA data structures. Can be mapped to -+ suitable OS allocation logic -+*/ -+ typedef struct kmem_cache PPA_MEM_CACHE; -+ -+/*! -+ \brief PPA Timer data structure. Should allow one shot timers to be configured with a passed -+ timer callback function -+*/ -+ typedef struct timer_list PPA_TIMER; -+ -+/*! -+ \brief PPA atomic timer structure. In linux, it is atomic_t structure. -+*/ -+ typedef atomic_t PPA_ATOMIC; -+ /*! -+ \brief PPA SIZE_T. For Linux OS, the size_t is unsigned int. -+*/ -+ typedef size_t PPA_SIZE_T; -+/*! -+ \brief PPA FILE PPA_FILE_OPERATIONS. For Linux OS, it is file_operations -+*/ -+ typedef struct file_operations PPA_FILE_OPERATIONS; -+ -+/*! -+ \brief PPA sync. For Linux OS, it is __sync -+ \note, someties GCC will wrongly optimize the code, so __sync is used to avoid it. \n -+ otherwise, just define PPA_SYNC to do { } while(0) -+*/ -+ -+ #define PPA_SYNC __sync -+ -+#if defined(CONFIG_IFX_PMCU) || defined(CONFIG_IFX_PMCU_MODULE) -+/*! -+ \brief PPA POWER MANAGEMENT RETURN VALUE. -+*/ -+ typedef IFX_PMCU_STATE_t PPA_PWM_STATE_t; -+ -+/*! -+ \brief PPA POWER MANAGEMENT RETURN VALUE. -+*/ -+ typedef IFX_PMCU_RETURN_t PPA_PWM_RETURN_t; -+ -+/*! -+ \brief PPA POWER MANAGEMENT MODUE STATE VALUE. -+*/ -+ typedef IFX_PMCU_MODULE_STATE_t PPA_PWM_MODULE_STATE_t; -+#endif //end of CONFIG_IFX_PMCU -+ -+#endif -+ -+ -+ -+/* -+ * #################################### -+ * Inline Functions -+ * #################################### -+ */ -+ -+ -+ -+/* -+ * #################################### -+ * Declaration -+ * #################################### -+ */ -+/** \addtogroup PPA_ADAPTATION_LAYER */ -+/*@{*/ -+ -+#ifdef __KERNEL__ -+/*! \brief Get the ppa adaption layer version -+ \param[in] p_family Pointer to the hardware family -+ \param[in] p_type Pointer to hardware type -+ \param[in] p_if Pointer interface -+ \param[in] p_mode Pointer mode -+ \param[in] p_major Pointer major version number -+ \param[in] p_mid Pointer to min version number -+ \param[in] p_minor Pointer to minor version number -+ \note Provide anything required to put in remark section. -+*/ -+ void ppa_get_stack_al_id(uint32_t *p_family, -+ uint32_t *p_type, -+ uint32_t *p_if, -+ uint32_t *p_mode, -+ uint32_t *p_major, -+ uint32_t *p_mid, -+ uint32_t *p_minor); -+ -+/*! \brief Get the PPA session according to PPA_BUF -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return returns the PPA session pointer if found, otherwise return NULL -+*/ -+ PPA_SESSION *ppa_get_session(PPA_BUF *ppa_buf); -+ -+ -+#if LINUX_VERSION_CODE < KERNEL_VERSION(2,6,32) -+ -+/*! \brief Get the PPA buffer network protocol header. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return point to the network header. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t *skb_network_header(const PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer transport protocol header. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return point to the transport protocol header. -+ \note Provide anything required to put in remark section. -+*/ -+// uint8_t *skb_transport_header(const PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer MAC header. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return point to the MAC header. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t *skb_mac_header(const PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv6 packet's header. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return point to the IPv6 header structure. -+ \note Provide anything required to put in remark section. -+*/ -+ struct ipv6hdr *ipv6_hdr(const PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv4 packet's header. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return point to the IPv4 header structure. -+ \note Provide anything required to put in remark section. -+*/ -+ struct iphdr *ip_hdr(const PPA_BUF *ppa_buf); -+ -+/*! \brief Returns if the IPv4 address is an IPv4 multicast packet. -+ \param[in] addr IPv4 address value. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is a IPv4 multicast packet. \n -+ - IFX_FALSE otherwise. \n -+ \note Provide anything required to put in remark section. -+*/ -+ uint32_t ipv4_is_multicast(uint32_t addr); -+ -+ -+#endif /*LINUX_VERSION_CODE < KERNEL_VERSION(2,6,22)*/ -+ -+ -+#if defined(CONFIG_IFX_PPA_IPv6_ENABLE) && (defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)) -+ -+ -+/*! \brief Get the PPA buffer IPv6 transport protocol. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return transport protocol value. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_get_ipv6_l4_proto(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv6 packet's Type of Service value. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return Type of Service value. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_get_ipv6_tos(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv6 packet's source IP address. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return source IP address value. -+ \note Provide anything required to put in remark section. -+*/ -+ PPA_IPADDR ppa_get_ipv6_saddr(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv6 packet's destination IP address. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return destination IP address value. -+ \note Provide anything required to put in remark section. -+*/ -+ PPA_IPADDR ppa_get_ipv6_daddr(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is an IPv6 multicast packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is an IPv6 multicast packet. \n -+ - IFX_FALSE otherwise. \n -+ \note Provide anything required to put in remark section. -+*/ -+ int32_t ppa_is_ipv6_multicast(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is an IPv6 fragment packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is an IPv6 fragment packet. \n -+ - IFX_FALSE otherwise. \n -+ \note Provide anything required to put in remark section. -+*/ -+ uint32_t ppa_is_ipv6_fragment(PPA_BUF *ppa_buf); -+ -+#endif /*CONFIG_IFX_PPA_IPv6_ENABLE*/ -+ -+ -+/*! \brief return the judgement of IPv6 packet type check. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return The function returns one of the following. \n -+ - IFX_TRUE, if the packet is an IPv6 packet. \n -+ - IFX_FALSE, if the packet is not an IPv6 packet. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_is_pkt_ipv6(const PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv4 packet's transport protocol value. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return transport protocol value. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_get_ip_l4_proto(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv4 packet's Type of Service value. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return Type of Service value. -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_get_ip_tos(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv4 packet's source IP address. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return source IP address value. -+ \note Provide anything required to put in remark section. -+*/ -+ PPA_IPADDR ppa_get_ip_saddr(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the PPA buffer IPv4 packet's destination IP address. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return destination IP address value. -+ \note Provide anything required to put in remark section. -+*/ -+ PPA_IPADDR ppa_get_ip_daddr(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is an IPv4 multicast packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is an IPv4 multicast packet. \n -+ - IFX_FALSE otherwise. \n -+ \note Provide anything required to put in remark section. -+*/ -+ int32_t ppa_is_ip_multicast(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is an IPv4 fragment packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is an IPv4 fragment packet. \n -+ - IFX_FALSE otherwise. \n -+ \note Provide anything required to put in remark section. -+*/ -+ uint32_t ppa_is_ip_fragment(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Turn the given IP to string and put it to the given buffer. -+ \param[in] ppa_ip the source ip address -+ \param[in] flag the flag of ipv6 or ipv4: 1--ipv6, 0-ipv4 -+ \param[out] strbuf contains the string format of IP ( the storage buffer should be allocated before calling the api). -+ \return return the point to the given buffer. -+ \note Provide anything required to put in remark section. -+*/ -+ int8_t *ppa_get_pkt_ip_string(PPA_IPADDR ppa_ip, uint32_t flag, int8_t *strbuf); -+ -+ -+/*! \brief Turn the given MAC address to string and put it to the given buffer. -+ \param[in] *mac point to MAC address buffer. -+ \param[out] *strbuf contains the string format of MAC. -+ \return return the point to the given buffer. -+ \note Provide anything required to put in remark section. -+*/ -+ int8_t *ppa_get_pkt_mac_string(uint8_t *mac, int8_t *strbuf); -+ -+ -+/*! \brief return the length of IP address. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return return the number of bytes of the length of IP address. -+ \note Provide anything required to put in remark section. -+*/ -+ uint32_t ppa_get_pkt_ip_len(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Get the PPA buffer IP protocol -+ \param[in] buf Pointer to the packet buffer. -+ \return The return value can be IP protocol value between 0-255. A value of 0 -+ \note Provide anything required to put in remark section. -+*/ -+ uint8_t ppa_get_pkt_ip_proto(PPA_BUF *buf); -+ -+ -+ -+/*! \brief Get the PPA buffer IP Type of Service field. -+ \param[in] buf Pointer to the packet buffer. -+ \return The return value is IP header ToS value. -+ \note -+*/ -+ uint8_t ppa_get_pkt_ip_tos(PPA_BUF *buf); -+ -+ -+ -+/*! \brief Returns source IP address of the packet. -+ \param[in] buf Pointer to the Packet buffer. -+ \return The Source IP address of the packet. -+ \note -+*/ -+ PPA_IPADDR ppa_get_pkt_src_ip(PPA_BUF *buf); -+ -+ -+ -+/*! \brief Will return source IP address of a packet, it is enhancement of ppa_get_pkt_src_ip in the sense that it can be. nvoked from both Layer 2 and Layer 3. If the source IP address it multicast one it will return 0. -+ \param[in] buf Pointer to the packet buffer. -+ \return The Source IP address of the packet. -+ \note -+*/ -+ IPADDR ppa_get_pkt_src_ip2(PPA_BUF *buf); -+ -+ -+ -+/*! \brief Returns destination IP address of the packet. -+ \param[in] buf Pointer to the packet buffer. -+ \return The Destination IP address of the packet.. -+ \note -+*/ -+ PPA_IPADDR ppa_get_pkt_dst_ip(PPA_BUF *buf); -+ -+ -+/*! \brief Returns source TCP/UDP port of the IP packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return TCP/UDP Source Port of the packet. -+ \note -+*/ -+ uint16_t ppa_get_pkt_src_port(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns destination TCP/UDP port of the packet. -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \return TCP/UDP Destination Port of the packet. -+ \note -+*/ -+ uint16_t ppa_get_pkt_dst_port(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Get the Source MAC address of the packet as received by the router. -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \param[out] mac MAC address buffer in which the source MAC address is copied by the function. -+ \return This function does not return anything. -+ \note This API may not implemented on older PPA version. -+*/ -+ void ppa_get_pkt_rx_src_mac_addr(PPA_BUF *ppa_buf, uint8_t mac[PPA_ETH_ALEN]); -+ -+ -+/*! \brief Get the Destination MAC address of the packet as received by the router. -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \param[out] mac MAC address buffer in which the Destination MAC address is copied by the function. -+ \return This function does not return anything. -+ \note This API may not implemented on older PPA version. -+*/ -+ void ppa_get_pkt_rx_dst_mac_addr(PPA_BUF *ppa_buf, uint8_t mac[PPA_ETH_ALEN]); -+ -+ -+/*! \brief Returns source (i.e. Received) interface of the packet at the router. -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \return Pointer to the Source /Rx Interface of the packet. The following values can be returned.\n -+ - NULL on error -+ - Pointer to Rx interface of the packet -+ \note This API may not implemented on older PPA version. -+*/ -+ PPA_NETIF *ppa_get_pkt_src_if(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief Returns Destination (i.e. Tx) interface of the packet at the router (for packets forwarded at IP or bridge level). -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n -+ - NULL on error -+ - Pointer to Rx interface of the packet -+ \note This API may not implemented on older PPA version. -+*/ -+ PPA_NETIF *ppa_get_pkt_dst_if(PPA_BUF *ppa_buf); -+ -+/*! \brief Returns skb priority of the packet at the router (for packets forwarded at IP or bridge level). -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n -+ - NULL on error -+ - Pointer to Rx interface of the packet -+*/ -+uint32_t ppa_get_pkt_priority(PPA_BUF *ppa_buf); -+ -+/*! \brief set new skb priority of the packet: for test purpose only -+ \param[in] ppa_buf Pointer to the PPA packet buffer. -+ \param[in] new_pri new skb priority value -+ \return new priority if sucessful. otherwise return -1; -+*/ -+uint32_t ppa_set_pkt_priority(PPA_BUF *ppa_buf, uint32_t new_pri); -+ -+ -+/*! -+ \brief get ppoe mac address and session id -+ \param[in] netif Pointer to pppoe network interface. -+ \param[out] *pa Pointer to pppoe addres. -+ \return Pointer to the Destination /Tx Interface of the packet. The following values can be returned.\n -+ - NULL on error -+ - Pointer to Rx interface of the packet -+ \note This API may not implemented on older PPA version. -+*/ -+ int32_t ppa_pppoe_get_pppoe_addr(PPA_NETIF *netif, struct pppoe_addr *pa); -+ -+ -+ -+/*! \brief Returns the PPPoE session Id of the net interface structure. -+ \param[in] netif Pointer network interface structure. -+ \return The return value can be any one of the following:\n -+ - Non-zero value is PPPoE Session Id -+ - Zero indicates no valid PPPoE session. -+ \note -+*/ -+__u16 ppa_pppoe_get_pppoe_session_id(PPA_NETIF *netif); -+ -+ -+/*! \brief Returns the PPPoE session Id of the packet. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \return The return value can be any one of the following:\n -+ - Non-zero value is PPPoE Session Id. \n -+ - Zero indicates no valid PPPoE session i.e. not a PPPoE session packet. -+ \note -+*/ -+ __u16 ppa_get_pkt_pppoe_session_id(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief get the pppoe's sub ethernet interface name -+ \param[in] netif Pointer to ppp network interface -+ \param[out] pppoe_eth_ifname Provide buffer to store its sub ethernet interface name -+ \return The return value can be any one of the following:\n -+ - Non-zero fail to get its sub ethernet interface name \n -+ - Zero indicates succeed -+ \note -+*/ -+ int32_t ppa_pppoe_get_eth_netif(PPA_NETIF *netif, PPA_IFNAME pppoe_eth_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+ -+/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a PPPoE interface specified by netif.. -+ \param[in] netif Pointer to the network interface structure in the stack. -+ \param[in] ifname Pointer to the network interface name. -+ \param[out] phy_ifname Interface name buffer in which the Physical interface name is copied by the function. -+ \return The return value can be any one of the following:\n -+ - IFX_SUCCESS, if PPPoE physical address retrieved ok -+ - IFX_FAILURE, on error -+ \note -+*/ -+ int32_t ppa_pppoe_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+/*! \brief check whether it is a ppp interface -+ \param[in] netif Pointer to the network interface structure in the stack. -+ \return The return value can be any one of the following:\n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. -+ \note This API may not implemented on older PPA version. -+*/ -+ uint32_t ppa_check_is_ppp_netif(PPA_NETIF *netif); -+ -+/*! \brief check whether it is a pppoe interface -+ \param[in] netif Pointer to the network interface structure in the stack. -+ \return The return value can be any one of the following:\n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. -+ \note This API may not implemented on older PPA version. -+*/ -+ uint32_t ppa_check_is_pppoe_netif(PPA_NETIF *netif); -+ -+/*! \brief get pppoe's destination mac address, ie, remote peer's mac address -+ \param[in] netif Pointer to the network interface structure in the stack. -+ \param[out] mac provide buffer to store desnation mac address -+ \return The return value can be any one of the following:\n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. -+ \note This API may not implemented on older PPA version. -+*/ -+ int32_t ppa_pppoe_get_dst_mac(PPA_NETIF *netif , uint8_t mac[PPA_ETH_ALEN]); -+ -+ -+/*! \brief This function returns the destination MAC address to be used in the Ethernet frame when transmitted out of the router. -+ \param[in] ppa_buf Pointer to the packet buffer. -+ \param[in] p_session Pointer to the NAT connection tracking session to which the packet belongs. This parameter may not be required in the function implementation, for eg. on Linux 2.4 adaptation. -+ \param[out] mac The destination MAC address for the specific packet is copied into this field. -+ \return The return value can be any one of the following: \n -+ - IFX_SUCCESS, if destination MAC address is retrieved ok \n -+ - IFX_FAILURE, on error -+ \note -+*/ -+ int32_t ppa_get_dst_mac(PPA_BUF *ppa_buf, PPA_SESSION *p_session, uint8_t mac[PPA_ETH_ALEN]); -+ -+ -+ -+/*! \brief Returns the pointer to network interface data structure in the stack for the specified interface name. For Linux, this is the netdevice structure pointer. -+ \param[in] ifname Pointer to the interface name. -+ \return The return value can be any one of the following: \n -+ - Pointer to network interface structure, on success. \n -+ - NULL on error. -+ \note This function needs to ensure that it has a handle / reference count to the network interface structure, so that the interface structure cannot be deleted while the PPA has a reference to it. Please see the section Release Reference to network interface structure for the function to release the PPA's reference to the PPA_NETIF structure when done. -+*/ -+ PPA_NETIF *ppa_get_netif(PPA_IFNAME *ifname); -+ -+ -+/*! \brief This function releases the reference to a PPA_NETIF structure obtained through the function ppa_get_netif. -+ \param[in] netif Pointer to the netif structure. -+ \return No return value. -+ \note -+*/ -+ void ppa_put_netif(PPA_NETIF *netif); -+ -+ -+ -+/*! \brief Get the MAC address of the specified interface of the router. It is valid for an Ethernet-like interface or a PPPoE interface bound to the former. -+ \param[in] netif Pointer to the network interface structure. -+ \param[out] mac MAC address buffer in which the MAC address of the interface is copied by the function if its an Ethernet like interface. -+ \return No return value. -+ \note This API may not implemented on older PPA version. -+*/ -+ int32_t ppa_get_netif_hwaddr(PPA_NETIF *netif, uint8_t mac[PPA_ETH_ALEN]); -+ -+ -+ -+ /*! \brief Returns the pointer to the interface name for the specified netif structure. -+ \param[in] netif Pointer to the network interface structure. -+ \return The return value can be any one of the following: \n -+ - Pointer to interface name, on success. \n -+ - NULL on error. -+ \note -+*/ -+ PPA_IFNAME *ppa_get_netif_name(PPA_NETIF *netif); -+ -+ -+ -+ -+ /*! \brief Returns true if both the netif structure points to same physical interface. -+ \param[in] netif1 Pointer to the first network interface structure. -+ \param[in] netif2 Pointer to the second network interface structure. -+ \return Valid values are below. \n -+ - IFX_TRUE, if netif1 is same as netif2 interface \n -+ - IFX_FALSE, if interface are not equal \n -+ \note -+*/ -+uint32_t ppa_is_netif_equal(PPA_NETIF *netif1, PPA_NETIF *netif2); -+ -+ -+ -+ -+ /*! \brief This function returns if the Network interface structure pointer corresponds to the interface name specified. -+ \param[in] netif Pointer to the network interface structure. -+ \param[in] ifname Pointer to the network interface name. -+ \return The function returns one of the following. \n -+ - IFX_TRUE, if the netif corresponds to the ifname. \n -+ - IFX_FALSE, if the netif is not for the ifname. -+ \note This API may not implemented on older PPA version. -+*/ -+ uint32_t ppa_is_netif_name(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+ -+/*! \brief This function checks if the interface name prefix specified applies for the interface name of the specified PPA_NETIF structure. For eg., eth0 and eth1 both have network prefix of eth (n=3). -+ \param[in] netif Pointer to the network interface structure. -+ \param[in] ifname_prefix Pointer to the network interface name prefix. -+ \param[in] n Number of bytes of the prefix to compare with the interface name of the netif. -+ \return The function returns one of the following. \n -+ - IFX_TRUE, if the netif corresponds to the ifname prefix. \n -+ - IFX_FALSE, if the netif is not matching the ifname prefix. -+ \note This API may not implemented on older PPA version. -+*/ -+ -+ uint32_t ppa_is_netif_name_prefix(PPA_NETIF *netif, PPA_IFNAME *ifname_prefix, int32_t n); -+ -+ -+ -+/*! \brief Get the Physical or underlying Interface for the interface specified by netif or ifname pointers. If netif is specified, it is used for the lookup, else ifname is used. -+ \param[in] netif Pointer to the network interface structure for which physical interface needs to be determined. -+ \param[in] ifname Pointer to the network interface name for which physical interface needs to be determined. -+ \param[in] phy_ifname Interface name buffer in which the Physical interface name is copied by the function. -+ \return This function returns the following values. \n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. \n -+ \note This API may not implemented on older PPA version. -+*/ -+ int32_t ppa_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+ -+/*! \brief This function gives the vlan interface name specified by netif strucutre or ifname pointers. One of the two arguments needs to be specified in the function. -+ \param[in] netif Pointer to the network interface structure for VLAN interface check is to be done. -+ \param[in] ifname Pointer to the network interface name for which VLAN check is to be done. -+ \param[in] vlan_ifname Buffer where the vlan interface name is copied by the function. -+ \return The function returns one of the following. \n -+ - IFX_TRUE, if the interface exist. \n -+ - IFX_FALSE, if the interface doesn't exist. -+ \note -+*/ -+ int32_t ppa_get_underlying_vlan_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME vlan_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+ -+/*! \brief This function checks whether the interface specified by netif or ifname pointers is a VLAN interface. One of the two arguments needs to be specified in the function. -+ \param[in] netif Pointer to the network interface structure for VLAN interface check is to be done. -+ \param[in] ifname Pointer to the network interface name for which VLAN check is to be done. -+ \return This function returns the following values. \n -+ - IFX_SUCCESS, if the VLAN interface exist. \n -+ - IFX_FALSE, if the interface is does not exist. -+ \note -+*/ -+ int32_t ppa_if_is_vlan_if(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+ -+ -+/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a pseudo VLAN interface specified by netif structure or interface name. -+ \param[in] netif Pointer to the VLAN net interface structure. -+ \param[in] ifname Pointer to the VLAN interface name for which underlying interface is to be determined -+ \param[out] phy_ifname Buffer where the physical/underlying interface is copied by the function for the VLAN interface ifname. -+ \return This function returns the following values. \n -+ - IFX_TRUE, if the interface is a VLAN interface \n -+ - IFX_FAILURE, if the interface is not a VLAN interface -+ \note -+*/ -+ int32_t ppa_vlan_get_underlying_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+ -+ -+/*! \brief This function returns the physical or underlying interface (Ethernet-like) for a pseudo VLAN interface specified by netif structure or interface name. -+ \param[in] netif Pointer to the VLAN network interface structure. -+ \param[in] ifname Pointer to the VLAN interface name for which underlying interface is to be determined. -+ \param[out] phy_ifname Buffer where the physical/underlying interface is copied by the function for the VLAN interface. -+ \return This function returns the following values. \n -+ - IFX_SUCCESS, if the VLAN interface exist \n -+ - IFX_FAILURE, if the interface is does not exist\n -+ \note -+*/ -+ int32_t ppa_vlan_get_physical_if(PPA_NETIF *netif, PPA_IFNAME *ifname, PPA_IFNAME phy_ifname[PPA_IF_NAME_SIZE]); -+ -+ -+ -+/*! \brief This function returns the VLAN Id and tag info for a VLAN interface specified by netif. This includes the VLAN tag, 802.1P bits and the CFI bit. The caller will first determine if the network interface is a VLAN interface before invoking this function. -+ \param[in] netif Pointer to the network interface structure for which VLANId is to be returned. -+ \return This function returns the VLAN TCI (Tag control information). -+ \note -+*/ -+ uint32_t ppa_get_vlan_id(PPA_NETIF *netif); -+ -+ -+ -+ -+/*! \brief This function returns the TCI including priority and VLAN Id for a PPA buffer pointer by buf. -+ \param[in] buf Pointer to PPA buffer. -+ \return This function returns the VLAN TCI (Tag control information). -+ \note -+*/ -+ uint32_t ppa_get_vlan_tag(PPA_BUF *buf); -+ -+ -+ -+/*! \brief This function returns whether the interface specified by ifname or netif pointer is enslaved to a bridge, i.e. member of a bridge. -+ \param[in] ifname Pointer to the network interface name for which bridge membership has to be determined. -+ \param[in] netif Pointer to the network interface structure for which bridge membership is to be determined. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE, if the network interface is enslaved to a bridge. \n -+ - IFX_FALSE, if the network interface is not enslaved to a bridge. -+ \note -+*/ -+ int32_t ppa_is_netif_bridged(PPA_IFNAME *ifname, PPA_NETIF *netif); -+ -+ -+ #ifdef NO_DOXY -+ int32_t ppa_get_bridge_member_ifs(PPA_IFNAME *ifname, int *, PPA_IFNAME **); -+ #endif -+ -+/*! \brief This function returns whether the interface specified by ifname or netif pointer is a bridge interface, i.e. other interfaces are enslaved to this bridge interface. For eg., br0 is a bridge interface in Linux which may have bridge members like eth0, nas0 etc. -+ \param[in] netif Pointer to the network interface structure for which bridge interface check is to be done. -+ \param[in] ifname Pointer to the network interface name for which bridge interface check is to be done. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE, if the network interface is a bridge interface/port. \n -+ - IFX_FALSE, if the network interface is not a bridge interface/port. -+ \note -+*/ -+ int32_t ppa_if_is_br_if(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+ -+/*! \brief This function performs a bridge forwarding database lookup for the bridge specified by netif and returns the member interface on which the packet needs to be forwarded. -+ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. -+ \param[in] buf Pointer to the packet buffer for the frame which has to be bridged (forwarded at Layer-2). -+ \param[out] p_netif Pointer to the bridge member network interface structure to which the packet needs to be forwarded. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, if the lookup is successful in the bridge forwarding database. \n -+ - IFX_FAILURE, if the lookup is not successful.\n -+ \note -+*/ -+ int32_t ppa_get_br_dst_port(PPA_NETIF *netif, PPA_BUF *buf, PPA_NETIF **p_netif); -+ -+ -+ -+/*! \brief This function performs a bridge forwarding database lookup for the bridge specified by netif and returns the member interface on which the packet needs to be forwarded. -+ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. -+ \param[in] mac Pointer to destination mac address. -+ \param[out] p_netif Pointer to the bridge member network interface structure to which the packet needs to be forwarded. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, if the lookup is successful in the bridge forwarding database. \n -+ - IFX_FAILURE, if the lookup is not successful. -+\note -+*/ -+ int32_t ppa_get_br_dst_port_with_mac(PPA_NETIF *netif, uint8_t mac[PPA_ETH_ALEN], PPA_NETIF **p_netif); -+ -+ -+/*! \brief This function returns the PPA ATM VC structure for the EoATM (RFC 2684 Ethernet over ATM) interface specified by netif. -+ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. -+ \param[in] pvcc Pointer to the pointer to PPA_VCC structure which is set to the VC associated with the EoATM interface specified by netif. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, if the VCC structure is found for the EoATM interface \n -+ - IFX_FAILURE, on error -+\note -+*/ -+ int32_t ppa_br2684_get_vcc(PPA_NETIF *netif, PPA_VCC **pvcc); -+ -+ -+ -+ -+ /*! \brief This function checks if the interface specified by netif or ifname pointers is an EoATM interface as per RFC2684. The interface will be specified by passing one of netif and ifname in the call. -+ \param[in] netif Pointer to the network interface structure for the EoATM check is to be performed. -+ \param[in] ifname Pointer to the interface name for which the EoATM check is to be performed. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE, if the interface is an EoATM interface. \n -+ - IFX_FALSE, if the interface is not an EoATM interface. \n -+\note -+*/ -+int32_t ppa_if_is_br2684(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+/*! \brief This function checks if the interface specified by netif or ifname pointers is bridged or routed encapsulaton. -+ \param[in] netif Pointer to the network interface structure for the check is to be performed. -+ \param[in] ifname Pointer to the interface name for which the check is to be performed. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, Interface is enabled with IP encapsulation. \n -+ - IFX_FAILURE, Error. -+\note -+*/ -+int32_t ppa_if_is_ipoa(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+ -+ -+/*! \brief This function returns the PPA ATM VC structure for the PPPoA (RFC 2364 PPP over AAL5) interface specified by netif. -+ \param[in] netif Pointer to the network interface structure for the bridge interface where destination lookup is to be performed. -+ \param[out] patmvcc Pointer to the pointer to PPA_VCC structure which is set to the VC associated with the PPPoATM interface specified by netif. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, if the VCC structure is found for the PPPoATM interface. \n -+ - IFX_FAILURE, on error. -+\note -+*/ -+int32_t ppa_pppoa_get_vcc(PPA_NETIF *netif, PPA_VCC **patmvcc); -+ -+ -+/*! \brief check whether it is a pppoa session. -+ \param[in] netif Pointer to the interface's netif -+ \param[in] ifname Pointer to interface name -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the two session pointers are the same. \n -+ - IFX_FALSE if the two session pointers point to different sessions. \n -+ \note, one of netif and ifname should be not NULL. -+*/ -+ int32_t ppa_if_is_pppoa(PPA_NETIF *netif, PPA_IFNAME *ifname); -+ -+ -+/*! \brief Returns true if the two sessions are the same. -+ \param[in] p_session1 Pointer to the PPA session 1. -+ \param[in] p_session2 Pointer to the PPA session 2. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the two session pointers are the same. \n -+ - IFX_FALSE if the two session pointers point to different sessions. \n -+\note -+*/ -+ uint32_t ppa_is_session_equal(PPA_SESSION *p_session1, PPA_SESSION *p_session2); -+ -+ -+ -+/*! \brief Get the Stack session Helper function for connection tracking. Such helper functions exist when a Connection tracking / SPI logic for the application protocol of that session. Examples are FTP control session, SIP signalling session etc. -+ \param[in] p_session Pointer to the PPA Session. -+ \return This function returns the one of the following values: \n -+ - Pointer to the session helper function as an uint32_t if helper exists. \n -+ - NULL otherwise. \n -+ \note The exact pointer of the session helper function is not of interest to PPA. Adaptations may just return IFX_TRUE if session has helper function, and return IFX_FALSE otherwise. -+*/ -+ uint32_t ppa_get_session_helper(PPA_SESSION *p_session); -+ -+ -+ -+/*! \brief Is the PPA session pointing to a special session which needs "slow path" handling due to protocol processing requirements of connection tracking, NAT or by any other criteria. Examples are FTP control session, SIP signalling session etc.The API can check the session based on either a PPA buffer pointer or a PPA session pointer. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \param[in] p_session Pointer to the PPA Session. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the session is a special session. \n -+ - IFX_FALSE otherwise\note. \n -+ \note -+*/ -+ uint32_t ppa_check_is_special_session(PPA_BUF *ppa_buf, PPA_SESSION *p_session); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is a fragmented IP datagram. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is fragment of an IP datagram. \n -+ - IFX_FALSE if the packet is a non-fragmented IP datagram. \n -+ \note -+*/ -+ uint32_t ppa_is_pkt_fragment(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is addressed to the host (i.e. terminated inside the router). -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is addressed to host, i.e. for host output. \n -+ - IFX_FALSE if the packet is to be forwarded out of the router. \n -+ \note -+*/ -+ int32_t ppa_is_pkt_host_output(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is a broadcast packet. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is a broadcast packet. \n -+ - IFX_FALSE if the packet is not a broadcast packet. \n -+ \note -+*/ -+ int32_t ppa_is_pkt_broadcast(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is a multicast packet. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if the packet is a multicast packet. \n -+ - IFX_FALSE otherwise. \n -+ \note -+*/ -+ int32_t ppa_is_pkt_multicast(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is a loopback packet, i.e. output to a loopback interface in the router (and not transmitted out of the router external interfaces). -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is a loopback packet. \n -+ - IFX_FALSE if the packet is not a loopback packet \n -+ \note -+*/ -+ int32_t ppa_is_pkt_loopback(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is for local delivery, i.e. ingress packet delivered to Layer-4 and above).. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is for local delivery to Layer-4 and above. \n -+ - IFX_FALSE if the packet is not a local delivery packet. \n -+ \note -+*/ -+ int32_t ppa_is_pkt_local(PPA_BUF *ppa_buf); -+ -+ -+ -+ /*! \brief Returns if the packet pointed to by ppa_buf is routed, i.e. forwarded at IP layer. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is forwarded at IP layer. \n -+ - IFX_FALSE if the packet is not forwarded at IP layer \n -+ \note -+*/ -+ int32_t ppa_is_pkt_routing(PPA_BUF *ppa_buf); -+ -+ -+ -+/*! \brief Returns if the packet pointed to by ppa_buf is multicast routed. -+ \param[in] ppa_buf Pointer to the PPA Buffer. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if packet is multicast forwarded at IP layer. \n -+ - IFX_FALSE if the packet is not multicast forwarded at IP layer. \n -+ \note -+*/ -+ int32_t ppa_is_pkt_mc_routing(PPA_BUF *ppa_buf); -+ -+ -+ -+ /*! \brief Returns true if tcp connection state is established for a PPA session. -+ \param[in] p_session Pointer to ppa connection tracking session data structure. -+ \return This function returns the one of the following values: \n -+ - IFX_TRUE if TCP connection state is established after SYN from server. \n -+ - IFX_FALSE if TCP connection is not established completely. \n -+ \note -+*/ -+ int32_t ppa_is_tcp_established(PPA_SESSION *p_session); -+ -+ -+ /*! \brief check whether the TCP session is open or not. -+ \param[in] p_session Pointer to ppa connection tracking session data structure. -+ \return This function returns the one of the following values: \n -+ - 1 if the tcp state is not TIME_WAIT or error -+ - otherwise, return 0 -+ \note -+*/ -+ int32_t ppa_is_tcp_open(PPA_SESSION *p_session); -+ -+ -+ -+/*! \brief Initialize a lock for synchronization. -+ \param[in] p_lock Pointer to the PPA lock variable which is allocated by the caller. -+ \return This function returns the one of the following values: \n -+ - IFX_SUCCESS, if PPA Lock initialization is success. \n -+ - IFX_FAILURE, if the PPA Lock initialization fails. \n -+ \note -+*/ -+ int32_t ppa_lock_init(PPA_LOCK *p_lock); -+ -+/*! \brief Get or Acquire a PPA lock for synchronization. -+ \param[in] p_lock Pointer to the PPA lock variable which has been already initialized by the caller. -+ \return No value returned. -+ \note -+*/ -+ void ppa_lock_get(PPA_LOCK *p_lock); -+ -+ -+/*! \brief Release a PPA Lock acquired for synchronization. -+ \param[in] p_lock Pointer to the PPA lock variable which is to be released by the caller.. -+ \return No valure returned. -+ \note -+*/ -+ void ppa_lock_release(PPA_LOCK *p_lock); -+ -+ -+/*! \brief Destroy a PPA lock created with the ppa_lock_init API -+ \param[in] p_lock Pointer to the PPA lock variable which is allocated by the caller. -+ \return No valure returned. -+ \note -+*/ -+ void ppa_lock_destroy(PPA_LOCK *p_lock); -+ -+ -+/*! \brief Disable interrupt processing to protect certain PPA critical regions and save current interrupt state to a global variable in the AL. -+ \return No valure returned. -+ \note -+*/ -+uint32_t ppa_disable_int(void); -+ -+ -+/*! \brief Enable interrupt processing to protect certain PPA critical regions. This must actually restore interrupt status from the last ppa_disable_int call. -+ \param[in] flag Interrupt status flag. -+ \return No valure returned. -+ \note -+*/ -+void ppa_enable_int(uint32_t flag); -+ -+ -+/*! \brief This function dynamically allocates memory for PPA use. -+ \param[in] size Specifies the number of bytes to be allocated. -+ \return The return value is one of the following: \n -+ - Non-NULL value, if memory allocation is successful. \n -+ - NULL, if the PPA Lock initialization fails. \n -+ \note -+*/ -+ void *ppa_malloc(uint32_t size); -+ -+/*! \brief This function frees dynamically allocated memory. -+ \param[in] buff Pointer to buffer allocated by ppa_malloc routine, which needs to be freed. -+ \return The return value is one of the following: \n -+ - IFX_SUCCESS, if memory free is successful. \n -+ - IFX_FAILURE, if the memory free operation fails. \n -+ \note -+*/ -+ int32_t ppa_free(void *buff); -+ -+ -+ -+ /*! \brief This function dynamically allocates memory for a cache of objects of a fixed size for PPA use. -+ \param[in] name Specifies the name of the memory cache as a string. -+ \param[in] size Specifies the object size in bytes for the memory cache to be created. -+ \param[out] pp_cache Pointer to pointer to the memory cache to be created. *pp_cache is set by the function. -+ \return The return value is one of the following: \n -+ - IFX_SUCCESS value, if memory cache creation is successful. \n -+ - IFX_FAILURE, if the memory cache creation fails. \n -+ \note -+*/int32_t ppa_mem_cache_create(const char *name, uint32_t size, PPA_MEM_CACHE **pp_cache); -+ -+ -+ /*! \brief This function frees (or destroys) dynamically created memory cache using ppa_mem_cache_create API. -+ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, which needs to be destroyed. -+ \return The return value is one of the following: \n -+ - IFX_SUCCESS, if memory cache is destroyed. \n -+ - IFX_FAILURE, if the memory cache free operation fails \n -+ \note -+*/ -+int32_t ppa_mem_cache_destroy(PPA_MEM_CACHE *p_cache); -+ -+ -+/*! \brief This function allocates a memory cache object from the specified memory cache created using ppa_mem_cache_create API. -+ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, to which an object needs to be freed. -+ \return No return value. -+ \note -+*/ -+ void *ppa_mem_cache_alloc(PPA_MEM_CACHE *p_cache); -+ -+ -+/*! \brief This function frees (or returns) allocated memory cache object using ppa_mem_cache_alloc API back to the memory cache pool. -+ \param[in] buf Pointer to memory cache object allocated from memory cache pointed to by p_cache pointer. -+ \param[in] p_cache Pointer to memory cache created by ppa_mem_cache_create routine, which needs to be destroyed. -+ \return The return value is one of the following: \n -+ - IFX_SUCCESS, if memory cache is destroyed. \n -+ - IFX_FAILURE, if the memory cache free operation fails. \n -+ \note -+*/ -+void ppa_mem_cache_free(void *buf, PPA_MEM_CACHE *p_cache); -+ -+ -+/*! \brief This function does a byte copy from source buffer to destination buffer for the specified number of bytes. -+ \param[in] dst Pointer to destination buffer to copy to. -+ \param[in] src Pointer to source buffer to copy from. -+ \param[in] count Specifies the number of bytes to copy. -+ \return No return value. -+ \note -+*/ -+ void ppa_memcpy(void *dst, const void *src, uint32_t count); -+ -+ -+ /*! \brief This function does a byte set to destination buffer with the specified fill byte for the specified number of bytes.. -+ \param[in] dst Pointer to destination buffer to set bytes. -+ \param[in] fillbyte Byte value to fill in the destination buffer. -+ \param[in] count Specifies the number of bytes to set to fillbyte. -+ \return No return value. -+ \note -+*/ -+ void ppa_memset(void *dst, uint32_t fillbyte, uint32_t count); -+ -+ /*! \brief This function compares the memory areas buff1 and buff2 for specified number of bytes. -+ \param[in] buff1 Pointer to destination first buffer. -+ \param[in] buff2 Pointer to source second buffer. -+ \param[in] count Specifies the number of bytes to compare. -+ \return Returns an integer less than, equal to, or greater than zero if the first n bytes of buff1 is found, respectively, to be less than, to match, or be greater than the first n bytes of buff2. -+ \note -+*/ -+ int ppa_memcmp(const void *buff1, const void *buff2, size_t count); -+ -+/*! \brief This function initializes the PPA_TIMER structure and fills in the callback function which is to be invoked by the timer facility when the timer expires. The PPA timer facility is a "one-shot" timer and not a periodic one. -+ \param[in] p_timer Pointer to the PPA_TIMER structure allocated by caller. -+ \param[in] callback Timer callback function that is invoked when the timer expires. -+ \return The function returns one of the following values: \n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. \n -+ \note -+*/ -+int32_t ppa_timer_init(PPA_TIMER *p_timer, void (*callback)(unsigned long)); -+ -+/*! \brief This function adds or installs a timer with the specified timer interval. -+ \param[in] p_timer Pointer to the initialized PPA_TIMER structure to be installed. -+ \param[in] timeout_in_sec Timer expiry interval in seconds after which the one-shot timer will fire. -+ \return The function returns one of the following values: \n -+ - IFX_SUCCESS, on success. \n -+ - IFX_FAILURE, on error. \n -+ \note -+*/ -+int32_t ppa_timer_add(PPA_TIMER *p_timer, uint32_t timeout_in_sec); -+ -+ -+/*! \brief This function deletes an install timer which has not yet expired. -+ \param[in] p_timer Pointer to the installed PPA_TIMER structure to be deleted. -+ \return The function returns one of the following values: \n -+ - IFX_SUCCESS, on successful deletion of the timer. \n -+ - IFX_FAILURE, on error (for eg., timer already expired, or invalid timer pointer). \n -+ \note -+*/ -+void ppa_timer_del(PPA_TIMER *p_timer); -+ -+ -+/*! \brief This function adds or installs a timer with the specified timer interval. -+ \return The function returns the following value: \n -+ - Current time in 10 milliseconds resolution. -+ \note -+*/ -+ uint32_t ppa_get_time_in_10msec(void); -+ -+/*! \brief This function returns the current time of the system in seconds. It can be the time since reboot of the system, or an absolute time wrt NTP synced world time. PPA uses this function for timing intervals or periods. -+ \return The function returns the following values: \n -+ - Current time in seconds \n -+ \note -+*/ -+ uint32_t ppa_get_time_in_sec(void); -+ -+ -+/*! \brief Read atomic variable. -+ \param[in] v Pointer to the PPA atomic variable which is to be read. -+ \return No return value. -+ \note -+*/ -+ int32_t ppa_atomic_read(PPA_ATOMIC *v); -+ -+/*! \brief Initialize the PPA atomic variable to specified value. -+ \param[in] v Pointer to the PPA atomic variable which is to be initalized. -+ \param[in] i Intended value to be set for atomic variable p_atomic. -+ \return No return value. -+ \note -+*/ -+ void ppa_atomic_set(PPA_ATOMIC *v, int32_t i); -+ -+/*! \brief Atomic Increment of variable. -+ \param[in] v Pointer to the PPA atomic variable which is to be incremented. -+ \return No return value. -+ \note -+*/ -+ int32_t ppa_atomic_inc(PPA_ATOMIC *v); -+ -+/*! \brief Atomic decrement of variable. -+ \param[in] v Pointer to the PPA atomic variable which is to be decremented. -+ \return No return value. -+ \note -+*/ -+int32_t ppa_atomic_dec(PPA_ATOMIC *v); -+ -+/*! \brief Used to perform buffer cloning. -+ \param[in] ppa_buf Pointer to ppa buffer. -+ \param[in] flags Reserved for future use. -+ \return The return value is the pointer to cloned PPA buffer structure. -+ \note -+*/ -+ PPA_BUF *ppa_buf_clone(PPA_BUF *ppa_buf, uint32_t flags); -+ -+ -+ -+/*! \brief Used to check if the buffer is cloned. -+ \param[in] ppa_buf Pointer to ppa buffer. -+ \return The return value is IFX_TRUE if the buffer is cloned and IFX_FLASE otherwise. -+ \note -+*/ -+int32_t ppa_buf_cloned(PPA_BUF *ppa_buf); -+ -+ -+/*! \brief get ppa prevous buffer -+ \param[in] ppa_buf Pointer to ppa buffer. -+ \return return the prevois buffer -+ \note -+*/ -+ PPA_BUF *ppa_buf_get_prev(PPA_BUF *ppa_buf); -+ -+/*! \brief get ppa next buffer -+ \param[in] ppa_buf Pointer to ppa buffer. -+ \return return the next buffer -+ \note -+*/ -+ PPA_BUF *ppa_buf_get_next(PPA_BUF *ppa_buf); -+ -+/*! \brief free ppa buffer -+ \param[in] ppa_buf Pointer to ppa buffer . -+ \note -+*/ -+ void ppa_buf_free(PPA_BUF *ppa_buf); -+ -+/*! \brief copy data from username to kernel -+ \param[out] to destination buffer -+ \param[in] from source buffer -+ \param[in] n bytes to copy -+ \note -+*/ -+ uint32_t ppa_copy_from_user(void *to, const void PPA_USER *from, uint32_t n); -+ -+/*! \brief copy data from kernel to username -+ \param[out] to destination buffer -+ \param[in] from source buffer -+ \param[in] n bytes to copy -+ \note -+*/ -+ uint32_t ppa_copy_to_user(void PPA_USER *to, const void *from, uint32_t n); -+ -+/*! \brief copy string, like strcpy -+ \param[out] dest destination buffer -+ \param[in] src source buffer -+ \note -+*/ -+ uint8_t *ppa_strcpy(uint8_t *dest, const uint8_t *src); -+ -+/*! \brief copy string, like strncpy -+ \param[out] dest destination buffer -+ \param[in] src source buffer -+ \param[in] n maximum bytes to copy -+ \note -+*/ -+ uint8_t *ppa_strncpy(uint8_t *dest, const uint8_t *src, PPA_SIZE_T n); -+ -+/*! \brief get string length, like strlen -+ \param[in] s string buffer -+ \return return the string length -+ \note -+*/ -+ PPA_SIZE_T ppa_strlen(const uint8_t *s); -+ -+/*! \brief shrink cache buffer. in linux, it is kmem_cache_shrink -+ \param[in] p_cache Pointer to cache buffer -+ \return return the string length -+ \note -+*/ -+ int32_t ppa_kmem_cache_shrink(PPA_MEM_CACHE *p_cache); -+ -+/*! \brief lookup symble. In linux, it is kallsyms_lookup -+ \note -+*/ -+ const uint8_t *ppa_kallsyms_lookup(uint32_t addr, uint32_t *symbolsize, uint32_t *offset, uint8_t **modname, uint8_t *namebuf); -+ -+/*! \brief register network device, in linux, it is register_netdev -+ \param[in] dev pointer to network device -+ \return -+ \note -+*/ -+ int32_t ppa_register_netdev(PPA_NETIF *dev); -+ -+/*! \brief unregister network device, in linux, it is unregister_netdev -+ \param[in] dev pointer to network device -+ \return -+ \note -+*/ -+ void ppa_unregister_netdev(PPA_NETIF *dev); -+ -+/*! \brief register char devide, in linux, it is register_chrdev -+ \param[in] major Character device major version -+ \param[in] name Character device name -+ \param[in] fops Character device operation pointer -+ \return -+ \note -+*/ -+ int32_t ppa_register_chrdev(int32_t major, const uint8_t *name, PPA_FILE_OPERATIONS *fops); -+ -+/*! \brief unregister char devide, in linux, it is unregister_chrdev -+ \param[in] major char device major version -+ \param[in] name char device name -+ \return -+ \note -+*/ -+ void ppa_unregister_chrdev(int32_t major, const uint8_t *name); -+ -+/*! \brief format a string to buffer, in linux, it is snprintf -+ \return -+ \note -+*/ -+ int ppa_snprintf(uint8_t* buf, size_t size, const uint8_t *fmt, ...); -+ -+/*! \brief format a string to buffer, in linux, it is sprintf -+ \return -+ \note -+*/ -+ int ppa_sprintf(uint8_t * buf, const uint8_t *fmt, ...); -+ -+/*! \brief get ioctl type, in linux, it is _IOC_TYPE -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_type(uint32_t); -+ -+/*! \brief get ioctl nr, in linux, it is _IOC_NR -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_nr(uint32_t); -+ -+/*! \brief get ioctl dir, in linux, it is _IOC_DIR -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_dir(uint32_t); -+ -+/*! \brief get ioctl read flag, in linux, it is _IOC_READ -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_read(void); -+ -+/*! \brief get ioctl write flag, in linux, it is _IOC_WRITE -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_write(void); -+ -+/*! \brief get ioctl size, in linux, it is _IOC_SIZE -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_size(uint32_t); -+ -+/*! \brief check ioctl access right, in linux, it is access_ok -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_access_ok(uint32_t type, uint32_t addr, uint32_t size); -+ -+/*! \brief get ioctl verify write flag, in linux it is VERIFY_WRITE -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_verify_write(void); -+ -+/*! \brief get ioctl verify read flag, in linux it is VERIFY_READ -+ \return -+ \note -+*/ -+ uint32_t ppa_ioc_verify_read(void); -+ -+/*! \brief print format string, in linux it is printk -+ \return -+ \note -+*/ -+ int32_t ppa_printk(const char *fmt, ...); -+ -+/*! \brief get egress qos mask -+ \param dev pointer to net device structure. -+ \param buf pointer to buffer. -+ \return -+ \note -+*/ -+ uint16_t ppa_vlan_dev_get_egress_qos_mask(PPA_NETIF *dev, PPA_BUF *buf); -+ -+#endif // __KERNEL__ -+/* @} */ -+ -+ -+#endif // __IFX_PPA_STACK_AL_H__20081103_1153__ -diff --git a/include/net/ipv6.h b/include/net/ipv6.h -index e4170a2..503c16f 100644 ---- a/include/net/ipv6.h -+++ b/include/net/ipv6.h -@@ -299,6 +299,11 @@ static inline int ipv6_addr_cmp(const struct in6_addr *a1, const struct in6_addr - return memcmp(a1, a2, sizeof(struct in6_addr)); - } - -+static inline void ipv6_addr_copy(struct in6_addr *a1, const struct in6_addr *a2) -+{ -+ memcpy(a1, a2, sizeof(struct in6_addr)); -+} -+ - static inline int - ipv6_masked_addr_cmp(const struct in6_addr *a1, const struct in6_addr *m, - const struct in6_addr *a2) -diff --git a/include/switch_api/AR9.h b/include/switch_api/AR9.h -new file mode 100644 -index 0000000..7cf8d3e ---- /dev/null -+++ b/include/switch_api/AR9.h -@@ -0,0 +1,4342 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ *****************************************************************************/ -+ -+#ifndef _AR9_H -+#define _AR9_H -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port Status Register' */ -+/* Bit: 'P1FCS' */ -+/* Description: 'Port 1 Flow Control Status' */ -+#define AR9_PS_REG_P1FCS_OFFSET 0x0000 -+#define AR9_PS_REG_P1FCS_SHIFT 12 -+#define AR9_PS_REG_P1FCS_SIZE 1 -+/* Bit: 'P1DS' */ -+/* Description: 'Port 1 Duplex Status' */ -+#define AR9_PS_REG_P1DS_OFFSET 0x0000 -+#define AR9_PS_REG_P1DS_SHIFT 11 -+#define AR9_PS_REG_P1DS_SIZE 1 -+/* Bit: 'P1SHS' */ -+/* Description: 'Port 1 Speed High Status' */ -+#define AR9_PS_REG_P1SHS_OFFSET 0x0000 -+#define AR9_PS_REG_P1SHS_SHIFT 10 -+#define AR9_PS_REG_P1SHS_SIZE 1 -+/* Bit: 'P1SS' */ -+/* Description: 'Port 1 Speed Status' */ -+#define AR9_PS_REG_P1SS_OFFSET 0x0000 -+#define AR9_PS_REG_P1SS_SHIFT 9 -+#define AR9_PS_REG_P1SS_SIZE 1 -+/* Bit: 'P1LS' */ -+/* Description: 'Port 1 Link Status' */ -+#define AR9_PS_REG_P1LS_OFFSET 0x0000 -+#define AR9_PS_REG_P1LS_SHIFT 8 -+#define AR9_PS_REG_P1LS_SIZE 1 -+/* Bit: 'P0FCS' */ -+/* Description: 'Port 0 Flow Control Status' */ -+#define AR9_PS_REG_P0FCS_OFFSET 0x0000 -+#define AR9_PS_REG_P0FCS_SHIFT 4 -+#define AR9_PS_REG_P0FCS_SIZE 1 -+/* Bit: 'P0DS' */ -+/* Description: 'Port 0 Duplex Status' */ -+#define AR9_PS_REG_P0DS_OFFSET 0x0000 -+#define AR9_PS_REG_P0DS_SHIFT 3 -+#define AR9_PS_REG_P0DS_SIZE 1 -+/* Bit: 'P0SHS' */ -+/* Description: 'Port 0 Speed High Status' */ -+#define AR9_PS_REG_P0SHS_OFFSET 0x0000 -+#define AR9_PS_REG_P0SHS_SHIFT 2 -+#define AR9_PS_REG_P0SHS_SIZE 1 -+/* Bit: 'P0SS' */ -+/* Description: 'Port 0 Speed Status' */ -+#define AR9_PS_REG_P0SS_OFFSET 0x0000 -+#define AR9_PS_REG_P0SS_SHIFT 1 -+#define AR9_PS_REG_P0SS_SIZE 1 -+/* Bit: 'P0LS' */ -+/* Description: 'Port 0 Link Status' */ -+#define AR9_PS_REG_P0LS_OFFSET 0x0000 -+#define AR9_PS_REG_P0LS_SHIFT 0 -+#define AR9_PS_REG_P0LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P0 Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define AR9_P0_CTL_REG_SPS_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_SPS_SHIFT 30 -+#define AR9_P0_CTL_REG_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define AR9_P0_CTL_REG_TCPE_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_TCPE_SHIFT 29 -+#define AR9_P0_CTL_REG_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define AR9_P0_CTL_REG_IPOVTU_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_IPOVTU_SHIFT 28 -+#define AR9_P0_CTL_REG_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define AR9_P0_CTL_REG_VPE_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_VPE_SHIFT 27 -+#define AR9_P0_CTL_REG_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define AR9_P0_CTL_REG_SPE_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_SPE_SHIFT 26 -+#define AR9_P0_CTL_REG_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define AR9_P0_CTL_REG_IPVLAN_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_IPVLAN_SHIFT 25 -+#define AR9_P0_CTL_REG_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define AR9_P0_CTL_REG_TPE_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_TPE_SHIFT 24 -+#define AR9_P0_CTL_REG_TPE_SIZE 1 -+/* Bit: 'DFWD' */ -+/* Description: 'Port Ingress Direct Forwarding' */ -+#define AR9_P0_CTL_REG_DFWD_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_DFWD_SHIFT 19 -+#define AR9_P0_CTL_REG_DFWD_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define AR9_P0_CTL_REG_FLP_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_FLP_SHIFT 18 -+#define AR9_P0_CTL_REG_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define AR9_P0_CTL_REG_FLD_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_FLD_SHIFT 17 -+#define AR9_P0_CTL_REG_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define AR9_P0_CTL_REG_RMWFQ_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_RMWFQ_SHIFT 16 -+#define AR9_P0_CTL_REG_RMWFQ_SIZE 1 -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define AR9_P0_CTL_REG_AD_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_AD_SHIFT 15 -+#define AR9_P0_CTL_REG_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define AR9_P0_CTL_REG_LD_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_LD_SHIFT 14 -+#define AR9_P0_CTL_REG_LD_SIZE 1 -+/* Bit: 'REDIR' */ -+/* Description: 'Port Redirect Option' */ -+#define AR9_P0_CTL_REG_REDIR_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_REDIR_SHIFT 13 -+#define AR9_P0_CTL_REG_REDIR_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define AR9_P0_CTL_REG_MNA024_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_MNA024_SHIFT 8 -+#define AR9_P0_CTL_REG_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define AR9_P0_CTL_REG_PPPOEP_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_PPPOEP_SHIFT 7 -+#define AR9_P0_CTL_REG_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define AR9_P0_CTL_REG_PM_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_PM_SHIFT 6 -+#define AR9_P0_CTL_REG_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define AR9_P0_CTL_REG_IPMO_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_IPMO_SHIFT 4 -+#define AR9_P0_CTL_REG_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define AR9_P0_CTL_REG_PAS_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_PAS_SHIFT 2 -+#define AR9_P0_CTL_REG_PAS_SIZE 2 -+/* Bit: 'DSV8021x' */ -+/* Description: 'Drop Scheme for violation 802.1x' */ -+#define AR9_P0_CTL_REG_DSV8021X_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_DSV8021X_SHIFT 1 -+#define AR9_P0_CTL_REG_DSV8021X_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define AR9_P0_CTL_REG_BYPASS_OFFSET 0x0004 -+#define AR9_P0_CTL_REG_BYPASS_SHIFT 0 -+#define AR9_P0_CTL_REG_BYPASS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P1 Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define AR9_P1_CTL_REG_SPS_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_SPS_SHIFT 30 -+#define AR9_P1_CTL_REG_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define AR9_P1_CTL_REG_TCPE_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_TCPE_SHIFT 29 -+#define AR9_P1_CTL_REG_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define AR9_P1_CTL_REG_IPOVTU_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_IPOVTU_SHIFT 28 -+#define AR9_P1_CTL_REG_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define AR9_P1_CTL_REG_VPE_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_VPE_SHIFT 27 -+#define AR9_P1_CTL_REG_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define AR9_P1_CTL_REG_SPE_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_SPE_SHIFT 26 -+#define AR9_P1_CTL_REG_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define AR9_P1_CTL_REG_IPVLAN_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_IPVLAN_SHIFT 25 -+#define AR9_P1_CTL_REG_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define AR9_P1_CTL_REG_TPE_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_TPE_SHIFT 24 -+#define AR9_P1_CTL_REG_TPE_SIZE 1 -+/* Bit: 'DFWD' */ -+/* Description: 'Port Ingress Direct Forwarding' */ -+#define AR9_P1_CTL_REG_DFWD_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_DFWD_SHIFT 19 -+#define AR9_P1_CTL_REG_DFWD_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define AR9_P1_CTL_REG_FLP_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_FLP_SHIFT 18 -+#define AR9_P1_CTL_REG_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define AR9_P1_CTL_REG_FLD_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_FLD_SHIFT 17 -+#define AR9_P1_CTL_REG_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define AR9_P1_CTL_REG_RMWFQ_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_RMWFQ_SHIFT 16 -+#define AR9_P1_CTL_REG_RMWFQ_SIZE 1 -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define AR9_P1_CTL_REG_AD_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_AD_SHIFT 15 -+#define AR9_P1_CTL_REG_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define AR9_P1_CTL_REG_LD_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_LD_SHIFT 14 -+#define AR9_P1_CTL_REG_LD_SIZE 1 -+/* Bit: 'REDIR' */ -+/* Description: 'Port Redirect Option' */ -+#define AR9_P1_CTL_REG_REDIR_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_REDIR_SHIFT 13 -+#define AR9_P1_CTL_REG_REDIR_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define AR9_P1_CTL_REG_MNA024_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_MNA024_SHIFT 8 -+#define AR9_P1_CTL_REG_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define AR9_P1_CTL_REG_PPPOEP_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_PPPOEP_SHIFT 7 -+#define AR9_P1_CTL_REG_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define AR9_P1_CTL_REG_PM_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_PM_SHIFT 6 -+#define AR9_P1_CTL_REG_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define AR9_P1_CTL_REG_IPMO_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_IPMO_SHIFT 4 -+#define AR9_P1_CTL_REG_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define AR9_P1_CTL_REG_PAS_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_PAS_SHIFT 2 -+#define AR9_P1_CTL_REG_PAS_SIZE 2 -+/* Bit: 'DSV8021x' */ -+/* Description: 'Drop Scheme for violation 802.1x' */ -+#define AR9_P1_CTL_REG_DSV8021X_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_DSV8021X_SHIFT 1 -+#define AR9_P1_CTL_REG_DSV8021X_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define AR9_P1_CTL_REG_BYPASS_OFFSET 0x0008 -+#define AR9_P1_CTL_REG_BYPASS_SHIFT 0 -+#define AR9_P1_CTL_REG_BYPASS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P2 Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define AR9_P2_CTL_REG_SPS_OFFSET 0x000C -+#define AR9_P2_CTL_REG_SPS_SHIFT 30 -+#define AR9_P2_CTL_REG_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define AR9_P2_CTL_REG_TCPE_OFFSET 0x000C -+#define AR9_P2_CTL_REG_TCPE_SHIFT 29 -+#define AR9_P2_CTL_REG_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define AR9_P2_CTL_REG_IPOVTU_OFFSET 0x000C -+#define AR9_P2_CTL_REG_IPOVTU_SHIFT 28 -+#define AR9_P2_CTL_REG_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define AR9_P2_CTL_REG_VPE_OFFSET 0x000C -+#define AR9_P2_CTL_REG_VPE_SHIFT 27 -+#define AR9_P2_CTL_REG_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define AR9_P2_CTL_REG_SPE_OFFSET 0x000C -+#define AR9_P2_CTL_REG_SPE_SHIFT 26 -+#define AR9_P2_CTL_REG_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define AR9_P2_CTL_REG_IPVLAN_OFFSET 0x000C -+#define AR9_P2_CTL_REG_IPVLAN_SHIFT 25 -+#define AR9_P2_CTL_REG_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define AR9_P2_CTL_REG_TPE_OFFSET 0x000C -+#define AR9_P2_CTL_REG_TPE_SHIFT 24 -+#define AR9_P2_CTL_REG_TPE_SIZE 1 -+/* Bit: 'DFWD' */ -+/* Description: 'Port Ingress Direct Forwarding' */ -+#define AR9_P2_CTL_REG_DFWD_OFFSET 0x000C -+#define AR9_P2_CTL_REG_DFWD_SHIFT 19 -+#define AR9_P2_CTL_REG_DFWD_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define AR9_P2_CTL_REG_FLP_OFFSET 0x000C -+#define AR9_P2_CTL_REG_FLP_SHIFT 18 -+#define AR9_P2_CTL_REG_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define AR9_P2_CTL_REG_FLD_OFFSET 0x000C -+#define AR9_P2_CTL_REG_FLD_SHIFT 17 -+#define AR9_P2_CTL_REG_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define AR9_P2_CTL_REG_RMWFQ_OFFSET 0x000C -+#define AR9_P2_CTL_REG_RMWFQ_SHIFT 16 -+#define AR9_P2_CTL_REG_RMWFQ_SIZE 1 -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define AR9_P2_CTL_REG_AD_OFFSET 0x000C -+#define AR9_P2_CTL_REG_AD_SHIFT 15 -+#define AR9_P2_CTL_REG_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define AR9_P2_CTL_REG_LD_OFFSET 0x000C -+#define AR9_P2_CTL_REG_LD_SHIFT 14 -+#define AR9_P2_CTL_REG_LD_SIZE 1 -+/* Bit: 'REDIR' */ -+/* Description: 'Port Redirect Option' */ -+#define AR9_P2_CTL_REG_REDIR_OFFSET 0x000C -+#define AR9_P2_CTL_REG_REDIR_SHIFT 13 -+#define AR9_P2_CTL_REG_REDIR_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define AR9_P2_CTL_REG_MNA024_OFFSET 0x000C -+#define AR9_P2_CTL_REG_MNA024_SHIFT 8 -+#define AR9_P2_CTL_REG_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define AR9_P2_CTL_REG_PPPOEP_OFFSET 0x000C -+#define AR9_P2_CTL_REG_PPPOEP_SHIFT 7 -+#define AR9_P2_CTL_REG_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define AR9_P2_CTL_REG_PM_OFFSET 0x000C -+#define AR9_P2_CTL_REG_PM_SHIFT 6 -+#define AR9_P2_CTL_REG_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define AR9_P2_CTL_REG_IPMO_OFFSET 0x000C -+#define AR9_P2_CTL_REG_IPMO_SHIFT 4 -+#define AR9_P2_CTL_REG_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define AR9_P2_CTL_REG_PAS_OFFSET 0x000C -+#define AR9_P2_CTL_REG_PAS_SHIFT 2 -+#define AR9_P2_CTL_REG_PAS_SIZE 2 -+/* Bit: 'DSV8021x' */ -+/* Description: 'Drop Scheme for violation 802.1x' */ -+#define AR9_P2_CTL_REG_DSV8021X_OFFSET 0x000C -+#define AR9_P2_CTL_REG_DSV8021X_SHIFT 1 -+#define AR9_P2_CTL_REG_DSV8021X_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define AR9_P2_CTL_REG_BYPASS_OFFSET 0x000C -+#define AR9_P2_CTL_REG_BYPASS_SHIFT 0 -+#define AR9_P2_CTL_REG_BYPASS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 VLAN Control Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define AR9_P0_VLAN_REG_DFID_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_DFID_SHIFT 30 -+#define AR9_P0_VLAN_REG_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define AR9_P0_VLAN_REG_TBVE_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_TBVE_SHIFT 29 -+#define AR9_P0_VLAN_REG_TBVE_SIZE 1 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define AR9_P0_VLAN_REG_IFNTE_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_IFNTE_SHIFT 28 -+#define AR9_P0_VLAN_REG_IFNTE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define AR9_P0_VLAN_REG_VC_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_VC_SHIFT 27 -+#define AR9_P0_VLAN_REG_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define AR9_P0_VLAN_REG_VSD_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_VSD_SHIFT 26 -+#define AR9_P0_VLAN_REG_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define AR9_P0_VLAN_REG_AOVTP_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_AOVTP_SHIFT 25 -+#define AR9_P0_VLAN_REG_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define AR9_P0_VLAN_REG_VMCE_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_VMCE_SHIFT 24 -+#define AR9_P0_VLAN_REG_VMCE_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Default VLAN Port Map' */ -+#define AR9_P0_VLAN_REG_DVPM_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_DVPM_SHIFT 16 -+#define AR9_P0_VLAN_REG_DVPM_SIZE 8 -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define AR9_P0_VLAN_REG_PP_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_PP_SHIFT 14 -+#define AR9_P0_VLAN_REG_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define AR9_P0_VLAN_REG_PPE_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_PPE_SHIFT 13 -+#define AR9_P0_VLAN_REG_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Port base VLAN tag member for Port 0' */ -+#define AR9_P0_VLAN_REG_PVTAGMP_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_PVTAGMP_SHIFT 12 -+#define AR9_P0_VLAN_REG_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define AR9_P0_VLAN_REG_PVID_OFFSET 0x0010 -+#define AR9_P0_VLAN_REG_PVID_SHIFT 0 -+#define AR9_P0_VLAN_REG_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 VLAN Control Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define AR9_P1_VLAN_REG_DFID_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_DFID_SHIFT 30 -+#define AR9_P1_VLAN_REG_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define AR9_P1_VLAN_REG_TBVE_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_TBVE_SHIFT 29 -+#define AR9_P1_VLAN_REG_TBVE_SIZE 1 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define AR9_P1_VLAN_REG_IFNTE_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_IFNTE_SHIFT 28 -+#define AR9_P1_VLAN_REG_IFNTE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define AR9_P1_VLAN_REG_VC_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_VC_SHIFT 27 -+#define AR9_P1_VLAN_REG_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define AR9_P1_VLAN_REG_VSD_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_VSD_SHIFT 26 -+#define AR9_P1_VLAN_REG_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define AR9_P1_VLAN_REG_AOVTP_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_AOVTP_SHIFT 25 -+#define AR9_P1_VLAN_REG_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define AR9_P1_VLAN_REG_VMCE_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_VMCE_SHIFT 24 -+#define AR9_P1_VLAN_REG_VMCE_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Default VLAN Port Map' */ -+#define AR9_P1_VLAN_REG_DVPM_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_DVPM_SHIFT 16 -+#define AR9_P1_VLAN_REG_DVPM_SIZE 8 -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define AR9_P1_VLAN_REG_PP_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_PP_SHIFT 14 -+#define AR9_P1_VLAN_REG_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define AR9_P1_VLAN_REG_PPE_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_PPE_SHIFT 13 -+#define AR9_P1_VLAN_REG_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Port base VLAN tag member for Port 0' */ -+#define AR9_P1_VLAN_REG_PVTAGMP_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_PVTAGMP_SHIFT 12 -+#define AR9_P1_VLAN_REG_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define AR9_P1_VLAN_REG_PVID_OFFSET 0x0014 -+#define AR9_P1_VLAN_REG_PVID_SHIFT 0 -+#define AR9_P1_VLAN_REG_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 VLAN Control Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define AR9_P2_VLAN_REG_DFID_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_DFID_SHIFT 30 -+#define AR9_P2_VLAN_REG_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define AR9_P2_VLAN_REG_TBVE_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_TBVE_SHIFT 29 -+#define AR9_P2_VLAN_REG_TBVE_SIZE 1 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define AR9_P2_VLAN_REG_IFNTE_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_IFNTE_SHIFT 28 -+#define AR9_P2_VLAN_REG_IFNTE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define AR9_P2_VLAN_REG_VC_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_VC_SHIFT 27 -+#define AR9_P2_VLAN_REG_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define AR9_P2_VLAN_REG_VSD_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_VSD_SHIFT 26 -+#define AR9_P2_VLAN_REG_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define AR9_P2_VLAN_REG_AOVTP_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_AOVTP_SHIFT 25 -+#define AR9_P2_VLAN_REG_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define AR9_P2_VLAN_REG_VMCE_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_VMCE_SHIFT 24 -+#define AR9_P2_VLAN_REG_VMCE_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Default VLAN Port Map' */ -+#define AR9_P2_VLAN_REG_DVPM_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_DVPM_SHIFT 16 -+#define AR9_P2_VLAN_REG_DVPM_SIZE 8 -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define AR9_P2_VLAN_REG_PP_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_PP_SHIFT 14 -+#define AR9_P2_VLAN_REG_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define AR9_P2_VLAN_REG_PPE_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_PPE_SHIFT 13 -+#define AR9_P2_VLAN_REG_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Port base VLAN tag member for Port 0' */ -+#define AR9_P2_VLAN_REG_PVTAGMP_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_PVTAGMP_SHIFT 12 -+#define AR9_P2_VLAN_REG_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define AR9_P2_VLAN_REG_PVID_OFFSET 0x0018 -+#define AR9_P2_VLAN_REG_PVID_SHIFT 0 -+#define AR9_P2_VLAN_REG_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Ingress Control Register' */ -+/* Bit: 'P0ITT' */ -+/* Description: 'Port 0 Ingress/Egress Timer Tick T selection' */ -+#define AR9_P0_INCTL_REG_P0ITT_OFFSET 0x0020 -+#define AR9_P0_INCTL_REG_P0ITT_SHIFT 11 -+#define AR9_P0_INCTL_REG_P0ITT_SIZE 2 -+/* Bit: 'P0ITR' */ -+/* Description: 'Port 0 Ingress Token R' */ -+#define AR9_P0_INCTL_REG_P0ITR_OFFSET 0x0020 -+#define AR9_P0_INCTL_REG_P0ITR_SHIFT 0 -+#define AR9_P0_INCTL_REG_P0ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Ingress Control Register' */ -+/* Bit: 'P1ITT' */ -+/* Description: 'Port 1 Ingress/Egress Timer Tick T selection' */ -+#define AR9_P1_INCTL_REG_P1ITT_OFFSET 0x0024 -+#define AR9_P1_INCTL_REG_P1ITT_SHIFT 11 -+#define AR9_P1_INCTL_REG_P1ITT_SIZE 2 -+/* Bit: 'P1ITR' */ -+/* Description: 'Port 1 Ingress Token R' */ -+#define AR9_P1_INCTL_REG_P1ITR_OFFSET 0x0024 -+#define AR9_P1_INCTL_REG_P1ITR_SHIFT 0 -+#define AR9_P1_INCTL_REG_P1ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Ingress Control Register' */ -+/* Bit: 'P2ITT' */ -+/* Description: 'Port 2 Ingress/Egress Timer Tick T selection' */ -+#define AR9_P2_INCTL_REG_P2ITT_OFFSET 0x0028 -+#define AR9_P2_INCTL_REG_P2ITT_SHIFT 11 -+#define AR9_P2_INCTL_REG_P2ITT_SIZE 2 -+/* Bit: 'P2ITR' */ -+/* Description: 'Port 2 Ingress Token R' */ -+#define AR9_P2_INCTL_REG_P2ITR_OFFSET 0x0028 -+#define AR9_P2_INCTL_REG_P2ITR_SHIFT 0 -+#define AR9_P2_INCTL_REG_P2ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q32 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0030 -+#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 -+#define AR9_P0_ECS_Q32_REG_P0SPQ3TR_SIZE 11 -+/* Bit: 'P0SPQ2TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ -+#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0030 -+#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 -+#define AR9_P0_ECS_Q32_REG_P0SPQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q32 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0040 -+#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 -+#define AR9_P1_ECS_Q32_REG_P0SPQ3TR_SIZE 11 -+/* Bit: 'P0SPQ2TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ -+#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0040 -+#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 -+#define AR9_P1_ECS_Q32_REG_P0SPQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q32 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_OFFSET 0x0050 -+#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_SHIFT 16 -+#define AR9_P2_ECS_Q32_REG_P0SPQ3TR_SIZE 11 -+/* Bit: 'P0SPQ2TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q2' */ -+#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_OFFSET 0x0050 -+#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_SHIFT 0 -+#define AR9_P2_ECS_Q32_REG_P0SPQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q10 Register' */ -+/* Bit: 'P0SPQ1TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ -+#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0034 -+#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 -+#define AR9_P0_ECS_Q10_REG_P0SPQ1TR_SIZE 11 -+/* Bit: 'P0SPQ0TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ -+#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0034 -+#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 -+#define AR9_P0_ECS_Q10_REG_P0SPQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q10 Register' */ -+/* Bit: 'P0SPQ1TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ -+#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0044 -+#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 -+#define AR9_P1_ECS_Q10_REG_P0SPQ1TR_SIZE 11 -+/* Bit: 'P0SPQ0TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ -+#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0044 -+#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 -+#define AR9_P1_ECS_Q10_REG_P0SPQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q10 Register' */ -+/* Bit: 'P0SPQ1TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q1' */ -+#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_OFFSET 0x0054 -+#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_SHIFT 16 -+#define AR9_P2_ECS_Q10_REG_P0SPQ1TR_SIZE 11 -+/* Bit: 'P0SPQ0TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q0' */ -+#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_OFFSET 0x0054 -+#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_SHIFT 0 -+#define AR9_P2_ECS_Q10_REG_P0SPQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q32 Register' */ -+/* Bit: 'P0WQ3TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q3' */ -+#define AR9_P0_ECW_Q32_REG_P0WQ3TR_OFFSET 0x0038 -+#define AR9_P0_ECW_Q32_REG_P0WQ3TR_SHIFT 16 -+#define AR9_P0_ECW_Q32_REG_P0WQ3TR_SIZE 11 -+/* Bit: 'P0WQ2TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q2' */ -+#define AR9_P0_ECW_Q32_REG_P0WQ2TR_OFFSET 0x0038 -+#define AR9_P0_ECW_Q32_REG_P0WQ2TR_SHIFT 0 -+#define AR9_P0_ECW_Q32_REG_P0WQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q32 Register' */ -+/* Bit: 'P1WQ3TR' */ -+/* Description: 'Port 1 Egress Token R for WFQ Q3' */ -+#define AR9_P1_ECW_Q32_REG_P1WQ3TR_OFFSET 0x0048 -+#define AR9_P1_ECW_Q32_REG_P1WQ3TR_SHIFT 16 -+#define AR9_P1_ECW_Q32_REG_P1WQ3TR_SIZE 11 -+/* Bit: 'P1WQ2TR' */ -+/* Description: 'Port 1 Egress Token R for WFQ Q2' */ -+#define AR9_P1_ECW_Q32_REG_P1WQ2TR_OFFSET 0x0048 -+#define AR9_P1_ECW_Q32_REG_P1WQ2TR_SHIFT 0 -+#define AR9_P1_ECW_Q32_REG_P1WQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q32 Register' */ -+/* Bit: 'P2WQ3TR' */ -+/* Description: 'Port 2 Egress Token R for WFQ Q3' */ -+#define AR9_P2_ECW_Q32_REG_P2WQ3TR_OFFSET 0x0058 -+#define AR9_P2_ECW_Q32_REG_P2WQ3TR_SHIFT 16 -+#define AR9_P2_ECW_Q32_REG_P2WQ3TR_SIZE 11 -+/* Bit: 'P2WQ2TR' */ -+/* Description: 'Port 2 Egress Token R for WFQ Q2' */ -+#define AR9_P2_ECW_Q32_REG_P2WQ2TR_OFFSET 0x0058 -+#define AR9_P2_ECW_Q32_REG_P2WQ2TR_SHIFT 0 -+#define AR9_P2_ECW_Q32_REG_P2WQ2TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q10 Register' */ -+/* Bit: 'P0WQ1TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q1' */ -+#define AR9_P0_ECW_Q10_REG_P0WQ1TR_OFFSET 0x003C -+#define AR9_P0_ECW_Q10_REG_P0WQ1TR_SHIFT 16 -+#define AR9_P0_ECW_Q10_REG_P0WQ1TR_SIZE 11 -+/* Bit: 'P0WQ0TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q0' */ -+#define AR9_P0_ECW_Q10_REG_P0WQ0TR_OFFSET 0x003C -+#define AR9_P0_ECW_Q10_REG_P0WQ0TR_SHIFT 0 -+#define AR9_P0_ECW_Q10_REG_P0WQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q10 Register' */ -+/* Bit: 'P1WQ1TR' */ -+/* Description: 'Port 1 Egress Token R for WFQ Q1' */ -+#define AR9_P1_ECW_Q10_REG_P1WQ1TR_OFFSET 0x004C -+#define AR9_P1_ECW_Q10_REG_P1WQ1TR_SHIFT 16 -+#define AR9_P1_ECW_Q10_REG_P1WQ1TR_SIZE 11 -+/* Bit: 'P1WQ0TR' */ -+/* Description: 'Port 1 Egress Token R for WFQ Q0' */ -+#define AR9_P1_ECW_Q10_REG_P1WQ0TR_OFFSET 0x004C -+#define AR9_P1_ECW_Q10_REG_P1WQ0TR_SHIFT 0 -+#define AR9_P1_ECW_Q10_REG_P1WQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q10 Register' */ -+/* Bit: 'P2WQ1TR' */ -+/* Description: 'Port 2 Egress Token R for WFQ Q1' */ -+#define AR9_P2_ECW_Q10_REG_P2WQ1TR_OFFSET 0x005C -+#define AR9_P2_ECW_Q10_REG_P2WQ1TR_SHIFT 16 -+#define AR9_P2_ECW_Q10_REG_P2WQ1TR_SIZE 11 -+/* Bit: 'P2WQ0TR' */ -+/* Description: 'Port 2 Egress Token R for WFQ Q0' */ -+#define AR9_P2_ECW_Q10_REG_P2WQ0TR_OFFSET 0x005C -+#define AR9_P2_ECW_Q10_REG_P2WQ0TR_SHIFT 0 -+#define AR9_P2_ECW_Q10_REG_P2WQ0TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Enable Register' */ -+/* Bit: 'DBFIE' */ -+/* Description: 'Data Buffer is Full Interrupt Enable' */ -+#define AR9_INT_ENA_REG_DBFIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_DBFIE_SHIFT 7 -+#define AR9_INT_ENA_REG_DBFIE_SIZE 1 -+/* Bit: 'DBNFIE' */ -+/* Description: 'Data Buffer is nearly Full Interrupt Enable' */ -+#define AR9_INT_ENA_REG_DBNFIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_DBNFIE_SHIFT 6 -+#define AR9_INT_ENA_REG_DBNFIE_SIZE 1 -+/* Bit: 'LTFIE' */ -+/* Description: 'Learning Table Full Interrupt Enable' */ -+#define AR9_INT_ENA_REG_LTFIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_LTFIE_SHIFT 5 -+#define AR9_INT_ENA_REG_LTFIE_SIZE 1 -+/* Bit: 'LTADIE' */ -+/* Description: 'Leaning Table Access Done Interrupt Enable' */ -+#define AR9_INT_ENA_REG_LTADIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_LTADIE_SHIFT 4 -+#define AR9_INT_ENA_REG_LTADIE_SIZE 1 -+/* Bit: 'PSVIE' */ -+/* Description: 'Port Security Violation Interrupt Enable' */ -+#define AR9_INT_ENA_REG_PSVIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_PSVIE_SHIFT 1 -+#define AR9_INT_ENA_REG_PSVIE_SIZE 3 -+/* Bit: 'PSCIE' */ -+/* Description: 'Port Status Change Interrupt Enable' */ -+#define AR9_INT_ENA_REG_PSCIE_OFFSET 0x0060 -+#define AR9_INT_ENA_REG_PSCIE_SHIFT 0 -+#define AR9_INT_ENA_REG_PSCIE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Status Register' */ -+/* Bit: 'DBF' */ -+/* Description: 'Data Buffer is Full' */ -+#define AR9_INT_ST_REG_DBF_OFFSET 0x0064 -+#define AR9_INT_ST_REG_DBF_SHIFT 7 -+#define AR9_INT_ST_REG_DBF_SIZE 1 -+/* Bit: 'DBNF' */ -+/* Description: 'Data Buffer is nearly Full' */ -+#define AR9_INT_ST_REG_DBNF_OFFSET 0x0064 -+#define AR9_INT_ST_REG_DBNF_SHIFT 6 -+#define AR9_INT_ST_REG_DBNF_SIZE 1 -+/* Bit: 'LTF' */ -+/* Description: 'Learning Table Full' */ -+#define AR9_INT_ST_REG_LTF_OFFSET 0x0064 -+#define AR9_INT_ST_REG_LTF_SHIFT 5 -+#define AR9_INT_ST_REG_LTF_SIZE 1 -+/* Bit: 'LTAD' */ -+/* Description: 'Leaning Table Access Done' */ -+#define AR9_INT_ST_REG_LTAD_OFFSET 0x0064 -+#define AR9_INT_ST_REG_LTAD_SHIFT 4 -+#define AR9_INT_ST_REG_LTAD_SIZE 1 -+/* Bit: 'PSV' */ -+/* Description: 'Port Security Violation' */ -+#define AR9_INT_ST_REG_PSV_OFFSET 0x0064 -+#define AR9_INT_ST_REG_PSV_SHIFT 1 -+#define AR9_INT_ST_REG_PSV_SIZE 3 -+/* Bit: 'PSC' */ -+/* Description: 'Port Status Change' */ -+#define AR9_INT_ST_REG_PSC_OFFSET 0x0064 -+#define AR9_INT_ST_REG_PSC_SHIFT 0 -+#define AR9_INT_ST_REG_PSC_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch Global Control Register 0' */ -+/* Bit: 'SE' */ -+/* Description: 'Switch Enable' */ -+#define AR9_SW_GCTL0_REG_SE_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_SE_SHIFT 31 -+#define AR9_SW_GCTL0_REG_SE_SIZE 1 -+/* Bit: 'ICRCCD' */ -+/* Description: 'CRC Check Disable' */ -+#define AR9_SW_GCTL0_REG_ICRCCD_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_ICRCCD_SHIFT 30 -+#define AR9_SW_GCTL0_REG_ICRCCD_SIZE 1 -+/* Bit: 'LPE' */ -+/* Description: 'Virtual Ports Over CPU Physical Port Enable' */ -+#define AR9_SW_GCTL0_REG_LPE_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_LPE_SHIFT 29 -+#define AR9_SW_GCTL0_REG_LPE_SIZE 1 -+/* Bit: 'RVID0' */ -+/* Description: 'Replace VID0' */ -+#define AR9_SW_GCTL0_REG_RVID0_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_RVID0_SHIFT 28 -+#define AR9_SW_GCTL0_REG_RVID0_SIZE 1 -+/* Bit: 'RVID1' */ -+/* Description: 'Replace VID1' */ -+#define AR9_SW_GCTL0_REG_RVID1_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_RVID1_SHIFT 27 -+#define AR9_SW_GCTL0_REG_RVID1_SIZE 1 -+/* Bit: 'RVIDFFF' */ -+/* Description: 'Replace VIDFFF' */ -+#define AR9_SW_GCTL0_REG_RVIDFFF_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_RVIDFFF_SHIFT 26 -+#define AR9_SW_GCTL0_REG_RVIDFFF_SIZE 1 -+/* Bit: 'PCR' */ -+/* Description: 'Priority Change Rule' */ -+#define AR9_SW_GCTL0_REG_PCR_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_PCR_SHIFT 25 -+#define AR9_SW_GCTL0_REG_PCR_SIZE 1 -+/* Bit: 'PCE' */ -+/* Description: 'Priority Change Enable' */ -+#define AR9_SW_GCTL0_REG_PCE_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_PCE_SHIFT 24 -+#define AR9_SW_GCTL0_REG_PCE_SIZE 1 -+/* Bit: 'TSIPGE' */ -+/* Description: 'Transmit Short IPG Enable' */ -+#define AR9_SW_GCTL0_REG_TSIPGE_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_TSIPGE_SHIFT 23 -+#define AR9_SW_GCTL0_REG_TSIPGE_SIZE 1 -+/* Bit: 'PHYBA' */ -+/* Description: 'PHY Base Address' */ -+#define AR9_SW_GCTL0_REG_PHYBA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_PHYBA_SHIFT 22 -+#define AR9_SW_GCTL0_REG_PHYBA_SIZE 1 -+/* Bit: 'DPWECH' */ -+/* Description: 'Drop Packet When Excessive Collision Happen' */ -+#define AR9_SW_GCTL0_REG_DPWECH_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_DPWECH_SHIFT 21 -+#define AR9_SW_GCTL0_REG_DPWECH_SIZE 1 -+/* Bit: 'ATS' */ -+/* Description: 'Aging Timer Select' */ -+#define AR9_SW_GCTL0_REG_ATS_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_ATS_SHIFT 18 -+#define AR9_SW_GCTL0_REG_ATS_SIZE 3 -+/* Bit: 'MCA' */ -+/* Description: 'Mirror CRC Also' */ -+#define AR9_SW_GCTL0_REG_MCA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MCA_SHIFT 17 -+#define AR9_SW_GCTL0_REG_MCA_SIZE 1 -+/* Bit: 'MRA' */ -+/* Description: 'Mirror RXER Also' */ -+#define AR9_SW_GCTL0_REG_MRA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MRA_SHIFT 16 -+#define AR9_SW_GCTL0_REG_MRA_SIZE 1 -+/* Bit: 'MPA' */ -+/* Description: 'Mirror PAUSE Also' */ -+#define AR9_SW_GCTL0_REG_MPA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MPA_SHIFT 15 -+#define AR9_SW_GCTL0_REG_MPA_SIZE 1 -+/* Bit: 'MLA' */ -+/* Description: 'Mirror Long Also' */ -+#define AR9_SW_GCTL0_REG_MLA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MLA_SHIFT 14 -+#define AR9_SW_GCTL0_REG_MLA_SIZE 1 -+/* Bit: 'MSA' */ -+/* Description: 'Mirror Short Also' */ -+#define AR9_SW_GCTL0_REG_MSA_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MSA_SHIFT 13 -+#define AR9_SW_GCTL0_REG_MSA_SIZE 1 -+/* Bit: 'SNIFFPN' */ -+/* Description: 'Sniffer port number' */ -+#define AR9_SW_GCTL0_REG_SNIFFPN_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_SNIFFPN_SHIFT 10 -+#define AR9_SW_GCTL0_REG_SNIFFPN_SIZE 3 -+/* Bit: 'MPL' */ -+/* Description: 'Max Packet Length (MAXPKTLEN)' */ -+#define AR9_SW_GCTL0_REG_MPL_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_MPL_SHIFT 8 -+#define AR9_SW_GCTL0_REG_MPL_SIZE 2 -+/* Bit: 'DMQ3' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q3)' */ -+#define AR9_SW_GCTL0_REG_DMQ3_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_DMQ3_SHIFT 6 -+#define AR9_SW_GCTL0_REG_DMQ3_SIZE 2 -+/* Bit: 'DMQ2' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q2)' */ -+#define AR9_SW_GCTL0_REG_DMQ2_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_DMQ2_SHIFT 4 -+#define AR9_SW_GCTL0_REG_DMQ2_SIZE 2 -+/* Bit: 'DMQ1' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q1)' */ -+#define AR9_SW_GCTL0_REG_DMQ1_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_DMQ1_SHIFT 2 -+#define AR9_SW_GCTL0_REG_DMQ1_SIZE 2 -+/* Bit: 'DMQ0' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q0)' */ -+#define AR9_SW_GCTL0_REG_DMQ0_OFFSET 0x0068 -+#define AR9_SW_GCTL0_REG_DMQ0_SHIFT 0 -+#define AR9_SW_GCTL0_REG_DMQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch Global Control Register 1' */ -+/* Bit: 'BISTDN' */ -+/* Description: 'BIST Done' */ -+#define AR9_SW_GCTL1_REG_BISTDN_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_BISTDN_SHIFT 27 -+#define AR9_SW_GCTL1_REG_BISTDN_SIZE 1 -+/* Bit: 'EDSTX' */ -+/* Description: 'Enable drop scheme of TX and RX' */ -+#define AR9_SW_GCTL1_REG_EDSTX_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_EDSTX_SHIFT 26 -+#define AR9_SW_GCTL1_REG_EDSTX_SIZE 1 -+/* Bit: 'CTTX' */ -+/* Description: 'Congestion threshold for TX queue' */ -+#define AR9_SW_GCTL1_REG_CTTX_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_CTTX_SHIFT 24 -+#define AR9_SW_GCTL1_REG_CTTX_SIZE 2 -+/* Bit: 'IJT' */ -+/* Description: 'Input Jam Threshold' */ -+#define AR9_SW_GCTL1_REG_IJT_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_IJT_SHIFT 21 -+#define AR9_SW_GCTL1_REG_IJT_SIZE 3 -+/* Bit: 'DIVS' */ -+/* Description: 'Do not Identify VLAN after SNAP' */ -+#define AR9_SW_GCTL1_REG_DIVS_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DIVS_SHIFT 20 -+#define AR9_SW_GCTL1_REG_DIVS_SIZE 1 -+/* Bit: 'DII6P' */ -+/* Description: 'Do not Identify IPV6 in PPPOE' */ -+#define AR9_SW_GCTL1_REG_DII6P_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DII6P_SHIFT 19 -+#define AR9_SW_GCTL1_REG_DII6P_SIZE 1 -+/* Bit: 'DIIPS' */ -+/* Description: 'Do not Identify IP in PPPOE after SNAP' */ -+#define AR9_SW_GCTL1_REG_DIIPS_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DIIPS_SHIFT 18 -+#define AR9_SW_GCTL1_REG_DIIPS_SIZE 1 -+/* Bit: 'DIE' */ -+/* Description: 'Do not Identify IPV6' */ -+#define AR9_SW_GCTL1_REG_DIE_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DIE_SHIFT 17 -+#define AR9_SW_GCTL1_REG_DIE_SIZE 1 -+/* Bit: 'DIIP' */ -+/* Description: 'Do not Identify IPv4 in PPPOE' */ -+#define AR9_SW_GCTL1_REG_DIIP_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DIIP_SHIFT 16 -+#define AR9_SW_GCTL1_REG_DIIP_SIZE 1 -+/* Bit: 'DIS' */ -+/* Description: 'Do not Identify SNAP' */ -+#define AR9_SW_GCTL1_REG_DIS_OFFSET 0x006C -+#define AR9_SW_GCTL1_REG_DIS_SHIFT 15 -+#define AR9_SW_GCTL1_REG_DIS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Default Portmap Register' */ -+/* Bit: 'UP' */ -+/* Description: 'Unknown Unicast Portmap' */ -+#define AR9_DF_PORTMAP_REG_UP_OFFSET 0x002C -+#define AR9_DF_PORTMAP_REG_UP_SHIFT 24 -+#define AR9_DF_PORTMAP_REG_UP_SIZE 8 -+/* Bit: 'BP' */ -+/* Description: 'Broadcast Portmap' */ -+#define AR9_DF_PORTMAP_REG_BP_OFFSET 0x002C -+#define AR9_DF_PORTMAP_REG_BP_SHIFT 16 -+#define AR9_DF_PORTMAP_REG_BP_SIZE 8 -+/* Bit: 'MP' */ -+/* Description: 'Unknown Multicast Portmap' */ -+#define AR9_DF_PORTMAP_REG_MP_OFFSET 0x002C -+#define AR9_DF_PORTMAP_REG_MP_SHIFT 8 -+#define AR9_DF_PORTMAP_REG_MP_SIZE 8 -+/* Bit: 'RP' */ -+/* Description: 'Reserve Portmap' */ -+#define AR9_DF_PORTMAP_REG_RP_OFFSET 0x002C -+#define AR9_DF_PORTMAP_REG_RP_SHIFT 0 -+#define AR9_DF_PORTMAP_REG_RP_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'ARP/RARP Register' */ -+/* Bit: 'MACA' */ -+/* Description: 'MAC Control Action' */ -+#define AR9_ARP_REG_MACA_OFFSET 0x0070 -+#define AR9_ARP_REG_MACA_SHIFT 14 -+#define AR9_ARP_REG_MACA_SIZE 2 -+/* Bit: 'UPT' */ -+/* Description: 'Unicast packet Treated as Cross_VLAN packet' */ -+#define AR9_ARP_REG_UPT_OFFSET 0x0070 -+#define AR9_ARP_REG_UPT_SHIFT 13 -+#define AR9_ARP_REG_UPT_SIZE 1 -+/* Bit: 'RPT' */ -+/* Description: 'RARP Packet Treated as Cross_VLAN Packet' */ -+#define AR9_ARP_REG_RPT_OFFSET 0x0070 -+#define AR9_ARP_REG_RPT_SHIFT 12 -+#define AR9_ARP_REG_RPT_SIZE 1 -+/* Bit: 'RAPA' */ -+/* Description: 'RARP/ARP Packet Action' */ -+#define AR9_ARP_REG_RAPA_OFFSET 0x0070 -+#define AR9_ARP_REG_RAPA_SHIFT 10 -+#define AR9_ARP_REG_RAPA_SIZE 2 -+/* Bit: 'RAPPE' */ -+/* Description: 'RARP/ARP Packet Priority Enable' */ -+#define AR9_ARP_REG_RAPPE_OFFSET 0x0070 -+#define AR9_ARP_REG_RAPPE_SHIFT 9 -+#define AR9_ARP_REG_RAPPE_SIZE 1 -+/* Bit: 'RAPP' */ -+/* Description: 'RARP/ARP Packet Priority' */ -+#define AR9_ARP_REG_RAPP_OFFSET 0x0070 -+#define AR9_ARP_REG_RAPP_SHIFT 7 -+#define AR9_ARP_REG_RAPP_SIZE 2 -+/* Bit: 'RAPOTH' */ -+/* Description: 'RARP/ARP Packet Output Tag Handle' */ -+#define AR9_ARP_REG_RAPOTH_OFFSET 0x0070 -+#define AR9_ARP_REG_RAPOTH_SHIFT 5 -+#define AR9_ARP_REG_RAPOTH_SIZE 2 -+/* Bit: 'APT' */ -+/* Description: 'ARP Packet Treated as Cross _ VLAN Packet' */ -+#define AR9_ARP_REG_APT_OFFSET 0x0070 -+#define AR9_ARP_REG_APT_SHIFT 4 -+#define AR9_ARP_REG_APT_SIZE 1 -+/* Bit: 'RAPTM' */ -+/* Description: 'RARP/ARP Packet Treated as Management Packet' */ -+#define AR9_ARP_REG_RAPTM_OFFSET 0x0070 -+#define AR9_ARP_REG_RAPTM_SHIFT 3 -+#define AR9_ARP_REG_RAPTM_SIZE 1 -+/* Bit: 'TAPTS' */ -+/* Description: 'RARP/ARP Packet Treated as Span Packet' */ -+#define AR9_ARP_REG_TAPTS_OFFSET 0x0070 -+#define AR9_ARP_REG_TAPTS_SHIFT 2 -+#define AR9_ARP_REG_TAPTS_SIZE 1 -+/* Bit: 'TAP' */ -+/* Description: 'Trap ARP Packet' */ -+#define AR9_ARP_REG_TAP_OFFSET 0x0070 -+#define AR9_ARP_REG_TAP_SHIFT 1 -+#define AR9_ARP_REG_TAP_SIZE 1 -+/* Bit: 'TRP' */ -+/* Description: 'Trap RARP Packet' */ -+#define AR9_ARP_REG_TRP_OFFSET 0x0070 -+#define AR9_ARP_REG_TRP_SHIFT 0 -+#define AR9_ARP_REG_TRP_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Storm control Register' */ -+/* Bit: 'STORM_10_TH' */ -+/* Description: '10M Threshold' */ -+#define AR9_STRM_CTL_REG_STORM_10_TH_OFFSET 0x0074 -+#define AR9_STRM_CTL_REG_STORM_10_TH_SHIFT 16 -+#define AR9_STRM_CTL_REG_STORM_10_TH_SIZE 13 -+/* Bit: 'STORM_B' */ -+/* Description: 'Storm Enable for Broadcast Packets' */ -+#define AR9_STRM_CTL_REG_STORM_B_OFFSET 0x0074 -+#define AR9_STRM_CTL_REG_STORM_B_SHIFT 15 -+#define AR9_STRM_CTL_REG_STORM_B_SIZE 1 -+/* Bit: 'STORM_M' */ -+/* Description: 'Storm Enable for Multicast Packets' */ -+#define AR9_STRM_CTL_REG_STORM_M_OFFSET 0x0074 -+#define AR9_STRM_CTL_REG_STORM_M_SHIFT 14 -+#define AR9_STRM_CTL_REG_STORM_M_SIZE 1 -+/* Bit: 'STORM_U' */ -+/* Description: 'Storm Enable for Un-learned Unicast Packets' */ -+#define AR9_STRM_CTL_REG_STORM_U_OFFSET 0x0074 -+#define AR9_STRM_CTL_REG_STORM_U_SHIFT 13 -+#define AR9_STRM_CTL_REG_STORM_U_SIZE 1 -+/* Bit: 'STORM_100_TH' */ -+/* Description: '100M Threshold' */ -+#define AR9_STRM_CTL_REG_STORM_100_TH_OFFSET 0x0074 -+#define AR9_STRM_CTL_REG_STORM_100_TH_SHIFT 0 -+#define AR9_STRM_CTL_REG_STORM_100_TH_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RGMII/GMII Port Control Register' */ -+/* Bit: 'MCS' */ -+/* Description: 'Management Clock Select' */ -+#define AR9_RGMII_CTL_REG_MCS_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_MCS_SHIFT 24 -+#define AR9_RGMII_CTL_REG_MCS_SIZE 8 -+/* Bit: 'P1CKIO' */ -+/* Description: 'Interface Clk PAD I/O Select' */ -+#define AR9_RGMII_CTL_REG_P1CKIO_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1CKIO_SHIFT 23 -+#define AR9_RGMII_CTL_REG_P1CKIO_SIZE 1 -+/* Bit: 'P1Feq' */ -+/* Description: 'Interface Reverse MII Clk Frequency' */ -+#define AR9_RGMII_CTL_REG_P1FEQ_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1FEQ_SHIFT 22 -+#define AR9_RGMII_CTL_REG_P1FEQ_SIZE 1 -+/* Bit: 'P0CKIO' */ -+/* Description: 'Interface Clk PAD I/O Select' */ -+#define AR9_RGMII_CTL_REG_P0CKIO_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0CKIO_SHIFT 21 -+#define AR9_RGMII_CTL_REG_P0CKIO_SIZE 1 -+/* Bit: 'P0Feq' */ -+/* Description: 'Interface Reverse MII Clk Frequency' */ -+#define AR9_RGMII_CTL_REG_P0FEQ_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0FEQ_SHIFT 20 -+#define AR9_RGMII_CTL_REG_P0FEQ_SIZE 1 -+/* Bit: 'P1IS' */ -+/* Description: 'Interface Selection' */ -+#define AR9_RGMII_CTL_REG_P1IS_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1IS_SHIFT 18 -+#define AR9_RGMII_CTL_REG_P1IS_SIZE 2 -+/* Bit: 'P1RDLY' */ -+/* Description: 'Port 1 RGMII Rx Clock Delay' */ -+#define AR9_RGMII_CTL_REG_P1RDLY_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1RDLY_SHIFT 16 -+#define AR9_RGMII_CTL_REG_P1RDLY_SIZE 2 -+/* Bit: 'P1TDLY' */ -+/* Description: 'Port 1 RGMII Tx Clock Delay' */ -+#define AR9_RGMII_CTL_REG_P1TDLY_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1TDLY_SHIFT 14 -+#define AR9_RGMII_CTL_REG_P1TDLY_SIZE 2 -+/* Bit: 'P1SPD' */ -+/* Description: 'Port 1 Speed' */ -+#define AR9_RGMII_CTL_REG_P1SPD_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1SPD_SHIFT 12 -+#define AR9_RGMII_CTL_REG_P1SPD_SIZE 2 -+/* Bit: 'P1DUP' */ -+/* Description: 'Port 1 Duplex mode' */ -+#define AR9_RGMII_CTL_REG_P1DUP_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1DUP_SHIFT 11 -+#define AR9_RGMII_CTL_REG_P1DUP_SIZE 1 -+/* Bit: 'P1FCE' */ -+/* Description: 'Port 1 Flow Control Enable' */ -+#define AR9_RGMII_CTL_REG_P1FCE_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P1FCE_SHIFT 10 -+#define AR9_RGMII_CTL_REG_P1FCE_SIZE 1 -+/* Bit: 'P0IS' */ -+/* Description: 'Interface Selection' */ -+#define AR9_RGMII_CTL_REG_P0IS_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0IS_SHIFT 8 -+#define AR9_RGMII_CTL_REG_P0IS_SIZE 2 -+/* Bit: 'P0RDLY' */ -+/* Description: 'Port 0 RGMII Rx Clock Delay' */ -+#define AR9_RGMII_CTL_REG_P0RDLY_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0RDLY_SHIFT 6 -+#define AR9_RGMII_CTL_REG_P0RDLY_SIZE 2 -+/* Bit: 'P0TDLY' */ -+/* Description: 'Port 0 RGMII Tx Clock Delay' */ -+#define AR9_RGMII_CTL_REG_P0TDLY_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0TDLY_SHIFT 4 -+#define AR9_RGMII_CTL_REG_P0TDLY_SIZE 2 -+/* Bit: 'P0SPD' */ -+/* Description: 'Port 0 Speed' */ -+#define AR9_RGMII_CTL_REG_P0SPD_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0SPD_SHIFT 2 -+#define AR9_RGMII_CTL_REG_P0SPD_SIZE 2 -+/* Bit: 'P0DUP' */ -+/* Description: 'Port 0 Duplex mode' */ -+#define AR9_RGMII_CTL_REG_P0DUP_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0DUP_SHIFT 1 -+#define AR9_RGMII_CTL_REG_P0DUP_SIZE 1 -+/* Bit: 'P0FCE' */ -+/* Description: 'Port 0 Flow Control Enable' */ -+#define AR9_RGMII_CTL_REG_P0FCE_OFFSET 0x0078 -+#define AR9_RGMII_CTL_REG_P0FCE_SHIFT 0 -+#define AR9_RGMII_CTL_REG_P0FCE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: '802.1p Priority Map Register' */ -+/* Bit: '1PPQ7' */ -+/* Description: 'Priority Queue 7' */ -+#define AR9_1P_PRT_REG_1PPQ7_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ7_SHIFT 14 -+#define AR9_1P_PRT_REG_1PPQ7_SIZE 2 -+/* Bit: '1PPQ6' */ -+/* Description: 'Priority Queue 6' */ -+#define AR9_1P_PRT_REG_1PPQ6_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ6_SHIFT 12 -+#define AR9_1P_PRT_REG_1PPQ6_SIZE 2 -+/* Bit: '1PPQ5' */ -+/* Description: 'Priority Queue 5' */ -+#define AR9_1P_PRT_REG_1PPQ5_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ5_SHIFT 10 -+#define AR9_1P_PRT_REG_1PPQ5_SIZE 2 -+/* Bit: '1PPQ4' */ -+/* Description: 'Priority Queue 4' */ -+#define AR9_1P_PRT_REG_1PPQ4_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ4_SHIFT 8 -+#define AR9_1P_PRT_REG_1PPQ4_SIZE 2 -+/* Bit: '1PPQ3' */ -+/* Description: 'Priority Queue 3' */ -+#define AR9_1P_PRT_REG_1PPQ3_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ3_SHIFT 6 -+#define AR9_1P_PRT_REG_1PPQ3_SIZE 2 -+/* Bit: '1PPQ2' */ -+/* Description: 'Priority Queue 2' */ -+#define AR9_1P_PRT_REG_1PPQ2_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ2_SHIFT 4 -+#define AR9_1P_PRT_REG_1PPQ2_SIZE 2 -+/* Bit: '1PPQ1' */ -+/* Description: 'Priority Queue 1' */ -+#define AR9_1P_PRT_REG_1PPQ1_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ1_SHIFT 2 -+#define AR9_1P_PRT_REG_1PPQ1_SIZE 2 -+/* Bit: '1PPQ0' */ -+/* Description: 'Priority Queue 0' */ -+#define AR9_1P_PRT_REG_1PPQ0_OFFSET 0x007C -+#define AR9_1P_PRT_REG_1PPQ0_SHIFT 0 -+#define AR9_1P_PRT_REG_1PPQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ingress Policing Flow Control On Watermark' */ -+/* Bit: 'F' */ -+/* Description: 'Ingress Policing Flow Control On Watermark' */ -+#define AR9_PAUSE_ON_WM_F_OFFSET 0x0080 -+#define AR9_PAUSE_ON_WM_F_SHIFT 0 -+#define AR9_PAUSE_ON_WM_F_SIZE 18 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ingress Policing Flow Control Off Watermark' */ -+/* Bit: 'B' */ -+/* Description: 'Ingress Policing Flow Control Off Watermark' */ -+#define AR9_PAUSE_OFF_WM_B_OFFSET 0x0084 -+#define AR9_PAUSE_OFF_WM_B_SHIFT 0 -+#define AR9_PAUSE_OFF_WM_B_SIZE 18 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Threshold Register' */ -+/* Bit: 'PUO2' */ -+/* Description: 'Port 2 Based Flow Control Off Watermark Offset' */ -+#define AR9_BF_TH_REG_PUO2_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PUO2_SHIFT 30 -+#define AR9_BF_TH_REG_PUO2_SIZE 2 -+/* Bit: 'PUO1' */ -+/* Description: 'Port 1 Based Flow Control Off Watermark Offset' */ -+#define AR9_BF_TH_REG_PUO1_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PUO1_SHIFT 28 -+#define AR9_BF_TH_REG_PUO1_SIZE 2 -+/* Bit: 'PUO0' */ -+/* Description: 'Port 0 Based Flow Control Off Watermark Offset' */ -+#define AR9_BF_TH_REG_PUO0_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PUO0_SHIFT 26 -+#define AR9_BF_TH_REG_PUO0_SIZE 2 -+/* Bit: 'PFO2' */ -+/* Description: 'Port 2 Based Flow Control On Watermark Offset' */ -+#define AR9_BF_TH_REG_PFO2_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PFO2_SHIFT 22 -+#define AR9_BF_TH_REG_PFO2_SIZE 2 -+/* Bit: 'PFO1' */ -+/* Description: 'Port 1 Based Flow Control On Watermark Offset' */ -+#define AR9_BF_TH_REG_PFO1_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PFO1_SHIFT 20 -+#define AR9_BF_TH_REG_PFO1_SIZE 2 -+/* Bit: 'PFO0' */ -+/* Description: 'Port 0 Based Flow Control On Watermark Offset' */ -+#define AR9_BF_TH_REG_PFO0_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PFO0_SHIFT 18 -+#define AR9_BF_TH_REG_PFO0_SIZE 2 -+/* Bit: 'TLA' */ -+/* Description: 'Global Flow Control Stop Watermark Selection' */ -+#define AR9_BF_TH_REG_TLA_OFFSET 0x0088 -+#define AR9_BF_TH_REG_TLA_SHIFT 13 -+#define AR9_BF_TH_REG_TLA_SIZE 1 -+/* Bit: 'THA' */ -+/* Description: 'Global Flow Control On Watermark Selection' */ -+#define AR9_BF_TH_REG_THA_OFFSET 0x0088 -+#define AR9_BF_TH_REG_THA_SHIFT 12 -+#define AR9_BF_TH_REG_THA_SIZE 1 -+/* Bit: 'TLO' */ -+/* Description: 'Global Flow Control Off Watermark Offset' */ -+#define AR9_BF_TH_REG_TLO_OFFSET 0x0088 -+#define AR9_BF_TH_REG_TLO_SHIFT 10 -+#define AR9_BF_TH_REG_TLO_SIZE 2 -+/* Bit: 'THO' */ -+/* Description: 'Global Flow Control On Watermark Offset' */ -+#define AR9_BF_TH_REG_THO_OFFSET 0x0088 -+#define AR9_BF_TH_REG_THO_SHIFT 8 -+#define AR9_BF_TH_REG_THO_SIZE 2 -+/* Bit: 'PUA' */ -+/* Description: 'Port Based Flow Control Off Watermark Selection ' */ -+#define AR9_BF_TH_REG_PUA_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PUA_SHIFT 5 -+#define AR9_BF_TH_REG_PUA_SIZE 3 -+/* Bit: 'PFA' */ -+/* Description: 'Port Based Flow Control on Watermark Selection' */ -+#define AR9_BF_TH_REG_PFA_OFFSET 0x0088 -+#define AR9_BF_TH_REG_PFA_SHIFT 1 -+#define AR9_BF_TH_REG_PFA_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Header Control Register' */ -+/* Bit: 'RES' */ -+/* Description: 'Reserved' */ -+#define AR9_PMAC_HD_CTL_RES_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_RES_SHIFT 23 -+#define AR9_PMAC_HD_CTL_RES_SIZE 9 -+/* Bit: 'RXSH' */ -+/* Description: 'Status Header for Packets from DMA to PMAC' */ -+#define AR9_PMAC_HD_CTL_RXSH_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_RXSH_SHIFT 22 -+#define AR9_PMAC_HD_CTL_RXSH_SIZE 1 -+/* Bit: 'RL2' */ -+/* Description: 'Remove Layer-2 Header from Packets Going from PMAC -+to DMA' */ -+#define AR9_PMAC_HD_CTL_RL2_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_RL2_SHIFT 21 -+#define AR9_PMAC_HD_CTL_RL2_SIZE 1 -+/* Bit: 'RC' */ -+/* Description: 'Remove CRC from Packets Going from PMAC to DMA' */ -+#define AR9_PMAC_HD_CTL_RC_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_RC_SHIFT 20 -+#define AR9_PMAC_HD_CTL_RC_SIZE 1 -+/* Bit: 'AS' */ -+/* Description: 'Status Header for Packets from PMAC to DMA' */ -+#define AR9_PMAC_HD_CTL_AS_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_AS_SHIFT 19 -+#define AR9_PMAC_HD_CTL_AS_SIZE 1 -+/* Bit: 'AC' */ -+/* Description: 'Add CRC for packets from DMA to PMAC' */ -+#define AR9_PMAC_HD_CTL_AC_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_AC_SHIFT 18 -+#define AR9_PMAC_HD_CTL_AC_SIZE 1 -+/* Bit: 'TYPE_LEN' */ -+/* Description: 'Contains the length/type value to the added to packets -+from DMA to PMAC' */ -+#define AR9_PMAC_HD_CTL_TYPE_LEN_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_TYPE_LEN_SHIFT 2 -+#define AR9_PMAC_HD_CTL_TYPE_LEN_SIZE 16 -+/* Bit: 'TAG' */ -+/* Description: 'Add TAG to Packets from DMA to PMAC' */ -+#define AR9_PMAC_HD_CTL_TAG_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_TAG_SHIFT 1 -+#define AR9_PMAC_HD_CTL_TAG_SIZE 1 -+/* Bit: 'ADD' */ -+/* Description: 'ADD Header to Packets from DMA to PMAC' */ -+#define AR9_PMAC_HD_CTL_ADD_OFFSET 0x008C -+#define AR9_PMAC_HD_CTL_ADD_SHIFT 0 -+#define AR9_PMAC_HD_CTL_ADD_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Source Address Register 1' */ -+/* Bit: 'SA_47_32' */ -+/* Description: 'Source Address to be inserted as a part of the Ethernet -+header.' */ -+#define AR9_PMAC_SA1_SA_47_32_OFFSET 0x0090 -+#define AR9_PMAC_SA1_SA_47_32_SHIFT 0 -+#define AR9_PMAC_SA1_SA_47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Source Address Register 2' */ -+/* Bit: 'SA_31_0' */ -+/* Description: 'Source Address' */ -+#define AR9_PMAC_SA2_SA_31_0_OFFSET 0x0094 -+#define AR9_PMAC_SA2_SA_31_0_SHIFT 0 -+#define AR9_PMAC_SA2_SA_31_0_SIZE 32 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Destination Address Register 1' */ -+/* Bit: 'DA_47_32' */ -+/* Description: 'Destination Address' */ -+#define AR9_PMAC_DA1_DA_47_32_OFFSET 0x0098 -+#define AR9_PMAC_DA1_DA_47_32_SHIFT 0 -+#define AR9_PMAC_DA1_DA_47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Destination Address Register 2' */ -+/* Bit: 'DA_31_0' */ -+/* Description: 'Destination Address to be inserted as a part of -+the Ethernet header.' */ -+#define AR9_PMAC_DA2_DA_31_0_OFFSET 0x009C -+#define AR9_PMAC_DA2_DA_31_0_SHIFT 0 -+#define AR9_PMAC_DA2_DA_31_0_SIZE 32 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC VLAN Register' */ -+/* Bit: 'PRI' */ -+/* Description: 'Priority to be inserted as a part of VLAN tag' */ -+#define AR9_PMAC_VLAN_PRI_OFFSET 0x00A0 -+#define AR9_PMAC_VLAN_PRI_SHIFT 13 -+#define AR9_PMAC_VLAN_PRI_SIZE 3 -+/* Bit: 'CFI' */ -+/* Description: 'CFI bit to be inserted as a part of VLAN tag' */ -+#define AR9_PMAC_VLAN_CFI_OFFSET 0x00A0 -+#define AR9_PMAC_VLAN_CFI_SHIFT 12 -+#define AR9_PMAC_VLAN_CFI_SIZE 1 -+/* Bit: 'VLAN ID' */ -+/* Description: 'VLAN ID to be inserted as a part of VLAN tag' */ -+#define AR9_PMAC_VLAN_VLAN_ID_OFFSET 0x00A0 -+#define AR9_PMAC_VLAN_VLAN_ID_SHIFT 0 -+#define AR9_PMAC_VLAN_VLAN_ID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC TX IPG Counter Register' */ -+/* Bit: 'IPG_CNT' */ -+/* Description: 'IPG Counter' */ -+#define AR9_PMAC_TX_IPG_IPG_CNT_OFFSET 0x00A4 -+#define AR9_PMAC_TX_IPG_IPG_CNT_SHIFT 0 -+#define AR9_PMAC_TX_IPG_IPG_CNT_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC RX IPG Counter Register' */ -+/* Bit: 'IDIS_REQ_WM' */ -+/* Description: 'Disable RX FIFO Request Watermark' */ -+#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_OFFSET 0x00A8 -+#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_SHIFT 8 -+#define AR9_PMAC_RX_IPG_IDIS_REQ_WM_SIZE 1 -+/* Bit: 'IREQ_WM' */ -+/* Description: 'RX FIFO Request Watermark' */ -+#define AR9_PMAC_RX_IPG_IREQ_WM_OFFSET 0x00A8 -+#define AR9_PMAC_RX_IPG_IREQ_WM_SHIFT 4 -+#define AR9_PMAC_RX_IPG_IREQ_WM_SIZE 4 -+/* Bit: 'IPG_CNT' */ -+/* Description: 'IPG Counter' */ -+#define AR9_PMAC_RX_IPG_IPG_CNT_OFFSET 0x00A8 -+#define AR9_PMAC_RX_IPG_IPG_CNT_SHIFT 0 -+#define AR9_PMAC_RX_IPG_IPG_CNT_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 0 Register' */ -+/* Bit: 'ADDR31_0' */ -+/* Description: 'Address [31:0]' */ -+#define AR9_ADR_TB_CTL0_REG_ADDR31_0_OFFSET 0x00AC -+#define AR9_ADR_TB_CTL0_REG_ADDR31_0_SHIFT 0 -+#define AR9_ADR_TB_CTL0_REG_ADDR31_0_SIZE 32 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 1 Register' */ -+/* Bit: 'PMAP' */ -+/* Description: 'Port Map' */ -+#define AR9_ADR_TB_CTL1_REG_PMAP_OFFSET 0x00B0 -+#define AR9_ADR_TB_CTL1_REG_PMAP_SHIFT 20 -+#define AR9_ADR_TB_CTL1_REG_PMAP_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID group' */ -+#define AR9_ADR_TB_CTL1_REG_FID_OFFSET 0x00B0 -+#define AR9_ADR_TB_CTL1_REG_FID_SHIFT 16 -+#define AR9_ADR_TB_CTL1_REG_FID_SIZE 2 -+/* Bit: 'ADDR47_32' */ -+/* Description: 'Address [47:32]' */ -+#define AR9_ADR_TB_CTL1_REG_ADDR47_32_OFFSET 0x00B0 -+#define AR9_ADR_TB_CTL1_REG_ADDR47_32_SHIFT 0 -+#define AR9_ADR_TB_CTL1_REG_ADDR47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 2 Register' */ -+/* Bit: 'IFCE' */ -+/* Description: 'Find Within Current HASH' */ -+#define AR9_ADR_TB_CTL2_REG_IFCE_OFFSET 0x00B4 -+#define AR9_ADR_TB_CTL2_REG_IFCE_SHIFT 23 -+#define AR9_ADR_TB_CTL2_REG_IFCE_SIZE 1 -+/* Bit: 'CMD' */ -+/* Description: 'Command' */ -+#define AR9_ADR_TB_CTL2_REG_CMD_OFFSET 0x00B4 -+#define AR9_ADR_TB_CTL2_REG_CMD_SHIFT 20 -+#define AR9_ADR_TB_CTL2_REG_CMD_SIZE 3 -+/* Bit: 'AC' */ -+/* Description: 'Access Control' */ -+#define AR9_ADR_TB_CTL2_REG_AC_OFFSET 0x00B4 -+#define AR9_ADR_TB_CTL2_REG_AC_SHIFT 16 -+#define AR9_ADR_TB_CTL2_REG_AC_SIZE 4 -+/* Bit: 'INFOT' */ -+/* Description: 'Info Type: Static address' */ -+#define AR9_ADR_TB_CTL2_REG_INFOT_OFFSET 0x00B4 -+#define AR9_ADR_TB_CTL2_REG_INFOT_SHIFT 12 -+#define AR9_ADR_TB_CTL2_REG_INFOT_SIZE 1 -+/* Bit: 'ITAT' */ -+/* Description: 'Info_Ctrl/Age Timer' */ -+#define AR9_ADR_TB_CTL2_REG_ITAT_OFFSET 0x00B4 -+#define AR9_ADR_TB_CTL2_REG_ITAT_SHIFT 0 -+#define AR9_ADR_TB_CTL2_REG_ITAT_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 0 Register' */ -+/* Bit: 'ADDRS31_0' */ -+/* Description: 'Address [31:0]' */ -+#define AR9_ADR_TB_ST0_REG_ADDRS31_0_OFFSET 0x00B8 -+#define AR9_ADR_TB_ST0_REG_ADDRS31_0_SHIFT 0 -+#define AR9_ADR_TB_ST0_REG_ADDRS31_0_SIZE 32 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 1 Register' */ -+/* Bit: 'PMAPS' */ -+/* Description: 'Port Map' */ -+#define AR9_ADR_TB_ST1_REG_PMAPS_OFFSET 0x00BC -+#define AR9_ADR_TB_ST1_REG_PMAPS_SHIFT 20 -+#define AR9_ADR_TB_ST1_REG_PMAPS_SIZE 8 -+/* Bit: 'FIDS' */ -+/* Description: 'FID group' */ -+#define AR9_ADR_TB_ST1_REG_FIDS_OFFSET 0x00BC -+#define AR9_ADR_TB_ST1_REG_FIDS_SHIFT 16 -+#define AR9_ADR_TB_ST1_REG_FIDS_SIZE 2 -+/* Bit: 'ADDRS47_32' */ -+/* Description: 'Address [47:32]' */ -+#define AR9_ADR_TB_ST1_REG_ADDRS47_32_OFFSET 0x00BC -+#define AR9_ADR_TB_ST1_REG_ADDRS47_32_SHIFT 0 -+#define AR9_ADR_TB_ST1_REG_ADDRS47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 2 Register' */ -+/* Bit: 'BUSY' */ -+/* Description: 'Busy: Access Logic is Busy' */ -+#define AR9_ADR_TB_ST2_REG_BUSY_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_BUSY_SHIFT 31 -+#define AR9_ADR_TB_ST2_REG_BUSY_SIZE 1 -+/* Bit: 'RSLT' */ -+/* Description: 'Result' */ -+#define AR9_ADR_TB_ST2_REG_RSLT_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_RSLT_SHIFT 28 -+#define AR9_ADR_TB_ST2_REG_RSLT_SIZE 3 -+/* Bit: 'CMD' */ -+/* Description: 'Command' */ -+#define AR9_ADR_TB_ST2_REG_CMD_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_CMD_SHIFT 20 -+#define AR9_ADR_TB_ST2_REG_CMD_SIZE 3 -+/* Bit: 'AC' */ -+/* Description: 'Access Control' */ -+#define AR9_ADR_TB_ST2_REG_AC_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_AC_SHIFT 16 -+#define AR9_ADR_TB_ST2_REG_AC_SIZE 4 -+/* Bit: 'BAD' */ -+/* Description: 'Bad Status' */ -+#define AR9_ADR_TB_ST2_REG_BAD_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_BAD_SHIFT 14 -+#define AR9_ADR_TB_ST2_REG_BAD_SIZE 1 -+/* Bit: 'OCP' */ -+/* Description: 'Occupy Status' */ -+#define AR9_ADR_TB_ST2_REG_OCP_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_OCP_SHIFT 13 -+#define AR9_ADR_TB_ST2_REG_OCP_SIZE 1 -+/* Bit: 'INFOTS' */ -+/* Description: 'Info Type: Static address' */ -+#define AR9_ADR_TB_ST2_REG_INFOTS_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_INFOTS_SHIFT 12 -+#define AR9_ADR_TB_ST2_REG_INFOTS_SIZE 1 -+/* Bit: 'ITATS' */ -+/* Description: 'Info_Ctrl/Age Timer Status' */ -+#define AR9_ADR_TB_ST2_REG_ITATS_OFFSET 0x00C0 -+#define AR9_ADR_TB_ST2_REG_ITATS_SHIFT 0 -+#define AR9_ADR_TB_ST2_REG_ITATS_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RMON Counter Control Register' */ -+/* Bit: 'BAS' */ -+/* Description: 'Busy/Access Start' */ -+#define AR9_RMON_CTL_REG_BAS_OFFSET 0x00C4 -+#define AR9_RMON_CTL_REG_BAS_SHIFT 11 -+#define AR9_RMON_CTL_REG_BAS_SIZE 1 -+/* Bit: 'CAC' */ -+/* Description: 'Command for access counter' */ -+#define AR9_RMON_CTL_REG_CAC_OFFSET 0x00C4 -+#define AR9_RMON_CTL_REG_CAC_SHIFT 9 -+#define AR9_RMON_CTL_REG_CAC_SIZE 2 -+/* Bit: 'PORTC' */ -+/* Description: 'Port' */ -+#define AR9_RMON_CTL_REG_PORTC_OFFSET 0x00C4 -+#define AR9_RMON_CTL_REG_PORTC_SHIFT 6 -+#define AR9_RMON_CTL_REG_PORTC_SIZE 3 -+/* Bit: 'OFFSET' */ -+/* Description: 'Counter Offset' */ -+#define AR9_RMON_CTL_REG_OFFSET_OFFSET 0x00C4 -+#define AR9_RMON_CTL_REG_OFFSET_SHIFT 0 -+#define AR9_RMON_CTL_REG_OFFSET_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RMON Counter Status Register' */ -+/* Bit: 'COUNTER' */ -+/* Description: 'RMON Counter field 31:0 or counter field 63:32' */ -+#define AR9_RMON_ST_REG_COUNTER_OFFSET 0x00C8 -+#define AR9_RMON_ST_REG_COUNTER_SHIFT 0 -+#define AR9_RMON_ST_REG_COUNTER_SIZE 32 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDIO Indirect Access Control' */ -+/* Bit: 'WD' */ -+/* Description: 'The Write Data to the MDIO register' */ -+#define AR9_MDIO_CTL_REG_WD_OFFSET 0x00CC -+#define AR9_MDIO_CTL_REG_WD_SHIFT 16 -+#define AR9_MDIO_CTL_REG_WD_SIZE 16 -+/* Bit: 'MBUSY' */ -+/* Description: 'Busy state' */ -+#define AR9_MDIO_CTL_REG_MBUSY_OFFSET 0x00CC -+#define AR9_MDIO_CTL_REG_MBUSY_SHIFT 15 -+#define AR9_MDIO_CTL_REG_MBUSY_SIZE 1 -+/* Bit: 'OP' */ -+/* Description: 'Operation Code' */ -+#define AR9_MDIO_CTL_REG_OP_OFFSET 0x00CC -+#define AR9_MDIO_CTL_REG_OP_SHIFT 10 -+#define AR9_MDIO_CTL_REG_OP_SIZE 2 -+/* Bit: 'PHYAD' */ -+/* Description: 'PHY Address' */ -+#define AR9_MDIO_CTL_REG_PHYAD_OFFSET 0x00CC -+#define AR9_MDIO_CTL_REG_PHYAD_SHIFT 5 -+#define AR9_MDIO_CTL_REG_PHYAD_SIZE 5 -+/* Bit: 'REGAD' */ -+/* Description: 'Register Address' */ -+#define AR9_MDIO_CTL_REG_REGAD_OFFSET 0x00CC -+#define AR9_MDIO_CTL_REG_REGAD_SHIFT 0 -+#define AR9_MDIO_CTL_REG_REGAD_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDIO Indirect Read Data' */ -+/* Bit: 'RD' */ -+/* Description: 'The Read Data' */ -+#define AR9_MDIO_DATA_REG_RD_OFFSET 0x00D0 -+#define AR9_MDIO_DATA_REG_RD_SHIFT 0 -+#define AR9_MDIO_DATA_REG_RD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter Action' */ -+/* Bit: 'QATF7' */ -+/* Description: 'Destination Queue for Type Filter 7' */ -+#define AR9_TP_FLT_ACT_REG_QATF7_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QATF7_SHIFT 30 -+#define AR9_TP_FLT_ACT_REG_QATF7_SIZE 2 -+/* Bit: 'QATF6' */ -+/* Description: 'Destination Queue for Type Filter 6' */ -+#define AR9_TP_FLT_ACT_REG_QATF6_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QATF6_SHIFT 28 -+#define AR9_TP_FLT_ACT_REG_QATF6_SIZE 2 -+/* Bit: 'QTF5' */ -+/* Description: 'Destination Queue for Type Filter 5' */ -+#define AR9_TP_FLT_ACT_REG_QTF5_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF5_SHIFT 26 -+#define AR9_TP_FLT_ACT_REG_QTF5_SIZE 2 -+/* Bit: 'QTF4' */ -+/* Description: 'Destination Queue for Type Filter 4' */ -+#define AR9_TP_FLT_ACT_REG_QTF4_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF4_SHIFT 24 -+#define AR9_TP_FLT_ACT_REG_QTF4_SIZE 2 -+/* Bit: 'QTF3' */ -+/* Description: 'Destination Queue for Type Filter 3' */ -+#define AR9_TP_FLT_ACT_REG_QTF3_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF3_SHIFT 22 -+#define AR9_TP_FLT_ACT_REG_QTF3_SIZE 2 -+/* Bit: 'QTF2' */ -+/* Description: 'Destination Queue for Type Filter 2' */ -+#define AR9_TP_FLT_ACT_REG_QTF2_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF2_SHIFT 20 -+#define AR9_TP_FLT_ACT_REG_QTF2_SIZE 2 -+/* Bit: 'QTF1' */ -+/* Description: 'Destination Queue for Type Filter 1' */ -+#define AR9_TP_FLT_ACT_REG_QTF1_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF1_SHIFT 18 -+#define AR9_TP_FLT_ACT_REG_QTF1_SIZE 2 -+/* Bit: 'QTF0' */ -+/* Description: 'Destination Queue for Type Filter 0' */ -+#define AR9_TP_FLT_ACT_REG_QTF0_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_QTF0_SHIFT 16 -+#define AR9_TP_FLT_ACT_REG_QTF0_SIZE 2 -+/* Bit: 'ATF7' */ -+/* Description: 'Action for Type Filter 7' */ -+#define AR9_TP_FLT_ACT_REG_ATF7_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF7_SHIFT 14 -+#define AR9_TP_FLT_ACT_REG_ATF7_SIZE 2 -+/* Bit: 'ATF6' */ -+/* Description: 'Action for Type Filter 6' */ -+#define AR9_TP_FLT_ACT_REG_ATF6_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF6_SHIFT 12 -+#define AR9_TP_FLT_ACT_REG_ATF6_SIZE 2 -+/* Bit: 'ATF5' */ -+/* Description: 'Action for Type Filter 5' */ -+#define AR9_TP_FLT_ACT_REG_ATF5_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF5_SHIFT 10 -+#define AR9_TP_FLT_ACT_REG_ATF5_SIZE 2 -+/* Bit: 'ATF4' */ -+/* Description: 'Action for Type Filter 4' */ -+#define AR9_TP_FLT_ACT_REG_ATF4_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF4_SHIFT 8 -+#define AR9_TP_FLT_ACT_REG_ATF4_SIZE 2 -+/* Bit: 'ATF3' */ -+/* Description: 'Action for Type Filter 3' */ -+#define AR9_TP_FLT_ACT_REG_ATF3_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF3_SHIFT 6 -+#define AR9_TP_FLT_ACT_REG_ATF3_SIZE 2 -+/* Bit: 'ATF2' */ -+/* Description: 'Action for Type Filter 2' */ -+#define AR9_TP_FLT_ACT_REG_ATF2_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF2_SHIFT 4 -+#define AR9_TP_FLT_ACT_REG_ATF2_SIZE 2 -+/* Bit: 'ATF1' */ -+/* Description: 'Action for Type Filter 1' */ -+#define AR9_TP_FLT_ACT_REG_ATF1_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF1_SHIFT 2 -+#define AR9_TP_FLT_ACT_REG_ATF1_SIZE 2 -+/* Bit: 'ATF0' */ -+/* Description: 'Action for Type Filter 0' */ -+#define AR9_TP_FLT_ACT_REG_ATF0_OFFSET 0x00D4 -+#define AR9_TP_FLT_ACT_REG_ATF0_SHIFT 0 -+#define AR9_TP_FLT_ACT_REG_ATF0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter Action' */ -+/* Bit: 'APF7' */ -+/* Description: 'Action for Protocol Filter 7' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF7_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF7_SHIFT 14 -+#define AR9_PRTCL_FLT_ACT_REG_APF7_SIZE 2 -+/* Bit: 'APF6' */ -+/* Description: 'Action for Protocol Filter 6' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF6_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF6_SHIFT 12 -+#define AR9_PRTCL_FLT_ACT_REG_APF6_SIZE 2 -+/* Bit: 'APF5' */ -+/* Description: 'Action for Protocol Filter 5' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF5_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF5_SHIFT 10 -+#define AR9_PRTCL_FLT_ACT_REG_APF5_SIZE 2 -+/* Bit: 'APF4' */ -+/* Description: 'Action for Protocol Filter 4' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF4_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF4_SHIFT 8 -+#define AR9_PRTCL_FLT_ACT_REG_APF4_SIZE 2 -+/* Bit: 'APF3' */ -+/* Description: 'Action for Protocol Filter 3' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF3_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF3_SHIFT 6 -+#define AR9_PRTCL_FLT_ACT_REG_APF3_SIZE 2 -+/* Bit: 'APF2' */ -+/* Description: 'Action for Protocol Filter 2' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF2_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF2_SHIFT 4 -+#define AR9_PRTCL_FLT_ACT_REG_APF2_SIZE 2 -+/* Bit: 'APF1' */ -+/* Description: 'Action for Protocol Filter 1' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF1_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF1_SHIFT 2 -+#define AR9_PRTCL_FLT_ACT_REG_APF1_SIZE 2 -+/* Bit: 'APF0' */ -+/* Description: 'Action for Protocol Filter 0' */ -+#define AR9_PRTCL_FLT_ACT_REG_APF0_OFFSET 0x00D8 -+#define AR9_PRTCL_FLT_ACT_REG_APF0_SHIFT 0 -+#define AR9_PRTCL_FLT_ACT_REG_APF0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 0' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT0_REG_M_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT0_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT0_REG_FID_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT0_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT0_REG_TM_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT0_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT0_REG_VV_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT0_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT0_REG_VP_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT0_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT0_REG_VID_OFFSET 0x0100 -+#define AR9_VLAN_FLT0_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT0_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 1' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT1_REG_M_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT1_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT1_REG_FID_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT1_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT1_REG_TM_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT1_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT1_REG_VV_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT1_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT1_REG_VP_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT1_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT1_REG_VID_OFFSET 0x0104 -+#define AR9_VLAN_FLT1_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT1_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 2' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT2_REG_M_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT2_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT2_REG_FID_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT2_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT2_REG_TM_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT2_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT2_REG_VV_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT2_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT2_REG_VP_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT2_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT2_REG_VID_OFFSET 0x0108 -+#define AR9_VLAN_FLT2_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT2_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 3' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT3_REG_M_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT3_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT3_REG_FID_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT3_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT3_REG_TM_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT3_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT3_REG_VV_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT3_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT3_REG_VP_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT3_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT3_REG_VID_OFFSET 0x010C -+#define AR9_VLAN_FLT3_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT3_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 4' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT4_REG_M_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT4_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT4_REG_FID_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT4_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT4_REG_TM_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT4_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT4_REG_VV_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT4_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT4_REG_VP_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT4_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT4_REG_VID_OFFSET 0x0110 -+#define AR9_VLAN_FLT4_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT4_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 5' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT5_REG_M_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT5_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT5_REG_FID_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT5_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT5_REG_TM_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT5_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT5_REG_VV_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT5_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT5_REG_VP_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT5_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT5_REG_VID_OFFSET 0x0114 -+#define AR9_VLAN_FLT5_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT5_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 6' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT6_REG_M_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT6_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT6_REG_FID_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT6_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT6_REG_TM_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT6_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT6_REG_VV_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT6_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT6_REG_VP_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT6_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT6_REG_VID_OFFSET 0x0118 -+#define AR9_VLAN_FLT6_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT6_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 7' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT7_REG_M_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT7_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT7_REG_FID_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT7_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT7_REG_TM_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT7_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT7_REG_VV_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT7_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT7_REG_VP_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT7_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT7_REG_VID_OFFSET 0x011C -+#define AR9_VLAN_FLT7_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT7_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 8' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT8_REG_M_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT8_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT8_REG_FID_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT8_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT8_REG_TM_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT8_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT8_REG_VV_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT8_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT8_REG_VP_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT8_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT8_REG_VID_OFFSET 0x0120 -+#define AR9_VLAN_FLT8_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT8_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 9' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT9_REG_M_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT9_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT9_REG_FID_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT9_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT9_REG_TM_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT9_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT9_REG_VV_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT9_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT9_REG_VP_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT9_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT9_REG_VID_OFFSET 0x0124 -+#define AR9_VLAN_FLT9_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT9_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 10' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT10_REG_M_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT10_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT10_REG_FID_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT10_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT10_REG_TM_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT10_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT10_REG_VV_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT10_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT10_REG_VP_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT10_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT10_REG_VID_OFFSET 0x0128 -+#define AR9_VLAN_FLT10_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT10_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 11' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT11_REG_M_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT11_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT11_REG_FID_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT11_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT11_REG_TM_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT11_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT11_REG_VV_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT11_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT11_REG_VP_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT11_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT11_REG_VID_OFFSET 0x012C -+#define AR9_VLAN_FLT11_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT11_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 12' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT12_REG_M_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT12_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT12_REG_FID_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT12_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT12_REG_TM_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT12_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT12_REG_VV_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT12_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT12_REG_VP_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT12_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT12_REG_VID_OFFSET 0x0130 -+#define AR9_VLAN_FLT12_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT12_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 13' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT13_REG_M_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT13_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT13_REG_FID_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT13_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT13_REG_TM_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT13_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT13_REG_VV_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT13_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT13_REG_VP_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT13_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT13_REG_VID_OFFSET 0x0134 -+#define AR9_VLAN_FLT13_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT13_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 14' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT14_REG_M_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT14_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT14_REG_FID_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT14_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT14_REG_TM_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT14_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT14_REG_VV_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT14_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT14_REG_VP_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT14_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT14_REG_VID_OFFSET 0x0138 -+#define AR9_VLAN_FLT14_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT14_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 15' */ -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define AR9_VLAN_FLT15_REG_M_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_M_SHIFT 24 -+#define AR9_VLAN_FLT15_REG_M_SIZE 8 -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define AR9_VLAN_FLT15_REG_FID_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_FID_SHIFT 22 -+#define AR9_VLAN_FLT15_REG_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define AR9_VLAN_FLT15_REG_TM_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_TM_SHIFT 19 -+#define AR9_VLAN_FLT15_REG_TM_SIZE 3 -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define AR9_VLAN_FLT15_REG_VV_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_VV_SHIFT 15 -+#define AR9_VLAN_FLT15_REG_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define AR9_VLAN_FLT15_REG_VP_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_VP_SHIFT 12 -+#define AR9_VLAN_FLT15_REG_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define AR9_VLAN_FLT15_REG_VID_OFFSET 0x013C -+#define AR9_VLAN_FLT15_REG_VID_SHIFT 0 -+#define AR9_VLAN_FLT15_REG_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 10' */ -+/* Bit: 'VCET1' */ -+/* Description: 'Value 1 Compared with Ether-Type' */ -+#define AR9_TP_FLT10_REG_VCET1_OFFSET 0x0140 -+#define AR9_TP_FLT10_REG_VCET1_SHIFT 16 -+#define AR9_TP_FLT10_REG_VCET1_SIZE 16 -+/* Bit: 'VCET0' */ -+/* Description: 'Value 0 Compared with Ether-Type' */ -+#define AR9_TP_FLT10_REG_VCET0_OFFSET 0x0140 -+#define AR9_TP_FLT10_REG_VCET0_SHIFT 0 -+#define AR9_TP_FLT10_REG_VCET0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 32' */ -+/* Bit: 'VCET1' */ -+/* Description: 'Value 1 Compared with Ether-Type' */ -+#define AR9_TP_FLT32_REG_VCET1_OFFSET 0x0144 -+#define AR9_TP_FLT32_REG_VCET1_SHIFT 16 -+#define AR9_TP_FLT32_REG_VCET1_SIZE 16 -+/* Bit: 'VCET0' */ -+/* Description: 'Value 0 Compared with Ether-Type' */ -+#define AR9_TP_FLT32_REG_VCET0_OFFSET 0x0144 -+#define AR9_TP_FLT32_REG_VCET0_SHIFT 0 -+#define AR9_TP_FLT32_REG_VCET0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 54' */ -+/* Bit: 'VCET1' */ -+/* Description: 'Value 1 Compared with Ether-Type' */ -+#define AR9_TP_FLT54_REG_VCET1_OFFSET 0x0148 -+#define AR9_TP_FLT54_REG_VCET1_SHIFT 16 -+#define AR9_TP_FLT54_REG_VCET1_SIZE 16 -+/* Bit: 'VCET0' */ -+/* Description: 'Value 0 Compared with Ether-Type' */ -+#define AR9_TP_FLT54_REG_VCET0_OFFSET 0x0148 -+#define AR9_TP_FLT54_REG_VCET0_SHIFT 0 -+#define AR9_TP_FLT54_REG_VCET0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 76' */ -+/* Bit: 'VCET1' */ -+/* Description: 'Value 1 Compared with Ether-Type' */ -+#define AR9_TP_FLT76_REG_VCET1_OFFSET 0x014C -+#define AR9_TP_FLT76_REG_VCET1_SHIFT 16 -+#define AR9_TP_FLT76_REG_VCET1_SIZE 16 -+/* Bit: 'VCET0' */ -+/* Description: 'Value 0 Compared with Ether-Type' */ -+#define AR9_TP_FLT76_REG_VCET0_OFFSET 0x014C -+#define AR9_TP_FLT76_REG_VCET0_SHIFT 0 -+#define AR9_TP_FLT76_REG_VCET0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 0' */ -+/* Bit: 'PQF' */ -+/* Description: 'Priority Queue F' */ -+#define AR9_DFSRV_MAP0_REG_PQF_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQF_SHIFT 30 -+#define AR9_DFSRV_MAP0_REG_PQF_SIZE 2 -+/* Bit: 'PQE' */ -+/* Description: 'Priority Queue E' */ -+#define AR9_DFSRV_MAP0_REG_PQE_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQE_SHIFT 28 -+#define AR9_DFSRV_MAP0_REG_PQE_SIZE 2 -+/* Bit: 'PQD' */ -+/* Description: 'Priority Queue D' */ -+#define AR9_DFSRV_MAP0_REG_PQD_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQD_SHIFT 26 -+#define AR9_DFSRV_MAP0_REG_PQD_SIZE 2 -+/* Bit: 'PQC' */ -+/* Description: 'Priority Queue C' */ -+#define AR9_DFSRV_MAP0_REG_PQC_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQC_SHIFT 24 -+#define AR9_DFSRV_MAP0_REG_PQC_SIZE 2 -+/* Bit: 'PQB' */ -+/* Description: 'Priority Queue B' */ -+#define AR9_DFSRV_MAP0_REG_PQB_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQB_SHIFT 22 -+#define AR9_DFSRV_MAP0_REG_PQB_SIZE 2 -+/* Bit: 'PQA' */ -+/* Description: 'Priority Queue A' */ -+#define AR9_DFSRV_MAP0_REG_PQA_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQA_SHIFT 20 -+#define AR9_DFSRV_MAP0_REG_PQA_SIZE 2 -+/* Bit: 'PQ9' */ -+/* Description: 'Priority Queue 9' */ -+#define AR9_DFSRV_MAP0_REG_PQ9_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ9_SHIFT 18 -+#define AR9_DFSRV_MAP0_REG_PQ9_SIZE 2 -+/* Bit: 'PQ8' */ -+/* Description: 'Priority Queue 8' */ -+#define AR9_DFSRV_MAP0_REG_PQ8_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ8_SHIFT 16 -+#define AR9_DFSRV_MAP0_REG_PQ8_SIZE 2 -+/* Bit: 'PQ7' */ -+/* Description: 'Priority Queue 7' */ -+#define AR9_DFSRV_MAP0_REG_PQ7_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ7_SHIFT 14 -+#define AR9_DFSRV_MAP0_REG_PQ7_SIZE 2 -+/* Bit: 'PQ6' */ -+/* Description: 'Priority Queue 6' */ -+#define AR9_DFSRV_MAP0_REG_PQ6_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ6_SHIFT 12 -+#define AR9_DFSRV_MAP0_REG_PQ6_SIZE 2 -+/* Bit: 'PQ5' */ -+/* Description: 'Priority Queue 5' */ -+#define AR9_DFSRV_MAP0_REG_PQ5_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ5_SHIFT 10 -+#define AR9_DFSRV_MAP0_REG_PQ5_SIZE 2 -+/* Bit: 'PQ4' */ -+/* Description: 'Priority Queue 4' */ -+#define AR9_DFSRV_MAP0_REG_PQ4_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ4_SHIFT 8 -+#define AR9_DFSRV_MAP0_REG_PQ4_SIZE 2 -+/* Bit: 'PQ3' */ -+/* Description: 'Priority Queue 3' */ -+#define AR9_DFSRV_MAP0_REG_PQ3_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ3_SHIFT 6 -+#define AR9_DFSRV_MAP0_REG_PQ3_SIZE 2 -+/* Bit: 'PQ2' */ -+/* Description: 'Priority Queue 2' */ -+#define AR9_DFSRV_MAP0_REG_PQ2_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ2_SHIFT 4 -+#define AR9_DFSRV_MAP0_REG_PQ2_SIZE 2 -+/* Bit: 'PQ1' */ -+/* Description: 'Priority Queue 1' */ -+#define AR9_DFSRV_MAP0_REG_PQ1_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ1_SHIFT 2 -+#define AR9_DFSRV_MAP0_REG_PQ1_SIZE 2 -+/* Bit: 'PQ0' */ -+/* Description: 'Priority Queue 0' */ -+#define AR9_DFSRV_MAP0_REG_PQ0_OFFSET 0x0150 -+#define AR9_DFSRV_MAP0_REG_PQ0_SHIFT 0 -+#define AR9_DFSRV_MAP0_REG_PQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 1' */ -+/* Bit: 'PQ1F' */ -+/* Description: 'Priority Queue 1F' */ -+#define AR9_DFSRV_MAP1_REG_PQ1F_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1F_SHIFT 30 -+#define AR9_DFSRV_MAP1_REG_PQ1F_SIZE 2 -+/* Bit: 'PQ1E' */ -+/* Description: 'Priority Queue 1E' */ -+#define AR9_DFSRV_MAP1_REG_PQ1E_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1E_SHIFT 28 -+#define AR9_DFSRV_MAP1_REG_PQ1E_SIZE 2 -+/* Bit: 'PQ1D' */ -+/* Description: 'Priority Queue 1D' */ -+#define AR9_DFSRV_MAP1_REG_PQ1D_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1D_SHIFT 26 -+#define AR9_DFSRV_MAP1_REG_PQ1D_SIZE 2 -+/* Bit: 'PQ1C' */ -+/* Description: 'Priority Queue 1C' */ -+#define AR9_DFSRV_MAP1_REG_PQ1C_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1C_SHIFT 24 -+#define AR9_DFSRV_MAP1_REG_PQ1C_SIZE 2 -+/* Bit: 'PQ1B' */ -+/* Description: 'Priority Queue 1B' */ -+#define AR9_DFSRV_MAP1_REG_PQ1B_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1B_SHIFT 22 -+#define AR9_DFSRV_MAP1_REG_PQ1B_SIZE 2 -+/* Bit: 'PQ1A' */ -+/* Description: 'Priority Queue 1A' */ -+#define AR9_DFSRV_MAP1_REG_PQ1A_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ1A_SHIFT 20 -+#define AR9_DFSRV_MAP1_REG_PQ1A_SIZE 2 -+/* Bit: 'PQ19' */ -+/* Description: 'Priority Queue 19' */ -+#define AR9_DFSRV_MAP1_REG_PQ19_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ19_SHIFT 18 -+#define AR9_DFSRV_MAP1_REG_PQ19_SIZE 2 -+/* Bit: 'PQ18' */ -+/* Description: 'Priority Queue 18' */ -+#define AR9_DFSRV_MAP1_REG_PQ18_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ18_SHIFT 16 -+#define AR9_DFSRV_MAP1_REG_PQ18_SIZE 2 -+/* Bit: 'PQ17' */ -+/* Description: 'Priority Queue 17' */ -+#define AR9_DFSRV_MAP1_REG_PQ17_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ17_SHIFT 14 -+#define AR9_DFSRV_MAP1_REG_PQ17_SIZE 2 -+/* Bit: 'PQ16' */ -+/* Description: 'Priority Queue 16' */ -+#define AR9_DFSRV_MAP1_REG_PQ16_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ16_SHIFT 12 -+#define AR9_DFSRV_MAP1_REG_PQ16_SIZE 2 -+/* Bit: 'PQ15' */ -+/* Description: 'Priority Queue 15' */ -+#define AR9_DFSRV_MAP1_REG_PQ15_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ15_SHIFT 10 -+#define AR9_DFSRV_MAP1_REG_PQ15_SIZE 2 -+/* Bit: 'PQ14' */ -+/* Description: 'Priority Queue 14' */ -+#define AR9_DFSRV_MAP1_REG_PQ14_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ14_SHIFT 8 -+#define AR9_DFSRV_MAP1_REG_PQ14_SIZE 2 -+/* Bit: 'PQ13' */ -+/* Description: 'Priority Queue 13' */ -+#define AR9_DFSRV_MAP1_REG_PQ13_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ13_SHIFT 6 -+#define AR9_DFSRV_MAP1_REG_PQ13_SIZE 2 -+/* Bit: 'PQ12' */ -+/* Description: 'Priority Queue 12' */ -+#define AR9_DFSRV_MAP1_REG_PQ12_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ12_SHIFT 4 -+#define AR9_DFSRV_MAP1_REG_PQ12_SIZE 2 -+/* Bit: 'PQ11' */ -+/* Description: 'Priority Queue 11' */ -+#define AR9_DFSRV_MAP1_REG_PQ11_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ11_SHIFT 2 -+#define AR9_DFSRV_MAP1_REG_PQ11_SIZE 2 -+/* Bit: 'PQ10' */ -+/* Description: 'Priority Queue 10' */ -+#define AR9_DFSRV_MAP1_REG_PQ10_OFFSET 0x0154 -+#define AR9_DFSRV_MAP1_REG_PQ10_SHIFT 0 -+#define AR9_DFSRV_MAP1_REG_PQ10_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 2' */ -+/* Bit: 'PQ2F' */ -+/* Description: 'Priority Queue 2F' */ -+#define AR9_DFSRV_MAP2_REG_PQ2F_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2F_SHIFT 30 -+#define AR9_DFSRV_MAP2_REG_PQ2F_SIZE 2 -+/* Bit: 'PQ2E' */ -+/* Description: 'Priority Queue 2E' */ -+#define AR9_DFSRV_MAP2_REG_PQ2E_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2E_SHIFT 28 -+#define AR9_DFSRV_MAP2_REG_PQ2E_SIZE 2 -+/* Bit: 'PQ2D' */ -+/* Description: 'Priority Queue 2D' */ -+#define AR9_DFSRV_MAP2_REG_PQ2D_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2D_SHIFT 26 -+#define AR9_DFSRV_MAP2_REG_PQ2D_SIZE 2 -+/* Bit: 'PQ2C' */ -+/* Description: 'Priority Queue 2C' */ -+#define AR9_DFSRV_MAP2_REG_PQ2C_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2C_SHIFT 24 -+#define AR9_DFSRV_MAP2_REG_PQ2C_SIZE 2 -+/* Bit: 'PQ2B' */ -+/* Description: 'Priority Queue 2B' */ -+#define AR9_DFSRV_MAP2_REG_PQ2B_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2B_SHIFT 22 -+#define AR9_DFSRV_MAP2_REG_PQ2B_SIZE 2 -+/* Bit: 'PQ2A' */ -+/* Description: 'Priority Queue 2A' */ -+#define AR9_DFSRV_MAP2_REG_PQ2A_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ2A_SHIFT 20 -+#define AR9_DFSRV_MAP2_REG_PQ2A_SIZE 2 -+/* Bit: 'PQ29' */ -+/* Description: 'Priority Queue 29' */ -+#define AR9_DFSRV_MAP2_REG_PQ29_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ29_SHIFT 18 -+#define AR9_DFSRV_MAP2_REG_PQ29_SIZE 2 -+/* Bit: 'PQ28' */ -+/* Description: 'Priority Queue 28' */ -+#define AR9_DFSRV_MAP2_REG_PQ28_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ28_SHIFT 16 -+#define AR9_DFSRV_MAP2_REG_PQ28_SIZE 2 -+/* Bit: 'PQ27' */ -+/* Description: 'Priority Queue 27' */ -+#define AR9_DFSRV_MAP2_REG_PQ27_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ27_SHIFT 14 -+#define AR9_DFSRV_MAP2_REG_PQ27_SIZE 2 -+/* Bit: 'PQ26' */ -+/* Description: 'Priority Queue 26' */ -+#define AR9_DFSRV_MAP2_REG_PQ26_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ26_SHIFT 12 -+#define AR9_DFSRV_MAP2_REG_PQ26_SIZE 2 -+/* Bit: 'PQ25' */ -+/* Description: 'Priority Queue 25' */ -+#define AR9_DFSRV_MAP2_REG_PQ25_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ25_SHIFT 10 -+#define AR9_DFSRV_MAP2_REG_PQ25_SIZE 2 -+/* Bit: 'PQ24' */ -+/* Description: 'Priority Queue 24' */ -+#define AR9_DFSRV_MAP2_REG_PQ24_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ24_SHIFT 8 -+#define AR9_DFSRV_MAP2_REG_PQ24_SIZE 2 -+/* Bit: 'PQ23' */ -+/* Description: 'Priority Queue 23' */ -+#define AR9_DFSRV_MAP2_REG_PQ23_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ23_SHIFT 6 -+#define AR9_DFSRV_MAP2_REG_PQ23_SIZE 2 -+/* Bit: 'PQ22' */ -+/* Description: 'Priority Queue 22' */ -+#define AR9_DFSRV_MAP2_REG_PQ22_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ22_SHIFT 4 -+#define AR9_DFSRV_MAP2_REG_PQ22_SIZE 2 -+/* Bit: 'PQ21' */ -+/* Description: 'Priority Queue 21' */ -+#define AR9_DFSRV_MAP2_REG_PQ21_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ21_SHIFT 2 -+#define AR9_DFSRV_MAP2_REG_PQ21_SIZE 2 -+/* Bit: 'PQ20' */ -+/* Description: 'Priority Queue 20' */ -+#define AR9_DFSRV_MAP2_REG_PQ20_OFFSET 0x0158 -+#define AR9_DFSRV_MAP2_REG_PQ20_SHIFT 0 -+#define AR9_DFSRV_MAP2_REG_PQ20_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 3' */ -+/* Bit: 'PQ3F' */ -+/* Description: 'Priority Queue 3F' */ -+#define AR9_DFSRV_MAP3_REG_PQ3F_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3F_SHIFT 30 -+#define AR9_DFSRV_MAP3_REG_PQ3F_SIZE 2 -+/* Bit: 'PQ3E' */ -+/* Description: 'Priority Queue 3E' */ -+#define AR9_DFSRV_MAP3_REG_PQ3E_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3E_SHIFT 28 -+#define AR9_DFSRV_MAP3_REG_PQ3E_SIZE 2 -+/* Bit: 'PQ3D' */ -+/* Description: 'Priority Queue 3D' */ -+#define AR9_DFSRV_MAP3_REG_PQ3D_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3D_SHIFT 26 -+#define AR9_DFSRV_MAP3_REG_PQ3D_SIZE 2 -+/* Bit: 'PQ3C' */ -+/* Description: 'Priority Queue 3C' */ -+#define AR9_DFSRV_MAP3_REG_PQ3C_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3C_SHIFT 24 -+#define AR9_DFSRV_MAP3_REG_PQ3C_SIZE 2 -+/* Bit: 'PQ3B' */ -+/* Description: 'Priority Queue 3B' */ -+#define AR9_DFSRV_MAP3_REG_PQ3B_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3B_SHIFT 22 -+#define AR9_DFSRV_MAP3_REG_PQ3B_SIZE 2 -+/* Bit: 'PQ3A' */ -+/* Description: 'Priority Queue 3A' */ -+#define AR9_DFSRV_MAP3_REG_PQ3A_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ3A_SHIFT 20 -+#define AR9_DFSRV_MAP3_REG_PQ3A_SIZE 2 -+/* Bit: 'PQ39' */ -+/* Description: 'Priority Queue 39' */ -+#define AR9_DFSRV_MAP3_REG_PQ39_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ39_SHIFT 18 -+#define AR9_DFSRV_MAP3_REG_PQ39_SIZE 2 -+/* Bit: 'PQ38' */ -+/* Description: 'Priority Queue 38' */ -+#define AR9_DFSRV_MAP3_REG_PQ38_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ38_SHIFT 16 -+#define AR9_DFSRV_MAP3_REG_PQ38_SIZE 2 -+/* Bit: 'PQ37' */ -+/* Description: 'Priority Queue 37' */ -+#define AR9_DFSRV_MAP3_REG_PQ37_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ37_SHIFT 14 -+#define AR9_DFSRV_MAP3_REG_PQ37_SIZE 2 -+/* Bit: 'PQ36' */ -+/* Description: 'Priority Queue 36' */ -+#define AR9_DFSRV_MAP3_REG_PQ36_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ36_SHIFT 12 -+#define AR9_DFSRV_MAP3_REG_PQ36_SIZE 2 -+/* Bit: 'PQ35' */ -+/* Description: 'Priority Queue 35' */ -+#define AR9_DFSRV_MAP3_REG_PQ35_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ35_SHIFT 10 -+#define AR9_DFSRV_MAP3_REG_PQ35_SIZE 2 -+/* Bit: 'PQ34' */ -+/* Description: 'Priority Queue 34' */ -+#define AR9_DFSRV_MAP3_REG_PQ34_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ34_SHIFT 8 -+#define AR9_DFSRV_MAP3_REG_PQ34_SIZE 2 -+/* Bit: 'PQ33' */ -+/* Description: 'Priority Queue 33' */ -+#define AR9_DFSRV_MAP3_REG_PQ33_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ33_SHIFT 6 -+#define AR9_DFSRV_MAP3_REG_PQ33_SIZE 2 -+/* Bit: 'PQ32' */ -+/* Description: 'Priority Queue 32' */ -+#define AR9_DFSRV_MAP3_REG_PQ32_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ32_SHIFT 4 -+#define AR9_DFSRV_MAP3_REG_PQ32_SIZE 2 -+/* Bit: 'PQ31' */ -+/* Description: 'Priority Queue 31' */ -+#define AR9_DFSRV_MAP3_REG_PQ31_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ31_SHIFT 2 -+#define AR9_DFSRV_MAP3_REG_PQ31_SIZE 2 -+/* Bit: 'PQ30' */ -+/* Description: 'Priority Queue 30' */ -+#define AR9_DFSRV_MAP3_REG_PQ30_OFFSET 0x015C -+#define AR9_DFSRV_MAP3_REG_PQ30_SHIFT 0 -+#define AR9_DFSRV_MAP3_REG_PQ30_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 0' */ -+/* Bit: 'ATUF0' */ -+/* Description: 'Action for TCP/UDP Port Filter 0' */ -+#define AR9_TCP_PF0_REG_ATUF0_OFFSET 0x0160 -+#define AR9_TCP_PF0_REG_ATUF0_SHIFT 28 -+#define AR9_TCP_PF0_REG_ATUF0_SIZE 2 -+/* Bit: 'TUPF0' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 0' */ -+#define AR9_TCP_PF0_REG_TUPF0_OFFSET 0x0160 -+#define AR9_TCP_PF0_REG_TUPF0_SHIFT 26 -+#define AR9_TCP_PF0_REG_TUPF0_SIZE 2 -+/* Bit: 'COMP0' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF0_REG_COMP0_OFFSET 0x0160 -+#define AR9_TCP_PF0_REG_COMP0_SHIFT 24 -+#define AR9_TCP_PF0_REG_COMP0_SIZE 2 -+/* Bit: 'PRANGE0' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF0_REG_PRANGE0_OFFSET 0x0160 -+#define AR9_TCP_PF0_REG_PRANGE0_SHIFT 16 -+#define AR9_TCP_PF0_REG_PRANGE0_SIZE 8 -+/* Bit: 'BASEPT0' */ -+/* Description: 'Base Port number 0' */ -+#define AR9_TCP_PF0_REG_BASEPT0_OFFSET 0x0160 -+#define AR9_TCP_PF0_REG_BASEPT0_SHIFT 0 -+#define AR9_TCP_PF0_REG_BASEPT0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 1' */ -+/* Bit: 'ATUF1' */ -+/* Description: 'Action for TCP/UDP Port Filter 1' */ -+#define AR9_TCP_PF1_REG_ATUF1_OFFSET 0x0164 -+#define AR9_TCP_PF1_REG_ATUF1_SHIFT 28 -+#define AR9_TCP_PF1_REG_ATUF1_SIZE 2 -+/* Bit: 'TUPF1' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 1' */ -+#define AR9_TCP_PF1_REG_TUPF1_OFFSET 0x0164 -+#define AR9_TCP_PF1_REG_TUPF1_SHIFT 26 -+#define AR9_TCP_PF1_REG_TUPF1_SIZE 2 -+/* Bit: 'COMP1' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF1_REG_COMP1_OFFSET 0x0164 -+#define AR9_TCP_PF1_REG_COMP1_SHIFT 24 -+#define AR9_TCP_PF1_REG_COMP1_SIZE 2 -+/* Bit: 'PRANGE1' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF1_REG_PRANGE1_OFFSET 0x0164 -+#define AR9_TCP_PF1_REG_PRANGE1_SHIFT 16 -+#define AR9_TCP_PF1_REG_PRANGE1_SIZE 8 -+/* Bit: 'BASEPT1' */ -+/* Description: 'Base Port number 1' */ -+#define AR9_TCP_PF1_REG_BASEPT1_OFFSET 0x0164 -+#define AR9_TCP_PF1_REG_BASEPT1_SHIFT 0 -+#define AR9_TCP_PF1_REG_BASEPT1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 2' */ -+/* Bit: 'ATUF2' */ -+/* Description: 'Action for TCP/UDP Port Filter 2' */ -+#define AR9_TCP_PF2_REG_ATUF2_OFFSET 0x0168 -+#define AR9_TCP_PF2_REG_ATUF2_SHIFT 28 -+#define AR9_TCP_PF2_REG_ATUF2_SIZE 2 -+/* Bit: 'TUPF2' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 2' */ -+#define AR9_TCP_PF2_REG_TUPF2_OFFSET 0x0168 -+#define AR9_TCP_PF2_REG_TUPF2_SHIFT 26 -+#define AR9_TCP_PF2_REG_TUPF2_SIZE 2 -+/* Bit: 'COMP2' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF2_REG_COMP2_OFFSET 0x0168 -+#define AR9_TCP_PF2_REG_COMP2_SHIFT 24 -+#define AR9_TCP_PF2_REG_COMP2_SIZE 2 -+/* Bit: 'PRANGE2' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF2_REG_PRANGE2_OFFSET 0x0168 -+#define AR9_TCP_PF2_REG_PRANGE2_SHIFT 16 -+#define AR9_TCP_PF2_REG_PRANGE2_SIZE 8 -+/* Bit: 'BASEPT2' */ -+/* Description: 'Base Port number 2' */ -+#define AR9_TCP_PF2_REG_BASEPT2_OFFSET 0x0168 -+#define AR9_TCP_PF2_REG_BASEPT2_SHIFT 0 -+#define AR9_TCP_PF2_REG_BASEPT2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 3' */ -+/* Bit: 'ATUF3' */ -+/* Description: 'Action for TCP/UDP Port Filter 3' */ -+#define AR9_TCP_PF3_REG_ATUF3_OFFSET 0x016C -+#define AR9_TCP_PF3_REG_ATUF3_SHIFT 28 -+#define AR9_TCP_PF3_REG_ATUF3_SIZE 2 -+/* Bit: 'TUPF3' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 3' */ -+#define AR9_TCP_PF3_REG_TUPF3_OFFSET 0x016C -+#define AR9_TCP_PF3_REG_TUPF3_SHIFT 26 -+#define AR9_TCP_PF3_REG_TUPF3_SIZE 2 -+/* Bit: 'COMP3' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF3_REG_COMP3_OFFSET 0x016C -+#define AR9_TCP_PF3_REG_COMP3_SHIFT 24 -+#define AR9_TCP_PF3_REG_COMP3_SIZE 2 -+/* Bit: 'PRANGE3' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF3_REG_PRANGE3_OFFSET 0x016C -+#define AR9_TCP_PF3_REG_PRANGE3_SHIFT 16 -+#define AR9_TCP_PF3_REG_PRANGE3_SIZE 8 -+/* Bit: 'BASEPT3' */ -+/* Description: 'Base Port number 3' */ -+#define AR9_TCP_PF3_REG_BASEPT3_OFFSET 0x016C -+#define AR9_TCP_PF3_REG_BASEPT3_SHIFT 0 -+#define AR9_TCP_PF3_REG_BASEPT3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 4' */ -+/* Bit: 'ATUF4' */ -+/* Description: 'Action for TCP/UDP Port Filter 4' */ -+#define AR9_TCP_PF4_REG_ATUF4_OFFSET 0x0170 -+#define AR9_TCP_PF4_REG_ATUF4_SHIFT 28 -+#define AR9_TCP_PF4_REG_ATUF4_SIZE 2 -+/* Bit: 'TUPF4' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 4' */ -+#define AR9_TCP_PF4_REG_TUPF4_OFFSET 0x0170 -+#define AR9_TCP_PF4_REG_TUPF4_SHIFT 26 -+#define AR9_TCP_PF4_REG_TUPF4_SIZE 2 -+/* Bit: 'COMP4' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF4_REG_COMP4_OFFSET 0x0170 -+#define AR9_TCP_PF4_REG_COMP4_SHIFT 24 -+#define AR9_TCP_PF4_REG_COMP4_SIZE 2 -+/* Bit: 'PRANGE4' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF4_REG_PRANGE4_OFFSET 0x0170 -+#define AR9_TCP_PF4_REG_PRANGE4_SHIFT 16 -+#define AR9_TCP_PF4_REG_PRANGE4_SIZE 8 -+/* Bit: 'BASEPT4' */ -+/* Description: 'Base Port number 4' */ -+#define AR9_TCP_PF4_REG_BASEPT4_OFFSET 0x0170 -+#define AR9_TCP_PF4_REG_BASEPT4_SHIFT 0 -+#define AR9_TCP_PF4_REG_BASEPT4_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 5' */ -+/* Bit: 'ATUF5' */ -+/* Description: 'Action for TCP/UDP Port Filter 5' */ -+#define AR9_TCP_PF5_REG_ATUF5_OFFSET 0x0174 -+#define AR9_TCP_PF5_REG_ATUF5_SHIFT 28 -+#define AR9_TCP_PF5_REG_ATUF5_SIZE 2 -+/* Bit: 'TUPF5' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 5' */ -+#define AR9_TCP_PF5_REG_TUPF5_OFFSET 0x0174 -+#define AR9_TCP_PF5_REG_TUPF5_SHIFT 26 -+#define AR9_TCP_PF5_REG_TUPF5_SIZE 2 -+/* Bit: 'COMP5' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF5_REG_COMP5_OFFSET 0x0174 -+#define AR9_TCP_PF5_REG_COMP5_SHIFT 24 -+#define AR9_TCP_PF5_REG_COMP5_SIZE 2 -+/* Bit: 'PRANGE5' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF5_REG_PRANGE5_OFFSET 0x0174 -+#define AR9_TCP_PF5_REG_PRANGE5_SHIFT 16 -+#define AR9_TCP_PF5_REG_PRANGE5_SIZE 8 -+/* Bit: 'BASEPT5' */ -+/* Description: 'Base Port number 5' */ -+#define AR9_TCP_PF5_REG_BASEPT5_OFFSET 0x0174 -+#define AR9_TCP_PF5_REG_BASEPT5_SHIFT 0 -+#define AR9_TCP_PF5_REG_BASEPT5_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 6' */ -+/* Bit: 'ATUF6' */ -+/* Description: 'Action for TCP/UDP Port Filter 6' */ -+#define AR9_TCP_PF6_REG_ATUF6_OFFSET 0x0178 -+#define AR9_TCP_PF6_REG_ATUF6_SHIFT 28 -+#define AR9_TCP_PF6_REG_ATUF6_SIZE 2 -+/* Bit: 'TUPF6' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 6' */ -+#define AR9_TCP_PF6_REG_TUPF6_OFFSET 0x0178 -+#define AR9_TCP_PF6_REG_TUPF6_SHIFT 26 -+#define AR9_TCP_PF6_REG_TUPF6_SIZE 2 -+/* Bit: 'COMP6' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF6_REG_COMP6_OFFSET 0x0178 -+#define AR9_TCP_PF6_REG_COMP6_SHIFT 24 -+#define AR9_TCP_PF6_REG_COMP6_SIZE 2 -+/* Bit: 'PRANGE6' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF6_REG_PRANGE6_OFFSET 0x0178 -+#define AR9_TCP_PF6_REG_PRANGE6_SHIFT 16 -+#define AR9_TCP_PF6_REG_PRANGE6_SIZE 8 -+/* Bit: 'BASEPT6' */ -+/* Description: 'Base Port number 6' */ -+#define AR9_TCP_PF6_REG_BASEPT6_OFFSET 0x0178 -+#define AR9_TCP_PF6_REG_BASEPT6_SHIFT 0 -+#define AR9_TCP_PF6_REG_BASEPT6_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 7' */ -+/* Bit: 'ATUF7' */ -+/* Description: 'Action for TCP/UDP Port Filter 7' */ -+#define AR9_TCP_PF7_REG_ATUF7_OFFSET 0x017C -+#define AR9_TCP_PF7_REG_ATUF7_SHIFT 28 -+#define AR9_TCP_PF7_REG_ATUF7_SIZE 2 -+/* Bit: 'TUPF7' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 7' */ -+#define AR9_TCP_PF7_REG_TUPF7_OFFSET 0x017C -+#define AR9_TCP_PF7_REG_TUPF7_SHIFT 26 -+#define AR9_TCP_PF7_REG_TUPF7_SIZE 2 -+/* Bit: 'COMP7' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define AR9_TCP_PF7_REG_COMP7_OFFSET 0x017C -+#define AR9_TCP_PF7_REG_COMP7_SHIFT 24 -+#define AR9_TCP_PF7_REG_COMP7_SIZE 2 -+/* Bit: 'PRANGE7' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define AR9_TCP_PF7_REG_PRANGE7_OFFSET 0x017C -+#define AR9_TCP_PF7_REG_PRANGE7_SHIFT 16 -+#define AR9_TCP_PF7_REG_PRANGE7_SIZE 8 -+/* Bit: 'BASEPT7' */ -+/* Description: 'Base Port number 7' */ -+#define AR9_TCP_PF7_REG_BASEPT7_OFFSET 0x017C -+#define AR9_TCP_PF7_REG_BASEPT7_SHIFT 0 -+#define AR9_TCP_PF7_REG_BASEPT7_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserved DA(0180C2000003~0180C2000000) control register' */ -+/* Bit: 'RA03_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_VALID_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_VALID_SHIFT 31 -+#define AR9_RA_03_00_REG_RA03_VALID_SIZE 1 -+/* Bit: 'RA03_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_SPAN_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_SPAN_SHIFT 30 -+#define AR9_RA_03_00_REG_RA03_SPAN_SIZE 1 -+/* Bit: 'RA03_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_MG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_MG_SHIFT 29 -+#define AR9_RA_03_00_REG_RA03_MG_SIZE 1 -+/* Bit: 'RA03_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_CV_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_CV_SHIFT 28 -+#define AR9_RA_03_00_REG_RA03_CV_SIZE 1 -+/* Bit: 'RA03_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_TXTAG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_TXTAG_SHIFT 26 -+#define AR9_RA_03_00_REG_RA03_TXTAG_SIZE 2 -+/* Bit: 'RA03_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_03_00_REG_RA03_ACT_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA03_ACT_SHIFT 24 -+#define AR9_RA_03_00_REG_RA03_ACT_SIZE 2 -+/* Bit: 'RA02_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_VALID_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_VALID_SHIFT 23 -+#define AR9_RA_03_00_REG_RA02_VALID_SIZE 1 -+/* Bit: 'RA02_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_SPAN_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_SPAN_SHIFT 22 -+#define AR9_RA_03_00_REG_RA02_SPAN_SIZE 1 -+/* Bit: 'RA02_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_MG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_MG_SHIFT 21 -+#define AR9_RA_03_00_REG_RA02_MG_SIZE 1 -+/* Bit: 'RA02_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_CV_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_CV_SHIFT 20 -+#define AR9_RA_03_00_REG_RA02_CV_SIZE 1 -+/* Bit: 'RA02_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_TXTAG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_TXTAG_SHIFT 18 -+#define AR9_RA_03_00_REG_RA02_TXTAG_SIZE 2 -+/* Bit: 'RA02_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_03_00_REG_RA02_ACT_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA02_ACT_SHIFT 16 -+#define AR9_RA_03_00_REG_RA02_ACT_SIZE 2 -+/* Bit: 'RA01_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_VALID_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_VALID_SHIFT 15 -+#define AR9_RA_03_00_REG_RA01_VALID_SIZE 1 -+/* Bit: 'RA01_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_SPAN_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_SPAN_SHIFT 14 -+#define AR9_RA_03_00_REG_RA01_SPAN_SIZE 1 -+/* Bit: 'RA01_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_MG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_MG_SHIFT 13 -+#define AR9_RA_03_00_REG_RA01_MG_SIZE 1 -+/* Bit: 'RA01_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_CV_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_CV_SHIFT 12 -+#define AR9_RA_03_00_REG_RA01_CV_SIZE 1 -+/* Bit: 'RA01_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_TXTAG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_TXTAG_SHIFT 10 -+#define AR9_RA_03_00_REG_RA01_TXTAG_SIZE 2 -+/* Bit: 'RA01_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_03_00_REG_RA01_ACT_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA01_ACT_SHIFT 8 -+#define AR9_RA_03_00_REG_RA01_ACT_SIZE 2 -+/* Bit: 'RA00_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_VALID_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_VALID_SHIFT 7 -+#define AR9_RA_03_00_REG_RA00_VALID_SIZE 1 -+/* Bit: 'RA00_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_SPAN_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_SPAN_SHIFT 6 -+#define AR9_RA_03_00_REG_RA00_SPAN_SIZE 1 -+/* Bit: 'RA00_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_MG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_MG_SHIFT 5 -+#define AR9_RA_03_00_REG_RA00_MG_SIZE 1 -+/* Bit: 'RA00_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_CV_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_CV_SHIFT 4 -+#define AR9_RA_03_00_REG_RA00_CV_SIZE 1 -+/* Bit: 'RA00_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_TXTAG_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_TXTAG_SHIFT 2 -+#define AR9_RA_03_00_REG_RA00_TXTAG_SIZE 2 -+/* Bit: 'RA00_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_03_00_REG_RA00_ACT_OFFSET 0x0180 -+#define AR9_RA_03_00_REG_RA00_ACT_SHIFT 0 -+#define AR9_RA_03_00_REG_RA00_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000007~0180C2000004' */ -+/* Bit: 'RA13_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_VALID_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_VALID_SHIFT 31 -+#define AR9_RA_07_04_REG_RA13_VALID_SIZE 1 -+/* Bit: 'RA13_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_SPAN_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_SPAN_SHIFT 30 -+#define AR9_RA_07_04_REG_RA13_SPAN_SIZE 1 -+/* Bit: 'RA13_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_MG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_MG_SHIFT 29 -+#define AR9_RA_07_04_REG_RA13_MG_SIZE 1 -+/* Bit: 'RA13_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_CV_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_CV_SHIFT 28 -+#define AR9_RA_07_04_REG_RA13_CV_SIZE 1 -+/* Bit: 'RA13_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_TXTAG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_TXTAG_SHIFT 26 -+#define AR9_RA_07_04_REG_RA13_TXTAG_SIZE 2 -+/* Bit: 'RA13_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_07_04_REG_RA13_ACT_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA13_ACT_SHIFT 24 -+#define AR9_RA_07_04_REG_RA13_ACT_SIZE 2 -+/* Bit: 'RA12_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_VALID_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_VALID_SHIFT 23 -+#define AR9_RA_07_04_REG_RA12_VALID_SIZE 1 -+/* Bit: 'RA12_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_SPAN_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_SPAN_SHIFT 22 -+#define AR9_RA_07_04_REG_RA12_SPAN_SIZE 1 -+/* Bit: 'RA12_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_MG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_MG_SHIFT 21 -+#define AR9_RA_07_04_REG_RA12_MG_SIZE 1 -+/* Bit: 'RA12_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_CV_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_CV_SHIFT 20 -+#define AR9_RA_07_04_REG_RA12_CV_SIZE 1 -+/* Bit: 'RA12_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_TXTAG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_TXTAG_SHIFT 18 -+#define AR9_RA_07_04_REG_RA12_TXTAG_SIZE 2 -+/* Bit: 'RA12_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_07_04_REG_RA12_ACT_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA12_ACT_SHIFT 16 -+#define AR9_RA_07_04_REG_RA12_ACT_SIZE 2 -+/* Bit: 'RA11_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_VALID_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_VALID_SHIFT 15 -+#define AR9_RA_07_04_REG_RA11_VALID_SIZE 1 -+/* Bit: 'RA11_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_SPAN_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_SPAN_SHIFT 14 -+#define AR9_RA_07_04_REG_RA11_SPAN_SIZE 1 -+/* Bit: 'RA11_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_MG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_MG_SHIFT 13 -+#define AR9_RA_07_04_REG_RA11_MG_SIZE 1 -+/* Bit: 'RA11_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_CV_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_CV_SHIFT 12 -+#define AR9_RA_07_04_REG_RA11_CV_SIZE 1 -+/* Bit: 'RA11_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_TXTAG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_TXTAG_SHIFT 10 -+#define AR9_RA_07_04_REG_RA11_TXTAG_SIZE 2 -+/* Bit: 'RA11_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_07_04_REG_RA11_ACT_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA11_ACT_SHIFT 8 -+#define AR9_RA_07_04_REG_RA11_ACT_SIZE 2 -+/* Bit: 'RA10_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_VALID_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_VALID_SHIFT 7 -+#define AR9_RA_07_04_REG_RA10_VALID_SIZE 1 -+/* Bit: 'RA10_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_SPAN_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_SPAN_SHIFT 6 -+#define AR9_RA_07_04_REG_RA10_SPAN_SIZE 1 -+/* Bit: 'RA10_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_MG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_MG_SHIFT 5 -+#define AR9_RA_07_04_REG_RA10_MG_SIZE 1 -+/* Bit: 'RA10_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_CV_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_CV_SHIFT 4 -+#define AR9_RA_07_04_REG_RA10_CV_SIZE 1 -+/* Bit: 'RA10_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_TXTAG_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_TXTAG_SHIFT 2 -+#define AR9_RA_07_04_REG_RA10_TXTAG_SIZE 2 -+/* Bit: 'RA10_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_07_04_REG_RA10_ACT_OFFSET 0x0184 -+#define AR9_RA_07_04_REG_RA10_ACT_SHIFT 0 -+#define AR9_RA_07_04_REG_RA10_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200000B~0180C2000008' */ -+/* Bit: 'RA23_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_VALID_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_VALID_SHIFT 31 -+#define AR9_RA_0B_08_REG_RA23_VALID_SIZE 1 -+/* Bit: 'RA23_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_SPAN_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_SPAN_SHIFT 30 -+#define AR9_RA_0B_08_REG_RA23_SPAN_SIZE 1 -+/* Bit: 'RA23_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_MG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_MG_SHIFT 29 -+#define AR9_RA_0B_08_REG_RA23_MG_SIZE 1 -+/* Bit: 'RA23_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_CV_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_CV_SHIFT 28 -+#define AR9_RA_0B_08_REG_RA23_CV_SIZE 1 -+/* Bit: 'RA23_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_TXTAG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_TXTAG_SHIFT 26 -+#define AR9_RA_0B_08_REG_RA23_TXTAG_SIZE 2 -+/* Bit: 'RA23_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_0B_08_REG_RA23_ACT_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA23_ACT_SHIFT 24 -+#define AR9_RA_0B_08_REG_RA23_ACT_SIZE 2 -+/* Bit: 'RA22_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_VALID_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_VALID_SHIFT 23 -+#define AR9_RA_0B_08_REG_RA22_VALID_SIZE 1 -+/* Bit: 'RA22_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_SPAN_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_SPAN_SHIFT 22 -+#define AR9_RA_0B_08_REG_RA22_SPAN_SIZE 1 -+/* Bit: 'RA22_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_MG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_MG_SHIFT 21 -+#define AR9_RA_0B_08_REG_RA22_MG_SIZE 1 -+/* Bit: 'RA22_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_CV_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_CV_SHIFT 20 -+#define AR9_RA_0B_08_REG_RA22_CV_SIZE 1 -+/* Bit: 'RA22_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_TXTAG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_TXTAG_SHIFT 18 -+#define AR9_RA_0B_08_REG_RA22_TXTAG_SIZE 2 -+/* Bit: 'RA22_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_0B_08_REG_RA22_ACT_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA22_ACT_SHIFT 16 -+#define AR9_RA_0B_08_REG_RA22_ACT_SIZE 2 -+/* Bit: 'RA21_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_VALID_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_VALID_SHIFT 15 -+#define AR9_RA_0B_08_REG_RA21_VALID_SIZE 1 -+/* Bit: 'RA21_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_SPAN_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_SPAN_SHIFT 14 -+#define AR9_RA_0B_08_REG_RA21_SPAN_SIZE 1 -+/* Bit: 'RA21_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_MG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_MG_SHIFT 13 -+#define AR9_RA_0B_08_REG_RA21_MG_SIZE 1 -+/* Bit: 'RA21_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_CV_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_CV_SHIFT 12 -+#define AR9_RA_0B_08_REG_RA21_CV_SIZE 1 -+/* Bit: 'RA21_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_TXTAG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_TXTAG_SHIFT 10 -+#define AR9_RA_0B_08_REG_RA21_TXTAG_SIZE 2 -+/* Bit: 'RA21_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_0B_08_REG_RA21_ACT_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA21_ACT_SHIFT 8 -+#define AR9_RA_0B_08_REG_RA21_ACT_SIZE 2 -+/* Bit: 'RA20_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_VALID_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_VALID_SHIFT 7 -+#define AR9_RA_0B_08_REG_RA20_VALID_SIZE 1 -+/* Bit: 'RA20_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_SPAN_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_SPAN_SHIFT 6 -+#define AR9_RA_0B_08_REG_RA20_SPAN_SIZE 1 -+/* Bit: 'RA20_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_MG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_MG_SHIFT 5 -+#define AR9_RA_0B_08_REG_RA20_MG_SIZE 1 -+/* Bit: 'RA20_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_CV_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_CV_SHIFT 4 -+#define AR9_RA_0B_08_REG_RA20_CV_SIZE 1 -+/* Bit: 'RA20_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_TXTAG_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_TXTAG_SHIFT 2 -+#define AR9_RA_0B_08_REG_RA20_TXTAG_SIZE 2 -+/* Bit: 'RA20_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_0B_08_REG_RA20_ACT_OFFSET 0x0188 -+#define AR9_RA_0B_08_REG_RA20_ACT_SHIFT 0 -+#define AR9_RA_0B_08_REG_RA20_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200000F~0180C200000C' */ -+/* Bit: 'RA33_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_VALID_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_VALID_SHIFT 31 -+#define AR9_RA_0F_0C_REG_RA33_VALID_SIZE 1 -+/* Bit: 'RA33_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_SPAN_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_SPAN_SHIFT 30 -+#define AR9_RA_0F_0C_REG_RA33_SPAN_SIZE 1 -+/* Bit: 'RA33_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_MG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_MG_SHIFT 29 -+#define AR9_RA_0F_0C_REG_RA33_MG_SIZE 1 -+/* Bit: 'RA33_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_CV_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_CV_SHIFT 28 -+#define AR9_RA_0F_0C_REG_RA33_CV_SIZE 1 -+/* Bit: 'RA33_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_TXTAG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_TXTAG_SHIFT 26 -+#define AR9_RA_0F_0C_REG_RA33_TXTAG_SIZE 2 -+/* Bit: 'RA33_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_0F_0C_REG_RA33_ACT_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA33_ACT_SHIFT 24 -+#define AR9_RA_0F_0C_REG_RA33_ACT_SIZE 2 -+/* Bit: 'RA32_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_VALID_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_VALID_SHIFT 23 -+#define AR9_RA_0F_0C_REG_RA32_VALID_SIZE 1 -+/* Bit: 'RA32_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_SPAN_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_SPAN_SHIFT 22 -+#define AR9_RA_0F_0C_REG_RA32_SPAN_SIZE 1 -+/* Bit: 'RA32_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_MG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_MG_SHIFT 21 -+#define AR9_RA_0F_0C_REG_RA32_MG_SIZE 1 -+/* Bit: 'RA32_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_CV_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_CV_SHIFT 20 -+#define AR9_RA_0F_0C_REG_RA32_CV_SIZE 1 -+/* Bit: 'RA32_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_TXTAG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_TXTAG_SHIFT 18 -+#define AR9_RA_0F_0C_REG_RA32_TXTAG_SIZE 2 -+/* Bit: 'RA32_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_0F_0C_REG_RA32_ACT_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA32_ACT_SHIFT 16 -+#define AR9_RA_0F_0C_REG_RA32_ACT_SIZE 2 -+/* Bit: 'RA31_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_VALID_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_VALID_SHIFT 15 -+#define AR9_RA_0F_0C_REG_RA31_VALID_SIZE 1 -+/* Bit: 'RA31_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_SPAN_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_SPAN_SHIFT 14 -+#define AR9_RA_0F_0C_REG_RA31_SPAN_SIZE 1 -+/* Bit: 'RA31_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_MG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_MG_SHIFT 13 -+#define AR9_RA_0F_0C_REG_RA31_MG_SIZE 1 -+/* Bit: 'RA31_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_CV_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_CV_SHIFT 12 -+#define AR9_RA_0F_0C_REG_RA31_CV_SIZE 1 -+/* Bit: 'RA31_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_TXTAG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_TXTAG_SHIFT 10 -+#define AR9_RA_0F_0C_REG_RA31_TXTAG_SIZE 2 -+/* Bit: 'RA31_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_0F_0C_REG_RA31_ACT_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA31_ACT_SHIFT 8 -+#define AR9_RA_0F_0C_REG_RA31_ACT_SIZE 2 -+/* Bit: 'RA30_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_VALID_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_VALID_SHIFT 7 -+#define AR9_RA_0F_0C_REG_RA30_VALID_SIZE 1 -+/* Bit: 'RA30_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_SPAN_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_SPAN_SHIFT 6 -+#define AR9_RA_0F_0C_REG_RA30_SPAN_SIZE 1 -+/* Bit: 'RA30_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_MG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_MG_SHIFT 5 -+#define AR9_RA_0F_0C_REG_RA30_MG_SIZE 1 -+/* Bit: 'RA30_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_CV_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_CV_SHIFT 4 -+#define AR9_RA_0F_0C_REG_RA30_CV_SIZE 1 -+/* Bit: 'RA30_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_TXTAG_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_TXTAG_SHIFT 2 -+#define AR9_RA_0F_0C_REG_RA30_TXTAG_SIZE 2 -+/* Bit: 'RA30_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_0F_0C_REG_RA30_ACT_OFFSET 0x018C -+#define AR9_RA_0F_0C_REG_RA30_ACT_SHIFT 0 -+#define AR9_RA_0F_0C_REG_RA30_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000013~0180C2000010' */ -+/* Bit: 'RA43_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_VALID_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_VALID_SHIFT 31 -+#define AR9_RA_13_10_REG_RA43_VALID_SIZE 1 -+/* Bit: 'RA43_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_SPAN_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_SPAN_SHIFT 30 -+#define AR9_RA_13_10_REG_RA43_SPAN_SIZE 1 -+/* Bit: 'RA43_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_MG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_MG_SHIFT 29 -+#define AR9_RA_13_10_REG_RA43_MG_SIZE 1 -+/* Bit: 'RA43_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_CV_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_CV_SHIFT 28 -+#define AR9_RA_13_10_REG_RA43_CV_SIZE 1 -+/* Bit: 'RA43_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_TXTAG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_TXTAG_SHIFT 26 -+#define AR9_RA_13_10_REG_RA43_TXTAG_SIZE 2 -+/* Bit: 'RA43_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_13_10_REG_RA43_ACT_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA43_ACT_SHIFT 24 -+#define AR9_RA_13_10_REG_RA43_ACT_SIZE 2 -+/* Bit: 'RA42_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_VALID_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_VALID_SHIFT 23 -+#define AR9_RA_13_10_REG_RA42_VALID_SIZE 1 -+/* Bit: 'RA42_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_SPAN_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_SPAN_SHIFT 22 -+#define AR9_RA_13_10_REG_RA42_SPAN_SIZE 1 -+/* Bit: 'RA42_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_MG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_MG_SHIFT 21 -+#define AR9_RA_13_10_REG_RA42_MG_SIZE 1 -+/* Bit: 'RA42_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_CV_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_CV_SHIFT 20 -+#define AR9_RA_13_10_REG_RA42_CV_SIZE 1 -+/* Bit: 'RA42_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_TXTAG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_TXTAG_SHIFT 18 -+#define AR9_RA_13_10_REG_RA42_TXTAG_SIZE 2 -+/* Bit: 'RA42_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_13_10_REG_RA42_ACT_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA42_ACT_SHIFT 16 -+#define AR9_RA_13_10_REG_RA42_ACT_SIZE 2 -+/* Bit: 'RA41_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_VALID_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_VALID_SHIFT 15 -+#define AR9_RA_13_10_REG_RA41_VALID_SIZE 1 -+/* Bit: 'RA41_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_SPAN_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_SPAN_SHIFT 14 -+#define AR9_RA_13_10_REG_RA41_SPAN_SIZE 1 -+/* Bit: 'RA41_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_MG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_MG_SHIFT 13 -+#define AR9_RA_13_10_REG_RA41_MG_SIZE 1 -+/* Bit: 'RA41_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_CV_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_CV_SHIFT 12 -+#define AR9_RA_13_10_REG_RA41_CV_SIZE 1 -+/* Bit: 'RA41_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_TXTAG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_TXTAG_SHIFT 10 -+#define AR9_RA_13_10_REG_RA41_TXTAG_SIZE 2 -+/* Bit: 'RA41_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_13_10_REG_RA41_ACT_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA41_ACT_SHIFT 8 -+#define AR9_RA_13_10_REG_RA41_ACT_SIZE 2 -+/* Bit: 'RA40_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_VALID_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_VALID_SHIFT 7 -+#define AR9_RA_13_10_REG_RA40_VALID_SIZE 1 -+/* Bit: 'RA40_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_SPAN_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_SPAN_SHIFT 6 -+#define AR9_RA_13_10_REG_RA40_SPAN_SIZE 1 -+/* Bit: 'RA40_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_MG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_MG_SHIFT 5 -+#define AR9_RA_13_10_REG_RA40_MG_SIZE 1 -+/* Bit: 'RA40_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_CV_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_CV_SHIFT 4 -+#define AR9_RA_13_10_REG_RA40_CV_SIZE 1 -+/* Bit: 'RA40_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_TXTAG_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_TXTAG_SHIFT 2 -+#define AR9_RA_13_10_REG_RA40_TXTAG_SIZE 2 -+/* Bit: 'RA40_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_13_10_REG_RA40_ACT_OFFSET 0x0190 -+#define AR9_RA_13_10_REG_RA40_ACT_SHIFT 0 -+#define AR9_RA_13_10_REG_RA40_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000017~0180C2000014' */ -+/* Bit: 'RA53_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_VALID_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_VALID_SHIFT 31 -+#define AR9_RA_17_14_REG_RA53_VALID_SIZE 1 -+/* Bit: 'RA53_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_SPAN_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_SPAN_SHIFT 30 -+#define AR9_RA_17_14_REG_RA53_SPAN_SIZE 1 -+/* Bit: 'RA53_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_MG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_MG_SHIFT 29 -+#define AR9_RA_17_14_REG_RA53_MG_SIZE 1 -+/* Bit: 'RA53_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_CV_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_CV_SHIFT 28 -+#define AR9_RA_17_14_REG_RA53_CV_SIZE 1 -+/* Bit: 'RA53_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_TXTAG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_TXTAG_SHIFT 26 -+#define AR9_RA_17_14_REG_RA53_TXTAG_SIZE 2 -+/* Bit: 'RA53_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_17_14_REG_RA53_ACT_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA53_ACT_SHIFT 24 -+#define AR9_RA_17_14_REG_RA53_ACT_SIZE 2 -+/* Bit: 'RA52_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_VALID_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_VALID_SHIFT 23 -+#define AR9_RA_17_14_REG_RA52_VALID_SIZE 1 -+/* Bit: 'RA52_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_SPAN_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_SPAN_SHIFT 22 -+#define AR9_RA_17_14_REG_RA52_SPAN_SIZE 1 -+/* Bit: 'RA52_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_MG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_MG_SHIFT 21 -+#define AR9_RA_17_14_REG_RA52_MG_SIZE 1 -+/* Bit: 'RA52_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_CV_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_CV_SHIFT 20 -+#define AR9_RA_17_14_REG_RA52_CV_SIZE 1 -+/* Bit: 'RA52_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_TXTAG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_TXTAG_SHIFT 18 -+#define AR9_RA_17_14_REG_RA52_TXTAG_SIZE 2 -+/* Bit: 'RA52_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_17_14_REG_RA52_ACT_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA52_ACT_SHIFT 16 -+#define AR9_RA_17_14_REG_RA52_ACT_SIZE 2 -+/* Bit: 'RA51_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_VALID_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_VALID_SHIFT 15 -+#define AR9_RA_17_14_REG_RA51_VALID_SIZE 1 -+/* Bit: 'RA51_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_SPAN_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_SPAN_SHIFT 14 -+#define AR9_RA_17_14_REG_RA51_SPAN_SIZE 1 -+/* Bit: 'RA51_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_MG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_MG_SHIFT 13 -+#define AR9_RA_17_14_REG_RA51_MG_SIZE 1 -+/* Bit: 'RA51_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_CV_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_CV_SHIFT 12 -+#define AR9_RA_17_14_REG_RA51_CV_SIZE 1 -+/* Bit: 'RA51_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_TXTAG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_TXTAG_SHIFT 10 -+#define AR9_RA_17_14_REG_RA51_TXTAG_SIZE 2 -+/* Bit: 'RA51_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_17_14_REG_RA51_ACT_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA51_ACT_SHIFT 8 -+#define AR9_RA_17_14_REG_RA51_ACT_SIZE 2 -+/* Bit: 'RA50_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_VALID_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_VALID_SHIFT 7 -+#define AR9_RA_17_14_REG_RA50_VALID_SIZE 1 -+/* Bit: 'RA50_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_SPAN_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_SPAN_SHIFT 6 -+#define AR9_RA_17_14_REG_RA50_SPAN_SIZE 1 -+/* Bit: 'RA50_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_MG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_MG_SHIFT 5 -+#define AR9_RA_17_14_REG_RA50_MG_SIZE 1 -+/* Bit: 'RA50_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_CV_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_CV_SHIFT 4 -+#define AR9_RA_17_14_REG_RA50_CV_SIZE 1 -+/* Bit: 'RA50_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_TXTAG_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_TXTAG_SHIFT 2 -+#define AR9_RA_17_14_REG_RA50_TXTAG_SIZE 2 -+/* Bit: 'RA50_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_17_14_REG_RA50_ACT_OFFSET 0x0194 -+#define AR9_RA_17_14_REG_RA50_ACT_SHIFT 0 -+#define AR9_RA_17_14_REG_RA50_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200001B~0180C2000018' */ -+/* Bit: 'RA63_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_VALID_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_VALID_SHIFT 31 -+#define AR9_RA_1B_18_REG_RA63_VALID_SIZE 1 -+/* Bit: 'RA63_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_SPAN_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_SPAN_SHIFT 30 -+#define AR9_RA_1B_18_REG_RA63_SPAN_SIZE 1 -+/* Bit: 'RA63_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_MG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_MG_SHIFT 29 -+#define AR9_RA_1B_18_REG_RA63_MG_SIZE 1 -+/* Bit: 'RA63_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_CV_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_CV_SHIFT 28 -+#define AR9_RA_1B_18_REG_RA63_CV_SIZE 1 -+/* Bit: 'RA63_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_TXTAG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_TXTAG_SHIFT 26 -+#define AR9_RA_1B_18_REG_RA63_TXTAG_SIZE 2 -+/* Bit: 'RA63_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_1B_18_REG_RA63_ACT_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA63_ACT_SHIFT 24 -+#define AR9_RA_1B_18_REG_RA63_ACT_SIZE 2 -+/* Bit: 'RA62_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_VALID_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_VALID_SHIFT 23 -+#define AR9_RA_1B_18_REG_RA62_VALID_SIZE 1 -+/* Bit: 'RA62_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_SPAN_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_SPAN_SHIFT 22 -+#define AR9_RA_1B_18_REG_RA62_SPAN_SIZE 1 -+/* Bit: 'RA62_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_MG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_MG_SHIFT 21 -+#define AR9_RA_1B_18_REG_RA62_MG_SIZE 1 -+/* Bit: 'RA62_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_CV_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_CV_SHIFT 20 -+#define AR9_RA_1B_18_REG_RA62_CV_SIZE 1 -+/* Bit: 'RA62_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_TXTAG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_TXTAG_SHIFT 18 -+#define AR9_RA_1B_18_REG_RA62_TXTAG_SIZE 2 -+/* Bit: 'RA62_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_1B_18_REG_RA62_ACT_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA62_ACT_SHIFT 16 -+#define AR9_RA_1B_18_REG_RA62_ACT_SIZE 2 -+/* Bit: 'RA61_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_VALID_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_VALID_SHIFT 15 -+#define AR9_RA_1B_18_REG_RA61_VALID_SIZE 1 -+/* Bit: 'RA61_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_SPAN_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_SPAN_SHIFT 14 -+#define AR9_RA_1B_18_REG_RA61_SPAN_SIZE 1 -+/* Bit: 'RA61_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_MG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_MG_SHIFT 13 -+#define AR9_RA_1B_18_REG_RA61_MG_SIZE 1 -+/* Bit: 'RA61_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_CV_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_CV_SHIFT 12 -+#define AR9_RA_1B_18_REG_RA61_CV_SIZE 1 -+/* Bit: 'RA61_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_TXTAG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_TXTAG_SHIFT 10 -+#define AR9_RA_1B_18_REG_RA61_TXTAG_SIZE 2 -+/* Bit: 'RA61_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_1B_18_REG_RA61_ACT_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA61_ACT_SHIFT 8 -+#define AR9_RA_1B_18_REG_RA61_ACT_SIZE 2 -+/* Bit: 'RA60_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_VALID_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_VALID_SHIFT 7 -+#define AR9_RA_1B_18_REG_RA60_VALID_SIZE 1 -+/* Bit: 'RA60_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_SPAN_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_SPAN_SHIFT 6 -+#define AR9_RA_1B_18_REG_RA60_SPAN_SIZE 1 -+/* Bit: 'RA60_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_MG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_MG_SHIFT 5 -+#define AR9_RA_1B_18_REG_RA60_MG_SIZE 1 -+/* Bit: 'RA60_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_CV_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_CV_SHIFT 4 -+#define AR9_RA_1B_18_REG_RA60_CV_SIZE 1 -+/* Bit: 'RA60_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_TXTAG_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_TXTAG_SHIFT 2 -+#define AR9_RA_1B_18_REG_RA60_TXTAG_SIZE 2 -+/* Bit: 'RA60_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_1B_18_REG_RA60_ACT_OFFSET 0x0198 -+#define AR9_RA_1B_18_REG_RA60_ACT_SHIFT 0 -+#define AR9_RA_1B_18_REG_RA60_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200001F~0180C200001C' */ -+/* Bit: 'RA73_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_VALID_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_VALID_SHIFT 31 -+#define AR9_RA_1F_1C_REG_RA73_VALID_SIZE 1 -+/* Bit: 'RA73_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_SPAN_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_SPAN_SHIFT 30 -+#define AR9_RA_1F_1C_REG_RA73_SPAN_SIZE 1 -+/* Bit: 'RA73_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_MG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_MG_SHIFT 29 -+#define AR9_RA_1F_1C_REG_RA73_MG_SIZE 1 -+/* Bit: 'RA73_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_CV_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_CV_SHIFT 28 -+#define AR9_RA_1F_1C_REG_RA73_CV_SIZE 1 -+/* Bit: 'RA73_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_TXTAG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_TXTAG_SHIFT 26 -+#define AR9_RA_1F_1C_REG_RA73_TXTAG_SIZE 2 -+/* Bit: 'RA73_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_1F_1C_REG_RA73_ACT_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA73_ACT_SHIFT 24 -+#define AR9_RA_1F_1C_REG_RA73_ACT_SIZE 2 -+/* Bit: 'RA72_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_VALID_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_VALID_SHIFT 23 -+#define AR9_RA_1F_1C_REG_RA72_VALID_SIZE 1 -+/* Bit: 'RA72_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_SPAN_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_SPAN_SHIFT 22 -+#define AR9_RA_1F_1C_REG_RA72_SPAN_SIZE 1 -+/* Bit: 'RA72_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_MG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_MG_SHIFT 21 -+#define AR9_RA_1F_1C_REG_RA72_MG_SIZE 1 -+/* Bit: 'RA72_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_CV_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_CV_SHIFT 20 -+#define AR9_RA_1F_1C_REG_RA72_CV_SIZE 1 -+/* Bit: 'RA72_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_TXTAG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_TXTAG_SHIFT 18 -+#define AR9_RA_1F_1C_REG_RA72_TXTAG_SIZE 2 -+/* Bit: 'RA72_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_1F_1C_REG_RA72_ACT_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA72_ACT_SHIFT 16 -+#define AR9_RA_1F_1C_REG_RA72_ACT_SIZE 2 -+/* Bit: 'RA71_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_VALID_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_VALID_SHIFT 15 -+#define AR9_RA_1F_1C_REG_RA71_VALID_SIZE 1 -+/* Bit: 'RA71_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_SPAN_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_SPAN_SHIFT 14 -+#define AR9_RA_1F_1C_REG_RA71_SPAN_SIZE 1 -+/* Bit: 'RA71_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_MG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_MG_SHIFT 13 -+#define AR9_RA_1F_1C_REG_RA71_MG_SIZE 1 -+/* Bit: 'RA71_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_CV_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_CV_SHIFT 12 -+#define AR9_RA_1F_1C_REG_RA71_CV_SIZE 1 -+/* Bit: 'RA71_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_TXTAG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_TXTAG_SHIFT 10 -+#define AR9_RA_1F_1C_REG_RA71_TXTAG_SIZE 2 -+/* Bit: 'RA71_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_1F_1C_REG_RA71_ACT_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA71_ACT_SHIFT 8 -+#define AR9_RA_1F_1C_REG_RA71_ACT_SIZE 2 -+/* Bit: 'RA70_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_VALID_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_VALID_SHIFT 7 -+#define AR9_RA_1F_1C_REG_RA70_VALID_SIZE 1 -+/* Bit: 'RA70_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_SPAN_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_SPAN_SHIFT 6 -+#define AR9_RA_1F_1C_REG_RA70_SPAN_SIZE 1 -+/* Bit: 'RA70_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_MG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_MG_SHIFT 5 -+#define AR9_RA_1F_1C_REG_RA70_MG_SIZE 1 -+/* Bit: 'RA70_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_CV_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_CV_SHIFT 4 -+#define AR9_RA_1F_1C_REG_RA70_CV_SIZE 1 -+/* Bit: 'RA70_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_TXTAG_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_TXTAG_SHIFT 2 -+#define AR9_RA_1F_1C_REG_RA70_TXTAG_SIZE 2 -+/* Bit: 'RA70_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_1F_1C_REG_RA70_ACT_OFFSET 0x019C -+#define AR9_RA_1F_1C_REG_RA70_ACT_SHIFT 0 -+#define AR9_RA_1F_1C_REG_RA70_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000023~0180C2000020' */ -+/* Bit: 'RA83_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_VALID_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_VALID_SHIFT 31 -+#define AR9_RA_23_20_REG_RA83_VALID_SIZE 1 -+/* Bit: 'RA83_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_SPAN_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_SPAN_SHIFT 30 -+#define AR9_RA_23_20_REG_RA83_SPAN_SIZE 1 -+/* Bit: 'RA83_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_MG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_MG_SHIFT 29 -+#define AR9_RA_23_20_REG_RA83_MG_SIZE 1 -+/* Bit: 'RA83_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_CV_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_CV_SHIFT 28 -+#define AR9_RA_23_20_REG_RA83_CV_SIZE 1 -+/* Bit: 'RA83_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_TXTAG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_TXTAG_SHIFT 26 -+#define AR9_RA_23_20_REG_RA83_TXTAG_SIZE 2 -+/* Bit: 'RA83_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_23_20_REG_RA83_ACT_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA83_ACT_SHIFT 24 -+#define AR9_RA_23_20_REG_RA83_ACT_SIZE 2 -+/* Bit: 'RA82_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_VALID_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_VALID_SHIFT 23 -+#define AR9_RA_23_20_REG_RA82_VALID_SIZE 1 -+/* Bit: 'RA82_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_SPAN_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_SPAN_SHIFT 22 -+#define AR9_RA_23_20_REG_RA82_SPAN_SIZE 1 -+/* Bit: 'RA82_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_MG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_MG_SHIFT 21 -+#define AR9_RA_23_20_REG_RA82_MG_SIZE 1 -+/* Bit: 'RA82_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_CV_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_CV_SHIFT 20 -+#define AR9_RA_23_20_REG_RA82_CV_SIZE 1 -+/* Bit: 'RA82_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_TXTAG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_TXTAG_SHIFT 18 -+#define AR9_RA_23_20_REG_RA82_TXTAG_SIZE 2 -+/* Bit: 'RA82_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_23_20_REG_RA82_ACT_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA82_ACT_SHIFT 16 -+#define AR9_RA_23_20_REG_RA82_ACT_SIZE 2 -+/* Bit: 'RA81_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_VALID_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_VALID_SHIFT 15 -+#define AR9_RA_23_20_REG_RA81_VALID_SIZE 1 -+/* Bit: 'RA81_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_SPAN_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_SPAN_SHIFT 14 -+#define AR9_RA_23_20_REG_RA81_SPAN_SIZE 1 -+/* Bit: 'RA81_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_MG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_MG_SHIFT 13 -+#define AR9_RA_23_20_REG_RA81_MG_SIZE 1 -+/* Bit: 'RA81_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_CV_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_CV_SHIFT 12 -+#define AR9_RA_23_20_REG_RA81_CV_SIZE 1 -+/* Bit: 'RA81_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_TXTAG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_TXTAG_SHIFT 10 -+#define AR9_RA_23_20_REG_RA81_TXTAG_SIZE 2 -+/* Bit: 'RA81_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_23_20_REG_RA81_ACT_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA81_ACT_SHIFT 8 -+#define AR9_RA_23_20_REG_RA81_ACT_SIZE 2 -+/* Bit: 'RA80_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_VALID_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_VALID_SHIFT 7 -+#define AR9_RA_23_20_REG_RA80_VALID_SIZE 1 -+/* Bit: 'RA80_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_SPAN_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_SPAN_SHIFT 6 -+#define AR9_RA_23_20_REG_RA80_SPAN_SIZE 1 -+/* Bit: 'RA80_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_MG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_MG_SHIFT 5 -+#define AR9_RA_23_20_REG_RA80_MG_SIZE 1 -+/* Bit: 'RA80_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_CV_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_CV_SHIFT 4 -+#define AR9_RA_23_20_REG_RA80_CV_SIZE 1 -+/* Bit: 'RA80_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_TXTAG_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_TXTAG_SHIFT 2 -+#define AR9_RA_23_20_REG_RA80_TXTAG_SIZE 2 -+/* Bit: 'RA80_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_23_20_REG_RA80_ACT_OFFSET 0x01A0 -+#define AR9_RA_23_20_REG_RA80_ACT_SHIFT 0 -+#define AR9_RA_23_20_REG_RA80_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000027~0180C2000024' */ -+/* Bit: 'RA93_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_VALID_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_VALID_SHIFT 31 -+#define AR9_RA_27_24_REG_RA93_VALID_SIZE 1 -+/* Bit: 'RA93_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_SPAN_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_SPAN_SHIFT 30 -+#define AR9_RA_27_24_REG_RA93_SPAN_SIZE 1 -+/* Bit: 'RA93_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_MG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_MG_SHIFT 29 -+#define AR9_RA_27_24_REG_RA93_MG_SIZE 1 -+/* Bit: 'RA93_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_CV_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_CV_SHIFT 28 -+#define AR9_RA_27_24_REG_RA93_CV_SIZE 1 -+/* Bit: 'RA93_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_TXTAG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_TXTAG_SHIFT 26 -+#define AR9_RA_27_24_REG_RA93_TXTAG_SIZE 2 -+/* Bit: 'RA93_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_27_24_REG_RA93_ACT_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA93_ACT_SHIFT 24 -+#define AR9_RA_27_24_REG_RA93_ACT_SIZE 2 -+/* Bit: 'RA92_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_VALID_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_VALID_SHIFT 23 -+#define AR9_RA_27_24_REG_RA92_VALID_SIZE 1 -+/* Bit: 'RA92_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_SPAN_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_SPAN_SHIFT 22 -+#define AR9_RA_27_24_REG_RA92_SPAN_SIZE 1 -+/* Bit: 'RA92_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_MG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_MG_SHIFT 21 -+#define AR9_RA_27_24_REG_RA92_MG_SIZE 1 -+/* Bit: 'RA92_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_CV_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_CV_SHIFT 20 -+#define AR9_RA_27_24_REG_RA92_CV_SIZE 1 -+/* Bit: 'RA92_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_TXTAG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_TXTAG_SHIFT 18 -+#define AR9_RA_27_24_REG_RA92_TXTAG_SIZE 2 -+/* Bit: 'RA92_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_27_24_REG_RA92_ACT_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA92_ACT_SHIFT 16 -+#define AR9_RA_27_24_REG_RA92_ACT_SIZE 2 -+/* Bit: 'RA91_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_VALID_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_VALID_SHIFT 15 -+#define AR9_RA_27_24_REG_RA91_VALID_SIZE 1 -+/* Bit: 'RA91_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_SPAN_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_SPAN_SHIFT 14 -+#define AR9_RA_27_24_REG_RA91_SPAN_SIZE 1 -+/* Bit: 'RA91_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_MG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_MG_SHIFT 13 -+#define AR9_RA_27_24_REG_RA91_MG_SIZE 1 -+/* Bit: 'RA91_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_CV_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_CV_SHIFT 12 -+#define AR9_RA_27_24_REG_RA91_CV_SIZE 1 -+/* Bit: 'RA91_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_TXTAG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_TXTAG_SHIFT 10 -+#define AR9_RA_27_24_REG_RA91_TXTAG_SIZE 2 -+/* Bit: 'RA91_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_27_24_REG_RA91_ACT_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA91_ACT_SHIFT 8 -+#define AR9_RA_27_24_REG_RA91_ACT_SIZE 2 -+/* Bit: 'RA90_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_VALID_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_VALID_SHIFT 7 -+#define AR9_RA_27_24_REG_RA90_VALID_SIZE 1 -+/* Bit: 'RA90_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_SPAN_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_SPAN_SHIFT 6 -+#define AR9_RA_27_24_REG_RA90_SPAN_SIZE 1 -+/* Bit: 'RA90_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_MG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_MG_SHIFT 5 -+#define AR9_RA_27_24_REG_RA90_MG_SIZE 1 -+/* Bit: 'RA90_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_CV_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_CV_SHIFT 4 -+#define AR9_RA_27_24_REG_RA90_CV_SIZE 1 -+/* Bit: 'RA90_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_TXTAG_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_TXTAG_SHIFT 2 -+#define AR9_RA_27_24_REG_RA90_TXTAG_SIZE 2 -+/* Bit: 'RA90_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_27_24_REG_RA90_ACT_OFFSET 0x01A4 -+#define AR9_RA_27_24_REG_RA90_ACT_SHIFT 0 -+#define AR9_RA_27_24_REG_RA90_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200002B~0180C2000028' */ -+/* Bit: 'RA103_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_VALID_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_VALID_SHIFT 31 -+#define AR9_RA_2B_28_REG_RA103_VALID_SIZE 1 -+/* Bit: 'RA103_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_SPAN_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_SPAN_SHIFT 30 -+#define AR9_RA_2B_28_REG_RA103_SPAN_SIZE 1 -+/* Bit: 'RA103_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_MG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_MG_SHIFT 29 -+#define AR9_RA_2B_28_REG_RA103_MG_SIZE 1 -+/* Bit: 'RA103_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_CV_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_CV_SHIFT 28 -+#define AR9_RA_2B_28_REG_RA103_CV_SIZE 1 -+/* Bit: 'RA103_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_TXTAG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_TXTAG_SHIFT 26 -+#define AR9_RA_2B_28_REG_RA103_TXTAG_SIZE 2 -+/* Bit: 'RA103_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_2B_28_REG_RA103_ACT_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA103_ACT_SHIFT 24 -+#define AR9_RA_2B_28_REG_RA103_ACT_SIZE 2 -+/* Bit: 'RA102_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_VALID_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_VALID_SHIFT 23 -+#define AR9_RA_2B_28_REG_RA102_VALID_SIZE 1 -+/* Bit: 'RA102_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_SPAN_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_SPAN_SHIFT 22 -+#define AR9_RA_2B_28_REG_RA102_SPAN_SIZE 1 -+/* Bit: 'RA102_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_MG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_MG_SHIFT 21 -+#define AR9_RA_2B_28_REG_RA102_MG_SIZE 1 -+/* Bit: 'RA102_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_CV_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_CV_SHIFT 20 -+#define AR9_RA_2B_28_REG_RA102_CV_SIZE 1 -+/* Bit: 'RA102_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_TXTAG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_TXTAG_SHIFT 18 -+#define AR9_RA_2B_28_REG_RA102_TXTAG_SIZE 2 -+/* Bit: 'RA102_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_2B_28_REG_RA102_ACT_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA102_ACT_SHIFT 16 -+#define AR9_RA_2B_28_REG_RA102_ACT_SIZE 2 -+/* Bit: 'RA101_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_VALID_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_VALID_SHIFT 15 -+#define AR9_RA_2B_28_REG_RA101_VALID_SIZE 1 -+/* Bit: 'RA101_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_SPAN_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_SPAN_SHIFT 14 -+#define AR9_RA_2B_28_REG_RA101_SPAN_SIZE 1 -+/* Bit: 'RA101_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_MG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_MG_SHIFT 13 -+#define AR9_RA_2B_28_REG_RA101_MG_SIZE 1 -+/* Bit: 'RA101_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_CV_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_CV_SHIFT 12 -+#define AR9_RA_2B_28_REG_RA101_CV_SIZE 1 -+/* Bit: 'RA101_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_TXTAG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_TXTAG_SHIFT 10 -+#define AR9_RA_2B_28_REG_RA101_TXTAG_SIZE 2 -+/* Bit: 'RA101_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_2B_28_REG_RA101_ACT_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA101_ACT_SHIFT 8 -+#define AR9_RA_2B_28_REG_RA101_ACT_SIZE 2 -+/* Bit: 'RA100_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_VALID_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_VALID_SHIFT 7 -+#define AR9_RA_2B_28_REG_RA100_VALID_SIZE 1 -+/* Bit: 'RA100_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_SPAN_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_SPAN_SHIFT 6 -+#define AR9_RA_2B_28_REG_RA100_SPAN_SIZE 1 -+/* Bit: 'RA100_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_MG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_MG_SHIFT 5 -+#define AR9_RA_2B_28_REG_RA100_MG_SIZE 1 -+/* Bit: 'RA100_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_CV_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_CV_SHIFT 4 -+#define AR9_RA_2B_28_REG_RA100_CV_SIZE 1 -+/* Bit: 'RA100_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_TXTAG_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_TXTAG_SHIFT 2 -+#define AR9_RA_2B_28_REG_RA100_TXTAG_SIZE 2 -+/* Bit: 'RA100_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_2B_28_REG_RA100_ACT_OFFSET 0x01A8 -+#define AR9_RA_2B_28_REG_RA100_ACT_SHIFT 0 -+#define AR9_RA_2B_28_REG_RA100_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200002F~0180C200002C' */ -+/* Bit: 'RA113_VALID' */ -+/* Description: 'Valid bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_VALID_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_VALID_SHIFT 31 -+#define AR9_RA_2F_2C_REG_RA113_VALID_SIZE 1 -+/* Bit: 'RA113_SPAN' */ -+/* Description: 'Span bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_SPAN_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_SPAN_SHIFT 30 -+#define AR9_RA_2F_2C_REG_RA113_SPAN_SIZE 1 -+/* Bit: 'RA113_MG' */ -+/* Description: 'Management bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_MG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_MG_SHIFT 29 -+#define AR9_RA_2F_2C_REG_RA113_MG_SIZE 1 -+/* Bit: 'RA113_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_CV_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_CV_SHIFT 28 -+#define AR9_RA_2F_2C_REG_RA113_CV_SIZE 1 -+/* Bit: 'RA113_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_TXTAG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_TXTAG_SHIFT 26 -+#define AR9_RA_2F_2C_REG_RA113_TXTAG_SIZE 2 -+/* Bit: 'RA113_ACT' */ -+/* Description: 'Action bit for 0180C2000003' */ -+#define AR9_RA_2F_2C_REG_RA113_ACT_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA113_ACT_SHIFT 24 -+#define AR9_RA_2F_2C_REG_RA113_ACT_SIZE 2 -+/* Bit: 'RA112_VALID' */ -+/* Description: 'Valid bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_VALID_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_VALID_SHIFT 23 -+#define AR9_RA_2F_2C_REG_RA112_VALID_SIZE 1 -+/* Bit: 'RA112_SPAN' */ -+/* Description: 'Span bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_SPAN_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_SPAN_SHIFT 22 -+#define AR9_RA_2F_2C_REG_RA112_SPAN_SIZE 1 -+/* Bit: 'RA112_MG' */ -+/* Description: 'Management bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_MG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_MG_SHIFT 21 -+#define AR9_RA_2F_2C_REG_RA112_MG_SIZE 1 -+/* Bit: 'RA112_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_CV_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_CV_SHIFT 20 -+#define AR9_RA_2F_2C_REG_RA112_CV_SIZE 1 -+/* Bit: 'RA112_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_TXTAG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_TXTAG_SHIFT 18 -+#define AR9_RA_2F_2C_REG_RA112_TXTAG_SIZE 2 -+/* Bit: 'RA112_ACT' */ -+/* Description: 'Action bit for 0180C2000002' */ -+#define AR9_RA_2F_2C_REG_RA112_ACT_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA112_ACT_SHIFT 16 -+#define AR9_RA_2F_2C_REG_RA112_ACT_SIZE 2 -+/* Bit: 'RA111_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_VALID_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_VALID_SHIFT 15 -+#define AR9_RA_2F_2C_REG_RA111_VALID_SIZE 1 -+/* Bit: 'RA111_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_SPAN_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_SPAN_SHIFT 14 -+#define AR9_RA_2F_2C_REG_RA111_SPAN_SIZE 1 -+/* Bit: 'RA111_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_MG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_MG_SHIFT 13 -+#define AR9_RA_2F_2C_REG_RA111_MG_SIZE 1 -+/* Bit: 'RA111_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_CV_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_CV_SHIFT 12 -+#define AR9_RA_2F_2C_REG_RA111_CV_SIZE 1 -+/* Bit: 'RA111_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_TXTAG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_TXTAG_SHIFT 10 -+#define AR9_RA_2F_2C_REG_RA111_TXTAG_SIZE 2 -+/* Bit: 'RA111_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define AR9_RA_2F_2C_REG_RA111_ACT_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA111_ACT_SHIFT 8 -+#define AR9_RA_2F_2C_REG_RA111_ACT_SIZE 2 -+/* Bit: 'RA110_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_VALID_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_VALID_SHIFT 7 -+#define AR9_RA_2F_2C_REG_RA110_VALID_SIZE 1 -+/* Bit: 'RA110_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_SPAN_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_SPAN_SHIFT 6 -+#define AR9_RA_2F_2C_REG_RA110_SPAN_SIZE 1 -+/* Bit: 'RA110_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_MG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_MG_SHIFT 5 -+#define AR9_RA_2F_2C_REG_RA110_MG_SIZE 1 -+/* Bit: 'RA110_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_CV_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_CV_SHIFT 4 -+#define AR9_RA_2F_2C_REG_RA110_CV_SIZE 1 -+/* Bit: 'RA110_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_TXTAG_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_TXTAG_SHIFT 2 -+#define AR9_RA_2F_2C_REG_RA110_TXTAG_SIZE 2 -+/* Bit: 'RA110_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define AR9_RA_2F_2C_REG_RA110_ACT_OFFSET 0x01AC -+#define AR9_RA_2F_2C_REG_RA110_ACT_SHIFT 0 -+#define AR9_RA_2F_2C_REG_RA110_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 0' */ -+/* Bit: 'PFR3' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F0_REG_PFR3_OFFSET 0x01B0 -+#define AR9_PRTCL_F0_REG_PFR3_SHIFT 24 -+#define AR9_PRTCL_F0_REG_PFR3_SIZE 8 -+/* Bit: 'PFR2' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F0_REG_PFR2_OFFSET 0x01B0 -+#define AR9_PRTCL_F0_REG_PFR2_SHIFT 16 -+#define AR9_PRTCL_F0_REG_PFR2_SIZE 8 -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F0_REG_PFR1_OFFSET 0x01B0 -+#define AR9_PRTCL_F0_REG_PFR1_SHIFT 8 -+#define AR9_PRTCL_F0_REG_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F0_REG_PFR0_OFFSET 0x01B0 -+#define AR9_PRTCL_F0_REG_PFR0_SHIFT 0 -+#define AR9_PRTCL_F0_REG_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 1' */ -+/* Bit: 'PFR3' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F1_REG_PFR3_OFFSET 0x01B4 -+#define AR9_PRTCL_F1_REG_PFR3_SHIFT 24 -+#define AR9_PRTCL_F1_REG_PFR3_SIZE 8 -+/* Bit: 'PFR2' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F1_REG_PFR2_OFFSET 0x01B4 -+#define AR9_PRTCL_F1_REG_PFR2_SHIFT 16 -+#define AR9_PRTCL_F1_REG_PFR2_SIZE 8 -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F1_REG_PFR1_OFFSET 0x01B4 -+#define AR9_PRTCL_F1_REG_PFR1_SHIFT 8 -+#define AR9_PRTCL_F1_REG_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define AR9_PRTCL_F1_REG_PFR0_OFFSET 0x01B4 -+#define AR9_PRTCL_F1_REG_PFR0_SHIFT 0 -+#define AR9_PRTCL_F1_REG_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+#endif /* #ifndef _AR9_H */ -diff --git a/include/switch_api/Tantos3G.h b/include/switch_api/Tantos3G.h -new file mode 100644 -index 0000000..04cb62f ---- /dev/null -+++ b/include/switch_api/Tantos3G.h -@@ -0,0 +1,5882 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+ -+#ifndef _TANTOS3G_H -+#define _TANTOS3G_H -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Status Register' */ -+/* Bit: 'P0FCS' */ -+/* Description: 'Port 0 Flow Control Status' */ -+#define TANTOS_3G_P0S_P0FCS_OFFSET 0x00 -+#define TANTOS_3G_P0S_P0FCS_SHIFT 4 -+#define TANTOS_3G_P0S_P0FCS_SIZE 1 -+/* Bit: 'P0DS' */ -+/* Description: 'Port 0 Duplex Status' */ -+#define TANTOS_3G_P0S_P0DS_OFFSET 0x00 -+#define TANTOS_3G_P0S_P0DS_SHIFT 3 -+#define TANTOS_3G_P0S_P0DS_SIZE 1 -+/* Bit: 'P0SHS' */ -+/* Description: 'Port 0 Speed High Status' */ -+#define TANTOS_3G_P0S_P0SHS_OFFSET 0x00 -+#define TANTOS_3G_P0S_P0SHS_SHIFT 2 -+#define TANTOS_3G_P0S_P0SHS_SIZE 1 -+/* Bit: 'P0SS' */ -+/* Description: 'Port 0 Speed Status' */ -+#define TANTOS_3G_P0S_P0SS_OFFSET 0x00 -+#define TANTOS_3G_P0S_P0SS_SHIFT 1 -+#define TANTOS_3G_P0S_P0SS_SIZE 1 -+/* Bit: 'P0LS' */ -+/* Description: 'Port 0 Link Status' */ -+#define TANTOS_3G_P0S_P0LS_OFFSET 0x00 -+#define TANTOS_3G_P0S_P0LS_SHIFT 0 -+#define TANTOS_3G_P0S_P0LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Status Register' */ -+/* Bit: 'P1FCS' */ -+/* Description: 'Port 1 Flow Control Status' */ -+#define TANTOS_3G_P1S_P1FCS_OFFSET 0x20 -+#define TANTOS_3G_P1S_P1FCS_SHIFT 4 -+#define TANTOS_3G_P1S_P1FCS_SIZE 1 -+/* Bit: 'P1DS' */ -+/* Description: 'Port 1 Duplex Status' */ -+#define TANTOS_3G_P1S_P1DS_OFFSET 0x20 -+#define TANTOS_3G_P1S_P1DS_SHIFT 3 -+#define TANTOS_3G_P1S_P1DS_SIZE 1 -+/* Bit: 'P1SHS' */ -+/* Description: 'Port 1 Speed High Status' */ -+#define TANTOS_3G_P1S_P1SHS_OFFSET 0x20 -+#define TANTOS_3G_P1S_P1SHS_SHIFT 2 -+#define TANTOS_3G_P1S_P1SHS_SIZE 1 -+/* Bit: 'P1SS' */ -+/* Description: 'Port 1 Speed Status' */ -+#define TANTOS_3G_P1S_P1SS_OFFSET 0x20 -+#define TANTOS_3G_P1S_P1SS_SHIFT 1 -+#define TANTOS_3G_P1S_P1SS_SIZE 1 -+/* Bit: 'P1LS' */ -+/* Description: 'Port 1 Link Status' */ -+#define TANTOS_3G_P1S_P1LS_OFFSET 0x20 -+#define TANTOS_3G_P1S_P1LS_SHIFT 0 -+#define TANTOS_3G_P1S_P1LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Status Register' */ -+/* Bit: 'P2FCS' */ -+/* Description: 'Port 2 Flow Control Status' */ -+#define TANTOS_3G_P2S_P2FCS_OFFSET 0x40 -+#define TANTOS_3G_P2S_P2FCS_SHIFT 4 -+#define TANTOS_3G_P2S_P2FCS_SIZE 1 -+/* Bit: 'P2DS' */ -+/* Description: 'Port 2 Duplex Status' */ -+#define TANTOS_3G_P2S_P2DS_OFFSET 0x40 -+#define TANTOS_3G_P2S_P2DS_SHIFT 3 -+#define TANTOS_3G_P2S_P2DS_SIZE 1 -+/* Bit: 'P2SHS' */ -+/* Description: 'Port 2 Speed High Status' */ -+#define TANTOS_3G_P2S_P2SHS_OFFSET 0x40 -+#define TANTOS_3G_P2S_P2SHS_SHIFT 2 -+#define TANTOS_3G_P2S_P2SHS_SIZE 1 -+/* Bit: 'P2SS' */ -+/* Description: 'Port 2 Speed Status' */ -+#define TANTOS_3G_P2S_P2SS_OFFSET 0x40 -+#define TANTOS_3G_P2S_P2SS_SHIFT 1 -+#define TANTOS_3G_P2S_P2SS_SIZE 1 -+/* Bit: 'P2LS' */ -+/* Description: 'Port 2 Link Status' */ -+#define TANTOS_3G_P2S_P2LS_OFFSET 0x40 -+#define TANTOS_3G_P2S_P2LS_SHIFT 0 -+#define TANTOS_3G_P2S_P2LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Status Register' */ -+/* Bit: 'P3FCS' */ -+/* Description: 'Port 3 Flow Control Status' */ -+#define TANTOS_3G_P3S_P3FCS_OFFSET 0x60 -+#define TANTOS_3G_P3S_P3FCS_SHIFT 4 -+#define TANTOS_3G_P3S_P3FCS_SIZE 1 -+/* Bit: 'P3DS' */ -+/* Description: 'Port 3 Duplex Status' */ -+#define TANTOS_3G_P3S_P3DS_OFFSET 0x60 -+#define TANTOS_3G_P3S_P3DS_SHIFT 3 -+#define TANTOS_3G_P3S_P3DS_SIZE 1 -+/* Bit: 'P3SHS' */ -+/* Description: 'Port 3 Speed High Status' */ -+#define TANTOS_3G_P3S_P3SHS_OFFSET 0x60 -+#define TANTOS_3G_P3S_P3SHS_SHIFT 2 -+#define TANTOS_3G_P3S_P3SHS_SIZE 1 -+/* Bit: 'P3SS' */ -+/* Description: 'Port 3 Speed Status' */ -+#define TANTOS_3G_P3S_P3SS_OFFSET 0x60 -+#define TANTOS_3G_P3S_P3SS_SHIFT 1 -+#define TANTOS_3G_P3S_P3SS_SIZE 1 -+/* Bit: 'P3LS' */ -+/* Description: 'Port 3 Link Status' */ -+#define TANTOS_3G_P3S_P3LS_OFFSET 0x60 -+#define TANTOS_3G_P3S_P3LS_SHIFT 0 -+#define TANTOS_3G_P3S_P3LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Status Register' */ -+/* Bit: 'P4FCS' */ -+/* Description: 'Port 4 Flow Control Status' */ -+#define TANTOS_3G_P4S_P4FCS_OFFSET 0x80 -+#define TANTOS_3G_P4S_P4FCS_SHIFT 4 -+#define TANTOS_3G_P4S_P4FCS_SIZE 1 -+/* Bit: 'P4DS' */ -+/* Description: 'Port 4 Duplex Status' */ -+#define TANTOS_3G_P4S_P4DS_OFFSET 0x80 -+#define TANTOS_3G_P4S_P4DS_SHIFT 3 -+#define TANTOS_3G_P4S_P4DS_SIZE 1 -+/* Bit: 'P4SHS' */ -+/* Description: 'Port 4 Speed High Status' */ -+#define TANTOS_3G_P4S_P4SHS_OFFSET 0x80 -+#define TANTOS_3G_P4S_P4SHS_SHIFT 2 -+#define TANTOS_3G_P4S_P4SHS_SIZE 1 -+/* Bit: 'P4SS' */ -+/* Description: 'Port 4 Speed Status' */ -+#define TANTOS_3G_P4S_P4SS_OFFSET 0x80 -+#define TANTOS_3G_P4S_P4SS_SHIFT 1 -+#define TANTOS_3G_P4S_P4SS_SIZE 1 -+/* Bit: 'P4LS' */ -+/* Description: 'Port 4 Link Status' */ -+#define TANTOS_3G_P4S_P4LS_OFFSET 0x80 -+#define TANTOS_3G_P4S_P4LS_SHIFT 0 -+#define TANTOS_3G_P4S_P4LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Status Register' */ -+/* Bit: 'P5FCS' */ -+/* Description: 'Port 5 Flow Control Status' */ -+#define TANTOS_3G_P5S_P5FCS_OFFSET 0xA0 -+#define TANTOS_3G_P5S_P5FCS_SHIFT 4 -+#define TANTOS_3G_P5S_P5FCS_SIZE 1 -+/* Bit: 'P5DS' */ -+/* Description: 'Port 5 Duplex Status' */ -+#define TANTOS_3G_P5S_P5DS_OFFSET 0xA0 -+#define TANTOS_3G_P5S_P5DS_SHIFT 3 -+#define TANTOS_3G_P5S_P5DS_SIZE 1 -+/* Bit: 'P5SHS' */ -+/* Description: 'Port 5 Speed High Status' */ -+#define TANTOS_3G_P5S_P5SHS_OFFSET 0xA0 -+#define TANTOS_3G_P5S_P5SHS_SHIFT 2 -+#define TANTOS_3G_P5S_P5SHS_SIZE 1 -+/* Bit: 'P5SS' */ -+/* Description: 'Port 5 Speed Status' */ -+#define TANTOS_3G_P5S_P5SS_OFFSET 0xA0 -+#define TANTOS_3G_P5S_P5SS_SHIFT 1 -+#define TANTOS_3G_P5S_P5SS_SIZE 1 -+/* Bit: 'P5LS' */ -+/* Description: 'Port 5 Link Status' */ -+#define TANTOS_3G_P5S_P5LS_OFFSET 0xA0 -+#define TANTOS_3G_P5S_P5LS_SHIFT 0 -+#define TANTOS_3G_P5S_P5LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Status Register' */ -+/* Bit: 'P6FCS' */ -+/* Description: 'Port 6 Flow Control Status' */ -+#define TANTOS_3G_P6S_P6FCS_OFFSET 0xC0 -+#define TANTOS_3G_P6S_P6FCS_SHIFT 4 -+#define TANTOS_3G_P6S_P6FCS_SIZE 1 -+/* Bit: 'P6DS' */ -+/* Description: 'Port 6 Duplex Status' */ -+#define TANTOS_3G_P6S_P6DS_OFFSET 0xC0 -+#define TANTOS_3G_P6S_P6DS_SHIFT 3 -+#define TANTOS_3G_P6S_P6DS_SIZE 1 -+/* Bit: 'P6SHS' */ -+/* Description: 'Port 6 Speed High Status' */ -+#define TANTOS_3G_P6S_P6SHS_OFFSET 0xC0 -+#define TANTOS_3G_P6S_P6SHS_SHIFT 2 -+#define TANTOS_3G_P6S_P6SHS_SIZE 1 -+/* Bit: 'P6SS' */ -+/* Description: 'Port 6 Speed Status' */ -+#define TANTOS_3G_P6S_P6SS_OFFSET 0xC0 -+#define TANTOS_3G_P6S_P6SS_SHIFT 1 -+#define TANTOS_3G_P6S_P6SS_SIZE 1 -+/* Bit: 'P6LS' */ -+/* Description: 'Port 6 Link Status' */ -+#define TANTOS_3G_P6S_P6LS_OFFSET 0xC0 -+#define TANTOS_3G_P6S_P6LS_SHIFT 0 -+#define TANTOS_3G_P6S_P6LS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P0 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P0BC_SPS_OFFSET 0x01 -+#define TANTOS_3G_P0BC_SPS_SHIFT 14 -+#define TANTOS_3G_P0BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P0BC_TCPE_OFFSET 0x01 -+#define TANTOS_3G_P0BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P0BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P0BC_IPOVTU_OFFSET 0x01 -+#define TANTOS_3G_P0BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P0BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P0BC_VPE_OFFSET 0x01 -+#define TANTOS_3G_P0BC_VPE_SHIFT 11 -+#define TANTOS_3G_P0BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P0BC_SPE_OFFSET 0x01 -+#define TANTOS_3G_P0BC_SPE_SHIFT 10 -+#define TANTOS_3G_P0BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P0BC_IPVLAN_OFFSET 0x01 -+#define TANTOS_3G_P0BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P0BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P0BC_TPE_OFFSET 0x01 -+#define TANTOS_3G_P0BC_TPE_SHIFT 8 -+#define TANTOS_3G_P0BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P0BC_FLP_OFFSET 0x01 -+#define TANTOS_3G_P0BC_FLP_SHIFT 2 -+#define TANTOS_3G_P0BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P0BC_FLD_OFFSET 0x01 -+#define TANTOS_3G_P0BC_FLD_SHIFT 1 -+#define TANTOS_3G_P0BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P0BC_RMWFQ_OFFSET 0x01 -+#define TANTOS_3G_P0BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P0BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P1 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P1BC_SPS_OFFSET 0x21 -+#define TANTOS_3G_P1BC_SPS_SHIFT 14 -+#define TANTOS_3G_P1BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P1BC_TCPE_OFFSET 0x21 -+#define TANTOS_3G_P1BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P1BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P1BC_IPOVTU_OFFSET 0x21 -+#define TANTOS_3G_P1BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P1BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P1BC_VPE_OFFSET 0x21 -+#define TANTOS_3G_P1BC_VPE_SHIFT 11 -+#define TANTOS_3G_P1BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P1BC_SPE_OFFSET 0x21 -+#define TANTOS_3G_P1BC_SPE_SHIFT 10 -+#define TANTOS_3G_P1BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P1BC_IPVLAN_OFFSET 0x21 -+#define TANTOS_3G_P1BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P1BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P1BC_TPE_OFFSET 0x21 -+#define TANTOS_3G_P1BC_TPE_SHIFT 8 -+#define TANTOS_3G_P1BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P1BC_FLP_OFFSET 0x21 -+#define TANTOS_3G_P1BC_FLP_SHIFT 2 -+#define TANTOS_3G_P1BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P1BC_FLD_OFFSET 0x21 -+#define TANTOS_3G_P1BC_FLD_SHIFT 1 -+#define TANTOS_3G_P1BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P1BC_RMWFQ_OFFSET 0x21 -+#define TANTOS_3G_P1BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P1BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P2 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P2BC_SPS_OFFSET 0x41 -+#define TANTOS_3G_P2BC_SPS_SHIFT 14 -+#define TANTOS_3G_P2BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P2BC_TCPE_OFFSET 0x41 -+#define TANTOS_3G_P2BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P2BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P2BC_IPOVTU_OFFSET 0x41 -+#define TANTOS_3G_P2BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P2BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P2BC_VPE_OFFSET 0x41 -+#define TANTOS_3G_P2BC_VPE_SHIFT 11 -+#define TANTOS_3G_P2BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P2BC_SPE_OFFSET 0x41 -+#define TANTOS_3G_P2BC_SPE_SHIFT 10 -+#define TANTOS_3G_P2BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P2BC_IPVLAN_OFFSET 0x41 -+#define TANTOS_3G_P2BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P2BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P2BC_TPE_OFFSET 0x41 -+#define TANTOS_3G_P2BC_TPE_SHIFT 8 -+#define TANTOS_3G_P2BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P2BC_FLP_OFFSET 0x41 -+#define TANTOS_3G_P2BC_FLP_SHIFT 2 -+#define TANTOS_3G_P2BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P2BC_FLD_OFFSET 0x41 -+#define TANTOS_3G_P2BC_FLD_SHIFT 1 -+#define TANTOS_3G_P2BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P2BC_RMWFQ_OFFSET 0x41 -+#define TANTOS_3G_P2BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P2BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P3 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P3BC_SPS_OFFSET 0x61 -+#define TANTOS_3G_P3BC_SPS_SHIFT 14 -+#define TANTOS_3G_P3BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P3BC_TCPE_OFFSET 0x61 -+#define TANTOS_3G_P3BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P3BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P3BC_IPOVTU_OFFSET 0x61 -+#define TANTOS_3G_P3BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P3BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P3BC_VPE_OFFSET 0x61 -+#define TANTOS_3G_P3BC_VPE_SHIFT 11 -+#define TANTOS_3G_P3BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P3BC_SPE_OFFSET 0x61 -+#define TANTOS_3G_P3BC_SPE_SHIFT 10 -+#define TANTOS_3G_P3BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P3BC_IPVLAN_OFFSET 0x61 -+#define TANTOS_3G_P3BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P3BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P3BC_TPE_OFFSET 0x61 -+#define TANTOS_3G_P3BC_TPE_SHIFT 8 -+#define TANTOS_3G_P3BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P3BC_FLP_OFFSET 0x61 -+#define TANTOS_3G_P3BC_FLP_SHIFT 2 -+#define TANTOS_3G_P3BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P3BC_FLD_OFFSET 0x61 -+#define TANTOS_3G_P3BC_FLD_SHIFT 1 -+#define TANTOS_3G_P3BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P3BC_RMWFQ_OFFSET 0x61 -+#define TANTOS_3G_P3BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P3BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P4 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P4BC_SPS_OFFSET 0x81 -+#define TANTOS_3G_P4BC_SPS_SHIFT 14 -+#define TANTOS_3G_P4BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P4BC_TCPE_OFFSET 0x81 -+#define TANTOS_3G_P4BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P4BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P4BC_IPOVTU_OFFSET 0x81 -+#define TANTOS_3G_P4BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P4BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P4BC_VPE_OFFSET 0x81 -+#define TANTOS_3G_P4BC_VPE_SHIFT 11 -+#define TANTOS_3G_P4BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P4BC_SPE_OFFSET 0x81 -+#define TANTOS_3G_P4BC_SPE_SHIFT 10 -+#define TANTOS_3G_P4BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P4BC_IPVLAN_OFFSET 0x81 -+#define TANTOS_3G_P4BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P4BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P4BC_TPE_OFFSET 0x81 -+#define TANTOS_3G_P4BC_TPE_SHIFT 8 -+#define TANTOS_3G_P4BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P4BC_FLP_OFFSET 0x81 -+#define TANTOS_3G_P4BC_FLP_SHIFT 2 -+#define TANTOS_3G_P4BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P4BC_FLD_OFFSET 0x81 -+#define TANTOS_3G_P4BC_FLD_SHIFT 1 -+#define TANTOS_3G_P4BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P4BC_RMWFQ_OFFSET 0x81 -+#define TANTOS_3G_P4BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P4BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P5 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P5BC_SPS_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_SPS_SHIFT 14 -+#define TANTOS_3G_P5BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P5BC_TCPE_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P5BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P5BC_IPOVTU_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P5BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P5BC_VPE_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_VPE_SHIFT 11 -+#define TANTOS_3G_P5BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P5BC_SPE_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_SPE_SHIFT 10 -+#define TANTOS_3G_P5BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P5BC_IPVLAN_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P5BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P5BC_TPE_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_TPE_SHIFT 8 -+#define TANTOS_3G_P5BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P5BC_FLP_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_FLP_SHIFT 2 -+#define TANTOS_3G_P5BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P5BC_FLD_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_FLD_SHIFT 1 -+#define TANTOS_3G_P5BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P5BC_RMWFQ_OFFSET 0xA1 -+#define TANTOS_3G_P5BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P5BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P6 Basic Control Register' */ -+/* Bit: 'SPS' */ -+/* Description: 'STP/RSTP port state' */ -+#define TANTOS_3G_P6BC_SPS_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_SPS_SHIFT 14 -+#define TANTOS_3G_P6BC_SPS_SIZE 2 -+/* Bit: 'TCPE' */ -+/* Description: 'TCP/UDP PRIEN' */ -+#define TANTOS_3G_P6BC_TCPE_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_TCPE_SHIFT 13 -+#define TANTOS_3G_P6BC_TCPE_SIZE 1 -+/* Bit: 'IPOVTU' */ -+/* Description: ' IP over TCP/UDP' */ -+#define TANTOS_3G_P6BC_IPOVTU_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_IPOVTU_SHIFT 12 -+#define TANTOS_3G_P6BC_IPOVTU_SIZE 1 -+/* Bit: 'VPE' */ -+/* Description: 'VLAN Priority Enable' */ -+#define TANTOS_3G_P6BC_VPE_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_VPE_SHIFT 11 -+#define TANTOS_3G_P6BC_VPE_SIZE 1 -+/* Bit: 'SPE' */ -+/* Description: 'Service Priority Enable' */ -+#define TANTOS_3G_P6BC_SPE_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_SPE_SHIFT 10 -+#define TANTOS_3G_P6BC_SPE_SIZE 1 -+/* Bit: 'IPVLAN' */ -+/* Description: 'IP over VLAN PRI' */ -+#define TANTOS_3G_P6BC_IPVLAN_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_IPVLAN_SHIFT 9 -+#define TANTOS_3G_P6BC_IPVLAN_SIZE 1 -+/* Bit: 'TPE' */ -+/* Description: 'Ether Type Priority Enable' */ -+#define TANTOS_3G_P6BC_TPE_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_TPE_SHIFT 8 -+#define TANTOS_3G_P6BC_TPE_SIZE 1 -+/* Bit: 'FLP' */ -+/* Description: 'Force Link Up' */ -+#define TANTOS_3G_P6BC_FLP_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_FLP_SHIFT 2 -+#define TANTOS_3G_P6BC_FLP_SIZE 1 -+/* Bit: 'FLD' */ -+/* Description: 'Force Link Down' */ -+#define TANTOS_3G_P6BC_FLD_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_FLD_SHIFT 1 -+#define TANTOS_3G_P6BC_FLD_SIZE 1 -+/* Bit: 'RMWFQ' */ -+/* Description: 'Ratio Mode for WFQ' */ -+#define TANTOS_3G_P6BC_RMWFQ_OFFSET 0xC1 -+#define TANTOS_3G_P6BC_RMWFQ_SHIFT 0 -+#define TANTOS_3G_P6BC_RMWFQ_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P0 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P0EC_AD_OFFSET 0x02 -+#define TANTOS_3G_P0EC_AD_SHIFT 15 -+#define TANTOS_3G_P0EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P0EC_LD_OFFSET 0x02 -+#define TANTOS_3G_P0EC_LD_SHIFT 14 -+#define TANTOS_3G_P0EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P0EC_IMTE_OFFSET 0x02 -+#define TANTOS_3G_P0EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P0EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P0EC_MNA024_OFFSET 0x02 -+#define TANTOS_3G_P0EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P0EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P0EC_PPPOEP_OFFSET 0x02 -+#define TANTOS_3G_P0EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P0EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P0EC_PM_OFFSET 0x02 -+#define TANTOS_3G_P0EC_PM_SHIFT 6 -+#define TANTOS_3G_P0EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P0EC_IPMO_OFFSET 0x02 -+#define TANTOS_3G_P0EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P0EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P0EC_PAS_OFFSET 0x02 -+#define TANTOS_3G_P0EC_PAS_SHIFT 2 -+#define TANTOS_3G_P0EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P0EC_IFNTE_OFFSET 0x02 -+#define TANTOS_3G_P0EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P0EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P1 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P1EC_AD_OFFSET 0x22 -+#define TANTOS_3G_P1EC_AD_SHIFT 15 -+#define TANTOS_3G_P1EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P1EC_LD_OFFSET 0x22 -+#define TANTOS_3G_P1EC_LD_SHIFT 14 -+#define TANTOS_3G_P1EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P1EC_IMTE_OFFSET 0x22 -+#define TANTOS_3G_P1EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P1EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P1EC_MNA024_OFFSET 0x22 -+#define TANTOS_3G_P1EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P1EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P1EC_PPPOEP_OFFSET 0x22 -+#define TANTOS_3G_P1EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P1EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P1EC_PM_OFFSET 0x22 -+#define TANTOS_3G_P1EC_PM_SHIFT 6 -+#define TANTOS_3G_P1EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P1EC_IPMO_OFFSET 0x22 -+#define TANTOS_3G_P1EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P1EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P1EC_PAS_OFFSET 0x22 -+#define TANTOS_3G_P1EC_PAS_SHIFT 2 -+#define TANTOS_3G_P1EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P1EC_IFNTE_OFFSET 0x22 -+#define TANTOS_3G_P1EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P1EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P2 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P2EC_AD_OFFSET 0x42 -+#define TANTOS_3G_P2EC_AD_SHIFT 15 -+#define TANTOS_3G_P2EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P2EC_LD_OFFSET 0x42 -+#define TANTOS_3G_P2EC_LD_SHIFT 14 -+#define TANTOS_3G_P2EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P2EC_IMTE_OFFSET 0x42 -+#define TANTOS_3G_P2EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P2EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P2EC_MNA024_OFFSET 0x42 -+#define TANTOS_3G_P2EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P2EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P2EC_PPPOEP_OFFSET 0x42 -+#define TANTOS_3G_P2EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P2EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P2EC_PM_OFFSET 0x42 -+#define TANTOS_3G_P2EC_PM_SHIFT 6 -+#define TANTOS_3G_P2EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P2EC_IPMO_OFFSET 0x42 -+#define TANTOS_3G_P2EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P2EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P2EC_PAS_OFFSET 0x42 -+#define TANTOS_3G_P2EC_PAS_SHIFT 2 -+#define TANTOS_3G_P2EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P2EC_IFNTE_OFFSET 0x42 -+#define TANTOS_3G_P2EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P2EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P3 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P3EC_AD_OFFSET 0x62 -+#define TANTOS_3G_P3EC_AD_SHIFT 15 -+#define TANTOS_3G_P3EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P3EC_LD_OFFSET 0x62 -+#define TANTOS_3G_P3EC_LD_SHIFT 14 -+#define TANTOS_3G_P3EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P3EC_IMTE_OFFSET 0x62 -+#define TANTOS_3G_P3EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P3EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P3EC_MNA024_OFFSET 0x62 -+#define TANTOS_3G_P3EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P3EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P3EC_PPPOEP_OFFSET 0x62 -+#define TANTOS_3G_P3EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P3EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P3EC_PM_OFFSET 0x62 -+#define TANTOS_3G_P3EC_PM_SHIFT 6 -+#define TANTOS_3G_P3EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P3EC_IPMO_OFFSET 0x62 -+#define TANTOS_3G_P3EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P3EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P3EC_PAS_OFFSET 0x62 -+#define TANTOS_3G_P3EC_PAS_SHIFT 2 -+#define TANTOS_3G_P3EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P3EC_IFNTE_OFFSET 0x62 -+#define TANTOS_3G_P3EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P3EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P4 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P4EC_AD_OFFSET 0x82 -+#define TANTOS_3G_P4EC_AD_SHIFT 15 -+#define TANTOS_3G_P4EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P4EC_LD_OFFSET 0x82 -+#define TANTOS_3G_P4EC_LD_SHIFT 14 -+#define TANTOS_3G_P4EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P4EC_IMTE_OFFSET 0x82 -+#define TANTOS_3G_P4EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P4EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P4EC_MNA024_OFFSET 0x82 -+#define TANTOS_3G_P4EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P4EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P4EC_PPPOEP_OFFSET 0x82 -+#define TANTOS_3G_P4EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P4EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P4EC_PM_OFFSET 0x82 -+#define TANTOS_3G_P4EC_PM_SHIFT 6 -+#define TANTOS_3G_P4EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P4EC_IPMO_OFFSET 0x82 -+#define TANTOS_3G_P4EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P4EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P4EC_PAS_OFFSET 0x82 -+#define TANTOS_3G_P4EC_PAS_SHIFT 2 -+#define TANTOS_3G_P4EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P4EC_IFNTE_OFFSET 0x82 -+#define TANTOS_3G_P4EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P4EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P5 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P5EC_AD_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_AD_SHIFT 15 -+#define TANTOS_3G_P5EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P5EC_LD_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_LD_SHIFT 14 -+#define TANTOS_3G_P5EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P5EC_IMTE_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P5EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P5EC_MNA024_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P5EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P5EC_PPPOEP_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P5EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P5EC_PM_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_PM_SHIFT 6 -+#define TANTOS_3G_P5EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P5EC_IPMO_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P5EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P5EC_PAS_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_PAS_SHIFT 2 -+#define TANTOS_3G_P5EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P5EC_IFNTE_OFFSET 0xA2 -+#define TANTOS_3G_P5EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P5EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'P6 Extended Control Register' */ -+/* Bit: 'AD' */ -+/* Description: 'Aging Disable' */ -+#define TANTOS_3G_P6EC_AD_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_AD_SHIFT 15 -+#define TANTOS_3G_P6EC_AD_SIZE 1 -+/* Bit: 'LD' */ -+/* Description: 'Learning Disable' */ -+#define TANTOS_3G_P6EC_LD_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_LD_SHIFT 14 -+#define TANTOS_3G_P6EC_LD_SIZE 1 -+/* Bit: 'IMTE' */ -+/* Description: 'IGMP/MLD Trap Enable' */ -+#define TANTOS_3G_P6EC_IMTE_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_IMTE_SHIFT 13 -+#define TANTOS_3G_P6EC_IMTE_SIZE 1 -+/* Bit: 'MNA024' */ -+/* Description: 'Maximum Number of Addresses' */ -+#define TANTOS_3G_P6EC_MNA024_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_MNA024_SHIFT 8 -+#define TANTOS_3G_P6EC_MNA024_SIZE 5 -+/* Bit: 'PPPOEP' */ -+/* Description: 'PPPOE Port Only' */ -+#define TANTOS_3G_P6EC_PPPOEP_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_PPPOEP_SHIFT 7 -+#define TANTOS_3G_P6EC_PPPOEP_SIZE 1 -+/* Bit: 'PM' */ -+/* Description: 'PPPOE Manage' */ -+#define TANTOS_3G_P6EC_PM_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_PM_SHIFT 6 -+#define TANTOS_3G_P6EC_PM_SIZE 1 -+/* Bit: 'IPMO' */ -+/* Description: 'Port Mirror Option' */ -+#define TANTOS_3G_P6EC_IPMO_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_IPMO_SHIFT 4 -+#define TANTOS_3G_P6EC_IPMO_SIZE 2 -+/* Bit: 'PAS' */ -+/* Description: '802.1x Port Authorized state' */ -+#define TANTOS_3G_P6EC_PAS_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_PAS_SHIFT 2 -+#define TANTOS_3G_P6EC_PAS_SIZE 2 -+/* Bit: 'IFNTE' */ -+/* Description: 'Input Force No TAG Enable' */ -+#define TANTOS_3G_P6EC_IFNTE_OFFSET 0xC2 -+#define TANTOS_3G_P6EC_IFNTE_SHIFT 1 -+#define TANTOS_3G_P6EC_IFNTE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P0PBVM_DFID_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P0PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P0PBVM_TBVE_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P0PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P0PBVM_VC_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P0PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P0PBVM_VSD_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P0PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P0PBVM_AOVTP_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P0PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P0PBVM_VMCE_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P0PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P0PBVM_BYPASS_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P0PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P0PBVM_DVPM_OFFSET 0x03 -+#define TANTOS_3G_P0PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P0PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P1PBVM_DFID_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P1PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P1PBVM_TBVE_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P1PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P1PBVM_VC_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P1PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P1PBVM_VSD_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P1PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P1PBVM_AOVTP_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P1PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P1PBVM_VMCE_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P1PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P1PBVM_BYPASS_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P1PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P1PBVM_DVPM_OFFSET 0x23 -+#define TANTOS_3G_P1PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P1PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P2PBVM_DFID_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P2PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P2PBVM_TBVE_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P2PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P2PBVM_VC_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P2PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P2PBVM_VSD_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P2PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P2PBVM_AOVTP_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P2PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P2PBVM_VMCE_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P2PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P2PBVM_BYPASS_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P2PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P2PBVM_DVPM_OFFSET 0x43 -+#define TANTOS_3G_P2PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P2PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P3PBVM_DFID_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P3PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P3PBVM_TBVE_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P3PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P3PBVM_VC_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P3PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P3PBVM_VSD_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P3PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P3PBVM_AOVTP_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P3PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P3PBVM_VMCE_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P3PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P3PBVM_BYPASS_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P3PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P3PBVM_DVPM_OFFSET 0x63 -+#define TANTOS_3G_P3PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P3PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P4PBVM_DFID_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P4PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P4PBVM_TBVE_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P4PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P4PBVM_VC_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P4PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P4PBVM_VSD_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P4PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P4PBVM_AOVTP_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P4PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P4PBVM_VMCE_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P4PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P4PBVM_BYPASS_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P4PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P4PBVM_DVPM_OFFSET 0x83 -+#define TANTOS_3G_P4PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P4PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P5PBVM_DFID_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P5PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P5PBVM_TBVE_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P5PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P5PBVM_VC_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P5PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P5PBVM_VSD_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P5PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P5PBVM_AOVTP_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P5PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P5PBVM_VMCE_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P5PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P5PBVM_BYPASS_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P5PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P5PBVM_DVPM_OFFSET 0xA3 -+#define TANTOS_3G_P5PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P5PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Port Base VLAN Map Register' */ -+/* Bit: 'DFID' */ -+/* Description: 'Default FID' */ -+#define TANTOS_3G_P6PBVM_DFID_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_DFID_SHIFT 14 -+#define TANTOS_3G_P6PBVM_DFID_SIZE 2 -+/* Bit: 'TBVE' */ -+/* Description: 'Tagged Base VLAN Enable' */ -+#define TANTOS_3G_P6PBVM_TBVE_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_TBVE_SHIFT 13 -+#define TANTOS_3G_P6PBVM_TBVE_SIZE 1 -+/* Bit: 'VC' */ -+/* Description: 'VID Check with the VID table' */ -+#define TANTOS_3G_P6PBVM_VC_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_VC_SHIFT 11 -+#define TANTOS_3G_P6PBVM_VC_SIZE 1 -+/* Bit: 'VSD' */ -+/* Description: 'VLAN Security Disable' */ -+#define TANTOS_3G_P6PBVM_VSD_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_VSD_SHIFT 10 -+#define TANTOS_3G_P6PBVM_VSD_SIZE 1 -+/* Bit: 'AOVTP' */ -+/* Description: 'Admit Only VLAN_Tagged Packet' */ -+#define TANTOS_3G_P6PBVM_AOVTP_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_AOVTP_SHIFT 9 -+#define TANTOS_3G_P6PBVM_AOVTP_SIZE 1 -+/* Bit: 'VMCE' */ -+/* Description: 'VLAN Member Check Enable' */ -+#define TANTOS_3G_P6PBVM_VMCE_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_VMCE_SHIFT 8 -+#define TANTOS_3G_P6PBVM_VMCE_SIZE 1 -+/* Bit: 'BYPASS' */ -+/* Description: 'ByPass Mode for Output' */ -+#define TANTOS_3G_P6PBVM_BYPASS_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_BYPASS_SHIFT 7 -+#define TANTOS_3G_P6PBVM_BYPASS_SIZE 1 -+/* Bit: 'DVPM' */ -+/* Description: 'Port Based VLAN Port Map' */ -+#define TANTOS_3G_P6PBVM_DVPM_OFFSET 0xC3 -+#define TANTOS_3G_P6PBVM_DVPM_SHIFT 0 -+#define TANTOS_3G_P6PBVM_DVPM_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P0DVID_PP_OFFSET 0x04 -+#define TANTOS_3G_P0DVID_PP_SHIFT 14 -+#define TANTOS_3G_P0DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P0DVID_PPE_OFFSET 0x04 -+#define TANTOS_3G_P0DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P0DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P0DVID_PVTAGMP_OFFSET 0x04 -+#define TANTOS_3G_P0DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P0DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P0DVID_PVID_OFFSET 0x04 -+#define TANTOS_3G_P0DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P0DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P1DVID_PP_OFFSET 0x24 -+#define TANTOS_3G_P1DVID_PP_SHIFT 14 -+#define TANTOS_3G_P1DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P1DVID_PPE_OFFSET 0x24 -+#define TANTOS_3G_P1DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P1DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P1DVID_PVTAGMP_OFFSET 0x24 -+#define TANTOS_3G_P1DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P1DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P1DVID_PVID_OFFSET 0x24 -+#define TANTOS_3G_P1DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P1DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P2DVID_PP_OFFSET 0x44 -+#define TANTOS_3G_P2DVID_PP_SHIFT 14 -+#define TANTOS_3G_P2DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P2DVID_PPE_OFFSET 0x44 -+#define TANTOS_3G_P2DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P2DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P2DVID_PVTAGMP_OFFSET 0x44 -+#define TANTOS_3G_P2DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P2DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P2DVID_PVID_OFFSET 0x44 -+#define TANTOS_3G_P2DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P2DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P3DVID_PP_OFFSET 0x64 -+#define TANTOS_3G_P3DVID_PP_SHIFT 14 -+#define TANTOS_3G_P3DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P3DVID_PPE_OFFSET 0x64 -+#define TANTOS_3G_P3DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P3DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P3DVID_PVTAGMP_OFFSET 0x64 -+#define TANTOS_3G_P3DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P3DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P3DVID_PVID_OFFSET 0x64 -+#define TANTOS_3G_P3DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P3DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P4DVID_PP_OFFSET 0x84 -+#define TANTOS_3G_P4DVID_PP_SHIFT 14 -+#define TANTOS_3G_P4DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P4DVID_PPE_OFFSET 0x84 -+#define TANTOS_3G_P4DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P4DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P4DVID_PVTAGMP_OFFSET 0x84 -+#define TANTOS_3G_P4DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P4DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P4DVID_PVID_OFFSET 0x84 -+#define TANTOS_3G_P4DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P4DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P5DVID_PP_OFFSET 0xA4 -+#define TANTOS_3G_P5DVID_PP_SHIFT 14 -+#define TANTOS_3G_P5DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P5DVID_PPE_OFFSET 0xA4 -+#define TANTOS_3G_P5DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P5DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P5DVID_PVTAGMP_OFFSET 0xA4 -+#define TANTOS_3G_P5DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P5DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P5DVID_PVID_OFFSET 0xA4 -+#define TANTOS_3G_P5DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P5DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Default VLAN ID & Priority Register' */ -+/* Bit: 'PP' */ -+/* Description: 'Port Priority' */ -+#define TANTOS_3G_P6DVID_PP_OFFSET 0xC4 -+#define TANTOS_3G_P6DVID_PP_SHIFT 14 -+#define TANTOS_3G_P6DVID_PP_SIZE 2 -+/* Bit: 'PPE' */ -+/* Description: 'Port Priority Enable' */ -+#define TANTOS_3G_P6DVID_PPE_OFFSET 0xC4 -+#define TANTOS_3G_P6DVID_PPE_SHIFT 13 -+#define TANTOS_3G_P6DVID_PPE_SIZE 1 -+/* Bit: 'PVTAGMP' */ -+/* Description: 'Portbase VLAN tag member for Port 0' */ -+#define TANTOS_3G_P6DVID_PVTAGMP_OFFSET 0xC4 -+#define TANTOS_3G_P6DVID_PVTAGMP_SHIFT 12 -+#define TANTOS_3G_P6DVID_PVTAGMP_SIZE 1 -+/* Bit: 'PVID' */ -+/* Description: 'PVID' */ -+#define TANTOS_3G_P6DVID_PVID_OFFSET 0xC4 -+#define TANTOS_3G_P6DVID_PVID_SHIFT 0 -+#define TANTOS_3G_P6DVID_PVID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_OFFSET 0x05 -+#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_OFFSET 0x25 -+#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_OFFSET 0x45 -+#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_OFFSET 0x65 -+#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_OFFSET 0x85 -+#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_OFFSET 0xA5 -+#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for Strict Q3 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_OFFSET 0xC5 -+#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECSQ3_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_OFFSET 0x06 -+#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_OFFSET 0x26 -+#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_OFFSET 0x46 -+#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_OFFSET 0x66 -+#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_OFFSET 0x86 -+#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_OFFSET 0xA6 -+#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for Strict Q2 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_OFFSET 0xC6 -+#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECSQ2_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_OFFSET 0x07 -+#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_OFFSET 0x27 -+#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_OFFSET 0x47 -+#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_OFFSET 0x67 -+#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_OFFSET 0x87 -+#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_OFFSET 0xA7 -+#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for Strict Q1 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_OFFSET 0xC7 -+#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECSQ1_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_OFFSET 0x08 -+#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_OFFSET 0x28 -+#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_OFFSET 0x48 -+#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_OFFSET 0x68 -+#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_OFFSET 0x88 -+#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_OFFSET 0xA8 -+#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for Strict Q0 Register' */ -+/* Bit: 'P0SPQ3TR' */ -+/* Description: 'Port 0 Egress Token R for Strict Priority Q3' */ -+#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_OFFSET 0xC8 -+#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECSQ0_P0SPQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P0WQ3TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P0ECWQ3_P0WQ3TR_OFFSET 0x09 -+#define TANTOS_3G_P0ECWQ3_P0WQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECWQ3_P0WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P1WQ3TR' */ -+/* Description: 'Port 1 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P1ECWQ3_P1WQ3TR_OFFSET 0x29 -+#define TANTOS_3G_P1ECWQ3_P1WQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECWQ3_P1WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P2WQ3TR' */ -+/* Description: 'Port 2 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P2ECWQ3_P2WQ3TR_OFFSET 0x49 -+#define TANTOS_3G_P2ECWQ3_P2WQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECWQ3_P2WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P3WQ3TR' */ -+/* Description: 'Port 3 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P3ECWQ3_P3WQ3TR_OFFSET 0x69 -+#define TANTOS_3G_P3ECWQ3_P3WQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECWQ3_P3WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P4WQ3TR' */ -+/* Description: 'Port 4 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P4ECWQ3_P4WQ3TR_OFFSET 0x89 -+#define TANTOS_3G_P4ECWQ3_P4WQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECWQ3_P4WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P5WQ3TR' */ -+/* Description: 'Port 5 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P5ECWQ3_P5WQ3TR_OFFSET 0xA9 -+#define TANTOS_3G_P5ECWQ3_P5WQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECWQ3_P5WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for WFQ Q3 Register' */ -+/* Bit: 'P6WQ3TR' */ -+/* Description: 'Port 6 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P6ECWQ3_P6WQ3TR_OFFSET 0xC9 -+#define TANTOS_3G_P6ECWQ3_P6WQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECWQ3_P6WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P0WQ3TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P0ECWQ2_P0WQ3TR_OFFSET 0x0A -+#define TANTOS_3G_P0ECWQ2_P0WQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECWQ2_P0WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P8WQ3TR' */ -+/* Description: 'Port 8 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P1ECWQ2_P8WQ3TR_OFFSET 0x2A -+#define TANTOS_3G_P1ECWQ2_P8WQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECWQ2_P8WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P9WQ3TR' */ -+/* Description: 'Port 9 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P2ECWQ2_P9WQ3TR_OFFSET 0x4A -+#define TANTOS_3G_P2ECWQ2_P9WQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECWQ2_P9WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P10WQ3TR' */ -+/* Description: 'Port 10 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P3ECWQ2_P10WQ3TR_OFFSET 0x6A -+#define TANTOS_3G_P3ECWQ2_P10WQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECWQ2_P10WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P11WQ3TR' */ -+/* Description: 'Port 11 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P4ECWQ2_P11WQ3TR_OFFSET 0x8A -+#define TANTOS_3G_P4ECWQ2_P11WQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECWQ2_P11WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P12WQ3TR' */ -+/* Description: 'Port 12 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P5ECWQ2_P12WQ3TR_OFFSET 0xAA -+#define TANTOS_3G_P5ECWQ2_P12WQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECWQ2_P12WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for WFQ Q2 Register' */ -+/* Bit: 'P13WQ3TR' */ -+/* Description: 'Port 13 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P6ECWQ2_P13WQ3TR_OFFSET 0xCA -+#define TANTOS_3G_P6ECWQ2_P13WQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECWQ2_P13WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P0WQ3TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P0ECWQ1_P0WQ3TR_OFFSET 0x0B -+#define TANTOS_3G_P0ECWQ1_P0WQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECWQ1_P0WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P15WQ3TR' */ -+/* Description: 'Port 15 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P1ECWQ1_P15WQ3TR_OFFSET 0x2B -+#define TANTOS_3G_P1ECWQ1_P15WQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECWQ1_P15WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P16WQ3TR' */ -+/* Description: 'Port 16 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P2ECWQ1_P16WQ3TR_OFFSET 0x4B -+#define TANTOS_3G_P2ECWQ1_P16WQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECWQ1_P16WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P17WQ3TR' */ -+/* Description: 'Port 17 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P3ECWQ1_P17WQ3TR_OFFSET 0x6B -+#define TANTOS_3G_P3ECWQ1_P17WQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECWQ1_P17WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P18WQ3TR' */ -+/* Description: 'Port 18 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P4ECWQ1_P18WQ3TR_OFFSET 0x8B -+#define TANTOS_3G_P4ECWQ1_P18WQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECWQ1_P18WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P19WQ3TR' */ -+/* Description: 'Port 19 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P5ECWQ1_P19WQ3TR_OFFSET 0xAB -+#define TANTOS_3G_P5ECWQ1_P19WQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECWQ1_P19WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for WFQ Q1 Register' */ -+/* Bit: 'P20WQ3TR' */ -+/* Description: 'Port 20 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P6ECWQ1_P20WQ3TR_OFFSET 0xCB -+#define TANTOS_3G_P6ECWQ1_P20WQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECWQ1_P20WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P0WQ3TR' */ -+/* Description: 'Port 0 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P0ECWQ0_P0WQ3TR_OFFSET 0x0C -+#define TANTOS_3G_P0ECWQ0_P0WQ3TR_SHIFT 0 -+#define TANTOS_3G_P0ECWQ0_P0WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P22WQ3TR' */ -+/* Description: 'Port 22 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P1ECWQ0_P22WQ3TR_OFFSET 0x2C -+#define TANTOS_3G_P1ECWQ0_P22WQ3TR_SHIFT 0 -+#define TANTOS_3G_P1ECWQ0_P22WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P23WQ3TR' */ -+/* Description: 'Port 23 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P2ECWQ0_P23WQ3TR_OFFSET 0x4C -+#define TANTOS_3G_P2ECWQ0_P23WQ3TR_SHIFT 0 -+#define TANTOS_3G_P2ECWQ0_P23WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P24WQ3TR' */ -+/* Description: 'Port 24 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P3ECWQ0_P24WQ3TR_OFFSET 0x6C -+#define TANTOS_3G_P3ECWQ0_P24WQ3TR_SHIFT 0 -+#define TANTOS_3G_P3ECWQ0_P24WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P25WQ3TR' */ -+/* Description: 'Port 25 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P4ECWQ0_P25WQ3TR_OFFSET 0x8C -+#define TANTOS_3G_P4ECWQ0_P25WQ3TR_SHIFT 0 -+#define TANTOS_3G_P4ECWQ0_P25WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P26WQ3TR' */ -+/* Description: 'Port 26 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P5ECWQ0_P26WQ3TR_OFFSET 0xAC -+#define TANTOS_3G_P5ECWQ0_P26WQ3TR_SHIFT 0 -+#define TANTOS_3G_P5ECWQ0_P26WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Egress Control for WFQ Q0 Register' */ -+/* Bit: 'P27WQ3TR' */ -+/* Description: 'Port 27 Egress Token R for WFQ Q3' */ -+#define TANTOS_3G_P6ECWQ0_P27WQ3TR_OFFSET 0xCC -+#define TANTOS_3G_P6ECWQ0_P27WQ3TR_SHIFT 0 -+#define TANTOS_3G_P6ECWQ0_P27WQ3TR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 0 Ingress Control Register' */ -+/* Bit: 'P0ITT' */ -+/* Description: 'Port 0 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P0ICR_P0ITT_OFFSET 0x0D -+#define TANTOS_3G_P0ICR_P0ITT_SHIFT 11 -+#define TANTOS_3G_P0ICR_P0ITT_SIZE 2 -+/* Bit: 'P0ITR' */ -+/* Description: 'Port 0 Ingress Token R' */ -+#define TANTOS_3G_P0ICR_P0ITR_OFFSET 0x0D -+#define TANTOS_3G_P0ICR_P0ITR_SHIFT 0 -+#define TANTOS_3G_P0ICR_P0ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 1 Ingress Control Register' */ -+/* Bit: 'P1ITT' */ -+/* Description: 'Port 1 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P1ICR_P1ITT_OFFSET 0x2D -+#define TANTOS_3G_P1ICR_P1ITT_SHIFT 11 -+#define TANTOS_3G_P1ICR_P1ITT_SIZE 2 -+/* Bit: 'P1ITR' */ -+/* Description: 'Port 1 Ingress Token R' */ -+#define TANTOS_3G_P1ICR_P1ITR_OFFSET 0x2D -+#define TANTOS_3G_P1ICR_P1ITR_SHIFT 0 -+#define TANTOS_3G_P1ICR_P1ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 2 Ingress Control Register' */ -+/* Bit: 'P2ITT' */ -+/* Description: 'Port 2 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P2ICR_P2ITT_OFFSET 0x4D -+#define TANTOS_3G_P2ICR_P2ITT_SHIFT 11 -+#define TANTOS_3G_P2ICR_P2ITT_SIZE 2 -+/* Bit: 'P2ITR' */ -+/* Description: 'Port 2 Ingress Token R' */ -+#define TANTOS_3G_P2ICR_P2ITR_OFFSET 0x4D -+#define TANTOS_3G_P2ICR_P2ITR_SHIFT 0 -+#define TANTOS_3G_P2ICR_P2ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 3 Ingress Control Register' */ -+/* Bit: 'P3ITT' */ -+/* Description: 'Port 3 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P3ICR_P3ITT_OFFSET 0x6D -+#define TANTOS_3G_P3ICR_P3ITT_SHIFT 11 -+#define TANTOS_3G_P3ICR_P3ITT_SIZE 2 -+/* Bit: 'P3ITR' */ -+/* Description: 'Port 3 Ingress Token R' */ -+#define TANTOS_3G_P3ICR_P3ITR_OFFSET 0x6D -+#define TANTOS_3G_P3ICR_P3ITR_SHIFT 0 -+#define TANTOS_3G_P3ICR_P3ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 4 Ingress Control Register' */ -+/* Bit: 'P4ITT' */ -+/* Description: 'Port 4 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P4ICR_P4ITT_OFFSET 0x8D -+#define TANTOS_3G_P4ICR_P4ITT_SHIFT 11 -+#define TANTOS_3G_P4ICR_P4ITT_SIZE 2 -+/* Bit: 'P4ITR' */ -+/* Description: 'Port 4 Ingress Token R' */ -+#define TANTOS_3G_P4ICR_P4ITR_OFFSET 0x8D -+#define TANTOS_3G_P4ICR_P4ITR_SHIFT 0 -+#define TANTOS_3G_P4ICR_P4ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 5 Ingress Control Register' */ -+/* Bit: 'P5ITT' */ -+/* Description: 'Port 5 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P5ICR_P5ITT_OFFSET 0xAD -+#define TANTOS_3G_P5ICR_P5ITT_SHIFT 11 -+#define TANTOS_3G_P5ICR_P5ITT_SIZE 2 -+/* Bit: 'P5ITR' */ -+/* Description: 'Port 5 Ingress Token R' */ -+#define TANTOS_3G_P5ICR_P5ITR_OFFSET 0xAD -+#define TANTOS_3G_P5ICR_P5ITR_SHIFT 0 -+#define TANTOS_3G_P5ICR_P5ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port 6 Ingress Control Register' */ -+/* Bit: 'P6ITT' */ -+/* Description: 'Port 6 Ingress/Egress Timer Tick T selection' */ -+#define TANTOS_3G_P6ICR_P6ITT_OFFSET 0xCD -+#define TANTOS_3G_P6ICR_P6ITT_SHIFT 11 -+#define TANTOS_3G_P6ICR_P6ITT_SIZE 2 -+/* Bit: 'P6ITR' */ -+/* Description: 'Port 6 Ingress Token R' */ -+#define TANTOS_3G_P6ICR_P6ITR_OFFSET 0xCD -+#define TANTOS_3G_P6ICR_P6ITR_SHIFT 0 -+#define TANTOS_3G_P6ICR_P6ITR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 0 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF0L_VV_OFFSET 0x10 -+#define TANTOS_3G_VF0L_VV_SHIFT 15 -+#define TANTOS_3G_VF0L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF0L_VP_OFFSET 0x10 -+#define TANTOS_3G_VF0L_VP_SHIFT 12 -+#define TANTOS_3G_VF0L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF0L_VID_OFFSET 0x10 -+#define TANTOS_3G_VF0L_VID_SHIFT 0 -+#define TANTOS_3G_VF0L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 1 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF1L_VV_OFFSET 0x12 -+#define TANTOS_3G_VF1L_VV_SHIFT 15 -+#define TANTOS_3G_VF1L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF1L_VP_OFFSET 0x12 -+#define TANTOS_3G_VF1L_VP_SHIFT 12 -+#define TANTOS_3G_VF1L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF1L_VID_OFFSET 0x12 -+#define TANTOS_3G_VF1L_VID_SHIFT 0 -+#define TANTOS_3G_VF1L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 2 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF2L_VV_OFFSET 0x14 -+#define TANTOS_3G_VF2L_VV_SHIFT 15 -+#define TANTOS_3G_VF2L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF2L_VP_OFFSET 0x14 -+#define TANTOS_3G_VF2L_VP_SHIFT 12 -+#define TANTOS_3G_VF2L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF2L_VID_OFFSET 0x14 -+#define TANTOS_3G_VF2L_VID_SHIFT 0 -+#define TANTOS_3G_VF2L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 3Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF3L_VV_OFFSET 0x16 -+#define TANTOS_3G_VF3L_VV_SHIFT 15 -+#define TANTOS_3G_VF3L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF3L_VP_OFFSET 0x16 -+#define TANTOS_3G_VF3L_VP_SHIFT 12 -+#define TANTOS_3G_VF3L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF3L_VID_OFFSET 0x16 -+#define TANTOS_3G_VF3L_VID_SHIFT 0 -+#define TANTOS_3G_VF3L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 4 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF4L_VV_OFFSET 0x18 -+#define TANTOS_3G_VF4L_VV_SHIFT 15 -+#define TANTOS_3G_VF4L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF4L_VP_OFFSET 0x18 -+#define TANTOS_3G_VF4L_VP_SHIFT 12 -+#define TANTOS_3G_VF4L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF4L_VID_OFFSET 0x18 -+#define TANTOS_3G_VF4L_VID_SHIFT 0 -+#define TANTOS_3G_VF4L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 5 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF5L_VV_OFFSET 0x1A -+#define TANTOS_3G_VF5L_VV_SHIFT 15 -+#define TANTOS_3G_VF5L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF5L_VP_OFFSET 0x1A -+#define TANTOS_3G_VF5L_VP_SHIFT 12 -+#define TANTOS_3G_VF5L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF5L_VID_OFFSET 0x1A -+#define TANTOS_3G_VF5L_VID_SHIFT 0 -+#define TANTOS_3G_VF5L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 6 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF6L_VV_OFFSET 0x1C -+#define TANTOS_3G_VF6L_VV_SHIFT 15 -+#define TANTOS_3G_VF6L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF6L_VP_OFFSET 0x1C -+#define TANTOS_3G_VF6L_VP_SHIFT 12 -+#define TANTOS_3G_VF6L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF6L_VID_OFFSET 0x1C -+#define TANTOS_3G_VF6L_VID_SHIFT 0 -+#define TANTOS_3G_VF6L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 7 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF7L_VV_OFFSET 0x1E -+#define TANTOS_3G_VF7L_VV_SHIFT 15 -+#define TANTOS_3G_VF7L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF7L_VP_OFFSET 0x1E -+#define TANTOS_3G_VF7L_VP_SHIFT 12 -+#define TANTOS_3G_VF7L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF7L_VID_OFFSET 0x1E -+#define TANTOS_3G_VF7L_VID_SHIFT 0 -+#define TANTOS_3G_VF7L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 8 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF8L_VV_OFFSET 0x30 -+#define TANTOS_3G_VF8L_VV_SHIFT 15 -+#define TANTOS_3G_VF8L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF8L_VP_OFFSET 0x30 -+#define TANTOS_3G_VF8L_VP_SHIFT 12 -+#define TANTOS_3G_VF8L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF8L_VID_OFFSET 0x30 -+#define TANTOS_3G_VF8L_VID_SHIFT 0 -+#define TANTOS_3G_VF8L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 9 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF9L_VV_OFFSET 0x32 -+#define TANTOS_3G_VF9L_VV_SHIFT 15 -+#define TANTOS_3G_VF9L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF9L_VP_OFFSET 0x32 -+#define TANTOS_3G_VF9L_VP_SHIFT 12 -+#define TANTOS_3G_VF9L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF9L_VID_OFFSET 0x32 -+#define TANTOS_3G_VF9L_VID_SHIFT 0 -+#define TANTOS_3G_VF9L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 10 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF10L_VV_OFFSET 0x34 -+#define TANTOS_3G_VF10L_VV_SHIFT 15 -+#define TANTOS_3G_VF10L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF10L_VP_OFFSET 0x34 -+#define TANTOS_3G_VF10L_VP_SHIFT 12 -+#define TANTOS_3G_VF10L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF10L_VID_OFFSET 0x34 -+#define TANTOS_3G_VF10L_VID_SHIFT 0 -+#define TANTOS_3G_VF10L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 11 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF11L_VV_OFFSET 0x36 -+#define TANTOS_3G_VF11L_VV_SHIFT 15 -+#define TANTOS_3G_VF11L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF11L_VP_OFFSET 0x36 -+#define TANTOS_3G_VF11L_VP_SHIFT 12 -+#define TANTOS_3G_VF11L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF11L_VID_OFFSET 0x36 -+#define TANTOS_3G_VF11L_VID_SHIFT 0 -+#define TANTOS_3G_VF11L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 12 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF12L_VV_OFFSET 0x38 -+#define TANTOS_3G_VF12L_VV_SHIFT 15 -+#define TANTOS_3G_VF12L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF12L_VP_OFFSET 0x38 -+#define TANTOS_3G_VF12L_VP_SHIFT 12 -+#define TANTOS_3G_VF12L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF12L_VID_OFFSET 0x38 -+#define TANTOS_3G_VF12L_VID_SHIFT 0 -+#define TANTOS_3G_VF12L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 13 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF13L_VV_OFFSET 0x3A -+#define TANTOS_3G_VF13L_VV_SHIFT 15 -+#define TANTOS_3G_VF13L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF13L_VP_OFFSET 0x3A -+#define TANTOS_3G_VF13L_VP_SHIFT 12 -+#define TANTOS_3G_VF13L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF13L_VID_OFFSET 0x3A -+#define TANTOS_3G_VF13L_VID_SHIFT 0 -+#define TANTOS_3G_VF13L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 14 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF14L_VV_OFFSET 0x3C -+#define TANTOS_3G_VF14L_VV_SHIFT 15 -+#define TANTOS_3G_VF14L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF14L_VP_OFFSET 0x3C -+#define TANTOS_3G_VF14L_VP_SHIFT 12 -+#define TANTOS_3G_VF14L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF14L_VID_OFFSET 0x3C -+#define TANTOS_3G_VF14L_VID_SHIFT 0 -+#define TANTOS_3G_VF14L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 15 Low' */ -+/* Bit: 'VV' */ -+/* Description: 'VLAN_Valid' */ -+#define TANTOS_3G_VF15L_VV_OFFSET 0x3E -+#define TANTOS_3G_VF15L_VV_SHIFT 15 -+#define TANTOS_3G_VF15L_VV_SIZE 1 -+/* Bit: 'VP' */ -+/* Description: 'VLAN PRI' */ -+#define TANTOS_3G_VF15L_VP_OFFSET 0x3E -+#define TANTOS_3G_VF15L_VP_SHIFT 12 -+#define TANTOS_3G_VF15L_VP_SIZE 3 -+/* Bit: 'VID' */ -+/* Description: 'VID' */ -+#define TANTOS_3G_VF15L_VID_OFFSET 0x3E -+#define TANTOS_3G_VF15L_VID_SHIFT 0 -+#define TANTOS_3G_VF15L_VID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 0 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF0H_FID_OFFSET 0x11 -+#define TANTOS_3G_VF0H_FID_SHIFT 14 -+#define TANTOS_3G_VF0H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF0H_TM_OFFSET 0x11 -+#define TANTOS_3G_VF0H_TM_SHIFT 7 -+#define TANTOS_3G_VF0H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF0H_M_OFFSET 0x11 -+#define TANTOS_3G_VF0H_M_SHIFT 0 -+#define TANTOS_3G_VF0H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 1 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF1H_FID_OFFSET 0x13 -+#define TANTOS_3G_VF1H_FID_SHIFT 14 -+#define TANTOS_3G_VF1H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF1H_TM_OFFSET 0x13 -+#define TANTOS_3G_VF1H_TM_SHIFT 7 -+#define TANTOS_3G_VF1H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF1H_M_OFFSET 0x13 -+#define TANTOS_3G_VF1H_M_SHIFT 0 -+#define TANTOS_3G_VF1H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 2 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF2H_FID_OFFSET 0x15 -+#define TANTOS_3G_VF2H_FID_SHIFT 14 -+#define TANTOS_3G_VF2H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF2H_TM_OFFSET 0x15 -+#define TANTOS_3G_VF2H_TM_SHIFT 7 -+#define TANTOS_3G_VF2H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF2H_M_OFFSET 0x15 -+#define TANTOS_3G_VF2H_M_SHIFT 0 -+#define TANTOS_3G_VF2H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 3 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF3H_FID_OFFSET 0x17 -+#define TANTOS_3G_VF3H_FID_SHIFT 14 -+#define TANTOS_3G_VF3H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF3H_TM_OFFSET 0x17 -+#define TANTOS_3G_VF3H_TM_SHIFT 7 -+#define TANTOS_3G_VF3H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF3H_M_OFFSET 0x17 -+#define TANTOS_3G_VF3H_M_SHIFT 0 -+#define TANTOS_3G_VF3H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 4 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF4H_FID_OFFSET 0x19 -+#define TANTOS_3G_VF4H_FID_SHIFT 14 -+#define TANTOS_3G_VF4H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF4H_TM_OFFSET 0x19 -+#define TANTOS_3G_VF4H_TM_SHIFT 7 -+#define TANTOS_3G_VF4H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF4H_M_OFFSET 0x19 -+#define TANTOS_3G_VF4H_M_SHIFT 0 -+#define TANTOS_3G_VF4H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 5 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF5H_FID_OFFSET 0x1B -+#define TANTOS_3G_VF5H_FID_SHIFT 14 -+#define TANTOS_3G_VF5H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF5H_TM_OFFSET 0x1B -+#define TANTOS_3G_VF5H_TM_SHIFT 7 -+#define TANTOS_3G_VF5H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF5H_M_OFFSET 0x1B -+#define TANTOS_3G_VF5H_M_SHIFT 0 -+#define TANTOS_3G_VF5H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 6 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF6H_FID_OFFSET 0x1D -+#define TANTOS_3G_VF6H_FID_SHIFT 14 -+#define TANTOS_3G_VF6H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF6H_TM_OFFSET 0x1D -+#define TANTOS_3G_VF6H_TM_SHIFT 7 -+#define TANTOS_3G_VF6H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF6H_M_OFFSET 0x1D -+#define TANTOS_3G_VF6H_M_SHIFT 0 -+#define TANTOS_3G_VF6H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 7 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF7H_FID_OFFSET 0x1F -+#define TANTOS_3G_VF7H_FID_SHIFT 14 -+#define TANTOS_3G_VF7H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF7H_TM_OFFSET 0x1F -+#define TANTOS_3G_VF7H_TM_SHIFT 7 -+#define TANTOS_3G_VF7H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF7H_M_OFFSET 0x1F -+#define TANTOS_3G_VF7H_M_SHIFT 0 -+#define TANTOS_3G_VF7H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 8 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF8H_FID_OFFSET 0x31 -+#define TANTOS_3G_VF8H_FID_SHIFT 14 -+#define TANTOS_3G_VF8H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF8H_TM_OFFSET 0x31 -+#define TANTOS_3G_VF8H_TM_SHIFT 7 -+#define TANTOS_3G_VF8H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF8H_M_OFFSET 0x31 -+#define TANTOS_3G_VF8H_M_SHIFT 0 -+#define TANTOS_3G_VF8H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 9 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF9H_FID_OFFSET 0x33 -+#define TANTOS_3G_VF9H_FID_SHIFT 14 -+#define TANTOS_3G_VF9H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF9H_TM_OFFSET 0x33 -+#define TANTOS_3G_VF9H_TM_SHIFT 7 -+#define TANTOS_3G_VF9H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF9H_M_OFFSET 0x33 -+#define TANTOS_3G_VF9H_M_SHIFT 0 -+#define TANTOS_3G_VF9H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 10 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF10H_FID_OFFSET 0x35 -+#define TANTOS_3G_VF10H_FID_SHIFT 14 -+#define TANTOS_3G_VF10H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF10H_TM_OFFSET 0x35 -+#define TANTOS_3G_VF10H_TM_SHIFT 7 -+#define TANTOS_3G_VF10H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF10H_M_OFFSET 0x35 -+#define TANTOS_3G_VF10H_M_SHIFT 0 -+#define TANTOS_3G_VF10H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 11 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF11H_FID_OFFSET 0x37 -+#define TANTOS_3G_VF11H_FID_SHIFT 14 -+#define TANTOS_3G_VF11H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF11H_TM_OFFSET 0x37 -+#define TANTOS_3G_VF11H_TM_SHIFT 7 -+#define TANTOS_3G_VF11H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF11H_M_OFFSET 0x37 -+#define TANTOS_3G_VF11H_M_SHIFT 0 -+#define TANTOS_3G_VF11H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 12 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF12H_FID_OFFSET 0x39 -+#define TANTOS_3G_VF12H_FID_SHIFT 14 -+#define TANTOS_3G_VF12H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF12H_TM_OFFSET 0x39 -+#define TANTOS_3G_VF12H_TM_SHIFT 7 -+#define TANTOS_3G_VF12H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF12H_M_OFFSET 0x39 -+#define TANTOS_3G_VF12H_M_SHIFT 0 -+#define TANTOS_3G_VF12H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 13 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF13H_FID_OFFSET 0x3B -+#define TANTOS_3G_VF13H_FID_SHIFT 14 -+#define TANTOS_3G_VF13H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF13H_TM_OFFSET 0x3B -+#define TANTOS_3G_VF13H_TM_SHIFT 7 -+#define TANTOS_3G_VF13H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF13H_M_OFFSET 0x3B -+#define TANTOS_3G_VF13H_M_SHIFT 0 -+#define TANTOS_3G_VF13H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 14 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF14H_FID_OFFSET 0x3D -+#define TANTOS_3G_VF14H_FID_SHIFT 14 -+#define TANTOS_3G_VF14H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF14H_TM_OFFSET 0x3D -+#define TANTOS_3G_VF14H_TM_SHIFT 7 -+#define TANTOS_3G_VF14H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF14H_M_OFFSET 0x3D -+#define TANTOS_3G_VF14H_M_SHIFT 0 -+#define TANTOS_3G_VF14H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Filter 15 High' */ -+/* Bit: 'FID' */ -+/* Description: 'FID' */ -+#define TANTOS_3G_VF15H_FID_OFFSET 0x3F -+#define TANTOS_3G_VF15H_FID_SHIFT 14 -+#define TANTOS_3G_VF15H_FID_SIZE 2 -+/* Bit: 'TM' */ -+/* Description: 'Tagged Member' */ -+#define TANTOS_3G_VF15H_TM_OFFSET 0x3F -+#define TANTOS_3G_VF15H_TM_SHIFT 7 -+#define TANTOS_3G_VF15H_TM_SIZE 7 -+/* Bit: 'M' */ -+/* Description: 'Member' */ -+#define TANTOS_3G_VF15H_M_OFFSET 0x3F -+#define TANTOS_3G_VF15H_M_SHIFT 0 -+#define TANTOS_3G_VF15H_M_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 0' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF0_VCET_OFFSET 0x50 -+#define TANTOS_3G_TF0_VCET_SHIFT 0 -+#define TANTOS_3G_TF0_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 1' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF1_VCET_OFFSET 0x51 -+#define TANTOS_3G_TF1_VCET_SHIFT 0 -+#define TANTOS_3G_TF1_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 2' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF2_VCET_OFFSET 0x52 -+#define TANTOS_3G_TF2_VCET_SHIFT 0 -+#define TANTOS_3G_TF2_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 3' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF3_VCET_OFFSET 0x53 -+#define TANTOS_3G_TF3_VCET_SHIFT 0 -+#define TANTOS_3G_TF3_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 4' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF4_VCET_OFFSET 0x54 -+#define TANTOS_3G_TF4_VCET_SHIFT 0 -+#define TANTOS_3G_TF4_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 5' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF5_VCET_OFFSET 0x55 -+#define TANTOS_3G_TF5_VCET_SHIFT 0 -+#define TANTOS_3G_TF5_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 6' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF6_VCET_OFFSET 0x56 -+#define TANTOS_3G_TF6_VCET_SHIFT 0 -+#define TANTOS_3G_TF6_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter 7' */ -+/* Bit: 'VCET' */ -+/* Description: 'Value Compared with Ether-Type' */ -+#define TANTOS_3G_TF7_VCET_OFFSET 0x57 -+#define TANTOS_3G_TF7_VCET_SHIFT 0 -+#define TANTOS_3G_TF7_VCET_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServ Mapping 0' */ -+/* Bit: 'PQ7' */ -+/* Description: 'Priority Queue 7' */ -+#define TANTOS_3G_DM0_PQ7_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ7_SHIFT 14 -+#define TANTOS_3G_DM0_PQ7_SIZE 2 -+/* Bit: 'PQ6' */ -+/* Description: 'Priority Queue 6' */ -+#define TANTOS_3G_DM0_PQ6_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ6_SHIFT 12 -+#define TANTOS_3G_DM0_PQ6_SIZE 2 -+/* Bit: 'PQ5' */ -+/* Description: 'Priority Queue 5' */ -+#define TANTOS_3G_DM0_PQ5_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ5_SHIFT 10 -+#define TANTOS_3G_DM0_PQ5_SIZE 2 -+/* Bit: 'PQ4' */ -+/* Description: 'Priority Queue 4' */ -+#define TANTOS_3G_DM0_PQ4_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ4_SHIFT 8 -+#define TANTOS_3G_DM0_PQ4_SIZE 2 -+/* Bit: 'PQ3' */ -+/* Description: 'Priority Queue 3' */ -+#define TANTOS_3G_DM0_PQ3_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ3_SHIFT 6 -+#define TANTOS_3G_DM0_PQ3_SIZE 2 -+/* Bit: 'PQ2' */ -+/* Description: 'Priority Queue 2' */ -+#define TANTOS_3G_DM0_PQ2_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ2_SHIFT 4 -+#define TANTOS_3G_DM0_PQ2_SIZE 2 -+/* Bit: 'PQ1' */ -+/* Description: 'Priority Queue 1' */ -+#define TANTOS_3G_DM0_PQ1_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ1_SHIFT 2 -+#define TANTOS_3G_DM0_PQ1_SIZE 2 -+/* Bit: 'PQ0' */ -+/* Description: 'Priority Queue 0' */ -+#define TANTOS_3G_DM0_PQ0_OFFSET 0x58 -+#define TANTOS_3G_DM0_PQ0_SHIFT 0 -+#define TANTOS_3G_DM0_PQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 1' */ -+/* Bit: 'PQF' */ -+/* Description: 'Priority Queue F' */ -+#define TANTOS_3G_DM1_PQF_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQF_SHIFT 14 -+#define TANTOS_3G_DM1_PQF_SIZE 2 -+/* Bit: 'PQE' */ -+/* Description: 'Priority Queue E' */ -+#define TANTOS_3G_DM1_PQE_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQE_SHIFT 12 -+#define TANTOS_3G_DM1_PQE_SIZE 2 -+/* Bit: 'PQD' */ -+/* Description: 'Priority Queue D' */ -+#define TANTOS_3G_DM1_PQD_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQD_SHIFT 10 -+#define TANTOS_3G_DM1_PQD_SIZE 2 -+/* Bit: 'PQC' */ -+/* Description: 'Priority Queue C' */ -+#define TANTOS_3G_DM1_PQC_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQC_SHIFT 8 -+#define TANTOS_3G_DM1_PQC_SIZE 2 -+/* Bit: 'PQB' */ -+/* Description: 'Priority Queue B' */ -+#define TANTOS_3G_DM1_PQB_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQB_SHIFT 6 -+#define TANTOS_3G_DM1_PQB_SIZE 2 -+/* Bit: 'PQA' */ -+/* Description: 'Priority Queue A' */ -+#define TANTOS_3G_DM1_PQA_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQA_SHIFT 4 -+#define TANTOS_3G_DM1_PQA_SIZE 2 -+/* Bit: 'PQ9' */ -+/* Description: 'Priority Queue 9' */ -+#define TANTOS_3G_DM1_PQ9_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQ9_SHIFT 2 -+#define TANTOS_3G_DM1_PQ9_SIZE 2 -+/* Bit: 'PQ8' */ -+/* Description: 'Priority Queue 8' */ -+#define TANTOS_3G_DM1_PQ8_OFFSET 0x59 -+#define TANTOS_3G_DM1_PQ8_SHIFT 0 -+#define TANTOS_3G_DM1_PQ8_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 2' */ -+/* Bit: 'PQ17' */ -+/* Description: 'Priority Queue 17' */ -+#define TANTOS_3G_DM2_PQ17_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ17_SHIFT 14 -+#define TANTOS_3G_DM2_PQ17_SIZE 2 -+/* Bit: 'PQ16' */ -+/* Description: 'Priority Queue 16' */ -+#define TANTOS_3G_DM2_PQ16_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ16_SHIFT 12 -+#define TANTOS_3G_DM2_PQ16_SIZE 2 -+/* Bit: 'PQ15' */ -+/* Description: 'Priority Queue 15' */ -+#define TANTOS_3G_DM2_PQ15_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ15_SHIFT 10 -+#define TANTOS_3G_DM2_PQ15_SIZE 2 -+/* Bit: 'PQ14' */ -+/* Description: 'Priority Queue 14' */ -+#define TANTOS_3G_DM2_PQ14_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ14_SHIFT 8 -+#define TANTOS_3G_DM2_PQ14_SIZE 2 -+/* Bit: 'PQ13' */ -+/* Description: 'Priority Queue 13' */ -+#define TANTOS_3G_DM2_PQ13_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ13_SHIFT 6 -+#define TANTOS_3G_DM2_PQ13_SIZE 2 -+/* Bit: 'PQ12' */ -+/* Description: 'Priority Queue 12' */ -+#define TANTOS_3G_DM2_PQ12_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ12_SHIFT 4 -+#define TANTOS_3G_DM2_PQ12_SIZE 2 -+/* Bit: 'PQ11' */ -+/* Description: 'Priority Queue 11' */ -+#define TANTOS_3G_DM2_PQ11_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ11_SHIFT 2 -+#define TANTOS_3G_DM2_PQ11_SIZE 2 -+/* Bit: 'PQ10' */ -+/* Description: 'Priority Queue 10' */ -+#define TANTOS_3G_DM2_PQ10_OFFSET 0x5A -+#define TANTOS_3G_DM2_PQ10_SHIFT 0 -+#define TANTOS_3G_DM2_PQ10_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 3' */ -+/* Bit: 'PQ1F' */ -+/* Description: 'Priority Queue 1F' */ -+#define TANTOS_3G_DM3_PQ1F_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1F_SHIFT 14 -+#define TANTOS_3G_DM3_PQ1F_SIZE 2 -+/* Bit: 'PQ1E' */ -+/* Description: 'Priority Queue 1E' */ -+#define TANTOS_3G_DM3_PQ1E_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1E_SHIFT 12 -+#define TANTOS_3G_DM3_PQ1E_SIZE 2 -+/* Bit: 'PQ1D' */ -+/* Description: 'Priority Queue 1D' */ -+#define TANTOS_3G_DM3_PQ1D_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1D_SHIFT 10 -+#define TANTOS_3G_DM3_PQ1D_SIZE 2 -+/* Bit: 'PQ1C' */ -+/* Description: 'Priority Queue 1C' */ -+#define TANTOS_3G_DM3_PQ1C_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1C_SHIFT 8 -+#define TANTOS_3G_DM3_PQ1C_SIZE 2 -+/* Bit: 'PQ1B' */ -+/* Description: 'Priority Queue 1B' */ -+#define TANTOS_3G_DM3_PQ1B_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1B_SHIFT 6 -+#define TANTOS_3G_DM3_PQ1B_SIZE 2 -+/* Bit: 'PQ1A' */ -+/* Description: 'Priority Queue 1A' */ -+#define TANTOS_3G_DM3_PQ1A_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ1A_SHIFT 4 -+#define TANTOS_3G_DM3_PQ1A_SIZE 2 -+/* Bit: 'PQ19' */ -+/* Description: 'Priority Queue 19' */ -+#define TANTOS_3G_DM3_PQ19_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ19_SHIFT 2 -+#define TANTOS_3G_DM3_PQ19_SIZE 2 -+/* Bit: 'PQ18' */ -+/* Description: 'Priority Queue 18' */ -+#define TANTOS_3G_DM3_PQ18_OFFSET 0x5B -+#define TANTOS_3G_DM3_PQ18_SHIFT 0 -+#define TANTOS_3G_DM3_PQ18_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 4' */ -+/* Bit: 'PQ27' */ -+/* Description: 'Priority Queue 27' */ -+#define TANTOS_3G_DM4_PQ27_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ27_SHIFT 14 -+#define TANTOS_3G_DM4_PQ27_SIZE 2 -+/* Bit: 'PQ26' */ -+/* Description: 'Priority Queue 26' */ -+#define TANTOS_3G_DM4_PQ26_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ26_SHIFT 12 -+#define TANTOS_3G_DM4_PQ26_SIZE 2 -+/* Bit: 'PQ25' */ -+/* Description: 'Priority Queue 25' */ -+#define TANTOS_3G_DM4_PQ25_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ25_SHIFT 10 -+#define TANTOS_3G_DM4_PQ25_SIZE 2 -+/* Bit: 'PQ24' */ -+/* Description: 'Priority Queue 24' */ -+#define TANTOS_3G_DM4_PQ24_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ24_SHIFT 8 -+#define TANTOS_3G_DM4_PQ24_SIZE 2 -+/* Bit: 'PQ23' */ -+/* Description: 'Priority Queue 23' */ -+#define TANTOS_3G_DM4_PQ23_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ23_SHIFT 6 -+#define TANTOS_3G_DM4_PQ23_SIZE 2 -+/* Bit: 'PQ22' */ -+/* Description: 'Priority Queue 22' */ -+#define TANTOS_3G_DM4_PQ22_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ22_SHIFT 4 -+#define TANTOS_3G_DM4_PQ22_SIZE 2 -+/* Bit: 'PQ21' */ -+/* Description: 'Priority Queue 21' */ -+#define TANTOS_3G_DM4_PQ21_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ21_SHIFT 2 -+#define TANTOS_3G_DM4_PQ21_SIZE 2 -+/* Bit: 'PQ20' */ -+/* Description: 'Priority Queue 20' */ -+#define TANTOS_3G_DM4_PQ20_OFFSET 0x5C -+#define TANTOS_3G_DM4_PQ20_SHIFT 0 -+#define TANTOS_3G_DM4_PQ20_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 5' */ -+/* Bit: 'PQ2F' */ -+/* Description: 'Priority Queue 2F' */ -+#define TANTOS_3G_DM5_PQ2F_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2F_SHIFT 14 -+#define TANTOS_3G_DM5_PQ2F_SIZE 2 -+/* Bit: 'PQ2E' */ -+/* Description: 'Priority Queue 2E' */ -+#define TANTOS_3G_DM5_PQ2E_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2E_SHIFT 12 -+#define TANTOS_3G_DM5_PQ2E_SIZE 2 -+/* Bit: 'PQ2D' */ -+/* Description: 'Priority Queue 2D' */ -+#define TANTOS_3G_DM5_PQ2D_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2D_SHIFT 10 -+#define TANTOS_3G_DM5_PQ2D_SIZE 2 -+/* Bit: 'PQ2C' */ -+/* Description: 'Priority Queue 2C' */ -+#define TANTOS_3G_DM5_PQ2C_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2C_SHIFT 8 -+#define TANTOS_3G_DM5_PQ2C_SIZE 2 -+/* Bit: 'PQ2B' */ -+/* Description: 'Priority Queue 2B' */ -+#define TANTOS_3G_DM5_PQ2B_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2B_SHIFT 6 -+#define TANTOS_3G_DM5_PQ2B_SIZE 2 -+/* Bit: 'PQ2A' */ -+/* Description: 'Priority Queue 2A' */ -+#define TANTOS_3G_DM5_PQ2A_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ2A_SHIFT 4 -+#define TANTOS_3G_DM5_PQ2A_SIZE 2 -+/* Bit: 'PQ29' */ -+/* Description: 'Priority Queue 29' */ -+#define TANTOS_3G_DM5_PQ29_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ29_SHIFT 2 -+#define TANTOS_3G_DM5_PQ29_SIZE 2 -+/* Bit: 'PQ28' */ -+/* Description: 'Priority Queue 28' */ -+#define TANTOS_3G_DM5_PQ28_OFFSET 0x5D -+#define TANTOS_3G_DM5_PQ28_SHIFT 0 -+#define TANTOS_3G_DM5_PQ28_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 6' */ -+/* Bit: 'PQ37' */ -+/* Description: 'Priority Queue 37' */ -+#define TANTOS_3G_DM6_PQ37_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ37_SHIFT 14 -+#define TANTOS_3G_DM6_PQ37_SIZE 2 -+/* Bit: 'PQ36' */ -+/* Description: 'Priority Queue 36' */ -+#define TANTOS_3G_DM6_PQ36_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ36_SHIFT 12 -+#define TANTOS_3G_DM6_PQ36_SIZE 2 -+/* Bit: 'PQ35' */ -+/* Description: 'Priority Queue 35' */ -+#define TANTOS_3G_DM6_PQ35_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ35_SHIFT 10 -+#define TANTOS_3G_DM6_PQ35_SIZE 2 -+/* Bit: 'PQ34' */ -+/* Description: 'Priority Queue 34' */ -+#define TANTOS_3G_DM6_PQ34_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ34_SHIFT 8 -+#define TANTOS_3G_DM6_PQ34_SIZE 2 -+/* Bit: 'PQ33' */ -+/* Description: 'Priority Queue 33' */ -+#define TANTOS_3G_DM6_PQ33_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ33_SHIFT 6 -+#define TANTOS_3G_DM6_PQ33_SIZE 2 -+/* Bit: 'PQ32' */ -+/* Description: 'Priority Queue 32' */ -+#define TANTOS_3G_DM6_PQ32_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ32_SHIFT 4 -+#define TANTOS_3G_DM6_PQ32_SIZE 2 -+/* Bit: 'PQ31' */ -+/* Description: 'Priority Queue 31' */ -+#define TANTOS_3G_DM6_PQ31_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ31_SHIFT 2 -+#define TANTOS_3G_DM6_PQ31_SIZE 2 -+/* Bit: 'PQ30' */ -+/* Description: 'Priority Queue 30' */ -+#define TANTOS_3G_DM6_PQ30_OFFSET 0x5E -+#define TANTOS_3G_DM6_PQ30_SHIFT 0 -+#define TANTOS_3G_DM6_PQ30_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'DiffServMapping 7' */ -+/* Bit: 'PQ3F' */ -+/* Description: 'Priority Queue 3F' */ -+#define TANTOS_3G_DM7_PQ3F_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3F_SHIFT 14 -+#define TANTOS_3G_DM7_PQ3F_SIZE 2 -+/* Bit: 'PQ3E' */ -+/* Description: 'Priority Queue 3E' */ -+#define TANTOS_3G_DM7_PQ3E_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3E_SHIFT 12 -+#define TANTOS_3G_DM7_PQ3E_SIZE 2 -+/* Bit: 'PQ3D' */ -+/* Description: 'Priority Queue 3D' */ -+#define TANTOS_3G_DM7_PQ3D_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3D_SHIFT 10 -+#define TANTOS_3G_DM7_PQ3D_SIZE 2 -+/* Bit: 'PQ3C' */ -+/* Description: 'Priority Queue 3C' */ -+#define TANTOS_3G_DM7_PQ3C_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3C_SHIFT 8 -+#define TANTOS_3G_DM7_PQ3C_SIZE 2 -+/* Bit: 'PQ3B' */ -+/* Description: 'Priority Queue 3B' */ -+#define TANTOS_3G_DM7_PQ3B_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3B_SHIFT 6 -+#define TANTOS_3G_DM7_PQ3B_SIZE 2 -+/* Bit: 'PQ3A' */ -+/* Description: 'Priority Queue 3A' */ -+#define TANTOS_3G_DM7_PQ3A_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ3A_SHIFT 4 -+#define TANTOS_3G_DM7_PQ3A_SIZE 2 -+/* Bit: 'PQ39' */ -+/* Description: 'Priority Queue 39' */ -+#define TANTOS_3G_DM7_PQ39_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ39_SHIFT 2 -+#define TANTOS_3G_DM7_PQ39_SIZE 2 -+/* Bit: 'PQ38' */ -+/* Description: 'Priority Queue 38' */ -+#define TANTOS_3G_DM7_PQ38_OFFSET 0x5F -+#define TANTOS_3G_DM7_PQ38_SHIFT 0 -+#define TANTOS_3G_DM7_PQ38_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 0' */ -+/* Bit: 'BASEPT0' */ -+/* Description: 'Base Port number 0' */ -+#define TANTOS_3G_TUPF0_BASEPT0_OFFSET 0x70 -+#define TANTOS_3G_TUPF0_BASEPT0_SHIFT 0 -+#define TANTOS_3G_TUPF0_BASEPT0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 1' */ -+/* Bit: 'BASEPT1' */ -+/* Description: 'Base Port number 1' */ -+#define TANTOS_3G_TUPF1_BASEPT1_OFFSET 0x72 -+#define TANTOS_3G_TUPF1_BASEPT1_SHIFT 0 -+#define TANTOS_3G_TUPF1_BASEPT1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 2' */ -+/* Bit: 'BASEPT2' */ -+/* Description: 'Base Port number 2' */ -+#define TANTOS_3G_TUPF2_BASEPT2_OFFSET 0x74 -+#define TANTOS_3G_TUPF2_BASEPT2_SHIFT 0 -+#define TANTOS_3G_TUPF2_BASEPT2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 3' */ -+/* Bit: 'BASEPT3' */ -+/* Description: 'Base Port number 3' */ -+#define TANTOS_3G_TUPF3_BASEPT3_OFFSET 0x76 -+#define TANTOS_3G_TUPF3_BASEPT3_SHIFT 0 -+#define TANTOS_3G_TUPF3_BASEPT3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 4' */ -+/* Bit: 'BASEPT4' */ -+/* Description: 'Base Port number 4' */ -+#define TANTOS_3G_TUPF4_BASEPT4_OFFSET 0x78 -+#define TANTOS_3G_TUPF4_BASEPT4_SHIFT 0 -+#define TANTOS_3G_TUPF4_BASEPT4_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 5' */ -+/* Bit: 'BASEPT5' */ -+/* Description: 'Base Port number 5' */ -+#define TANTOS_3G_TUPF5_BASEPT5_OFFSET 0x7A -+#define TANTOS_3G_TUPF5_BASEPT5_SHIFT 0 -+#define TANTOS_3G_TUPF5_BASEPT5_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 6' */ -+/* Bit: 'BASEPT6' */ -+/* Description: 'Base Port number 6' */ -+#define TANTOS_3G_TUPF6_BASEPT6_OFFSET 0x7C -+#define TANTOS_3G_TUPF6_BASEPT6_SHIFT 0 -+#define TANTOS_3G_TUPF6_BASEPT6_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Filter 7' */ -+/* Bit: 'BASEPT7' */ -+/* Description: 'Base Port number 7' */ -+#define TANTOS_3G_TUPF7_BASEPT7_OFFSET 0x7E -+#define TANTOS_3G_TUPF7_BASEPT7_SHIFT 0 -+#define TANTOS_3G_TUPF7_BASEPT7_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 0' */ -+/* Bit: 'ATUF0' */ -+/* Description: 'Action for TCP/UDP Port Filter 0' */ -+#define TANTOS_3G_TUPR0_ATUF0_OFFSET 0x71 -+#define TANTOS_3G_TUPR0_ATUF0_SHIFT 12 -+#define TANTOS_3G_TUPR0_ATUF0_SIZE 2 -+/* Bit: 'TUPF0' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 0' */ -+#define TANTOS_3G_TUPR0_TUPF0_OFFSET 0x71 -+#define TANTOS_3G_TUPR0_TUPF0_SHIFT 10 -+#define TANTOS_3G_TUPR0_TUPF0_SIZE 2 -+/* Bit: 'COMP0' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR0_COMP0_OFFSET 0x71 -+#define TANTOS_3G_TUPR0_COMP0_SHIFT 8 -+#define TANTOS_3G_TUPR0_COMP0_SIZE 2 -+/* Bit: 'PRANGE0' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR0_PRANGE0_OFFSET 0x71 -+#define TANTOS_3G_TUPR0_PRANGE0_SHIFT 0 -+#define TANTOS_3G_TUPR0_PRANGE0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 1' */ -+/* Bit: 'ATUF1' */ -+/* Description: 'Action for TCP/UDP Port Filter 1' */ -+#define TANTOS_3G_TUPR1_ATUF1_OFFSET 0x73 -+#define TANTOS_3G_TUPR1_ATUF1_SHIFT 12 -+#define TANTOS_3G_TUPR1_ATUF1_SIZE 2 -+/* Bit: 'TUPF1' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 1' */ -+#define TANTOS_3G_TUPR1_TUPF1_OFFSET 0x73 -+#define TANTOS_3G_TUPR1_TUPF1_SHIFT 10 -+#define TANTOS_3G_TUPR1_TUPF1_SIZE 2 -+/* Bit: 'COMP1' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR1_COMP1_OFFSET 0x73 -+#define TANTOS_3G_TUPR1_COMP1_SHIFT 8 -+#define TANTOS_3G_TUPR1_COMP1_SIZE 2 -+/* Bit: 'PRANGE1' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR1_PRANGE1_OFFSET 0x73 -+#define TANTOS_3G_TUPR1_PRANGE1_SHIFT 0 -+#define TANTOS_3G_TUPR1_PRANGE1_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 2' */ -+/* Bit: 'ATUF2' */ -+/* Description: 'Action for TCP/UDP Port Filter 2' */ -+#define TANTOS_3G_TUPR2_ATUF2_OFFSET 0x75 -+#define TANTOS_3G_TUPR2_ATUF2_SHIFT 12 -+#define TANTOS_3G_TUPR2_ATUF2_SIZE 2 -+/* Bit: 'TUPF2' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 2' */ -+#define TANTOS_3G_TUPR2_TUPF2_OFFSET 0x75 -+#define TANTOS_3G_TUPR2_TUPF2_SHIFT 10 -+#define TANTOS_3G_TUPR2_TUPF2_SIZE 2 -+/* Bit: 'COMP2' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR2_COMP2_OFFSET 0x75 -+#define TANTOS_3G_TUPR2_COMP2_SHIFT 8 -+#define TANTOS_3G_TUPR2_COMP2_SIZE 2 -+/* Bit: 'PRANGE2' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR2_PRANGE2_OFFSET 0x75 -+#define TANTOS_3G_TUPR2_PRANGE2_SHIFT 0 -+#define TANTOS_3G_TUPR2_PRANGE2_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 3' */ -+/* Bit: 'ATUF3' */ -+/* Description: 'Action for TCP/UDP Port Filter 3' */ -+#define TANTOS_3G_TUPR3_ATUF3_OFFSET 0x77 -+#define TANTOS_3G_TUPR3_ATUF3_SHIFT 12 -+#define TANTOS_3G_TUPR3_ATUF3_SIZE 2 -+/* Bit: 'TUPF3' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 3' */ -+#define TANTOS_3G_TUPR3_TUPF3_OFFSET 0x77 -+#define TANTOS_3G_TUPR3_TUPF3_SHIFT 10 -+#define TANTOS_3G_TUPR3_TUPF3_SIZE 2 -+/* Bit: 'COMP3' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR3_COMP3_OFFSET 0x77 -+#define TANTOS_3G_TUPR3_COMP3_SHIFT 8 -+#define TANTOS_3G_TUPR3_COMP3_SIZE 2 -+/* Bit: 'PRANGE3' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR3_PRANGE3_OFFSET 0x77 -+#define TANTOS_3G_TUPR3_PRANGE3_SHIFT 0 -+#define TANTOS_3G_TUPR3_PRANGE3_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 4' */ -+/* Bit: 'ATUF4' */ -+/* Description: 'Action for TCP/UDP Port Filter 4' */ -+#define TANTOS_3G_TUPR4_ATUF4_OFFSET 0x79 -+#define TANTOS_3G_TUPR4_ATUF4_SHIFT 12 -+#define TANTOS_3G_TUPR4_ATUF4_SIZE 2 -+/* Bit: 'TUPF4' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 4' */ -+#define TANTOS_3G_TUPR4_TUPF4_OFFSET 0x79 -+#define TANTOS_3G_TUPR4_TUPF4_SHIFT 10 -+#define TANTOS_3G_TUPR4_TUPF4_SIZE 2 -+/* Bit: 'COMP4' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR4_COMP4_OFFSET 0x79 -+#define TANTOS_3G_TUPR4_COMP4_SHIFT 8 -+#define TANTOS_3G_TUPR4_COMP4_SIZE 2 -+/* Bit: 'PRANGE4' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR4_PRANGE4_OFFSET 0x79 -+#define TANTOS_3G_TUPR4_PRANGE4_SHIFT 0 -+#define TANTOS_3G_TUPR4_PRANGE4_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 5' */ -+/* Bit: 'ATUF5' */ -+/* Description: 'Action for TCP/UDP Port Filter 5' */ -+#define TANTOS_3G_TUPR5_ATUF5_OFFSET 0x7B -+#define TANTOS_3G_TUPR5_ATUF5_SHIFT 12 -+#define TANTOS_3G_TUPR5_ATUF5_SIZE 2 -+/* Bit: 'TUPF5' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 5' */ -+#define TANTOS_3G_TUPR5_TUPF5_OFFSET 0x7B -+#define TANTOS_3G_TUPR5_TUPF5_SHIFT 10 -+#define TANTOS_3G_TUPR5_TUPF5_SIZE 2 -+/* Bit: 'COMP5' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR5_COMP5_OFFSET 0x7B -+#define TANTOS_3G_TUPR5_COMP5_SHIFT 8 -+#define TANTOS_3G_TUPR5_COMP5_SIZE 2 -+/* Bit: 'PRANGE5' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR5_PRANGE5_OFFSET 0x7B -+#define TANTOS_3G_TUPR5_PRANGE5_SHIFT 0 -+#define TANTOS_3G_TUPR5_PRANGE5_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 6' */ -+/* Bit: 'ATUF6' */ -+/* Description: 'Action for TCP/UDP Port Filter 6' */ -+#define TANTOS_3G_TUPR6_ATUF6_OFFSET 0x7D -+#define TANTOS_3G_TUPR6_ATUF6_SHIFT 12 -+#define TANTOS_3G_TUPR6_ATUF6_SIZE 2 -+/* Bit: 'TUPF6' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 6' */ -+#define TANTOS_3G_TUPR6_TUPF6_OFFSET 0x7D -+#define TANTOS_3G_TUPR6_TUPF6_SHIFT 10 -+#define TANTOS_3G_TUPR6_TUPF6_SIZE 2 -+/* Bit: 'COMP6' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR6_COMP6_OFFSET 0x7D -+#define TANTOS_3G_TUPR6_COMP6_SHIFT 8 -+#define TANTOS_3G_TUPR6_COMP6_SIZE 2 -+/* Bit: 'PRANGE6' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR6_PRANGE6_OFFSET 0x7D -+#define TANTOS_3G_TUPR6_PRANGE6_SHIFT 0 -+#define TANTOS_3G_TUPR6_PRANGE6_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'TCP/UDP Port Range 7' */ -+/* Bit: 'ATUF7' */ -+/* Description: 'Action for TCP/UDP Port Filter 7' */ -+#define TANTOS_3G_TUPR7_ATUF7_OFFSET 0x7F -+#define TANTOS_3G_TUPR7_ATUF7_SHIFT 12 -+#define TANTOS_3G_TUPR7_ATUF7_SIZE 2 -+/* Bit: 'TUPF7' */ -+/* Description: 'TCP/UDP PRI for TCP/UDP Port Filter 7' */ -+#define TANTOS_3G_TUPR7_TUPF7_OFFSET 0x7F -+#define TANTOS_3G_TUPR7_TUPF7_SHIFT 10 -+#define TANTOS_3G_TUPR7_TUPF7_SIZE 2 -+/* Bit: 'COMP7' */ -+/* Description: 'Compare TCP/UDP Source Port or Destination Port' */ -+#define TANTOS_3G_TUPR7_COMP7_OFFSET 0x7F -+#define TANTOS_3G_TUPR7_COMP7_SHIFT 8 -+#define TANTOS_3G_TUPR7_COMP7_SIZE 2 -+/* Bit: 'PRANGE7' */ -+/* Description: 'Port Range in TCP/UDP' */ -+#define TANTOS_3G_TUPR7_PRANGE7_OFFSET 0x7F -+#define TANTOS_3G_TUPR7_PRANGE7_SHIFT 0 -+#define TANTOS_3G_TUPR7_PRANGE7_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserved DA(0180C2000001~0180C2000000) control register' */ -+/* Bit: 'RA01_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_VALID_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_VALID_SHIFT 15 -+#define TANTOS_3G_RA_01_00_RA01_VALID_SIZE 1 -+/* Bit: 'RA01_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_SPAN_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_01_00_RA01_SPAN_SIZE 1 -+/* Bit: 'RA01_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_MG_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_MG_SHIFT 13 -+#define TANTOS_3G_RA_01_00_RA01_MG_SIZE 1 -+/* Bit: 'RA01_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_CV_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_CV_SHIFT 12 -+#define TANTOS_3G_RA_01_00_RA01_CV_SIZE 1 -+/* Bit: 'RA01_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_TXTAG_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_01_00_RA01_TXTAG_SIZE 2 -+/* Bit: 'RA01_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_01_00_RA01_ACT_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA01_ACT_SHIFT 8 -+#define TANTOS_3G_RA_01_00_RA01_ACT_SIZE 2 -+/* Bit: 'RA00_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_VALID_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_VALID_SHIFT 7 -+#define TANTOS_3G_RA_01_00_RA00_VALID_SIZE 1 -+/* Bit: 'RA00_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_SPAN_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_01_00_RA00_SPAN_SIZE 1 -+/* Bit: 'RA00_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_MG_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_MG_SHIFT 5 -+#define TANTOS_3G_RA_01_00_RA00_MG_SIZE 1 -+/* Bit: 'RA00_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_CV_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_CV_SHIFT 4 -+#define TANTOS_3G_RA_01_00_RA00_CV_SIZE 1 -+/* Bit: 'RA00_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_TXTAG_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_01_00_RA00_TXTAG_SIZE 2 -+/* Bit: 'RA00_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_01_00_RA00_ACT_OFFSET 0x90 -+#define TANTOS_3G_RA_01_00_RA00_ACT_SHIFT 0 -+#define TANTOS_3G_RA_01_00_RA00_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000003~0180C2000002' */ -+/* Bit: 'RA23_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_VALID_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_VALID_SHIFT 15 -+#define TANTOS_3G_RA_03_02_RA23_VALID_SIZE 1 -+/* Bit: 'RA23_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_SPAN_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_03_02_RA23_SPAN_SIZE 1 -+/* Bit: 'RA23_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_MG_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_MG_SHIFT 13 -+#define TANTOS_3G_RA_03_02_RA23_MG_SIZE 1 -+/* Bit: 'RA23_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_CV_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_CV_SHIFT 12 -+#define TANTOS_3G_RA_03_02_RA23_CV_SIZE 1 -+/* Bit: 'RA23_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_TXTAG_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_03_02_RA23_TXTAG_SIZE 2 -+/* Bit: 'RA23_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_03_02_RA23_ACT_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA23_ACT_SHIFT 8 -+#define TANTOS_3G_RA_03_02_RA23_ACT_SIZE 2 -+/* Bit: 'RA20_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_VALID_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_VALID_SHIFT 7 -+#define TANTOS_3G_RA_03_02_RA20_VALID_SIZE 1 -+/* Bit: 'RA20_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_SPAN_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_03_02_RA20_SPAN_SIZE 1 -+/* Bit: 'RA20_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_MG_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_MG_SHIFT 5 -+#define TANTOS_3G_RA_03_02_RA20_MG_SIZE 1 -+/* Bit: 'RA20_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_CV_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_CV_SHIFT 4 -+#define TANTOS_3G_RA_03_02_RA20_CV_SIZE 1 -+/* Bit: 'RA20_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_TXTAG_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_03_02_RA20_TXTAG_SIZE 2 -+/* Bit: 'RA20_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_03_02_RA20_ACT_OFFSET 0x91 -+#define TANTOS_3G_RA_03_02_RA20_ACT_SHIFT 0 -+#define TANTOS_3G_RA_03_02_RA20_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000005~0180C2000004' */ -+/* Bit: 'RA45_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_VALID_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_VALID_SHIFT 15 -+#define TANTOS_3G_RA_05_04_RA45_VALID_SIZE 1 -+/* Bit: 'RA45_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_SPAN_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_05_04_RA45_SPAN_SIZE 1 -+/* Bit: 'RA45_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_MG_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_MG_SHIFT 13 -+#define TANTOS_3G_RA_05_04_RA45_MG_SIZE 1 -+/* Bit: 'RA45_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_CV_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_CV_SHIFT 12 -+#define TANTOS_3G_RA_05_04_RA45_CV_SIZE 1 -+/* Bit: 'RA45_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_TXTAG_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_05_04_RA45_TXTAG_SIZE 2 -+/* Bit: 'RA45_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_05_04_RA45_ACT_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA45_ACT_SHIFT 8 -+#define TANTOS_3G_RA_05_04_RA45_ACT_SIZE 2 -+/* Bit: 'RA40_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_VALID_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_VALID_SHIFT 7 -+#define TANTOS_3G_RA_05_04_RA40_VALID_SIZE 1 -+/* Bit: 'RA40_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_SPAN_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_05_04_RA40_SPAN_SIZE 1 -+/* Bit: 'RA40_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_MG_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_MG_SHIFT 5 -+#define TANTOS_3G_RA_05_04_RA40_MG_SIZE 1 -+/* Bit: 'RA40_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_CV_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_CV_SHIFT 4 -+#define TANTOS_3G_RA_05_04_RA40_CV_SIZE 1 -+/* Bit: 'RA40_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_TXTAG_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_05_04_RA40_TXTAG_SIZE 2 -+/* Bit: 'RA40_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_05_04_RA40_ACT_OFFSET 0x92 -+#define TANTOS_3G_RA_05_04_RA40_ACT_SHIFT 0 -+#define TANTOS_3G_RA_05_04_RA40_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000007~0180C2000006' */ -+/* Bit: 'RA67_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_VALID_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_VALID_SHIFT 15 -+#define TANTOS_3G_RA_07_06_RA67_VALID_SIZE 1 -+/* Bit: 'RA67_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_SPAN_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_07_06_RA67_SPAN_SIZE 1 -+/* Bit: 'RA67_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_MG_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_MG_SHIFT 13 -+#define TANTOS_3G_RA_07_06_RA67_MG_SIZE 1 -+/* Bit: 'RA67_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_CV_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_CV_SHIFT 12 -+#define TANTOS_3G_RA_07_06_RA67_CV_SIZE 1 -+/* Bit: 'RA67_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_TXTAG_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_07_06_RA67_TXTAG_SIZE 2 -+/* Bit: 'RA67_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_07_06_RA67_ACT_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA67_ACT_SHIFT 8 -+#define TANTOS_3G_RA_07_06_RA67_ACT_SIZE 2 -+/* Bit: 'RA60_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_VALID_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_VALID_SHIFT 7 -+#define TANTOS_3G_RA_07_06_RA60_VALID_SIZE 1 -+/* Bit: 'RA60_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_SPAN_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_07_06_RA60_SPAN_SIZE 1 -+/* Bit: 'RA60_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_MG_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_MG_SHIFT 5 -+#define TANTOS_3G_RA_07_06_RA60_MG_SIZE 1 -+/* Bit: 'RA60_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_CV_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_CV_SHIFT 4 -+#define TANTOS_3G_RA_07_06_RA60_CV_SIZE 1 -+/* Bit: 'RA60_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_TXTAG_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_07_06_RA60_TXTAG_SIZE 2 -+/* Bit: 'RA60_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_07_06_RA60_ACT_OFFSET 0x93 -+#define TANTOS_3G_RA_07_06_RA60_ACT_SHIFT 0 -+#define TANTOS_3G_RA_07_06_RA60_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000009~0180C2000008' */ -+/* Bit: 'RA89_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_VALID_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_VALID_SHIFT 15 -+#define TANTOS_3G_RA_09_08_RA89_VALID_SIZE 1 -+/* Bit: 'RA89_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_SPAN_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_09_08_RA89_SPAN_SIZE 1 -+/* Bit: 'RA89_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_MG_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_MG_SHIFT 13 -+#define TANTOS_3G_RA_09_08_RA89_MG_SIZE 1 -+/* Bit: 'RA89_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_CV_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_CV_SHIFT 12 -+#define TANTOS_3G_RA_09_08_RA89_CV_SIZE 1 -+/* Bit: 'RA89_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_TXTAG_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_09_08_RA89_TXTAG_SIZE 2 -+/* Bit: 'RA89_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_09_08_RA89_ACT_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA89_ACT_SHIFT 8 -+#define TANTOS_3G_RA_09_08_RA89_ACT_SIZE 2 -+/* Bit: 'RA80_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_VALID_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_VALID_SHIFT 7 -+#define TANTOS_3G_RA_09_08_RA80_VALID_SIZE 1 -+/* Bit: 'RA80_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_SPAN_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_09_08_RA80_SPAN_SIZE 1 -+/* Bit: 'RA80_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_MG_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_MG_SHIFT 5 -+#define TANTOS_3G_RA_09_08_RA80_MG_SIZE 1 -+/* Bit: 'RA80_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_CV_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_CV_SHIFT 4 -+#define TANTOS_3G_RA_09_08_RA80_CV_SIZE 1 -+/* Bit: 'RA80_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_TXTAG_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_09_08_RA80_TXTAG_SIZE 2 -+/* Bit: 'RA80_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_09_08_RA80_ACT_OFFSET 0x94 -+#define TANTOS_3G_RA_09_08_RA80_ACT_SHIFT 0 -+#define TANTOS_3G_RA_09_08_RA80_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200000B~0180C200000A' */ -+/* Bit: 'RA1101_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_VALID_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_VALID_SHIFT 15 -+#define TANTOS_3G_RA_0B_0A_RA1101_VALID_SIZE 1 -+/* Bit: 'RA1101_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_0B_0A_RA1101_SPAN_SIZE 1 -+/* Bit: 'RA1101_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_MG_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_MG_SHIFT 13 -+#define TANTOS_3G_RA_0B_0A_RA1101_MG_SIZE 1 -+/* Bit: 'RA1101_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_CV_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_CV_SHIFT 12 -+#define TANTOS_3G_RA_0B_0A_RA1101_CV_SIZE 1 -+/* Bit: 'RA1101_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_0B_0A_RA1101_TXTAG_SIZE 2 -+/* Bit: 'RA1101_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0B_0A_RA1101_ACT_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1101_ACT_SHIFT 8 -+#define TANTOS_3G_RA_0B_0A_RA1101_ACT_SIZE 2 -+/* Bit: 'RA1100_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_VALID_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_VALID_SHIFT 7 -+#define TANTOS_3G_RA_0B_0A_RA1100_VALID_SIZE 1 -+/* Bit: 'RA1100_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_0B_0A_RA1100_SPAN_SIZE 1 -+/* Bit: 'RA1100_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_MG_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_MG_SHIFT 5 -+#define TANTOS_3G_RA_0B_0A_RA1100_MG_SIZE 1 -+/* Bit: 'RA1100_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_CV_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_CV_SHIFT 4 -+#define TANTOS_3G_RA_0B_0A_RA1100_CV_SIZE 1 -+/* Bit: 'RA1100_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_0B_0A_RA1100_TXTAG_SIZE 2 -+/* Bit: 'RA1100_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0B_0A_RA1100_ACT_OFFSET 0x95 -+#define TANTOS_3G_RA_0B_0A_RA1100_ACT_SHIFT 0 -+#define TANTOS_3G_RA_0B_0A_RA1100_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200000D~0180C200000C' */ -+/* Bit: 'RA1321_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_VALID_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_VALID_SHIFT 15 -+#define TANTOS_3G_RA_0D_0C_RA1321_VALID_SIZE 1 -+/* Bit: 'RA1321_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_0D_0C_RA1321_SPAN_SIZE 1 -+/* Bit: 'RA1321_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_MG_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_MG_SHIFT 13 -+#define TANTOS_3G_RA_0D_0C_RA1321_MG_SIZE 1 -+/* Bit: 'RA1321_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_CV_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_CV_SHIFT 12 -+#define TANTOS_3G_RA_0D_0C_RA1321_CV_SIZE 1 -+/* Bit: 'RA1321_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_0D_0C_RA1321_TXTAG_SIZE 2 -+/* Bit: 'RA1321_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0D_0C_RA1321_ACT_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1321_ACT_SHIFT 8 -+#define TANTOS_3G_RA_0D_0C_RA1321_ACT_SIZE 2 -+/* Bit: 'RA1320_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_VALID_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_VALID_SHIFT 7 -+#define TANTOS_3G_RA_0D_0C_RA1320_VALID_SIZE 1 -+/* Bit: 'RA1320_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_0D_0C_RA1320_SPAN_SIZE 1 -+/* Bit: 'RA1320_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_MG_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_MG_SHIFT 5 -+#define TANTOS_3G_RA_0D_0C_RA1320_MG_SIZE 1 -+/* Bit: 'RA1320_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_CV_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_CV_SHIFT 4 -+#define TANTOS_3G_RA_0D_0C_RA1320_CV_SIZE 1 -+/* Bit: 'RA1320_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_0D_0C_RA1320_TXTAG_SIZE 2 -+/* Bit: 'RA1320_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0D_0C_RA1320_ACT_OFFSET 0x96 -+#define TANTOS_3G_RA_0D_0C_RA1320_ACT_SHIFT 0 -+#define TANTOS_3G_RA_0D_0C_RA1320_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200000F~0180C200000E' */ -+/* Bit: 'RA1541_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_VALID_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_VALID_SHIFT 15 -+#define TANTOS_3G_RA_0F_0E_RA1541_VALID_SIZE 1 -+/* Bit: 'RA1541_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_0F_0E_RA1541_SPAN_SIZE 1 -+/* Bit: 'RA1541_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_MG_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_MG_SHIFT 13 -+#define TANTOS_3G_RA_0F_0E_RA1541_MG_SIZE 1 -+/* Bit: 'RA1541_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_CV_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_CV_SHIFT 12 -+#define TANTOS_3G_RA_0F_0E_RA1541_CV_SIZE 1 -+/* Bit: 'RA1541_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_0F_0E_RA1541_TXTAG_SIZE 2 -+/* Bit: 'RA1541_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_0F_0E_RA1541_ACT_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1541_ACT_SHIFT 8 -+#define TANTOS_3G_RA_0F_0E_RA1541_ACT_SIZE 2 -+/* Bit: 'RA1540_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_VALID_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_VALID_SHIFT 7 -+#define TANTOS_3G_RA_0F_0E_RA1540_VALID_SIZE 1 -+/* Bit: 'RA1540_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_0F_0E_RA1540_SPAN_SIZE 1 -+/* Bit: 'RA1540_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_MG_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_MG_SHIFT 5 -+#define TANTOS_3G_RA_0F_0E_RA1540_MG_SIZE 1 -+/* Bit: 'RA1540_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_CV_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_CV_SHIFT 4 -+#define TANTOS_3G_RA_0F_0E_RA1540_CV_SIZE 1 -+/* Bit: 'RA1540_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_0F_0E_RA1540_TXTAG_SIZE 2 -+/* Bit: 'RA1540_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_0F_0E_RA1540_ACT_OFFSET 0x97 -+#define TANTOS_3G_RA_0F_0E_RA1540_ACT_SHIFT 0 -+#define TANTOS_3G_RA_0F_0E_RA1540_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000011~0180C2000010' */ -+/* Bit: 'RA1761_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_VALID_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_VALID_SHIFT 15 -+#define TANTOS_3G_RA_11_10_RA1761_VALID_SIZE 1 -+/* Bit: 'RA1761_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_SPAN_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_11_10_RA1761_SPAN_SIZE 1 -+/* Bit: 'RA1761_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_MG_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_MG_SHIFT 13 -+#define TANTOS_3G_RA_11_10_RA1761_MG_SIZE 1 -+/* Bit: 'RA1761_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_CV_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_CV_SHIFT 12 -+#define TANTOS_3G_RA_11_10_RA1761_CV_SIZE 1 -+/* Bit: 'RA1761_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_TXTAG_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_11_10_RA1761_TXTAG_SIZE 2 -+/* Bit: 'RA1761_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_11_10_RA1761_ACT_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1761_ACT_SHIFT 8 -+#define TANTOS_3G_RA_11_10_RA1761_ACT_SIZE 2 -+/* Bit: 'RA1760_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_VALID_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_VALID_SHIFT 7 -+#define TANTOS_3G_RA_11_10_RA1760_VALID_SIZE 1 -+/* Bit: 'RA1760_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_SPAN_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_11_10_RA1760_SPAN_SIZE 1 -+/* Bit: 'RA1760_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_MG_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_MG_SHIFT 5 -+#define TANTOS_3G_RA_11_10_RA1760_MG_SIZE 1 -+/* Bit: 'RA1760_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_CV_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_CV_SHIFT 4 -+#define TANTOS_3G_RA_11_10_RA1760_CV_SIZE 1 -+/* Bit: 'RA1760_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_TXTAG_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_11_10_RA1760_TXTAG_SIZE 2 -+/* Bit: 'RA1760_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_11_10_RA1760_ACT_OFFSET 0x98 -+#define TANTOS_3G_RA_11_10_RA1760_ACT_SHIFT 0 -+#define TANTOS_3G_RA_11_10_RA1760_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000013~0180C2000012' */ -+/* Bit: 'RA1981_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_VALID_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_VALID_SHIFT 15 -+#define TANTOS_3G_RA_13_12_RA1981_VALID_SIZE 1 -+/* Bit: 'RA1981_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_SPAN_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_13_12_RA1981_SPAN_SIZE 1 -+/* Bit: 'RA1981_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_MG_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_MG_SHIFT 13 -+#define TANTOS_3G_RA_13_12_RA1981_MG_SIZE 1 -+/* Bit: 'RA1981_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_CV_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_CV_SHIFT 12 -+#define TANTOS_3G_RA_13_12_RA1981_CV_SIZE 1 -+/* Bit: 'RA1981_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_TXTAG_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_13_12_RA1981_TXTAG_SIZE 2 -+/* Bit: 'RA1981_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_13_12_RA1981_ACT_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1981_ACT_SHIFT 8 -+#define TANTOS_3G_RA_13_12_RA1981_ACT_SIZE 2 -+/* Bit: 'RA1980_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_VALID_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_VALID_SHIFT 7 -+#define TANTOS_3G_RA_13_12_RA1980_VALID_SIZE 1 -+/* Bit: 'RA1980_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_SPAN_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_13_12_RA1980_SPAN_SIZE 1 -+/* Bit: 'RA1980_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_MG_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_MG_SHIFT 5 -+#define TANTOS_3G_RA_13_12_RA1980_MG_SIZE 1 -+/* Bit: 'RA1980_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_CV_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_CV_SHIFT 4 -+#define TANTOS_3G_RA_13_12_RA1980_CV_SIZE 1 -+/* Bit: 'RA1980_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_TXTAG_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_13_12_RA1980_TXTAG_SIZE 2 -+/* Bit: 'RA1980_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_13_12_RA1980_ACT_OFFSET 0x99 -+#define TANTOS_3G_RA_13_12_RA1980_ACT_SHIFT 0 -+#define TANTOS_3G_RA_13_12_RA1980_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000015~0180C2000014' */ -+/* Bit: 'RA2021_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_VALID_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_VALID_SHIFT 15 -+#define TANTOS_3G_RA_15_14_RA2021_VALID_SIZE 1 -+/* Bit: 'RA2021_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_SPAN_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_15_14_RA2021_SPAN_SIZE 1 -+/* Bit: 'RA2021_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_MG_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_MG_SHIFT 13 -+#define TANTOS_3G_RA_15_14_RA2021_MG_SIZE 1 -+/* Bit: 'RA2021_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_CV_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_CV_SHIFT 12 -+#define TANTOS_3G_RA_15_14_RA2021_CV_SIZE 1 -+/* Bit: 'RA2021_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_TXTAG_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_15_14_RA2021_TXTAG_SIZE 2 -+/* Bit: 'RA2021_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_15_14_RA2021_ACT_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA2021_ACT_SHIFT 8 -+#define TANTOS_3G_RA_15_14_RA2021_ACT_SIZE 2 -+/* Bit: 'RA200_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_VALID_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_VALID_SHIFT 7 -+#define TANTOS_3G_RA_15_14_RA200_VALID_SIZE 1 -+/* Bit: 'RA200_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_SPAN_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_15_14_RA200_SPAN_SIZE 1 -+/* Bit: 'RA200_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_MG_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_MG_SHIFT 5 -+#define TANTOS_3G_RA_15_14_RA200_MG_SIZE 1 -+/* Bit: 'RA200_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_CV_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_CV_SHIFT 4 -+#define TANTOS_3G_RA_15_14_RA200_CV_SIZE 1 -+/* Bit: 'RA200_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_TXTAG_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_15_14_RA200_TXTAG_SIZE 2 -+/* Bit: 'RA200_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_15_14_RA200_ACT_OFFSET 0x9A -+#define TANTOS_3G_RA_15_14_RA200_ACT_SHIFT 0 -+#define TANTOS_3G_RA_15_14_RA200_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000017~0180C2000016' */ -+/* Bit: 'RA2223_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_VALID_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_VALID_SHIFT 15 -+#define TANTOS_3G_RA_17_16_RA2223_VALID_SIZE 1 -+/* Bit: 'RA2223_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_SPAN_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_17_16_RA2223_SPAN_SIZE 1 -+/* Bit: 'RA2223_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_MG_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_MG_SHIFT 13 -+#define TANTOS_3G_RA_17_16_RA2223_MG_SIZE 1 -+/* Bit: 'RA2223_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_CV_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_CV_SHIFT 12 -+#define TANTOS_3G_RA_17_16_RA2223_CV_SIZE 1 -+/* Bit: 'RA2223_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_TXTAG_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_17_16_RA2223_TXTAG_SIZE 2 -+/* Bit: 'RA2223_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_17_16_RA2223_ACT_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA2223_ACT_SHIFT 8 -+#define TANTOS_3G_RA_17_16_RA2223_ACT_SIZE 2 -+/* Bit: 'RA220_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_VALID_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_VALID_SHIFT 7 -+#define TANTOS_3G_RA_17_16_RA220_VALID_SIZE 1 -+/* Bit: 'RA220_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_SPAN_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_17_16_RA220_SPAN_SIZE 1 -+/* Bit: 'RA220_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_MG_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_MG_SHIFT 5 -+#define TANTOS_3G_RA_17_16_RA220_MG_SIZE 1 -+/* Bit: 'RA220_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_CV_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_CV_SHIFT 4 -+#define TANTOS_3G_RA_17_16_RA220_CV_SIZE 1 -+/* Bit: 'RA220_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_TXTAG_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_17_16_RA220_TXTAG_SIZE 2 -+/* Bit: 'RA220_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_17_16_RA220_ACT_OFFSET 0x9B -+#define TANTOS_3G_RA_17_16_RA220_ACT_SHIFT 0 -+#define TANTOS_3G_RA_17_16_RA220_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000019~0180C2000018' */ -+/* Bit: 'RA2425_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_VALID_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_VALID_SHIFT 15 -+#define TANTOS_3G_RA_19_18_RA2425_VALID_SIZE 1 -+/* Bit: 'RA2425_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_SPAN_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_19_18_RA2425_SPAN_SIZE 1 -+/* Bit: 'RA2425_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_MG_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_MG_SHIFT 13 -+#define TANTOS_3G_RA_19_18_RA2425_MG_SIZE 1 -+/* Bit: 'RA2425_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_CV_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_CV_SHIFT 12 -+#define TANTOS_3G_RA_19_18_RA2425_CV_SIZE 1 -+/* Bit: 'RA2425_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_TXTAG_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_19_18_RA2425_TXTAG_SIZE 2 -+/* Bit: 'RA2425_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_19_18_RA2425_ACT_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA2425_ACT_SHIFT 8 -+#define TANTOS_3G_RA_19_18_RA2425_ACT_SIZE 2 -+/* Bit: 'RA240_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_VALID_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_VALID_SHIFT 7 -+#define TANTOS_3G_RA_19_18_RA240_VALID_SIZE 1 -+/* Bit: 'RA240_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_SPAN_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_19_18_RA240_SPAN_SIZE 1 -+/* Bit: 'RA240_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_MG_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_MG_SHIFT 5 -+#define TANTOS_3G_RA_19_18_RA240_MG_SIZE 1 -+/* Bit: 'RA240_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_CV_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_CV_SHIFT 4 -+#define TANTOS_3G_RA_19_18_RA240_CV_SIZE 1 -+/* Bit: 'RA240_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_TXTAG_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_19_18_RA240_TXTAG_SIZE 2 -+/* Bit: 'RA240_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_19_18_RA240_ACT_OFFSET 0x9C -+#define TANTOS_3G_RA_19_18_RA240_ACT_SHIFT 0 -+#define TANTOS_3G_RA_19_18_RA240_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200001B~0180C200001A' */ -+/* Bit: 'RA2627_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_VALID_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_VALID_SHIFT 15 -+#define TANTOS_3G_RA_1B_1A_RA2627_VALID_SIZE 1 -+/* Bit: 'RA2627_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_1B_1A_RA2627_SPAN_SIZE 1 -+/* Bit: 'RA2627_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_MG_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_MG_SHIFT 13 -+#define TANTOS_3G_RA_1B_1A_RA2627_MG_SIZE 1 -+/* Bit: 'RA2627_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_CV_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_CV_SHIFT 12 -+#define TANTOS_3G_RA_1B_1A_RA2627_CV_SIZE 1 -+/* Bit: 'RA2627_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_1B_1A_RA2627_TXTAG_SIZE 2 -+/* Bit: 'RA2627_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1B_1A_RA2627_ACT_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA2627_ACT_SHIFT 8 -+#define TANTOS_3G_RA_1B_1A_RA2627_ACT_SIZE 2 -+/* Bit: 'RA260_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_VALID_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_VALID_SHIFT 7 -+#define TANTOS_3G_RA_1B_1A_RA260_VALID_SIZE 1 -+/* Bit: 'RA260_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_SPAN_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_1B_1A_RA260_SPAN_SIZE 1 -+/* Bit: 'RA260_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_MG_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_MG_SHIFT 5 -+#define TANTOS_3G_RA_1B_1A_RA260_MG_SIZE 1 -+/* Bit: 'RA260_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_CV_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_CV_SHIFT 4 -+#define TANTOS_3G_RA_1B_1A_RA260_CV_SIZE 1 -+/* Bit: 'RA260_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_1B_1A_RA260_TXTAG_SIZE 2 -+/* Bit: 'RA260_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1B_1A_RA260_ACT_OFFSET 0x9D -+#define TANTOS_3G_RA_1B_1A_RA260_ACT_SHIFT 0 -+#define TANTOS_3G_RA_1B_1A_RA260_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200001D~0180C200001C' */ -+/* Bit: 'RA2829_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_VALID_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_VALID_SHIFT 15 -+#define TANTOS_3G_RA_1D_1C_RA2829_VALID_SIZE 1 -+/* Bit: 'RA2829_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_1D_1C_RA2829_SPAN_SIZE 1 -+/* Bit: 'RA2829_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_MG_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_MG_SHIFT 13 -+#define TANTOS_3G_RA_1D_1C_RA2829_MG_SIZE 1 -+/* Bit: 'RA2829_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_CV_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_CV_SHIFT 12 -+#define TANTOS_3G_RA_1D_1C_RA2829_CV_SIZE 1 -+/* Bit: 'RA2829_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_1D_1C_RA2829_TXTAG_SIZE 2 -+/* Bit: 'RA2829_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1D_1C_RA2829_ACT_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA2829_ACT_SHIFT 8 -+#define TANTOS_3G_RA_1D_1C_RA2829_ACT_SIZE 2 -+/* Bit: 'RA280_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_VALID_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_VALID_SHIFT 7 -+#define TANTOS_3G_RA_1D_1C_RA280_VALID_SIZE 1 -+/* Bit: 'RA280_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_SPAN_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_1D_1C_RA280_SPAN_SIZE 1 -+/* Bit: 'RA280_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_MG_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_MG_SHIFT 5 -+#define TANTOS_3G_RA_1D_1C_RA280_MG_SIZE 1 -+/* Bit: 'RA280_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_CV_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_CV_SHIFT 4 -+#define TANTOS_3G_RA_1D_1C_RA280_CV_SIZE 1 -+/* Bit: 'RA280_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_1D_1C_RA280_TXTAG_SIZE 2 -+/* Bit: 'RA280_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1D_1C_RA280_ACT_OFFSET 0x9E -+#define TANTOS_3G_RA_1D_1C_RA280_ACT_SHIFT 0 -+#define TANTOS_3G_RA_1D_1C_RA280_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200001F~0180C200001E' */ -+/* Bit: 'RA3031_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_VALID_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_VALID_SHIFT 15 -+#define TANTOS_3G_RA_1F_1E_RA3031_VALID_SIZE 1 -+/* Bit: 'RA3031_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_1F_1E_RA3031_SPAN_SIZE 1 -+/* Bit: 'RA3031_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_MG_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_MG_SHIFT 13 -+#define TANTOS_3G_RA_1F_1E_RA3031_MG_SIZE 1 -+/* Bit: 'RA3031_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_CV_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_CV_SHIFT 12 -+#define TANTOS_3G_RA_1F_1E_RA3031_CV_SIZE 1 -+/* Bit: 'RA3031_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_1F_1E_RA3031_TXTAG_SIZE 2 -+/* Bit: 'RA3031_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_1F_1E_RA3031_ACT_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA3031_ACT_SHIFT 8 -+#define TANTOS_3G_RA_1F_1E_RA3031_ACT_SIZE 2 -+/* Bit: 'RA300_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_VALID_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_VALID_SHIFT 7 -+#define TANTOS_3G_RA_1F_1E_RA300_VALID_SIZE 1 -+/* Bit: 'RA300_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_SPAN_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_1F_1E_RA300_SPAN_SIZE 1 -+/* Bit: 'RA300_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_MG_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_MG_SHIFT 5 -+#define TANTOS_3G_RA_1F_1E_RA300_MG_SIZE 1 -+/* Bit: 'RA300_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_CV_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_CV_SHIFT 4 -+#define TANTOS_3G_RA_1F_1E_RA300_CV_SIZE 1 -+/* Bit: 'RA300_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_1F_1E_RA300_TXTAG_SIZE 2 -+/* Bit: 'RA300_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_1F_1E_RA300_ACT_OFFSET 0x9F -+#define TANTOS_3G_RA_1F_1E_RA300_ACT_SHIFT 0 -+#define TANTOS_3G_RA_1F_1E_RA300_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000021~0180C2000020' */ -+/* Bit: 'RA3233_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_VALID_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_VALID_SHIFT 15 -+#define TANTOS_3G_RA_21_20_RA3233_VALID_SIZE 1 -+/* Bit: 'RA3233_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_SPAN_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_21_20_RA3233_SPAN_SIZE 1 -+/* Bit: 'RA3233_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_MG_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_MG_SHIFT 13 -+#define TANTOS_3G_RA_21_20_RA3233_MG_SIZE 1 -+/* Bit: 'RA3233_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_CV_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_CV_SHIFT 12 -+#define TANTOS_3G_RA_21_20_RA3233_CV_SIZE 1 -+/* Bit: 'RA3233_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_TXTAG_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_21_20_RA3233_TXTAG_SIZE 2 -+/* Bit: 'RA3233_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_21_20_RA3233_ACT_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA3233_ACT_SHIFT 8 -+#define TANTOS_3G_RA_21_20_RA3233_ACT_SIZE 2 -+/* Bit: 'RA320_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_VALID_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_VALID_SHIFT 7 -+#define TANTOS_3G_RA_21_20_RA320_VALID_SIZE 1 -+/* Bit: 'RA320_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_SPAN_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_21_20_RA320_SPAN_SIZE 1 -+/* Bit: 'RA320_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_MG_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_MG_SHIFT 5 -+#define TANTOS_3G_RA_21_20_RA320_MG_SIZE 1 -+/* Bit: 'RA320_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_CV_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_CV_SHIFT 4 -+#define TANTOS_3G_RA_21_20_RA320_CV_SIZE 1 -+/* Bit: 'RA320_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_TXTAG_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_21_20_RA320_TXTAG_SIZE 2 -+/* Bit: 'RA320_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_21_20_RA320_ACT_OFFSET 0xB0 -+#define TANTOS_3G_RA_21_20_RA320_ACT_SHIFT 0 -+#define TANTOS_3G_RA_21_20_RA320_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000023~0180C2000022' */ -+/* Bit: 'RA3435_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_VALID_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_VALID_SHIFT 15 -+#define TANTOS_3G_RA_23_22_RA3435_VALID_SIZE 1 -+/* Bit: 'RA3435_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_SPAN_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_23_22_RA3435_SPAN_SIZE 1 -+/* Bit: 'RA3435_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_MG_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_MG_SHIFT 13 -+#define TANTOS_3G_RA_23_22_RA3435_MG_SIZE 1 -+/* Bit: 'RA3435_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_CV_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_CV_SHIFT 12 -+#define TANTOS_3G_RA_23_22_RA3435_CV_SIZE 1 -+/* Bit: 'RA3435_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_TXTAG_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_23_22_RA3435_TXTAG_SIZE 2 -+/* Bit: 'RA3435_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_23_22_RA3435_ACT_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA3435_ACT_SHIFT 8 -+#define TANTOS_3G_RA_23_22_RA3435_ACT_SIZE 2 -+/* Bit: 'RA340_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_VALID_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_VALID_SHIFT 7 -+#define TANTOS_3G_RA_23_22_RA340_VALID_SIZE 1 -+/* Bit: 'RA340_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_SPAN_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_23_22_RA340_SPAN_SIZE 1 -+/* Bit: 'RA340_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_MG_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_MG_SHIFT 5 -+#define TANTOS_3G_RA_23_22_RA340_MG_SIZE 1 -+/* Bit: 'RA340_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_CV_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_CV_SHIFT 4 -+#define TANTOS_3G_RA_23_22_RA340_CV_SIZE 1 -+/* Bit: 'RA340_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_TXTAG_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_23_22_RA340_TXTAG_SIZE 2 -+/* Bit: 'RA340_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_23_22_RA340_ACT_OFFSET 0xB1 -+#define TANTOS_3G_RA_23_22_RA340_ACT_SHIFT 0 -+#define TANTOS_3G_RA_23_22_RA340_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000025~0180C2000024' */ -+/* Bit: 'RA3637_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_VALID_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_VALID_SHIFT 15 -+#define TANTOS_3G_RA_25_24_RA3637_VALID_SIZE 1 -+/* Bit: 'RA3637_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_SPAN_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_25_24_RA3637_SPAN_SIZE 1 -+/* Bit: 'RA3637_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_MG_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_MG_SHIFT 13 -+#define TANTOS_3G_RA_25_24_RA3637_MG_SIZE 1 -+/* Bit: 'RA3637_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_CV_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_CV_SHIFT 12 -+#define TANTOS_3G_RA_25_24_RA3637_CV_SIZE 1 -+/* Bit: 'RA3637_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_TXTAG_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_25_24_RA3637_TXTAG_SIZE 2 -+/* Bit: 'RA3637_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_25_24_RA3637_ACT_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA3637_ACT_SHIFT 8 -+#define TANTOS_3G_RA_25_24_RA3637_ACT_SIZE 2 -+/* Bit: 'RA360_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_VALID_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_VALID_SHIFT 7 -+#define TANTOS_3G_RA_25_24_RA360_VALID_SIZE 1 -+/* Bit: 'RA360_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_SPAN_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_25_24_RA360_SPAN_SIZE 1 -+/* Bit: 'RA360_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_MG_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_MG_SHIFT 5 -+#define TANTOS_3G_RA_25_24_RA360_MG_SIZE 1 -+/* Bit: 'RA360_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_CV_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_CV_SHIFT 4 -+#define TANTOS_3G_RA_25_24_RA360_CV_SIZE 1 -+/* Bit: 'RA360_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_TXTAG_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_25_24_RA360_TXTAG_SIZE 2 -+/* Bit: 'RA360_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_25_24_RA360_ACT_OFFSET 0xB2 -+#define TANTOS_3G_RA_25_24_RA360_ACT_SHIFT 0 -+#define TANTOS_3G_RA_25_24_RA360_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000027~0180C2000026' */ -+/* Bit: 'RA3839_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_VALID_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_VALID_SHIFT 15 -+#define TANTOS_3G_RA_27_26_RA3839_VALID_SIZE 1 -+/* Bit: 'RA3839_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_SPAN_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_27_26_RA3839_SPAN_SIZE 1 -+/* Bit: 'RA3839_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_MG_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_MG_SHIFT 13 -+#define TANTOS_3G_RA_27_26_RA3839_MG_SIZE 1 -+/* Bit: 'RA3839_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_CV_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_CV_SHIFT 12 -+#define TANTOS_3G_RA_27_26_RA3839_CV_SIZE 1 -+/* Bit: 'RA3839_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_TXTAG_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_27_26_RA3839_TXTAG_SIZE 2 -+/* Bit: 'RA3839_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_27_26_RA3839_ACT_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA3839_ACT_SHIFT 8 -+#define TANTOS_3G_RA_27_26_RA3839_ACT_SIZE 2 -+/* Bit: 'RA380_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_VALID_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_VALID_SHIFT 7 -+#define TANTOS_3G_RA_27_26_RA380_VALID_SIZE 1 -+/* Bit: 'RA380_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_SPAN_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_27_26_RA380_SPAN_SIZE 1 -+/* Bit: 'RA380_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_MG_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_MG_SHIFT 5 -+#define TANTOS_3G_RA_27_26_RA380_MG_SIZE 1 -+/* Bit: 'RA380_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_CV_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_CV_SHIFT 4 -+#define TANTOS_3G_RA_27_26_RA380_CV_SIZE 1 -+/* Bit: 'RA380_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_TXTAG_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_27_26_RA380_TXTAG_SIZE 2 -+/* Bit: 'RA380_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_27_26_RA380_ACT_OFFSET 0xB3 -+#define TANTOS_3G_RA_27_26_RA380_ACT_SHIFT 0 -+#define TANTOS_3G_RA_27_26_RA380_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C2000029~0180C2000028' */ -+/* Bit: 'RA4041_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_VALID_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_VALID_SHIFT 15 -+#define TANTOS_3G_RA_29_28_RA4041_VALID_SIZE 1 -+/* Bit: 'RA4041_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_SPAN_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_29_28_RA4041_SPAN_SIZE 1 -+/* Bit: 'RA4041_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_MG_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_MG_SHIFT 13 -+#define TANTOS_3G_RA_29_28_RA4041_MG_SIZE 1 -+/* Bit: 'RA4041_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_CV_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_CV_SHIFT 12 -+#define TANTOS_3G_RA_29_28_RA4041_CV_SIZE 1 -+/* Bit: 'RA4041_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_TXTAG_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_29_28_RA4041_TXTAG_SIZE 2 -+/* Bit: 'RA4041_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_29_28_RA4041_ACT_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA4041_ACT_SHIFT 8 -+#define TANTOS_3G_RA_29_28_RA4041_ACT_SIZE 2 -+/* Bit: 'RA400_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_VALID_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_VALID_SHIFT 7 -+#define TANTOS_3G_RA_29_28_RA400_VALID_SIZE 1 -+/* Bit: 'RA400_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_SPAN_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_29_28_RA400_SPAN_SIZE 1 -+/* Bit: 'RA400_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_MG_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_MG_SHIFT 5 -+#define TANTOS_3G_RA_29_28_RA400_MG_SIZE 1 -+/* Bit: 'RA400_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_CV_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_CV_SHIFT 4 -+#define TANTOS_3G_RA_29_28_RA400_CV_SIZE 1 -+/* Bit: 'RA400_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_TXTAG_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_29_28_RA400_TXTAG_SIZE 2 -+/* Bit: 'RA400_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_29_28_RA400_ACT_OFFSET 0xB4 -+#define TANTOS_3G_RA_29_28_RA400_ACT_SHIFT 0 -+#define TANTOS_3G_RA_29_28_RA400_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200002B~0180C200002A' */ -+/* Bit: 'RA4243_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_VALID_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_VALID_SHIFT 15 -+#define TANTOS_3G_RA_2B_2A_RA4243_VALID_SIZE 1 -+/* Bit: 'RA4243_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_2B_2A_RA4243_SPAN_SIZE 1 -+/* Bit: 'RA4243_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_MG_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_MG_SHIFT 13 -+#define TANTOS_3G_RA_2B_2A_RA4243_MG_SIZE 1 -+/* Bit: 'RA4243_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_CV_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_CV_SHIFT 12 -+#define TANTOS_3G_RA_2B_2A_RA4243_CV_SIZE 1 -+/* Bit: 'RA4243_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_2B_2A_RA4243_TXTAG_SIZE 2 -+/* Bit: 'RA4243_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2B_2A_RA4243_ACT_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA4243_ACT_SHIFT 8 -+#define TANTOS_3G_RA_2B_2A_RA4243_ACT_SIZE 2 -+/* Bit: 'RA420_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_VALID_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_VALID_SHIFT 7 -+#define TANTOS_3G_RA_2B_2A_RA420_VALID_SIZE 1 -+/* Bit: 'RA420_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_SPAN_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_2B_2A_RA420_SPAN_SIZE 1 -+/* Bit: 'RA420_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_MG_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_MG_SHIFT 5 -+#define TANTOS_3G_RA_2B_2A_RA420_MG_SIZE 1 -+/* Bit: 'RA420_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_CV_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_CV_SHIFT 4 -+#define TANTOS_3G_RA_2B_2A_RA420_CV_SIZE 1 -+/* Bit: 'RA420_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_2B_2A_RA420_TXTAG_SIZE 2 -+/* Bit: 'RA420_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2B_2A_RA420_ACT_OFFSET 0xB5 -+#define TANTOS_3G_RA_2B_2A_RA420_ACT_SHIFT 0 -+#define TANTOS_3G_RA_2B_2A_RA420_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200002D~0180C200002C' */ -+/* Bit: 'RA4445_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_VALID_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_VALID_SHIFT 15 -+#define TANTOS_3G_RA_2D_2C_RA4445_VALID_SIZE 1 -+/* Bit: 'RA4445_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_2D_2C_RA4445_SPAN_SIZE 1 -+/* Bit: 'RA4445_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_MG_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_MG_SHIFT 13 -+#define TANTOS_3G_RA_2D_2C_RA4445_MG_SIZE 1 -+/* Bit: 'RA4445_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_CV_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_CV_SHIFT 12 -+#define TANTOS_3G_RA_2D_2C_RA4445_CV_SIZE 1 -+/* Bit: 'RA4445_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_2D_2C_RA4445_TXTAG_SIZE 2 -+/* Bit: 'RA4445_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2D_2C_RA4445_ACT_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA4445_ACT_SHIFT 8 -+#define TANTOS_3G_RA_2D_2C_RA4445_ACT_SIZE 2 -+/* Bit: 'RA440_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_VALID_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_VALID_SHIFT 7 -+#define TANTOS_3G_RA_2D_2C_RA440_VALID_SIZE 1 -+/* Bit: 'RA440_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_SPAN_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_2D_2C_RA440_SPAN_SIZE 1 -+/* Bit: 'RA440_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_MG_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_MG_SHIFT 5 -+#define TANTOS_3G_RA_2D_2C_RA440_MG_SIZE 1 -+/* Bit: 'RA440_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_CV_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_CV_SHIFT 4 -+#define TANTOS_3G_RA_2D_2C_RA440_CV_SIZE 1 -+/* Bit: 'RA440_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_2D_2C_RA440_TXTAG_SIZE 2 -+/* Bit: 'RA440_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2D_2C_RA440_ACT_OFFSET 0xB6 -+#define TANTOS_3G_RA_2D_2C_RA440_ACT_SHIFT 0 -+#define TANTOS_3G_RA_2D_2C_RA440_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Reserve Action for 0180C200002F~0180C200002E' */ -+/* Bit: 'RA4647_VALID' */ -+/* Description: 'Valid bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_VALID_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_VALID_SHIFT 15 -+#define TANTOS_3G_RA_2F_2E_RA4647_VALID_SIZE 1 -+/* Bit: 'RA4647_SPAN' */ -+/* Description: 'Span bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_SHIFT 14 -+#define TANTOS_3G_RA_2F_2E_RA4647_SPAN_SIZE 1 -+/* Bit: 'RA4647_MG' */ -+/* Description: 'Management bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_MG_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_MG_SHIFT 13 -+#define TANTOS_3G_RA_2F_2E_RA4647_MG_SIZE 1 -+/* Bit: 'RA4647_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_CV_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_CV_SHIFT 12 -+#define TANTOS_3G_RA_2F_2E_RA4647_CV_SIZE 1 -+/* Bit: 'RA4647_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SHIFT 10 -+#define TANTOS_3G_RA_2F_2E_RA4647_TXTAG_SIZE 2 -+/* Bit: 'RA4647_ACT' */ -+/* Description: 'Action bit for 0180C2000001' */ -+#define TANTOS_3G_RA_2F_2E_RA4647_ACT_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA4647_ACT_SHIFT 8 -+#define TANTOS_3G_RA_2F_2E_RA4647_ACT_SIZE 2 -+/* Bit: 'RA460_VALID' */ -+/* Description: 'Valid bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_VALID_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_VALID_SHIFT 7 -+#define TANTOS_3G_RA_2F_2E_RA460_VALID_SIZE 1 -+/* Bit: 'RA460_SPAN' */ -+/* Description: 'Span bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_SPAN_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_SPAN_SHIFT 6 -+#define TANTOS_3G_RA_2F_2E_RA460_SPAN_SIZE 1 -+/* Bit: 'RA460_MG' */ -+/* Description: 'Management bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_MG_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_MG_SHIFT 5 -+#define TANTOS_3G_RA_2F_2E_RA460_MG_SIZE 1 -+/* Bit: 'RA460_CV' */ -+/* Description: 'Cross_VLAN bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_CV_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_CV_SHIFT 4 -+#define TANTOS_3G_RA_2F_2E_RA460_CV_SIZE 1 -+/* Bit: 'RA460_TXTAG' */ -+/* Description: 'TXTAG bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_SHIFT 2 -+#define TANTOS_3G_RA_2F_2E_RA460_TXTAG_SIZE 2 -+/* Bit: 'RA460_ACT' */ -+/* Description: 'Action bit for 0180C2000000' */ -+#define TANTOS_3G_RA_2F_2E_RA460_ACT_OFFSET 0xB7 -+#define TANTOS_3G_RA_2F_2E_RA460_ACT_SHIFT 0 -+#define TANTOS_3G_RA_2F_2E_RA460_ACT_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 0' */ -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_0_PFR1_OFFSET 0xB8 -+#define TANTOS_3G_PF_0_PFR1_SHIFT 8 -+#define TANTOS_3G_PF_0_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_0_PFR0_OFFSET 0xB8 -+#define TANTOS_3G_PF_0_PFR0_SHIFT 0 -+#define TANTOS_3G_PF_0_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 3 and 2' */ -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_1_PFR1_OFFSET 0xB9 -+#define TANTOS_3G_PF_1_PFR1_SHIFT 8 -+#define TANTOS_3G_PF_1_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_1_PFR0_OFFSET 0xB9 -+#define TANTOS_3G_PF_1_PFR0_SHIFT 0 -+#define TANTOS_3G_PF_1_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 5 and 4' */ -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_2_PFR1_OFFSET 0xBA -+#define TANTOS_3G_PF_2_PFR1_SHIFT 8 -+#define TANTOS_3G_PF_2_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_2_PFR0_OFFSET 0xBA -+#define TANTOS_3G_PF_2_PFR0_SHIFT 0 -+#define TANTOS_3G_PF_2_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter 7 and 6' */ -+/* Bit: 'PFR1' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_3_PFR1_OFFSET 0xBB -+#define TANTOS_3G_PF_3_PFR1_SHIFT 8 -+#define TANTOS_3G_PF_3_PFR1_SIZE 8 -+/* Bit: 'PFR0' */ -+/* Description: 'Value Compared with Protocol in IP Header' */ -+#define TANTOS_3G_PF_3_PFR0_OFFSET 0xBB -+#define TANTOS_3G_PF_3_PFR0_SHIFT 0 -+#define TANTOS_3G_PF_3_PFR0_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Control 0 Register' */ -+/* Bit: 'PHYIE6' */ -+/* Description: 'PHY Initial Enable for port 6' */ -+#define TANTOS_3G_PHYIC0_PHYIE6_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE6_SHIFT 14 -+#define TANTOS_3G_PHYIC0_PHYIE6_SIZE 1 -+/* Bit: 'PHYIE5' */ -+/* Description: 'PHY Initial Enable for port 5' */ -+#define TANTOS_3G_PHYIC0_PHYIE5_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE5_SHIFT 13 -+#define TANTOS_3G_PHYIC0_PHYIE5_SIZE 1 -+/* Bit: 'PHYIE4' */ -+/* Description: 'PHY Initial Enable for port 4' */ -+#define TANTOS_3G_PHYIC0_PHYIE4_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE4_SHIFT 12 -+#define TANTOS_3G_PHYIC0_PHYIE4_SIZE 1 -+/* Bit: 'PHYIE3' */ -+/* Description: 'PHY Initial Enable for port 3' */ -+#define TANTOS_3G_PHYIC0_PHYIE3_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE3_SHIFT 11 -+#define TANTOS_3G_PHYIC0_PHYIE3_SIZE 1 -+/* Bit: 'PHYIE2' */ -+/* Description: 'PHY Initial Enable for port 2' */ -+#define TANTOS_3G_PHYIC0_PHYIE2_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE2_SHIFT 10 -+#define TANTOS_3G_PHYIC0_PHYIE2_SIZE 1 -+/* Bit: 'PHYIE1' */ -+/* Description: 'PHY Initial Enable for port 1' */ -+#define TANTOS_3G_PHYIC0_PHYIE1_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE1_SHIFT 9 -+#define TANTOS_3G_PHYIC0_PHYIE1_SIZE 1 -+/* Bit: 'PHYIE0' */ -+/* Description: 'PHY Initial Enable for port 0' */ -+#define TANTOS_3G_PHYIC0_PHYIE0_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_PHYIE0_SHIFT 8 -+#define TANTOS_3G_PHYIC0_PHYIE0_SIZE 1 -+/* Bit: 'REGA0' */ -+/* Description: 'Register Address 0' */ -+#define TANTOS_3G_PHYIC0_REGA0_OFFSET 0xD0 -+#define TANTOS_3G_PHYIC0_REGA0_SHIFT 0 -+#define TANTOS_3G_PHYIC0_REGA0_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Control 1 Register' */ -+/* Bit: 'PHYIE6' */ -+/* Description: 'PHY Initial Enable for port 6' */ -+#define TANTOS_3G_PHYIC1_PHYIE6_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE6_SHIFT 14 -+#define TANTOS_3G_PHYIC1_PHYIE6_SIZE 1 -+/* Bit: 'PHYIE5' */ -+/* Description: 'PHY Initial Enable for port 5' */ -+#define TANTOS_3G_PHYIC1_PHYIE5_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE5_SHIFT 13 -+#define TANTOS_3G_PHYIC1_PHYIE5_SIZE 1 -+/* Bit: 'PHYIE4' */ -+/* Description: 'PHY Initial Enable for port 4' */ -+#define TANTOS_3G_PHYIC1_PHYIE4_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE4_SHIFT 12 -+#define TANTOS_3G_PHYIC1_PHYIE4_SIZE 1 -+/* Bit: 'PHYIE3' */ -+/* Description: 'PHY Initial Enable for port 3' */ -+#define TANTOS_3G_PHYIC1_PHYIE3_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE3_SHIFT 11 -+#define TANTOS_3G_PHYIC1_PHYIE3_SIZE 1 -+/* Bit: 'PHYIE2' */ -+/* Description: 'PHY Initial Enable for port 2' */ -+#define TANTOS_3G_PHYIC1_PHYIE2_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE2_SHIFT 10 -+#define TANTOS_3G_PHYIC1_PHYIE2_SIZE 1 -+/* Bit: 'PHYIE1' */ -+/* Description: 'PHY Initial Enable for port 1' */ -+#define TANTOS_3G_PHYIC1_PHYIE1_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE1_SHIFT 9 -+#define TANTOS_3G_PHYIC1_PHYIE1_SIZE 1 -+/* Bit: 'PHYIE0' */ -+/* Description: 'PHY Initial Enable for port 0' */ -+#define TANTOS_3G_PHYIC1_PHYIE0_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_PHYIE0_SHIFT 8 -+#define TANTOS_3G_PHYIC1_PHYIE0_SIZE 1 -+/* Bit: 'REGA0' */ -+/* Description: 'Register Address 0' */ -+#define TANTOS_3G_PHYIC1_REGA0_OFFSET 0xD2 -+#define TANTOS_3G_PHYIC1_REGA0_SHIFT 0 -+#define TANTOS_3G_PHYIC1_REGA0_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Control 2 Register' */ -+/* Bit: 'PHYIE6' */ -+/* Description: 'PHY Initial Enable for port 6' */ -+#define TANTOS_3G_PHYIC2_PHYIE6_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE6_SHIFT 14 -+#define TANTOS_3G_PHYIC2_PHYIE6_SIZE 1 -+/* Bit: 'PHYIE5' */ -+/* Description: 'PHY Initial Enable for port 5' */ -+#define TANTOS_3G_PHYIC2_PHYIE5_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE5_SHIFT 13 -+#define TANTOS_3G_PHYIC2_PHYIE5_SIZE 1 -+/* Bit: 'PHYIE4' */ -+/* Description: 'PHY Initial Enable for port 4' */ -+#define TANTOS_3G_PHYIC2_PHYIE4_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE4_SHIFT 12 -+#define TANTOS_3G_PHYIC2_PHYIE4_SIZE 1 -+/* Bit: 'PHYIE3' */ -+/* Description: 'PHY Initial Enable for port 3' */ -+#define TANTOS_3G_PHYIC2_PHYIE3_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE3_SHIFT 11 -+#define TANTOS_3G_PHYIC2_PHYIE3_SIZE 1 -+/* Bit: 'PHYIE2' */ -+/* Description: 'PHY Initial Enable for port 2' */ -+#define TANTOS_3G_PHYIC2_PHYIE2_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE2_SHIFT 10 -+#define TANTOS_3G_PHYIC2_PHYIE2_SIZE 1 -+/* Bit: 'PHYIE1' */ -+/* Description: 'PHY Initial Enable for port 1' */ -+#define TANTOS_3G_PHYIC2_PHYIE1_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE1_SHIFT 9 -+#define TANTOS_3G_PHYIC2_PHYIE1_SIZE 1 -+/* Bit: 'PHYIE0' */ -+/* Description: 'PHY Initial Enable for port 0' */ -+#define TANTOS_3G_PHYIC2_PHYIE0_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_PHYIE0_SHIFT 8 -+#define TANTOS_3G_PHYIC2_PHYIE0_SIZE 1 -+/* Bit: 'REGA0' */ -+/* Description: 'Register Address 0' */ -+#define TANTOS_3G_PHYIC2_REGA0_OFFSET 0xD4 -+#define TANTOS_3G_PHYIC2_REGA0_SHIFT 0 -+#define TANTOS_3G_PHYIC2_REGA0_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Control 3 Register' */ -+/* Bit: 'PHYIE6' */ -+/* Description: 'PHY Initial Enable for port 6' */ -+#define TANTOS_3G_PHYIC3_PHYIE6_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE6_SHIFT 14 -+#define TANTOS_3G_PHYIC3_PHYIE6_SIZE 1 -+/* Bit: 'PHYIE5' */ -+/* Description: 'PHY Initial Enable for port 5' */ -+#define TANTOS_3G_PHYIC3_PHYIE5_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE5_SHIFT 13 -+#define TANTOS_3G_PHYIC3_PHYIE5_SIZE 1 -+/* Bit: 'PHYIE4' */ -+/* Description: 'PHY Initial Enable for port 4' */ -+#define TANTOS_3G_PHYIC3_PHYIE4_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE4_SHIFT 12 -+#define TANTOS_3G_PHYIC3_PHYIE4_SIZE 1 -+/* Bit: 'PHYIE3' */ -+/* Description: 'PHY Initial Enable for port 3' */ -+#define TANTOS_3G_PHYIC3_PHYIE3_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE3_SHIFT 11 -+#define TANTOS_3G_PHYIC3_PHYIE3_SIZE 1 -+/* Bit: 'PHYIE2' */ -+/* Description: 'PHY Initial Enable for port 2' */ -+#define TANTOS_3G_PHYIC3_PHYIE2_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE2_SHIFT 10 -+#define TANTOS_3G_PHYIC3_PHYIE2_SIZE 1 -+/* Bit: 'PHYIE1' */ -+/* Description: 'PHY Initial Enable for port 1' */ -+#define TANTOS_3G_PHYIC3_PHYIE1_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE1_SHIFT 9 -+#define TANTOS_3G_PHYIC3_PHYIE1_SIZE 1 -+/* Bit: 'PHYIE0' */ -+/* Description: 'PHY Initial Enable for port 0' */ -+#define TANTOS_3G_PHYIC3_PHYIE0_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_PHYIE0_SHIFT 8 -+#define TANTOS_3G_PHYIC3_PHYIE0_SIZE 1 -+/* Bit: 'REGA0' */ -+/* Description: 'Register Address 0' */ -+#define TANTOS_3G_PHYIC3_REGA0_OFFSET 0xD6 -+#define TANTOS_3G_PHYIC3_REGA0_SHIFT 0 -+#define TANTOS_3G_PHYIC3_REGA0_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Data 0 Register' */ -+/* Bit: 'REGD0' */ -+/* Description: 'Register Data 0' */ -+#define TANTOS_3G_PHYID0_REGD0_OFFSET 0xD1 -+#define TANTOS_3G_PHYID0_REGD0_SHIFT 0 -+#define TANTOS_3G_PHYID0_REGD0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Data 1 Register' */ -+/* Bit: 'REGD1' */ -+/* Description: 'Register Data 0' */ -+#define TANTOS_3G_PHYID1_REGD1_OFFSET 0xD3 -+#define TANTOS_3G_PHYID1_REGD1_SHIFT 0 -+#define TANTOS_3G_PHYID1_REGD1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Data 2 Register' */ -+/* Bit: 'REGD2' */ -+/* Description: 'Register Data 0' */ -+#define TANTOS_3G_PHYID2_REGD2_OFFSET 0xD5 -+#define TANTOS_3G_PHYID2_REGD2_SHIFT 0 -+#define TANTOS_3G_PHYID2_REGD2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Initial Data 3 Register' */ -+/* Bit: 'REGD3' */ -+/* Description: 'Register Data 0' */ -+#define TANTOS_3G_PHYID3_REGD3_OFFSET 0xD7 -+#define TANTOS_3G_PHYID3_REGD3_SHIFT 0 -+#define TANTOS_3G_PHYID3_REGD3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Enable Register' */ -+/* Bit: 'LTADIE' */ -+/* Description: 'Leaning Table Access Done Interrupt Enable' */ -+#define TANTOS_3G_IE_LTADIE_OFFSET 0xD8 -+#define TANTOS_3G_IE_LTADIE_SHIFT 8 -+#define TANTOS_3G_IE_LTADIE_SIZE 1 -+/* Bit: 'PSVIE' */ -+/* Description: 'Port Security Violation Interrupt Enable' */ -+#define TANTOS_3G_IE_PSVIE_OFFSET 0xD8 -+#define TANTOS_3G_IE_PSVIE_SHIFT 1 -+#define TANTOS_3G_IE_PSVIE_SIZE 7 -+/* Bit: 'PSCIE' */ -+/* Description: 'Port Status Change Interrupt Enable' */ -+#define TANTOS_3G_IE_PSCIE_OFFSET 0xD8 -+#define TANTOS_3G_IE_PSCIE_SHIFT 0 -+#define TANTOS_3G_IE_PSCIE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Status Register' */ -+/* Bit: 'LTAD' */ -+/* Description: 'Leaning Table Access Done' */ -+#define TANTOS_3G_IS_LTAD_OFFSET 0xD9 -+#define TANTOS_3G_IS_LTAD_SHIFT 8 -+#define TANTOS_3G_IS_LTAD_SIZE 1 -+/* Bit: 'PSV' */ -+/* Description: 'Port Security Violation' */ -+#define TANTOS_3G_IS_PSV_OFFSET 0xD9 -+#define TANTOS_3G_IS_PSV_SHIFT 1 -+#define TANTOS_3G_IS_PSV_SIZE 7 -+/* Bit: 'PSC' */ -+/* Description: 'Port Status Change' */ -+#define TANTOS_3G_IS_PSC_OFFSET 0xD9 -+#define TANTOS_3G_IS_PSC_SHIFT 0 -+#define TANTOS_3G_IS_PSC_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter Action 0' */ -+/* Bit: 'ATF7' */ -+/* Description: 'Action for Type Filter 7' */ -+#define TANTOS_3G_TFA0_ATF7_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF7_SHIFT 14 -+#define TANTOS_3G_TFA0_ATF7_SIZE 2 -+/* Bit: 'ATF6' */ -+/* Description: 'Action for Type Filter 6' */ -+#define TANTOS_3G_TFA0_ATF6_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF6_SHIFT 12 -+#define TANTOS_3G_TFA0_ATF6_SIZE 2 -+/* Bit: 'ATF5' */ -+/* Description: 'Action for Type Filter 5' */ -+#define TANTOS_3G_TFA0_ATF5_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF5_SHIFT 10 -+#define TANTOS_3G_TFA0_ATF5_SIZE 2 -+/* Bit: 'ATF4' */ -+/* Description: 'Action for Type Filter 4' */ -+#define TANTOS_3G_TFA0_ATF4_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF4_SHIFT 8 -+#define TANTOS_3G_TFA0_ATF4_SIZE 2 -+/* Bit: 'ATF3' */ -+/* Description: 'Action for Type Filter 3' */ -+#define TANTOS_3G_TFA0_ATF3_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF3_SHIFT 6 -+#define TANTOS_3G_TFA0_ATF3_SIZE 2 -+/* Bit: 'ATF2' */ -+/* Description: 'Action for Type Filter 2' */ -+#define TANTOS_3G_TFA0_ATF2_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF2_SHIFT 4 -+#define TANTOS_3G_TFA0_ATF2_SIZE 2 -+/* Bit: 'ATF1' */ -+/* Description: 'Action for Type Filter 1' */ -+#define TANTOS_3G_TFA0_ATF1_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF1_SHIFT 2 -+#define TANTOS_3G_TFA0_ATF1_SIZE 2 -+/* Bit: 'ATF0' */ -+/* Description: 'Action for Type Filter 0' */ -+#define TANTOS_3G_TFA0_ATF0_OFFSET 0xDA -+#define TANTOS_3G_TFA0_ATF0_SHIFT 0 -+#define TANTOS_3G_TFA0_ATF0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Type Filter Action 1' */ -+/* Bit: 'QATF7' */ -+/* Description: 'Destination Queue for Type Filter 7' */ -+#define TANTOS_3G_TFA1_QATF7_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QATF7_SHIFT 14 -+#define TANTOS_3G_TFA1_QATF7_SIZE 2 -+/* Bit: 'QATF6' */ -+/* Description: 'Destination Queue for Type Filter 6' */ -+#define TANTOS_3G_TFA1_QATF6_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QATF6_SHIFT 12 -+#define TANTOS_3G_TFA1_QATF6_SIZE 2 -+/* Bit: 'QTF5' */ -+/* Description: 'Destination Queue for Type Filter 5' */ -+#define TANTOS_3G_TFA1_QTF5_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF5_SHIFT 10 -+#define TANTOS_3G_TFA1_QTF5_SIZE 2 -+/* Bit: 'QTF4' */ -+/* Description: 'Destination Queue for Type Filter 4' */ -+#define TANTOS_3G_TFA1_QTF4_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF4_SHIFT 8 -+#define TANTOS_3G_TFA1_QTF4_SIZE 2 -+/* Bit: 'QTF3' */ -+/* Description: 'Destination Queue for Type Filter 3' */ -+#define TANTOS_3G_TFA1_QTF3_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF3_SHIFT 6 -+#define TANTOS_3G_TFA1_QTF3_SIZE 2 -+/* Bit: 'QTF2' */ -+/* Description: 'Destination Queue for Type Filter 2' */ -+#define TANTOS_3G_TFA1_QTF2_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF2_SHIFT 4 -+#define TANTOS_3G_TFA1_QTF2_SIZE 2 -+/* Bit: 'QTF1' */ -+/* Description: 'Destination Queue for Type Filter 1' */ -+#define TANTOS_3G_TFA1_QTF1_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF1_SHIFT 2 -+#define TANTOS_3G_TFA1_QTF1_SIZE 2 -+/* Bit: 'QTF0' */ -+/* Description: 'Destination Queue for Type Filter 0' */ -+#define TANTOS_3G_TFA1_QTF0_OFFSET 0xDB -+#define TANTOS_3G_TFA1_QTF0_SHIFT 0 -+#define TANTOS_3G_TFA1_QTF0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'ARP/RARP Register' */ -+/* Bit: 'MACA' */ -+/* Description: 'MAC Control Action' */ -+#define TANTOS_3G_AR_MACA_OFFSET 0xDC -+#define TANTOS_3G_AR_MACA_SHIFT 14 -+#define TANTOS_3G_AR_MACA_SIZE 2 -+/* Bit: 'UPT' */ -+/* Description: 'Unicast packet Treated as Cross_VLAN packet' */ -+#define TANTOS_3G_AR_UPT_OFFSET 0xDC -+#define TANTOS_3G_AR_UPT_SHIFT 13 -+#define TANTOS_3G_AR_UPT_SIZE 1 -+/* Bit: 'RPT' */ -+/* Description: 'RARP Packet Treated as Cross_VLAN Packet' */ -+#define TANTOS_3G_AR_RPT_OFFSET 0xDC -+#define TANTOS_3G_AR_RPT_SHIFT 12 -+#define TANTOS_3G_AR_RPT_SIZE 1 -+/* Bit: 'RAPA' */ -+/* Description: 'RARP/ARP Packet Action' */ -+#define TANTOS_3G_AR_RAPA_OFFSET 0xDC -+#define TANTOS_3G_AR_RAPA_SHIFT 10 -+#define TANTOS_3G_AR_RAPA_SIZE 2 -+/* Bit: 'RAPPE' */ -+/* Description: 'RARP/ARP Packet Priority Enable' */ -+#define TANTOS_3G_AR_RAPPE_OFFSET 0xDC -+#define TANTOS_3G_AR_RAPPE_SHIFT 9 -+#define TANTOS_3G_AR_RAPPE_SIZE 1 -+/* Bit: 'RAPP' */ -+/* Description: 'RARP/ARP Packet Priority' */ -+#define TANTOS_3G_AR_RAPP_OFFSET 0xDC -+#define TANTOS_3G_AR_RAPP_SHIFT 7 -+#define TANTOS_3G_AR_RAPP_SIZE 2 -+/* Bit: 'RAPOTH' */ -+/* Description: 'RARP/ARP Packet Output Tag Handle' */ -+#define TANTOS_3G_AR_RAPOTH_OFFSET 0xDC -+#define TANTOS_3G_AR_RAPOTH_SHIFT 5 -+#define TANTOS_3G_AR_RAPOTH_SIZE 2 -+/* Bit: 'APT' */ -+/* Description: 'ARP Packet Treated as Cross _ VLAN Packet' */ -+#define TANTOS_3G_AR_APT_OFFSET 0xDC -+#define TANTOS_3G_AR_APT_SHIFT 4 -+#define TANTOS_3G_AR_APT_SIZE 1 -+/* Bit: 'RAPTM' */ -+/* Description: 'RARP/ARP Packet Treated as Management Packet' */ -+#define TANTOS_3G_AR_RAPTM_OFFSET 0xDC -+#define TANTOS_3G_AR_RAPTM_SHIFT 3 -+#define TANTOS_3G_AR_RAPTM_SIZE 1 -+/* Bit: 'TAPTS' */ -+/* Description: 'RARP/ARP Packet Treated as Span Packet' */ -+#define TANTOS_3G_AR_TAPTS_OFFSET 0xDC -+#define TANTOS_3G_AR_TAPTS_SHIFT 2 -+#define TANTOS_3G_AR_TAPTS_SIZE 1 -+/* Bit: 'TAP' */ -+/* Description: 'Trap ARP Packet' */ -+#define TANTOS_3G_AR_TAP_OFFSET 0xDC -+#define TANTOS_3G_AR_TAP_SHIFT 1 -+#define TANTOS_3G_AR_TAP_SIZE 1 -+/* Bit: 'TRP' */ -+/* Description: 'Trap RARP Packet' */ -+#define TANTOS_3G_AR_TRP_OFFSET 0xDC -+#define TANTOS_3G_AR_TRP_SHIFT 0 -+#define TANTOS_3G_AR_TRP_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Packet Identification Option' */ -+/* Bit: 'DIVS' */ -+/* Description: 'Do not Identify VLAN after SNAP' */ -+#define TANTOS_3G_PIOFGPM_DIVS_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DIVS_SHIFT 14 -+#define TANTOS_3G_PIOFGPM_DIVS_SIZE 1 -+/* Bit: 'DII6P' */ -+/* Description: 'Do not Identify IPV6 in PPPOE' */ -+#define TANTOS_3G_PIOFGPM_DII6P_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DII6P_SHIFT 13 -+#define TANTOS_3G_PIOFGPM_DII6P_SIZE 1 -+/* Bit: 'DIIPS' */ -+/* Description: 'Do not Identify IP in PPPOE after SNAP' */ -+#define TANTOS_3G_PIOFGPM_DIIPS_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DIIPS_SHIFT 12 -+#define TANTOS_3G_PIOFGPM_DIIPS_SIZE 1 -+/* Bit: 'DIE' */ -+/* Description: 'Do not Identify Ether-Type = 0x0800, IP VER = 6 -+as IPV6 packets' */ -+#define TANTOS_3G_PIOFGPM_DIE_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DIE_SHIFT 11 -+#define TANTOS_3G_PIOFGPM_DIE_SIZE 1 -+/* Bit: 'DIIP' */ -+/* Description: 'Do not Identify IP in PPPOE' */ -+#define TANTOS_3G_PIOFGPM_DIIP_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DIIP_SHIFT 10 -+#define TANTOS_3G_PIOFGPM_DIIP_SIZE 1 -+/* Bit: 'DIS' */ -+/* Description: 'Do not Identify SNAP' */ -+#define TANTOS_3G_PIOFGPM_DIS_OFFSET 0xDD -+#define TANTOS_3G_PIOFGPM_DIS_SHIFT 9 -+#define TANTOS_3G_PIOFGPM_DIS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch Global Control Register 1' */ -+/* Bit: 'TSIPGE' */ -+/* Description: 'Transmit Short IPG Enable' */ -+#define TANTOS_3G_SGC1_TSIPGE_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_TSIPGE_SHIFT 15 -+#define TANTOS_3G_SGC1_TSIPGE_SIZE 1 -+/* Bit: 'PHYBA' */ -+/* Description: 'PHY Base Address' */ -+#define TANTOS_3G_SGC1_PHYBA_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_PHYBA_SHIFT 14 -+#define TANTOS_3G_SGC1_PHYBA_SIZE 1 -+/* Bit: 'DPWECH' */ -+/* Description: 'Drop Packet When Excessive Collision Happen' */ -+#define TANTOS_3G_SGC1_DPWECH_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_DPWECH_SHIFT 13 -+#define TANTOS_3G_SGC1_DPWECH_SIZE 1 -+/* Bit: 'ATS' */ -+/* Description: 'Aging Timer Select' */ -+#define TANTOS_3G_SGC1_ATS_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_ATS_SHIFT 10 -+#define TANTOS_3G_SGC1_ATS_SIZE 3 -+/* Bit: 'MPL' */ -+/* Description: 'Max Packet Length (MAXPKTLEN)' */ -+#define TANTOS_3G_SGC1_MPL_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_MPL_SHIFT 8 -+#define TANTOS_3G_SGC1_MPL_SIZE 2 -+/* Bit: 'DMQ3' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q3)' */ -+#define TANTOS_3G_SGC1_DMQ3_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_DMQ3_SHIFT 6 -+#define TANTOS_3G_SGC1_DMQ3_SIZE 2 -+/* Bit: 'DMQ2' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q2)' */ -+#define TANTOS_3G_SGC1_DMQ2_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_DMQ2_SHIFT 4 -+#define TANTOS_3G_SGC1_DMQ2_SIZE 2 -+/* Bit: 'DMQ1' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q1)' */ -+#define TANTOS_3G_SGC1_DMQ1_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_DMQ1_SHIFT 2 -+#define TANTOS_3G_SGC1_DMQ1_SIZE 2 -+/* Bit: 'DMQ0' */ -+/* Description: 'Discard Mode (Drop scheme for Packets Classified -+as Q0)' */ -+#define TANTOS_3G_SGC1_DMQ0_OFFSET 0xE0 -+#define TANTOS_3G_SGC1_DMQ0_SHIFT 0 -+#define TANTOS_3G_SGC1_DMQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch Global Control Register 2' */ -+/* Bit: 'SE' */ -+/* Description: 'Switch Enable. (when WAIT_INIT=1)' */ -+#define TANTOS_3G_SGC2_SE_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_SE_SHIFT 15 -+#define TANTOS_3G_SGC2_SE_SIZE 1 -+/* Bit: 'ICRCCD' */ -+/* Description: 'CRC Check Disable' */ -+#define TANTOS_3G_SGC2_ICRCCD_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_ICRCCD_SHIFT 14 -+#define TANTOS_3G_SGC2_ICRCCD_SIZE 1 -+/* Bit: 'ITRUNK' */ -+/* Description: 'Port 2 and Port 3 Trunk Enable' */ -+#define TANTOS_3G_SGC2_ITRUNK_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_ITRUNK_SHIFT 12 -+#define TANTOS_3G_SGC2_ITRUNK_SIZE 1 -+/* Bit: 'ITENLMT' */ -+/* Description: '10Mbit/s Drop Packet before 100Mbit/s Enable' */ -+#define TANTOS_3G_SGC2_ITENLMT_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_ITENLMT_SHIFT 11 -+#define TANTOS_3G_SGC2_ITENLMT_SIZE 1 -+/* Bit: 'RVID0' */ -+/* Description: 'Replace VID0' */ -+#define TANTOS_3G_SGC2_RVID0_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_RVID0_SHIFT 9 -+#define TANTOS_3G_SGC2_RVID0_SIZE 1 -+/* Bit: 'RVID1' */ -+/* Description: 'Replace VID1' */ -+#define TANTOS_3G_SGC2_RVID1_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_RVID1_SHIFT 8 -+#define TANTOS_3G_SGC2_RVID1_SIZE 1 -+/* Bit: 'RVIDFFF' */ -+/* Description: 'Replace VIDFFF' */ -+#define TANTOS_3G_SGC2_RVIDFFF_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_RVIDFFF_SHIFT 7 -+#define TANTOS_3G_SGC2_RVIDFFF_SIZE 1 -+/* Bit: 'DUPCOLSP' */ -+/* Description: 'Dupcol LED Separate' */ -+#define TANTOS_3G_SGC2_DUPCOLSP_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_DUPCOLSP_SHIFT 6 -+#define TANTOS_3G_SGC2_DUPCOLSP_SIZE 1 -+/* Bit: 'PCR' */ -+/* Description: 'Priority Change Rule' */ -+#define TANTOS_3G_SGC2_PCR_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_PCR_SHIFT 4 -+#define TANTOS_3G_SGC2_PCR_SIZE 1 -+/* Bit: 'PCE' */ -+/* Description: 'Priority Change Enable' */ -+#define TANTOS_3G_SGC2_PCE_OFFSET 0xE1 -+#define TANTOS_3G_SGC2_PCE_SHIFT 3 -+#define TANTOS_3G_SGC2_PCE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'CPU Port & Mirror Control Register' */ -+/* Bit: 'SPN' */ -+/* Description: 'Sniffer Port Number' */ -+#define TANTOS_3G_CMH_SPN_OFFSET 0xE2 -+#define TANTOS_3G_CMH_SPN_SHIFT 13 -+#define TANTOS_3G_CMH_SPN_SIZE 3 -+/* Bit: 'MCA' */ -+/* Description: 'Mirror CRC Also' */ -+#define TANTOS_3G_CMH_MCA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_MCA_SHIFT 12 -+#define TANTOS_3G_CMH_MCA_SIZE 1 -+/* Bit: 'MRA' */ -+/* Description: 'Mirror RXER Also' */ -+#define TANTOS_3G_CMH_MRA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_MRA_SHIFT 11 -+#define TANTOS_3G_CMH_MRA_SIZE 1 -+/* Bit: 'MPA' */ -+/* Description: 'Mirror PAUSE Also' */ -+#define TANTOS_3G_CMH_MPA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_MPA_SHIFT 10 -+#define TANTOS_3G_CMH_MPA_SIZE 1 -+/* Bit: 'MLA' */ -+/* Description: 'Mirror Long Also' */ -+#define TANTOS_3G_CMH_MLA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_MLA_SHIFT 9 -+#define TANTOS_3G_CMH_MLA_SIZE 1 -+/* Bit: 'MSA' */ -+/* Description: 'Mirror Short Also' */ -+#define TANTOS_3G_CMH_MSA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_MSA_SHIFT 8 -+#define TANTOS_3G_CMH_MSA_SIZE 1 -+/* Bit: 'CPN' */ -+/* Description: 'CPU Port Number' */ -+#define TANTOS_3G_CMH_CPN_OFFSET 0xE2 -+#define TANTOS_3G_CMH_CPN_SHIFT 5 -+#define TANTOS_3G_CMH_CPN_SIZE 3 -+/* Bit: 'STRE' */ -+/* Description: 'Special TAG Receive Enable' */ -+#define TANTOS_3G_CMH_STRE_OFFSET 0xE2 -+#define TANTOS_3G_CMH_STRE_SHIFT 4 -+#define TANTOS_3G_CMH_STRE_SIZE 1 -+/* Bit: 'STTE' */ -+/* Description: 'Special TAG Transmit Enable' */ -+#define TANTOS_3G_CMH_STTE_OFFSET 0xE2 -+#define TANTOS_3G_CMH_STTE_SHIFT 3 -+#define TANTOS_3G_CMH_STTE_SIZE 1 -+/* Bit: 'PAST' */ -+/* Description: 'Pause also adds Special Tag when Special TAG Transmit -+is enabled' */ -+#define TANTOS_3G_CMH_PAST_OFFSET 0xE2 -+#define TANTOS_3G_CMH_PAST_SHIFT 2 -+#define TANTOS_3G_CMH_PAST_SIZE 1 -+/* Bit: 'CCCRC' */ -+/* Description: 'CPU Port doesn't check CRC for packets with Special -+Tag' */ -+#define TANTOS_3G_CMH_CCCRC_OFFSET 0xE2 -+#define TANTOS_3G_CMH_CCCRC_SHIFT 1 -+#define TANTOS_3G_CMH_CCCRC_SIZE 1 -+/* Bit: 'IGSTA' */ -+/* Description: 'Interframe gap for Special Tag application' */ -+#define TANTOS_3G_CMH_IGSTA_OFFSET 0xE2 -+#define TANTOS_3G_CMH_IGSTA_SHIFT 0 -+#define TANTOS_3G_CMH_IGSTA_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Multicast Snooping Register' */ -+/* Bit: 'SCPA' */ -+/* Description: 'Snooping Control Packet Action' */ -+#define TANTOS_3G_MS_SCPA_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPA_SHIFT 14 -+#define TANTOS_3G_MS_SCPA_SIZE 2 -+/* Bit: 'SCPPE' */ -+/* Description: 'Snooping Control Packet Priority Enable' */ -+#define TANTOS_3G_MS_SCPPE_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPPE_SHIFT 13 -+#define TANTOS_3G_MS_SCPPE_SIZE 1 -+/* Bit: 'SCPP' */ -+/* Description: 'Snooping Control Packet Priority' */ -+#define TANTOS_3G_MS_SCPP_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPP_SHIFT 11 -+#define TANTOS_3G_MS_SCPP_SIZE 2 -+/* Bit: 'SCPTTH' */ -+/* Description: 'Snooping Control Packet Transmission Tag Handle' */ -+#define TANTOS_3G_MS_SCPTTH_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPTTH_SHIFT 9 -+#define TANTOS_3G_MS_SCPTTH_SIZE 2 -+/* Bit: 'SCPTCP' */ -+/* Description: 'Snooping Control Packet Treated as Cross_VLAN Packet' */ -+#define TANTOS_3G_MS_SCPTCP_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPTCP_SHIFT 8 -+#define TANTOS_3G_MS_SCPTCP_SIZE 1 -+/* Bit: 'SCPTMP' */ -+/* Description: 'Snooping Control Packet Treated as Management Packet' */ -+#define TANTOS_3G_MS_SCPTMP_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPTMP_SHIFT 7 -+#define TANTOS_3G_MS_SCPTMP_SIZE 1 -+/* Bit: 'SCPTSP' */ -+/* Description: 'Snooping Control Packet Treated as Span Packet' */ -+#define TANTOS_3G_MS_SCPTSP_OFFSET 0xE3 -+#define TANTOS_3G_MS_SCPTSP_SHIFT 6 -+#define TANTOS_3G_MS_SCPTSP_SIZE 1 -+/* Bit: 'ASC' */ -+/* Description: 'Additional Snooping Control. These bits are used -+when the packets on the incoming port with the Ethernet destination -+address = 01-00-5E-XX-XX-XX/33-33-XX-XX-XX-XX are not IGMP_IP/MLD_IPV/ MLD_IPV6 -+packets and not found in the learning table or the hardware IGMP -+table' */ -+#define TANTOS_3G_MS_ASC_OFFSET 0xE3 -+#define TANTOS_3G_MS_ASC_SHIFT 4 -+#define TANTOS_3G_MS_ASC_SIZE 2 -+/* Bit: 'IPMPT' */ -+/* Description: 'IP Multicast Packet Treated as Cross_VLAN packet' */ -+#define TANTOS_3G_MS_IPMPT_OFFSET 0xE3 -+#define TANTOS_3G_MS_IPMPT_SHIFT 2 -+#define TANTOS_3G_MS_IPMPT_SIZE 1 -+/* Bit: 'RV' */ -+/* Description: 'Robust Variable' */ -+#define TANTOS_3G_MS_RV_OFFSET 0xE3 -+#define TANTOS_3G_MS_RV_SHIFT 0 -+#define TANTOS_3G_MS_RV_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Hardware IGMP Control Register' */ -+/* Bit: 'QI' */ -+/* Description: 'Query Interval' */ -+#define TANTOS_3G_HIC_QI_OFFSET 0xE4 -+#define TANTOS_3G_HIC_QI_SHIFT 8 -+#define TANTOS_3G_HIC_QI_SIZE 8 -+/* Bit: 'HIPI' */ -+/* Description: 'Hardware IGMP Packet Ignore CPU Port' */ -+#define TANTOS_3G_HIC_HIPI_OFFSET 0xE4 -+#define TANTOS_3G_HIC_HIPI_SHIFT 7 -+#define TANTOS_3G_HIC_HIPI_SIZE 1 -+/* Bit: 'DRP' */ -+/* Description: 'Default Router Portmap' */ -+#define TANTOS_3G_HIC_DRP_OFFSET 0xE4 -+#define TANTOS_3G_HIC_DRP_SHIFT 0 -+#define TANTOS_3G_HIC_DRP_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Unicast Port Map and Broadcast Port Map' */ -+/* Bit: 'UP' */ -+/* Description: 'Unicast Portmap' */ -+#define TANTOS_3G_UPMBPM_UP_OFFSET 0xE5 -+#define TANTOS_3G_UPMBPM_UP_SHIFT 8 -+#define TANTOS_3G_UPMBPM_UP_SIZE 7 -+/* Bit: 'BP' */ -+/* Description: 'Broadcast Portmap' */ -+#define TANTOS_3G_UPMBPM_BP_OFFSET 0xE5 -+#define TANTOS_3G_UPMBPM_BP_SHIFT 0 -+#define TANTOS_3G_UPMBPM_BP_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Multicast Port Map and Reserve Port Map' */ -+/* Bit: 'MP' */ -+/* Description: 'Multicast Portmap' */ -+#define TANTOS_3G_MPMRPM_MP_OFFSET 0xE6 -+#define TANTOS_3G_MPMRPM_MP_SHIFT 8 -+#define TANTOS_3G_MPMRPM_MP_SIZE 7 -+/* Bit: 'RP' */ -+/* Description: 'Reserve Portmap' */ -+#define TANTOS_3G_MPMRPM_RP_OFFSET 0xE6 -+#define TANTOS_3G_MPMRPM_RP_SHIFT 0 -+#define TANTOS_3G_MPMRPM_RP_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Protocol Filter Action' */ -+/* Bit: 'APF7' */ -+/* Description: 'Action for Protocol Filter 7' */ -+#define TANTOS_3G_PFA_APF7_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF7_SHIFT 14 -+#define TANTOS_3G_PFA_APF7_SIZE 2 -+/* Bit: 'APF6' */ -+/* Description: 'Action for Protocol Filter 6' */ -+#define TANTOS_3G_PFA_APF6_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF6_SHIFT 12 -+#define TANTOS_3G_PFA_APF6_SIZE 2 -+/* Bit: 'APF5' */ -+/* Description: 'Action for Protocol Filter 5' */ -+#define TANTOS_3G_PFA_APF5_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF5_SHIFT 10 -+#define TANTOS_3G_PFA_APF5_SIZE 2 -+/* Bit: 'APF4' */ -+/* Description: 'Action for Protocol Filter 4' */ -+#define TANTOS_3G_PFA_APF4_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF4_SHIFT 8 -+#define TANTOS_3G_PFA_APF4_SIZE 2 -+/* Bit: 'APF3' */ -+/* Description: 'Action for Protocol Filter 3' */ -+#define TANTOS_3G_PFA_APF3_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF3_SHIFT 6 -+#define TANTOS_3G_PFA_APF3_SIZE 2 -+/* Bit: 'APF2' */ -+/* Description: 'Action for Protocol Filter 2' */ -+#define TANTOS_3G_PFA_APF2_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF2_SHIFT 4 -+#define TANTOS_3G_PFA_APF2_SIZE 2 -+/* Bit: 'APF1' */ -+/* Description: 'Action for Protocol Filter 1' */ -+#define TANTOS_3G_PFA_APF1_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF1_SHIFT 2 -+#define TANTOS_3G_PFA_APF1_SIZE 2 -+/* Bit: 'APF0' */ -+/* Description: 'Action for Protocol Filter 0' */ -+#define TANTOS_3G_PFA_APF0_OFFSET 0xE7 -+#define TANTOS_3G_PFA_APF0_SHIFT 0 -+#define TANTOS_3G_PFA_APF0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: '802.1p Priority Map Register' */ -+/* Bit: '1PPQ7' */ -+/* Description: 'Priority Queue 7' */ -+#define TANTOS_3G_1PPM_1PPQ7_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ7_SHIFT 14 -+#define TANTOS_3G_1PPM_1PPQ7_SIZE 2 -+/* Bit: '1PPQ6' */ -+/* Description: 'Priority Queue 6' */ -+#define TANTOS_3G_1PPM_1PPQ6_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ6_SHIFT 12 -+#define TANTOS_3G_1PPM_1PPQ6_SIZE 2 -+/* Bit: '1PPQ5' */ -+/* Description: 'Priority Queue 5' */ -+#define TANTOS_3G_1PPM_1PPQ5_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ5_SHIFT 10 -+#define TANTOS_3G_1PPM_1PPQ5_SIZE 2 -+/* Bit: '1PPQ4' */ -+/* Description: 'Priority Queue 4' */ -+#define TANTOS_3G_1PPM_1PPQ4_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ4_SHIFT 8 -+#define TANTOS_3G_1PPM_1PPQ4_SIZE 2 -+/* Bit: '1PPQ3' */ -+/* Description: 'Priority Queue 3' */ -+#define TANTOS_3G_1PPM_1PPQ3_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ3_SHIFT 6 -+#define TANTOS_3G_1PPM_1PPQ3_SIZE 2 -+/* Bit: '1PPQ2' */ -+/* Description: 'Priority Queue 2' */ -+#define TANTOS_3G_1PPM_1PPQ2_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ2_SHIFT 4 -+#define TANTOS_3G_1PPM_1PPQ2_SIZE 2 -+/* Bit: '1PPQ1' */ -+/* Description: 'Priority Queue 1' */ -+#define TANTOS_3G_1PPM_1PPQ1_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ1_SHIFT 2 -+#define TANTOS_3G_1PPM_1PPQ1_SIZE 2 -+/* Bit: '1PPQ0' */ -+/* Description: 'Priority Queue 0' */ -+#define TANTOS_3G_1PPM_1PPQ0_OFFSET 0xE8 -+#define TANTOS_3G_1PPM_1PPQ0_SHIFT 0 -+#define TANTOS_3G_1PPM_1PPQ0_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch MAC Address Register 1' */ -+/* Bit: 'ADDR47_41' */ -+/* Description: 'Address [47:41]' */ -+#define TANTOS_3G_SMA1_ADDR47_41_OFFSET 0xE9 -+#define TANTOS_3G_SMA1_ADDR47_41_SHIFT 9 -+#define TANTOS_3G_SMA1_ADDR47_41_SIZE 7 -+/* Bit: 'PAC' */ -+/* Description: 'Pause Address Change' */ -+#define TANTOS_3G_SMA1_PAC_OFFSET 0xE9 -+#define TANTOS_3G_SMA1_PAC_SHIFT 8 -+#define TANTOS_3G_SMA1_PAC_SIZE 1 -+/* Bit: 'ADDR39_32' */ -+/* Description: 'Address [39:32]' */ -+#define TANTOS_3G_SMA1_ADDR39_32_OFFSET 0xE9 -+#define TANTOS_3G_SMA1_ADDR39_32_SHIFT 0 -+#define TANTOS_3G_SMA1_ADDR39_32_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch MAC Address Register 2' */ -+/* Bit: 'ADDR31_16' */ -+/* Description: 'Address [31:16]' */ -+#define TANTOS_3G_SMA2_ADDR31_16_OFFSET 0xEA -+#define TANTOS_3G_SMA2_ADDR31_16_SHIFT 0 -+#define TANTOS_3G_SMA2_ADDR31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Switch MAC Address Register 3' */ -+/* Bit: 'ADDR15_0' */ -+/* Description: 'Address [15:0]' */ -+#define TANTOS_3G_SMA3_ADDR15_0_OFFSET 0xEB -+#define TANTOS_3G_SMA3_ADDR15_0_SHIFT 0 -+#define TANTOS_3G_SMA3_ADDR15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Global Bucket Size Base counter' */ -+/* Bit: 'Base15_0' */ -+/* Description: 'Base[15:0]' */ -+#define TANTOS_3G_GBSBC_BASE15_0_OFFSET 0xEC -+#define TANTOS_3G_GBSBC_BASE15_0_SHIFT 0 -+#define TANTOS_3G_GBSBC_BASE15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Global Bucket Size Extend Base Counter' */ -+/* Bit: 'EBase15_0' */ -+/* Description: 'Extend Base[15:0]' */ -+#define TANTOS_3G_GBSEBC_EBASE15_0_OFFSET 0xED -+#define TANTOS_3G_GBSEBC_EBASE15_0_SHIFT 0 -+#define TANTOS_3G_GBSEBC_EBASE15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Global Bucket Size Counter High Bits' */ -+/* Bit: 'EBase17_16' */ -+/* Description: 'EBase[17:16]' */ -+#define TANTOS_3G_GBSCHB_EBASE17_16_OFFSET 0xEE -+#define TANTOS_3G_GBSCHB_EBASE17_16_SHIFT 8 -+#define TANTOS_3G_GBSCHB_EBASE17_16_SIZE 2 -+/* Bit: 'Base17_16' */ -+/* Description: 'Base[17:16]' */ -+#define TANTOS_3G_GBSCHB_BASE17_16_OFFSET 0xEE -+#define TANTOS_3G_GBSCHB_BASE17_16_SHIFT 0 -+#define TANTOS_3G_GBSCHB_BASE17_16_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Congestion Control register' */ -+/* Bit: 'EDSTX' */ -+/* Description: 'Drop scheme selection' */ -+#define TANTOS_3G_CCR_EDSTX_OFFSET 0xEF -+#define TANTOS_3G_CCR_EDSTX_SHIFT 15 -+#define TANTOS_3G_CCR_EDSTX_SIZE 1 -+/* Bit: 'IRSJA' */ -+/* Description: 'IGMP Report Supression and Join Aggregation control' */ -+#define TANTOS_3G_CCR_IRSJA_OFFSET 0xEF -+#define TANTOS_3G_CCR_IRSJA_SHIFT 8 -+#define TANTOS_3G_CCR_IRSJA_SIZE 2 -+/* Bit: 'IJT' */ -+/* Description: 'Input Jam Threshold' */ -+#define TANTOS_3G_CCR_IJT_OFFSET 0xEF -+#define TANTOS_3G_CCR_IJT_SHIFT 0 -+#define TANTOS_3G_CCR_IJT_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Storm control Register 0' */ -+/* Bit: 'STORM_B' */ -+/* Description: 'Storm Enable for Broadcast Packets' */ -+#define TANTOS_3G_SCR0_STORM_B_OFFSET 0xF0 -+#define TANTOS_3G_SCR0_STORM_B_SHIFT 15 -+#define TANTOS_3G_SCR0_STORM_B_SIZE 1 -+/* Bit: 'STORM_M' */ -+/* Description: 'Storm Enable for Multicast Packets' */ -+#define TANTOS_3G_SCR0_STORM_M_OFFSET 0xF0 -+#define TANTOS_3G_SCR0_STORM_M_SHIFT 14 -+#define TANTOS_3G_SCR0_STORM_M_SIZE 1 -+/* Bit: 'STORM_U' */ -+/* Description: 'Storm Enable for Un-learned Unicast Packets' */ -+#define TANTOS_3G_SCR0_STORM_U_OFFSET 0xF0 -+#define TANTOS_3G_SCR0_STORM_U_SHIFT 13 -+#define TANTOS_3G_SCR0_STORM_U_SIZE 1 -+/* Bit: 'STORM_100_TH' */ -+/* Description: '100M Threshold' */ -+#define TANTOS_3G_SCR0_STORM_100_TH_OFFSET 0xF0 -+#define TANTOS_3G_SCR0_STORM_100_TH_SHIFT 0 -+#define TANTOS_3G_SCR0_STORM_100_TH_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Storm Control Register 1' */ -+/* Bit: 'STORM_10_TH' */ -+/* Description: '10M Threshold' */ -+#define TANTOS_3G_SCR1_STORM_10_TH_OFFSET 0xF1 -+#define TANTOS_3G_SCR1_STORM_10_TH_SHIFT 0 -+#define TANTOS_3G_SCR1_STORM_10_TH_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Management Clock Select Register' */ -+/* Bit: 'MCS' */ -+/* Description: 'Management Clock Select' */ -+#define TANTOS_3G_MCSR_MCS_OFFSET 0xF2 -+#define TANTOS_3G_MCSR_MCS_SHIFT 0 -+#define TANTOS_3G_MCSR_MCS_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RGMII/GMII Port Control Register' */ -+/* Bit: 'P6SPD' */ -+/* Description: 'Port 6 Speed' */ -+#define TANTOS_3G_RGMIICR_P6SPD_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P6SPD_SHIFT 10 -+#define TANTOS_3G_RGMIICR_P6SPD_SIZE 2 -+/* Bit: 'P6DUP' */ -+/* Description: 'Port 6 Duplex mode' */ -+#define TANTOS_3G_RGMIICR_P6DUP_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P6DUP_SHIFT 9 -+#define TANTOS_3G_RGMIICR_P6DUP_SIZE 1 -+/* Bit: 'P6FCE' */ -+/* Description: 'Port 6 Flow Control Enable' */ -+#define TANTOS_3G_RGMIICR_P6FCE_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P6FCE_SHIFT 8 -+#define TANTOS_3G_RGMIICR_P6FCE_SIZE 1 -+/* Bit: 'P5SPD' */ -+/* Description: 'Port 5 Speed' */ -+#define TANTOS_3G_RGMIICR_P5SPD_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P5SPD_SHIFT 6 -+#define TANTOS_3G_RGMIICR_P5SPD_SIZE 2 -+/* Bit: 'P5DUP' */ -+/* Description: 'Port 5 Duplex mode' */ -+#define TANTOS_3G_RGMIICR_P5DUP_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P5DUP_SHIFT 5 -+#define TANTOS_3G_RGMIICR_P5DUP_SIZE 1 -+/* Bit: 'P5FCE' */ -+/* Description: 'Port 5 Flow Control Enable' */ -+#define TANTOS_3G_RGMIICR_P5FCE_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P5FCE_SHIFT 4 -+#define TANTOS_3G_RGMIICR_P5FCE_SIZE 1 -+/* Bit: 'P4SPD' */ -+/* Description: 'Port 4 Speed' */ -+#define TANTOS_3G_RGMIICR_P4SPD_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P4SPD_SHIFT 2 -+#define TANTOS_3G_RGMIICR_P4SPD_SIZE 2 -+/* Bit: 'P4DUP' */ -+/* Description: 'Port 4 Duplex mode' */ -+#define TANTOS_3G_RGMIICR_P4DUP_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P4DUP_SHIFT 1 -+#define TANTOS_3G_RGMIICR_P4DUP_SIZE 1 -+/* Bit: 'P4FCE' */ -+/* Description: 'Port 4 Flow Control Enable' */ -+#define TANTOS_3G_RGMIICR_P4FCE_OFFSET 0xF5 -+#define TANTOS_3G_RGMIICR_P4FCE_SHIFT 0 -+#define TANTOS_3G_RGMIICR_P4FCE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Hardware IGMP Option Register' */ -+/* Bit: 'TIMERC' */ -+/* Description: 'Timer configuration for IGMP' */ -+#define TANTOS_3G_HIOR_TIMERC_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_TIMERC_SHIFT 9 -+#define TANTOS_3G_HIOR_TIMERC_SIZE 1 -+/* Bit: 'HISE' */ -+/* Description: 'Hardware IGMP Snooping Enable' */ -+#define TANTOS_3G_HIOR_HISE_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_HISE_SHIFT 8 -+#define TANTOS_3G_HIOR_HISE_SIZE 1 -+/* Bit: 'HISFL' */ -+/* Description: 'Hardware IGMP Snooping fast Leave option' */ -+#define TANTOS_3G_HIOR_HISFL_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_HISFL_SHIFT 7 -+#define TANTOS_3G_HIOR_HISFL_SIZE 1 -+/* Bit: 'IGMPV3E' */ -+/* Description: 'IGMPv3 enable' */ -+#define TANTOS_3G_HIOR_IGMPV3E_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_IGMPV3E_SHIFT 6 -+#define TANTOS_3G_HIOR_IGMPV3E_SIZE 1 -+/* Bit: 'SARE' */ -+/* Description: 'SA Replacement Enable' */ -+#define TANTOS_3G_HIOR_SARE_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_SARE_SHIFT 5 -+#define TANTOS_3G_HIOR_SARE_SIZE 1 -+/* Bit: 'PPPoEHR' */ -+/* Description: 'PPPoE header remove for IGMP data stream enable' */ -+#define TANTOS_3G_HIOR_PPPOEHR_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_PPPOEHR_SHIFT 4 -+#define TANTOS_3G_HIOR_PPPOEHR_SIZE 1 -+/* Bit: 'B33' */ -+/* Description: 'Broadcast 33.33.0.0.0.x disable' */ -+#define TANTOS_3G_HIOR_B33_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_B33_SHIFT 3 -+#define TANTOS_3G_HIOR_B33_SIZE 1 -+/* Bit: 'B01' */ -+/* Description: 'Broadcast 01.0.5E.0.0.x disable' */ -+#define TANTOS_3G_HIOR_B01_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_B01_SHIFT 2 -+#define TANTOS_3G_HIOR_B01_SIZE 1 -+/* Bit: 'B224' */ -+/* Description: 'Broadcast 224.0.0.x disable' */ -+#define TANTOS_3G_HIOR_B224_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_B224_SHIFT 1 -+#define TANTOS_3G_HIOR_B224_SIZE 1 -+/* Bit: 'DAIPS' */ -+/* Description: 'DA or IP for Search group ID' */ -+#define TANTOS_3G_HIOR_DAIPS_OFFSET 0xF6 -+#define TANTOS_3G_HIOR_DAIPS_SHIFT 0 -+#define TANTOS_3G_HIOR_DAIPS_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PPPoE Session ID Register' */ -+/* Bit: 'PPPoESID' */ -+/* Description: 'PPPoE Session ID' */ -+#define TANTOS_3G_PSIDR_PPPOESID_OFFSET 0xF7 -+#define TANTOS_3G_PSIDR_PPPOESID_SHIFT 0 -+#define TANTOS_3G_PSIDR_PPPOESID_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Chip Identifier 0' */ -+/* Bit: 'BOND' */ -+/* Description: 'Bonding Option' */ -+#define TANTOS_3G_CI0_BOND_OFFSET 0x100 -+#define TANTOS_3G_CI0_BOND_SHIFT 4 -+#define TANTOS_3G_CI0_BOND_SIZE 1 -+/* Bit: 'VN' */ -+/* Description: 'Version Number' */ -+#define TANTOS_3G_CI0_VN_OFFSET 0x100 -+#define TANTOS_3G_CI0_VN_SHIFT 0 -+#define TANTOS_3G_CI0_VN_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Chip Identifier 1' */ -+/* Bit: 'PC' */ -+/* Description: 'Product Code' */ -+#define TANTOS_3G_CI1_PC_OFFSET 0x101 -+#define TANTOS_3G_CI1_PC_SHIFT 0 -+#define TANTOS_3G_CI1_PC_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Global Status and Hardware Setting Register' */ -+/* Bit: 'LTBR' */ -+/* Description: 'Learning Table Bist Result' */ -+#define TANTOS_3G_GSHS_LTBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_LTBR_SHIFT 11 -+#define TANTOS_3G_GSHS_LTBR_SIZE 1 -+/* Bit: 'LLTBR' */ -+/* Description: 'Linklist Table Bist Result' */ -+#define TANTOS_3G_GSHS_LLTBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_LLTBR_SHIFT 10 -+#define TANTOS_3G_GSHS_LLTBR_SIZE 1 -+/* Bit: 'CTBR' */ -+/* Description: 'Control Table Bist Result' */ -+#define TANTOS_3G_GSHS_CTBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_CTBR_SHIFT 9 -+#define TANTOS_3G_GSHS_CTBR_SIZE 1 -+/* Bit: 'HISTBR' */ -+/* Description: 'Hardware IGMP Source List Table Bist Result' */ -+#define TANTOS_3G_GSHS_HISTBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_HISTBR_SHIFT 8 -+#define TANTOS_3G_GSHS_HISTBR_SIZE 1 -+/* Bit: 'HIGTBR' */ -+/* Description: 'Hardware IGMP Group Table Bist Result' */ -+#define TANTOS_3G_GSHS_HIGTBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_HIGTBR_SHIFT 7 -+#define TANTOS_3G_GSHS_HIGTBR_SIZE 1 -+/* Bit: 'DBBR' */ -+/* Description: 'Data Buffer Bist Result' */ -+#define TANTOS_3G_GSHS_DBBR_OFFSET 0x102 -+#define TANTOS_3G_GSHS_DBBR_SHIFT 6 -+#define TANTOS_3G_GSHS_DBBR_SIZE 1 -+/* Bit: 'P6M' */ -+/* Description: 'P6 Mode' */ -+#define TANTOS_3G_GSHS_P6M_OFFSET 0x102 -+#define TANTOS_3G_GSHS_P6M_SHIFT 4 -+#define TANTOS_3G_GSHS_P6M_SIZE 2 -+/* Bit: 'P5M' */ -+/* Description: 'P5 Mode' */ -+#define TANTOS_3G_GSHS_P5M_OFFSET 0x102 -+#define TANTOS_3G_GSHS_P5M_SHIFT 2 -+#define TANTOS_3G_GSHS_P5M_SIZE 2 -+/* Bit: 'P4M' */ -+/* Description: 'P4 Mode' */ -+#define TANTOS_3G_GSHS_P4M_OFFSET 0x102 -+#define TANTOS_3G_GSHS_P4M_SHIFT 0 -+#define TANTOS_3G_GSHS_P4M_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 0 Register' */ -+/* Bit: 'ADDR15_0' */ -+/* Description: 'Address [15:0]' */ -+#define TANTOS_3G_ATC0_ADDR15_0_OFFSET 0x104 -+#define TANTOS_3G_ATC0_ADDR15_0_SHIFT 0 -+#define TANTOS_3G_ATC0_ADDR15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 1 Register' */ -+/* Bit: 'ADDR31_16' */ -+/* Description: 'Address [31:16]' */ -+#define TANTOS_3G_ATC1_ADDR31_16_OFFSET 0x105 -+#define TANTOS_3G_ATC1_ADDR31_16_SHIFT 0 -+#define TANTOS_3G_ATC1_ADDR31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 2 Register' */ -+/* Bit: 'ADDR47_32' */ -+/* Description: 'Address [47:32]' */ -+#define TANTOS_3G_ATC2_ADDR47_32_OFFSET 0x106 -+#define TANTOS_3G_ATC2_ADDR47_32_SHIFT 0 -+#define TANTOS_3G_ATC2_ADDR47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 3 Register' */ -+/* Bit: 'PMAP' */ -+/* Description: 'Port Map' */ -+#define TANTOS_3G_ATC3_PMAP_OFFSET 0x107 -+#define TANTOS_3G_ATC3_PMAP_SHIFT 4 -+#define TANTOS_3G_ATC3_PMAP_SIZE 7 -+/* Bit: 'FID' */ -+/* Description: 'FID group' */ -+#define TANTOS_3G_ATC3_FID_OFFSET 0x107 -+#define TANTOS_3G_ATC3_FID_SHIFT 0 -+#define TANTOS_3G_ATC3_FID_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 4 Register' */ -+/* Bit: 'INFOT' */ -+/* Description: 'Info Type: Static address' */ -+#define TANTOS_3G_ATC4_INFOT_OFFSET 0x108 -+#define TANTOS_3G_ATC4_INFOT_SHIFT 12 -+#define TANTOS_3G_ATC4_INFOT_SIZE 1 -+/* Bit: 'ITAT' */ -+/* Description: 'Info_Ctrl/Age Timer' */ -+#define TANTOS_3G_ATC4_ITAT_OFFSET 0x108 -+#define TANTOS_3G_ATC4_ITAT_SHIFT 0 -+#define TANTOS_3G_ATC4_ITAT_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Control 5 Register' */ -+/* Bit: 'FCE' */ -+/* Description: 'Find within the current entry' */ -+#define TANTOS_3G_ATC5_FCE_OFFSET 0x109 -+#define TANTOS_3G_ATC5_FCE_SHIFT 7 -+#define TANTOS_3G_ATC5_FCE_SIZE 1 -+/* Bit: 'CMD' */ -+/* Description: 'Command' */ -+#define TANTOS_3G_ATC5_CMD_OFFSET 0x109 -+#define TANTOS_3G_ATC5_CMD_SHIFT 4 -+#define TANTOS_3G_ATC5_CMD_SIZE 3 -+/* Bit: 'AC' */ -+/* Description: 'Access Control' */ -+#define TANTOS_3G_ATC5_AC_OFFSET 0x109 -+#define TANTOS_3G_ATC5_AC_SHIFT 0 -+#define TANTOS_3G_ATC5_AC_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 0 Register' */ -+/* Bit: 'ADDRS15_0' */ -+/* Description: 'Address [15:0]' */ -+#define TANTOS_3G_ATS0_ADDRS15_0_OFFSET 0x10A -+#define TANTOS_3G_ATS0_ADDRS15_0_SHIFT 0 -+#define TANTOS_3G_ATS0_ADDRS15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 1 Register' */ -+/* Bit: 'ADDRS31_16' */ -+/* Description: 'Address [31:16]' */ -+#define TANTOS_3G_ATS1_ADDRS31_16_OFFSET 0x10B -+#define TANTOS_3G_ATS1_ADDRS31_16_SHIFT 0 -+#define TANTOS_3G_ATS1_ADDRS31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 2 Register' */ -+/* Bit: 'ADDRS47_32' */ -+/* Description: 'Address [47:32]' */ -+#define TANTOS_3G_ATS2_ADDRS47_32_OFFSET 0x10C -+#define TANTOS_3G_ATS2_ADDRS47_32_SHIFT 0 -+#define TANTOS_3G_ATS2_ADDRS47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 3 Register' */ -+/* Bit: 'PMAPS' */ -+/* Description: 'Port Map' */ -+#define TANTOS_3G_ATS3_PMAPS_OFFSET 0x10D -+#define TANTOS_3G_ATS3_PMAPS_SHIFT 4 -+#define TANTOS_3G_ATS3_PMAPS_SIZE 7 -+/* Bit: 'FIDS' */ -+/* Description: 'FID group' */ -+#define TANTOS_3G_ATS3_FIDS_OFFSET 0x10D -+#define TANTOS_3G_ATS3_FIDS_SHIFT 0 -+#define TANTOS_3G_ATS3_FIDS_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 4 Register' */ -+/* Bit: 'BAD' */ -+/* Description: 'Bad Status' */ -+#define TANTOS_3G_ATS4_BAD_OFFSET 0x10E -+#define TANTOS_3G_ATS4_BAD_SHIFT 14 -+#define TANTOS_3G_ATS4_BAD_SIZE 1 -+/* Bit: 'OCP' */ -+/* Description: 'Occupy' */ -+#define TANTOS_3G_ATS4_OCP_OFFSET 0x10E -+#define TANTOS_3G_ATS4_OCP_SHIFT 13 -+#define TANTOS_3G_ATS4_OCP_SIZE 1 -+/* Bit: 'INFOTS' */ -+/* Description: 'Info Type: Static address' */ -+#define TANTOS_3G_ATS4_INFOTS_OFFSET 0x10E -+#define TANTOS_3G_ATS4_INFOTS_SHIFT 12 -+#define TANTOS_3G_ATS4_INFOTS_SIZE 1 -+/* Bit: 'ITATS' */ -+/* Description: 'Info_Ctrl/Age Timer Status' */ -+#define TANTOS_3G_ATS4_ITATS_OFFSET 0x10E -+#define TANTOS_3G_ATS4_ITATS_SHIFT 0 -+#define TANTOS_3G_ATS4_ITATS_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Address Table Status 5 Register' */ -+/* Bit: 'BUSY' */ -+/* Description: 'Busy' */ -+#define TANTOS_3G_ATS5_BUSY_OFFSET 0x10F -+#define TANTOS_3G_ATS5_BUSY_SHIFT 15 -+#define TANTOS_3G_ATS5_BUSY_SIZE 1 -+/* Bit: 'RSLT' */ -+/* Description: 'Result' */ -+#define TANTOS_3G_ATS5_RSLT_OFFSET 0x10F -+#define TANTOS_3G_ATS5_RSLT_SHIFT 12 -+#define TANTOS_3G_ATS5_RSLT_SIZE 3 -+/* Bit: 'FCE' */ -+/* Description: 'Find within the current entry' */ -+#define TANTOS_3G_ATS5_FCE_OFFSET 0x10F -+#define TANTOS_3G_ATS5_FCE_SHIFT 7 -+#define TANTOS_3G_ATS5_FCE_SIZE 1 -+/* Bit: 'CMD' */ -+/* Description: 'Command' */ -+#define TANTOS_3G_ATS5_CMD_OFFSET 0x10F -+#define TANTOS_3G_ATS5_CMD_SHIFT 4 -+#define TANTOS_3G_ATS5_CMD_SIZE 3 -+/* Bit: 'AC' */ -+/* Description: 'Access Control' */ -+#define TANTOS_3G_ATS5_AC_OFFSET 0x10F -+#define TANTOS_3G_ATS5_AC_SHIFT 0 -+#define TANTOS_3G_ATS5_AC_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 0 Register' */ -+/* Bit: 'SIP15_0' */ -+/* Description: 'Source IP[15:0]' */ -+#define TANTOS_3G_IGMPTC0_SIP15_0_OFFSET 0x110 -+#define TANTOS_3G_IGMPTC0_SIP15_0_SHIFT 0 -+#define TANTOS_3G_IGMPTC0_SIP15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 1 Register' */ -+/* Bit: 'SIP31_16' */ -+/* Description: 'Source IP[31:16]' */ -+#define TANTOS_3G_IGMPTC1_SIP31_16_OFFSET 0x111 -+#define TANTOS_3G_IGMPTC1_SIP31_16_SHIFT 0 -+#define TANTOS_3G_IGMPTC1_SIP31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 2 Register' */ -+/* Bit: 'SIP47_32' */ -+/* Description: 'Source IP[47:32] for IPv6 MLD' */ -+#define TANTOS_3G_IGMPTC2_SIP47_32_OFFSET 0x112 -+#define TANTOS_3G_IGMPTC2_SIP47_32_SHIFT 0 -+#define TANTOS_3G_IGMPTC2_SIP47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 3 Register' */ -+/* Bit: 'GID15_0' */ -+/* Description: 'Group ID [15:0]' */ -+#define TANTOS_3G_IGMPTC3_GID15_0_OFFSET 0x113 -+#define TANTOS_3G_IGMPTC3_GID15_0_SHIFT 0 -+#define TANTOS_3G_IGMPTC3_GID15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 4 Register' */ -+/* Bit: 'GID31_16' */ -+/* Description: 'Group ID [31:16]. For IPv4 only [23:16] are used.' */ -+#define TANTOS_3G_IGMPTC4_GID31_16_OFFSET 0x114 -+#define TANTOS_3G_IGMPTC4_GID31_16_SHIFT 0 -+#define TANTOS_3G_IGMPTC4_GID31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Control 5 Register' */ -+/* Bit: 'ICMD' */ -+/* Description: 'IGMP Command' */ -+#define TANTOS_3G_IGMPTC5_ICMD_OFFSET 0x115 -+#define TANTOS_3G_IGMPTC5_ICMD_SHIFT 8 -+#define TANTOS_3G_IGMPTC5_ICMD_SIZE 3 -+/* Bit: 'INVC' */ -+/* Description: 'Invalid control' */ -+#define TANTOS_3G_IGMPTC5_INVC_OFFSET 0x115 -+#define TANTOS_3G_IGMPTC5_INVC_SHIFT 5 -+#define TANTOS_3G_IGMPTC5_INVC_SIZE 1 -+/* Bit: 'FMODE' */ -+/* Description: 'Filter Mode' */ -+#define TANTOS_3G_IGMPTC5_FMODE_OFFSET 0x115 -+#define TANTOS_3G_IGMPTC5_FMODE_SHIFT 4 -+#define TANTOS_3G_IGMPTC5_FMODE_SIZE 1 -+/* Bit: 'PORT' */ -+/* Description: 'Port number associated with this command' */ -+#define TANTOS_3G_IGMPTC5_PORT_OFFSET 0x115 -+#define TANTOS_3G_IGMPTC5_PORT_SHIFT 0 -+#define TANTOS_3G_IGMPTC5_PORT_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Status 0 Register' */ -+/* Bit: 'SIPGID0' */ -+/* Description: 'Source IP or Group ID bit [15:0]' */ -+#define TANTOS_3G_IGMPTS0_SIPGID0_OFFSET 0x116 -+#define TANTOS_3G_IGMPTS0_SIPGID0_SHIFT 0 -+#define TANTOS_3G_IGMPTS0_SIPGID0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Status 1 Register' */ -+/* Bit: 'SIPGID1' */ -+/* Description: 'Source IP or Group ID bit [31:16]' */ -+#define TANTOS_3G_IGMPTS1_SIPGID1_OFFSET 0x117 -+#define TANTOS_3G_IGMPTS1_SIPGID1_SHIFT 0 -+#define TANTOS_3G_IGMPTS1_SIPGID1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Status 2 Register' */ -+/* Bit: 'SIPGID2' */ -+/* Description: 'Source IP or Group ID bit [47:32]' */ -+#define TANTOS_3G_IGMPTS2_SIPGID2_OFFSET 0x118 -+#define TANTOS_3G_IGMPTS2_SIPGID2_SHIFT 0 -+#define TANTOS_3G_IGMPTS2_SIPGID2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Status 3 Register' */ -+/* Bit: 'S3PMI' */ -+/* Description: 'Port Map Include/exclude Status' */ -+#define TANTOS_3G_IGMPTS3_S3PMI_OFFSET 0x119 -+#define TANTOS_3G_IGMPTS3_S3PMI_SHIFT 7 -+#define TANTOS_3G_IGMPTS3_S3PMI_SIZE 7 -+/* Bit: 'S3PMV' */ -+/* Description: 'Port Map Valid Status' */ -+#define TANTOS_3G_IGMPTS3_S3PMV_OFFSET 0x119 -+#define TANTOS_3G_IGMPTS3_S3PMV_SHIFT 0 -+#define TANTOS_3G_IGMPTS3_S3PMV_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Table Status 4 Register' */ -+/* Bit: 'S4BUSY' */ -+/* Description: 'Busy' */ -+#define TANTOS_3G_IGMPTS4_S4BUSY_OFFSET 0x11A -+#define TANTOS_3G_IGMPTS4_S4BUSY_SHIFT 3 -+#define TANTOS_3G_IGMPTS4_S4BUSY_SIZE 1 -+/* Bit: 'S4R' */ -+/* Description: 'Result' */ -+#define TANTOS_3G_IGMPTS4_S4R_OFFSET 0x11A -+#define TANTOS_3G_IGMPTS4_S4R_SHIFT 0 -+#define TANTOS_3G_IGMPTS4_S4R_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RMON Counter Control Register' */ -+/* Bit: 'BAS' */ -+/* Description: 'Busy/Access Start' */ -+#define TANTOS_3G_RCC_BAS_OFFSET 0x11B -+#define TANTOS_3G_RCC_BAS_SHIFT 11 -+#define TANTOS_3G_RCC_BAS_SIZE 1 -+/* Bit: 'CAC' */ -+/* Description: 'Command for access counter' */ -+#define TANTOS_3G_RCC_CAC_OFFSET 0x11B -+#define TANTOS_3G_RCC_CAC_SHIFT 9 -+#define TANTOS_3G_RCC_CAC_SIZE 2 -+/* Bit: 'PORTC' */ -+/* Description: 'Port' */ -+#define TANTOS_3G_RCC_PORTC_OFFSET 0x11B -+#define TANTOS_3G_RCC_PORTC_SHIFT 6 -+#define TANTOS_3G_RCC_PORTC_SIZE 3 -+/* Bit: 'OFFSET' */ -+/* Description: 'Counter Offset' */ -+#define TANTOS_3G_RCC_OFFSET_OFFSET 0x11B -+#define TANTOS_3G_RCC_OFFSET_SHIFT 0 -+#define TANTOS_3G_RCC_OFFSET_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RMON Counter Status Low Register' */ -+/* Bit: 'COUNTER' */ -+/* Description: 'Counter [15:0] or Counter[47:32] for byte count' */ -+#define TANTOS_3G_RCSL_COUNTER_OFFSET 0x11C -+#define TANTOS_3G_RCSL_COUNTER_SHIFT 0 -+#define TANTOS_3G_RCSL_COUNTER_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RMON Counter Status High Register' */ -+/* Bit: 'COUNTER' */ -+/* Description: 'Counter [31:16] or Counter[63:48] for byte count' */ -+#define TANTOS_3G_RCSH_COUNTER_OFFSET 0x11D -+#define TANTOS_3G_RCSH_COUNTER_SHIFT 0 -+#define TANTOS_3G_RCSH_COUNTER_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MII Indirect Access Control' */ -+/* Bit: 'MBUSY' */ -+/* Description: 'Busy state' */ -+#define TANTOS_3G_MIIAC_MBUSY_OFFSET 0x120 -+#define TANTOS_3G_MIIAC_MBUSY_SHIFT 15 -+#define TANTOS_3G_MIIAC_MBUSY_SIZE 1 -+/* Bit: 'OP' */ -+/* Description: 'Operation Code' */ -+#define TANTOS_3G_MIIAC_OP_OFFSET 0x120 -+#define TANTOS_3G_MIIAC_OP_SHIFT 10 -+#define TANTOS_3G_MIIAC_OP_SIZE 2 -+/* Bit: 'PHYAD' */ -+/* Description: 'PHY Address' */ -+#define TANTOS_3G_MIIAC_PHYAD_OFFSET 0x120 -+#define TANTOS_3G_MIIAC_PHYAD_SHIFT 5 -+#define TANTOS_3G_MIIAC_PHYAD_SIZE 5 -+/* Bit: 'REGAD' */ -+/* Description: 'Register Address' */ -+#define TANTOS_3G_MIIAC_REGAD_OFFSET 0x120 -+#define TANTOS_3G_MIIAC_REGAD_SHIFT 0 -+#define TANTOS_3G_MIIAC_REGAD_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MII Indirect Write Data' */ -+/* Bit: 'WD' */ -+/* Description: 'The Write Data to the MII register' */ -+#define TANTOS_3G_MIIWD_WD_OFFSET 0x121 -+#define TANTOS_3G_MIIWD_WD_SHIFT 0 -+#define TANTOS_3G_MIIWD_WD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MII Indirect Read Data' */ -+/* Bit: 'RD' */ -+/* Description: 'The Read Data' */ -+#define TANTOS_3G_MIIRD_RD_OFFSET 0x122 -+#define TANTOS_3G_MIIRD_RD_SHIFT 0 -+#define TANTOS_3G_MIIRD_RD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+#endif /* #ifndef _TANTOS3G_H */ -diff --git a/include/switch_api/VR9_switch.h b/include/switch_api/VR9_switch.h -new file mode 100644 -index 0000000..f0dd37a ---- /dev/null -+++ b/include/switch_api/VR9_switch.h -@@ -0,0 +1,2637 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2011 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+#ifndef _VR9_SWITCH_H -+#define _VR9_SWITCH_H -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch ResetControl Register' */ -+/* Bit: 'R1' */ -+/* Description: 'GSWIP Software Reset' */ -+#define VR9_ETHSW_SWRES_R1_OFFSET 0x000 -+#define VR9_ETHSW_SWRES_R1_SHIFT 1 -+#define VR9_ETHSW_SWRES_R1_SIZE 1 -+/* Bit: 'R0' */ -+/* Description: 'GSWIP Hardware Reset' */ -+#define VR9_ETHSW_SWRES_R0_OFFSET 0x000 -+#define VR9_ETHSW_SWRES_R0_SHIFT 0 -+#define VR9_ETHSW_SWRES_R0_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch Clock ControlRegister ' */ -+/* Bit: 'CORACT_OVR' */ -+/* Description: 'Core Active Override' */ -+#define VR9_ETHSW_CLK_CORACT_OVR_OFFSET 0x001 -+#define VR9_ETHSW_CLK_CORACT_OVR_SHIFT 1 -+#define VR9_ETHSW_CLK_CORACT_OVR_SIZE 1 -+/* Bit: 'LNKDWN_OVR' */ -+/* Description: 'Link Down Override' */ -+#define VR9_ETHSW_CLK_LNKDWN_OVR_OFFSET 0x001 -+#define VR9_ETHSW_CLK_LNKDWN_OVR_SHIFT 0 -+#define VR9_ETHSW_CLK_LNKDWN_OVR_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch SharedSegment Buffer Mode Register' */ -+/* Bit: 'ADDE' */ -+/* Description: 'Memory Address' */ -+#define VR9_ETHSW_SSB_MODE_ADDE_OFFSET 0x003 -+#define VR9_ETHSW_SSB_MODE_ADDE_SHIFT 2 -+#define VR9_ETHSW_SSB_MODE_ADDE_SIZE 4 -+/* Bit: 'MODE' */ -+/* Description: 'Memory Access Mode' */ -+#define VR9_ETHSW_SSB_MODE_MODE_OFFSET 0x003 -+#define VR9_ETHSW_SSB_MODE_MODE_SHIFT 0 -+#define VR9_ETHSW_SSB_MODE_MODE_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch SharedSegment Buffer Address Register' */ -+/* Bit: 'ADDE' */ -+/* Description: 'Memory Address' */ -+#define VR9_ETHSW_SSB_ADDR_ADDE_OFFSET 0x004 -+#define VR9_ETHSW_SSB_ADDR_ADDE_SHIFT 0 -+#define VR9_ETHSW_SSB_ADDR_ADDE_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch SharedSegment Buffer Data Register' */ -+/* Bit: 'DATA' */ -+/* Description: 'Data Value' */ -+#define VR9_ETHSW_SSB_DATA_DATA_OFFSET 0x005 -+#define VR9_ETHSW_SSB_DATA_DATA_SHIFT 0 -+#define VR9_ETHSW_SSB_DATA_DATA_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 0' */ -+/* Bit: 'SPEED' */ -+/* Description: 'Clock frequency' */ -+#define VR9_ETHSW_CAP_0_SPEED_OFFSET 0x006 -+#define VR9_ETHSW_CAP_0_SPEED_SHIFT 0 -+#define VR9_ETHSW_CAP_0_SPEED_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 1' */ -+/* Bit: 'GMAC' */ -+/* Description: 'MAC operation mode' */ -+#define VR9_ETHSW_CAP_1_GMAC_OFFSET 0x007 -+#define VR9_ETHSW_CAP_1_GMAC_SHIFT 15 -+#define VR9_ETHSW_CAP_1_GMAC_SIZE 1 -+/* Bit: 'QUEUE' */ -+/* Description: 'Number of queues' */ -+#define VR9_ETHSW_CAP_1_QUEUE_OFFSET 0x007 -+#define VR9_ETHSW_CAP_1_QUEUE_SHIFT 8 -+#define VR9_ETHSW_CAP_1_QUEUE_SIZE 7 -+/* Bit: 'VPORTS' */ -+/* Description: 'Number of virtual ports' */ -+#define VR9_ETHSW_CAP_1_VPORTS_OFFSET 0x007 -+#define VR9_ETHSW_CAP_1_VPORTS_SHIFT 4 -+#define VR9_ETHSW_CAP_1_VPORTS_SIZE 4 -+/* Bit: 'PPORTS' */ -+/* Description: 'Number of physical ports' */ -+#define VR9_ETHSW_CAP_1_PPORTS_OFFSET 0x007 -+#define VR9_ETHSW_CAP_1_PPORTS_SHIFT 0 -+#define VR9_ETHSW_CAP_1_PPORTS_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 2' */ -+/* Bit: 'PACKETS' */ -+/* Description: 'Number of packets' */ -+#define VR9_ETHSW_CAP_2_PACKETS_OFFSET 0x008 -+#define VR9_ETHSW_CAP_2_PACKETS_SHIFT 0 -+#define VR9_ETHSW_CAP_2_PACKETS_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 3' */ -+/* Bit: 'METERS' */ -+/* Description: 'Number of traffic meters' */ -+#define VR9_ETHSW_CAP_3_METERS_OFFSET 0x009 -+#define VR9_ETHSW_CAP_3_METERS_SHIFT 8 -+#define VR9_ETHSW_CAP_3_METERS_SIZE 8 -+/* Bit: 'SHAPERS' */ -+/* Description: 'Number of traffic shapers' */ -+#define VR9_ETHSW_CAP_3_SHAPERS_OFFSET 0x009 -+#define VR9_ETHSW_CAP_3_SHAPERS_SHIFT 0 -+#define VR9_ETHSW_CAP_3_SHAPERS_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 4' */ -+/* Bit: 'PPPOE' */ -+/* Description: 'PPPoE table size' */ -+#define VR9_ETHSW_CAP_4_PPPOE_OFFSET 0x00A -+#define VR9_ETHSW_CAP_4_PPPOE_SHIFT 8 -+#define VR9_ETHSW_CAP_4_PPPOE_SIZE 8 -+/* Bit: 'VLAN' */ -+/* Description: 'Active VLAN table size' */ -+#define VR9_ETHSW_CAP_4_VLAN_OFFSET 0x00A -+#define VR9_ETHSW_CAP_4_VLAN_SHIFT 0 -+#define VR9_ETHSW_CAP_4_VLAN_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 5' */ -+/* Bit: 'IPPLEN' */ -+/* Description: 'IP packet length table size' */ -+#define VR9_ETHSW_CAP_5_IPPLEN_OFFSET 0x00B -+#define VR9_ETHSW_CAP_5_IPPLEN_SHIFT 8 -+#define VR9_ETHSW_CAP_5_IPPLEN_SIZE 8 -+/* Bit: 'PROT' */ -+/* Description: 'Protocol table size' */ -+#define VR9_ETHSW_CAP_5_PROT_OFFSET 0x00B -+#define VR9_ETHSW_CAP_5_PROT_SHIFT 0 -+#define VR9_ETHSW_CAP_5_PROT_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 6' */ -+/* Bit: 'MACDASA' */ -+/* Description: 'MAC DA/SA table size' */ -+#define VR9_ETHSW_CAP_6_MACDASA_OFFSET 0x00C -+#define VR9_ETHSW_CAP_6_MACDASA_SHIFT 8 -+#define VR9_ETHSW_CAP_6_MACDASA_SIZE 8 -+/* Bit: 'APPL' */ -+/* Description: 'Application table size' */ -+#define VR9_ETHSW_CAP_6_APPL_OFFSET 0x00C -+#define VR9_ETHSW_CAP_6_APPL_SHIFT 0 -+#define VR9_ETHSW_CAP_6_APPL_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 7' */ -+/* Bit: 'IPDASAM' */ -+/* Description: 'IP DA/SA MSB table size' */ -+#define VR9_ETHSW_CAP_7_IPDASAM_OFFSET 0x00D -+#define VR9_ETHSW_CAP_7_IPDASAM_SHIFT 8 -+#define VR9_ETHSW_CAP_7_IPDASAM_SIZE 8 -+/* Bit: 'IPDASAL' */ -+/* Description: 'IP DA/SA LSB table size' */ -+#define VR9_ETHSW_CAP_7_IPDASAL_OFFSET 0x00D -+#define VR9_ETHSW_CAP_7_IPDASAL_SHIFT 0 -+#define VR9_ETHSW_CAP_7_IPDASAL_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 8' */ -+/* Bit: 'MCAST' */ -+/* Description: 'Multicast table size' */ -+#define VR9_ETHSW_CAP_8_MCAST_OFFSET 0x00E -+#define VR9_ETHSW_CAP_8_MCAST_SHIFT 0 -+#define VR9_ETHSW_CAP_8_MCAST_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 9' */ -+/* Bit: 'FLAGG' */ -+/* Description: 'Flow Aggregation table size' */ -+#define VR9_ETHSW_CAP_9_FLAGG_OFFSET 0x00F -+#define VR9_ETHSW_CAP_9_FLAGG_SHIFT 0 -+#define VR9_ETHSW_CAP_9_FLAGG_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 10' */ -+/* Bit: 'MACBT' */ -+/* Description: 'MAC bridging table size' */ -+#define VR9_ETHSW_CAP_10_MACBT_OFFSET 0x010 -+#define VR9_ETHSW_CAP_10_MACBT_SHIFT 0 -+#define VR9_ETHSW_CAP_10_MACBT_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 11' */ -+/* Bit: 'BSIZEL' */ -+/* Description: 'Packet buffer size (lower part, in byte)' */ -+#define VR9_ETHSW_CAP_11_BSIZEL_OFFSET 0x011 -+#define VR9_ETHSW_CAP_11_BSIZEL_SHIFT 0 -+#define VR9_ETHSW_CAP_11_BSIZEL_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch CapabilityRegister 12' */ -+/* Bit: 'BSIZEH' */ -+/* Description: 'Packet buffer size (higher part, in byte)' */ -+#define VR9_ETHSW_CAP_12_BSIZEH_OFFSET 0x012 -+#define VR9_ETHSW_CAP_12_BSIZEH_SHIFT 0 -+#define VR9_ETHSW_CAP_12_BSIZEH_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch VersionRegister' */ -+/* Bit: 'MOD_ID' */ -+/* Description: 'Module Identification' */ -+#define VR9_ETHSW_VERSION_MOD_ID_OFFSET 0x013 -+#define VR9_ETHSW_VERSION_MOD_ID_SHIFT 8 -+#define VR9_ETHSW_VERSION_MOD_ID_SIZE 8 -+/* Bit: 'REV_ID' */ -+/* Description: 'Hardware Revision Identification' */ -+#define VR9_ETHSW_VERSION_REV_ID_OFFSET 0x013 -+#define VR9_ETHSW_VERSION_REV_ID_SHIFT 0 -+#define VR9_ETHSW_VERSION_REV_ID_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Enable Register' */ -+/* Bit: 'FDMAIE' */ -+/* Description: 'Fetch DMA Interrupt Enable' */ -+#define VR9_ETHSW_IER_FDMAIE_OFFSET 0x014 -+#define VR9_ETHSW_IER_FDMAIE_SHIFT 4 -+#define VR9_ETHSW_IER_FDMAIE_SIZE 1 -+/* Bit: 'SDMAIE' */ -+/* Description: 'Store DMA Interrupt Enable' */ -+#define VR9_ETHSW_IER_SDMAIE_OFFSET 0x014 -+#define VR9_ETHSW_IER_SDMAIE_SHIFT 3 -+#define VR9_ETHSW_IER_SDMAIE_SIZE 1 -+/* Bit: 'MACIE' */ -+/* Description: 'Ethernet MAC Interrupt Enable' */ -+#define VR9_ETHSW_IER_MACIE_OFFSET 0x014 -+#define VR9_ETHSW_IER_MACIE_SHIFT 2 -+#define VR9_ETHSW_IER_MACIE_SIZE 1 -+/* Bit: 'PCEIE' */ -+/* Description: 'Parser and Classification Engine Interrupt Enable' */ -+#define VR9_ETHSW_IER_PCEIE_OFFSET 0x014 -+#define VR9_ETHSW_IER_PCEIE_SHIFT 1 -+#define VR9_ETHSW_IER_PCEIE_SIZE 1 -+/* Bit: 'BMIE' */ -+/* Description: 'Buffer Manager Interrupt Enable' */ -+#define VR9_ETHSW_IER_BMIE_OFFSET 0x014 -+#define VR9_ETHSW_IER_BMIE_SHIFT 0 -+#define VR9_ETHSW_IER_BMIE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Interrupt Status Register' */ -+/* Bit: 'FDMAINT' */ -+/* Description: 'Fetch DMA Interrupt' */ -+#define VR9_ETHSW_ISR_FDMAINT_OFFSET 0x015 -+#define VR9_ETHSW_ISR_FDMAINT_SHIFT 4 -+#define VR9_ETHSW_ISR_FDMAINT_SIZE 1 -+/* Bit: 'SDMAINT' */ -+/* Description: 'Store DMA Interrupt' */ -+#define VR9_ETHSW_ISR_SDMAINT_OFFSET 0x015 -+#define VR9_ETHSW_ISR_SDMAINT_SHIFT 3 -+#define VR9_ETHSW_ISR_SDMAINT_SIZE 1 -+/* Bit: 'MACINT' */ -+/* Description: 'Ethernet MAC Interrupt' */ -+#define VR9_ETHSW_ISR_MACINT_OFFSET 0x015 -+#define VR9_ETHSW_ISR_MACINT_SHIFT 2 -+#define VR9_ETHSW_ISR_MACINT_SIZE 1 -+/* Bit: 'PCEINT' */ -+/* Description: 'Parser and Classification Engine Interrupt' */ -+#define VR9_ETHSW_ISR_PCEINT_OFFSET 0x015 -+#define VR9_ETHSW_ISR_PCEINT_SHIFT 1 -+#define VR9_ETHSW_ISR_PCEINT_SIZE 1 -+/* Bit: 'BMINT' */ -+/* Description: 'Buffer Manager Interrupt' */ -+#define VR9_ETHSW_ISR_BMINT_OFFSET 0x015 -+#define VR9_ETHSW_ISR_BMINT_SHIFT 0 -+#define VR9_ETHSW_ISR_BMINT_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Value Register 3' */ -+/* Bit: 'VAL3' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_BM_RAM_VAL_3_VAL3_OFFSET 0x040 -+#define VR9_BM_RAM_VAL_3_VAL3_SHIFT 0 -+#define VR9_BM_RAM_VAL_3_VAL3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Value Register 2' */ -+/* Bit: 'VAL2' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_BM_RAM_VAL_2_VAL2_OFFSET 0x041 -+#define VR9_BM_RAM_VAL_2_VAL2_SHIFT 0 -+#define VR9_BM_RAM_VAL_2_VAL2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Value Register 1' */ -+/* Bit: 'VAL1' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_BM_RAM_VAL_1_VAL1_OFFSET 0x042 -+#define VR9_BM_RAM_VAL_1_VAL1_SHIFT 0 -+#define VR9_BM_RAM_VAL_1_VAL1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Value Register 0' */ -+/* Bit: 'VAL0' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_BM_RAM_VAL_0_VAL0_OFFSET 0x043 -+#define VR9_BM_RAM_VAL_0_VAL0_SHIFT 0 -+#define VR9_BM_RAM_VAL_0_VAL0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Address Register' */ -+/* Bit: 'ADDR' */ -+/* Description: 'RAM Address' */ -+#define VR9_BM_RAM_ADDR_ADDR_OFFSET 0x044 -+#define VR9_BM_RAM_ADDR_ADDR_SHIFT 0 -+#define VR9_BM_RAM_ADDR_ADDR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'RAM Access Control Register' */ -+/* Bit: 'BAS' */ -+/* Description: 'Access Busy/Access Start' */ -+#define VR9_BM_RAM_CTRL_BAS_OFFSET 0x045 -+#define VR9_BM_RAM_CTRL_BAS_SHIFT 15 -+#define VR9_BM_RAM_CTRL_BAS_SIZE 1 -+/* Bit: 'OPMOD' */ -+/* Description: 'Lookup Table Access Operation Mode' */ -+#define VR9_BM_RAM_CTRL_OPMOD_OFFSET 0x045 -+#define VR9_BM_RAM_CTRL_OPMOD_SHIFT 5 -+#define VR9_BM_RAM_CTRL_OPMOD_SIZE 1 -+/* Bit: 'ADDR' */ -+/* Description: 'Address for RAM selection' */ -+#define VR9_BM_RAM_CTRL_ADDR_OFFSET 0x045 -+#define VR9_BM_RAM_CTRL_ADDR_SHIFT 0 -+#define VR9_BM_RAM_CTRL_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Free Segment Queue ManagerGlobal Control Register' */ -+/* Bit: 'SEGNUM' */ -+/* Description: 'Maximum Segment Number' */ -+#define VR9_BM_FSQM_GCTRL_SEGNUM_OFFSET 0x046 -+#define VR9_BM_FSQM_GCTRL_SEGNUM_SHIFT 0 -+#define VR9_BM_FSQM_GCTRL_SEGNUM_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Number of Consumed SegmentsRegister' */ -+/* Bit: 'FSEG' */ -+/* Description: 'Number of Consumed Segments' */ -+#define VR9_BM_CONS_SEG_FSEG_OFFSET 0x047 -+#define VR9_BM_CONS_SEG_FSEG_SHIFT 0 -+#define VR9_BM_CONS_SEG_FSEG_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Number of Consumed PacketPointers Register' */ -+/* Bit: 'FQP' */ -+/* Description: 'Number of Consumed Packet Pointers' */ -+#define VR9_BM_CONS_PKT_FQP_OFFSET 0x048 -+#define VR9_BM_CONS_PKT_FQP_SHIFT 0 -+#define VR9_BM_CONS_PKT_FQP_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Manager Global ControlRegister 0' */ -+/* Bit: 'BM_STA' */ -+/* Description: 'Buffer Manager Initialization Status Bit' */ -+#define VR9_BM_GCTRL_BM_STA_OFFSET 0x049 -+#define VR9_BM_GCTRL_BM_STA_SHIFT 13 -+#define VR9_BM_GCTRL_BM_STA_SIZE 1 -+/* Bit: 'SAT' */ -+/* Description: 'RMON Counter Update Mode' */ -+#define VR9_BM_GCTRL_SAT_OFFSET 0x049 -+#define VR9_BM_GCTRL_SAT_SHIFT 12 -+#define VR9_BM_GCTRL_SAT_SIZE 1 -+/* Bit: 'FR_RBC' */ -+/* Description: 'Freeze RMON RX Bad Byte 64 Bit Counter' */ -+#define VR9_BM_GCTRL_FR_RBC_OFFSET 0x049 -+#define VR9_BM_GCTRL_FR_RBC_SHIFT 11 -+#define VR9_BM_GCTRL_FR_RBC_SIZE 1 -+/* Bit: 'FR_RGC' */ -+/* Description: 'Freeze RMON RX Good Byte 64 Bit Counter' */ -+#define VR9_BM_GCTRL_FR_RGC_OFFSET 0x049 -+#define VR9_BM_GCTRL_FR_RGC_SHIFT 10 -+#define VR9_BM_GCTRL_FR_RGC_SIZE 1 -+/* Bit: 'FR_TGC' */ -+/* Description: 'Freeze RMON TX Good Byte 64 Bit Counter' */ -+#define VR9_BM_GCTRL_FR_TGC_OFFSET 0x049 -+#define VR9_BM_GCTRL_FR_TGC_SHIFT 9 -+#define VR9_BM_GCTRL_FR_TGC_SIZE 1 -+/* Bit: 'I_FIN' */ -+/* Description: 'RAM initialization finished' */ -+#define VR9_BM_GCTRL_I_FIN_OFFSET 0x049 -+#define VR9_BM_GCTRL_I_FIN_SHIFT 8 -+#define VR9_BM_GCTRL_I_FIN_SIZE 1 -+/* Bit: 'CX_INI' */ -+/* Description: 'PQM Context RAM initialization' */ -+#define VR9_BM_GCTRL_CX_INI_OFFSET 0x049 -+#define VR9_BM_GCTRL_CX_INI_SHIFT 7 -+#define VR9_BM_GCTRL_CX_INI_SIZE 1 -+/* Bit: 'FP_INI' */ -+/* Description: 'FPQM RAM initialization' */ -+#define VR9_BM_GCTRL_FP_INI_OFFSET 0x049 -+#define VR9_BM_GCTRL_FP_INI_SHIFT 6 -+#define VR9_BM_GCTRL_FP_INI_SIZE 1 -+/* Bit: 'FS_INI' */ -+/* Description: 'FSQM RAM initialization' */ -+#define VR9_BM_GCTRL_FS_INI_OFFSET 0x049 -+#define VR9_BM_GCTRL_FS_INI_SHIFT 5 -+#define VR9_BM_GCTRL_FS_INI_SIZE 1 -+/* Bit: 'R_SRES' */ -+/* Description: 'Software Reset for RMON' */ -+#define VR9_BM_GCTRL_R_SRES_OFFSET 0x049 -+#define VR9_BM_GCTRL_R_SRES_SHIFT 4 -+#define VR9_BM_GCTRL_R_SRES_SIZE 1 -+/* Bit: 'S_SRES' */ -+/* Description: 'Software Reset for Scheduler' */ -+#define VR9_BM_GCTRL_S_SRES_OFFSET 0x049 -+#define VR9_BM_GCTRL_S_SRES_SHIFT 3 -+#define VR9_BM_GCTRL_S_SRES_SIZE 1 -+/* Bit: 'A_SRES' */ -+/* Description: 'Software Reset for AVG' */ -+#define VR9_BM_GCTRL_A_SRES_OFFSET 0x049 -+#define VR9_BM_GCTRL_A_SRES_SHIFT 2 -+#define VR9_BM_GCTRL_A_SRES_SIZE 1 -+/* Bit: 'P_SRES' */ -+/* Description: 'Software Reset for PQM' */ -+#define VR9_BM_GCTRL_P_SRES_OFFSET 0x049 -+#define VR9_BM_GCTRL_P_SRES_SHIFT 1 -+#define VR9_BM_GCTRL_P_SRES_SIZE 1 -+/* Bit: 'F_SRES' */ -+/* Description: 'Software Reset for FSQM' */ -+#define VR9_BM_GCTRL_F_SRES_OFFSET 0x049 -+#define VR9_BM_GCTRL_F_SRES_SHIFT 0 -+#define VR9_BM_GCTRL_F_SRES_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Queue Manager GlobalControl Register 0' */ -+/* Bit: 'GL_MOD' */ -+/* Description: 'WRED Mode Signal' */ -+#define VR9_BM_QUEUE_GCTRL_GL_MOD_OFFSET 0x04A -+#define VR9_BM_QUEUE_GCTRL_GL_MOD_SHIFT 10 -+#define VR9_BM_QUEUE_GCTRL_GL_MOD_SIZE 1 -+/* Bit: 'AQUI' */ -+/* Description: 'Average Queue Update Interval' */ -+#define VR9_BM_QUEUE_GCTRL_AQUI_OFFSET 0x04A -+#define VR9_BM_QUEUE_GCTRL_AQUI_SHIFT 7 -+#define VR9_BM_QUEUE_GCTRL_AQUI_SIZE 3 -+/* Bit: 'AQWF' */ -+/* Description: 'Average Queue Weight Factor' */ -+#define VR9_BM_QUEUE_GCTRL_AQWF_OFFSET 0x04A -+#define VR9_BM_QUEUE_GCTRL_AQWF_SHIFT 3 -+#define VR9_BM_QUEUE_GCTRL_AQWF_SIZE 4 -+/* Bit: 'QAVGEN' */ -+/* Description: 'Queue Average Calculation Enable' */ -+#define VR9_BM_QUEUE_GCTRL_QAVGEN_OFFSET 0x04A -+#define VR9_BM_QUEUE_GCTRL_QAVGEN_SHIFT 2 -+#define VR9_BM_QUEUE_GCTRL_QAVGEN_SIZE 1 -+/* Bit: 'DPROB' */ -+/* Description: 'Drop Probability Profile' */ -+#define VR9_BM_QUEUE_GCTRL_DPROB_OFFSET 0x04A -+#define VR9_BM_QUEUE_GCTRL_DPROB_SHIFT 0 -+#define VR9_BM_QUEUE_GCTRL_DPROB_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Red Threshold Register0' */ -+/* Bit: 'MINTH' */ -+/* Description: 'Minimum Threshold' */ -+#define VR9_BM_WRED_RTH_0_MINTH_OFFSET 0x04B -+#define VR9_BM_WRED_RTH_0_MINTH_SHIFT 0 -+#define VR9_BM_WRED_RTH_0_MINTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Red Threshold Register1' */ -+/* Bit: 'MAXTH' */ -+/* Description: 'Maximum Threshold' */ -+#define VR9_BM_WRED_RTH_1_MAXTH_OFFSET 0x04C -+#define VR9_BM_WRED_RTH_1_MAXTH_SHIFT 0 -+#define VR9_BM_WRED_RTH_1_MAXTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Yellow ThresholdRegister 0' */ -+/* Bit: 'MINTH' */ -+/* Description: 'Minimum Threshold' */ -+#define VR9_BM_WRED_YTH_0_MINTH_OFFSET 0x04D -+#define VR9_BM_WRED_YTH_0_MINTH_SHIFT 0 -+#define VR9_BM_WRED_YTH_0_MINTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Yellow ThresholdRegister 1' */ -+/* Bit: 'MAXTH' */ -+/* Description: 'Maximum Threshold' */ -+#define VR9_BM_WRED_YTH_1_MAXTH_OFFSET 0x04E -+#define VR9_BM_WRED_YTH_1_MAXTH_SHIFT 0 -+#define VR9_BM_WRED_YTH_1_MAXTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Green ThresholdRegister 0' */ -+/* Bit: 'MINTH' */ -+/* Description: 'Minimum Threshold' */ -+#define VR9_BM_WRED_GTH_0_MINTH_OFFSET 0x04F -+#define VR9_BM_WRED_GTH_0_MINTH_SHIFT 0 -+#define VR9_BM_WRED_GTH_0_MINTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'WRED Green ThresholdRegister 1' */ -+/* Bit: 'MAXTH' */ -+/* Description: 'Maximum Threshold' */ -+#define VR9_BM_WRED_GTH_1_MAXTH_OFFSET 0x050 -+#define VR9_BM_WRED_GTH_1_MAXTH_SHIFT 0 -+#define VR9_BM_WRED_GTH_1_MAXTH_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Drop Threshold ConfigurationRegister 0' */ -+/* Bit: 'THR_FQ' */ -+/* Description: 'Threshold for frames marked red' */ -+#define VR9_BM_DROP_GTH_0_THR_FQ_OFFSET 0x051 -+#define VR9_BM_DROP_GTH_0_THR_FQ_SHIFT 0 -+#define VR9_BM_DROP_GTH_0_THR_FQ_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Drop Threshold ConfigurationRegister 1' */ -+/* Bit: 'THY_FQ' */ -+/* Description: 'Threshold for frames marked yellow' */ -+#define VR9_BM_DROP_GTH_1_THY_FQ_OFFSET 0x052 -+#define VR9_BM_DROP_GTH_1_THY_FQ_SHIFT 0 -+#define VR9_BM_DROP_GTH_1_THY_FQ_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Drop Threshold ConfigurationRegister 2' */ -+/* Bit: 'THG_FQ' */ -+/* Description: 'Threshold for frames marked green' */ -+#define VR9_BM_DROP_GTH_2_THG_FQ_OFFSET 0x053 -+#define VR9_BM_DROP_GTH_2_THG_FQ_SHIFT 0 -+#define VR9_BM_DROP_GTH_2_THG_FQ_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Manager Global InterruptEnable Register' */ -+/* Bit: 'CNT4' */ -+/* Description: 'Counter Group 4 (RMON-CLASSIFICATION) Interrupt -+Enable' */ -+#define VR9_BM_IER_CNT4_OFFSET 0x054 -+#define VR9_BM_IER_CNT4_SHIFT 7 -+#define VR9_BM_IER_CNT4_SIZE 1 -+/* Bit: 'CNT3' */ -+/* Description: 'Counter Group 3 (RMON-PQM) Interrupt Enable' */ -+#define VR9_BM_IER_CNT3_OFFSET 0x054 -+#define VR9_BM_IER_CNT3_SHIFT 6 -+#define VR9_BM_IER_CNT3_SIZE 1 -+/* Bit: 'CNT2' */ -+/* Description: 'Counter Group 2 (RMON-SCHEDULER) Interrupt Enable' */ -+#define VR9_BM_IER_CNT2_OFFSET 0x054 -+#define VR9_BM_IER_CNT2_SHIFT 5 -+#define VR9_BM_IER_CNT2_SIZE 1 -+/* Bit: 'CNT1' */ -+/* Description: 'Counter Group 1 (RMON-QFETCH) Interrupt Enable' */ -+#define VR9_BM_IER_CNT1_OFFSET 0x054 -+#define VR9_BM_IER_CNT1_SHIFT 4 -+#define VR9_BM_IER_CNT1_SIZE 1 -+/* Bit: 'CNT0' */ -+/* Description: 'Counter Group 0 (RMON-QSTOR) Interrupt Enable' */ -+#define VR9_BM_IER_CNT0_OFFSET 0x054 -+#define VR9_BM_IER_CNT0_SHIFT 3 -+#define VR9_BM_IER_CNT0_SIZE 1 -+/* Bit: 'DEQ' */ -+/* Description: 'PQM dequeue Interrupt Enable' */ -+#define VR9_BM_IER_DEQ_OFFSET 0x054 -+#define VR9_BM_IER_DEQ_SHIFT 2 -+#define VR9_BM_IER_DEQ_SIZE 1 -+/* Bit: 'ENQ' */ -+/* Description: 'PQM Enqueue Interrupt Enable' */ -+#define VR9_BM_IER_ENQ_OFFSET 0x054 -+#define VR9_BM_IER_ENQ_SHIFT 1 -+#define VR9_BM_IER_ENQ_SIZE 1 -+/* Bit: 'FSQM' */ -+/* Description: 'Buffer Empty Interrupt Enable' */ -+#define VR9_BM_IER_FSQM_OFFSET 0x054 -+#define VR9_BM_IER_FSQM_SHIFT 0 -+#define VR9_BM_IER_FSQM_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Manager Global InterruptStatus Register' */ -+/* Bit: 'CNT4' */ -+/* Description: 'Counter Group 4 Interrupt' */ -+#define VR9_BM_ISR_CNT4_OFFSET 0x055 -+#define VR9_BM_ISR_CNT4_SHIFT 7 -+#define VR9_BM_ISR_CNT4_SIZE 1 -+/* Bit: 'CNT3' */ -+/* Description: 'Counter Group 3 Interrupt' */ -+#define VR9_BM_ISR_CNT3_OFFSET 0x055 -+#define VR9_BM_ISR_CNT3_SHIFT 6 -+#define VR9_BM_ISR_CNT3_SIZE 1 -+/* Bit: 'CNT2' */ -+/* Description: 'Counter Group 2 Interrupt' */ -+#define VR9_BM_ISR_CNT2_OFFSET 0x055 -+#define VR9_BM_ISR_CNT2_SHIFT 5 -+#define VR9_BM_ISR_CNT2_SIZE 1 -+/* Bit: 'CNT1' */ -+/* Description: 'Counter Group 1 Interrupt' */ -+#define VR9_BM_ISR_CNT1_OFFSET 0x055 -+#define VR9_BM_ISR_CNT1_SHIFT 4 -+#define VR9_BM_ISR_CNT1_SIZE 1 -+/* Bit: 'CNT0' */ -+/* Description: 'Counter Group 0 Interrupt' */ -+#define VR9_BM_ISR_CNT0_OFFSET 0x055 -+#define VR9_BM_ISR_CNT0_SHIFT 3 -+#define VR9_BM_ISR_CNT0_SIZE 1 -+/* Bit: 'DEQ' */ -+/* Description: 'PQM dequeue Interrupt Enable' */ -+#define VR9_BM_ISR_DEQ_OFFSET 0x055 -+#define VR9_BM_ISR_DEQ_SHIFT 2 -+#define VR9_BM_ISR_DEQ_SIZE 1 -+/* Bit: 'ENQ' */ -+/* Description: 'PQM Enqueue Interrupt' */ -+#define VR9_BM_ISR_ENQ_OFFSET 0x055 -+#define VR9_BM_ISR_ENQ_SHIFT 1 -+#define VR9_BM_ISR_ENQ_SIZE 1 -+/* Bit: 'FSQM' */ -+/* Description: 'Buffer Empty Interrupt' */ -+#define VR9_BM_ISR_FSQM_OFFSET 0x055 -+#define VR9_BM_ISR_FSQM_SHIFT 0 -+#define VR9_BM_ISR_FSQM_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Manager RMON CounterInterrupt Select Register' */ -+/* Bit: 'PORT' */ -+/* Description: 'Port Number' */ -+#define VR9_BM_CISEL_PORT_OFFSET 0x056 -+#define VR9_BM_CISEL_PORT_SHIFT 0 -+#define VR9_BM_CISEL_PORT_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Debug Control Register' */ -+/* Bit: 'DBG_SEL' */ -+/* Description: 'Select Signal for Debug Multiplexer' */ -+#define VR9_BM_DEBUG_CTRL_DBG_SEL_OFFSET 0x057 -+#define VR9_BM_DEBUG_CTRL_DBG_SEL_SHIFT 0 -+#define VR9_BM_DEBUG_CTRL_DBG_SEL_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Debug Value Register' */ -+/* Bit: 'DBG_DAT' */ -+/* Description: 'Debug Data Value' */ -+#define VR9_BM_DEBUG_VAL_DBG_DAT_OFFSET 0x058 -+#define VR9_BM_DEBUG_VAL_DBG_DAT_SHIFT 0 -+#define VR9_BM_DEBUG_VAL_DBG_DAT_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer Manager PortConfiguration Register' */ -+/* Bit: 'IGCNT' */ -+/* Description: 'Ingress Special Tag RMON count' */ -+#define VR9_BM_PCFG_IGCNT_OFFSET 0x080 -+#define VR9_BM_PCFG_IGCNT_SHIFT 1 -+#define VR9_BM_PCFG_IGCNT_SIZE 1 -+/* Bit: 'CNTEN' */ -+/* Description: 'RMON Counter Enable' */ -+#define VR9_BM_PCFG_CNTEN_OFFSET 0x080 -+#define VR9_BM_PCFG_CNTEN_SHIFT 0 -+#define VR9_BM_PCFG_CNTEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Buffer ManagerRMON Control Register' */ -+/* Bit: 'RAM2_RES' */ -+/* Description: 'Software Reset for RMON RAM2' */ -+#define VR9_BM_RMON_CTRL_RAM2_RES_OFFSET 0x081 -+#define VR9_BM_RMON_CTRL_RAM2_RES_SHIFT 1 -+#define VR9_BM_RMON_CTRL_RAM2_RES_SIZE 1 -+/* Bit: 'RAM1_RES' */ -+/* Description: 'Software Reset for RMON RAM1' */ -+#define VR9_BM_RMON_CTRL_RAM1_RES_OFFSET 0x081 -+#define VR9_BM_RMON_CTRL_RAM1_RES_SHIFT 0 -+#define VR9_BM_RMON_CTRL_RAM1_RES_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Packet Queue ManagerRate Shaper Assignment Register' */ -+/* Bit: 'EN2' */ -+/* Description: 'Rate Shaper 2 Enable' */ -+#define VR9_PQM_RS_EN2_OFFSET 0x101 -+#define VR9_PQM_RS_EN2_SHIFT 15 -+#define VR9_PQM_RS_EN2_SIZE 1 -+/* Bit: 'RS2' */ -+/* Description: 'Rate Shaper 2' */ -+#define VR9_PQM_RS_RS2_OFFSET 0x101 -+#define VR9_PQM_RS_RS2_SHIFT 8 -+#define VR9_PQM_RS_RS2_SIZE 4 -+/* Bit: 'EN1' */ -+/* Description: 'Rate Shaper 1 Enable' */ -+#define VR9_PQM_RS_EN1_OFFSET 0x101 -+#define VR9_PQM_RS_EN1_SHIFT 7 -+#define VR9_PQM_RS_EN1_SIZE 1 -+/* Bit: 'RS1' */ -+/* Description: 'Rate Shaper 1' */ -+#define VR9_PQM_RS_RS1_OFFSET 0x101 -+#define VR9_PQM_RS_RS1_SHIFT 0 -+#define VR9_PQM_RS_RS1_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Rate Shaper ControlRegister' */ -+/* Bit: 'RSEN' */ -+/* Description: 'Rate Shaper Enable' */ -+#define VR9_RS_CTRL_RSEN_OFFSET 0x140 -+#define VR9_RS_CTRL_RSEN_SHIFT 0 -+#define VR9_RS_CTRL_RSEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Rate Shaper CommittedBurst Size Register' */ -+/* Bit: 'CBS' */ -+/* Description: 'Committed Burst Size' */ -+#define VR9_RS_CBS_CBS_OFFSET 0x141 -+#define VR9_RS_CBS_CBS_SHIFT 0 -+#define VR9_RS_CBS_CBS_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Rate Shaper InstantaneousBurst Size Register' */ -+/* Bit: 'IBS' */ -+/* Description: 'Instantaneous Burst Size' */ -+#define VR9_RS_IBS_IBS_OFFSET 0x142 -+#define VR9_RS_IBS_IBS_SHIFT 0 -+#define VR9_RS_IBS_IBS_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Rate Shaper RateExponent Register' */ -+/* Bit: 'EXP' */ -+/* Description: 'Exponent' */ -+#define VR9_RS_CIR_EXP_EXP_OFFSET 0x143 -+#define VR9_RS_CIR_EXP_EXP_SHIFT 0 -+#define VR9_RS_CIR_EXP_EXP_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Rate Shaper RateMantissa Register' */ -+/* Bit: 'MANT' */ -+/* Description: 'Mantissa' */ -+#define VR9_RS_CIR_MANT_MANT_OFFSET 0x144 -+#define VR9_RS_CIR_MANT_MANT_SHIFT 0 -+#define VR9_RS_CIR_MANT_MANT_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 15' */ -+/* Bit: 'KEY15' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_15_KEY15_OFFSET 0x438 -+#define VR9_PCE_TBL_KEY_15_KEY15_SHIFT 0 -+#define VR9_PCE_TBL_KEY_15_KEY15_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 14' */ -+/* Bit: 'KEY14' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_14_KEY14_OFFSET 0x439 -+#define VR9_PCE_TBL_KEY_14_KEY14_SHIFT 0 -+#define VR9_PCE_TBL_KEY_14_KEY14_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 13' */ -+/* Bit: 'KEY13' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_13_KEY13_OFFSET 0x43A -+#define VR9_PCE_TBL_KEY_13_KEY13_SHIFT 0 -+#define VR9_PCE_TBL_KEY_13_KEY13_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 12' */ -+/* Bit: 'KEY12' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_12_KEY12_OFFSET 0x43B -+#define VR9_PCE_TBL_KEY_12_KEY12_SHIFT 0 -+#define VR9_PCE_TBL_KEY_12_KEY12_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 11' */ -+/* Bit: 'KEY11' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_11_KEY11_OFFSET 0x43C -+#define VR9_PCE_TBL_KEY_11_KEY11_SHIFT 0 -+#define VR9_PCE_TBL_KEY_11_KEY11_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 10' */ -+/* Bit: 'KEY10' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_10_KEY10_OFFSET 0x43D -+#define VR9_PCE_TBL_KEY_10_KEY10_SHIFT 0 -+#define VR9_PCE_TBL_KEY_10_KEY10_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 9' */ -+/* Bit: 'KEY9' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_9_KEY9_OFFSET 0x43E -+#define VR9_PCE_TBL_KEY_9_KEY9_SHIFT 0 -+#define VR9_PCE_TBL_KEY_9_KEY9_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 8' */ -+/* Bit: 'KEY8' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_8_KEY8_OFFSET 0x43F -+#define VR9_PCE_TBL_KEY_8_KEY8_SHIFT 0 -+#define VR9_PCE_TBL_KEY_8_KEY8_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 7' */ -+/* Bit: 'KEY7' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_7_KEY7_OFFSET 0x440 -+#define VR9_PCE_TBL_KEY_7_KEY7_SHIFT 0 -+#define VR9_PCE_TBL_KEY_7_KEY7_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 6' */ -+/* Bit: 'KEY6' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_6_KEY6_OFFSET 0x441 -+#define VR9_PCE_TBL_KEY_6_KEY6_SHIFT 0 -+#define VR9_PCE_TBL_KEY_6_KEY6_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 5' */ -+/* Bit: 'KEY5' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_5_KEY5_OFFSET 0x442 -+#define VR9_PCE_TBL_KEY_5_KEY5_SHIFT 0 -+#define VR9_PCE_TBL_KEY_5_KEY5_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 4' */ -+/* Bit: 'KEY4' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_4_KEY4_OFFSET 0x443 -+#define VR9_PCE_TBL_KEY_4_KEY4_SHIFT 0 -+#define VR9_PCE_TBL_KEY_4_KEY4_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 3' */ -+/* Bit: 'KEY3' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_3_KEY3_OFFSET 0x444 -+#define VR9_PCE_TBL_KEY_3_KEY3_SHIFT 0 -+#define VR9_PCE_TBL_KEY_3_KEY3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 2' */ -+/* Bit: 'KEY2' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_2_KEY2_OFFSET 0x445 -+#define VR9_PCE_TBL_KEY_2_KEY2_SHIFT 0 -+#define VR9_PCE_TBL_KEY_2_KEY2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 1' */ -+/* Bit: 'KEY1' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_1_KEY1_OFFSET 0x446 -+#define VR9_PCE_TBL_KEY_1_KEY1_SHIFT 0 -+#define VR9_PCE_TBL_KEY_1_KEY1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Key Data 0' */ -+/* Bit: 'KEY0' */ -+/* Description: 'Key Value[15:0]' */ -+#define VR9_PCE_TBL_KEY_0_KEY0_OFFSET 0x447 -+#define VR9_PCE_TBL_KEY_0_KEY0_SHIFT 0 -+#define VR9_PCE_TBL_KEY_0_KEY0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Mask Write Register0' */ -+/* Bit: 'MASK0' */ -+/* Description: 'Mask Pattern [15:0]' */ -+#define VR9_PCE_TBL_MASK_0_MASK0_OFFSET 0x448 -+#define VR9_PCE_TBL_MASK_0_MASK0_SHIFT 0 -+#define VR9_PCE_TBL_MASK_0_MASK0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Value Register4' */ -+/* Bit: 'VAL4' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_PCE_TBL_VAL_4_VAL4_OFFSET 0x449 -+#define VR9_PCE_TBL_VAL_4_VAL4_SHIFT 0 -+#define VR9_PCE_TBL_VAL_4_VAL4_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Value Register3' */ -+/* Bit: 'VAL3' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_PCE_TBL_VAL_3_VAL3_OFFSET 0x44A -+#define VR9_PCE_TBL_VAL_3_VAL3_SHIFT 0 -+#define VR9_PCE_TBL_VAL_3_VAL3_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Value Register2' */ -+/* Bit: 'VAL2' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_PCE_TBL_VAL_2_VAL2_OFFSET 0x44B -+#define VR9_PCE_TBL_VAL_2_VAL2_SHIFT 0 -+#define VR9_PCE_TBL_VAL_2_VAL2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Value Register1' */ -+/* Bit: 'VAL1' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_PCE_TBL_VAL_1_VAL1_OFFSET 0x44C -+#define VR9_PCE_TBL_VAL_1_VAL1_SHIFT 0 -+#define VR9_PCE_TBL_VAL_1_VAL1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Value Register0' */ -+/* Bit: 'VAL0' */ -+/* Description: 'Data value [15:0]' */ -+#define VR9_PCE_TBL_VAL_0_VAL0_OFFSET 0x44D -+#define VR9_PCE_TBL_VAL_0_VAL0_SHIFT 0 -+#define VR9_PCE_TBL_VAL_0_VAL0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Entry AddressRegister' */ -+/* Bit: 'ADDR' */ -+/* Description: 'Table Address' */ -+#define VR9_PCE_TBL_ADDR_ADDR_OFFSET 0x44E -+#define VR9_PCE_TBL_ADDR_ADDR_SHIFT 0 -+#define VR9_PCE_TBL_ADDR_ADDR_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table Access ControlRegister' */ -+/* Bit: 'BAS' */ -+/* Description: 'Access Busy/Access Start' */ -+#define VR9_PCE_TBL_CTRL_BAS_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_BAS_SHIFT 15 -+#define VR9_PCE_TBL_CTRL_BAS_SIZE 1 -+/* Bit: 'TYPE' */ -+/* Description: 'Lookup Entry Type' */ -+#define VR9_PCE_TBL_CTRL_TYPE_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_TYPE_SHIFT 13 -+#define VR9_PCE_TBL_CTRL_TYPE_SIZE 1 -+/* Bit: 'VLD' */ -+/* Description: 'Lookup Entry Valid' */ -+#define VR9_PCE_TBL_CTRL_VLD_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_VLD_SHIFT 12 -+#define VR9_PCE_TBL_CTRL_VLD_SIZE 1 -+/* Bit: 'KEYFORM' */ -+/* Description: 'Key Format' */ -+#define VR9_PCE_TBL_CTRL_KEYFORM_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_KEYFORM_SHIFT 11 -+#define VR9_PCE_TBL_CTRL_KEYFORM_SIZE 1 -+/* Bit: 'GMAP' */ -+/* Description: 'Group Map' */ -+#define VR9_PCE_TBL_CTRL_GMAP_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_GMAP_SHIFT 7 -+#define VR9_PCE_TBL_CTRL_GMAP_SIZE 4 -+/* Bit: 'OPMOD' */ -+/* Description: 'Lookup Table Access Operation Mode' */ -+#define VR9_PCE_TBL_CTRL_OPMOD_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_OPMOD_SHIFT 5 -+#define VR9_PCE_TBL_CTRL_OPMOD_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'Lookup Table Address' */ -+#define VR9_PCE_TBL_CTRL_ADDR_OFFSET 0x44F -+#define VR9_PCE_TBL_CTRL_ADDR_SHIFT 0 -+#define VR9_PCE_TBL_CTRL_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Table General StatusRegister' */ -+/* Bit: 'TBUSY' */ -+/* Description: 'Table Access Busy' */ -+#define VR9_PCE_TBL_STAT_TBUSY_OFFSET 0x450 -+#define VR9_PCE_TBL_STAT_TBUSY_SHIFT 2 -+#define VR9_PCE_TBL_STAT_TBUSY_SIZE 1 -+/* Bit: 'TEMPT' */ -+/* Description: 'Table Empty' */ -+#define VR9_PCE_TBL_STAT_TEMPT_OFFSET 0x450 -+#define VR9_PCE_TBL_STAT_TEMPT_SHIFT 1 -+#define VR9_PCE_TBL_STAT_TEMPT_SIZE 1 -+/* Bit: 'TFUL' */ -+/* Description: 'Table Full' */ -+#define VR9_PCE_TBL_STAT_TFUL_OFFSET 0x450 -+#define VR9_PCE_TBL_STAT_TFUL_SHIFT 0 -+#define VR9_PCE_TBL_STAT_TFUL_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Aging Counter ConfigurationRegister 0' */ -+/* Bit: 'EXP' */ -+/* Description: 'Aging Counter Exponent Value ' */ -+#define VR9_PCE_AGE_0_EXP_OFFSET 0x451 -+#define VR9_PCE_AGE_0_EXP_SHIFT 0 -+#define VR9_PCE_AGE_0_EXP_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Aging Counter ConfigurationRegister 1' */ -+/* Bit: 'MANT' */ -+/* Description: 'Aging Counter Mantissa Value ' */ -+#define VR9_PCE_AGE_1_MANT_OFFSET 0x452 -+#define VR9_PCE_AGE_1_MANT_SHIFT 0 -+#define VR9_PCE_AGE_1_MANT_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port Map Register 1' */ -+/* Bit: 'MPMAP' */ -+/* Description: 'Monitoring Port Map' */ -+#define VR9_PCE_PMAP_1_MPMAP_OFFSET 0x453 -+#define VR9_PCE_PMAP_1_MPMAP_SHIFT 0 -+#define VR9_PCE_PMAP_1_MPMAP_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port Map Register 2' */ -+/* Bit: 'DMCPMAP' */ -+/* Description: 'Default Multicast Port Map' */ -+#define VR9_PCE_PMAP_2_DMCPMAP_OFFSET 0x454 -+#define VR9_PCE_PMAP_2_DMCPMAP_SHIFT 0 -+#define VR9_PCE_PMAP_2_DMCPMAP_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Port Map Register 3' */ -+/* Bit: 'UUCMAP' */ -+/* Description: 'Default Unknown Unicast Port Map' */ -+#define VR9_PCE_PMAP_3_UUCMAP_OFFSET 0x455 -+#define VR9_PCE_PMAP_3_UUCMAP_SHIFT 0 -+#define VR9_PCE_PMAP_3_UUCMAP_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Global Control Register0' */ -+/* Bit: 'IGMP' */ -+/* Description: 'IGMP Mode Selection' */ -+#define VR9_PCE_GCTRL_0_IGMP_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_IGMP_SHIFT 15 -+#define VR9_PCE_GCTRL_0_IGMP_SIZE 1 -+/* Bit: 'VLAN' */ -+/* Description: 'VLAN-aware Switching' */ -+#define VR9_PCE_GCTRL_0_VLAN_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_VLAN_SHIFT 14 -+#define VR9_PCE_GCTRL_0_VLAN_SIZE 1 -+/* Bit: 'NOPM' */ -+/* Description: 'No Port Map Forwarding' */ -+#define VR9_PCE_GCTRL_0_NOPM_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_NOPM_SHIFT 13 -+#define VR9_PCE_GCTRL_0_NOPM_SIZE 1 -+/* Bit: 'SCONUC' */ -+/* Description: 'Unknown Unicast Storm Control' */ -+#define VR9_PCE_GCTRL_0_SCONUC_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_SCONUC_SHIFT 12 -+#define VR9_PCE_GCTRL_0_SCONUC_SIZE 1 -+/* Bit: 'SCONMC' */ -+/* Description: 'Multicast Storm Control' */ -+#define VR9_PCE_GCTRL_0_SCONMC_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_SCONMC_SHIFT 11 -+#define VR9_PCE_GCTRL_0_SCONMC_SIZE 1 -+/* Bit: 'SCONBC' */ -+/* Description: 'Broadcast Storm Control' */ -+#define VR9_PCE_GCTRL_0_SCONBC_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_SCONBC_SHIFT 10 -+#define VR9_PCE_GCTRL_0_SCONBC_SIZE 1 -+/* Bit: 'SCONMOD' */ -+/* Description: 'Storm Control Mode' */ -+#define VR9_PCE_GCTRL_0_SCONMOD_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_SCONMOD_SHIFT 8 -+#define VR9_PCE_GCTRL_0_SCONMOD_SIZE 2 -+/* Bit: 'SCONMET' */ -+/* Description: 'Storm Control Metering Instance' */ -+#define VR9_PCE_GCTRL_0_SCONMET_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_SCONMET_SHIFT 4 -+#define VR9_PCE_GCTRL_0_SCONMET_SIZE 4 -+/* Bit: 'MC_VALID' */ -+/* Description: 'Access Request' */ -+#define VR9_PCE_GCTRL_0_MC_VALID_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_MC_VALID_SHIFT 3 -+#define VR9_PCE_GCTRL_0_MC_VALID_SIZE 1 -+/* Bit: 'PLCKMOD' */ -+/* Description: 'Port Lock Mode' */ -+#define VR9_PCE_GCTRL_0_PLCKMOD_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_PLCKMOD_SHIFT 2 -+#define VR9_PCE_GCTRL_0_PLCKMOD_SIZE 1 -+/* Bit: 'PLIMMOD' */ -+/* Description: 'MAC Address Learning Limitation Mode' */ -+#define VR9_PCE_GCTRL_0_PLIMMOD_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_PLIMMOD_SHIFT 1 -+#define VR9_PCE_GCTRL_0_PLIMMOD_SIZE 1 -+/* Bit: 'MTFL' */ -+/* Description: 'MAC Table Flushing' */ -+#define VR9_PCE_GCTRL_0_MTFL_OFFSET 0x456 -+#define VR9_PCE_GCTRL_0_MTFL_SHIFT 0 -+#define VR9_PCE_GCTRL_0_MTFL_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Global Control Register1' */ -+/* Bit: 'PARSER_DBG' */ -+/* Description: 'Parser Debug Selection' */ -+#define VR9_PCE_GCTRL_1_PARSER_DBG_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_PARSER_DBG_SHIFT 14 -+#define VR9_PCE_GCTRL_1_PARSER_DBG_SIZE 2 -+/* Bit: 'FLOWPTR_LIST_EN' */ -+/* Description: 'Flow Pointer List enable' */ -+#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_SHIFT 4 -+#define VR9_PCE_GCTRL_1_FLOWPTR_LIST_EN_SIZE 1 -+/* Bit: 'MAC_GLOCKMOD' */ -+/* Description: 'MAC Address Table Lock forwarding mode' */ -+#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_SHIFT 3 -+#define VR9_PCE_GCTRL_1_MAC_GLOCKMOD_SIZE 1 -+/* Bit: 'MAC_GLOCK' */ -+/* Description: 'MAC Address Table Lock' */ -+#define VR9_PCE_GCTRL_1_MAC_GLOCK_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_MAC_GLOCK_SHIFT 2 -+#define VR9_PCE_GCTRL_1_MAC_GLOCK_SIZE 1 -+/* Bit: 'PCE_DIS' */ -+/* Description: 'PCE Disable after currently processed packet' */ -+#define VR9_PCE_GCTRL_1_PCE_DIS_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_PCE_DIS_SHIFT 1 -+#define VR9_PCE_GCTRL_1_PCE_DIS_SIZE 1 -+/* Bit: 'LRNMOD' */ -+/* Description: 'MAC Address Learning Mode' */ -+#define VR9_PCE_GCTRL_1_LRNMOD_OFFSET 0x457 -+#define VR9_PCE_GCTRL_1_LRNMOD_SHIFT 0 -+#define VR9_PCE_GCTRL_1_LRNMOD_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-color MarkerGlobal Control Register' */ -+/* Bit: 'DPRED' */ -+/* Description: 'Re-marking Drop Precedence Red Encoding' */ -+#define VR9_PCE_TCM_GLOB_CTRL_DPRED_OFFSET 0x458 -+#define VR9_PCE_TCM_GLOB_CTRL_DPRED_SHIFT 6 -+#define VR9_PCE_TCM_GLOB_CTRL_DPRED_SIZE 3 -+/* Bit: 'DPYEL' */ -+/* Description: 'Re-marking Drop Precedence Yellow Encoding' */ -+#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_OFFSET 0x458 -+#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_SHIFT 3 -+#define VR9_PCE_TCM_GLOB_CTRL_DPYEL_SIZE 3 -+/* Bit: 'DPGRN' */ -+/* Description: 'Re-marking Drop Precedence Green Encoding' */ -+#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_OFFSET 0x458 -+#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_SHIFT 0 -+#define VR9_PCE_TCM_GLOB_CTRL_DPGRN_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Control Register' */ -+/* Bit: 'FAGEEN' */ -+/* Description: 'Force Aging of Table Entries Enable' */ -+#define VR9_PCE_IGMP_CTRL_FAGEEN_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_FAGEEN_SHIFT 15 -+#define VR9_PCE_IGMP_CTRL_FAGEEN_SIZE 1 -+/* Bit: 'FLEAVE' */ -+/* Description: 'Fast Leave Enable' */ -+#define VR9_PCE_IGMP_CTRL_FLEAVE_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_FLEAVE_SHIFT 14 -+#define VR9_PCE_IGMP_CTRL_FLEAVE_SIZE 1 -+/* Bit: 'DMRTEN' */ -+/* Description: 'Default Maximum Response Time Enable' */ -+#define VR9_PCE_IGMP_CTRL_DMRTEN_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_DMRTEN_SHIFT 13 -+#define VR9_PCE_IGMP_CTRL_DMRTEN_SIZE 1 -+/* Bit: 'JASUP' */ -+/* Description: 'Join Aggregation Suppression Enable' */ -+#define VR9_PCE_IGMP_CTRL_JASUP_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_JASUP_SHIFT 12 -+#define VR9_PCE_IGMP_CTRL_JASUP_SIZE 1 -+/* Bit: 'REPSUP' */ -+/* Description: 'Report Suppression Enable' */ -+#define VR9_PCE_IGMP_CTRL_REPSUP_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_REPSUP_SHIFT 11 -+#define VR9_PCE_IGMP_CTRL_REPSUP_SIZE 1 -+/* Bit: 'SRPEN' */ -+/* Description: 'Snooping of Router Port Enable' */ -+#define VR9_PCE_IGMP_CTRL_SRPEN_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_SRPEN_SHIFT 10 -+#define VR9_PCE_IGMP_CTRL_SRPEN_SIZE 1 -+/* Bit: 'ROB' */ -+/* Description: 'Robustness Variable' */ -+#define VR9_PCE_IGMP_CTRL_ROB_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_ROB_SHIFT 8 -+#define VR9_PCE_IGMP_CTRL_ROB_SIZE 2 -+/* Bit: 'DMRT' */ -+/* Description: 'IGMP Default Maximum Response Time' */ -+#define VR9_PCE_IGMP_CTRL_DMRT_OFFSET 0x459 -+#define VR9_PCE_IGMP_CTRL_DMRT_SHIFT 0 -+#define VR9_PCE_IGMP_CTRL_DMRT_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Default RouterPort Map Register' */ -+/* Bit: 'DRPM' */ -+/* Description: 'IGMP Default Router Port Map' */ -+#define VR9_PCE_IGMP_DRPM_DRPM_OFFSET 0x45A -+#define VR9_PCE_IGMP_DRPM_DRPM_SHIFT 0 -+#define VR9_PCE_IGMP_DRPM_DRPM_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Aging Register0' */ -+/* Bit: 'MANT' */ -+/* Description: 'IGMP Group Aging Time Mantissa' */ -+#define VR9_PCE_IGMP_AGE_0_MANT_OFFSET 0x45B -+#define VR9_PCE_IGMP_AGE_0_MANT_SHIFT 3 -+#define VR9_PCE_IGMP_AGE_0_MANT_SIZE 8 -+/* Bit: 'EXP' */ -+/* Description: 'IGMP Group Aging Time Exponent' */ -+#define VR9_PCE_IGMP_AGE_0_EXP_OFFSET 0x45B -+#define VR9_PCE_IGMP_AGE_0_EXP_SHIFT 0 -+#define VR9_PCE_IGMP_AGE_0_EXP_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Aging Register1' */ -+/* Bit: 'MANT' */ -+/* Description: 'IGMP Router Port Aging Time Mantissa' */ -+#define VR9_PCE_IGMP_AGE_1_MANT_OFFSET 0x45C -+#define VR9_PCE_IGMP_AGE_1_MANT_SHIFT 0 -+#define VR9_PCE_IGMP_AGE_1_MANT_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'IGMP Status Register' */ -+/* Bit: 'IGPM' */ -+/* Description: 'IGMP Port Map' */ -+#define VR9_PCE_IGMP_STAT_IGPM_OFFSET 0x45D -+#define VR9_PCE_IGMP_STAT_IGPM_SHIFT 0 -+#define VR9_PCE_IGMP_STAT_IGPM_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN ControlRegister' */ -+/* Bit: 'PASSEN' */ -+/* Description: 'WoL Password Enable' */ -+#define VR9_WOL_GLB_CTRL_PASSEN_OFFSET 0x45E -+#define VR9_WOL_GLB_CTRL_PASSEN_SHIFT 0 -+#define VR9_WOL_GLB_CTRL_PASSEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN DestinationAddress Register 0' */ -+/* Bit: 'DA0' */ -+/* Description: 'WoL Destination Address [15:0]' */ -+#define VR9_WOL_DA_0_DA0_OFFSET 0x45F -+#define VR9_WOL_DA_0_DA0_SHIFT 0 -+#define VR9_WOL_DA_0_DA0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN DestinationAddress Register 1' */ -+/* Bit: 'DA1' */ -+/* Description: 'WoL Destination Address [31:16]' */ -+#define VR9_WOL_DA_1_DA1_OFFSET 0x460 -+#define VR9_WOL_DA_1_DA1_SHIFT 0 -+#define VR9_WOL_DA_1_DA1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN DestinationAddress Register 2' */ -+/* Bit: 'DA2' */ -+/* Description: 'WoL Destination Address [47:32]' */ -+#define VR9_WOL_DA_2_DA2_OFFSET 0x461 -+#define VR9_WOL_DA_2_DA2_SHIFT 0 -+#define VR9_WOL_DA_2_DA2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN Password Register0' */ -+/* Bit: 'PW0' */ -+/* Description: 'WoL Password [15:0]' */ -+#define VR9_WOL_PW_0_PW0_OFFSET 0x462 -+#define VR9_WOL_PW_0_PW0_SHIFT 0 -+#define VR9_WOL_PW_0_PW0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN Password Register1' */ -+/* Bit: 'PW1' */ -+/* Description: 'WoL Password [31:16]' */ -+#define VR9_WOL_PW_1_PW1_OFFSET 0x463 -+#define VR9_WOL_PW_1_PW1_SHIFT 0 -+#define VR9_WOL_PW_1_PW1_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN Password Register2' */ -+/* Bit: 'PW2' */ -+/* Description: 'WoL Password [47:32]' */ -+#define VR9_WOL_PW_2_PW2_OFFSET 0x464 -+#define VR9_WOL_PW_2_PW2_SHIFT 0 -+#define VR9_WOL_PW_2_PW2_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Global Interrupt Enable Register 0' */ -+/* Bit: 'PINT_15' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_15_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_15_SHIFT 15 -+#define VR9_PCE_IER_0_PINT_15_SIZE 1 -+/* Bit: 'PINT_14' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_14_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_14_SHIFT 14 -+#define VR9_PCE_IER_0_PINT_14_SIZE 1 -+/* Bit: 'PINT_13' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_13_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_13_SHIFT 13 -+#define VR9_PCE_IER_0_PINT_13_SIZE 1 -+/* Bit: 'PINT_12' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_12_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_12_SHIFT 12 -+#define VR9_PCE_IER_0_PINT_12_SIZE 1 -+/* Bit: 'PINT_11' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_11_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_11_SHIFT 11 -+#define VR9_PCE_IER_0_PINT_11_SIZE 1 -+/* Bit: 'PINT_10' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_10_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_10_SHIFT 10 -+#define VR9_PCE_IER_0_PINT_10_SIZE 1 -+/* Bit: 'PINT_9' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_9_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_9_SHIFT 9 -+#define VR9_PCE_IER_0_PINT_9_SIZE 1 -+/* Bit: 'PINT_8' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_8_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_8_SHIFT 8 -+#define VR9_PCE_IER_0_PINT_8_SIZE 1 -+/* Bit: 'PINT_7' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_7_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_7_SHIFT 7 -+#define VR9_PCE_IER_0_PINT_7_SIZE 1 -+/* Bit: 'PINT_6' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_6_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_6_SHIFT 6 -+#define VR9_PCE_IER_0_PINT_6_SIZE 1 -+/* Bit: 'PINT_5' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_5_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_5_SHIFT 5 -+#define VR9_PCE_IER_0_PINT_5_SIZE 1 -+/* Bit: 'PINT_4' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_4_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_4_SHIFT 4 -+#define VR9_PCE_IER_0_PINT_4_SIZE 1 -+/* Bit: 'PINT_3' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_3_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_3_SHIFT 3 -+#define VR9_PCE_IER_0_PINT_3_SIZE 1 -+/* Bit: 'PINT_2' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_2_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_2_SHIFT 2 -+#define VR9_PCE_IER_0_PINT_2_SIZE 1 -+/* Bit: 'PINT_1' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_1_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_1_SHIFT 1 -+#define VR9_PCE_IER_0_PINT_1_SIZE 1 -+/* Bit: 'PINT_0' */ -+/* Description: 'Port Interrupt Enable' */ -+#define VR9_PCE_IER_0_PINT_0_OFFSET 0x465 -+#define VR9_PCE_IER_0_PINT_0_SHIFT 0 -+#define VR9_PCE_IER_0_PINT_0_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Global Interrupt Enable Register 1' */ -+/* Bit: 'FLOWINT' */ -+/* Description: 'Traffic Flow Table Interrupt Rule matched Interrupt -+Enable' */ -+#define VR9_PCE_IER_1_FLOWINT_OFFSET 0x466 -+#define VR9_PCE_IER_1_FLOWINT_SHIFT 6 -+#define VR9_PCE_IER_1_FLOWINT_SIZE 1 -+/* Bit: 'CPH2' */ -+/* Description: 'Classification Phase 2 Ready Interrupt Enable' */ -+#define VR9_PCE_IER_1_CPH2_OFFSET 0x466 -+#define VR9_PCE_IER_1_CPH2_SHIFT 5 -+#define VR9_PCE_IER_1_CPH2_SIZE 1 -+/* Bit: 'CPH1' */ -+/* Description: 'Classification Phase 1 Ready Interrupt Enable' */ -+#define VR9_PCE_IER_1_CPH1_OFFSET 0x466 -+#define VR9_PCE_IER_1_CPH1_SHIFT 4 -+#define VR9_PCE_IER_1_CPH1_SIZE 1 -+/* Bit: 'CPH0' */ -+/* Description: 'Classification Phase 0 Ready Interrupt Enable' */ -+#define VR9_PCE_IER_1_CPH0_OFFSET 0x466 -+#define VR9_PCE_IER_1_CPH0_SHIFT 3 -+#define VR9_PCE_IER_1_CPH0_SIZE 1 -+/* Bit: 'PRDY' */ -+/* Description: 'Parser Ready Interrupt Enable' */ -+#define VR9_PCE_IER_1_PRDY_OFFSET 0x466 -+#define VR9_PCE_IER_1_PRDY_SHIFT 2 -+#define VR9_PCE_IER_1_PRDY_SIZE 1 -+/* Bit: 'IGTF' */ -+/* Description: 'IGMP Table Full Interrupt Enable' */ -+#define VR9_PCE_IER_1_IGTF_OFFSET 0x466 -+#define VR9_PCE_IER_1_IGTF_SHIFT 1 -+#define VR9_PCE_IER_1_IGTF_SIZE 1 -+/* Bit: 'MTF' */ -+/* Description: 'MAC Table Full Interrupt Enable' */ -+#define VR9_PCE_IER_1_MTF_OFFSET 0x466 -+#define VR9_PCE_IER_1_MTF_SHIFT 0 -+#define VR9_PCE_IER_1_MTF_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Global Interrupt Status Register 0' */ -+/* Bit: 'PINT_15' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_15_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_15_SHIFT 15 -+#define VR9_PCE_ISR_0_PINT_15_SIZE 1 -+/* Bit: 'PINT_14' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_14_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_14_SHIFT 14 -+#define VR9_PCE_ISR_0_PINT_14_SIZE 1 -+/* Bit: 'PINT_13' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_13_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_13_SHIFT 13 -+#define VR9_PCE_ISR_0_PINT_13_SIZE 1 -+/* Bit: 'PINT_12' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_12_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_12_SHIFT 12 -+#define VR9_PCE_ISR_0_PINT_12_SIZE 1 -+/* Bit: 'PINT_11' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_11_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_11_SHIFT 11 -+#define VR9_PCE_ISR_0_PINT_11_SIZE 1 -+/* Bit: 'PINT_10' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_10_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_10_SHIFT 10 -+#define VR9_PCE_ISR_0_PINT_10_SIZE 1 -+/* Bit: 'PINT_9' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_9_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_9_SHIFT 9 -+#define VR9_PCE_ISR_0_PINT_9_SIZE 1 -+/* Bit: 'PINT_8' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_8_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_8_SHIFT 8 -+#define VR9_PCE_ISR_0_PINT_8_SIZE 1 -+/* Bit: 'PINT_7' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_7_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_7_SHIFT 7 -+#define VR9_PCE_ISR_0_PINT_7_SIZE 1 -+/* Bit: 'PINT_6' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_6_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_6_SHIFT 6 -+#define VR9_PCE_ISR_0_PINT_6_SIZE 1 -+/* Bit: 'PINT_5' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_5_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_5_SHIFT 5 -+#define VR9_PCE_ISR_0_PINT_5_SIZE 1 -+/* Bit: 'PINT_4' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_4_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_4_SHIFT 4 -+#define VR9_PCE_ISR_0_PINT_4_SIZE 1 -+/* Bit: 'PINT_3' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_3_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_3_SHIFT 3 -+#define VR9_PCE_ISR_0_PINT_3_SIZE 1 -+/* Bit: 'PINT_2' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_2_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_2_SHIFT 2 -+#define VR9_PCE_ISR_0_PINT_2_SIZE 1 -+/* Bit: 'PINT_1' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_1_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_1_SHIFT 1 -+#define VR9_PCE_ISR_0_PINT_1_SIZE 1 -+/* Bit: 'PINT_0' */ -+/* Description: 'Port Interrupt' */ -+#define VR9_PCE_ISR_0_PINT_0_OFFSET 0x467 -+#define VR9_PCE_ISR_0_PINT_0_SHIFT 0 -+#define VR9_PCE_ISR_0_PINT_0_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Global Interrupt Status Register 1' */ -+/* Bit: 'FLOWINT' */ -+/* Description: 'Traffic Flow Table Interrupt Rule matched' */ -+#define VR9_PCE_ISR_1_FLOWINT_OFFSET 0x468 -+#define VR9_PCE_ISR_1_FLOWINT_SHIFT 6 -+#define VR9_PCE_ISR_1_FLOWINT_SIZE 1 -+/* Bit: 'CPH2' */ -+/* Description: 'Classification Phase 2 Ready Interrupt' */ -+#define VR9_PCE_ISR_1_CPH2_OFFSET 0x468 -+#define VR9_PCE_ISR_1_CPH2_SHIFT 5 -+#define VR9_PCE_ISR_1_CPH2_SIZE 1 -+/* Bit: 'CPH1' */ -+/* Description: 'Classification Phase 1 Ready Interrupt' */ -+#define VR9_PCE_ISR_1_CPH1_OFFSET 0x468 -+#define VR9_PCE_ISR_1_CPH1_SHIFT 4 -+#define VR9_PCE_ISR_1_CPH1_SIZE 1 -+/* Bit: 'CPH0' */ -+/* Description: 'Classification Phase 0 Ready Interrupt' */ -+#define VR9_PCE_ISR_1_CPH0_OFFSET 0x468 -+#define VR9_PCE_ISR_1_CPH0_SHIFT 3 -+#define VR9_PCE_ISR_1_CPH0_SIZE 1 -+/* Bit: 'PRDY' */ -+/* Description: 'Parser Ready Interrupt' */ -+#define VR9_PCE_ISR_1_PRDY_OFFSET 0x468 -+#define VR9_PCE_ISR_1_PRDY_SHIFT 2 -+#define VR9_PCE_ISR_1_PRDY_SIZE 1 -+/* Bit: 'IGTF' */ -+/* Description: 'IGMP Table Full Interrupt' */ -+#define VR9_PCE_ISR_1_IGTF_OFFSET 0x468 -+#define VR9_PCE_ISR_1_IGTF_SHIFT 1 -+#define VR9_PCE_ISR_1_IGTF_SIZE 1 -+/* Bit: 'MTF' */ -+/* Description: 'MAC Table Full Interrupt' */ -+#define VR9_PCE_ISR_1_MTF_OFFSET 0x468 -+#define VR9_PCE_ISR_1_MTF_SHIFT 0 -+#define VR9_PCE_ISR_1_MTF_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser Status Register' */ -+/* Bit: 'FSM_DAT_CNT' */ -+/* Description: 'Parser FSM Data Counter' */ -+#define VR9_PARSER_STAT_FSM_DAT_CNT_OFFSET 0x469 -+#define VR9_PARSER_STAT_FSM_DAT_CNT_SHIFT 8 -+#define VR9_PARSER_STAT_FSM_DAT_CNT_SIZE 8 -+/* Bit: 'FSM_STATE' */ -+/* Description: 'Parser FSM State' */ -+#define VR9_PARSER_STAT_FSM_STATE_OFFSET 0x469 -+#define VR9_PARSER_STAT_FSM_STATE_SHIFT 5 -+#define VR9_PARSER_STAT_FSM_STATE_SIZE 3 -+/* Bit: 'PKT_ERR' */ -+/* Description: 'Packet error detected' */ -+#define VR9_PARSER_STAT_PKT_ERR_OFFSET 0x469 -+#define VR9_PARSER_STAT_PKT_ERR_SHIFT 4 -+#define VR9_PARSER_STAT_PKT_ERR_SIZE 1 -+/* Bit: 'FSM_FIN' */ -+/* Description: 'Parser FSM finished' */ -+#define VR9_PARSER_STAT_FSM_FIN_OFFSET 0x469 -+#define VR9_PARSER_STAT_FSM_FIN_SHIFT 3 -+#define VR9_PARSER_STAT_FSM_FIN_SIZE 1 -+/* Bit: 'FSM_START' */ -+/* Description: 'Parser FSM start' */ -+#define VR9_PARSER_STAT_FSM_START_OFFSET 0x469 -+#define VR9_PARSER_STAT_FSM_START_SHIFT 2 -+#define VR9_PARSER_STAT_FSM_START_SIZE 1 -+/* Bit: 'FIFO_RDY' */ -+/* Description: 'Parser FIFO ready for read.' */ -+#define VR9_PARSER_STAT_FIFO_RDY_OFFSET 0x469 -+#define VR9_PARSER_STAT_FIFO_RDY_SHIFT 1 -+#define VR9_PARSER_STAT_FIFO_RDY_SIZE 1 -+/* Bit: 'FIFO_FULL' */ -+/* Description: 'Parser's FIFO full' */ -+#define VR9_PARSER_STAT_FIFO_FULL_OFFSET 0x469 -+#define VR9_PARSER_STAT_FIFO_FULL_SHIFT 0 -+#define VR9_PARSER_STAT_FIFO_FULL_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Port ControlRegister 0' */ -+/* Bit: 'MCST' */ -+/* Description: 'Multicast Forwarding Mode Selection' */ -+#define VR9_PCE_PCTRL_0_MCST_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_MCST_SHIFT 13 -+#define VR9_PCE_PCTRL_0_MCST_SIZE 1 -+/* Bit: 'EGSTEN' */ -+/* Description: 'Table-based Egress Special Tag Enable' */ -+#define VR9_PCE_PCTRL_0_EGSTEN_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_EGSTEN_SHIFT 12 -+#define VR9_PCE_PCTRL_0_EGSTEN_SIZE 1 -+/* Bit: 'IGSTEN' */ -+/* Description: 'Ingress Special Tag Enable' */ -+#define VR9_PCE_PCTRL_0_IGSTEN_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_IGSTEN_SHIFT 11 -+#define VR9_PCE_PCTRL_0_IGSTEN_SIZE 1 -+/* Bit: 'PCPEN' */ -+/* Description: 'PCP Remarking Mode' */ -+#define VR9_PCE_PCTRL_0_PCPEN_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_PCPEN_SHIFT 10 -+#define VR9_PCE_PCTRL_0_PCPEN_SIZE 1 -+/* Bit: 'CLPEN' */ -+/* Description: 'Class Remarking Mode' */ -+#define VR9_PCE_PCTRL_0_CLPEN_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_CLPEN_SHIFT 9 -+#define VR9_PCE_PCTRL_0_CLPEN_SIZE 1 -+/* Bit: 'DPEN' */ -+/* Description: 'Drop Precedence Remarking Mode' */ -+#define VR9_PCE_PCTRL_0_DPEN_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_DPEN_SHIFT 8 -+#define VR9_PCE_PCTRL_0_DPEN_SIZE 1 -+/* Bit: 'CMOD' */ -+/* Description: 'Three-color Marker Color Mode' */ -+#define VR9_PCE_PCTRL_0_CMOD_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_CMOD_SHIFT 7 -+#define VR9_PCE_PCTRL_0_CMOD_SIZE 1 -+/* Bit: 'VREP' */ -+/* Description: 'VLAN Replacement Mode' */ -+#define VR9_PCE_PCTRL_0_VREP_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_VREP_SHIFT 6 -+#define VR9_PCE_PCTRL_0_VREP_SIZE 1 -+/* Bit: 'TVM' */ -+/* Description: 'Transparent VLAN Mode' */ -+#define VR9_PCE_PCTRL_0_TVM_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_TVM_SHIFT 5 -+#define VR9_PCE_PCTRL_0_TVM_SIZE 1 -+/* Bit: 'PLOCK' */ -+/* Description: 'Port Locking Enable' */ -+#define VR9_PCE_PCTRL_0_PLOCK_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_PLOCK_SHIFT 4 -+#define VR9_PCE_PCTRL_0_PLOCK_SIZE 1 -+/* Bit: 'AGEDIS' */ -+/* Description: 'Aging Disable' */ -+#define VR9_PCE_PCTRL_0_AGEDIS_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_AGEDIS_SHIFT 3 -+#define VR9_PCE_PCTRL_0_AGEDIS_SIZE 1 -+/* Bit: 'PSTATE' */ -+/* Description: 'Port State' */ -+#define VR9_PCE_PCTRL_0_PSTATE_OFFSET 0x480 -+#define VR9_PCE_PCTRL_0_PSTATE_SHIFT 0 -+#define VR9_PCE_PCTRL_0_PSTATE_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Port ControlRegister 1' */ -+/* Bit: 'LRNLIM' */ -+/* Description: 'MAC Address Learning Limit' */ -+#define VR9_PCE_PCTRL_1_LRNLIM_OFFSET 0x481 -+#define VR9_PCE_PCTRL_1_LRNLIM_SHIFT 0 -+#define VR9_PCE_PCTRL_1_LRNLIM_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Port ControlRegister 2' */ -+/* Bit: 'DSCPMOD' */ -+/* Description: 'DSCP Mode Selection' */ -+#define VR9_PCE_PCTRL_2_DSCPMOD_OFFSET 0x482 -+#define VR9_PCE_PCTRL_2_DSCPMOD_SHIFT 7 -+#define VR9_PCE_PCTRL_2_DSCPMOD_SIZE 1 -+/* Bit: 'DSCP' */ -+/* Description: 'Enable DSCP to select the Class of Service' */ -+#define VR9_PCE_PCTRL_2_DSCP_OFFSET 0x482 -+#define VR9_PCE_PCTRL_2_DSCP_SHIFT 5 -+#define VR9_PCE_PCTRL_2_DSCP_SIZE 2 -+/* Bit: 'PCP' */ -+/* Description: 'Enable VLAN PCP to select the Class of Service' */ -+#define VR9_PCE_PCTRL_2_PCP_OFFSET 0x482 -+#define VR9_PCE_PCTRL_2_PCP_SHIFT 4 -+#define VR9_PCE_PCTRL_2_PCP_SIZE 1 -+/* Bit: 'PCLASS' */ -+/* Description: 'Port-based Traffic Class' */ -+#define VR9_PCE_PCTRL_2_PCLASS_OFFSET 0x482 -+#define VR9_PCE_PCTRL_2_PCLASS_SHIFT 0 -+#define VR9_PCE_PCTRL_2_PCLASS_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Port ControlRegister 3' */ -+/* Bit: 'VIO_8' */ -+/* Description: 'Violation Type 8 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_8_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_8_SHIFT 12 -+#define VR9_PCE_PCTRL_3_VIO_8_SIZE 1 -+/* Bit: 'EDIR' */ -+/* Description: 'Egress Redirection Mode' */ -+#define VR9_PCE_PCTRL_3_EDIR_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_EDIR_SHIFT 11 -+#define VR9_PCE_PCTRL_3_EDIR_SIZE 1 -+/* Bit: 'RXDMIR' */ -+/* Description: 'Receive Mirroring Enable for dropped frames' */ -+#define VR9_PCE_PCTRL_3_RXDMIR_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_RXDMIR_SHIFT 10 -+#define VR9_PCE_PCTRL_3_RXDMIR_SIZE 1 -+/* Bit: 'RXVMIR' */ -+/* Description: 'Receive Mirroring Enable for valid frames' */ -+#define VR9_PCE_PCTRL_3_RXVMIR_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_RXVMIR_SHIFT 9 -+#define VR9_PCE_PCTRL_3_RXVMIR_SIZE 1 -+/* Bit: 'TXMIR' */ -+/* Description: 'Transmit Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_TXMIR_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_TXMIR_SHIFT 8 -+#define VR9_PCE_PCTRL_3_TXMIR_SIZE 1 -+/* Bit: 'VIO_7' */ -+/* Description: 'Violation Type 7 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_7_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_7_SHIFT 7 -+#define VR9_PCE_PCTRL_3_VIO_7_SIZE 1 -+/* Bit: 'VIO_6' */ -+/* Description: 'Violation Type 6 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_6_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_6_SHIFT 6 -+#define VR9_PCE_PCTRL_3_VIO_6_SIZE 1 -+/* Bit: 'VIO_5' */ -+/* Description: 'Violation Type 5 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_5_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_5_SHIFT 5 -+#define VR9_PCE_PCTRL_3_VIO_5_SIZE 1 -+/* Bit: 'VIO_4' */ -+/* Description: 'Violation Type 4 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_4_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_4_SHIFT 4 -+#define VR9_PCE_PCTRL_3_VIO_4_SIZE 1 -+/* Bit: 'VIO_3' */ -+/* Description: 'Violation Type 3 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_3_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_3_SHIFT 3 -+#define VR9_PCE_PCTRL_3_VIO_3_SIZE 1 -+/* Bit: 'VIO_2' */ -+/* Description: 'Violation Type 2 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_2_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_2_SHIFT 2 -+#define VR9_PCE_PCTRL_3_VIO_2_SIZE 1 -+/* Bit: 'VIO_1' */ -+/* Description: 'Violation Type 1 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_1_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_1_SHIFT 1 -+#define VR9_PCE_PCTRL_3_VIO_1_SIZE 1 -+/* Bit: 'VIO_0' */ -+/* Description: 'Violation Type 0 Mirroring Enable' */ -+#define VR9_PCE_PCTRL_3_VIO_0_OFFSET 0x483 -+#define VR9_PCE_PCTRL_3_VIO_0_SHIFT 0 -+#define VR9_PCE_PCTRL_3_VIO_0_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Wake-on-LAN ControlRegister' */ -+/* Bit: 'PORT' */ -+/* Description: 'WoL Enable' */ -+#define VR9_WOL_CTRL_PORT_OFFSET 0x484 -+#define VR9_WOL_CTRL_PORT_SHIFT 0 -+#define VR9_WOL_CTRL_PORT_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE VLAN ControlRegister' */ -+/* Bit: 'VID0' */ -+/* Description: 'Priority Tagged Rule' */ -+#define VR9_PCE_VCTRL_VID0_OFFSET 0x485 -+#define VR9_PCE_VCTRL_VID0_SHIFT 6 -+#define VR9_PCE_VCTRL_VID0_SIZE 1 -+/* Bit: 'VSR' */ -+/* Description: 'VLAN Security Rule' */ -+#define VR9_PCE_VCTRL_VSR_OFFSET 0x485 -+#define VR9_PCE_VCTRL_VSR_SHIFT 5 -+#define VR9_PCE_VCTRL_VSR_SIZE 1 -+/* Bit: 'VEMR' */ -+/* Description: 'VLAN Egress Member Violation Rule' */ -+#define VR9_PCE_VCTRL_VEMR_OFFSET 0x485 -+#define VR9_PCE_VCTRL_VEMR_SHIFT 4 -+#define VR9_PCE_VCTRL_VEMR_SIZE 1 -+/* Bit: 'VIMR' */ -+/* Description: 'VLAN Ingress Member Violation Rule' */ -+#define VR9_PCE_VCTRL_VIMR_OFFSET 0x485 -+#define VR9_PCE_VCTRL_VIMR_SHIFT 3 -+#define VR9_PCE_VCTRL_VIMR_SIZE 1 -+/* Bit: 'VINR' */ -+/* Description: 'VLAN Ingress Tag Rule' */ -+#define VR9_PCE_VCTRL_VINR_OFFSET 0x485 -+#define VR9_PCE_VCTRL_VINR_SHIFT 1 -+#define VR9_PCE_VCTRL_VINR_SIZE 2 -+/* Bit: 'UVR' */ -+/* Description: 'Unknown VLAN Rule' */ -+#define VR9_PCE_VCTRL_UVR_OFFSET 0x485 -+#define VR9_PCE_VCTRL_UVR_SHIFT 0 -+#define VR9_PCE_VCTRL_UVR_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Default PortVID Register' */ -+/* Bit: 'PVID' */ -+/* Description: 'Default Port VID Index' */ -+#define VR9_PCE_DEFPVID_PVID_OFFSET 0x486 -+#define VR9_PCE_DEFPVID_PVID_SHIFT 0 -+#define VR9_PCE_DEFPVID_PVID_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PCE Port StatusRegister' */ -+/* Bit: 'LRNCNT' */ -+/* Description: 'Learning Count' */ -+#define VR9_PCE_PSTAT_LRNCNT_OFFSET 0x487 -+#define VR9_PCE_PSTAT_LRNCNT_SHIFT 0 -+#define VR9_PCE_PSTAT_LRNCNT_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Port Interrupt Enable Register' */ -+/* Bit: 'FRZDRP' */ -+/* Description: 'MAC Table Freeze Drop Interrupt Enable' */ -+#define VR9_PCE_PIER_FRZDRP_OFFSET 0x488 -+#define VR9_PCE_PIER_FRZDRP_SHIFT 6 -+#define VR9_PCE_PIER_FRZDRP_SIZE 1 -+/* Bit: 'CLDRP' */ -+/* Description: 'Classification Drop Interrupt Enable' */ -+#define VR9_PCE_PIER_CLDRP_OFFSET 0x488 -+#define VR9_PCE_PIER_CLDRP_SHIFT 5 -+#define VR9_PCE_PIER_CLDRP_SIZE 1 -+/* Bit: 'PTDRP' */ -+/* Description: 'Port Drop Interrupt Enable' */ -+#define VR9_PCE_PIER_PTDRP_OFFSET 0x488 -+#define VR9_PCE_PIER_PTDRP_SHIFT 4 -+#define VR9_PCE_PIER_PTDRP_SIZE 1 -+/* Bit: 'VLAN' */ -+/* Description: 'VLAN Violation Interrupt Enable' */ -+#define VR9_PCE_PIER_VLAN_OFFSET 0x488 -+#define VR9_PCE_PIER_VLAN_SHIFT 3 -+#define VR9_PCE_PIER_VLAN_SIZE 1 -+/* Bit: 'WOL' */ -+/* Description: 'Wake-on-LAN Interrupt Enable' */ -+#define VR9_PCE_PIER_WOL_OFFSET 0x488 -+#define VR9_PCE_PIER_WOL_SHIFT 2 -+#define VR9_PCE_PIER_WOL_SIZE 1 -+/* Bit: 'LOCK' */ -+/* Description: 'Port Lock Alert Interrupt Enable' */ -+#define VR9_PCE_PIER_LOCK_OFFSET 0x488 -+#define VR9_PCE_PIER_LOCK_SHIFT 1 -+#define VR9_PCE_PIER_LOCK_SIZE 1 -+/* Bit: 'LIM' */ -+/* Description: 'Port Limit Alert Interrupt Enable' */ -+#define VR9_PCE_PIER_LIM_OFFSET 0x488 -+#define VR9_PCE_PIER_LIM_SHIFT 0 -+#define VR9_PCE_PIER_LIM_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Parser and ClassificationEngine Port Interrupt Status Register' */ -+/* Bit: 'FRZDRP' */ -+/* Description: 'MAC Table Freeze Drop Interrupt' */ -+#define VR9_PCE_PISR_FRZDRP_OFFSET 0x489 -+#define VR9_PCE_PISR_FRZDRP_SHIFT 6 -+#define VR9_PCE_PISR_FRZDRP_SIZE 1 -+/* Bit: 'CLDRP' */ -+/* Description: 'Classification Drop Interrupt' */ -+#define VR9_PCE_PISR_CLDRP_OFFSET 0x489 -+#define VR9_PCE_PISR_CLDRP_SHIFT 5 -+#define VR9_PCE_PISR_CLDRP_SIZE 1 -+/* Bit: 'PTDRP' */ -+/* Description: 'Port Drop Interrupt' */ -+#define VR9_PCE_PISR_PTDRP_OFFSET 0x489 -+#define VR9_PCE_PISR_PTDRP_SHIFT 4 -+#define VR9_PCE_PISR_PTDRP_SIZE 1 -+/* Bit: 'VLAN' */ -+/* Description: 'VLAN Violation Interrupt' */ -+#define VR9_PCE_PISR_VLAN_OFFSET 0x489 -+#define VR9_PCE_PISR_VLAN_SHIFT 3 -+#define VR9_PCE_PISR_VLAN_SIZE 1 -+/* Bit: 'WOL' */ -+/* Description: 'Wake-on-LAN Interrupt' */ -+#define VR9_PCE_PISR_WOL_OFFSET 0x489 -+#define VR9_PCE_PISR_WOL_SHIFT 2 -+#define VR9_PCE_PISR_WOL_SIZE 1 -+/* Bit: 'LOCK' */ -+/* Description: 'Port Lock Alert Interrupt' */ -+#define VR9_PCE_PISR_LOCK_OFFSET 0x489 -+#define VR9_PCE_PISR_LOCK_SHIFT 1 -+#define VR9_PCE_PISR_LOCK_SIZE 1 -+/* Bit: 'LIMIT' */ -+/* Description: 'Port Limitation Alert Interrupt' */ -+#define VR9_PCE_PISR_LIMIT_OFFSET 0x489 -+#define VR9_PCE_PISR_LIMIT_SHIFT 0 -+#define VR9_PCE_PISR_LIMIT_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-colorMarker Control Register' */ -+/* Bit: 'TCMEN' */ -+/* Description: 'Three-color Marker metering instance enable' */ -+#define VR9_PCE_TCM_CTRL_TCMEN_OFFSET 0x580 -+#define VR9_PCE_TCM_CTRL_TCMEN_SHIFT 0 -+#define VR9_PCE_TCM_CTRL_TCMEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-colorMarker Status Register' */ -+/* Bit: 'AL1' */ -+/* Description: 'Three-color Marker Alert 1 Status' */ -+#define VR9_PCE_TCM_STAT_AL1_OFFSET 0x581 -+#define VR9_PCE_TCM_STAT_AL1_SHIFT 1 -+#define VR9_PCE_TCM_STAT_AL1_SIZE 1 -+/* Bit: 'AL0' */ -+/* Description: 'Three-color Marker Alert 0 Status' */ -+#define VR9_PCE_TCM_STAT_AL0_OFFSET 0x581 -+#define VR9_PCE_TCM_STAT_AL0_SHIFT 0 -+#define VR9_PCE_TCM_STAT_AL0_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-color MarkerCommitted Burst Size Register' */ -+/* Bit: 'CBS' */ -+/* Description: 'Committed Burst Size' */ -+#define VR9_PCE_TCM_CBS_CBS_OFFSET 0x582 -+#define VR9_PCE_TCM_CBS_CBS_SHIFT 0 -+#define VR9_PCE_TCM_CBS_CBS_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-color MarkerExcess Burst Size Register' */ -+/* Bit: 'EBS' */ -+/* Description: 'Excess Burst Size' */ -+#define VR9_PCE_TCM_EBS_EBS_OFFSET 0x583 -+#define VR9_PCE_TCM_EBS_EBS_SHIFT 0 -+#define VR9_PCE_TCM_EBS_EBS_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-color MarkerInstantaneous Burst Size Register' */ -+/* Bit: 'IBS' */ -+/* Description: 'Instantaneous Burst Size' */ -+#define VR9_PCE_TCM_IBS_IBS_OFFSET 0x584 -+#define VR9_PCE_TCM_IBS_IBS_SHIFT 0 -+#define VR9_PCE_TCM_IBS_IBS_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-colorMarker Constant Information Rate Mantissa Register' */ -+/* Bit: 'MANT' */ -+/* Description: 'Rate Counter Mantissa' */ -+#define VR9_PCE_TCM_CIR_MANT_MANT_OFFSET 0x585 -+#define VR9_PCE_TCM_CIR_MANT_MANT_SHIFT 0 -+#define VR9_PCE_TCM_CIR_MANT_MANT_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Three-colorMarker Constant Information Rate Exponent Register' */ -+/* Bit: 'EXP' */ -+/* Description: 'Rate Counter Exponent' */ -+#define VR9_PCE_TCM_CIR_EXP_EXP_OFFSET 0x586 -+#define VR9_PCE_TCM_CIR_EXP_EXP_SHIFT 0 -+#define VR9_PCE_TCM_CIR_EXP_EXP_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Test Register' */ -+/* Bit: 'JTP' */ -+/* Description: 'Jitter Test Pattern' */ -+#define VR9_MAC_TEST_JTP_OFFSET 0x8C0 -+#define VR9_MAC_TEST_JTP_SHIFT 0 -+#define VR9_MAC_TEST_JTP_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Pause FrameSource Address Configuration Register' */ -+/* Bit: 'SAMOD' */ -+/* Description: 'Source Address Mode' */ -+#define VR9_MAC_PFAD_CFG_SAMOD_OFFSET 0x8C1 -+#define VR9_MAC_PFAD_CFG_SAMOD_SHIFT 0 -+#define VR9_MAC_PFAD_CFG_SAMOD_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Pause Frame SourceAddress Part 0 ' */ -+/* Bit: 'PFAD' */ -+/* Description: 'Pause Frame Source Address Part 0' */ -+#define VR9_MAC_PFSA_0_PFAD_OFFSET 0x8C2 -+#define VR9_MAC_PFSA_0_PFAD_SHIFT 0 -+#define VR9_MAC_PFSA_0_PFAD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Pause Frame SourceAddress Part 1 ' */ -+/* Bit: 'PFAD' */ -+/* Description: 'Pause Frame Source Address Part 1' */ -+#define VR9_MAC_PFSA_1_PFAD_OFFSET 0x8C3 -+#define VR9_MAC_PFSA_1_PFAD_SHIFT 0 -+#define VR9_MAC_PFSA_1_PFAD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Pause Frame SourceAddress Part 2 ' */ -+/* Bit: 'PFAD' */ -+/* Description: 'Pause Frame Source Address Part 2' */ -+#define VR9_MAC_PFSA_2_PFAD_OFFSET 0x8C4 -+#define VR9_MAC_PFSA_2_PFAD_SHIFT 0 -+#define VR9_MAC_PFSA_2_PFAD_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Frame Length Register' */ -+/* Bit: 'LEN' */ -+/* Description: 'Maximum Frame Length' */ -+#define VR9_MAC_FLEN_LEN_OFFSET 0x8C5 -+#define VR9_MAC_FLEN_LEN_SHIFT 0 -+#define VR9_MAC_FLEN_LEN_SIZE 14 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC VLAN EthertypeRegister 0' */ -+/* Bit: 'OUTER' */ -+/* Description: 'Ethertype' */ -+#define VR9_MAC_VLAN_ETYPE_0_OUTER_OFFSET 0x8C6 -+#define VR9_MAC_VLAN_ETYPE_0_OUTER_SHIFT 0 -+#define VR9_MAC_VLAN_ETYPE_0_OUTER_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC VLAN EthertypeRegister 1' */ -+/* Bit: 'INNER' */ -+/* Description: 'Ethertype' */ -+#define VR9_MAC_VLAN_ETYPE_1_INNER_OFFSET 0x8C7 -+#define VR9_MAC_VLAN_ETYPE_1_INNER_SHIFT 0 -+#define VR9_MAC_VLAN_ETYPE_1_INNER_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Interrupt EnableRegister' */ -+/* Bit: 'MACIEN' */ -+/* Description: 'MAC Interrupt Enable' */ -+#define VR9_MAC_IER_MACIEN_OFFSET 0x8C8 -+#define VR9_MAC_IER_MACIEN_SHIFT 0 -+#define VR9_MAC_IER_MACIEN_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Interrupt StatusRegister' */ -+/* Bit: 'MACINT' */ -+/* Description: 'MAC Interrupt' */ -+#define VR9_MAC_ISR_MACINT_OFFSET 0x8C9 -+#define VR9_MAC_ISR_MACINT_SHIFT 0 -+#define VR9_MAC_ISR_MACINT_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Port Status Register' */ -+/* Bit: 'PACT' */ -+/* Description: 'PHY Active Status' */ -+#define VR9_MAC_PSTAT_PACT_OFFSET 0x900 -+#define VR9_MAC_PSTAT_PACT_SHIFT 11 -+#define VR9_MAC_PSTAT_PACT_SIZE 1 -+/* Bit: 'GBIT' */ -+/* Description: 'Gigabit Speed Status' */ -+#define VR9_MAC_PSTAT_GBIT_OFFSET 0x900 -+#define VR9_MAC_PSTAT_GBIT_SHIFT 10 -+#define VR9_MAC_PSTAT_GBIT_SIZE 1 -+/* Bit: 'MBIT' */ -+/* Description: 'Megabit Speed Status' */ -+#define VR9_MAC_PSTAT_MBIT_OFFSET 0x900 -+#define VR9_MAC_PSTAT_MBIT_SHIFT 9 -+#define VR9_MAC_PSTAT_MBIT_SIZE 1 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Status' */ -+#define VR9_MAC_PSTAT_FDUP_OFFSET 0x900 -+#define VR9_MAC_PSTAT_FDUP_SHIFT 8 -+#define VR9_MAC_PSTAT_FDUP_SIZE 1 -+/* Bit: 'RXPAU' */ -+/* Description: 'Receive Pause Status' */ -+#define VR9_MAC_PSTAT_RXPAU_OFFSET 0x900 -+#define VR9_MAC_PSTAT_RXPAU_SHIFT 7 -+#define VR9_MAC_PSTAT_RXPAU_SIZE 1 -+/* Bit: 'TXPAU' */ -+/* Description: 'Transmit Pause Status' */ -+#define VR9_MAC_PSTAT_TXPAU_OFFSET 0x900 -+#define VR9_MAC_PSTAT_TXPAU_SHIFT 6 -+#define VR9_MAC_PSTAT_TXPAU_SIZE 1 -+/* Bit: 'RXPAUEN' */ -+/* Description: 'Receive Pause Enable Status' */ -+#define VR9_MAC_PSTAT_RXPAUEN_OFFSET 0x900 -+#define VR9_MAC_PSTAT_RXPAUEN_SHIFT 5 -+#define VR9_MAC_PSTAT_RXPAUEN_SIZE 1 -+/* Bit: 'TXPAUEN' */ -+/* Description: 'Transmit Pause Enable Status' */ -+#define VR9_MAC_PSTAT_TXPAUEN_OFFSET 0x900 -+#define VR9_MAC_PSTAT_TXPAUEN_SHIFT 4 -+#define VR9_MAC_PSTAT_TXPAUEN_SIZE 1 -+/* Bit: 'LSTAT' */ -+/* Description: 'Link Status' */ -+#define VR9_MAC_PSTAT_LSTAT_OFFSET 0x900 -+#define VR9_MAC_PSTAT_LSTAT_SHIFT 3 -+#define VR9_MAC_PSTAT_LSTAT_SIZE 1 -+/* Bit: 'CRS' */ -+/* Description: 'Carrier Sense Status' */ -+#define VR9_MAC_PSTAT_CRS_OFFSET 0x900 -+#define VR9_MAC_PSTAT_CRS_SHIFT 2 -+#define VR9_MAC_PSTAT_CRS_SIZE 1 -+/* Bit: 'TXLPI' */ -+/* Description: 'Transmit Low-power Idle Status' */ -+#define VR9_MAC_PSTAT_TXLPI_OFFSET 0x900 -+#define VR9_MAC_PSTAT_TXLPI_SHIFT 1 -+#define VR9_MAC_PSTAT_TXLPI_SIZE 1 -+/* Bit: 'RXLPI' */ -+/* Description: 'Receive Low-power Idle Status' */ -+#define VR9_MAC_PSTAT_RXLPI_OFFSET 0x900 -+#define VR9_MAC_PSTAT_RXLPI_SHIFT 0 -+#define VR9_MAC_PSTAT_RXLPI_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Interrupt Status Register' */ -+/* Bit: 'PHYERR' */ -+/* Description: 'PHY Error Interrupt' */ -+#define VR9_MAC_PISR_PHYERR_OFFSET 0x901 -+#define VR9_MAC_PISR_PHYERR_SHIFT 15 -+#define VR9_MAC_PISR_PHYERR_SIZE 1 -+/* Bit: 'ALIGN' */ -+/* Description: 'Allignment Error Interrupt' */ -+#define VR9_MAC_PISR_ALIGN_OFFSET 0x901 -+#define VR9_MAC_PISR_ALIGN_SHIFT 14 -+#define VR9_MAC_PISR_ALIGN_SIZE 1 -+/* Bit: 'PACT' */ -+/* Description: 'PHY Active Status' */ -+#define VR9_MAC_PISR_PACT_OFFSET 0x901 -+#define VR9_MAC_PISR_PACT_SHIFT 13 -+#define VR9_MAC_PISR_PACT_SIZE 1 -+/* Bit: 'SPEED' */ -+/* Description: 'Megabit Speed Status' */ -+#define VR9_MAC_PISR_SPEED_OFFSET 0x901 -+#define VR9_MAC_PISR_SPEED_SHIFT 12 -+#define VR9_MAC_PISR_SPEED_SIZE 1 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Status' */ -+#define VR9_MAC_PISR_FDUP_OFFSET 0x901 -+#define VR9_MAC_PISR_FDUP_SHIFT 11 -+#define VR9_MAC_PISR_FDUP_SIZE 1 -+/* Bit: 'RXPAUEN' */ -+/* Description: 'Receive Pause Enable Status' */ -+#define VR9_MAC_PISR_RXPAUEN_OFFSET 0x901 -+#define VR9_MAC_PISR_RXPAUEN_SHIFT 10 -+#define VR9_MAC_PISR_RXPAUEN_SIZE 1 -+/* Bit: 'TXPAUEN' */ -+/* Description: 'Transmit Pause Enable Status' */ -+#define VR9_MAC_PISR_TXPAUEN_OFFSET 0x901 -+#define VR9_MAC_PISR_TXPAUEN_SHIFT 9 -+#define VR9_MAC_PISR_TXPAUEN_SIZE 1 -+/* Bit: 'LPIOFF' */ -+/* Description: 'Receive Low-power Idle Mode is left' */ -+#define VR9_MAC_PISR_LPIOFF_OFFSET 0x901 -+#define VR9_MAC_PISR_LPIOFF_SHIFT 8 -+#define VR9_MAC_PISR_LPIOFF_SIZE 1 -+/* Bit: 'LPION' */ -+/* Description: 'Receive Low-power Idle Mode is entered' */ -+#define VR9_MAC_PISR_LPION_OFFSET 0x901 -+#define VR9_MAC_PISR_LPION_SHIFT 7 -+#define VR9_MAC_PISR_LPION_SIZE 1 -+/* Bit: 'JAM' */ -+/* Description: 'Jam Status Detected' */ -+#define VR9_MAC_PISR_JAM_OFFSET 0x901 -+#define VR9_MAC_PISR_JAM_SHIFT 6 -+#define VR9_MAC_PISR_JAM_SIZE 1 -+/* Bit: 'TOOSHORT' */ -+/* Description: 'Too Short Frame Error Detected' */ -+#define VR9_MAC_PISR_TOOSHORT_OFFSET 0x901 -+#define VR9_MAC_PISR_TOOSHORT_SHIFT 5 -+#define VR9_MAC_PISR_TOOSHORT_SIZE 1 -+/* Bit: 'TOOLONG' */ -+/* Description: 'Too Long Frame Error Detected' */ -+#define VR9_MAC_PISR_TOOLONG_OFFSET 0x901 -+#define VR9_MAC_PISR_TOOLONG_SHIFT 4 -+#define VR9_MAC_PISR_TOOLONG_SIZE 1 -+/* Bit: 'LENERR' */ -+/* Description: 'Length Mismatch Error Detected' */ -+#define VR9_MAC_PISR_LENERR_OFFSET 0x901 -+#define VR9_MAC_PISR_LENERR_SHIFT 3 -+#define VR9_MAC_PISR_LENERR_SIZE 1 -+/* Bit: 'FCSERR' */ -+/* Description: 'Frame Checksum Error Detected' */ -+#define VR9_MAC_PISR_FCSERR_OFFSET 0x901 -+#define VR9_MAC_PISR_FCSERR_SHIFT 2 -+#define VR9_MAC_PISR_FCSERR_SIZE 1 -+/* Bit: 'TXPAUSE' */ -+/* Description: 'Pause Frame Transmitted' */ -+#define VR9_MAC_PISR_TXPAUSE_OFFSET 0x901 -+#define VR9_MAC_PISR_TXPAUSE_SHIFT 1 -+#define VR9_MAC_PISR_TXPAUSE_SIZE 1 -+/* Bit: 'RXPAUSE' */ -+/* Description: 'Pause Frame Received' */ -+#define VR9_MAC_PISR_RXPAUSE_OFFSET 0x901 -+#define VR9_MAC_PISR_RXPAUSE_SHIFT 0 -+#define VR9_MAC_PISR_RXPAUSE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Interrupt Enable Register' */ -+/* Bit: 'PHYERR' */ -+/* Description: 'PHY Error Interrupt' */ -+#define VR9_MAC_PIER_PHYERR_OFFSET 0x902 -+#define VR9_MAC_PIER_PHYERR_SHIFT 15 -+#define VR9_MAC_PIER_PHYERR_SIZE 1 -+/* Bit: 'ALIGN' */ -+/* Description: 'Allignment Error Interrupt' */ -+#define VR9_MAC_PIER_ALIGN_OFFSET 0x902 -+#define VR9_MAC_PIER_ALIGN_SHIFT 14 -+#define VR9_MAC_PIER_ALIGN_SIZE 1 -+/* Bit: 'PACT' */ -+/* Description: 'PHY Active Status' */ -+#define VR9_MAC_PIER_PACT_OFFSET 0x902 -+#define VR9_MAC_PIER_PACT_SHIFT 13 -+#define VR9_MAC_PIER_PACT_SIZE 1 -+/* Bit: 'SPEED' */ -+/* Description: 'Megabit Speed Status' */ -+#define VR9_MAC_PIER_SPEED_OFFSET 0x902 -+#define VR9_MAC_PIER_SPEED_SHIFT 12 -+#define VR9_MAC_PIER_SPEED_SIZE 1 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Status' */ -+#define VR9_MAC_PIER_FDUP_OFFSET 0x902 -+#define VR9_MAC_PIER_FDUP_SHIFT 11 -+#define VR9_MAC_PIER_FDUP_SIZE 1 -+/* Bit: 'RXPAUEN' */ -+/* Description: 'Receive Pause Enable Status' */ -+#define VR9_MAC_PIER_RXPAUEN_OFFSET 0x902 -+#define VR9_MAC_PIER_RXPAUEN_SHIFT 10 -+#define VR9_MAC_PIER_RXPAUEN_SIZE 1 -+/* Bit: 'TXPAUEN' */ -+/* Description: 'Transmit Pause Enable Status' */ -+#define VR9_MAC_PIER_TXPAUEN_OFFSET 0x902 -+#define VR9_MAC_PIER_TXPAUEN_SHIFT 9 -+#define VR9_MAC_PIER_TXPAUEN_SIZE 1 -+/* Bit: 'LPIOFF' */ -+/* Description: 'Low-power Idle Off Interrupt Mask' */ -+#define VR9_MAC_PIER_LPIOFF_OFFSET 0x902 -+#define VR9_MAC_PIER_LPIOFF_SHIFT 8 -+#define VR9_MAC_PIER_LPIOFF_SIZE 1 -+/* Bit: 'LPION' */ -+/* Description: 'Low-power Idle On Interrupt Mask' */ -+#define VR9_MAC_PIER_LPION_OFFSET 0x902 -+#define VR9_MAC_PIER_LPION_SHIFT 7 -+#define VR9_MAC_PIER_LPION_SIZE 1 -+/* Bit: 'JAM' */ -+/* Description: 'Jam Status Interrupt Mask' */ -+#define VR9_MAC_PIER_JAM_OFFSET 0x902 -+#define VR9_MAC_PIER_JAM_SHIFT 6 -+#define VR9_MAC_PIER_JAM_SIZE 1 -+/* Bit: 'TOOSHORT' */ -+/* Description: 'Too Short Frame Error Interrupt Mask' */ -+#define VR9_MAC_PIER_TOOSHORT_OFFSET 0x902 -+#define VR9_MAC_PIER_TOOSHORT_SHIFT 5 -+#define VR9_MAC_PIER_TOOSHORT_SIZE 1 -+/* Bit: 'TOOLONG' */ -+/* Description: 'Too Long Frame Error Interrupt Mask' */ -+#define VR9_MAC_PIER_TOOLONG_OFFSET 0x902 -+#define VR9_MAC_PIER_TOOLONG_SHIFT 4 -+#define VR9_MAC_PIER_TOOLONG_SIZE 1 -+/* Bit: 'LENERR' */ -+/* Description: 'Length Mismatch Error Interrupt Mask' */ -+#define VR9_MAC_PIER_LENERR_OFFSET 0x902 -+#define VR9_MAC_PIER_LENERR_SHIFT 3 -+#define VR9_MAC_PIER_LENERR_SIZE 1 -+/* Bit: 'FCSERR' */ -+/* Description: 'Frame Checksum Error Interrupt Mask' */ -+#define VR9_MAC_PIER_FCSERR_OFFSET 0x902 -+#define VR9_MAC_PIER_FCSERR_SHIFT 2 -+#define VR9_MAC_PIER_FCSERR_SIZE 1 -+/* Bit: 'TXPAUSE' */ -+/* Description: 'Transmit Pause Frame Interrupt Mask' */ -+#define VR9_MAC_PIER_TXPAUSE_OFFSET 0x902 -+#define VR9_MAC_PIER_TXPAUSE_SHIFT 1 -+#define VR9_MAC_PIER_TXPAUSE_SIZE 1 -+/* Bit: 'RXPAUSE' */ -+/* Description: 'Receive Pause Frame Interrupt Mask' */ -+#define VR9_MAC_PIER_RXPAUSE_OFFSET 0x902 -+#define VR9_MAC_PIER_RXPAUSE_SHIFT 0 -+#define VR9_MAC_PIER_RXPAUSE_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register0' */ -+/* Bit: 'BM' */ -+/* Description: 'Burst Mode Control' */ -+#define VR9_MAC_CTRL_0_BM_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_BM_SHIFT 12 -+#define VR9_MAC_CTRL_0_BM_SIZE 1 -+/* Bit: 'APADEN' */ -+/* Description: 'Automatic VLAN Padding Enable' */ -+#define VR9_MAC_CTRL_0_APADEN_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_APADEN_SHIFT 11 -+#define VR9_MAC_CTRL_0_APADEN_SIZE 1 -+/* Bit: 'VPAD2EN' */ -+/* Description: 'Stacked VLAN Padding Enable' */ -+#define VR9_MAC_CTRL_0_VPAD2EN_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_VPAD2EN_SHIFT 10 -+#define VR9_MAC_CTRL_0_VPAD2EN_SIZE 1 -+/* Bit: 'VPADEN' */ -+/* Description: 'VLAN Padding Enable' */ -+#define VR9_MAC_CTRL_0_VPADEN_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_VPADEN_SHIFT 9 -+#define VR9_MAC_CTRL_0_VPADEN_SIZE 1 -+/* Bit: 'PADEN' */ -+/* Description: 'Padding Enable' */ -+#define VR9_MAC_CTRL_0_PADEN_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_PADEN_SHIFT 8 -+#define VR9_MAC_CTRL_0_PADEN_SIZE 1 -+/* Bit: 'FCS' */ -+/* Description: 'Transmit FCS Control' */ -+#define VR9_MAC_CTRL_0_FCS_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_FCS_SHIFT 7 -+#define VR9_MAC_CTRL_0_FCS_SIZE 1 -+/* Bit: 'FCON' */ -+/* Description: 'Flow Control Mode' */ -+#define VR9_MAC_CTRL_0_FCON_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_FCON_SHIFT 4 -+#define VR9_MAC_CTRL_0_FCON_SIZE 3 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_MAC_CTRL_0_FDUP_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_FDUP_SHIFT 2 -+#define VR9_MAC_CTRL_0_FDUP_SIZE 2 -+/* Bit: 'GMII' */ -+/* Description: 'GMII/MII interface mode selection' */ -+#define VR9_MAC_CTRL_0_GMII_OFFSET 0x903 -+#define VR9_MAC_CTRL_0_GMII_SHIFT 0 -+#define VR9_MAC_CTRL_0_GMII_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register1' */ -+/* Bit: 'DEFERMODE' */ -+/* Description: 'Defer Model' */ -+#define VR9_MAC_CTRL_1_DEFERMODE_OFFSET 0x904 -+#define VR9_MAC_CTRL_1_DEFERMODE_SHIFT 15 -+#define VR9_MAC_CTRL_1_DEFERMODE_SIZE 1 -+/* Bit: 'SHORTPRE' */ -+/* Description: 'Short Preamble Control' */ -+#define VR9_MAC_CTRL_1_SHORTPRE_OFFSET 0x904 -+#define VR9_MAC_CTRL_1_SHORTPRE_SHIFT 8 -+#define VR9_MAC_CTRL_1_SHORTPRE_SIZE 1 -+/* Bit: 'IPG' */ -+/* Description: 'Minimum Inter Packet Gap Size' */ -+#define VR9_MAC_CTRL_1_IPG_OFFSET 0x904 -+#define VR9_MAC_CTRL_1_IPG_SHIFT 0 -+#define VR9_MAC_CTRL_1_IPG_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register2' */ -+/* Bit: 'MLEN' */ -+/* Description: 'Maximum Untagged Frame Length' */ -+#define VR9_MAC_CTRL_2_MLEN_OFFSET 0x905 -+#define VR9_MAC_CTRL_2_MLEN_SHIFT 3 -+#define VR9_MAC_CTRL_2_MLEN_SIZE 1 -+/* Bit: 'LCHKL' */ -+/* Description: 'Frame Length Check Long Enable' */ -+#define VR9_MAC_CTRL_2_LCHKL_OFFSET 0x905 -+#define VR9_MAC_CTRL_2_LCHKL_SHIFT 2 -+#define VR9_MAC_CTRL_2_LCHKL_SIZE 1 -+/* Bit: 'LCHKS' */ -+/* Description: 'Frame Length Check Short Enable' */ -+#define VR9_MAC_CTRL_2_LCHKS_OFFSET 0x905 -+#define VR9_MAC_CTRL_2_LCHKS_SHIFT 0 -+#define VR9_MAC_CTRL_2_LCHKS_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register3' */ -+/* Bit: 'RCNT' */ -+/* Description: 'Retry Count' */ -+#define VR9_MAC_CTRL_3_RCNT_OFFSET 0x906 -+#define VR9_MAC_CTRL_3_RCNT_SHIFT 0 -+#define VR9_MAC_CTRL_3_RCNT_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register4' */ -+/* Bit: 'GWAIT' */ -+/* Description: 'LPI Wait Time for 1G' */ -+#define VR9_MAC_CTRL_4_GWAIT_OFFSET 0x907 -+#define VR9_MAC_CTRL_4_GWAIT_SHIFT 8 -+#define VR9_MAC_CTRL_4_GWAIT_SIZE 7 -+/* Bit: 'LPIEN' */ -+/* Description: 'LPI Mode Enable' */ -+#define VR9_MAC_CTRL_4_LPIEN_OFFSET 0x907 -+#define VR9_MAC_CTRL_4_LPIEN_SHIFT 7 -+#define VR9_MAC_CTRL_4_LPIEN_SIZE 1 -+/* Bit: 'WAIT' */ -+/* Description: 'LPI Wait Time for 100M' */ -+#define VR9_MAC_CTRL_4_WAIT_OFFSET 0x907 -+#define VR9_MAC_CTRL_4_WAIT_SHIFT 0 -+#define VR9_MAC_CTRL_4_WAIT_SIZE 7 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Control Register5' */ -+/* Bit: 'PJPS_NOBP' */ -+/* Description: 'Prolonged Jam pattern size during no-backpressure -+state' */ -+#define VR9_MAC_CTRL_5_PJPS_NOBP_OFFSET 0x908 -+#define VR9_MAC_CTRL_5_PJPS_NOBP_SHIFT 1 -+#define VR9_MAC_CTRL_5_PJPS_NOBP_SIZE 1 -+/* Bit: 'PJPS_BP' */ -+/* Description: 'Prolonged Jam pattern size during backpressure state' */ -+#define VR9_MAC_CTRL_5_PJPS_BP_OFFSET 0x908 -+#define VR9_MAC_CTRL_5_PJPS_BP_SHIFT 0 -+#define VR9_MAC_CTRL_5_PJPS_BP_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MAC Test Enable Register' */ -+/* Bit: 'JTEN' */ -+/* Description: 'Jitter Test Enable' */ -+#define VR9_MAC_TESTEN_JTEN_OFFSET 0x90B -+#define VR9_MAC_TESTEN_JTEN_SHIFT 2 -+#define VR9_MAC_TESTEN_JTEN_SIZE 1 -+/* Bit: 'TXER' */ -+/* Description: 'Transmit Error Insertion' */ -+#define VR9_MAC_TESTEN_TXER_OFFSET 0x90B -+#define VR9_MAC_TESTEN_TXER_SHIFT 1 -+#define VR9_MAC_TESTEN_TXER_SIZE 1 -+/* Bit: 'LOOP' */ -+/* Description: 'MAC Loopback Enable' */ -+#define VR9_MAC_TESTEN_LOOP_OFFSET 0x90B -+#define VR9_MAC_TESTEN_LOOP_SHIFT 0 -+#define VR9_MAC_TESTEN_LOOP_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch FetchDMA Control Register' */ -+/* Bit: 'EGCNT' */ -+/* Description: 'Egress Special Tag RMON count' */ -+#define VR9_FDMA_CTRL_EGCNT_OFFSET 0xA40 -+#define VR9_FDMA_CTRL_EGCNT_SHIFT 7 -+#define VR9_FDMA_CTRL_EGCNT_SIZE 1 -+/* Bit: 'LPI_MODE' */ -+/* Description: 'Low Power Idle Mode' */ -+#define VR9_FDMA_CTRL_LPI_MODE_OFFSET 0xA40 -+#define VR9_FDMA_CTRL_LPI_MODE_SHIFT 4 -+#define VR9_FDMA_CTRL_LPI_MODE_SIZE 3 -+/* Bit: 'EGSTAG' */ -+/* Description: 'Egress Special Tag Size' */ -+#define VR9_FDMA_CTRL_EGSTAG_OFFSET 0xA40 -+#define VR9_FDMA_CTRL_EGSTAG_SHIFT 2 -+#define VR9_FDMA_CTRL_EGSTAG_SIZE 2 -+/* Bit: 'IGSTAG' */ -+/* Description: 'Ingress Special Tag Size' */ -+#define VR9_FDMA_CTRL_IGSTAG_OFFSET 0xA40 -+#define VR9_FDMA_CTRL_IGSTAG_SHIFT 1 -+#define VR9_FDMA_CTRL_IGSTAG_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Special Tag EthertypeControl Register' */ -+/* Bit: 'ETYPE' */ -+/* Description: 'Special Tag Ethertype' */ -+#define VR9_FDMA_STETYPE_ETYPE_OFFSET 0xA41 -+#define VR9_FDMA_STETYPE_ETYPE_SHIFT 0 -+#define VR9_FDMA_STETYPE_ETYPE_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'VLAN Tag EthertypeControl Register' */ -+/* Bit: 'ETYPE' */ -+/* Description: 'VLAN Tag Ethertype' */ -+#define VR9_FDMA_VTETYPE_ETYPE_OFFSET 0xA42 -+#define VR9_FDMA_VTETYPE_ETYPE_SHIFT 0 -+#define VR9_FDMA_VTETYPE_ETYPE_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'FDMA Status Register0' */ -+/* Bit: 'FSMS' */ -+/* Description: 'FSM states status' */ -+#define VR9_FDMA_STAT_0_FSMS_OFFSET 0xA43 -+#define VR9_FDMA_STAT_0_FSMS_SHIFT 0 -+#define VR9_FDMA_STAT_0_FSMS_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Fetch DMA Global InterruptEnable Register' */ -+/* Bit: 'PCKD' */ -+/* Description: 'Packet Drop Interrupt Enable' */ -+#define VR9_FDMA_IER_PCKD_OFFSET 0xA44 -+#define VR9_FDMA_IER_PCKD_SHIFT 14 -+#define VR9_FDMA_IER_PCKD_SIZE 1 -+/* Bit: 'PCKR' */ -+/* Description: 'Packet Ready Interrupt Enable' */ -+#define VR9_FDMA_IER_PCKR_OFFSET 0xA44 -+#define VR9_FDMA_IER_PCKR_SHIFT 13 -+#define VR9_FDMA_IER_PCKR_SIZE 1 -+/* Bit: 'PCKT' */ -+/* Description: 'Packet Sent Interrupt Enable' */ -+#define VR9_FDMA_IER_PCKT_OFFSET 0xA44 -+#define VR9_FDMA_IER_PCKT_SHIFT 0 -+#define VR9_FDMA_IER_PCKT_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Fetch DMA Global InterruptStatus Register' */ -+/* Bit: 'PCKTD' */ -+/* Description: 'Packet Drop' */ -+#define VR9_FDMA_ISR_PCKTD_OFFSET 0xA45 -+#define VR9_FDMA_ISR_PCKTD_SHIFT 14 -+#define VR9_FDMA_ISR_PCKTD_SIZE 1 -+/* Bit: 'PCKR' */ -+/* Description: 'Packet is Ready for Transmission' */ -+#define VR9_FDMA_ISR_PCKR_OFFSET 0xA45 -+#define VR9_FDMA_ISR_PCKR_SHIFT 13 -+#define VR9_FDMA_ISR_PCKR_SIZE 1 -+/* Bit: 'PCKT' */ -+/* Description: 'Packet Sent Event' */ -+#define VR9_FDMA_ISR_PCKT_OFFSET 0xA45 -+#define VR9_FDMA_ISR_PCKT_SHIFT 0 -+#define VR9_FDMA_ISR_PCKT_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchFetch DMA Port Control Register' */ -+/* Bit: 'ST_TYPE' */ -+/* Description: 'Special Tag Ethertype Mode' */ -+#define VR9_FDMA_PCTRL_ST_TYPE_OFFSET 0xA80 -+#define VR9_FDMA_PCTRL_ST_TYPE_SHIFT 5 -+#define VR9_FDMA_PCTRL_ST_TYPE_SIZE 1 -+/* Bit: 'VLANMOD' */ -+/* Description: 'VLAN Modification Control' */ -+#define VR9_FDMA_PCTRL_VLANMOD_OFFSET 0xA80 -+#define VR9_FDMA_PCTRL_VLANMOD_SHIFT 3 -+#define VR9_FDMA_PCTRL_VLANMOD_SIZE 2 -+/* Bit: 'DSCPRM' */ -+/* Description: 'DSCP Re-marking Enable' */ -+#define VR9_FDMA_PCTRL_DSCPRM_OFFSET 0xA80 -+#define VR9_FDMA_PCTRL_DSCPRM_SHIFT 2 -+#define VR9_FDMA_PCTRL_DSCPRM_SIZE 1 -+/* Bit: 'STEN' */ -+/* Description: 'Special Tag Insertion Enable' */ -+#define VR9_FDMA_PCTRL_STEN_OFFSET 0xA80 -+#define VR9_FDMA_PCTRL_STEN_SHIFT 1 -+#define VR9_FDMA_PCTRL_STEN_SIZE 1 -+/* Bit: 'EN' */ -+/* Description: 'FDMA Port Enable' */ -+#define VR9_FDMA_PCTRL_EN_OFFSET 0xA80 -+#define VR9_FDMA_PCTRL_EN_SHIFT 0 -+#define VR9_FDMA_PCTRL_EN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchFetch DMA Port Priority Register' */ -+/* Bit: 'PRIO' */ -+/* Description: 'FDMA PRIO' */ -+#define VR9_FDMA_PRIO_PRIO_OFFSET 0xA81 -+#define VR9_FDMA_PRIO_PRIO_SHIFT 0 -+#define VR9_FDMA_PRIO_PRIO_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchFetch DMA Port Status Register 0' */ -+/* Bit: 'PKT_AVAIL' */ -+/* Description: 'Port Egress Packet Available' */ -+#define VR9_FDMA_PSTAT0_PKT_AVAIL_OFFSET 0xA82 -+#define VR9_FDMA_PSTAT0_PKT_AVAIL_SHIFT 15 -+#define VR9_FDMA_PSTAT0_PKT_AVAIL_SIZE 1 -+/* Bit: 'POK' */ -+/* Description: 'Port Status OK' */ -+#define VR9_FDMA_PSTAT0_POK_OFFSET 0xA82 -+#define VR9_FDMA_PSTAT0_POK_SHIFT 14 -+#define VR9_FDMA_PSTAT0_POK_SIZE 1 -+/* Bit: 'PSEG' */ -+/* Description: 'Port Egress Segment Count' */ -+#define VR9_FDMA_PSTAT0_PSEG_OFFSET 0xA82 -+#define VR9_FDMA_PSTAT0_PSEG_SHIFT 0 -+#define VR9_FDMA_PSTAT0_PSEG_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchFetch DMA Port Status Register 1' */ -+/* Bit: 'HDR_PTR' */ -+/* Description: 'Header Pointer' */ -+#define VR9_FDMA_PSTAT1_HDR_PTR_OFFSET 0xA83 -+#define VR9_FDMA_PSTAT1_HDR_PTR_SHIFT 0 -+#define VR9_FDMA_PSTAT1_HDR_PTR_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Egress TimeStamp Register 0' */ -+/* Bit: 'TSTL' */ -+/* Description: 'Time Stamp [15:0]' */ -+#define VR9_FDMA_TSTAMP0_TSTL_OFFSET 0xA84 -+#define VR9_FDMA_TSTAMP0_TSTL_SHIFT 0 -+#define VR9_FDMA_TSTAMP0_TSTL_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Egress TimeStamp Register 1' */ -+/* Bit: 'TSTH' */ -+/* Description: 'Time Stamp [31:16]' */ -+#define VR9_FDMA_TSTAMP1_TSTH_OFFSET 0xA85 -+#define VR9_FDMA_TSTAMP1_TSTH_SHIFT 0 -+#define VR9_FDMA_TSTAMP1_TSTH_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet Switch StoreDMA Control Register' */ -+/* Bit: 'RMON_ALIGN' */ -+/* Description: 'MUX to select what to count on align error rmon -+counter' */ -+#define VR9_SDMA_CTRL_RMON_ALIGN_OFFSET 0xB40 -+#define VR9_SDMA_CTRL_RMON_ALIGN_SHIFT 2 -+#define VR9_SDMA_CTRL_RMON_ALIGN_SIZE 2 -+/* Bit: 'ARBIT' */ -+/* Description: 'SIMPLE ARBITER FOR PARSER FILLING' */ -+#define VR9_SDMA_CTRL_ARBIT_OFFSET 0xB40 -+#define VR9_SDMA_CTRL_ARBIT_SHIFT 1 -+#define VR9_SDMA_CTRL_ARBIT_SIZE 1 -+/* Bit: 'TSTEN' */ -+/* Description: 'Time Stamp Enable' */ -+#define VR9_SDMA_CTRL_TSTEN_OFFSET 0xB40 -+#define VR9_SDMA_CTRL_TSTEN_SHIFT 0 -+#define VR9_SDMA_CTRL_TSTEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold1 Register' */ -+/* Bit: 'THR1' */ -+/* Description: 'Threshold 1' */ -+#define VR9_SDMA_FCTHR1_THR1_OFFSET 0xB41 -+#define VR9_SDMA_FCTHR1_THR1_SHIFT 0 -+#define VR9_SDMA_FCTHR1_THR1_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold2 Register' */ -+/* Bit: 'THR2' */ -+/* Description: 'Threshold 2' */ -+#define VR9_SDMA_FCTHR2_THR2_OFFSET 0xB42 -+#define VR9_SDMA_FCTHR2_THR2_SHIFT 0 -+#define VR9_SDMA_FCTHR2_THR2_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold3 Register' */ -+/* Bit: 'THR3' */ -+/* Description: 'Threshold 3' */ -+#define VR9_SDMA_FCTHR3_THR3_OFFSET 0xB43 -+#define VR9_SDMA_FCTHR3_THR3_SHIFT 0 -+#define VR9_SDMA_FCTHR3_THR3_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold4 Register' */ -+/* Bit: 'THR4' */ -+/* Description: 'Threshold 4' */ -+#define VR9_SDMA_FCTHR4_THR4_OFFSET 0xB44 -+#define VR9_SDMA_FCTHR4_THR4_SHIFT 0 -+#define VR9_SDMA_FCTHR4_THR4_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold5 Register' */ -+/* Bit: 'THR5' */ -+/* Description: 'Threshold 5' */ -+#define VR9_SDMA_FCTHR5_THR5_OFFSET 0xB45 -+#define VR9_SDMA_FCTHR5_THR5_SHIFT 0 -+#define VR9_SDMA_FCTHR5_THR5_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold6 Register' */ -+/* Bit: 'THR6' */ -+/* Description: 'Threshold 6' */ -+#define VR9_SDMA_FCTHR6_THR6_OFFSET 0xB46 -+#define VR9_SDMA_FCTHR6_THR6_SHIFT 0 -+#define VR9_SDMA_FCTHR6_THR6_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Flow Control Threshold7 Register' */ -+/* Bit: 'THR7' */ -+/* Description: 'Threshold 7' */ -+#define VR9_SDMA_FCTHR7_THR7_OFFSET 0xB47 -+#define VR9_SDMA_FCTHR7_THR7_SHIFT 0 -+#define VR9_SDMA_FCTHR7_THR7_SIZE 11 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Status Register0' */ -+/* Bit: 'BPS_FILL' */ -+/* Description: 'Back Pressure Status' */ -+#define VR9_SDMA_STAT_0_BPS_FILL_OFFSET 0xB48 -+#define VR9_SDMA_STAT_0_BPS_FILL_SHIFT 4 -+#define VR9_SDMA_STAT_0_BPS_FILL_SIZE 3 -+/* Bit: 'BPS_PNT' */ -+/* Description: 'Back Pressure Status' */ -+#define VR9_SDMA_STAT_0_BPS_PNT_OFFSET 0xB48 -+#define VR9_SDMA_STAT_0_BPS_PNT_SHIFT 2 -+#define VR9_SDMA_STAT_0_BPS_PNT_SIZE 2 -+/* Bit: 'DROP' */ -+/* Description: 'Back Pressure Status' */ -+#define VR9_SDMA_STAT_0_DROP_OFFSET 0xB48 -+#define VR9_SDMA_STAT_0_DROP_SHIFT 0 -+#define VR9_SDMA_STAT_0_DROP_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Status Register1' */ -+/* Bit: 'FILL' */ -+/* Description: 'Buffer Filling Level' */ -+#define VR9_SDMA_STAT_1_FILL_OFFSET 0xB49 -+#define VR9_SDMA_STAT_1_FILL_SHIFT 0 -+#define VR9_SDMA_STAT_1_FILL_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Status Register2' */ -+/* Bit: 'FSMS' */ -+/* Description: 'FSM states status' */ -+#define VR9_SDMA_STAT_2_FSMS_OFFSET 0xB4A -+#define VR9_SDMA_STAT_2_FSMS_SHIFT 0 -+#define VR9_SDMA_STAT_2_FSMS_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Interrupt Enable Register' */ -+/* Bit: 'BPEX' */ -+/* Description: 'Buffer Pointers Exceeded' */ -+#define VR9_SDMA_IER_BPEX_OFFSET 0xB4B -+#define VR9_SDMA_IER_BPEX_SHIFT 15 -+#define VR9_SDMA_IER_BPEX_SIZE 1 -+/* Bit: 'BFULL' */ -+/* Description: 'Buffer Full' */ -+#define VR9_SDMA_IER_BFULL_OFFSET 0xB4B -+#define VR9_SDMA_IER_BFULL_SHIFT 14 -+#define VR9_SDMA_IER_BFULL_SIZE 1 -+/* Bit: 'FERR' */ -+/* Description: 'Frame Error' */ -+#define VR9_SDMA_IER_FERR_OFFSET 0xB4B -+#define VR9_SDMA_IER_FERR_SHIFT 13 -+#define VR9_SDMA_IER_FERR_SIZE 1 -+/* Bit: 'FRX' */ -+/* Description: 'Frame Received Successfully' */ -+#define VR9_SDMA_IER_FRX_OFFSET 0xB4B -+#define VR9_SDMA_IER_FRX_SHIFT 0 -+#define VR9_SDMA_IER_FRX_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'SDMA Interrupt Status Register' */ -+/* Bit: 'BPEX' */ -+/* Description: 'Packet Descriptors Exceeded' */ -+#define VR9_SDMA_ISR_BPEX_OFFSET 0xB4C -+#define VR9_SDMA_ISR_BPEX_SHIFT 15 -+#define VR9_SDMA_ISR_BPEX_SIZE 1 -+/* Bit: 'BFULL' */ -+/* Description: 'Buffer Full' */ -+#define VR9_SDMA_ISR_BFULL_OFFSET 0xB4C -+#define VR9_SDMA_ISR_BFULL_SHIFT 14 -+#define VR9_SDMA_ISR_BFULL_SIZE 1 -+/* Bit: 'FERR' */ -+/* Description: 'Frame Error' */ -+#define VR9_SDMA_ISR_FERR_OFFSET 0xB4C -+#define VR9_SDMA_ISR_FERR_SHIFT 13 -+#define VR9_SDMA_ISR_FERR_SIZE 1 -+/* Bit: 'FRX' */ -+/* Description: 'Frame Received Successfully' */ -+#define VR9_SDMA_ISR_FRX_OFFSET 0xB4C -+#define VR9_SDMA_ISR_FRX_SHIFT 0 -+#define VR9_SDMA_ISR_FRX_SIZE 13 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchStore DMA Port Control Register' */ -+/* Bit: 'DTHR' */ -+/* Description: 'Drop Threshold Selection' */ -+#define VR9_SDMA_PCTRL_DTHR_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_DTHR_SHIFT 13 -+#define VR9_SDMA_PCTRL_DTHR_SIZE 2 -+/* Bit: 'PTHR' */ -+/* Description: 'Pause Threshold Selection' */ -+#define VR9_SDMA_PCTRL_PTHR_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_PTHR_SHIFT 11 -+#define VR9_SDMA_PCTRL_PTHR_SIZE 2 -+/* Bit: 'PHYEFWD' */ -+/* Description: 'Forward PHY Error Frames' */ -+#define VR9_SDMA_PCTRL_PHYEFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_PHYEFWD_SHIFT 10 -+#define VR9_SDMA_PCTRL_PHYEFWD_SIZE 1 -+/* Bit: 'ALGFWD' */ -+/* Description: 'Forward Alignment Error Frames' */ -+#define VR9_SDMA_PCTRL_ALGFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_ALGFWD_SHIFT 9 -+#define VR9_SDMA_PCTRL_ALGFWD_SIZE 1 -+/* Bit: 'LENFWD' */ -+/* Description: 'Forward Length Errored Frames' */ -+#define VR9_SDMA_PCTRL_LENFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_LENFWD_SHIFT 8 -+#define VR9_SDMA_PCTRL_LENFWD_SIZE 1 -+/* Bit: 'OSFWD' */ -+/* Description: 'Forward Oversized Frames' */ -+#define VR9_SDMA_PCTRL_OSFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_OSFWD_SHIFT 7 -+#define VR9_SDMA_PCTRL_OSFWD_SIZE 1 -+/* Bit: 'USFWD' */ -+/* Description: 'Forward Undersized Frames' */ -+#define VR9_SDMA_PCTRL_USFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_USFWD_SHIFT 6 -+#define VR9_SDMA_PCTRL_USFWD_SIZE 1 -+/* Bit: 'FCSIGN' */ -+/* Description: 'Ignore FCS Errors' */ -+#define VR9_SDMA_PCTRL_FCSIGN_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_FCSIGN_SHIFT 5 -+#define VR9_SDMA_PCTRL_FCSIGN_SIZE 1 -+/* Bit: 'FCSFWD' */ -+/* Description: 'Forward FCS Errored Frames' */ -+#define VR9_SDMA_PCTRL_FCSFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_FCSFWD_SHIFT 4 -+#define VR9_SDMA_PCTRL_FCSFWD_SIZE 1 -+/* Bit: 'PAUFWD' */ -+/* Description: 'Pause Frame Forwarding' */ -+#define VR9_SDMA_PCTRL_PAUFWD_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_PAUFWD_SHIFT 3 -+#define VR9_SDMA_PCTRL_PAUFWD_SIZE 1 -+/* Bit: 'MFCEN' */ -+/* Description: 'Metering Flow Control Enable' */ -+#define VR9_SDMA_PCTRL_MFCEN_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_MFCEN_SHIFT 2 -+#define VR9_SDMA_PCTRL_MFCEN_SIZE 1 -+/* Bit: 'FCEN' */ -+/* Description: 'Flow Control Enable' */ -+#define VR9_SDMA_PCTRL_FCEN_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_FCEN_SHIFT 1 -+#define VR9_SDMA_PCTRL_FCEN_SIZE 1 -+/* Bit: 'PEN' */ -+/* Description: 'Port Enable' */ -+#define VR9_SDMA_PCTRL_PEN_OFFSET 0xBC0 -+#define VR9_SDMA_PCTRL_PEN_SHIFT 0 -+#define VR9_SDMA_PCTRL_PEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchStore DMA Port Priority Register' */ -+/* Bit: 'MIN_IFG' */ -+/* Description: 'Minimum IFG,SFD and preamble' */ -+#define VR9_SDMA_PRIO_MIN_IFG_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_MIN_IFG_SHIFT 7 -+#define VR9_SDMA_PRIO_MIN_IFG_SIZE 5 -+/* Bit: 'PHYEIGN' */ -+/* Description: 'Ignore PHY Error Frames' */ -+#define VR9_SDMA_PRIO_PHYEIGN_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_PHYEIGN_SHIFT 6 -+#define VR9_SDMA_PRIO_PHYEIGN_SIZE 1 -+/* Bit: 'ALGIGN' */ -+/* Description: 'Ignore Alignment Error Frames' */ -+#define VR9_SDMA_PRIO_ALGIGN_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_ALGIGN_SHIFT 5 -+#define VR9_SDMA_PRIO_ALGIGN_SIZE 1 -+/* Bit: 'LENIGN' */ -+/* Description: 'Ignore Length Errored Frames' */ -+#define VR9_SDMA_PRIO_LENIGN_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_LENIGN_SHIFT 4 -+#define VR9_SDMA_PRIO_LENIGN_SIZE 1 -+/* Bit: 'OSIGN' */ -+/* Description: 'Ignore Oversized Frames' */ -+#define VR9_SDMA_PRIO_OSIGN_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_OSIGN_SHIFT 3 -+#define VR9_SDMA_PRIO_OSIGN_SIZE 1 -+/* Bit: 'USIGN' */ -+/* Description: 'Ignore Undersized Frames' */ -+#define VR9_SDMA_PRIO_USIGN_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_USIGN_SHIFT 2 -+#define VR9_SDMA_PRIO_USIGN_SIZE 1 -+/* Bit: 'PRIO' */ -+/* Description: 'SDMA PRIO' */ -+#define VR9_SDMA_PRIO_PRIO_OFFSET 0xBC1 -+#define VR9_SDMA_PRIO_PRIO_SHIFT 0 -+#define VR9_SDMA_PRIO_PRIO_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchStore DMA Port Status Register 0' */ -+/* Bit: 'HDR_PTR' */ -+/* Description: 'Port Ingress Queue Header Pointer' */ -+#define VR9_SDMA_PSTAT0_HDR_PTR_OFFSET 0xBC2 -+#define VR9_SDMA_PSTAT0_HDR_PTR_SHIFT 0 -+#define VR9_SDMA_PSTAT0_HDR_PTR_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ethernet SwitchStore DMA Port Status Register 1' */ -+/* Bit: 'PPKT' */ -+/* Description: 'Port Ingress Packet Count' */ -+#define VR9_SDMA_PSTAT1_PPKT_OFFSET 0xBC3 -+#define VR9_SDMA_PSTAT1_PPKT_SHIFT 0 -+#define VR9_SDMA_PSTAT1_PPKT_SIZE 10 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ingress TimeStamp Register 0' */ -+/* Bit: 'TSTL' */ -+/* Description: 'Time Stamp [15:0]' */ -+#define VR9_SDMA_TSTAMP0_TSTL_OFFSET 0xBC4 -+#define VR9_SDMA_TSTAMP0_TSTL_SHIFT 0 -+#define VR9_SDMA_TSTAMP0_TSTL_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Ingress TimeStamp Register 1' */ -+/* Bit: 'TSTH' */ -+/* Description: 'Time Stamp [31:16]' */ -+#define VR9_SDMA_TSTAMP1_TSTH_OFFSET 0xBC5 -+#define VR9_SDMA_TSTAMP1_TSTH_SHIFT 0 -+#define VR9_SDMA_TSTAMP1_TSTH_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+#endif /* #ifndef _VR9_SWITCH_H */ -diff --git a/include/switch_api/VR9_top.h b/include/switch_api/VR9_top.h -new file mode 100644 -index 0000000..626a4bf ---- /dev/null -+++ b/include/switch_api/VR9_top.h -@@ -0,0 +1,798 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2011 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+#ifndef _VR9_TOP_H -+#define _VR9_TOP_H -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Global Control Register0' */ -+/* Bit: 'SE' */ -+/* Description: 'Global Switch Macro Enable' */ -+#define VR9_GLOB_CTRL_SE_OFFSET 0x000 -+#define VR9_GLOB_CTRL_SE_SHIFT 15 -+#define VR9_GLOB_CTRL_SE_SIZE 1 -+/* Bit: 'HWRES' */ -+/* Description: 'Global Hardware Reset' */ -+#define VR9_GLOB_CTRL_HWRES_OFFSET 0x000 -+#define VR9_GLOB_CTRL_HWRES_SHIFT 1 -+#define VR9_GLOB_CTRL_HWRES_SIZE 1 -+/* Bit: 'SWRES' */ -+/* Description: 'Global Software Reset' */ -+#define VR9_GLOB_CTRL_SWRES_OFFSET 0x000 -+#define VR9_GLOB_CTRL_SWRES_SHIFT 0 -+#define VR9_GLOB_CTRL_SWRES_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDIO Control Register' */ -+/* Bit: 'MBUSY' */ -+/* Description: 'MDIO Busy' */ -+#define VR9_MDIO_CTRL_MBUSY_OFFSET 0x008 -+#define VR9_MDIO_CTRL_MBUSY_SHIFT 12 -+#define VR9_MDIO_CTRL_MBUSY_SIZE 1 -+/* Bit: 'OP' */ -+/* Description: 'Operation Code' */ -+#define VR9_MDIO_CTRL_OP_OFFSET 0x008 -+#define VR9_MDIO_CTRL_OP_SHIFT 10 -+#define VR9_MDIO_CTRL_OP_SIZE 2 -+/* Bit: 'PHYAD' */ -+/* Description: 'PHY Address' */ -+#define VR9_MDIO_CTRL_PHYAD_OFFSET 0x008 -+#define VR9_MDIO_CTRL_PHYAD_SHIFT 5 -+#define VR9_MDIO_CTRL_PHYAD_SIZE 5 -+/* Bit: 'REGAD' */ -+/* Description: 'Register Address' */ -+#define VR9_MDIO_CTRL_REGAD_OFFSET 0x008 -+#define VR9_MDIO_CTRL_REGAD_SHIFT 0 -+#define VR9_MDIO_CTRL_REGAD_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDIO Read Data Register' */ -+/* Bit: 'RDATA' */ -+/* Description: 'Read Data' */ -+#define VR9_MDIO_READ_RDATA_OFFSET 0x009 -+#define VR9_MDIO_READ_RDATA_SHIFT 0 -+#define VR9_MDIO_READ_RDATA_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDIO Write Data Register' */ -+/* Bit: 'WDATA' */ -+/* Description: 'Write Data' */ -+#define VR9_MDIO_WRITE_WDATA_OFFSET 0x00A -+#define VR9_MDIO_WRITE_WDATA_SHIFT 0 -+#define VR9_MDIO_WRITE_WDATA_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDC Clock ConfigurationRegister 0' */ -+/* Bit: 'PEN_5' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_5_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_5_SHIFT 5 -+#define VR9_MDC_CFG_0_PEN_5_SIZE 1 -+/* Bit: 'PEN_4' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_4_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_4_SHIFT 4 -+#define VR9_MDC_CFG_0_PEN_4_SIZE 1 -+/* Bit: 'PEN_3' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_3_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_3_SHIFT 3 -+#define VR9_MDC_CFG_0_PEN_3_SIZE 1 -+/* Bit: 'PEN_2' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_2_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_2_SHIFT 2 -+#define VR9_MDC_CFG_0_PEN_2_SIZE 1 -+/* Bit: 'PEN_1' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_1_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_1_SHIFT 1 -+#define VR9_MDC_CFG_0_PEN_1_SIZE 1 -+/* Bit: 'PEN_0' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_0_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_0_SHIFT 0 -+#define VR9_MDC_CFG_0_PEN_0_SIZE 1 -+/* Bit: 'PEN_0~PEN_5' */ -+/* Description: 'Polling State Machine Enable' */ -+#define VR9_MDC_CFG_0_PEN_ALL_OFFSET 0x00B -+#define VR9_MDC_CFG_0_PEN_ALL_SHIFT 0 -+#define VR9_MDC_CFG_0_PEN_ALL_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'MDC Clock ConfigurationRegister 1' */ -+/* Bit: 'RES' */ -+/* Description: 'MDIO Hardware Reset' */ -+#define VR9_MDC_CFG_1_RES_OFFSET 0x00C -+#define VR9_MDC_CFG_1_RES_SHIFT 15 -+#define VR9_MDC_CFG_1_RES_SIZE 1 -+/* Bit: 'MCEN' */ -+/* Description: 'Management Clock Enable' */ -+#define VR9_MDC_CFG_1_MCEN_OFFSET 0x00C -+#define VR9_MDC_CFG_1_MCEN_SHIFT 8 -+#define VR9_MDC_CFG_1_MCEN_SIZE 1 -+/* Bit: 'FREQ' */ -+/* Description: 'MDIO Interface Clock Rate' */ -+#define VR9_MDC_CFG_1_FREQ_OFFSET 0x00C -+#define VR9_MDC_CFG_1_FREQ_SHIFT 0 -+#define VR9_MDC_CFG_1_FREQ_SIZE 8 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 5' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_5_LNKST_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_5_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_5_SPEED_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_5_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_5_FDUP_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_5_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_5_FCONTX_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_5_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_5_FCONRX_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_5_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_5_ADDR_OFFSET 0x010 -+#define VR9_PHY_ADDR_5_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_5_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 4' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_4_LNKST_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_4_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_4_SPEED_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_4_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_4_FDUP_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_4_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_4_FCONTX_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_4_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_4_FCONRX_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_4_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_4_ADDR_OFFSET 0x011 -+#define VR9_PHY_ADDR_4_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_4_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 3' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_3_LNKST_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_3_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_3_SPEED_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_3_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_3_FDUP_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_3_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_3_FCONTX_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_3_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_3_FCONRX_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_3_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_3_ADDR_OFFSET 0x012 -+#define VR9_PHY_ADDR_3_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_3_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 2' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_2_LNKST_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_2_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_2_SPEED_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_2_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_2_FDUP_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_2_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_2_FCONTX_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_2_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_2_FCONRX_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_2_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_2_ADDR_OFFSET 0x013 -+#define VR9_PHY_ADDR_2_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_2_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 1' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_1_LNKST_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_1_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_1_SPEED_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_1_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_1_FDUP_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_1_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_1_FCONTX_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_1_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_1_FCONRX_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_1_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_1_ADDR_OFFSET 0x014 -+#define VR9_PHY_ADDR_1_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_1_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY Address RegisterPORT 0' */ -+/* Bit: 'LNKST' */ -+/* Description: 'Link Status Control' */ -+#define VR9_PHY_ADDR_0_LNKST_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_LNKST_SHIFT 13 -+#define VR9_PHY_ADDR_0_LNKST_SIZE 2 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PHY_ADDR_0_SPEED_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_SPEED_SHIFT 11 -+#define VR9_PHY_ADDR_0_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Control' */ -+#define VR9_PHY_ADDR_0_FDUP_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_FDUP_SHIFT 9 -+#define VR9_PHY_ADDR_0_FDUP_SIZE 2 -+/* Bit: 'FCONTX' */ -+/* Description: 'Flow Control Mode TX' */ -+#define VR9_PHY_ADDR_0_FCONTX_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_FCONTX_SHIFT 7 -+#define VR9_PHY_ADDR_0_FCONTX_SIZE 2 -+/* Bit: 'FCONRX' */ -+/* Description: 'Flow Control Mode RX' */ -+#define VR9_PHY_ADDR_0_FCONRX_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_FCONRX_SHIFT 5 -+#define VR9_PHY_ADDR_0_FCONRX_SIZE 2 -+/* Bit: 'ADDR' */ -+/* Description: 'PHY Address' */ -+#define VR9_PHY_ADDR_0_ADDR_OFFSET 0x015 -+#define VR9_PHY_ADDR_0_ADDR_SHIFT 0 -+#define VR9_PHY_ADDR_0_ADDR_SIZE 5 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PHY MDIO PollingStatus per PORT' */ -+/* Bit: 'CLK_STOP_CAPABLE' */ -+/* Description: 'PHY supports MAC turning of TX clk' */ -+#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_SHIFT 8 -+#define VR9_MDIO_STAT_0_CLK_STOP_CAPABLE_SIZE 1 -+/* Bit: 'EEE_CAPABLE' */ -+/* Description: 'PHY and link partner support EEE for current speed' */ -+#define VR9_MDIO_STAT_0_EEE_CAPABLE_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_EEE_CAPABLE_SHIFT 7 -+#define VR9_MDIO_STAT_0_EEE_CAPABLE_SIZE 1 -+/* Bit: 'PACT' */ -+/* Description: 'PHY Active Status' */ -+#define VR9_MDIO_STAT_0_PACT_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_PACT_SHIFT 6 -+#define VR9_MDIO_STAT_0_PACT_SIZE 1 -+/* Bit: 'LSTAT' */ -+/* Description: 'Link Status' */ -+#define VR9_MDIO_STAT_0_LSTAT_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_LSTAT_SHIFT 5 -+#define VR9_MDIO_STAT_0_LSTAT_SIZE 1 -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_MDIO_STAT_0_SPEED_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_SPEED_SHIFT 3 -+#define VR9_MDIO_STAT_0_SPEED_SIZE 2 -+/* Bit: 'FDUP' */ -+/* Description: 'Full Duplex Status' */ -+#define VR9_MDIO_STAT_0_FDUP_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_FDUP_SHIFT 2 -+#define VR9_MDIO_STAT_0_FDUP_SIZE 1 -+/* Bit: 'RXPAUEN' */ -+/* Description: 'Receive Pause Enable Status' */ -+#define VR9_MDIO_STAT_0_RXPAUEN_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_RXPAUEN_SHIFT 1 -+#define VR9_MDIO_STAT_0_RXPAUEN_SIZE 1 -+/* Bit: 'TXPAUEN' */ -+/* Description: 'Transmit Pause Enable Status' */ -+#define VR9_MDIO_STAT_0_TXPAUEN_OFFSET 0x016 -+#define VR9_MDIO_STAT_0_TXPAUEN_SHIFT 0 -+#define VR9_MDIO_STAT_0_TXPAUEN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'EEE auto negotiationoverides' */ -+/* Bit: 'CLK_STOP_CAPABLE' */ -+/* Description: 'clk stop capable' */ -+#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_OFFSET 0x01C -+#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_SHIFT 2 -+#define VR9_ANEG_EEE_0_CLK_STOP_CAPABLE_SIZE 2 -+/* Bit: 'EEE_CAPABLE' */ -+/* Description: 'EEE capable' */ -+#define VR9_ANEG_EEE_0_EEE_CAPABLE_OFFSET 0x01C -+#define VR9_ANEG_EEE_0_EEE_CAPABLE_SHIFT 0 -+#define VR9_ANEG_EEE_0_EEE_CAPABLE_SIZE 2 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'xMII Port 0 ConfigurationRegister' */ -+/* Bit: 'RES' */ -+/* Description: 'Hardware Reset' */ -+#define VR9_MII_CFG_0_RES_OFFSET 0x036 -+#define VR9_MII_CFG_0_RES_SHIFT 15 -+#define VR9_MII_CFG_0_RES_SIZE 1 -+/* Bit: 'EN' */ -+/* Description: 'xMII Interface Enable' */ -+#define VR9_MII_CFG_0_EN_OFFSET 0x036 -+#define VR9_MII_CFG_0_EN_SHIFT 14 -+#define VR9_MII_CFG_0_EN_SIZE 1 -+/* Bit: 'ISOL' */ -+/* Description: 'ISOLATE xMII Interface' */ -+#define VR9_MII_CFG_0_ISOL_OFFSET 0x036 -+#define VR9_MII_CFG_0_ISOL_SHIFT 13 -+#define VR9_MII_CFG_0_ISOL_SIZE 1 -+/* Bit: 'LDCLKDIS' */ -+/* Description: 'Link Down Clock Disable' */ -+#define VR9_MII_CFG_0_LDCLKDIS_OFFSET 0x036 -+#define VR9_MII_CFG_0_LDCLKDIS_SHIFT 12 -+#define VR9_MII_CFG_0_LDCLKDIS_SIZE 1 -+/* Bit: 'CRS' */ -+/* Description: 'CRS Sensitivity Configuration' */ -+#define VR9_MII_CFG_0_CRS_OFFSET 0x036 -+#define VR9_MII_CFG_0_CRS_SHIFT 9 -+#define VR9_MII_CFG_0_CRS_SIZE 2 -+/* Bit: 'RGMII_IBS' */ -+/* Description: 'RGMII In Band Status' */ -+#define VR9_MII_CFG_0_RGMII_IBS_OFFSET 0x036 -+#define VR9_MII_CFG_0_RGMII_IBS_SHIFT 8 -+#define VR9_MII_CFG_0_RGMII_IBS_SIZE 1 -+/* Bit: 'RMII' */ -+/* Description: 'RMII Reference Clock Direction of the Port' */ -+#define VR9_MII_CFG_0_RMII_OFFSET 0x036 -+#define VR9_MII_CFG_0_RMII_SHIFT 7 -+#define VR9_MII_CFG_0_RMII_SIZE 1 -+/* Bit: 'MIIRATE' */ -+/* Description: 'xMII Port Interface Clock Rate' */ -+#define VR9_MII_CFG_0_MIIRATE_OFFSET 0x036 -+#define VR9_MII_CFG_0_MIIRATE_SHIFT 4 -+#define VR9_MII_CFG_0_MIIRATE_SIZE 3 -+/* Bit: 'MIIMODE' */ -+/* Description: 'xMII Interface Mode' */ -+#define VR9_MII_CFG_0_MIIMODE_OFFSET 0x036 -+#define VR9_MII_CFG_0_MIIMODE_SHIFT 0 -+#define VR9_MII_CFG_0_MIIMODE_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Configuration of ClockDelay for Port 0' */ -+/* Bit: 'RXLOCK' */ -+/* Description: 'Lock Status MDL of Receive PCDU' */ -+#define VR9_PCDU_0_RXLOCK_OFFSET 0x037 -+#define VR9_PCDU_0_RXLOCK_SHIFT 15 -+#define VR9_PCDU_0_RXLOCK_SIZE 1 -+/* Bit: 'TXLOCK' */ -+/* Description: 'Lock Status of MDL of Transmit PCDU' */ -+#define VR9_PCDU_0_TXLOCK_OFFSET 0x037 -+#define VR9_PCDU_0_TXLOCK_SHIFT 14 -+#define VR9_PCDU_0_TXLOCK_SIZE 1 -+/* Bit: 'RXDLY' */ -+/* Description: 'Configure Receive Clock Delay' */ -+#define VR9_PCDU_0_RXDLY_OFFSET 0x037 -+#define VR9_PCDU_0_RXDLY_SHIFT 7 -+#define VR9_PCDU_0_RXDLY_SIZE 3 -+/* Bit: 'TXDLY' */ -+/* Description: 'Configure Transmit PCDU' */ -+#define VR9_PCDU_0_TXDLY_OFFSET 0x037 -+#define VR9_PCDU_0_TXDLY_SHIFT 0 -+#define VR9_PCDU_0_TXDLY_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'xMII Port 1 ConfigurationRegister' */ -+/* Bit: 'RES' */ -+/* Description: 'Hardware Reset' */ -+#define VR9_MII_CFG_1_RES_OFFSET 0x038 -+#define VR9_MII_CFG_1_RES_SHIFT 15 -+#define VR9_MII_CFG_1_RES_SIZE 1 -+/* Bit: 'EN' */ -+/* Description: 'xMII Interface Enable' */ -+#define VR9_MII_CFG_1_EN_OFFSET 0x038 -+#define VR9_MII_CFG_1_EN_SHIFT 14 -+#define VR9_MII_CFG_1_EN_SIZE 1 -+/* Bit: 'ISOL' */ -+/* Description: 'ISOLATE xMII Interface' */ -+#define VR9_MII_CFG_1_ISOL_OFFSET 0x038 -+#define VR9_MII_CFG_1_ISOL_SHIFT 13 -+#define VR9_MII_CFG_1_ISOL_SIZE 1 -+/* Bit: 'LDCLKDIS' */ -+/* Description: 'Link Down Clock Disable' */ -+#define VR9_MII_CFG_1_LDCLKDIS_OFFSET 0x038 -+#define VR9_MII_CFG_1_LDCLKDIS_SHIFT 12 -+#define VR9_MII_CFG_1_LDCLKDIS_SIZE 1 -+/* Bit: 'CRS' */ -+/* Description: 'CRS Sensitivity Configuration' */ -+#define VR9_MII_CFG_1_CRS_OFFSET 0x038 -+#define VR9_MII_CFG_1_CRS_SHIFT 9 -+#define VR9_MII_CFG_1_CRS_SIZE 2 -+/* Bit: 'RGMII_IBS' */ -+/* Description: 'RGMII In Band Status' */ -+#define VR9_MII_CFG_1_RGMII_IBS_OFFSET 0x038 -+#define VR9_MII_CFG_1_RGMII_IBS_SHIFT 8 -+#define VR9_MII_CFG_1_RGMII_IBS_SIZE 1 -+/* Bit: 'RMII' */ -+/* Description: 'RMII Reference Clock Direction of the Port' */ -+#define VR9_MII_CFG_1_RMII_OFFSET 0x038 -+#define VR9_MII_CFG_1_RMII_SHIFT 7 -+#define VR9_MII_CFG_1_RMII_SIZE 1 -+/* Bit: 'MIIRATE' */ -+/* Description: 'xMII Port Interface Clock Rate' */ -+#define VR9_MII_CFG_1_MIIRATE_OFFSET 0x038 -+#define VR9_MII_CFG_1_MIIRATE_SHIFT 4 -+#define VR9_MII_CFG_1_MIIRATE_SIZE 3 -+/* Bit: 'MIIMODE' */ -+/* Description: 'xMII Interface Mode' */ -+#define VR9_MII_CFG_1_MIIMODE_OFFSET 0x038 -+#define VR9_MII_CFG_1_MIIMODE_SHIFT 0 -+#define VR9_MII_CFG_1_MIIMODE_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Configuration of ClockDelay for Port 1' */ -+/* Bit: 'RXLOCK' */ -+/* Description: 'Lock Status MDL of Receive PCDU' */ -+#define VR9_PCDU_1_RXLOCK_OFFSET 0x039 -+#define VR9_PCDU_1_RXLOCK_SHIFT 15 -+#define VR9_PCDU_1_RXLOCK_SIZE 1 -+/* Bit: 'TXLOCK' */ -+/* Description: 'Lock Status of MDL of Transmit PCDU' */ -+#define VR9_PCDU_1_TXLOCK_OFFSET 0x039 -+#define VR9_PCDU_1_TXLOCK_SHIFT 14 -+#define VR9_PCDU_1_TXLOCK_SIZE 1 -+/* Bit: 'RXDLY' */ -+/* Description: 'Configure Receive Clock Delay' */ -+#define VR9_PCDU_1_RXDLY_OFFSET 0x039 -+#define VR9_PCDU_1_RXDLY_SHIFT 7 -+#define VR9_PCDU_1_RXDLY_SIZE 3 -+/* Bit: 'TXDLY' */ -+/* Description: 'Configure Transmit PCDU' */ -+#define VR9_PCDU_1_TXDLY_OFFSET 0x039 -+#define VR9_PCDU_1_TXDLY_SHIFT 0 -+#define VR9_PCDU_1_TXDLY_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'xMII Port 5 ConfigurationRegister' */ -+/* Bit: 'RES' */ -+/* Description: 'Hardware Reset' */ -+#define VR9_MII_CFG_5_RES_OFFSET 0x040 -+#define VR9_MII_CFG_5_RES_SHIFT 15 -+#define VR9_MII_CFG_5_RES_SIZE 1 -+/* Bit: 'EN' */ -+/* Description: 'xMII Interface Enable' */ -+#define VR9_MII_CFG_5_EN_OFFSET 0x040 -+#define VR9_MII_CFG_5_EN_SHIFT 14 -+#define VR9_MII_CFG_5_EN_SIZE 1 -+/* Bit: 'ISOL' */ -+/* Description: 'ISOLATE xMII Interface' */ -+#define VR9_MII_CFG_5_ISOL_OFFSET 0x040 -+#define VR9_MII_CFG_5_ISOL_SHIFT 13 -+#define VR9_MII_CFG_5_ISOL_SIZE 1 -+/* Bit: 'LDCLKDIS' */ -+/* Description: 'Link Down Clock Disable' */ -+#define VR9_MII_CFG_5_LDCLKDIS_OFFSET 0x040 -+#define VR9_MII_CFG_5_LDCLKDIS_SHIFT 12 -+#define VR9_MII_CFG_5_LDCLKDIS_SIZE 1 -+/* Bit: 'CRS' */ -+/* Description: 'CRS Sensitivity Configuration' */ -+#define VR9_MII_CFG_5_CRS_OFFSET 0x040 -+#define VR9_MII_CFG_5_CRS_SHIFT 9 -+#define VR9_MII_CFG_5_CRS_SIZE 2 -+/* Bit: 'RGMII_IBS' */ -+/* Description: 'RGMII In Band Status' */ -+#define VR9_MII_CFG_5_RGMII_IBS_OFFSET 0x040 -+#define VR9_MII_CFG_5_RGMII_IBS_SHIFT 8 -+#define VR9_MII_CFG_5_RGMII_IBS_SIZE 1 -+/* Bit: 'MIIRATE' */ -+/* Description: 'xMII Port Interface Clock Rate' */ -+#define VR9_MII_CFG_5_MIIRATE_OFFSET 0x040 -+#define VR9_MII_CFG_5_MIIRATE_SHIFT 4 -+#define VR9_MII_CFG_5_MIIRATE_SIZE 3 -+/* Bit: 'MIIMODE' */ -+/* Description: 'xMII Interface Mode' */ -+#define VR9_MII_CFG_5_MIIMODE_OFFSET 0x040 -+#define VR9_MII_CFG_5_MIIMODE_SHIFT 0 -+#define VR9_MII_CFG_5_MIIMODE_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Configuration of ClockDelay for External Port 5' */ -+/* Bit: 'RXLOCK' */ -+/* Description: 'Lock Status MDL of Receive PCDU' */ -+#define VR9_PCDU_5_RXLOCK_OFFSET 0x041 -+#define VR9_PCDU_5_RXLOCK_SHIFT 15 -+#define VR9_PCDU_5_RXLOCK_SIZE 1 -+/* Bit: 'TXLOCK' */ -+/* Description: 'Lock Status of MDL of Transmit PCDU' */ -+#define VR9_PCDU_5_TXLOCK_OFFSET 0x041 -+#define VR9_PCDU_5_TXLOCK_SHIFT 14 -+#define VR9_PCDU_5_TXLOCK_SIZE 1 -+/* Bit: 'RXDLY' */ -+/* Description: 'Configure Receive Clock Delay' */ -+#define VR9_PCDU_5_RXDLY_OFFSET 0x041 -+#define VR9_PCDU_5_RXDLY_SHIFT 7 -+#define VR9_PCDU_5_RXDLY_SIZE 3 -+/* Bit: 'TXDLY' */ -+/* Description: 'Configure Transmit PCDU' */ -+#define VR9_PCDU_5_TXDLY_OFFSET 0x041 -+#define VR9_PCDU_5_TXDLY_SHIFT 0 -+#define VR9_PCDU_5_TXDLY_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Receive Buffer ControlRegister for Port 0' */ -+/* Bit: 'RBUF_UFL' */ -+/* Description: 'Receive Buffer Underflow Indicator' */ -+#define VR9_RXB_CTL_0_RBUF_UFL_OFFSET 0x056 -+#define VR9_RXB_CTL_0_RBUF_UFL_SHIFT 15 -+#define VR9_RXB_CTL_0_RBUF_UFL_SIZE 1 -+/* Bit: 'RBUF_OFL' */ -+/* Description: 'Receive Buffer Overflow Indicator' */ -+#define VR9_RXB_CTL_0_RBUF_OFL_OFFSET 0x056 -+#define VR9_RXB_CTL_0_RBUF_OFL_SHIFT 14 -+#define VR9_RXB_CTL_0_RBUF_OFL_SIZE 1 -+/* Bit: 'RBUF_DLY_WP' */ -+/* Description: 'Delay' */ -+#define VR9_RXB_CTL_0_RBUF_DLY_WP_OFFSET 0x056 -+#define VR9_RXB_CTL_0_RBUF_DLY_WP_SHIFT 0 -+#define VR9_RXB_CTL_0_RBUF_DLY_WP_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Receive Buffer ControlRegister External Port 1' */ -+/* Bit: 'RBUF_UFL' */ -+/* Description: 'Receive Buffer Underflow Indicator' */ -+#define VR9_RXB_CTL_1_RBUF_UFL_OFFSET 0x057 -+#define VR9_RXB_CTL_1_RBUF_UFL_SHIFT 15 -+#define VR9_RXB_CTL_1_RBUF_UFL_SIZE 1 -+/* Bit: 'RBUF_OFL' */ -+/* Description: 'Receive Buffer Overflow Indicator' */ -+#define VR9_RXB_CTL_1_RBUF_OFL_OFFSET 0x057 -+#define VR9_RXB_CTL_1_RBUF_OFL_SHIFT 14 -+#define VR9_RXB_CTL_1_RBUF_OFL_SIZE 1 -+/* Bit: 'RBUF_DLY_WP' */ -+/* Description: 'Delay' */ -+#define VR9_RXB_CTL_1_RBUF_DLY_WP_OFFSET 0x057 -+#define VR9_RXB_CTL_1_RBUF_DLY_WP_SHIFT 0 -+#define VR9_RXB_CTL_1_RBUF_DLY_WP_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Receive Buffer ControlRegister External Port 5' */ -+/* Bit: 'RBUF_UFL' */ -+/* Description: 'Receive Buffer Underflow Indicator' */ -+#define VR9_RXB_CTL_5_RBUF_UFL_OFFSET 0x05B -+#define VR9_RXB_CTL_5_RBUF_UFL_SHIFT 15 -+#define VR9_RXB_CTL_5_RBUF_UFL_SIZE 1 -+/* Bit: 'RBUF_OFL' */ -+/* Description: 'Receive Buffer Overflow Indicator' */ -+#define VR9_RXB_CTL_5_RBUF_OFL_OFFSET 0x05B -+#define VR9_RXB_CTL_5_RBUF_OFL_SHIFT 14 -+#define VR9_RXB_CTL_5_RBUF_OFL_SIZE 1 -+/* Bit: 'RBUF_DLY_WP' */ -+/* Description: 'Delay' */ -+#define VR9_RXB_CTL_5_RBUF_DLY_WP_OFFSET 0x05B -+#define VR9_RXB_CTL_5_RBUF_DLY_WP_SHIFT 0 -+#define VR9_RXB_CTL_5_RBUF_DLY_WP_SIZE 3 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'Debug Control Register' */ -+/* Bit: 'DBG_EN' */ -+/* Description: 'Debug enable' */ -+#define VR9_DBG_CTL_DBG_EN_OFFSET 0x081 -+#define VR9_DBG_CTL_DBG_EN_SHIFT 14 -+#define VR9_DBG_CTL_DBG_EN_SIZE 1 -+/* Bit: 'DBG_SEL' */ -+/* Description: 'Debug select' */ -+#define VR9_DBG_CTL_DBG_SEL_OFFSET 0x081 -+#define VR9_DBG_CTL_DBG_SEL_SHIFT 0 -+#define VR9_DBG_CTL_DBG_SEL_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Header ControlRegister' */ -+/* Bit: 'FC' */ -+/* Description: 'Enable Flow Control' */ -+#define VR9_PMAC_HD_CTL_FC_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_FC_SHIFT 10 -+#define VR9_PMAC_HD_CTL_FC_SIZE 1 -+/* Bit: 'CCRC' */ -+/* Description: 'Check CRC' */ -+#define VR9_PMAC_HD_CTL_CCRC_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_CCRC_SHIFT 9 -+#define VR9_PMAC_HD_CTL_CCRC_SIZE 1 -+/* Bit: 'RST' */ -+/* Description: 'Remove Special Tag' */ -+#define VR9_PMAC_HD_CTL_RST_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_RST_SHIFT 8 -+#define VR9_PMAC_HD_CTL_RST_SIZE 1 -+/* Bit: 'AST' */ -+/* Description: 'Add Special Tag' */ -+#define VR9_PMAC_HD_CTL_AST_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_AST_SHIFT 7 -+#define VR9_PMAC_HD_CTL_AST_SIZE 1 -+/* Bit: 'RXSH' */ -+/* Description: 'Status Header' */ -+#define VR9_PMAC_HD_CTL_RXSH_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_RXSH_SHIFT 6 -+#define VR9_PMAC_HD_CTL_RXSH_SIZE 1 -+/* Bit: 'RL2' */ -+/* Description: 'Remove Layer-2 Header' */ -+#define VR9_PMAC_HD_CTL_RL2_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_RL2_SHIFT 5 -+#define VR9_PMAC_HD_CTL_RL2_SIZE 1 -+/* Bit: 'RC' */ -+/* Description: 'Remove CRC' */ -+#define VR9_PMAC_HD_CTL_RC_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_RC_SHIFT 4 -+#define VR9_PMAC_HD_CTL_RC_SIZE 1 -+/* Bit: 'AS' */ -+/* Description: 'Add Status Header' */ -+#define VR9_PMAC_HD_CTL_AS_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_AS_SHIFT 3 -+#define VR9_PMAC_HD_CTL_AS_SIZE 1 -+/* Bit: 'AC' */ -+/* Description: 'Add CRC' */ -+#define VR9_PMAC_HD_CTL_AC_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_AC_SHIFT 2 -+#define VR9_PMAC_HD_CTL_AC_SIZE 1 -+/* Bit: 'TAG' */ -+/* Description: 'Add TAG' */ -+#define VR9_PMAC_HD_CTL_TAG_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_TAG_SHIFT 1 -+#define VR9_PMAC_HD_CTL_TAG_SIZE 1 -+/* Bit: 'ADD' */ -+/* Description: 'ADD Header' */ -+#define VR9_PMAC_HD_CTL_ADD_OFFSET 0x082 -+#define VR9_PMAC_HD_CTL_ADD_SHIFT 0 -+#define VR9_PMAC_HD_CTL_ADD_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Type/Length Register' */ -+/* Bit: 'TYPE_LEN' */ -+/* Description: 'TYPE or Lenght Value' */ -+#define VR9_PMAC_TL_TYPE_LEN_OFFSET 0x083 -+#define VR9_PMAC_TL_TYPE_LEN_SHIFT 0 -+#define VR9_PMAC_TL_TYPE_LEN_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Source Address Register1' */ -+/* Bit: 'SA_47_32' */ -+/* Description: 'Source Address 47..32' */ -+#define VR9_PMAC_SA1_SA_47_32_OFFSET 0x084 -+#define VR9_PMAC_SA1_SA_47_32_SHIFT 0 -+#define VR9_PMAC_SA1_SA_47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Source Address Register2' */ -+/* Bit: 'SA_31_16' */ -+/* Description: 'Source Address 31..16' */ -+#define VR9_PMAC_SA2_SA_31_16_OFFSET 0x085 -+#define VR9_PMAC_SA2_SA_31_16_SHIFT 0 -+#define VR9_PMAC_SA2_SA_31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Source Address Register3' */ -+/* Bit: 'SA_15_0' */ -+/* Description: 'Source Address 15..0' */ -+#define VR9_PMAC_SA3_SA_15_0_OFFSET 0x086 -+#define VR9_PMAC_SA3_SA_15_0_SHIFT 0 -+#define VR9_PMAC_SA3_SA_15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Destination AddressRegister 1' */ -+/* Bit: 'SA_47_32' */ -+/* Description: 'Destination Address 47..32' */ -+#define VR9_PMAC_DA1_SA_47_32_OFFSET 0x087 -+#define VR9_PMAC_DA1_SA_47_32_SHIFT 0 -+#define VR9_PMAC_DA1_SA_47_32_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Destination AddressRegister 2' */ -+/* Bit: 'DA_31_16' */ -+/* Description: 'Destination Address 31..16' */ -+#define VR9_PMAC_DA2_DA_31_16_OFFSET 0x088 -+#define VR9_PMAC_DA2_DA_31_16_SHIFT 0 -+#define VR9_PMAC_DA2_DA_31_16_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Destination AddressRegister 3' */ -+/* Bit: 'DA_15_0' */ -+/* Description: 'Destination Address 15..0' */ -+#define VR9_PMAC_DA3_DA_15_0_OFFSET 0x089 -+#define VR9_PMAC_DA3_DA_15_0_SHIFT 0 -+#define VR9_PMAC_DA3_DA_15_0_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC VLAN Register' */ -+/* Bit: 'PRI' */ -+/* Description: 'VLAN Priority' */ -+#define VR9_PMAC_VLAN_PRI_OFFSET 0x08A -+#define VR9_PMAC_VLAN_PRI_SHIFT 13 -+#define VR9_PMAC_VLAN_PRI_SIZE 3 -+/* Bit: 'CFI' */ -+/* Description: 'Canonical Format Identifier' */ -+#define VR9_PMAC_VLAN_CFI_OFFSET 0x08A -+#define VR9_PMAC_VLAN_CFI_SHIFT 12 -+#define VR9_PMAC_VLAN_CFI_SIZE 1 -+/* Bit: 'VLAN_ID' */ -+/* Description: 'VLAN ID' */ -+#define VR9_PMAC_VLAN_VLAN_ID_OFFSET 0x08A -+#define VR9_PMAC_VLAN_VLAN_ID_SHIFT 0 -+#define VR9_PMAC_VLAN_VLAN_ID_SIZE 12 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Inter Packet Gapin RX Direction' */ -+/* Bit: 'REQ_DS_THRES' */ -+/* Description: 'Request Deassertion Threshold' */ -+#define VR9_PMAC_RX_IPG_REQ_DS_THRES_OFFSET 0x08B -+#define VR9_PMAC_RX_IPG_REQ_DS_THRES_SHIFT 8 -+#define VR9_PMAC_RX_IPG_REQ_DS_THRES_SIZE 1 -+/* Bit: 'REQ_AS_THRES' */ -+/* Description: 'Request Assertion Threshold' */ -+#define VR9_PMAC_RX_IPG_REQ_AS_THRES_OFFSET 0x08B -+#define VR9_PMAC_RX_IPG_REQ_AS_THRES_SHIFT 4 -+#define VR9_PMAC_RX_IPG_REQ_AS_THRES_SIZE 4 -+/* Bit: 'IPG_CNT' */ -+/* Description: 'IPG Counter' */ -+#define VR9_PMAC_RX_IPG_IPG_CNT_OFFSET 0x08B -+#define VR9_PMAC_RX_IPG_IPG_CNT_SHIFT 0 -+#define VR9_PMAC_RX_IPG_IPG_CNT_SIZE 4 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Special Tag Ethertype' */ -+/* Bit: 'ST_ETYPE' */ -+/* Description: 'Special Tag Ethertype' */ -+#define VR9_PMAC_ST_ETYPE_ST_ETYPE_OFFSET 0x08C -+#define VR9_PMAC_ST_ETYPE_ST_ETYPE_SHIFT 0 -+#define VR9_PMAC_ST_ETYPE_ST_ETYPE_SIZE 16 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Ethernet WAN Group' */ -+/* Bit: 'EWAN' */ -+/* Description: 'Ethernet WAN Group' */ -+#define VR9_PMAC_EWAN_EWAN_OFFSET 0x08D -+#define VR9_PMAC_EWAN_EWAN_SHIFT 0 -+#define VR9_PMAC_EWAN_EWAN_SIZE 6 -+/* -------------------------------------------------------------------------- */ -+/* Register: 'PMAC Control Register' */ -+/* Bit: 'SPEED' */ -+/* Description: 'Speed Control' */ -+#define VR9_PMAC_CTL_SPEED_OFFSET 0x08E -+#define VR9_PMAC_CTL_SPEED_SHIFT 1 -+#define VR9_PMAC_CTL_SPEED_SIZE 1 -+/* Bit: 'EN' */ -+/* Description: 'PMAC Enable' */ -+#define VR9_PMAC_CTL_EN_OFFSET 0x08E -+#define VR9_PMAC_CTL_EN_SHIFT 0 -+#define VR9_PMAC_CTL_EN_SIZE 1 -+/* -------------------------------------------------------------------------- */ -+#endif /* #ifndef _VR9_TOP_H */ -diff --git a/include/switch_api/commonReg.h b/include/switch_api/commonReg.h -new file mode 100644 -index 0000000..373defc ---- /dev/null -+++ b/include/switch_api/commonReg.h -@@ -0,0 +1,1312 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+******************************************************************************/ -+#ifndef _IFX_ETHSW_REGMAPPERSELECTOR_H -+#define _IFX_ETHSW_REGMAPPERSELECTOR_H -+ -+typedef enum { -+ ARP_APT, /* (# 0) */ -+ ARP_MACA, /* (# 1) */ -+ ARP_RAPA, /* (# 2) */ -+ ARP_RAPOTH, /* (# 3) */ -+ ARP_RAPP, /* (# 4) */ -+ ARP_RAPPE, /* (# 5) */ -+ ARP_RAPTM, /* (# 6) */ -+ ARP_RPT, /* (# 7) */ -+ ARP_TAP, /* (# 8) */ -+ ARP_TAPTS, /* (# 9) */ -+ ARP_TRP, /* (# 10) */ -+ ARP_UPT, /* (# 11) */ -+ BIST_CTBR, /* (# 12) */ -+ BIST_DBBR, /* (# 13) */ -+ BIST_DONE, /* (# 14) */ -+ BIST_HIGTBR, /* (# 15) */ -+ BIST_HISTBR, /* (# 16) */ -+ BIST_LLTBR, /* (# 17) */ -+ BIST_LTBR, /* (# 18) */ -+ BUFFER_PFA, /* (# 19) */ -+ BUFFER_PFO0, /* (# 20) */ -+ BUFFER_PFO1, /* (# 21) */ -+ BUFFER_PFO2, /* (# 22) */ -+ BUFFER_PUA, /* (# 23) */ -+ BUFFER_PUO0, /* (# 24) */ -+ BUFFER_PUO1, /* (# 25) */ -+ BUFFER_PUO2, /* (# 26) */ -+ BUFFER_THA, /* (# 27) */ -+ BUFFER_THO, /* (# 28) */ -+ BUFFER_TLA, /* (# 29) */ -+ BUFFER_TLO, /* (# 30) */ -+ CHIPID_BOND, /* (# 31) */ -+ CHIPID_PC, /* (# 32) */ -+ CHIPID_VN, /* (# 33) */ -+ CONGESTION_EDSTX, /* (# 34) */ -+ CONGESTION_IJT, /* (# 35) */ -+ CONGESTION_IRSJA, /* (# 36) */ -+ CONGESTION_STORM_100_TH, /* (# 37) */ -+ CONGESTION_STORM_10_TH, /* (# 38) */ -+ CONGESTION_STORM_B, /* (# 39) */ -+ CONGESTION_STORM_M, /* (# 40) */ -+ CONGESTION_STORM_U, /* (# 41) */ -+ DIFFSERV_PQA, /* (# 42) */ -+ DIFFSERV_PQA01, /* (# 43) */ -+ DIFFSERV_PQA02, /* (# 44) */ -+ DIFFSERV_PQA03, /* (# 45) */ -+ DIFFSERV_PQA04, /* (# 46) */ -+ DIFFSERV_PQA05, /* (# 47) */ -+ DIFFSERV_PQA06, /* (# 48) */ -+ DIFFSERV_PQA07, /* (# 49) */ -+ DIFFSERV_PQA08, /* (# 50) */ -+ DIFFSERV_PQA09, /* (# 51) */ -+ DIFFSERV_PQA10, /* (# 52) */ -+ DIFFSERV_PQA11, /* (# 53) */ -+ DIFFSERV_PQA12, /* (# 54) */ -+ DIFFSERV_PQA13, /* (# 55) */ -+ DIFFSERV_PQA14, /* (# 56) */ -+ DIFFSERV_PQA15, /* (# 57) */ -+ DIFFSERV_PQB, /* (# 58) */ -+ DIFFSERV_PQB01, /* (# 59) */ -+ DIFFSERV_PQB02, /* (# 60) */ -+ DIFFSERV_PQB03, /* (# 61) */ -+ DIFFSERV_PQB04, /* (# 62) */ -+ DIFFSERV_PQB05, /* (# 63) */ -+ DIFFSERV_PQB06, /* (# 64) */ -+ DIFFSERV_PQB07, /* (# 65) */ -+ DIFFSERV_PQB08, /* (# 66) */ -+ DIFFSERV_PQB09, /* (# 67) */ -+ DIFFSERV_PQB10, /* (# 68) */ -+ DIFFSERV_PQB11, /* (# 69) */ -+ DIFFSERV_PQB12, /* (# 70) */ -+ DIFFSERV_PQB13, /* (# 71) */ -+ DIFFSERV_PQB14, /* (# 72) */ -+ DIFFSERV_PQB15, /* (# 73) */ -+ DIFFSERV_PQC, /* (# 74) */ -+ DIFFSERV_PQC01, /* (# 75) */ -+ DIFFSERV_PQC02, /* (# 76) */ -+ DIFFSERV_PQC03, /* (# 77) */ -+ DIFFSERV_PQC04, /* (# 78) */ -+ DIFFSERV_PQC05, /* (# 79) */ -+ DIFFSERV_PQC06, /* (# 80) */ -+ DIFFSERV_PQC07, /* (# 81) */ -+ DIFFSERV_PQC08, /* (# 82) */ -+ DIFFSERV_PQC09, /* (# 83) */ -+ DIFFSERV_PQC10, /* (# 84) */ -+ DIFFSERV_PQC11, /* (# 85) */ -+ DIFFSERV_PQC12, /* (# 86) */ -+ DIFFSERV_PQC13, /* (# 87) */ -+ DIFFSERV_PQC14, /* (# 88) */ -+ DIFFSERV_PQC15, /* (# 89) */ -+ DIFFSERV_PQD, /* (# 90) */ -+ DIFFSERV_PQD01, /* (# 91) */ -+ DIFFSERV_PQD02, /* (# 92) */ -+ DIFFSERV_PQD03, /* (# 93) */ -+ DIFFSERV_PQD04, /* (# 94) */ -+ DIFFSERV_PQD05, /* (# 95) */ -+ DIFFSERV_PQD06, /* (# 96) */ -+ DIFFSERV_PQD07, /* (# 97) */ -+ DIFFSERV_PQD08, /* (# 98) */ -+ DIFFSERV_PQD09, /* (# 99) */ -+ DIFFSERV_PQD10, /* (# 100) */ -+ DIFFSERV_PQD11, /* (# 101) */ -+ DIFFSERV_PQD12, /* (# 102) */ -+ DIFFSERV_PQD13, /* (# 103) */ -+ DIFFSERV_PQD14, /* (# 104) */ -+ DIFFSERV_PQD15, /* (# 105) */ -+ DOT1X_PRIORITY_1PPQ, /* (# 106) */ -+ DOT1X_PRIORITY_1PPQ1, /* (# 107) */ -+ DOT1X_PRIORITY_1PPQ2, /* (# 108) */ -+ DOT1X_PRIORITY_1PPQ3, /* (# 109) */ -+ DOT1X_PRIORITY_1PPQ4, /* (# 110) */ -+ DOT1X_PRIORITY_1PPQ5, /* (# 111) */ -+ DOT1X_PRIORITY_1PPQ6, /* (# 112) */ -+ DOT1X_PRIORITY_1PPQ7, /* (# 113) */ -+ GLOBAL_ATS, /* (# 114) */ -+ GLOBAL_CTTX, /* (# 115) */ -+ GLOBAL_DIE, /* (# 116) */ -+ GLOBAL_DII6P, /* (# 117) */ -+ GLOBAL_DIIP, /* (# 118) */ -+ GLOBAL_DIIPS, /* (# 119) */ -+ GLOBAL_DIS, /* (# 120) */ -+ GLOBAL_DIVS, /* (# 121) */ -+ GLOBAL_DMQ0, /* (# 122) */ -+ GLOBAL_DMQ1, /* (# 123) */ -+ GLOBAL_DMQ2, /* (# 124) */ -+ GLOBAL_DMQ3, /* (# 125) */ -+ GLOBAL_DPWECH, /* (# 126) */ -+ GLOBAL_DUPCOLSP, /* (# 127) */ -+ GLOBAL_ICRCCD, /* (# 128) */ -+ GLOBAL_ITENLMT, /* (# 129) */ -+ GLOBAL_ITRUNK, /* (# 130) */ -+ GLOBAL_LPE, /* (# 131) */ -+ GLOBAL_MPL, /* (# 132) */ -+ GLOBAL_P4M, /* (# 133) */ -+ GLOBAL_P5M, /* (# 134) */ -+ GLOBAL_P6M, /* (# 135) */ -+ GLOBAL_PCE, /* (# 136) */ -+ GLOBAL_PCR, /* (# 137) */ -+ GLOBAL_PHYBA, /* (# 138) */ -+ GLOBAL_RVID0, /* (# 139) */ -+ GLOBAL_RVID1, /* (# 140) */ -+ GLOBAL_RVIDFFF, /* (# 141) */ -+ GLOBAL_SE, /* (# 142) */ -+ GLOBAL_TSIPGE, /* (# 143) */ -+ INGRESS_FLOW_CTRL_B, /* (# 144) */ -+ INGRESS_FLOW_CTRL_BASE15_0, /* (# 145) */ -+ INGRESS_FLOW_CTRL_BASE17_16, /* (# 146) */ -+ INGRESS_FLOW_CTRL_EBASE15_0, /* (# 147) */ -+ INGRESS_FLOW_CTRL_EBASE17_16, /* (# 148) */ -+ INGRESS_FLOW_CTRL_F, /* (# 149) */ -+ IRQ_DBF, /* (# 150) */ -+ IRQ_DBFIE, /* (# 151) */ -+ IRQ_DBNF, /* (# 152) */ -+ IRQ_DBNFIE, /* (# 153) */ -+ IRQ_LTAD, /* (# 154) */ -+ IRQ_LTADIE, /* (# 155) */ -+ IRQ_LTF, /* (# 156) */ -+ IRQ_LTFIE, /* (# 157) */ -+ IRQ_PSC, /* (# 158) */ -+ IRQ_PSCIE, /* (# 159) */ -+ IRQ_PSV, /* (# 160) */ -+ IRQ_PSVIE, /* (# 161) */ -+ MAC_TABLE_ADDR15_0, /* (# 162) */ -+ MAC_TABLE_ADDR31_0, /* (# 163) */ -+ MAC_TABLE_ADDR31_16, /* (# 164) */ -+ MAC_TABLE_ADDR47_32, /* (# 165) */ -+ MAC_TABLE_ADDRS15_0, /* (# 166) */ -+ MAC_TABLE_ADDRS31_0, /* (# 167) */ -+ MAC_TABLE_ADDRS31_16, /* (# 168) */ -+ MAC_TABLE_ADDRS47_32, /* (# 169) */ -+ MAC_TABLE_BAD, /* (# 170) */ -+ MAC_TABLE_BUSY, /* (# 171) */ -+ MAC_TABLE_C_AC, /* (# 172) */ -+ MAC_TABLE_C_CMD, /* (# 173) */ -+ MAC_TABLE_C_FCE, /* (# 174) */ -+ MAC_TABLE_FID, /* (# 175) */ -+ MAC_TABLE_FIDS, /* (# 176) */ -+ MAC_TABLE_INFOT, /* (# 177) */ -+ MAC_TABLE_INFOTS, /* (# 178) */ -+ MAC_TABLE_ITAT, /* (# 179) */ -+ MAC_TABLE_ITATS, /* (# 180) */ -+ MAC_TABLE_OCP, /* (# 181) */ -+ MAC_TABLE_PMAP, /* (# 182) */ -+ MAC_TABLE_PMAPS, /* (# 183) */ -+ MAC_TABLE_RSLT, /* (# 184) */ -+ MAC_TABLE_S_AC, /* (# 185) */ -+ MAC_TABLE_S_CMD, /* (# 186) */ -+ MAC_TABLE_S_FCE, /* (# 187) */ -+ MCS, /* (# 188) */ -+ MDIO_MBUSY, /* (# 189) */ -+ MDIO_OP, /* (# 190) */ -+ MDIO_PHYAD, /* (# 191) */ -+ MDIO_RD, /* (# 192) */ -+ MDIO_REGAD, /* (# 193) */ -+ MDIO_WD, /* (# 194) */ -+ MIRROR_CCCRC, /* (# 195) */ -+ MIRROR_CPN, /* (# 196) */ -+ MIRROR_IGSTA, /* (# 197) */ -+ MIRROR_MCA, /* (# 198) */ -+ MIRROR_MLA, /* (# 199) */ -+ MIRROR_MPA, /* (# 200) */ -+ MIRROR_MRA, /* (# 201) */ -+ MIRROR_MSA, /* (# 202) */ -+ MIRROR_PAST, /* (# 203) */ -+ MIRROR_SNIFFPN, /* (# 204) */ -+ MIRROR_STRE, /* (# 205) */ -+ MIRROR_STTE, /* (# 206) */ -+ MULTICAST_ASC, /* (# 207) */ -+ MULTICAST_B01, /* (# 208) */ -+ MULTICAST_B224, /* (# 209) */ -+ MULTICAST_B33, /* (# 210) */ -+ MULTICAST_DAIPS, /* (# 211) */ -+ MULTICAST_DRP, /* (# 212) */ -+ MULTICAST_FMODE, /* (# 213) */ -+ MULTICAST_GID15_0, /* (# 214) */ -+ MULTICAST_GID31_16, /* (# 215) */ -+ MULTICAST_HIPI, /* (# 216) */ -+ MULTICAST_HISE, /* (# 217) */ -+ MULTICAST_HISFL, /* (# 218) */ -+ MULTICAST_ICMD, /* (# 219) */ -+ MULTICAST_IGMPV3E, /* (# 220) */ -+ MULTICAST_INVC, /* (# 221) */ -+ MULTICAST_IPMPT, /* (# 222) */ -+ MULTICAST_PORT, /* (# 223) */ -+ MULTICAST_PPPOEHR, /* (# 224) */ -+ MULTICAST_QI, /* (# 225) */ -+ MULTICAST_RV, /* (# 226) */ -+ MULTICAST_S3PMI, /* (# 227) */ -+ MULTICAST_S3PMV, /* (# 228) */ -+ MULTICAST_S4BUSY, /* (# 229) */ -+ MULTICAST_S4R, /* (# 230) */ -+ MULTICAST_SARE, /* (# 231) */ -+ MULTICAST_SCPA, /* (# 232) */ -+ MULTICAST_SCPP, /* (# 233) */ -+ MULTICAST_SCPPE, /* (# 234) */ -+ MULTICAST_SCPTCP, /* (# 235) */ -+ MULTICAST_SCPTMP, /* (# 236) */ -+ MULTICAST_SCPTSP, /* (# 237) */ -+ MULTICAST_SCPTTH, /* (# 238) */ -+ MULTICAST_SIP15_0, /* (# 239) */ -+ MULTICAST_SIP31_16, /* (# 240) */ -+ MULTICAST_SIP47_32, /* (# 241) */ -+ MULTICAST_SIPGID0, /* (# 242) */ -+ MULTICAST_SIPGID1, /* (# 243) */ -+ MULTICAST_SIPGID2, /* (# 244) */ -+ MULTICAST_TIMERC, /* (# 245) */ -+ PAUSE_ADDR15_0, /* (# 246) */ -+ PAUSE_ADDR31_16, /* (# 247) */ -+ PAUSE_ADDR39_32, /* (# 248) */ -+ PAUSE_ADDR47_41, /* (# 249) */ -+ PAUSE_PAC, /* (# 250) */ -+ PHY_INIT_PHYIE0, /* (# 251) */ -+ PHY_INIT_PHYIE01, /* (# 252) */ -+ PHY_INIT_PHYIE02, /* (# 253) */ -+ PHY_INIT_PHYIE03, /* (# 254) */ -+ PHY_INIT_PHYIE1, /* (# 255) */ -+ PHY_INIT_PHYIE11, /* (# 256) */ -+ PHY_INIT_PHYIE12, /* (# 257) */ -+ PHY_INIT_PHYIE13, /* (# 258) */ -+ PHY_INIT_PHYIE2, /* (# 259) */ -+ PHY_INIT_PHYIE21, /* (# 260) */ -+ PHY_INIT_PHYIE22, /* (# 261) */ -+ PHY_INIT_PHYIE23, /* (# 262) */ -+ PHY_INIT_PHYIE3, /* (# 263) */ -+ PHY_INIT_PHYIE31, /* (# 264) */ -+ PHY_INIT_PHYIE32, /* (# 265) */ -+ PHY_INIT_PHYIE33, /* (# 266) */ -+ PHY_INIT_PHYIE4, /* (# 267) */ -+ PHY_INIT_PHYIE41, /* (# 268) */ -+ PHY_INIT_PHYIE42, /* (# 269) */ -+ PHY_INIT_PHYIE43, /* (# 270) */ -+ PHY_INIT_PHYIE5, /* (# 271) */ -+ PHY_INIT_PHYIE51, /* (# 272) */ -+ PHY_INIT_PHYIE52, /* (# 273) */ -+ PHY_INIT_PHYIE53, /* (# 274) */ -+ PHY_INIT_PHYIE6, /* (# 275) */ -+ PHY_INIT_PHYIE61, /* (# 276) */ -+ PHY_INIT_PHYIE62, /* (# 277) */ -+ PHY_INIT_PHYIE63, /* (# 278) */ -+ PHY_INIT_REGA, /* (# 279) */ -+ PHY_INIT_REGA1, /* (# 280) */ -+ PHY_INIT_REGA2, /* (# 281) */ -+ PHY_INIT_REGA3, /* (# 282) */ -+ PHY_INIT_REGD, /* (# 283) */ -+ PHY_INIT_REGD1, /* (# 284) */ -+ PHY_INIT_REGD2, /* (# 285) */ -+ PHY_INIT_REGD3, /* (# 286) */ -+ PMAC_ADD, /* (# 287) */ -+ PMAC_ADD_CRC, /* (# 288) */ -+ PMAC_AS, /* (# 289) */ -+ PMAC_CFI, /* (# 290) */ -+ PMAC_DA_31_0, /* (# 291) */ -+ PMAC_DA_47_32, /* (# 292) */ -+ PMAC_IDIS_REQ_WM, /* (# 293) */ -+ PMAC_IPG_RX_CNT, /* (# 294) */ -+ PMAC_IPG_TX_CNT, /* (# 295) */ -+ PMAC_IREQ_WM, /* (# 296) */ -+ PMAC_PRI, /* (# 297) */ -+ PMAC_RC, /* (# 298) */ -+ PMAC_RL2, /* (# 299) */ -+ PMAC_RXSH, /* (# 300) */ -+ PMAC_SA_31_0, /* (# 301) */ -+ PMAC_SA_47_32, /* (# 302) */ -+ PMAC_TAG, /* (# 303) */ -+ PMAC_TYPE_LEN, /* (# 304) */ -+ PMAC_VLAN_ID, /* (# 305) */ -+ PORT_AD, /* (# 306) */ -+ PORT_AD1, /* (# 307) */ -+ PORT_AD2, /* (# 308) */ -+ PORT_AD3, /* (# 309) */ -+ PORT_AD4, /* (# 310) */ -+ PORT_AD5, /* (# 311) */ -+ PORT_AD6, /* (# 312) */ -+ PORT_BP, /* (# 313) */ -+ PORT_DFWD, /* (# 314) */ -+ PORT_DFWD1, /* (# 315) */ -+ PORT_DFWD2, /* (# 316) */ -+ PORT_DSV821X, /* (# 317) */ -+ PORT_DSV821X1, /* (# 318) */ -+ PORT_DSV821X2, /* (# 319) */ -+ PORT_EGRESS_PSPQ0TR, /* (# 320) */ -+ PORT_EGRESS_PSPQ0TR1, /* (# 321) */ -+ PORT_EGRESS_PSPQ0TR2, /* (# 322) */ -+ PORT_EGRESS_PSPQ0TR3, /* (# 323) */ -+ PORT_EGRESS_PSPQ0TR4, /* (# 324) */ -+ PORT_EGRESS_PSPQ0TR5, /* (# 325) */ -+ PORT_EGRESS_PSPQ0TR6, /* (# 326) */ -+ PORT_EGRESS_PSPQ1TR, /* (# 327) */ -+ PORT_EGRESS_PSPQ1TR1, /* (# 328) */ -+ PORT_EGRESS_PSPQ1TR2, /* (# 329) */ -+ PORT_EGRESS_PSPQ1TR3, /* (# 330) */ -+ PORT_EGRESS_PSPQ1TR4, /* (# 331) */ -+ PORT_EGRESS_PSPQ1TR5, /* (# 332) */ -+ PORT_EGRESS_PSPQ1TR6, /* (# 333) */ -+ PORT_EGRESS_PSPQ2TR, /* (# 334) */ -+ PORT_EGRESS_PSPQ2TR1, /* (# 335) */ -+ PORT_EGRESS_PSPQ2TR2, /* (# 336) */ -+ PORT_EGRESS_PSPQ2TR3, /* (# 337) */ -+ PORT_EGRESS_PSPQ2TR4, /* (# 338) */ -+ PORT_EGRESS_PSPQ2TR5, /* (# 339) */ -+ PORT_EGRESS_PSPQ2TR6, /* (# 340) */ -+ PORT_EGRESS_PSPQ3TR, /* (# 341) */ -+ PORT_EGRESS_PSPQ3TR1, /* (# 342) */ -+ PORT_EGRESS_PSPQ3TR2, /* (# 343) */ -+ PORT_EGRESS_PSPQ3TR3, /* (# 344) */ -+ PORT_EGRESS_PSPQ3TR4, /* (# 345) */ -+ PORT_EGRESS_PSPQ3TR5, /* (# 346) */ -+ PORT_EGRESS_PSPQ3TR6, /* (# 347) */ -+ PORT_EGRESS_PWQ0TR, /* (# 348) */ -+ PORT_EGRESS_PWQ0TR1, /* (# 349) */ -+ PORT_EGRESS_PWQ0TR2, /* (# 350) */ -+ PORT_EGRESS_PWQ0TR3, /* (# 351) */ -+ PORT_EGRESS_PWQ0TR4, /* (# 352) */ -+ PORT_EGRESS_PWQ0TR5, /* (# 353) */ -+ PORT_EGRESS_PWQ0TR6, /* (# 354) */ -+ PORT_EGRESS_PWQ1TR, /* (# 355) */ -+ PORT_EGRESS_PWQ1TR1, /* (# 356) */ -+ PORT_EGRESS_PWQ1TR2, /* (# 357) */ -+ PORT_EGRESS_PWQ1TR3, /* (# 358) */ -+ PORT_EGRESS_PWQ1TR4, /* (# 359) */ -+ PORT_EGRESS_PWQ1TR5, /* (# 360) */ -+ PORT_EGRESS_PWQ1TR6, /* (# 361) */ -+ PORT_EGRESS_PWQ2TR, /* (# 362) */ -+ PORT_EGRESS_PWQ2TR1, /* (# 363) */ -+ PORT_EGRESS_PWQ2TR2, /* (# 364) */ -+ PORT_EGRESS_PWQ2TR3, /* (# 365) */ -+ PORT_EGRESS_PWQ2TR4, /* (# 366) */ -+ PORT_EGRESS_PWQ2TR5, /* (# 367) */ -+ PORT_EGRESS_PWQ2TR6, /* (# 368) */ -+ PORT_EGRESS_PWQ3TR, /* (# 369) */ -+ PORT_EGRESS_PWQ3TR1, /* (# 370) */ -+ PORT_EGRESS_PWQ3TR2, /* (# 371) */ -+ PORT_EGRESS_PWQ3TR3, /* (# 372) */ -+ PORT_EGRESS_PWQ3TR4, /* (# 373) */ -+ PORT_EGRESS_PWQ3TR5, /* (# 374) */ -+ PORT_EGRESS_PWQ3TR6, /* (# 375) */ -+ PORT_FILTER_ATUF, /* (# 376) */ -+ PORT_FILTER_ATUF1, /* (# 377) */ -+ PORT_FILTER_ATUF2, /* (# 378) */ -+ PORT_FILTER_ATUF3, /* (# 379) */ -+ PORT_FILTER_ATUF4, /* (# 380) */ -+ PORT_FILTER_ATUF5, /* (# 381) */ -+ PORT_FILTER_ATUF6, /* (# 382) */ -+ PORT_FILTER_ATUF7, /* (# 383) */ -+ PORT_FILTER_BASEPT, /* (# 384) */ -+ PORT_FILTER_BASEPT1, /* (# 385) */ -+ PORT_FILTER_BASEPT2, /* (# 386) */ -+ PORT_FILTER_BASEPT3, /* (# 387) */ -+ PORT_FILTER_BASEPT4, /* (# 388) */ -+ PORT_FILTER_BASEPT5, /* (# 389) */ -+ PORT_FILTER_BASEPT6, /* (# 390) */ -+ PORT_FILTER_BASEPT7, /* (# 391) */ -+ PORT_FILTER_COMP, /* (# 392) */ -+ PORT_FILTER_COMP1, /* (# 393) */ -+ PORT_FILTER_COMP2, /* (# 394) */ -+ PORT_FILTER_COMP3, /* (# 395) */ -+ PORT_FILTER_COMP4, /* (# 396) */ -+ PORT_FILTER_COMP5, /* (# 397) */ -+ PORT_FILTER_COMP6, /* (# 398) */ -+ PORT_FILTER_COMP7, /* (# 399) */ -+ PORT_FILTER_PRANGE, /* (# 400) */ -+ PORT_FILTER_PRANGE1, /* (# 401) */ -+ PORT_FILTER_PRANGE2, /* (# 402) */ -+ PORT_FILTER_PRANGE3, /* (# 403) */ -+ PORT_FILTER_PRANGE4, /* (# 404) */ -+ PORT_FILTER_PRANGE5, /* (# 405) */ -+ PORT_FILTER_PRANGE6, /* (# 406) */ -+ PORT_FILTER_PRANGE7, /* (# 407) */ -+ PORT_FILTER_TUPF, /* (# 408) */ -+ PORT_FILTER_TUPF1, /* (# 409) */ -+ PORT_FILTER_TUPF2, /* (# 410) */ -+ PORT_FILTER_TUPF3, /* (# 411) */ -+ PORT_FILTER_TUPF4, /* (# 412) */ -+ PORT_FILTER_TUPF5, /* (# 413) */ -+ PORT_FILTER_TUPF6, /* (# 414) */ -+ PORT_FILTER_TUPF7, /* (# 415) */ -+ PORT_FLD, /* (# 416) */ -+ PORT_FLD1, /* (# 417) */ -+ PORT_FLD2, /* (# 418) */ -+ PORT_FLD3, /* (# 419) */ -+ PORT_FLD4, /* (# 420) */ -+ PORT_FLD5, /* (# 421) */ -+ PORT_FLD6, /* (# 422) */ -+ PORT_FLP, /* (# 423) */ -+ PORT_FLP1, /* (# 424) */ -+ PORT_FLP2, /* (# 425) */ -+ PORT_FLP3, /* (# 426) */ -+ PORT_FLP4, /* (# 427) */ -+ PORT_FLP5, /* (# 428) */ -+ PORT_FLP6, /* (# 429) */ -+ PORT_IFNTE, /* (# 430) */ -+ PORT_IFNTE1, /* (# 431) */ -+ PORT_IFNTE2, /* (# 432) */ -+ PORT_IFNTE3, /* (# 433) */ -+ PORT_IFNTE4, /* (# 434) */ -+ PORT_IFNTE5, /* (# 435) */ -+ PORT_IFNTE6, /* (# 436) */ -+ PORT_IMTE, /* (# 437) */ -+ PORT_IMTE1, /* (# 438) */ -+ PORT_IMTE2, /* (# 439) */ -+ PORT_IMTE3, /* (# 440) */ -+ PORT_IMTE4, /* (# 441) */ -+ PORT_IMTE5, /* (# 442) */ -+ PORT_IMTE6, /* (# 443) */ -+ PORT_INGRESS_PITR, /* (# 444) */ -+ PORT_INGRESS_PITR1, /* (# 445) */ -+ PORT_INGRESS_PITR2, /* (# 446) */ -+ PORT_INGRESS_PITR3, /* (# 447) */ -+ PORT_INGRESS_PITR4, /* (# 448) */ -+ PORT_INGRESS_PITR5, /* (# 449) */ -+ PORT_INGRESS_PITR6, /* (# 450) */ -+ PORT_INGRESS_PITT, /* (# 451) */ -+ PORT_INGRESS_PITT1, /* (# 452) */ -+ PORT_INGRESS_PITT2, /* (# 453) */ -+ PORT_INGRESS_PITT3, /* (# 454) */ -+ PORT_INGRESS_PITT4, /* (# 455) */ -+ PORT_INGRESS_PITT5, /* (# 456) */ -+ PORT_INGRESS_PITT6, /* (# 457) */ -+ PORT_IPMO, /* (# 458) */ -+ PORT_IPMO1, /* (# 459) */ -+ PORT_IPMO2, /* (# 460) */ -+ PORT_IPMO3, /* (# 461) */ -+ PORT_IPMO4, /* (# 462) */ -+ PORT_IPMO5, /* (# 463) */ -+ PORT_IPMO6, /* (# 464) */ -+ PORT_IPOVTU, /* (# 465) */ -+ PORT_IPOVTU1, /* (# 466) */ -+ PORT_IPOVTU2, /* (# 467) */ -+ PORT_IPOVTU3, /* (# 468) */ -+ PORT_IPOVTU4, /* (# 469) */ -+ PORT_IPOVTU5, /* (# 470) */ -+ PORT_IPOVTU6, /* (# 471) */ -+ PORT_IPVLAN, /* (# 472) */ -+ PORT_IPVLAN1, /* (# 473) */ -+ PORT_IPVLAN2, /* (# 474) */ -+ PORT_IPVLAN3, /* (# 475) */ -+ PORT_IPVLAN4, /* (# 476) */ -+ PORT_IPVLAN5, /* (# 477) */ -+ PORT_IPVLAN6, /* (# 478) */ -+ PORT_LD, /* (# 479) */ -+ PORT_LD1, /* (# 480) */ -+ PORT_LD2, /* (# 481) */ -+ PORT_LD3, /* (# 482) */ -+ PORT_LD4, /* (# 483) */ -+ PORT_LD5, /* (# 484) */ -+ PORT_LD6, /* (# 485) */ -+ PORT_MNA24, /* (# 486) */ -+ PORT_MNA241, /* (# 487) */ -+ PORT_MNA242, /* (# 488) */ -+ PORT_MNA243, /* (# 489) */ -+ PORT_MNA244, /* (# 490) */ -+ PORT_MNA245, /* (# 491) */ -+ PORT_MNA246, /* (# 492) */ -+ PORT_MP, /* (# 493) */ -+ PORT_PAS, /* (# 494) */ -+ PORT_PAS1, /* (# 495) */ -+ PORT_PAS2, /* (# 496) */ -+ PORT_PAS3, /* (# 497) */ -+ PORT_PAS4, /* (# 498) */ -+ PORT_PAS5, /* (# 499) */ -+ PORT_PAS6, /* (# 500) */ -+ PORT_PDS, /* (# 501) */ -+ PORT_PDS1, /* (# 502) */ -+ PORT_PDS2, /* (# 503) */ -+ PORT_PDS3, /* (# 504) */ -+ PORT_PDS4, /* (# 505) */ -+ PORT_PDS5, /* (# 506) */ -+ PORT_PDS6, /* (# 507) */ -+ PORT_PFCS, /* (# 508) */ -+ PORT_PFCS1, /* (# 509) */ -+ PORT_PFCS2, /* (# 510) */ -+ PORT_PFCS3, /* (# 511) */ -+ PORT_PFCS4, /* (# 512) */ -+ PORT_PFCS5, /* (# 513) */ -+ PORT_PFCS6, /* (# 514) */ -+ PORT_PLS, /* (# 515) */ -+ PORT_PLS1, /* (# 516) */ -+ PORT_PLS2, /* (# 517) */ -+ PORT_PLS3, /* (# 518) */ -+ PORT_PLS4, /* (# 519) */ -+ PORT_PLS5, /* (# 520) */ -+ PORT_PLS6, /* (# 521) */ -+ PORT_PM, /* (# 522) */ -+ PORT_PM1, /* (# 523) */ -+ PORT_PM2, /* (# 524) */ -+ PORT_PM3, /* (# 525) */ -+ PORT_PM4, /* (# 526) */ -+ PORT_PM5, /* (# 527) */ -+ PORT_PM6, /* (# 528) */ -+ PORT_PPPOEP, /* (# 529) */ -+ PORT_PPPOEP1, /* (# 530) */ -+ PORT_PPPOEP2, /* (# 531) */ -+ PORT_PPPOEP3, /* (# 532) */ -+ PORT_PPPOEP4, /* (# 533) */ -+ PORT_PPPOEP5, /* (# 534) */ -+ PORT_PPPOEP6, /* (# 535) */ -+ PORT_PSHS, /* (# 536) */ -+ PORT_PSHS1, /* (# 537) */ -+ PORT_PSHS2, /* (# 538) */ -+ PORT_PSHS3, /* (# 539) */ -+ PORT_PSHS4, /* (# 540) */ -+ PORT_PSHS5, /* (# 541) */ -+ PORT_PSHS6, /* (# 542) */ -+ PORT_PSS, /* (# 543) */ -+ PORT_PSS1, /* (# 544) */ -+ PORT_PSS2, /* (# 545) */ -+ PORT_PSS3, /* (# 546) */ -+ PORT_PSS4, /* (# 547) */ -+ PORT_PSS5, /* (# 548) */ -+ PORT_PSS6, /* (# 549) */ -+ PORT_REDIR, /* (# 550) */ -+ PORT_REDIR1, /* (# 551) */ -+ PORT_REDIR2, /* (# 552) */ -+ PORT_RGMII_GMII_P0CKIO, /* (# 553) */ -+ PORT_RGMII_GMII_P0DUP, /* (# 554) */ -+ PORT_RGMII_GMII_P0FCE, /* (# 555) */ -+ PORT_RGMII_GMII_P0FEQ, /* (# 556) */ -+ PORT_RGMII_GMII_P0IS, /* (# 557) */ -+ PORT_RGMII_GMII_P0RDLY, /* (# 558) */ -+ PORT_RGMII_GMII_P0SPD, /* (# 559) */ -+ PORT_RGMII_GMII_P0TDLY, /* (# 560) */ -+ PORT_RGMII_GMII_P1CKIO, /* (# 561) */ -+ PORT_RGMII_GMII_P1DUP, /* (# 562) */ -+ PORT_RGMII_GMII_P1FCE, /* (# 563) */ -+ PORT_RGMII_GMII_P1FEQ, /* (# 564) */ -+ PORT_RGMII_GMII_P1IS, /* (# 565) */ -+ PORT_RGMII_GMII_P1RDLY, /* (# 566) */ -+ PORT_RGMII_GMII_P1SPD, /* (# 567) */ -+ PORT_RGMII_GMII_P1TDLY, /* (# 568) */ -+ PORT_RGMII_GMII_P4DUP, /* (# 569) */ -+ PORT_RGMII_GMII_P4FCE, /* (# 570) */ -+ PORT_RGMII_GMII_P4SPD, /* (# 571) */ -+ PORT_RGMII_GMII_P5DUP, /* (# 572) */ -+ PORT_RGMII_GMII_P5FCE, /* (# 573) */ -+ PORT_RGMII_GMII_P5SPD, /* (# 574) */ -+ PORT_RGMII_GMII_P6DUP, /* (# 575) */ -+ PORT_RGMII_GMII_P6FCE, /* (# 576) */ -+ PORT_RGMII_GMII_P6SPD, /* (# 577) */ -+ PORT_RMWFQ, /* (# 578) */ -+ PORT_RMWFQ1, /* (# 579) */ -+ PORT_RMWFQ2, /* (# 580) */ -+ PORT_RMWFQ3, /* (# 581) */ -+ PORT_RMWFQ4, /* (# 582) */ -+ PORT_RMWFQ5, /* (# 583) */ -+ PORT_RMWFQ6, /* (# 584) */ -+ PORT_RP, /* (# 585) */ -+ PORT_SPE, /* (# 586) */ -+ PORT_SPE1, /* (# 587) */ -+ PORT_SPE2, /* (# 588) */ -+ PORT_SPE3, /* (# 589) */ -+ PORT_SPE4, /* (# 590) */ -+ PORT_SPE5, /* (# 591) */ -+ PORT_SPE6, /* (# 592) */ -+ PORT_SPS, /* (# 593) */ -+ PORT_SPS1, /* (# 594) */ -+ PORT_SPS2, /* (# 595) */ -+ PORT_SPS3, /* (# 596) */ -+ PORT_SPS4, /* (# 597) */ -+ PORT_SPS5, /* (# 598) */ -+ PORT_SPS6, /* (# 599) */ -+ PORT_TCPE, /* (# 600) */ -+ PORT_TCPE1, /* (# 601) */ -+ PORT_TCPE2, /* (# 602) */ -+ PORT_TCPE3, /* (# 603) */ -+ PORT_TCPE4, /* (# 604) */ -+ PORT_TCPE5, /* (# 605) */ -+ PORT_TCPE6, /* (# 606) */ -+ PORT_TPE, /* (# 607) */ -+ PORT_TPE1, /* (# 608) */ -+ PORT_TPE2, /* (# 609) */ -+ PORT_TPE3, /* (# 610) */ -+ PORT_TPE4, /* (# 611) */ -+ PORT_TPE5, /* (# 612) */ -+ PORT_TPE6, /* (# 613) */ -+ PORT_UP, /* (# 614) */ -+ PORT_VLAN_AOVTP, /* (# 615) */ -+ PORT_VLAN_AOVTP1, /* (# 616) */ -+ PORT_VLAN_AOVTP2, /* (# 617) */ -+ PORT_VLAN_AOVTP3, /* (# 618) */ -+ PORT_VLAN_AOVTP4, /* (# 619) */ -+ PORT_VLAN_AOVTP5, /* (# 620) */ -+ PORT_VLAN_AOVTP6, /* (# 621) */ -+ PORT_VLAN_BYPASS, /* (# 622) */ -+ PORT_VLAN_BYPASS1, /* (# 623) */ -+ PORT_VLAN_BYPASS2, /* (# 624) */ -+ PORT_VLAN_BYPASS3, /* (# 625) */ -+ PORT_VLAN_BYPASS4, /* (# 626) */ -+ PORT_VLAN_BYPASS5, /* (# 627) */ -+ PORT_VLAN_BYPASS6, /* (# 628) */ -+ PORT_VLAN_DFID, /* (# 629) */ -+ PORT_VLAN_DFID1, /* (# 630) */ -+ PORT_VLAN_DFID2, /* (# 631) */ -+ PORT_VLAN_DFID3, /* (# 632) */ -+ PORT_VLAN_DFID4, /* (# 633) */ -+ PORT_VLAN_DFID5, /* (# 634) */ -+ PORT_VLAN_DFID6, /* (# 635) */ -+ PORT_VLAN_DVPM, /* (# 636) */ -+ PORT_VLAN_DVPM1, /* (# 637) */ -+ PORT_VLAN_DVPM2, /* (# 638) */ -+ PORT_VLAN_DVPM3, /* (# 639) */ -+ PORT_VLAN_DVPM4, /* (# 640) */ -+ PORT_VLAN_DVPM5, /* (# 641) */ -+ PORT_VLAN_DVPM6, /* (# 642) */ -+ PORT_VLAN_PP, /* (# 643) */ -+ PORT_VLAN_PP1, /* (# 644) */ -+ PORT_VLAN_PP2, /* (# 645) */ -+ PORT_VLAN_PP3, /* (# 646) */ -+ PORT_VLAN_PP4, /* (# 647) */ -+ PORT_VLAN_PP5, /* (# 648) */ -+ PORT_VLAN_PP6, /* (# 649) */ -+ PORT_VLAN_PPE, /* (# 650) */ -+ PORT_VLAN_PPE1, /* (# 651) */ -+ PORT_VLAN_PPE2, /* (# 652) */ -+ PORT_VLAN_PPE3, /* (# 653) */ -+ PORT_VLAN_PPE4, /* (# 654) */ -+ PORT_VLAN_PPE5, /* (# 655) */ -+ PORT_VLAN_PPE6, /* (# 656) */ -+ PORT_VLAN_PVID, /* (# 657) */ -+ PORT_VLAN_PVID1, /* (# 658) */ -+ PORT_VLAN_PVID2, /* (# 659) */ -+ PORT_VLAN_PVID3, /* (# 660) */ -+ PORT_VLAN_PVID4, /* (# 661) */ -+ PORT_VLAN_PVID5, /* (# 662) */ -+ PORT_VLAN_PVID6, /* (# 663) */ -+ PORT_VLAN_PVTAGMP, /* (# 664) */ -+ PORT_VLAN_PVTAGMP1, /* (# 665) */ -+ PORT_VLAN_PVTAGMP2, /* (# 666) */ -+ PORT_VLAN_PVTAGMP3, /* (# 667) */ -+ PORT_VLAN_PVTAGMP4, /* (# 668) */ -+ PORT_VLAN_PVTAGMP5, /* (# 669) */ -+ PORT_VLAN_PVTAGMP6, /* (# 670) */ -+ PORT_VLAN_TBVE, /* (# 671) */ -+ PORT_VLAN_TBVE1, /* (# 672) */ -+ PORT_VLAN_TBVE2, /* (# 673) */ -+ PORT_VLAN_TBVE3, /* (# 674) */ -+ PORT_VLAN_TBVE4, /* (# 675) */ -+ PORT_VLAN_TBVE5, /* (# 676) */ -+ PORT_VLAN_TBVE6, /* (# 677) */ -+ PORT_VLAN_VC, /* (# 678) */ -+ PORT_VLAN_VC1, /* (# 679) */ -+ PORT_VLAN_VC2, /* (# 680) */ -+ PORT_VLAN_VC3, /* (# 681) */ -+ PORT_VLAN_VC4, /* (# 682) */ -+ PORT_VLAN_VC5, /* (# 683) */ -+ PORT_VLAN_VC6, /* (# 684) */ -+ PORT_VLAN_VMCE, /* (# 685) */ -+ PORT_VLAN_VMCE1, /* (# 686) */ -+ PORT_VLAN_VMCE2, /* (# 687) */ -+ PORT_VLAN_VMCE3, /* (# 688) */ -+ PORT_VLAN_VMCE4, /* (# 689) */ -+ PORT_VLAN_VMCE5, /* (# 690) */ -+ PORT_VLAN_VMCE6, /* (# 691) */ -+ PORT_VLAN_VSD, /* (# 692) */ -+ PORT_VLAN_VSD1, /* (# 693) */ -+ PORT_VLAN_VSD2, /* (# 694) */ -+ PORT_VLAN_VSD3, /* (# 695) */ -+ PORT_VLAN_VSD4, /* (# 696) */ -+ PORT_VLAN_VSD5, /* (# 697) */ -+ PORT_VLAN_VSD6, /* (# 698) */ -+ PORT_VPE, /* (# 699) */ -+ PORT_VPE1, /* (# 700) */ -+ PORT_VPE2, /* (# 701) */ -+ PORT_VPE3, /* (# 702) */ -+ PORT_VPE4, /* (# 703) */ -+ PORT_VPE5, /* (# 704) */ -+ PORT_VPE6, /* (# 705) */ -+ PPPOE_SID, /* (# 706) */ -+ PROTOCOL_FILTER_APF, /* (# 707) */ -+ PROTOCOL_FILTER_APF1, /* (# 708) */ -+ PROTOCOL_FILTER_APF2, /* (# 709) */ -+ PROTOCOL_FILTER_APF3, /* (# 710) */ -+ PROTOCOL_FILTER_APF4, /* (# 711) */ -+ PROTOCOL_FILTER_APF5, /* (# 712) */ -+ PROTOCOL_FILTER_APF6, /* (# 713) */ -+ PROTOCOL_FILTER_APF7, /* (# 714) */ -+ PROTOCOL_FILTER_PFR0, /* (# 715) */ -+ PROTOCOL_FILTER_PFR01, /* (# 716) */ -+ PROTOCOL_FILTER_PFR02, /* (# 717) */ -+ PROTOCOL_FILTER_PFR03, /* (# 718) */ -+ PROTOCOL_FILTER_PFR1, /* (# 719) */ -+ PROTOCOL_FILTER_PFR11, /* (# 720) */ -+ PROTOCOL_FILTER_PFR12, /* (# 721) */ -+ PROTOCOL_FILTER_PFR13, /* (# 722) */ -+ PROTOCOL_FILTER_PFR2, /* (# 723) */ -+ PROTOCOL_FILTER_PFR21, /* (# 724) */ -+ PROTOCOL_FILTER_PFR3, /* (# 725) */ -+ PROTOCOL_FILTER_PFR31, /* (# 726) */ -+ RA00_ACT, /* (# 727) */ -+ RA00_ACT1, /* (# 728) */ -+ RA00_ACT2, /* (# 729) */ -+ RA00_ACT3, /* (# 730) */ -+ RA00_ACT4, /* (# 731) */ -+ RA00_ACT5, /* (# 732) */ -+ RA00_ACT6, /* (# 733) */ -+ RA00_ACT7, /* (# 734) */ -+ RA00_ACT8, /* (# 735) */ -+ RA00_ACT9, /* (# 736) */ -+ RA00_ACT10, /* (# 737) */ -+ RA00_ACT11, /* (# 738) */ -+ RA00_ACT12, /* (# 739) */ -+ RA00_ACT13, /* (# 740) */ -+ RA00_ACT14, /* (# 741) */ -+ RA00_ACT15, /* (# 742) */ -+ RA00_ACT16, /* (# 743) */ -+ RA00_ACT17, /* (# 744) */ -+ RA00_ACT18, /* (# 745) */ -+ RA00_ACT19, /* (# 746) */ -+ RA00_ACT20, /* (# 747) */ -+ RA00_ACT21, /* (# 748) */ -+ RA00_ACT22, /* (# 749) */ -+ RA00_ACT23, /* (# 750) */ -+ RA00_CV, /* (# 751) */ -+ RA00_CV1, /* (# 752) */ -+ RA00_CV2, /* (# 753) */ -+ RA00_CV3, /* (# 754) */ -+ RA00_CV4, /* (# 755) */ -+ RA00_CV5, /* (# 756) */ -+ RA00_CV6, /* (# 757) */ -+ RA00_CV7, /* (# 758) */ -+ RA00_CV8, /* (# 759) */ -+ RA00_CV9, /* (# 760) */ -+ RA00_CV10, /* (# 761) */ -+ RA00_CV11, /* (# 762) */ -+ RA00_CV12, /* (# 763) */ -+ RA00_CV13, /* (# 764) */ -+ RA00_CV14, /* (# 765) */ -+ RA00_CV15, /* (# 766) */ -+ RA00_CV16, /* (# 767) */ -+ RA00_CV17, /* (# 768) */ -+ RA00_CV18, /* (# 769) */ -+ RA00_CV19, /* (# 770) */ -+ RA00_CV20, /* (# 771) */ -+ RA00_CV21, /* (# 772) */ -+ RA00_CV22, /* (# 773) */ -+ RA00_CV23, /* (# 774) */ -+ RA00_MG, /* (# 775) */ -+ RA00_MG1, /* (# 776) */ -+ RA00_MG2, /* (# 777) */ -+ RA00_MG3, /* (# 778) */ -+ RA00_MG4, /* (# 779) */ -+ RA00_MG5, /* (# 780) */ -+ RA00_MG6, /* (# 781) */ -+ RA00_MG7, /* (# 782) */ -+ RA00_MG8, /* (# 783) */ -+ RA00_MG9, /* (# 784) */ -+ RA00_MG10, /* (# 785) */ -+ RA00_MG11, /* (# 786) */ -+ RA00_MG12, /* (# 787) */ -+ RA00_MG13, /* (# 788) */ -+ RA00_MG14, /* (# 789) */ -+ RA00_MG15, /* (# 790) */ -+ RA00_MG16, /* (# 791) */ -+ RA00_MG17, /* (# 792) */ -+ RA00_MG18, /* (# 793) */ -+ RA00_MG19, /* (# 794) */ -+ RA00_MG20, /* (# 795) */ -+ RA00_MG21, /* (# 796) */ -+ RA00_MG22, /* (# 797) */ -+ RA00_MG23, /* (# 798) */ -+ RA00_SPAN, /* (# 799) */ -+ RA00_SPAN1, /* (# 800) */ -+ RA00_SPAN2, /* (# 801) */ -+ RA00_SPAN3, /* (# 802) */ -+ RA00_SPAN4, /* (# 803) */ -+ RA00_SPAN5, /* (# 804) */ -+ RA00_SPAN6, /* (# 805) */ -+ RA00_SPAN7, /* (# 806) */ -+ RA00_SPAN8, /* (# 807) */ -+ RA00_SPAN9, /* (# 808) */ -+ RA00_SPAN10, /* (# 809) */ -+ RA00_SPAN11, /* (# 810) */ -+ RA00_SPAN12, /* (# 811) */ -+ RA00_SPAN13, /* (# 812) */ -+ RA00_SPAN14, /* (# 813) */ -+ RA00_SPAN15, /* (# 814) */ -+ RA00_SPAN16, /* (# 815) */ -+ RA00_SPAN17, /* (# 816) */ -+ RA00_SPAN18, /* (# 817) */ -+ RA00_SPAN19, /* (# 818) */ -+ RA00_SPAN20, /* (# 819) */ -+ RA00_SPAN21, /* (# 820) */ -+ RA00_SPAN22, /* (# 821) */ -+ RA00_SPAN23, /* (# 822) */ -+ RA00_TXTAG, /* (# 823) */ -+ RA00_TXTAG1, /* (# 824) */ -+ RA00_TXTAG2, /* (# 825) */ -+ RA00_TXTAG3, /* (# 826) */ -+ RA00_TXTAG4, /* (# 827) */ -+ RA00_TXTAG5, /* (# 828) */ -+ RA00_TXTAG6, /* (# 829) */ -+ RA00_TXTAG7, /* (# 830) */ -+ RA00_TXTAG8, /* (# 831) */ -+ RA00_TXTAG9, /* (# 832) */ -+ RA00_TXTAG10, /* (# 833) */ -+ RA00_TXTAG11, /* (# 834) */ -+ RA00_TXTAG12, /* (# 835) */ -+ RA00_TXTAG13, /* (# 836) */ -+ RA00_TXTAG14, /* (# 837) */ -+ RA00_TXTAG15, /* (# 838) */ -+ RA00_TXTAG16, /* (# 839) */ -+ RA00_TXTAG17, /* (# 840) */ -+ RA00_TXTAG18, /* (# 841) */ -+ RA00_TXTAG19, /* (# 842) */ -+ RA00_TXTAG20, /* (# 843) */ -+ RA00_TXTAG21, /* (# 844) */ -+ RA00_TXTAG22, /* (# 845) */ -+ RA00_TXTAG23, /* (# 846) */ -+ RA00_VALID, /* (# 847) */ -+ RA00_VALID1, /* (# 848) */ -+ RA00_VALID2, /* (# 849) */ -+ RA00_VALID3, /* (# 850) */ -+ RA00_VALID4, /* (# 851) */ -+ RA00_VALID5, /* (# 852) */ -+ RA00_VALID6, /* (# 853) */ -+ RA00_VALID7, /* (# 854) */ -+ RA00_VALID8, /* (# 855) */ -+ RA00_VALID9, /* (# 856) */ -+ RA00_VALID10, /* (# 857) */ -+ RA00_VALID11, /* (# 858) */ -+ RA00_VALID12, /* (# 859) */ -+ RA00_VALID13, /* (# 860) */ -+ RA00_VALID14, /* (# 861) */ -+ RA00_VALID15, /* (# 862) */ -+ RA00_VALID16, /* (# 863) */ -+ RA00_VALID17, /* (# 864) */ -+ RA00_VALID18, /* (# 865) */ -+ RA00_VALID19, /* (# 866) */ -+ RA00_VALID20, /* (# 867) */ -+ RA00_VALID21, /* (# 868) */ -+ RA00_VALID22, /* (# 869) */ -+ RA00_VALID23, /* (# 870) */ -+ RA01_ACT, /* (# 871) */ -+ RA01_ACT1, /* (# 872) */ -+ RA01_ACT2, /* (# 873) */ -+ RA01_ACT3, /* (# 874) */ -+ RA01_ACT4, /* (# 875) */ -+ RA01_ACT5, /* (# 876) */ -+ RA01_ACT6, /* (# 877) */ -+ RA01_ACT7, /* (# 878) */ -+ RA01_ACT8, /* (# 879) */ -+ RA01_ACT9, /* (# 880) */ -+ RA01_ACT10, /* (# 881) */ -+ RA01_ACT11, /* (# 882) */ -+ RA01_ACT12, /* (# 883) */ -+ RA01_ACT13, /* (# 884) */ -+ RA01_ACT14, /* (# 885) */ -+ RA01_ACT15, /* (# 886) */ -+ RA01_ACT16, /* (# 887) */ -+ RA01_ACT17, /* (# 888) */ -+ RA01_ACT18, /* (# 889) */ -+ RA01_ACT19, /* (# 890) */ -+ RA01_ACT20, /* (# 891) */ -+ RA01_ACT21, /* (# 892) */ -+ RA01_ACT22, /* (# 893) */ -+ RA01_ACT23, /* (# 894) */ -+ RA01_CV, /* (# 895) */ -+ RA01_CV1, /* (# 896) */ -+ RA01_CV2, /* (# 897) */ -+ RA01_CV3, /* (# 898) */ -+ RA01_CV4, /* (# 899) */ -+ RA01_CV5, /* (# 900) */ -+ RA01_CV6, /* (# 901) */ -+ RA01_CV7, /* (# 902) */ -+ RA01_CV8, /* (# 903) */ -+ RA01_CV9, /* (# 904) */ -+ RA01_CV10, /* (# 905) */ -+ RA01_CV11, /* (# 906) */ -+ RA01_CV12, /* (# 907) */ -+ RA01_CV13, /* (# 908) */ -+ RA01_CV14, /* (# 909) */ -+ RA01_CV15, /* (# 910) */ -+ RA01_CV16, /* (# 911) */ -+ RA01_CV17, /* (# 912) */ -+ RA01_CV18, /* (# 913) */ -+ RA01_CV19, /* (# 914) */ -+ RA01_CV20, /* (# 915) */ -+ RA01_CV21, /* (# 916) */ -+ RA01_CV22, /* (# 917) */ -+ RA01_CV23, /* (# 918) */ -+ RA01_MG, /* (# 919) */ -+ RA01_MG1, /* (# 920) */ -+ RA01_MG2, /* (# 921) */ -+ RA01_MG3, /* (# 922) */ -+ RA01_MG4, /* (# 923) */ -+ RA01_MG5, /* (# 924) */ -+ RA01_MG6, /* (# 925) */ -+ RA01_MG7, /* (# 926) */ -+ RA01_MG8, /* (# 927) */ -+ RA01_MG9, /* (# 928) */ -+ RA01_MG10, /* (# 929) */ -+ RA01_MG11, /* (# 930) */ -+ RA01_MG12, /* (# 931) */ -+ RA01_MG13, /* (# 932) */ -+ RA01_MG14, /* (# 933) */ -+ RA01_MG15, /* (# 934) */ -+ RA01_MG16, /* (# 935) */ -+ RA01_MG17, /* (# 936) */ -+ RA01_MG18, /* (# 937) */ -+ RA01_MG19, /* (# 938) */ -+ RA01_MG20, /* (# 939) */ -+ RA01_MG21, /* (# 940) */ -+ RA01_MG22, /* (# 941) */ -+ RA01_MG23, /* (# 942) */ -+ RA01_SPAN, /* (# 943) */ -+ RA01_SPAN1, /* (# 944) */ -+ RA01_SPAN2, /* (# 945) */ -+ RA01_SPAN3, /* (# 946) */ -+ RA01_SPAN4, /* (# 947) */ -+ RA01_SPAN5, /* (# 948) */ -+ RA01_SPAN6, /* (# 949) */ -+ RA01_SPAN7, /* (# 950) */ -+ RA01_SPAN8, /* (# 951) */ -+ RA01_SPAN9, /* (# 952) */ -+ RA01_SPAN10, /* (# 953) */ -+ RA01_SPAN11, /* (# 954) */ -+ RA01_SPAN12, /* (# 955) */ -+ RA01_SPAN13, /* (# 956) */ -+ RA01_SPAN14, /* (# 957) */ -+ RA01_SPAN15, /* (# 958) */ -+ RA01_SPAN16, /* (# 959) */ -+ RA01_SPAN17, /* (# 960) */ -+ RA01_SPAN18, /* (# 961) */ -+ RA01_SPAN19, /* (# 962) */ -+ RA01_SPAN20, /* (# 963) */ -+ RA01_SPAN21, /* (# 964) */ -+ RA01_SPAN22, /* (# 965) */ -+ RA01_SPAN23, /* (# 966) */ -+ RA01_TXTAG, /* (# 967) */ -+ RA01_TXTAG1, /* (# 968) */ -+ RA01_TXTAG2, /* (# 969) */ -+ RA01_TXTAG3, /* (# 970) */ -+ RA01_TXTAG4, /* (# 971) */ -+ RA01_TXTAG5, /* (# 972) */ -+ RA01_TXTAG6, /* (# 973) */ -+ RA01_TXTAG7, /* (# 974) */ -+ RA01_TXTAG8, /* (# 975) */ -+ RA01_TXTAG9, /* (# 976) */ -+ RA01_TXTAG10, /* (# 977) */ -+ RA01_TXTAG11, /* (# 978) */ -+ RA01_TXTAG12, /* (# 979) */ -+ RA01_TXTAG13, /* (# 980) */ -+ RA01_TXTAG14, /* (# 981) */ -+ RA01_TXTAG15, /* (# 982) */ -+ RA01_TXTAG16, /* (# 983) */ -+ RA01_TXTAG17, /* (# 984) */ -+ RA01_TXTAG18, /* (# 985) */ -+ RA01_TXTAG19, /* (# 986) */ -+ RA01_TXTAG20, /* (# 987) */ -+ RA01_TXTAG21, /* (# 988) */ -+ RA01_TXTAG22, /* (# 989) */ -+ RA01_TXTAG23, /* (# 990) */ -+ RA01_VALID, /* (# 991) */ -+ RA01_VALID1, /* (# 992) */ -+ RA01_VALID2, /* (# 993) */ -+ RA01_VALID3, /* (# 994) */ -+ RA01_VALID4, /* (# 995) */ -+ RA01_VALID5, /* (# 996) */ -+ RA01_VALID6, /* (# 997) */ -+ RA01_VALID7, /* (# 998) */ -+ RA01_VALID8, /* (# 999) */ -+ RA01_VALID9, /* (# 1000) */ -+ RA01_VALID10, /* (# 1001) */ -+ RA01_VALID11, /* (# 1002) */ -+ RA01_VALID12, /* (# 1003) */ -+ RA01_VALID13, /* (# 1004) */ -+ RA01_VALID14, /* (# 1005) */ -+ RA01_VALID15, /* (# 1006) */ -+ RA01_VALID16, /* (# 1007) */ -+ RA01_VALID17, /* (# 1008) */ -+ RA01_VALID18, /* (# 1009) */ -+ RA01_VALID19, /* (# 1010) */ -+ RA01_VALID20, /* (# 1011) */ -+ RA01_VALID21, /* (# 1012) */ -+ RA01_VALID22, /* (# 1013) */ -+ RA01_VALID23, /* (# 1014) */ -+ RA02_ACT, /* (# 1015) */ -+ RA02_ACT1, /* (# 1016) */ -+ RA02_ACT2, /* (# 1017) */ -+ RA02_ACT3, /* (# 1018) */ -+ RA02_ACT4, /* (# 1019) */ -+ RA02_ACT5, /* (# 1020) */ -+ RA02_ACT6, /* (# 1021) */ -+ RA02_ACT7, /* (# 1022) */ -+ RA02_ACT8, /* (# 1023) */ -+ RA02_ACT9, /* (# 1024) */ -+ RA02_ACT10, /* (# 1025) */ -+ RA02_ACT11, /* (# 1026) */ -+ RA02_CV, /* (# 1027) */ -+ RA02_CV1, /* (# 1028) */ -+ RA02_CV2, /* (# 1029) */ -+ RA02_CV3, /* (# 1030) */ -+ RA02_CV4, /* (# 1031) */ -+ RA02_CV5, /* (# 1032) */ -+ RA02_CV6, /* (# 1033) */ -+ RA02_CV7, /* (# 1034) */ -+ RA02_CV8, /* (# 1035) */ -+ RA02_CV9, /* (# 1036) */ -+ RA02_CV10, /* (# 1037) */ -+ RA02_CV11, /* (# 1038) */ -+ RA02_MG, /* (# 1039) */ -+ RA02_MG1, /* (# 1040) */ -+ RA02_MG2, /* (# 1041) */ -+ RA02_MG3, /* (# 1042) */ -+ RA02_MG4, /* (# 1043) */ -+ RA02_MG5, /* (# 1044) */ -+ RA02_MG6, /* (# 1045) */ -+ RA02_MG7, /* (# 1046) */ -+ RA02_MG8, /* (# 1047) */ -+ RA02_MG9, /* (# 1048) */ -+ RA02_MG10, /* (# 1049) */ -+ RA02_MG11, /* (# 1050) */ -+ RA02_SPAN, /* (# 1051) */ -+ RA02_SPAN1, /* (# 1052) */ -+ RA02_SPAN2, /* (# 1053) */ -+ RA02_SPAN3, /* (# 1054) */ -+ RA02_SPAN4, /* (# 1055) */ -+ RA02_SPAN5, /* (# 1056) */ -+ RA02_SPAN6, /* (# 1057) */ -+ RA02_SPAN7, /* (# 1058) */ -+ RA02_SPAN8, /* (# 1059) */ -+ RA02_SPAN9, /* (# 1060) */ -+ RA02_SPAN10, /* (# 1061) */ -+ RA02_SPAN11, /* (# 1062) */ -+ RA02_TXTAG, /* (# 1063) */ -+ RA02_TXTAG1, /* (# 1064) */ -+ RA02_TXTAG2, /* (# 1065) */ -+ RA02_TXTAG3, /* (# 1066) */ -+ RA02_TXTAG4, /* (# 1067) */ -+ RA02_TXTAG5, /* (# 1068) */ -+ RA02_TXTAG6, /* (# 1069) */ -+ RA02_TXTAG7, /* (# 1070) */ -+ RA02_TXTAG8, /* (# 1071) */ -+ RA02_TXTAG9, /* (# 1072) */ -+ RA02_TXTAG10, /* (# 1073) */ -+ RA02_TXTAG11, /* (# 1074) */ -+ RA02_VALID, /* (# 1075) */ -+ RA02_VALID1, /* (# 1076) */ -+ RA02_VALID2, /* (# 1077) */ -+ RA02_VALID3, /* (# 1078) */ -+ RA02_VALID4, /* (# 1079) */ -+ RA02_VALID5, /* (# 1080) */ -+ RA02_VALID6, /* (# 1081) */ -+ RA02_VALID7, /* (# 1082) */ -+ RA02_VALID8, /* (# 1083) */ -+ RA02_VALID9, /* (# 1084) */ -+ RA02_VALID10, /* (# 1085) */ -+ RA02_VALID11, /* (# 1086) */ -+ RA03_ACT, /* (# 1087) */ -+ RA03_ACT1, /* (# 1088) */ -+ RA03_ACT2, /* (# 1089) */ -+ RA03_ACT3, /* (# 1090) */ -+ RA03_ACT4, /* (# 1091) */ -+ RA03_ACT5, /* (# 1092) */ -+ RA03_ACT6, /* (# 1093) */ -+ RA03_ACT7, /* (# 1094) */ -+ RA03_ACT8, /* (# 1095) */ -+ RA03_ACT9, /* (# 1096) */ -+ RA03_ACT10, /* (# 1097) */ -+ RA03_ACT11, /* (# 1098) */ -+ RA03_CV, /* (# 1099) */ -+ RA03_CV1, /* (# 1100) */ -+ RA03_CV2, /* (# 1101) */ -+ RA03_CV3, /* (# 1102) */ -+ RA03_CV4, /* (# 1103) */ -+ RA03_CV5, /* (# 1104) */ -+ RA03_CV6, /* (# 1105) */ -+ RA03_CV7, /* (# 1106) */ -+ RA03_CV8, /* (# 1107) */ -+ RA03_CV9, /* (# 1108) */ -+ RA03_CV10, /* (# 1109) */ -+ RA03_CV11, /* (# 1110) */ -+ RA03_MG, /* (# 1111) */ -+ RA03_MG1, /* (# 1112) */ -+ RA03_MG2, /* (# 1113) */ -+ RA03_MG3, /* (# 1114) */ -+ RA03_MG4, /* (# 1115) */ -+ RA03_MG5, /* (# 1116) */ -+ RA03_MG6, /* (# 1117) */ -+ RA03_MG7, /* (# 1118) */ -+ RA03_MG8, /* (# 1119) */ -+ RA03_MG9, /* (# 1120) */ -+ RA03_MG10, /* (# 1121) */ -+ RA03_MG11, /* (# 1122) */ -+ RA03_SPAN, /* (# 1123) */ -+ RA03_SPAN1, /* (# 1124) */ -+ RA03_SPAN2, /* (# 1125) */ -+ RA03_SPAN3, /* (# 1126) */ -+ RA03_SPAN4, /* (# 1127) */ -+ RA03_SPAN5, /* (# 1128) */ -+ RA03_SPAN6, /* (# 1129) */ -+ RA03_SPAN7, /* (# 1130) */ -+ RA03_SPAN8, /* (# 1131) */ -+ RA03_SPAN9, /* (# 1132) */ -+ RA03_SPAN10, /* (# 1133) */ -+ RA03_SPAN11, /* (# 1134) */ -+ RA03_TXTAG, /* (# 1135) */ -+ RA03_TXTAG1, /* (# 1136) */ -+ RA03_TXTAG2, /* (# 1137) */ -+ RA03_TXTAG3, /* (# 1138) */ -+ RA03_TXTAG4, /* (# 1139) */ -+ RA03_TXTAG5, /* (# 1140) */ -+ RA03_TXTAG6, /* (# 1141) */ -+ RA03_TXTAG7, /* (# 1142) */ -+ RA03_TXTAG8, /* (# 1143) */ -+ RA03_TXTAG9, /* (# 1144) */ -+ RA03_TXTAG10, /* (# 1145) */ -+ RA03_TXTAG11, /* (# 1146) */ -+ RA03_VALID, /* (# 1147) */ -+ RA03_VALID1, /* (# 1148) */ -+ RA03_VALID2, /* (# 1149) */ -+ RA03_VALID3, /* (# 1150) */ -+ RA03_VALID4, /* (# 1151) */ -+ RA03_VALID5, /* (# 1152) */ -+ RA03_VALID6, /* (# 1153) */ -+ RA03_VALID7, /* (# 1154) */ -+ RA03_VALID8, /* (# 1155) */ -+ RA03_VALID9, /* (# 1156) */ -+ RA03_VALID10, /* (# 1157) */ -+ RA03_VALID11, /* (# 1158) */ -+ RMON_BAS, /* (# 1159) */ -+ RMON_CAC, /* (# 1160) */ -+ RMON_COUNTER, /* (# 1161) */ -+ RMON_HIGH_COUNTER, /* (# 1162) */ -+ RMON_LOW_COUNTER, /* (# 1163) */ -+ RMON_OFFSET, /* (# 1164) */ -+ RMON_PORTC, /* (# 1165) */ -+ TYPE_FILTER_ATF, /* (# 1166) */ -+ TYPE_FILTER_ATF1, /* (# 1167) */ -+ TYPE_FILTER_ATF2, /* (# 1168) */ -+ TYPE_FILTER_ATF3, /* (# 1169) */ -+ TYPE_FILTER_ATF4, /* (# 1170) */ -+ TYPE_FILTER_ATF5, /* (# 1171) */ -+ TYPE_FILTER_ATF6, /* (# 1172) */ -+ TYPE_FILTER_ATF7, /* (# 1173) */ -+ TYPE_FILTER_QTF, /* (# 1174) */ -+ TYPE_FILTER_QTF1, /* (# 1175) */ -+ TYPE_FILTER_QTF2, /* (# 1176) */ -+ TYPE_FILTER_QTF3, /* (# 1177) */ -+ TYPE_FILTER_QTF4, /* (# 1178) */ -+ TYPE_FILTER_QTF5, /* (# 1179) */ -+ TYPE_FILTER_QTF6, /* (# 1180) */ -+ TYPE_FILTER_QTF7, /* (# 1181) */ -+ TYPE_FILTER_VCET0, /* (# 1182) */ -+ TYPE_FILTER_VCET01, /* (# 1183) */ -+ TYPE_FILTER_VCET02, /* (# 1184) */ -+ TYPE_FILTER_VCET03, /* (# 1185) */ -+ TYPE_FILTER_VCET1, /* (# 1186) */ -+ TYPE_FILTER_VCET11, /* (# 1187) */ -+ TYPE_FILTER_VCET12, /* (# 1188) */ -+ TYPE_FILTER_VCET13, /* (# 1189) */ -+ TYPE_FILTER_VCET_ALL, /* (# 1190) */ -+ TYPE_FILTER_VCET_ALL1, /* (# 1191) */ -+ TYPE_FILTER_VCET_ALL2, /* (# 1192) */ -+ TYPE_FILTER_VCET_ALL3, /* (# 1193) */ -+ TYPE_FILTER_VCET_ALL4, /* (# 1194) */ -+ TYPE_FILTER_VCET_ALL5, /* (# 1195) */ -+ TYPE_FILTER_VCET_ALL6, /* (# 1196) */ -+ TYPE_FILTER_VCET_ALL7, /* (# 1197) */ -+ VLAN_FILTER_M, /* (# 1198) */ -+ VLAN_FILTER_M1, /* (# 1199) */ -+ VLAN_FILTER_M2, /* (# 1200) */ -+ VLAN_FILTER_M3, /* (# 1201) */ -+ VLAN_FILTER_M4, /* (# 1202) */ -+ VLAN_FILTER_M5, /* (# 1203) */ -+ VLAN_FILTER_M6, /* (# 1204) */ -+ VLAN_FILTER_M7, /* (# 1205) */ -+ VLAN_FILTER_M8, /* (# 1206) */ -+ VLAN_FILTER_M9, /* (# 1207) */ -+ VLAN_FILTER_M10, /* (# 1208) */ -+ VLAN_FILTER_M11, /* (# 1209) */ -+ VLAN_FILTER_M12, /* (# 1210) */ -+ VLAN_FILTER_M13, /* (# 1211) */ -+ VLAN_FILTER_M14, /* (# 1212) */ -+ VLAN_FILTER_M15, /* (# 1213) */ -+ VLAN_FILTER_TM, /* (# 1214) */ -+ VLAN_FILTER_TM1, /* (# 1215) */ -+ VLAN_FILTER_TM2, /* (# 1216) */ -+ VLAN_FILTER_TM3, /* (# 1217) */ -+ VLAN_FILTER_TM4, /* (# 1218) */ -+ VLAN_FILTER_TM5, /* (# 1219) */ -+ VLAN_FILTER_TM6, /* (# 1220) */ -+ VLAN_FILTER_TM7, /* (# 1221) */ -+ VLAN_FILTER_TM8, /* (# 1222) */ -+ VLAN_FILTER_TM9, /* (# 1223) */ -+ VLAN_FILTER_TM10, /* (# 1224) */ -+ VLAN_FILTER_TM11, /* (# 1225) */ -+ VLAN_FILTER_TM12, /* (# 1226) */ -+ VLAN_FILTER_TM13, /* (# 1227) */ -+ VLAN_FILTER_TM14, /* (# 1228) */ -+ VLAN_FILTER_TM15, /* (# 1229) */ -+ VLAN_FILTER_VFID, /* (# 1230) */ -+ VLAN_FILTER_VFID1, /* (# 1231) */ -+ VLAN_FILTER_VFID2, /* (# 1232) */ -+ VLAN_FILTER_VFID3, /* (# 1233) */ -+ VLAN_FILTER_VFID4, /* (# 1234) */ -+ VLAN_FILTER_VFID5, /* (# 1235) */ -+ VLAN_FILTER_VFID6, /* (# 1236) */ -+ VLAN_FILTER_VFID7, /* (# 1237) */ -+ VLAN_FILTER_VFID8, /* (# 1238) */ -+ VLAN_FILTER_VFID9, /* (# 1239) */ -+ VLAN_FILTER_VFID10, /* (# 1240) */ -+ VLAN_FILTER_VFID11, /* (# 1241) */ -+ VLAN_FILTER_VFID12, /* (# 1242) */ -+ VLAN_FILTER_VFID13, /* (# 1243) */ -+ VLAN_FILTER_VFID14, /* (# 1244) */ -+ VLAN_FILTER_VFID15, /* (# 1245) */ -+ VLAN_FILTER_VID, /* (# 1246) */ -+ VLAN_FILTER_VID1, /* (# 1247) */ -+ VLAN_FILTER_VID2, /* (# 1248) */ -+ VLAN_FILTER_VID3, /* (# 1249) */ -+ VLAN_FILTER_VID4, /* (# 1250) */ -+ VLAN_FILTER_VID5, /* (# 1251) */ -+ VLAN_FILTER_VID6, /* (# 1252) */ -+ VLAN_FILTER_VID7, /* (# 1253) */ -+ VLAN_FILTER_VID8, /* (# 1254) */ -+ VLAN_FILTER_VID9, /* (# 1255) */ -+ VLAN_FILTER_VID10, /* (# 1256) */ -+ VLAN_FILTER_VID11, /* (# 1257) */ -+ VLAN_FILTER_VID12, /* (# 1258) */ -+ VLAN_FILTER_VID13, /* (# 1259) */ -+ VLAN_FILTER_VID14, /* (# 1260) */ -+ VLAN_FILTER_VID15, /* (# 1261) */ -+ VLAN_FILTER_VP, /* (# 1262) */ -+ VLAN_FILTER_VP1, /* (# 1263) */ -+ VLAN_FILTER_VP2, /* (# 1264) */ -+ VLAN_FILTER_VP3, /* (# 1265) */ -+ VLAN_FILTER_VP4, /* (# 1266) */ -+ VLAN_FILTER_VP5, /* (# 1267) */ -+ VLAN_FILTER_VP6, /* (# 1268) */ -+ VLAN_FILTER_VP7, /* (# 1269) */ -+ VLAN_FILTER_VP8, /* (# 1270) */ -+ VLAN_FILTER_VP9, /* (# 1271) */ -+ VLAN_FILTER_VP10, /* (# 1272) */ -+ VLAN_FILTER_VP11, /* (# 1273) */ -+ VLAN_FILTER_VP12, /* (# 1274) */ -+ VLAN_FILTER_VP13, /* (# 1275) */ -+ VLAN_FILTER_VP14, /* (# 1276) */ -+ VLAN_FILTER_VP15, /* (# 1277) */ -+ VLAN_FILTER_VV, /* (# 1278) */ -+ VLAN_FILTER_VV1, /* (# 1279) */ -+ VLAN_FILTER_VV2, /* (# 1280) */ -+ VLAN_FILTER_VV3, /* (# 1281) */ -+ VLAN_FILTER_VV4, /* (# 1282) */ -+ VLAN_FILTER_VV5, /* (# 1283) */ -+ VLAN_FILTER_VV6, /* (# 1284) */ -+ VLAN_FILTER_VV7, /* (# 1285) */ -+ VLAN_FILTER_VV8, /* (# 1286) */ -+ VLAN_FILTER_VV9, /* (# 1287) */ -+ VLAN_FILTER_VV10, /* (# 1288) */ -+ VLAN_FILTER_VV11, /* (# 1289) */ -+ VLAN_FILTER_VV12, /* (# 1290) */ -+ VLAN_FILTER_VV13, /* (# 1291) */ -+ VLAN_FILTER_VV14, /* (# 1292) */ -+ VLAN_FILTER_VV15, /* (# 1293) */ -+ COMMON_BIT_LATEST /* (# 1294) */ -+}IFX_ETHSW_regMapperSelector_t; -+ -+#endif /* #ifndef _IFX_ETHSW_REGMAPPERSELECTOR_H */ -diff --git a/include/switch_api/gphy_fw.h b/include/switch_api/gphy_fw.h -new file mode 100644 -index 0000000..9a9ee30 ---- /dev/null -+++ b/include/switch_api/gphy_fw.h -@@ -0,0 +1,20 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file gphy_fw.h -+ \remarks implement GPHY driver firmware on VR9 platform -+ *****************************************************************************/ -+ -+#ifndef _GPHY_FW_H_ -+#define _GPHY_FW_H_ -+ -+#define GPHY_FW_LEN (64 * 1024) -+#define GPHY_FW_LEN_D (128 * 1024) -+ -+#endif /* _GPHY_FW_H_ */ -diff --git a/include/switch_api/gphy_fw_fe.h b/include/switch_api/gphy_fw_fe.h -new file mode 100644 -index 0000000..323858c ---- /dev/null -+++ b/include/switch_api/gphy_fw_fe.h -@@ -0,0 +1,8217 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file gphy_fw_fe.h -+ \remarks implement GPHY driver firmware in VR9 platform -+ \Track bin : gphy_fw_fe.bin [ 0915-2010 ] -+ *****************************************************************************/ -+#ifndef __GPHY_IP_22F_FW__ -+#define __GPHY_IP_22F_FW__ -+ -+static const unsigned char gphy_fe_fw_data[] = { -+ 0x80, 0x4E, 0x00, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x7F, 0x54, 0xEF, 0xF9, -+ 0x80, 0x22, 0x99, 0xF5, 0x00, 0x00, 0x22, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, -+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, -+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF2, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17, 0x09, 0x02, 0x00, 0x00, 0x00, 0x81, 0x75, 0x2A, 0x0B, -+ 0x2D, 0x03, 0x02, 0xB1, 0x75, 0x07, 0x10, 0x75, 0x0E, 0x7E, 0x12, 0x11, 0x73, 0x71, 0x6C, 0x7F, -+ 0x56, 0x7F, 0x22, 0x7E, 0xF7, 0x21, 0x73, 0x71, 0xEF, 0xD1, 0x01, 0x90, 0x01, 0x90, 0xE4, 0xF0, -+ 0x80, 0x22, 0xF0, 0xCE, 0x54, 0x90, 0xE5, 0x95, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, -+ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, -+ 0xE0, 0xC0, 0x04, 0x74, 0x83, 0xC0, 0x82, 0xC0, 0xE5, 0x08, 0x04, 0x02, 0xC4, 0x0F, 0x54, 0x90, -+ 0x74, 0xE0, 0xC0, 0x03, 0xC0, 0xE0, 0xC0, 0x04, 0x02, 0x83, 0xC0, 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GPHY firmware PHY-1V5-22F-IP-VR9-A22-T4406 */ -+static const unsigned char gphy_fe_fw_data_a12 [] = { -+ 0x80, 0x41, 0x03, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x7F, 0x54, 0xEF, 0xF9, -+ 0x80, 0x22, 0x99, 0xF5, 0x00, 0x00, 0x00, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, -+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, -+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, 0x0A, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3D, 0x0C, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x50, 0x0E, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA8, 0x0E, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF5, 0x0E, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x42, 0x0F, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8F, 0x0F, -+ 0x80, 0x00, 0x00, 0x00, 0x54, 0x90, 0xE5, 0x95, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, -+ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, -+ 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -+ -+ -+#endif /*__GPHY_IP_22F_FW__ */ -diff --git a/include/switch_api/gphy_fw_ge.h b/include/switch_api/gphy_fw_ge.h -new file mode 100644 -index 0000000..a4ed0e9 ---- /dev/null -+++ b/include/switch_api/gphy_fw_ge.h -@@ -0,0 +1,8216 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file gphy_fw_ge.h -+ \remarks implement GPHY driver firmware in VR9 platform -+ \Track bin : gphy_fw_ge.bin [ 1215-2010 ] -+ *****************************************************************************/ -+#ifndef __GPHY_IP_11G_FW__ -+#define __GPHY_IP_11G_FW__ -+ -+static const unsigned char gphy_ge_fw_data[] = { -+ 0x80, 0x05, 0x03, 0x02, 0x32, 0x32, 0x32, 0x00, 0x80, 0x32, 0x32, 0x32, 0x00, 0x00, 0x32, 0xF9, -+ 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF2, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEB, -+ 0x61, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9C, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xDC, -+ 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x7C, 0xE1, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xA3, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x8D, 0x08, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0A, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x44, 0x0B, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x0B, -+ 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x86, 0x0B, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9D, -+ 0x80, 0x00, 0x00, 0x00, 0x54, 0x90, 0xE5, 0x98, 0xC0, 0x03, 0xC4, 0x0F, 0xC0, 0x04, 0x74, 0xE0, -+ 0xC0, 0x82, 0xC0, 0xE0, 0x00, 0x04, 0x02, 0x83, 0x0F, 0x54, 0x90, 0xE5, 0xE0, 0xC0, 0x03, 0xC4, -+ 0xE0, 0xC0, 0x04, 0x74, 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0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, -+}; -+ -+#endif /*__GPHY_IP_11G_FW__ */ -diff --git a/include/switch_api/ifx_ethsw.h b/include/switch_api/ifx_ethsw.h -new file mode 100644 -index 0000000..fc55000 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw.h -@@ -0,0 +1,3820 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef _IFX_ETHSW_H_ -+#define _IFX_ETHSW_H_ -+ -+#include "ifx_types.h" -+ -+/* =================================== */ -+/* Global typedef forward declarations */ -+/* =================================== */ -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+ -+/* IOCTL MAGIC */ -+#define IFX_ETHSW_MAGIC ('E') -+ -+/* Group definitions for Doxygen */ -+/** \defgroup ETHSW_IOCTL Ethernet Switch Application Interface -+ This chapter describes the entire interface for accessing and -+ configuring the services of the Ethernet switch module. Switching is done -+ based on the physical and virtual ports. */ -+/*@{*/ -+ -+/** \defgroup ETHSW_IOCTL_BRIDGE Ethernet Bridging Functions -+ Ethernet bridging (or switching) is the basic task of the device. It -+ provides individual configurations per port and standard global -+ switch features. -+*/ -+/** \defgroup ETHSW_IOCTL_VLAN VLAN Functions -+ This chapter describes VLAN bridging functionality. -+*/ -+/** \defgroup ETHSW_IOCTL_MULTICAST Multicast Functions -+ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, -+ MLDv1, and MLDv2. -+*/ -+/** \defgroup ETHSW_IOCTL_OAM Operation, Administration, and Management Functions -+ This chapter summarizes the functions that are provided to monitor the -+ data traffic passing through the device. -+*/ -+/** \defgroup ETHSW_IOCTL_QOS Quality of Service Functions -+ Switch and port configuration for Quality of Service (QoS). -+*/ -+ -+/*@}*/ -+ -+/* -------------------------------------------------------------------------- */ -+/* Structure and Enumeration Type Defintions */ -+/* -------------------------------------------------------------------------- */ -+ -+/** \addtogroup ETHSW_IOCTL_BRIDGE */ -+/*@{*/ -+ -+/** MAC Address Field Size. -+ Number of bytes used to store MAC address information. */ -+#define IFX_MAC_ADDRESS_LENGTH 6 -+ -+/** MAC Table Entry to be read. -+ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ. */ -+typedef struct -+{ -+ /** Restart the get operation from the beginning of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation got all last valid entries of the -+ table. This boolean parameter is set by the switch API -+ when the Switch API is called after the last valid one was returned already. */ -+ IFX_boolean_t bLast; -+ /** Get the MAC table entry belonging to the given Filtering Identifier (FID) -+ (not supported by all switches). */ -+ IFX_uint32_t nFId; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint32_t nPortId; -+ /** Aging Time, given in multiples of 1 second in a range from 1 s to 1,000,000 s. -+ The value read back in a GET command might differ slightly from the value -+ given in the SET command due to limited hardware timing resolution. -+ Filled out by the switch API implementation. */ -+ IFX_int32_t nAgeTimer; -+ /** Static Entry (value will be aged out after 'nAgeTimer' if the entry -+ is not set to static). */ -+ IFX_boolean_t bStaticEntry; -+ /** MAC Address. Filled out by the switch API implementation. */ -+ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; -+}IFX_ETHSW_MAC_tableRead_t; -+ -+/** Search for a MAC address entry in the address table. -+ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY. */ -+typedef struct -+{ -+ /** MAC Address. This parameter needs to be provided for the search operation. -+ This is an input parameter. */ -+ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; -+ /** Get the MAC table entry belonging to the given Filtering Identifier (FID) -+ (not supported by all switches). -+ This is an input parameter. */ -+ IFX_uint32_t nFId; -+ /** MAC Address Found. Switch API sets this boolean variable in case -+ the requested MAC address 'nMAC' is found inside the address table, -+ otherwise it is set to FALSE. -+ This is an output parameter. */ -+ IFX_boolean_t bFound; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint32_t nPortId; -+ /** Aging Time, given in multiples of 1 second in a range from 1 s to 1,000,000 s. -+ The value read back in a GET command might differ slightly from the value -+ given in the SET command due to limited hardware timing resolution. -+ Filled out by the switch API implementation. -+ This is an output parameter. */ -+ IFX_int32_t nAgeTimer; -+ /** Static Entry (value will be aged out after 'nAgeTimer' if the entry -+ is not set to static). -+ This is an output parameter. */ -+ IFX_boolean_t bStaticEntry; -+}IFX_ETHSW_MAC_tableQuery_t; -+ -+/** MAC Table Entry to be added. -+ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD. */ -+typedef struct -+{ -+ /** Filtering Identifier (FID) (not supported by all switches) */ -+ IFX_uint32_t nFId; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint32_t nPortId; -+ /** Aging Time, given in multiples of 1 second in a range -+ from 1 s to 1,000,000 s. -+ The configured value might be rounded that it fits to the given hardware platform. */ -+ IFX_int32_t nAgeTimer; -+ /** Static Entry (value will be aged out if the entry is not set to static). The -+ switch API implementation uses the maximum age timer in case the entry -+ is not static. */ -+ IFX_boolean_t bStaticEntry; -+ /** Egress queue traffic class. -+ The queue index starts counting from zero. */ -+ IFX_uint8_t nTrafficClass; -+ /** MAC Address to add to the table. */ -+ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; -+}IFX_ETHSW_MAC_tableAdd_t; -+ -+/** MAC Table Entry to be removed. -+ Used by \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE. */ -+typedef struct -+{ -+ /** Filtering Identifier (FID) (not supported by all switches) */ -+ IFX_uint32_t nFId; -+ /** MAC Address to be removed from the table. */ -+ IFX_uint8_t nMAC[IFX_MAC_ADDRESS_LENGTH]; -+}IFX_ETHSW_MAC_tableRemove_t; -+ -+/** Packet forwarding. -+ Used by \ref IFX_ETHSW_STP_BPDU_Rule_t and \ref IFX_ETHSW_multicastSnoopCfg_t -+ and \ref IFX_ETHSW_8021X_EAPOL_Rule_t. */ -+typedef enum -+{ -+ /** Default; portmap is determined by the forwarding classification. */ -+ IFX_ETHSW_PORT_FORWARD_DEFAULT = 0, -+ /** Discard; discard packets. */ -+ IFX_ETHSW_PORT_FORWARD_DISCARD = 1, -+ /** Forward to the CPU port. This requires that the CPU port is previously -+ set by calling \ref IFX_ETHSW_CPU_PORT_CFG_SET. */ -+ IFX_ETHSW_PORT_FORWARD_CPU = 2, -+ /** Forward to a port, selected by the parameter 'nForwardPortId'. -+ Please note that this feature is not supported by all -+ hardware platforms. */ -+ IFX_ETHSW_PORT_FORWARD_PORT = 3 -+}IFX_ETHSW_portForward_t; -+ -+/** Spanning Tree Protocol port states. -+ Used by \ref IFX_ETHSW_STP_portCfg_t. */ -+typedef enum -+{ -+ /** Forwarding state. The port is allowed to transmit and receive -+ all packets. Address Learning is allowed. */ -+ IFX_ETHSW_STP_PORT_STATE_FORWARD = 0, -+ /** Disabled/Discarding state. The port entity will not transmit -+ and receive any packets. Learning is disabled in this state. */ -+ IFX_ETHSW_STP_PORT_STATE_DISABLE = 1, -+ /** Learning state. The port entity will only transmit and receive -+ Spanning Tree Protocol packets (BPDU). All other packets are discarded. -+ MAC table address learning is enabled for all good frames. */ -+ IFX_ETHSW_STP_PORT_STATE_LEARNING = 2, -+ /** Blocking/Listening. Only the Spanning Tree Protocol packets will -+ be received and transmitted. All other packets are discarded by -+ the port entity. MAC table address learning is disabled in this -+ state. */ -+ IFX_ETHSW_STP_PORT_STATE_BLOCKING = 3 -+}IFX_ETHSW_STP_PortState_t; -+ -+/** Configures the Spanning Tree Protocol state of an Ethernet port. -+ Used by \ref IFX_ETHSW_STP_PORT_CFG_SET -+ and \ref IFX_ETHSW_STP_PORT_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Spanning Tree Protocol state of the port. */ -+ IFX_ETHSW_STP_PortState_t ePortState; -+}IFX_ETHSW_STP_portCfg_t; -+ -+/** Spanning tree packet detection and forwarding. -+ Used by \ref IFX_ETHSW_STP_BPDU_RULE_SET -+ and \ref IFX_ETHSW_STP_BPDU_RULE_GET. */ -+typedef struct -+{ -+ /** Filter spanning tree packets and forward them, discard them or -+ disable the filter. */ -+ IFX_ETHSW_portForward_t eForwardPort; -+ /** Target port for forwarded packets; only used if selected by -+ 'eForwardPort'. Forwarding is done -+ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ -+ IFX_uint8_t nForwardPortId; -+}IFX_ETHSW_STP_BPDU_Rule_t; -+ -+/** Describes the 802.1x port state. -+ Used by \ref IFX_ETHSW_8021X_portCfg_t. */ -+typedef enum -+{ -+ /** Receive and transmit direction are authorized. The port is allowed to -+ transmit and receive all packets and the address learning process is -+ also allowed. */ -+ IFX_ETHSW_8021X_PORT_STATE_AUTHORIZED = 0, -+ /** Receive and transmit direction are unauthorized. All the packets -+ except EAPOL are not allowed to transmit and receive. The address learning -+ process is disabled. */ -+ IFX_ETHSW_8021X_PORT_STATE_UNAUTHORIZED = 1, -+ /** Receive direction is authorized, transmit direction is unauthorized. -+ The port is allowed to receive all packets. Packet transmission to this -+ port is not allowed. The address learning process is also allowed. */ -+ IFX_ETHSW_8021X_PORT_STATE_RX_AUTHORIZED = 2, -+ /** Transmit direction is authorized, receive direction is unauthorized. -+ The port is allowed to transmit all packets. Packet reception on this -+ port is not allowed. The address learning process is disabled. */ -+ IFX_ETHSW_8021X_PORT_STATE_TX_AUTHORIZED = 3 -+}IFX_ETHSW_8021X_portState_t; -+ -+/** EAPOL frames filtering rule parameter. -+ Used by \ref IFX_ETHSW_8021X_EAPOL_RULE_GET -+ and \ref IFX_ETHSW_8021X_EAPOL_RULE_SET. */ -+typedef struct -+{ -+ /** Filter authentication packets and forward them, discard them or -+ disable the filter. */ -+ IFX_ETHSW_portForward_t eForwardPort; -+ /** Target port for forwarded packets, only used if selected by -+ 'eForwardPort'. Forwarding is done -+ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ -+ IFX_uint8_t nForwardPortId; -+}IFX_ETHSW_8021X_EAPOL_Rule_t; -+ -+/** 802.1x port authentication status. -+ Used by \ref IFX_ETHSW_8021X_PORT_CFG_GET -+ and \ref IFX_ETHSW_8021X_PORT_CFG_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint32_t nPortId; -+ /** 802.1x state of the port. */ -+ IFX_ETHSW_8021X_portState_t eState; -+}IFX_ETHSW_8021X_portCfg_t; -+ -+/*@}*/ /* ETHSW_IOCTL_BRIDGE */ -+ -+/** \addtogroup ETHSW_IOCTL_VLAN */ -+/*@{*/ -+ -+/** VLAN port configuration for ingress packet filtering. Tagged packet and -+ untagged packet can be configured to be accepted or dropped (filtered out). -+ Used by \ref IFX_ETHSW_VLAN_portCfg_t. */ -+typedef enum -+{ -+ /** Admit all. Tagged and untagged packets are allowed. */ -+ IFX_ETHSW_VLAN_ADMIT_ALL = 0, -+ /** Untagged packets only (not supported yet). Tagged packets are dropped. */ -+ IFX_ETHSW_VLAN_ADMIT_UNTAGGED = 1, -+ /** Tagged packets only. Untagged packets are dropped. */ -+ IFX_ETHSW_VLAN_ADMIT_TAGGED = 2 -+}IFX_ETHSW_VLAN_Admit_t; -+ -+/** Add a VLAN ID group to the VLAN hardware table of the switch. -+ Used by \ref IFX_ETHSW_VLAN_ID_CREATE. */ -+typedef struct -+{ -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+ /** Filtering Identifier (FID) (not supported by all switches). */ -+ IFX_uint32_t nFId; -+}IFX_ETHSW_VLAN_IdCreate_t; -+ -+/** Read out the VLAN ID to FID assignment. The user provides the VLAN ID -+ parameter and the switch APi returns the FID parameter. -+ Used by \ref IFX_ETHSW_VLAN_ID_GET. */ -+typedef struct -+{ -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+ /** Filtering Identifier (FID) (not supported by all switches). */ -+ IFX_uint32_t nFId; -+}IFX_ETHSW_VLAN_IdGet_t; -+ -+/** Remove a VLAN ID from the switch VLAN table. -+ Used by \ref IFX_ETHSW_VLAN_ID_DELETE. */ -+typedef struct -+{ -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+}IFX_ETHSW_VLAN_IdDelete_t; -+ -+/** Adds a VLAN to a port and set its egress filter information. -+ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. */ -+typedef struct -+{ -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint8_t nPortId; -+ /** Tag Member Egress. Enable egress tag-based support. -+ If enabled, all port egress traffic -+ from this VLAN group carries a VLAN group tag. */ -+ IFX_boolean_t bVLAN_TagEgress; -+}IFX_ETHSW_VLAN_portMemberAdd_t; -+ -+/** Remove the VLAN configuration from an Ethernet port. -+ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. */ -+typedef struct -+{ -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. -+ If the selected VLAN ID is not found in the vLAN table, -+ an error code is delivered. */ -+ IFX_uint16_t nVId; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint8_t nPortId; -+}IFX_ETHSW_VLAN_portMemberRemove_t; -+ -+/** Read the VLAN port membership table. -+ Used by \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ. */ -+typedef struct -+{ -+ /** Restart the get operation from the start of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This parameter is always reset -+ during the read operation. This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation got all last valid entries of the -+ table. This boolean parameter is set by the switch API -+ when the Switch API is called after the last valid one was returned already. */ -+ IFX_boolean_t bLast; -+ /** VLAN ID. The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+ /** Ethernet Port number (zero-based counting). Every bit represents -+ an Ethernet port. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint32_t nPortId; -+ /** Enable egress tag-Portmap. Every bit represents an Ethernet port. -+ This field is used as portmap field, and the MSB bit is -+ statically always set. LSB represents Port 0 with -+ incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ All port egress traffic from this VLAN group carries a -+ VLAN group tag, in case the port bit is set. -+ -+ \remarks -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint32_t nTagId; -+}IFX_ETHSW_VLAN_portMemberRead_t; -+ -+/** Port configuration for VLAN member violation. -+ Used by \ref IFX_ETHSW_VLAN_portCfg_t. */ -+typedef enum -+{ -+ /** No VLAN member violation. Ingress and egress packets violating the -+ membership pass and are not filtered out. */ -+ IFX_ETHSW_VLAN_MEMBER_VIOLATION_NO = 0, -+ /** VLAN member violation for ingress packets. Ingress packets violating -+ the membership are filtered out. Egress packets violating the -+ membership are not filtered out. */ -+ IFX_ETHSW_VLAN_MEMBER_VIOLATION_INGRESS = 1, -+ /** VLAN member violation for egress packets. Egress packets violating -+ the membership are filtered out. Ingress packets violating the -+ membership are not filtered out.*/ -+ IFX_ETHSW_VLAN_MEMBER_VIOLATION_EGRESS = 2, -+ /** VLAN member violation for ingress and egress packets. -+ Ingress and egress packets violating the membership are filtered out. */ -+ IFX_ETHSW_VLAN_MEMBER_VIOLATION_BOTH = 3 -+}IFX_ETHSW_VLAN_MemberViolation_t; -+ -+/** VLAN Port Configuration. -+ Used by \ref IFX_ETHSW_VLAN_PORT_CFG_GET -+ and \ref IFX_ETHSW_VLAN_PORT_CFG_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Port VLAN ID (PVID). The software shall ensure that the used VLAN has -+ been configured in advance on the hardware by -+ using \ref IFX_ETHSW_VLAN_ID_CREATE. */ -+ IFX_uint16_t nPortVId; -+ /** Drop ingress VLAN-tagged packets if the VLAN ID -+ is not listed in the active VLAN set. If disabled, all incoming -+ VLAN-tagged packets are forwarded using the FID tag members and -+ the port members of the PVID. */ -+ IFX_boolean_t bVLAN_UnknownDrop; -+ /** Reassign all ingress VLAN tagged packets to the port-based -+ VLAN ID (PVID). */ -+ IFX_boolean_t bVLAN_ReAssign; -+ /** VLAN ingress and egress membership violation mode. Allows admittance of -+ VLAN-tagged packets where the port is not a member of the VLAN ID -+ carried in the received and sent packet. */ -+ IFX_ETHSW_VLAN_MemberViolation_t eVLAN_MemberViolation; -+ /** Ingress VLAN-tagged or untagged packet filter configuration. */ -+ IFX_ETHSW_VLAN_Admit_t eAdmitMode; -+ /** Transparent VLAN Mode (TVM). All packets are handled as untagged -+ packets. Any existing tag is ignored and treated as packet payload. */ -+ IFX_boolean_t bTVM; -+}IFX_ETHSW_VLAN_portCfg_t; -+ -+/** This VLAN configuration supports replacing of the VID of received packets -+ with the PVID of the receiving port. -+ Used by \ref IFX_ETHSW_VLAN_RESERVED_ADD -+ and \ref IFX_ETHSW_VLAN_RESERVED_REMOVE. */ -+typedef struct -+{ -+ /** VID of the received packet to be replaced by the PVID. -+ The valid range is from 0 to 4095. -+ An error code is delivered in case of range mismatch. */ -+ IFX_uint16_t nVId; -+}IFX_ETHSW_VLAN_reserved_t; -+ -+/*@}*/ /* ETHSW_IOCTL_VLAN */ -+ -+/** \addtogroup ETHSW_IOCTL_QOS */ -+/*@{*/ -+ -+/** DSCP mapping table. -+ Used by \ref IFX_ETHSW_QOS_DSCP_CLASS_SET -+ and \ref IFX_ETHSW_QOS_DSCP_CLASS_GET. */ -+typedef struct -+{ -+ /** Traffic class associated with a particular DSCP value. -+ DSCP is the index to an array of resulting traffic class values. -+ The index starts counting from zero. */ -+ IFX_uint8_t nTrafficClass[64]; -+}IFX_ETHSW_QoS_DSCP_ClassCfg_t; -+ -+/** Traffic class associated with a particular 802.1P (PCP) priority mapping value. -+ This table is global for the entire switch device. Priority map entry structure. -+ Used by \ref IFX_ETHSW_QOS_PCP_CLASS_SET -+ and \ref IFX_ETHSW_QOS_PCP_CLASS_GET. */ -+typedef struct -+{ -+ /** Configures the PCP to traffic class mapping. -+ The queue index starts counting from zero. */ -+ IFX_uint8_t nTrafficClass[8]; -+}IFX_ETHSW_QoS_PCP_ClassCfg_t; -+ -+/** Ingress DSCP remarking attribute. This attribute defines on the -+ ingress port packets how these will be remarked on the egress port. -+ A packet is only remarked in case its ingress and its egress port -+ have remarking enabled. -+ Used by \ref IFX_ETHSW_QoS_portRemarkingCfg_t. */ -+typedef enum -+{ -+ /** No DSCP Remarking. No remarking is done on the egress port. */ -+ IFX_ETHSW_DSCP_REMARK_DISABLE = 0, -+ /** TC DSCP 6-Bit Remarking. The complete DSCP remarking is done based -+ on the traffic class. The traffic class to DSCP value mapping is -+ given in a device global table. */ -+ IFX_ETHSW_DSCP_REMARK_TC6 = 1, -+ /** TC DSCP 3-Bit Remarking. The upper 3-Bits of the DSCP field are -+ remarked based on the traffic class. The traffic class to DSCP value -+ mapping is given in a device global table. */ -+ IFX_ETHSW_DSCP_REMARK_TC3 = 2, -+ /** Drop Precedence Remarking. The Drop Precedence is remarked on the -+ egress side. */ -+ IFX_ETHSW_DSCP_REMARK_DP3 = 3, -+ /** TC Drop Precedence Remarking. The Drop Precedence is remarked on the -+ egress side and the upper 3-Bits of the DSCP field are -+ remarked based on the traffic class. The traffic class to DSCP value -+ mapping is given in a device global table. */ -+ IFX_ETHSW_DSCP_REMARK_DP3_TC3 = 4 -+}IFX_ETHSW_Qos_ingressRemarking_t; -+ -+/** Port Remarking Configuration. Ingress and Egress remarking options for -+ DSCP and PCP. Remarking is done either on the used traffic class or -+ the drop precedence. -+ Used by \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET -+ and \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Ingress DSCP Remarking. Specifies on ingress side how a packet should -+ be remarked. This DSCP remarking only works in case remarking is -+ enabled on the egress port. -+ This configuration requires that remarking is also enabled on the -+ egress port. DSCP remarking enable on either ingress or egress port -+ side does not perform any remark operation. */ -+ IFX_ETHSW_Qos_ingressRemarking_t eDSCP_IngressRemarkingEnable; -+ /** Egress DSCP Remarking. Applies remarking on egress packets in a -+ fashion as specified on the ingress port. This ingress port remarking -+ is configured by the parameter 'eDSCP_IngressRemarking'. -+ This configuration requires that remarking is also enabled on the -+ ingress port. DSCP remarking enable on either ingress or egress port -+ side does not perform any remark operation. */ -+ IFX_boolean_t bDSCP_EgressRemarkingEnable; -+ /** Ingress PCP Remarking. Applies remarking to all port ingress packets. -+ This configuration requires that remarking is also enabled on the -+ egress port. PCP remarking enable on either ingress or egress port -+ side does not perform any remark operation. */ -+ IFX_boolean_t bPCP_IngressRemarkingEnable; -+ /** Egress PCP Remarking. Applies remarking for all port egress packets. -+ This configuration requires that remarking is also enabled on the -+ ingress port. PCP remarking enable on either ingress or egress port -+ side does not perform any remark operation. */ -+ IFX_boolean_t bPCP_EgressRemarkingEnable; -+}IFX_ETHSW_QoS_portRemarkingCfg_t; -+ -+/** Traffic class to DSCP mapping table. -+ Used by \ref IFX_ETHSW_QOS_CLASS_DSCP_SET -+ and \ref IFX_ETHSW_QOS_CLASS_DSCP_GET. */ -+typedef struct -+{ -+ /** DSCP value (6-bit) associated with a particular Traffic class. -+ Traffic class is the index to an array of resulting DSCP values. -+ The index starts counting from zero. */ -+ IFX_uint8_t nDSCP[16]; -+}IFX_ETHSW_QoS_ClassDSCP_Cfg_t; -+ -+/** Traffic class associated with a particular 802.1P (PCP) priority mapping value. -+ This table is global for the entire switch device. Priority map entry structure. -+ Used by \ref IFX_ETHSW_QOS_CLASS_PCP_SET -+ and \ref IFX_ETHSW_QOS_CLASS_PCP_GET. */ -+typedef struct -+{ -+ /** Configures the traffic class to PCP (3-bit) mapping. -+ The queue index starts counting from zero. */ -+ IFX_uint8_t nPCP[16]; -+}IFX_ETHSW_QoS_ClassPCP_Cfg_t; -+ -+/** DSCP Drop Precedence to color code assignment. -+ Used by \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. */ -+typedef enum -+{ -+ /** Critical Packet. Metering never changes the drop precedence of these packets. */ -+ IFX_ETHSW_DROP_PRECEDENCE_CRITICAL = 0, -+ /** Green Drop Precedence Packet. Packet is marked with a 'low' drop precedence. */ -+ IFX_ETHSW_DROP_PRECEDENCE_GREEN = 1, -+ /** Yellow Drop Precedence Packet. Packet is marked with a 'middle' drop precedence. */ -+ IFX_ETHSW_DROP_PRECEDENCE_YELLOW = 2, -+ /** Red Drop Precedence Packet. Packet is marked with a 'high' drop precedence. */ -+ IFX_ETHSW_DROP_PRECEDENCE_RED = 3 -+}IFX_ETHSW_QoS_DropPrecedence_t; -+ -+/** DSCP to Drop Precedence assignment table configuration. -+ Used by \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET -+ and \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET. */ -+typedef struct -+{ -+ /** DSCP to drop precedence assignment. Every array entry represents the -+ drop precedence for one of the 64 existing DSCP values. -+ DSCP is the index to an array of resulting drop precedence values. -+ The index starts counting from zero. */ -+ IFX_ETHSW_QoS_DropPrecedence_t nDSCP_DropPrecedence[64]; -+}IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t; -+ -+/** Selection of the traffic class field. -+ Used by \ref IFX_ETHSW_QoS_portCfg_t. */ -+typedef enum -+{ -+ /** No traffic class assignment based on DSCP or PCP */ -+ IFX_ETHSW_QOS_CLASS_SELECT_NO = 0, -+ /** Traffic class assignment based on DSCP. PCP information is ignored. -+ The Port Class is used in case DSCP is not available in the packet. */ -+ IFX_ETHSW_QOS_CLASS_SELECT_DSCP = 1, -+ /** Traffic class assignment based on PCP. DSCP information is ignored. -+ The Port Class is used in case PCP is not available in the packet. */ -+ IFX_ETHSW_QOS_CLASS_SELECT_PCP = 2, -+ /** Traffic class assignment based on DSCP. Make the assignment based on -+ PCP in case the DSCP information is not available in the packet header. -+ The Port Class is used in case both are not available in the packet. */ -+ IFX_ETHSW_QOS_CLASS_SELECT_DSCP_PCP = 3, -+ /** Traffic class assignment based on PCP. Make the assignment based on -+ DSCP in case the PCP information is not available in the packet header. -+ The Port Class is used in case both are not available in the packet. */ -+ IFX_ETHSW_QOS_CLASS_SELECT_PCP_DSCP = 4 -+}IFX_ETHSW_QoS_ClassSelect_t; -+ -+/** Describes which priority information of ingress packets is used -+ (taken into account) to identify the packet priority and the related egress -+ priority queue. For DSCP, the priority to queue assignment is done -+ using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. For VLAN, the priority to queue -+ assignment is done using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. -+ Used by \ref IFX_ETHSW_QOS_PORT_CFG_SET -+ and \ref IFX_ETHSW_QOS_PORT_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Select the packet header field on which to base the traffic class assignment. */ -+ IFX_ETHSW_QoS_ClassSelect_t eClassMode; -+ /** Default port priority in case no other priority -+ (such as VLAN-based PCP or IP-based DSCP) is used. */ -+ IFX_uint8_t nTrafficClass; -+}IFX_ETHSW_QoS_portCfg_t; -+ -+/** Configures a rate shaper instance with the rate and the burst size. -+ Used by \ref IFX_ETHSW_QOS_SHAPER_CFG_SET -+ and \ref IFX_ETHSW_QOS_SHAPER_CFG_GET. */ -+typedef struct -+{ -+ /** Rate shaper index (zero-based counting). */ -+ IFX_uint32_t nRateShaperId; -+ /** Enable/Disable the rate shaper. */ -+ IFX_boolean_t bEnable; -+ /** Committed Burst Size (CBS [bytes]) */ -+ IFX_uint32_t nCbs; -+ /** Rate [kbit/s] */ -+ IFX_uint32_t nRate; -+}IFX_ETHSW_QoS_ShaperCfg_t; -+ -+/** Assign one rate shaper instance to a QoS queue. -+ Used by \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN -+ and \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN. */ -+typedef struct -+{ -+ /** Rate shaper index (zero-based counting). */ -+ IFX_uint8_t nRateShaperId; -+ /** QoS queue index (zero-based counting). */ -+ IFX_uint8_t nQueueId; -+}IFX_ETHSW_QoS_ShaperQueue_t; -+ -+/** Retrieve if a rate shaper instance is assigned to a QoS egress queue. -+ Used by \ref IFX_ETHSW_QOS_SHAPER_QUEUE_GET. */ -+typedef struct -+{ -+ /** QoS queue index (zero-based counting). -+ This parameter is the input parameter for the GET function. */ -+ IFX_uint8_t nQueueId; -+ /** Rate shaper instance assigned. -+ If IFX_TRUE, a rate shaper instance is assigned to the queue. Otherwise no shaper instance is assigned. */ -+ IFX_boolean_t bAssigned; -+ /** Rate shaper index (zero-based counting). Only a valid instance is returned in case 'bAssigned == IFX_TRUE'. */ -+ IFX_uint8_t nRateShaperId; -+}IFX_ETHSW_QoS_ShaperQueueGet_t; -+ -+/** Drop Probability Profile. Defines the drop probability profile. -+ Used by \ref IFX_ETHSW_QoS_WRED_Cfg_t. */ -+typedef enum -+{ -+ /** Pmin = 25%, Pmax = 75% (default) */ -+ IFX_ETHSW_QOS_WRED_PROFILE_P0 = 0, -+ /** Pmin = 25%, Pmax = 50% */ -+ IFX_ETHSW_QOS_WRED_PROFILE_P1 = 1, -+ /** Pmin = 50%, Pmax = 50% */ -+ IFX_ETHSW_QOS_WRED_PROFILE_P2 = 2, -+ /** Pmin = 50%, Pmax = 75% */ -+ IFX_ETHSW_QOS_WRED_PROFILE_P3 = 3 -+}IFX_ETHSW_QoS_WRED_Profile_t; -+ -+/** Configures the global probability profile of the device. -+ The min. and max. values are given in number of packet -+ buffer segments. The size of a segment can be -+ retrieved using \ref IFX_ETHSW_CAP_GET. -+ Used by \ref IFX_ETHSW_QOS_WRED_CFG_SET -+ and \ref IFX_ETHSW_QOS_WRED_CFG_GET. */ -+typedef struct -+{ -+ /** Drop Probability Profile. */ -+ IFX_ETHSW_QoS_WRED_Profile_t eProfile; -+ /** WRED Red Threshold Min [number of segments]. */ -+ IFX_uint32_t nRed_Min; -+ /** WRED Red Threshold Max [number of segments]. */ -+ IFX_uint32_t nRed_Max; -+ /** WRED Yellow Threshold Min [number of segments]. */ -+ IFX_uint32_t nYellow_Min; -+ /** WRED Yellow Threshold Max [number of segments]. */ -+ IFX_uint32_t nYellow_Max; -+ /** WRED Green Threshold Min [number of segments]. */ -+ IFX_uint32_t nGreen_Min; -+ /** WRED Green Threshold Max [number of segments]. */ -+ IFX_uint32_t nGreen_Max; -+}IFX_ETHSW_QoS_WRED_Cfg_t; -+ -+/** Configures the WRED threshold parameter. -+ The min. and max. values are given in number of packet -+ buffer segments. The size of a segment can be -+ retrieved using \ref IFX_ETHSW_CAP_GET. -+ Used by \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET -+ and \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET. */ -+typedef struct -+{ -+ /** QoS queue index (zero-based counting). */ -+ IFX_uint32_t nQueueId; -+ /** WRED Red Threshold Min [number of segments]. */ -+ IFX_uint32_t nRed_Min; -+ /** WRED Red Threshold Max [number of segments]. */ -+ IFX_uint32_t nRed_Max; -+ /** WRED Yellow Threshold Min [number of segments]. */ -+ IFX_uint32_t nYellow_Min; -+ /** WRED Yellow Threshold Max [number of segments]. */ -+ IFX_uint32_t nYellow_Max; -+ /** WRED Green Threshold Min [number of segments]. */ -+ IFX_uint32_t nGreen_Min; -+ /** WRED Green Threshold Max [number of segments]. */ -+ IFX_uint32_t nGreen_Max; -+}IFX_ETHSW_QoS_WRED_QueueCfg_t; -+ -+/** Configures the parameters of a rate meter instance. -+ Used by \ref IFX_ETHSW_QOS_METER_CFG_SET -+ and \ref IFX_ETHSW_QOS_METER_CFG_GET. */ -+typedef struct -+{ -+ /** Enable/Disable the meter shaper. */ -+ IFX_boolean_t bEnable; -+ /** Meter index (zero-based counting). */ -+ IFX_uint32_t nMeterId; -+ /** Committed Burst Size (CBS [Bytes]). */ -+ IFX_uint32_t nCbs; -+ /** Excess Burst Size (EBS [Bytes]). */ -+ IFX_uint32_t nEbs; -+ /** Rate [kbit/s] */ -+ IFX_uint32_t nRate; -+}IFX_ETHSW_QoS_meterCfg_t; -+ -+/** Specifies the direction for ingress and egress. -+ Used by \ref IFX_ETHSW_QoS_meterPort_t -+ and \ref IFX_ETHSW_QoS_meterPortGet_t. */ -+typedef enum -+{ -+ /** No direction. */ -+ IFX_ETHSW_DIRECTION_NONE = 0, -+ /** Ingress direction. */ -+ IFX_ETHSW_DIRECTION_INGRESS = 1, -+ /** Egress direction. */ -+ IFX_ETHSW_DIRECTION_EGRESS = 2, -+ /** Ingress and egress direction. */ -+ IFX_ETHSW_DIRECTION_BOTH = 3 -+}IFX_ETHSW_direction_t; -+ -+/** Assign a rate meter instance to an ingress and/or egress port. -+ Used by \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN -+ and \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN. */ -+typedef struct -+{ -+ /** Meter index (zero-based counting). */ -+ IFX_uint32_t nMeterId; -+ /** Port assignment. Could be either ingress, egress or both. Setting it to -+ 'IFX_ETHSW_DIRECTION_NONE' would remove the queue for any port -+ assignment. */ -+ IFX_ETHSW_direction_t eDir; -+ /** Ingress Port Id. */ -+ IFX_uint32_t nPortIngressId; -+ /** Egress Port Id. */ -+ IFX_uint32_t nPortEgressId; -+}IFX_ETHSW_QoS_meterPort_t; -+ -+/** Reads out all meter instance to port assignments. -+ Used by \ref IFX_ETHSW_QOS_METER_PORT_GET. */ -+typedef struct -+{ -+ /** Restart the get operation from the start of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation got all last valid entries of the -+ table. This boolean parameter is set by the switch API -+ when the Switch API is called after the last valid one was returned already. */ -+ IFX_boolean_t bLast; -+ /** Port assignment. Could be either ingress, egress or both. Setting it to -+ 'IFX_ETHSW_DIRECTION_NONE' would remove the queue for any port -+ assignment. */ -+ IFX_ETHSW_direction_t eDir; -+ /** Meter index (zero-based counting). */ -+ IFX_uint8_t nMeterId; -+ /** Ingress Port Id. */ -+ IFX_uint8_t nPortIngressId; -+ /** Egress Port Id. */ -+ IFX_uint8_t nPortEgressId; -+}IFX_ETHSW_QoS_meterPortGet_t; -+ -+/** Assigns one meter instances for storm control. -+ Used by \ref IFX_ETHSW_QOS_STORM_CFG_SET and \ref IFX_ETHSW_QOS_STORM_CFG_GET. */ -+typedef struct -+{ -+ /** Meter index 0 (zero-based counting). */ -+ IFX_int32_t nMeterId; -+ /** Meter instances used for broadcast traffic. */ -+ IFX_boolean_t bBroadcast; -+ /** Meter instances used for multicast traffic. */ -+ IFX_boolean_t bMulticast; -+ /** Meter instances used for unknown unicast traffic. */ -+ IFX_boolean_t bUnknownUnicast; -+}IFX_ETHSW_QoS_stormCfg_t; -+ -+/** Select the type of the egress queue scheduler. -+ Used by \ref IFX_ETHSW_QoS_schedulerCfg_t. */ -+typedef enum -+{ -+ /** Strict Priority. */ -+ IFX_ETHSW_QOS_SCHEDULER_STRICT = 0, -+ /** Weighted Fair Queuing. */ -+ IFX_ETHSW_QOS_SCHEDULER_WFQ = 1 -+}IFX_ETHSW_QoS_Scheduler_t; -+ -+/** Configures the egress queues attached to a single port, and that -+ are scheduled to transmit the queued Ethernet packets. -+ Used by \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET -+ and \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET. */ -+typedef struct -+{ -+ /** QoS queue index (zero-based counting). */ -+ IFX_uint8_t nQueueId; -+ /** Scheduler Type (Strict Priority/Weighted Fair Queuing). */ -+ IFX_ETHSW_QoS_Scheduler_t eType; -+ /** Weight in Token. Parameter used for WFQ configuration. -+ Sets the weight in token in relation to all remaining -+ queues on this egress port having WFQ configuration. -+ This parameter is only used -+ when 'eType=IFX_ETHSW_QOS_SCHEDULER_WFQ'. */ -+ IFX_uint32_t nWeight; -+}IFX_ETHSW_QoS_schedulerCfg_t; -+ -+/** Sets the Queue ID for one traffic class of one port. -+ Used by \ref IFX_ETHSW_QOS_QUEUE_PORT_SET -+ and \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ This is an input parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ -+ IFX_uint8_t nPortId; -+ /** Traffic Class index (zero-based counting). -+ This is an input parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ -+ IFX_uint8_t nTrafficClassId; -+ /** QoS queue index (zero-based counting). -+ This is an output parameter for \ref IFX_ETHSW_QOS_QUEUE_PORT_GET. */ -+ IFX_uint8_t nQueueId; -+}IFX_ETHSW_QoS_queuePort_t; -+ -+/*@}*/ /* ETHSW_IOCTL_QOS */ -+ -+/** \addtogroup ETHSW_IOCTL_MULTICAST */ -+/*@{*/ -+ -+/** Define setting the priority queue to an undefined value. -+ This disables the priority feature. */ -+#define IFX_ETHSW_TRAFFIC_CLASS_DISABLE 0xFF -+ -+/** Configure the IGMP snooping mode. -+ Used by \ref IFX_ETHSW_multicastSnoopCfg_t. */ -+typedef enum -+{ -+ /** IGMP management packet snooping and multicast level 3 table learning -+ is disabled. */ -+ IFX_ETHSW_MULTICAST_SNOOP_MODE_DISABLED = 0, -+ /** IGMP management packet snooping is enabled and used for the hardware -+ auto-learning to fill the multicast level 3 table. */ -+ IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING = 1, -+ /** IGMP management packet snooping is enabled and forwarded to the -+ configured port. No autolearning of the multicast level 3 table. This -+ table has to be maintained by the management software. */ -+ IFX_ETHSW_MULTICAST_SNOOP_MODE_FORWARD = 2 -+}IFX_ETHSW_multicastSnoopMode_t; -+ -+/** Configure the IGMP report suppression mode. -+ Used by \ref IFX_ETHSW_multicastSnoopCfg_t. */ -+typedef enum -+{ -+ /** Report Suppression and Join Aggregation. */ -+ IFX_ETHSW_MULTICAST_REPORT_JOIN = 0, -+ /** Report Suppression. No Join Aggregation. */ -+ IFX_ETHSW_MULTICAST_REPORT = 1, -+ /** Transparent Mode. No Report Suppression and no Join Aggregation. */ -+ IFX_ETHSW_MULTICAST_TRANSPARENT = 2 -+}IFX_ETHSW_multicastReportSuppression_t; -+ -+/** Configure the switch multicast configuration. -+ Used by \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET -+ and \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET. */ -+typedef struct -+{ -+ /** Enables and configures the IGMP/MLD snooping feature. -+ Select autolearning or management packet forwarding mode. -+ Packet forwarding is done to the port selected in 'eForwardPort'. */ -+ IFX_ETHSW_multicastSnoopMode_t eIGMP_Mode; -+ /** IGMPv3 hardware support. -+ When enabled the IGMP table includes both the group table and -+ the source list table. Otherwise the table only includes the -+ group table. This feature is needed when supporting IGMPv3 and -+ MLDv2 protocols. */ -+ IFX_boolean_t bIGMPv3; -+ /** Enables snooped IGMP control packets treated as cross-VLAN packets. This -+ parameter is used for hardware auto-learning and snooping packets -+ forwarded to a dedicated port. This dedicated port can be selected -+ over 'eForwardPort'. */ -+ IFX_boolean_t bCrossVLAN; -+ /** Forward snooped packet, only used if forwarded mode -+ is selected -+ by 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. */ -+ IFX_ETHSW_portForward_t eForwardPort; -+ /** Target port for forwarded packets, only used if selected by -+ 'eForwardPort'. Forwarding is done -+ if 'eForwardPort = IFX_ETHSW_PORT_FORWARD_PORT'. */ -+ IFX_uint8_t nForwardPortId; -+ /** Snooping control class of service. -+ Snooping control packet can be forwarded to the 'nForwardPortId' when -+ selected in 'eIGMP_Mode'. The class of service of this port can be -+ selected for the snooped control packets, starting from zero. -+ The maximum possible service class depends -+ on the hardware platform used. The value -+ IFX_ETHSW_TRAFFIC_CLASS_DISABLE disables overwriting the given -+ class assignment. */ -+ IFX_uint8_t nClassOfService; -+ /** Robustness variable. -+ Used when the hardware-based IGMP/MLD snooping function is enabled. This -+ robust variable is used in case IGMP hardware learning is -+ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). -+ Supported range: 1 ... 3 */ -+ IFX_uint8_t nRobust; -+ /** Query interval. -+ Used to define the query interval in units of 100 ms when the -+ hardware-based IGMP/MLD snooping function is enabled. -+ The automatically learned router port will be aged out if no IGMP/MLD -+ query frame is received from the router port -+ for (nQueryInterval * nRobust) seconds. -+ The supported range is from 100 ms to 25.5 s, with a default value -+ of 10 s. This query interval is used in case IGMP hardware learning is -+ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ -+ IFX_uint8_t nQueryInterval; -+ /** IGMP/MLD report suppression and Join Aggregation control. -+ Whenever the report message is already sent out for the same multicast -+ group, the successive report message within the -+ query-max-responsetime with the same group ID will be filtered -+ by the switch. This is called report suppression. -+ Whenever the join message is already sent out for the same multicast -+ group, the successive join message with the same group ID will be filtered. -+ This is called join aggregation. This suppression control is used in -+ case IGMP hardware learning is -+ enable ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ -+ IFX_ETHSW_multicastReportSuppression_t eSuppressionAggregation; -+ /** Hardware IGMP snooping fast leave option. -+ Allows the hardware to automatically clear the membership -+ when receiving the IGMP leave packet. This -+ fast leave option is used in case IGMP hardware learning is -+ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). -+ Note: The fast-leave option shall only be enabled where only -+ one host is connected to each interface. -+ If fast-leave is enabled where more than one host is connected -+ to an interface, some hosts might be dropped inadvertently. -+ Fast-leave processing is supported only with IGMP version 2 hosts. */ -+ IFX_boolean_t bFastLeave; -+ /** Hardware router port auto-learning. Allows for the -+ ports on which a router is located to be learned automatically. This router port learning option is -+ used in case IGMP hardware learning is -+ enabled ('eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_AUTOLEARNING'). */ -+ IFX_boolean_t bLearningRouter; -+}IFX_ETHSW_multicastSnoopCfg_t; -+ -+/** Add an Ethernet port as router port to the switch hardware multicast table. -+ Used by \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD -+ and \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint8_t nPortId; -+}IFX_ETHSW_multicastRouter_t; -+ -+/** Check if a port has been selected as a router port. -+ Used by \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ. */ -+typedef struct -+{ -+ /** Restart the get operation from the start of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This parameter is always reset -+ during the read operation. This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation got all last valid entries of the -+ table. This boolean parameter is set by the switch API -+ when the Switch API is called after the last valid one was returned already. */ -+ IFX_boolean_t bLast; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+}IFX_ETHSW_multicastRouterRead_t; -+ -+/** This is a union to describe the IPv4 and IPv6 parameter. -+ Used by \ref IFX_ETHSW_multicastTable_t -+ and \ref IFX_ETHSW_multicastTableRead_t. */ -+typedef union -+{ -+ /** Describe the IPv4 address. -+ Only used if the IPv4 address should be read or configured. -+ Cannot be used together with the IPv6 address fields. */ -+ IFX_uint32_t nIPv4; -+ /** Describe the IPv6 address. -+ Only used if the IPv6 address should be read or configured. -+ Cannot be used together with the IPv4 address fields. */ -+ IFX_uint16_t nIPv6[8]; -+}IFX_ETHSW_IP_t; -+ -+/** Selection to use IPv4 or IPv6. -+ Used by \ref IFX_ETHSW_multicastTable_t -+ and \ref IFX_ETHSW_multicastTableRead_t. */ -+typedef enum -+{ -+ /** IPv4 */ -+ IFX_ETHSW_IP_SELECT_IPV4 = 0, -+ /** IPv6 */ -+ IFX_ETHSW_IP_SELECT_IPV6 = 1 -+}IFX_ETHSW_IP_Select_t; -+ -+/** Defines the multicast group member mode. -+ Used by \ref IFX_ETHSW_multicastTable_t -+ and \ref IFX_ETHSW_multicastTableRead_t. */ -+typedef enum -+{ -+ /** Include source IP address membership mode. -+ Only supported for IGMPv3. */ -+ IFX_ETHSW_IGMP_MEMBER_INCLUDE = 0, -+ /** Exclude source IP address membership mode. -+ Only supported for IGMPv3. */ -+ IFX_ETHSW_IGMP_MEMBER_EXCLUDE = 1, -+ /** Group source IP address is 'don't care'. This means all source IP -+ addresses (*) are included for the multicast group membership. -+ This is the default mode for IGMPv1 and IGMPv2. */ -+ IFX_ETHSW_IGMP_MEMBER_DONT_CARE = 2 -+}IFX_ETHSW_IGMP_MemberMode_t; -+ -+/** Add a host as a member to a multicast group. -+ Used by \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD and \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Select the IP version of the 'uIP_Gda' and 'uIP_Gsa' fields. -+ Both fields support either IPv4 or IPv6. */ -+ IFX_ETHSW_IP_Select_t eIPVersion; -+ /** Group Destination IP address (GDA). */ -+ IFX_ETHSW_IP_t uIP_Gda; -+ /** Group Source IP address. Only used in case IGMPv3 support is enabled -+ and 'eModeMember != IFX_ETHSW_IGMP_MEMBER_DONT_CARE'. */ -+ IFX_ETHSW_IP_t uIP_Gsa; -+ /** Group member filter mode. -+ This parameter is ignored when deleting a multicast membership table entry. -+ The configurations 'IFX_ETHSW_IGMP_MEMBER_EXCLUDE' -+ and 'IFX_ETHSW_IGMP_MEMBER_INCLUDE' are only supported -+ if IGMPv3 is used. */ -+ IFX_ETHSW_IGMP_MemberMode_t eModeMember; -+}IFX_ETHSW_multicastTable_t; -+ -+/** Read out the multicast membership table. -+ Used by \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ. */ -+typedef struct -+{ -+ /** Restart the get operation from the beginning of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This parameter is always reset -+ during the read operation. This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation got all last valid entries of the -+ table. This boolean parameter is set by the switch API -+ when the Switch API is called after the last valid one was returned already. */ -+ IFX_boolean_t bLast; -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. -+ -+ \remarks -+ This field is used as portmap field, when the MSB bit is set. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. -+ The macro \ref IFX_ETHSW_PORTMAP_FLAG_SET allows to set the MSB bit, -+ marking it as portmap variable. -+ Checking the portmap flag can be done by -+ using the \ref IFX_ETHSW_PORTMAP_FLAG_GET macro. */ -+ IFX_uint8_t nPortId; -+ /** Select the IP version of the 'uIP_Gda' and 'uIP_Gsa' fields. -+ Both fields support either IPv4 or IPv6. */ -+ IFX_ETHSW_IP_Select_t eIPVersion; -+ /** Group Destination IP address (GDA). */ -+ IFX_ETHSW_IP_t uIP_Gda; -+ /** Group Source IP address. Only used in case IGMPv3 support is enabled. */ -+ IFX_ETHSW_IP_t uIP_Gsa; -+ /** Group member filter mode. -+ This parameter is ignored when deleting a multicast membership table entry. -+ The configurations 'IFX_ETHSW_IGMP_MEMBER_EXCLUDE' -+ and 'IFX_ETHSW_IGMP_MEMBER_INCLUDE' are only supported -+ if IGMPv3 is used. */ -+ IFX_ETHSW_IGMP_MemberMode_t eModeMember; -+}IFX_ETHSW_multicastTableRead_t; -+ -+/*@}*/ /* ETHSW_IOCTL_MULTICAST */ -+ -+/** \addtogroup ETHSW_IOCTL_OAM */ -+/*@{*/ -+ -+/** Maximum version information string length. */ -+#define IFX_ETHSW_VERSION_LEN 64 -+ -+/** Maximum String Length for the Capability String. */ -+#define IFX_ETHSW_CAP_STRING_LEN 128 -+ -+/** Sets the portmap flag of a PortID variable. -+ Some Switch API commands allow to use a port index as portmap variable. -+ This requires that the MSB bit is set to indicate that this variable -+ contains a portmap, instead of a port index. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. */ -+#define IFX_ETHSW_PORTMAP_FLAG_SET(varType) (1 << ( sizeof(((varType *)0)->nPortId) * 8 - 1)) -+ -+/** Checks the portmap flag of a PortID variable. -+ Some Switch API commands allow to use a port index as portmap variable. -+ This requires that the MSB bit is set to indicate that this variable -+ contains a portmap, instead of a port index. -+ In portmap mode, every value bit represents an Ethernet port. -+ LSB represents Port 0 with incrementing counting. -+ The (MSB - 1) bit represent the last port. */ -+#define IFX_ETHSW_PORTMAP_FLAG_GET(varType) (1 << ( sizeof(((varType *)0)->nPortId) * 8 - 1)) -+ -+/** Data structure used to request the Switch API and device hardware -+ version information. A zero-based index is provided to the Switch API that -+ describes the request version information. -+ Used by \ref IFX_ETHSW_VERSION_GET. */ -+typedef struct -+{ -+ /** Version ID starting with 0. */ -+ IFX_uint16_t nId; -+ /** Name or ID of the version information. */ -+ IFX_char_t cName[IFX_ETHSW_VERSION_LEN]; -+ /** Version string information. */ -+ IFX_char_t cVersion[IFX_ETHSW_VERSION_LEN]; -+}IFX_ETHSW_version_t; -+ -+/** Switch API hardware initialization mode. -+ Used by \ref IFX_ETHSW_HW_Init_t. */ -+typedef enum -+{ -+ /** Access the switch hardware to read out status and capability -+ information. Then define the basic hardware configuration to bring -+ the hardware into a pre-defined state. */ -+ IFX_ETHSW_HW_INIT_WR = 0, -+ /** Access the switch hardware to read out status and capability -+ information. Do not write any hardware configuration to the device. -+ This means that the current existing hardware configuration remains -+ unchanged. */ -+ IFX_ETHSW_HW_INIT_RO = 1, -+ /** Initialize the switch software module but do not touch the switch -+ hardware. This means that no read or write operations are done on -+ the switch hardware. Status and capability information cannot be -+ retrieved from the hardware. */ -+ IFX_ETHSW_HW_INIT_NO = 2 -+}IFX_ETHSW_HW_InitMode_t; -+ -+/** Switch hardware platform initialization structure. -+ Used by \ref IFX_ETHSW_HW_INIT. */ -+typedef struct -+{ -+ /** Select the type of Switch API and hardware initialization. */ -+ IFX_ETHSW_HW_InitMode_t eInitMode; -+}IFX_ETHSW_HW_Init_t; -+ -+/** Aging Timer Value. -+ Used by \ref IFX_ETHSW_cfg_t. */ -+typedef enum -+{ -+ /** 1 second */ -+ IFX_ETHSW_AGETIMER_1_SEC = 1, -+ /** 10 seconds */ -+ IFX_ETHSW_AGETIMER_10_SEC = 2, -+ /** 300 seconds */ -+ IFX_ETHSW_AGETIMER_300_SEC = 3, -+ /** 1 hour */ -+ IFX_ETHSW_AGETIMER_1_HOUR = 4, -+ /** 24 hours */ -+ IFX_ETHSW_AGETIMER_1_DAY = 5 -+}IFX_ETHSW_ageTimer_t; -+ -+/** Ethernet port speed mode. -+ A port might support only a subset of the possible settings. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** 10 Mbit/s */ -+ IFX_ETHSW_PORT_SPEED_10 = 10, -+ /** 100 Mbit/s */ -+ IFX_ETHSW_PORT_SPEED_100 = 100, -+ /** 200 Mbit/s */ -+ IFX_ETHSW_PORT_SPEED_200 = 200, -+ /** 1000 Mbit/s */ -+ IFX_ETHSW_PORT_SPEED_1000 = 1000 -+}IFX_ETHSW_portSpeed_t; -+ -+/** Ethernet port duplex status. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** Port operates in full-duplex mode */ -+ IFX_ETHSW_DUPLEX_FULL = 0, -+ /** Port operates in half-duplex mode */ -+ IFX_ETHSW_DUPLEX_HALF = 1 -+}IFX_ETHSW_portDuplex_t; -+ -+/** Force the MAC and PHY link modus. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** Link up. Any connected LED -+ still behaves based on the real PHY status. */ -+ IFX_ETHSW_PORT_LINK_UP = 0, -+ /** Link down. */ -+ IFX_ETHSW_PORT_LINK_DOWN = 1 -+}IFX_ETHSW_portLink_t; -+ -+/** Enumeration used for phone capability types. -+ Used by \ref IFX_ETHSW_cap_t. */ -+typedef enum -+{ -+ /** Number of physical Ethernet ports. */ -+ IFX_ETHSW_CAP_TYPE_PORT = 0, -+ /** Number of virtual Ethernet ports. */ -+ IFX_ETHSW_CAP_TYPE_VIRTUAL_PORT = 1, -+ /** Size of internal packet memory [in Bytes]. */ -+ IFX_ETHSW_CAP_TYPE_BUFFER_SIZE = 2, -+ /** Buffer segment size. -+ Byte size of a segment, used to store received packet data. */ -+ IFX_ETHSW_CAP_TYPE_SEGMENT_SIZE = 3, -+ /** Number of priority queues per device. */ -+ IFX_ETHSW_CAP_TYPE_PRIORITY_QUEUE = 4, -+ /** Number of meter instances. */ -+ IFX_ETHSW_CAP_TYPE_METER = 5, -+ /** Number of rate shaper instances. */ -+ IFX_ETHSW_CAP_TYPE_RATE_SHAPER = 6, -+ /** Number of VLAN groups that can be configured on the switch hardware. */ -+ IFX_ETHSW_CAP_TYPE_VLAN_GROUP = 7, -+ /** Number of Filtering Identifiers (FIDs) */ -+ IFX_ETHSW_CAP_TYPE_FID = 8, -+ /** Number of MAC table entries */ -+ IFX_ETHSW_CAP_TYPE_MAC_TABLE_SIZE = 9, -+ /** Number of multicast level 3 hardware table entries */ -+ IFX_ETHSW_CAP_TYPE_MULTICAST_TABLE_SIZE = 10, -+ /** Number of supported PPPoE sessions. */ -+ IFX_ETHSW_CAP_TYPE_PPPOE_SESSION = 11, -+ /** Last Capability Index */ -+ IFX_ETHSW_CAP_TYPE_LAST = 12 -+} IFX_ETHSW_capType_t; -+ -+/** Capability structure. -+ Used by \ref IFX_ETHSW_CAP_GET. */ -+typedef struct -+{ -+ /** Defines the capability type, see \ref IFX_ETHSW_capType_t.*/ -+ IFX_ETHSW_capType_t nCapType; -+ /** Description of the capability. */ -+ IFX_char_t cDesc[IFX_ETHSW_CAP_STRING_LEN]; -+ /** Defines if, what or how many are available. The definition of cap -+ depends on the type, see captype. */ -+ IFX_uint32_t nCap; -+} IFX_ETHSW_cap_t; -+ -+/** Global switch configuration. -+ Used by \ref IFX_ETHSW_CFG_SET and \ref IFX_ETHSW_CFG_GET. */ -+typedef struct -+{ -+ /** MAC table aging timer. After this timer expires the MAC table -+ entry is aged out. */ -+ IFX_ETHSW_ageTimer_t eMAC_TableAgeTimer; -+ /** VLAN Awareness. The switch is VLAN unaware if this variable is disabled. -+ In this mode, no VLAN-related APIs are supported and return with an error. -+ The existing VLAN configuration is discarded when VLAN is disabled again. */ -+ IFX_boolean_t bVLAN_Aware; -+ /** Maximum Ethernet packet length. */ -+ IFX_uint16_t nMaxPacketLen; -+ /** Automatic MAC address table learning limitation consecutive action. -+ These frame addresses are not learned, but there exists control as to whether -+ the frame is still forwarded or dropped. -+ -+ - IFX_FALSE: Drop -+ - IFX_TRUE: Forward -+ */ -+ IFX_boolean_t bLearningLimitAction; -+ /** Pause frame MAC source address mode. If enabled, use the alternative -+ address specified with 'nMAC'. */ -+ IFX_boolean_t bPauseMAC_ModeSrc; -+ /** Pause frame MAC source address. */ -+ IFX_uint8_t nPauseMAC_Src[IFX_MAC_ADDRESS_LENGTH]; -+}IFX_ETHSW_cfg_t; -+ -+/** Port Enable Options. -+ Used by \ref IFX_ETHSW_portCfg_t. */ -+typedef enum -+{ -+ /** The port is disabled in both directions. */ -+ IFX_ETHSW_PORT_DISABLE = 0, -+ /** The port is enabled in both directions (ingress and egress). */ -+ IFX_ETHSW_PORT_ENABLE_RXTX = 1, -+ /** The port is enabled in the receive (ingress) direction only. */ -+ IFX_ETHSW_PORT_ENABLE_RX = 2, -+ /** The port is enabled in the transmit (egress) direction only. */ -+ IFX_ETHSW_PORT_ENABLE_TX = 3 -+}IFX_ETHSW_portEnable_t; -+ -+/** Port Mirror Options. -+ Used by \ref IFX_ETHSW_portCfg_t. */ -+typedef enum -+{ -+ /** Mirror Feature is disabled. Normal port usage. */ -+ IFX_ETHSW_PORT_MONITOR_NONE = 0, -+ /** Port Ingress packets are mirrored to the monitor port. */ -+ IFX_ETHSW_PORT_MONITOR_RX = 1, -+ /** Port Egress packets are mirrored to the monitor port. */ -+ IFX_ETHSW_PORT_MONITOR_TX = 2, -+ /** Port Ingress and Egress packets are mirrored to the monitor port. */ -+ IFX_ETHSW_PORT_MONITOR_RXTX = 3, -+ /** Packet mirroring of 'unknown VLAN violation' frames. */ -+ IFX_ETHSW_PORT_MONITOR_VLAN_UNKNOWN = 4, -+ /** Packet mirroring of 'VLAN ingress or egress membership violation' frames. */ -+ IFX_ETHSW_PORT_MONITOR_VLAN_MEMBERSHIP = 16, -+ /** Packet mirroring of 'port state violation' frames. */ -+ IFX_ETHSW_PORT_MONITOR_PORT_STATE = 32, -+ /** Packet mirroring of 'MAC learning limit violation' frames. */ -+ IFX_ETHSW_PORT_MONITOR_LEARNING_LIMIT = 64, -+ /** Packet mirroring of 'port lock violation' frames. */ -+ IFX_ETHSW_PORT_MONITOR_PORT_LOCK = 128 -+}IFX_ETHSW_portMonitor_t; -+ -+/** Ethernet flow control status. -+ Used by \ref IFX_ETHSW_portCfg_t. */ -+typedef enum -+{ -+ /** Automatic flow control mode selection through auto-negotiation. */ -+ IFX_ETHSW_FLOW_AUTO = 0, -+ /** Receive flow control only */ -+ IFX_ETHSW_FLOW_RX = 1, -+ /** Transmit flow control only */ -+ IFX_ETHSW_FLOW_TX = 2, -+ /** Receive and Transmit flow control */ -+ IFX_ETHSW_FLOW_RXTX = 3, -+ /** No flow control */ -+ IFX_ETHSW_FLOW_OFF = 4 -+}IFX_ETHSW_portFlow_t; -+ -+/** Port Configuration. -+ Used by \ref IFX_ETHSW_PORT_CFG_GET and \ref IFX_ETHSW_PORT_CFG_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Enable Port (ingress only, egress only, both directions, or disabled). -+ This parameter is used for Spanning Tree Protocol and 802.1X applications. */ -+ IFX_ETHSW_portEnable_t eEnable; -+ /** Drop unknown unicast packets. -+ Do not send out unknown unicast packets on this port, -+ if the boolean parameter is enabled. By default packets of this type -+ are forwarded to this port. */ -+ IFX_boolean_t bUnicastUnknownDrop; -+ /** Drop unknown multicast packets. -+ Do not send out unknown multicast packets on this port, -+ if boolean parameter is enabled. By default packets of this type -+ are forwarded to this port. */ -+ IFX_boolean_t bMulticastUnknownDrop; -+ /** Drop reserved packet types -+ (destination address from '01 80 C2 00 00 00' to -+ '01 80 C2 00 00 2F') received on this port. */ -+ IFX_boolean_t bReservedPacketDrop; -+ /** Drop Broadcast packets received on this port. By default packets of this -+ type are forwarded to this port. */ -+ IFX_boolean_t bBroadcastDrop; -+ /** Enables MAC address table aging. -+ The MAC table entries learned on this port are removed after the -+ aging time has expired. -+ The aging time is a global parameter, common to all ports. */ -+ IFX_boolean_t bAging; -+ /** Automatic MAC address table learning locking on the port specified -+ by 'nPortId'. */ -+ IFX_boolean_t bLearningMAC_PortLock; -+ /** Automatic MAC address table learning limitation on this port. -+ The learning functionality is disabled when the limit value is zero. -+ The value 0xFFFF to allow unlimited learned address. */ -+ IFX_uint16_t nLearningLimit; -+ /** Port Flow Control Status. Enables the flow control function. */ -+ IFX_ETHSW_portFlow_t eFlowCtrl; -+ /** Port monitor feature. Allows forwarding of egress and/or ingress -+ packets to the monitor port. If enabled, the monitor port gets -+ a copy of the selected packet type. */ -+ IFX_ETHSW_portMonitor_t ePortMonitor; -+}IFX_ETHSW_portCfg_t; -+ -+/** Special tag Ethertype mode */ -+typedef enum -+{ -+ /** The EtherType field of the Special Tag of egress packets is always set -+ to a prefined value. This same defined value applies for all -+ switch ports. */ -+ IFX_ETHSW_CPU_ETHTYPE_PREDEFINED = 0, -+ /** The Ethertype field of the Special Tag of egress packets is set to -+ the FlowID parameter, which is a results of the switch flow -+ classification result. The switch flow table rule provides this -+ FlowID as action parameter. */ -+ IFX_ETHSW_CPU_ETHTYPE_FLOWID = 1 -+}IFX_ETHSW_CPU_SpecialTagEthType_t; -+ -+/** Defines one port that is directly connected to the software running on a CPU. -+ Used by \ref IFX_ETHSW_CPU_PORT_CFG_SET and \ref IFX_ETHSW_CPU_PORT_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** CPU port validity. -+ Set command: set true to define a CPU port, set false to undo the setting. -+ Get command: true if defined as CPU, false if not defined as CPU port. */ -+ IFX_boolean_t bCPU_PortValid; -+ /** Special tag enable in ingress direction. */ -+ IFX_boolean_t bSpecialTagIngress; -+ /** Special tag enable in egress direction. */ -+ IFX_boolean_t bSpecialTagEgress; -+ /** Enable FCS check -+ -+ - IFX_FALSE: No check, forward all frames -+ - IFX_TRUE: Check FCS, drop frames with errors -+ */ -+ IFX_boolean_t bFcsCheck; -+ /** Enable FCS generation -+ -+ - IFX_FALSE: Forward packets without FCS -+ - IFX_TRUE: Generate FCS for all frames -+ */ -+ IFX_boolean_t bFcsGenerate; -+ /** Special tag Ethertype mode. */ -+ IFX_ETHSW_CPU_SpecialTagEthType_t bSpecialTagEthType; -+}IFX_ETHSW_CPU_PortCfg_t; -+ -+/** Ethernet layer-2 header selector, when adding or removing on -+ transmitted packets. -+ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ -+typedef enum -+{ -+ /** No additional Ethernet header. */ -+ IFX_ETHSW_CPU_HEADER_NO = 0, -+ /** Additional Ethernet header. */ -+ IFX_ETHSW_CPU_HEADER_MAC = 1, -+ /** Additional Ethernet- and VLAN- header. */ -+ IFX_ETHSW_CPU_HEADER_VLAN = 2 -+}IFX_ETHSW_CPU_HeaderMode_t; -+ -+/** CPU Port Layer-2 Header extension. -+ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ -+typedef struct -+{ -+ /** Packet MAC Source Address. */ -+ IFX_uint8_t nMAC_Src[IFX_MAC_ADDRESS_LENGTH]; -+ /** Packet MAC Destination Address. */ -+ IFX_uint8_t nMAC_Dst[IFX_MAC_ADDRESS_LENGTH]; -+ /** Packet EtherType Field. */ -+ IFX_uint16_t nEthertype; -+ /** VLAN Tag Priority Field. -+ Only used when adding VLAN tag is -+ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ -+ IFX_uint8_t nVLAN_Prio; -+ /** VLAN Tag Canonical Format Identifier. -+ Only used when adding VLAN tag is -+ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ -+ IFX_uint8_t nVLAN_CFI; -+ /** VLAN Tag VLAN ID. -+ Only used when adding VLAN tag is -+ enabled (eHeaderAdd=IFX_ETHSW_CPU_HEADER_VLAN). */ -+ IFX_uint16_t nVLAN_ID; -+}IFX_ETHSW_CPU_Header_t; -+ -+/** CPU port PAUSE frame handling. -+ Used by \ref IFX_ETHSW_CPU_PortExtendCfg_t. */ -+typedef enum -+{ -+ /** Forward all PAUSE frames coming from the switch macro towards -+ the DMA channel. These frames do not influence the packet transmission. */ -+ IFX_ETHSW_CPU_PAUSE_FORWARD = 0, -+ /** Dispatch all PAUSE frames coming from the switch macro towards -+ the DMA channel. These are filtered out and the packets transmission is -+ stopped and restarted accordingly. */ -+ IFX_ETHSW_CPU_PAUSE_DISPATCH = 1 -+}IFX_ETHSW_CPU_Pause_t; -+ -+/** Ethernet port interface mode. -+ A port might support only a subset of the possible settings. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** Normal PHY interface (twisted pair), use the internal MII Interface. */ -+ IFX_ETHSW_PORT_HW_MII = 0, -+ /** Reduced MII interface in normal mode. */ -+ IFX_ETHSW_PORT_HW_RMII = 1, -+ /** GMII or MII, depending upon the speed. */ -+ IFX_ETHSW_PORT_HW_GMII = 2, -+ /** RGMII mode. */ -+ IFX_ETHSW_PORT_HW_RGMII = 3 -+}IFX_ETHSW_MII_Mode_t; -+ -+/** Ethernt port configuration for PHY or MAC mode. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** MAC Mode. The Ethernet port is configured to work in MAC mode. */ -+ IFX_ETHSW_PORT_MAC = 0, -+ /** PHY Mode. The Ethernet port is configured to work in PHY mode. */ -+ IFX_ETHSW_PORT_PHY = 1 -+}IFX_ETHSW_MII_Type_t; -+ -+/** Ethernet port clock source configuration. -+ Used by \ref IFX_ETHSW_portLinkCfg_t. */ -+typedef enum -+{ -+ /** Clock Mode not applicable. */ -+ IFX_ETHSW_PORT_CLK_NA = 0, -+ /** Clock Master Mode. The port is configured to provide the clock as output signal. */ -+ IFX_ETHSW_PORT_CLK_MASTER = 1, -+ /** Clock Slave Mode. The port is configured to use the input clock signal. */ -+ IFX_ETHSW_PORT_CLK_SLAVE = 2 -+}IFX_ETHSW_clkMode_t; -+ -+/** Additional CPU port configuration for platforms where the CPU port is -+ fixed set on a dedicated port. -+ -+ Used by \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET -+ and \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET. */ -+typedef struct -+{ -+ /** Add Ethernet layer-2 header (also VLAN) to the transmit packet. -+ The corresponding header fields are set in 'sHeader'. */ -+ IFX_ETHSW_CPU_HeaderMode_t eHeaderAdd; -+ /** Remove Ethernet layer-2 header (also VLAN) for packets going from -+ Ethernet switch to the DMA. Only the first VLAN tag found is removed -+ and additional available VLAN tags remain untouched. */ -+ IFX_boolean_t bHeaderRemove; -+ /** Ethernet layer-2 header information. Used when adding a header to the -+ transmitted packet. The parameter 'eHeaderAdd' selects the mode if -+ a layer-2 header should be added (including VLAN). -+ This structure contains all fields of the Ethernet and VLAN header. */ -+ IFX_ETHSW_CPU_Header_t sHeader; -+ /** Describes how the port handles received PAUSE frames coming from the -+ switch. Either forward them to DMA or stop/start transmission. -+ Note that the parameter 'eFlowCtrl' of the -+ command 'IFX_ETHSW_PORT_CFG_SET' determines whether the switch -+ generates PAUSE frames. */ -+ IFX_ETHSW_CPU_Pause_t ePauseCtrl; -+ /** Remove the CRC (FCS) of all packets coming from the switch towards -+ the DMA channel. -+ Note that the FCS check and generation option can be configured -+ using 'IFX_ETHSW_CPU_PORT_CFG_SET'. */ -+ IFX_boolean_t bFcsRemove; -+ /** Port map of Ethernet switch ports that are assigned to the WAN side -+ (dedicated for applications where ports are grouped into WAN- and -+ LAN- segments). All ports that are not selected belong to the LAN segment. -+ The LSB bit represents port 0, the higher bits represent the higher -+ port numbers. */ -+ IFX_uint32_t nWAN_Ports; -+}IFX_ETHSW_CPU_PortExtendCfg_t; -+ -+/** Ethernet port link, speed status and flow control status. -+ Used by \ref IFX_ETHSW_PORT_LINK_CFG_GET -+ and \ref IFX_ETHSW_PORT_LINK_CFG_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Force Port Duplex Mode. -+ -+ - IFX_FALSE: Negotiate Duplex Mode. Auto-negotiation mode. Negotiated -+ duplex mode given in 'eDuplex' -+ during IFX_ETHSW_PORT_LINK_CFG_GET calls. -+ - IFX_TRUE: Force Duplex Mode. Force duplex mode in 'eDuplex'. -+ */ -+ IFX_boolean_t bDuplexForce; -+ /** Port Duplex Status. */ -+ IFX_ETHSW_portDuplex_t eDuplex; -+ /** Force Link Speed. -+ -+ - IFX_FALSE: Negotiate Link Speed. Negotiated speed given in -+ 'eSpeed' during IFX_ETHSW_PORT_LINK_CFG_GET calls. -+ - IFX_TRUE: Force Link Speed. Forced speed mode in 'eSpeed'. -+ */ -+ IFX_boolean_t bSpeedForce; -+ /** Ethernet port link up/down and speed status. */ -+ IFX_ETHSW_portSpeed_t eSpeed; -+ /** Force Link. -+ -+ - IFX_FALSE: Auto-negotiate Link. Current link status is given in -+ 'eLink' during IFX_ETHSW_PORT_LINK_CFG_GET calls. -+ - IFX_TRUE: Force Duplex Mode. Force duplex mode in 'eLink'. -+ */ -+ IFX_boolean_t bLinkForce; -+ /** Link Status. Read out the current link status. -+ Note that the link could be forced by setting 'bLinkForce'. */ -+ IFX_ETHSW_portLink_t eLink; -+ /** Selected interface mode (MII/RMII/RGMII/GMII). */ -+ IFX_ETHSW_MII_Mode_t eMII_Mode; -+ /** Select MAC or PHY mode (PHY = Reverse xMII). */ -+ IFX_ETHSW_MII_Type_t eMII_Type; -+ /** Interface Clock mode (used for RMII mode). */ -+ IFX_ETHSW_clkMode_t eClkMode; -+ /** 'Low Power Idle' Support for 'Energy Efficient Ethernet'. -+ Only enable this feature in case the attached PHY also supports it. */ -+ IFX_boolean_t bLPI; -+}IFX_ETHSW_portLinkCfg_t; -+ -+/** Ethernet Interface RGMII Clock Configuration. Only needed in case the -+ interface runs in RGMII mode. -+ Used by \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET -+ and \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Clock Delay RX [multiple of 500 ps]. */ -+ IFX_uint8_t nDelayRx; -+ /** Clock Delay TX [multiple of 500 ps]. */ -+ IFX_uint8_t nDelayTx; -+}IFX_ETHSW_portRGMII_ClkCfg_t; -+ -+/** Query whether the Ethernet switch hardware has detected a connected -+ PHY on the port. -+ Used by \ref IFX_ETHSW_PORT_PHY_QUERY. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Check if the Ethernet switch hardware has detected a connected PHY -+ on this port. */ -+ IFX_boolean_t bPHY_Present; -+}IFX_ETHSW_portPHY_Query_t; -+ -+/** Ethernet PHY address definition. Defines the relationship between a -+ bridge port and the MDIO address of a PHY that is attached to this port. -+ Used by \ref IFX_ETHSW_PORT_PHY_ADDR_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Device address on the MDIO interface */ -+ IFX_uint8_t nAddressDev; -+}IFX_ETHSW_portPHY_Addr_t; -+ -+/** Port redirection control. -+ Used by \ref IFX_ETHSW_PORT_REDIRECT_GET -+ and \ref IFX_ETHSW_PORT_REDIRECT_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Port Redirect Option. -+ If enabled, all packets destined to 'nPortId' are redirected to the -+ CPU port. The destination port map in the status header information is -+ not changed so that the original destination port can be identified by -+ software. */ -+ IFX_boolean_t bRedirectEgress; -+ /** Port Ingress Direct Forwarding. -+ If enabled, all packets sourced from 'nPortId' are directly forwarded to queue 0 -+ of the CPU port. These packets are not modified and are not affected by -+ normal learning, look up, VLAN processing and queue selection. */ -+ IFX_boolean_t bRedirectIngress; -+}IFX_ETHSW_portRedirectCfg_t; -+ -+/** Port monitor configuration. -+ Used by \ref IFX_ETHSW_MONITOR_PORT_CFG_GET -+ and \ref IFX_ETHSW_MONITOR_PORT_CFG_SET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** This port is used as a monitor port. To use this feature, the port -+ mirror function is enabled on one or more ports. */ -+ IFX_boolean_t bMonitorPort; -+}IFX_ETHSW_monitorPortCfg_t; -+ -+/** -+ RMON Counters - Type 1. -+ This structure contains the RMON counters of one Ethernet Switch Port. -+ Used by \ref IFX_ETHSW_RMON_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. This parameter specifies for which MAC port the RMON1 -+ counter is read. It has to be set by the application before -+ calling \ref IFX_ETHSW_RMON_GET. */ -+ IFX_uint8_t nPortId; -+ /** Receive Packet Count (only packets that are accepted and not discarded). */ -+ IFX_uint32_t nRxGoodPkts; -+ /** Receive Unicast Packet Count. */ -+ IFX_uint32_t nRxUnicastPkts; -+ /** Receive Broadcast Packet Count. */ -+ IFX_uint32_t nRxBroadcastPkts; -+ /** Receive Multicast Packet Count. */ -+ IFX_uint32_t nRxMulticastPkts; -+ /** Receive FCS Error Packet Count. */ -+ IFX_uint32_t nRxFCSErrorPkts; -+ /** Receive Undersize Good Packet Count. */ -+ IFX_uint32_t nRxUnderSizeGoodPkts; -+ /** Receive Oversize Good Packet Count. */ -+ IFX_uint32_t nRxOversizeGoodPkts; -+ /** Receive Undersize Error Packet Count. */ -+ IFX_uint32_t nRxUnderSizeErrorPkts; -+ /** Receive Good Pause Packet Count. */ -+ IFX_uint32_t nRxGoodPausePkts; -+ /** Receive Oversize Error Packet Count. */ -+ IFX_uint32_t nRxOversizeErrorPkts; -+ /** Receive Align Error Packet Count. */ -+ IFX_uint32_t nRxAlignErrorPkts; -+ /** Filtered Packet Count. */ -+ IFX_uint32_t nRxFilteredPkts; -+ /** Receive Size 64 Packet Count. */ -+ IFX_uint32_t nRx64BytePkts; -+ /** Receive Size 65-127 Packet Count. */ -+ IFX_uint32_t nRx127BytePkts; -+ /** Receive Size 128-255 Packet Count. */ -+ IFX_uint32_t nRx255BytePkts; -+ /** Receive Size 256-511 Packet Count. */ -+ IFX_uint32_t nRx511BytePkts; -+ /** Receive Size 512-1023 Packet Count. */ -+ IFX_uint32_t nRx1023BytePkts; -+ /** Receive Size 1024-1522 (or more, if configured) Packet Count. */ -+ IFX_uint32_t nRxMaxBytePkts; -+ /** Transmit Packet Count. */ -+ IFX_uint32_t nTxGoodPkts; -+ /** Transmit Unicast Packet Count. */ -+ IFX_uint32_t nTxUnicastPkts; -+ /** Transmit Broadcast Packet Count. */ -+ IFX_uint32_t nTxBroadcastPkts; -+ /** Transmit Multicast Packet Count. */ -+ IFX_uint32_t nTxMulticastPkts; -+ /** Transmit Single Collision Count. */ -+ IFX_uint32_t nTxSingleCollCount; -+ /** Transmit Multiple Collision Count. */ -+ IFX_uint32_t nTxMultCollCount; -+ /** Transmit Late Collision Count. */ -+ IFX_uint32_t nTxLateCollCount; -+ /** Transmit Excessive Collision Count. */ -+ IFX_uint32_t nTxExcessCollCount; -+ /** Transmit Collision Count. */ -+ IFX_uint32_t nTxCollCount; -+ /** Transmit Pause Packet Count. */ -+ IFX_uint32_t nTxPauseCount; -+ /** Transmit Size 64 Packet Count. */ -+ IFX_uint32_t nTx64BytePkts; -+ /** Transmit Size 65-127 Packet Count. */ -+ IFX_uint32_t nTx127BytePkts; -+ /** Transmit Size 128-255 Packet Count. */ -+ IFX_uint32_t nTx255BytePkts; -+ /** Transmit Size 256-511 Packet Count. */ -+ IFX_uint32_t nTx511BytePkts; -+ /** Transmit Size 512-1023 Packet Count. */ -+ IFX_uint32_t nTx1023BytePkts; -+ /** Transmit Size 1024-1522 (or more, if configured) Packet Count. */ -+ IFX_uint32_t nTxMaxBytePkts; -+ /** Transmit Drop Packet Count. */ -+ IFX_uint32_t nTxDroppedPkts; -+ /** Transmit Dropped Packet Count, based on Congestion Management. */ -+ IFX_uint32_t nTxAcmDroppedPkts; -+ /** Receive Dropped Packet Count. */ -+ IFX_uint32_t nRxDroppedPkts; -+ /** Receive Good Byte Count (64 bit). */ -+ IFX_uint64_t nRxGoodBytes; -+ /** Receive Bad Byte Count (64 bit). */ -+ IFX_uint64_t nRxBadBytes; -+ /** Transmit Good Byte Count (64 bit). */ -+ IFX_uint64_t nTxGoodBytes; -+}IFX_ETHSW_RMON_cnt_t; -+ -+/** RMON Counter Clear. -+ This structure specifies on which port the RMON counter should be deleted. -+ Used by \ref IFX_ETHSW_RMON_CLEAR. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+}IFX_ETHSW_RMON_clear_t; -+ -+/** MDIO Interface Configuration. -+ Used by \ref IFX_ETHSW_MDIO_CFG_GET and \ref IFX_ETHSW_MDIO_CFG_SET. */ -+typedef struct -+{ -+ /** MDIO interface clock and data rate [in kHz]. */ -+ IFX_uint32_t nMDIO_Speed; -+ /** MDIO interface enable. */ -+ IFX_boolean_t bMDIO_Enable; -+}IFX_ETHSW_MDIO_cfg_t; -+ -+/** MDIO Register Access. -+ The 'nData' value is directly written to the device register -+ or read from the device. -+ Some PHY device registers have standard bit definitions as stated in -+ IEEE 802. -+ Used by \ref IFX_ETHSW_MDIO_DATA_READ and \ref IFX_ETHSW_MDIO_DATA_WRITE. */ -+typedef struct -+{ -+ /** Device address on the MDIO interface */ -+ IFX_uint8_t nAddressDev; -+ /** Register address inside the device. */ -+ IFX_uint8_t nAddressReg; -+ /** Exchange data word with the device (read / write). */ -+ IFX_uint16_t nData; -+}IFX_ETHSW_MDIO_data_t; -+ -+/** Enumeration for function status return. The upper four bits are reserved for -+ error classification */ -+typedef enum -+{ -+ IFX_ETHSW_statusOk = 0, -+ /** Invalid function parameter */ -+ IFX_ETHSW_statusParam = -2, -+ /** No space left in VLAN table */ -+ IFX_ETHSW_statusVLAN_Space = -3, -+ /** Requested VLAN ID not found in table */ -+ IFX_ETHSW_statusVLAN_ID = -4, -+ /** Invalid ioctl */ -+ IFX_ETHSW_statusInvalIoctl = -5, -+ /** Operation not supported by hardware */ -+ IFX_ETHSW_statusNoSupport = -6, -+ /** Timeout */ -+ IFX_ETHSW_statusTimeout = -7, -+ /** At least one value is out of range */ -+ IFX_ETHSW_statusValueRange = -8, -+ /** The PortId/QueueId/etc. is not available in this hardware or the -+ selected feature is not available on this port */ -+ IFX_ETHSW_statusPortInvalid = -9, -+ /** The interrupt is not available in this hardware */ -+ IFX_ETHSW_statusIRQ_Invalid = -10, -+ /** The MAC table is full, an entry could not be added */ -+ IFX_ETHSW_statusMAC_TableFull = -11, -+ /** Generic or unknown error occurred */ -+ IFX_ETHSW_statusErr = -1 -+}IFX_ETHSW_status_t; -+ -+/** Configures the Wake-on-LAN function. -+ Used by \ref IFX_ETHSW_WOL_CFG_SET and \ref IFX_ETHSW_WOL_CFG_GET. */ -+typedef struct -+{ -+ /** WoL MAC address. */ -+ IFX_uint8_t nWolMAC[6]; -+ /** WoL password. */ -+ IFX_uint8_t nWolPassword[6]; -+ /** WoL password enable. */ -+ IFX_boolean_t bWolPasswordEnable; -+}IFX_ETHSW_WoL_Cfg_t; -+ -+/** Enables Wake-on-LAN functionality on the port. -+ Used by \ref IFX_ETHSW_WOL_PORT_CFG_SET -+ and \ref IFX_ETHSW_WOL_PORT_CFG_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Enable Wake-on-LAN. */ -+ IFX_boolean_t bWakeOnLAN_Enable; -+}IFX_ETHSW_WoL_PortCfg_t; -+ -+/*@}*/ /* ETHSW_IOCTL_OAM */ -+ -+/* -------------------------------------------------------------------------- */ -+/* IOCTL Command Definitions */ -+/* -------------------------------------------------------------------------- */ -+ -+/** \addtogroup ETHSW_IOCTL_BRIDGE */ -+/*@{*/ -+ -+/** -+ Read an entry of the MAC table. -+ If the parameter 'bInitial=TRUE', the GET operation starts at the beginning -+ of the table. Otherwise it continues the GET operation at the entry that -+ follows the previous access. -+ The function sets all fields to zero in case the end of the table is reached. -+ In order to read out the complete table, this function can be called in a loop. -+ The Switch API sets 'bLast=IFX_TRUE' when the last entry is read out. -+ This 'bLast' parameter could be the loop exit criteria. -+ -+ \param IFX_ETHSW_MAC_tableRead_t Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MAC_TABLE_ENTRY_READ _IOWR(IFX_ETHSW_MAGIC, 0x01, IFX_ETHSW_MAC_tableRead_t) -+ -+/** -+ Search the MAC Address table for a specific address entry. -+ A MAC address is provided by the application and Switch API -+ performs a search operation on the hardware table. -+ Many hardware platforms provide an optimized and fast address search algorithm. -+ -+ \param IFX_ETHSW_MAC_tableQuery_t Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MAC_TABLE_ENTRY_QUERY _IOWR(IFX_ETHSW_MAGIC, 0x02, IFX_ETHSW_MAC_tableQuery_t) -+ -+/** -+ Add a MAC table entry. If an entry already exists for the given MAC Address -+ and Filtering Database (FID), this entry is overwritten. If not, -+ a new entry is added. -+ -+ \param IFX_ETHSW_MAC_tableAdd_t Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableAdd_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MAC_TABLE_ENTRY_ADD _IOW(IFX_ETHSW_MAGIC, 0x03, IFX_ETHSW_MAC_tableAdd_t) -+ -+/** -+ Remove a single MAC entry from the MAC table. -+ -+ \param IFX_ETHSW_MAC_tableRemove_t Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRemove_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x04, IFX_ETHSW_MAC_tableRemove_t) -+ -+/** -+ Remove all MAC entries from the MAC table. -+ -+ \param IFX_void_t This command does not require any parameter structure -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MAC_TABLE_CLEAR _IO(IFX_ETHSW_MAGIC, 0x05) -+ -+/** -+ Configure the Spanning Tree Protocol state of an Ethernet port. -+ The switch supports four Spanning Tree Port states (Disable/Discarding, -+ Blocking/Listening, Learning and Forwarding state) for every port, to enable -+ the Spanning Tree Protocol function when co-operating with software on -+ the CPU port. -+ Identified Spanning Tree Protocol packets can be redirected to the CPU port. -+ Depending on the hardware implementation, the CPU port assignement is fixed -+ or can be configured using \ref IFX_ETHSW_CPU_PORT_CFG_SET. -+ The current port state can be read back -+ using \ref IFX_ETHSW_STP_PORT_CFG_GET. -+ -+ \param IFX_ETHSW_STP_portCfg_t Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_STP_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x06, IFX_ETHSW_STP_portCfg_t) -+ -+/** -+ Read out the current Spanning Tree Protocol state of an Ethernet port. -+ This configuration can be set using \ref IFX_ETHSW_STP_PORT_CFG_SET. -+ -+ \param IFX_ETHSW_STP_portCfg_t Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_STP_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x07, IFX_ETHSW_STP_portCfg_t) -+ -+/** -+ Set the Spanning Tree configuration. This configuration includes the -+ filtering of detected spanning tree packets. These packets could be -+ redirected to one dedicated port (e.g. CPU port) or they could be discarded. -+ The current configuration can be read using \ref IFX_ETHSW_STP_BPDU_RULE_GET. -+ -+ \param IFX_ETHSW_STP_BPDU_Rule_t Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_STP_BPDU_RULE_SET _IOW(IFX_ETHSW_MAGIC, 0x08, IFX_ETHSW_STP_BPDU_Rule_t) -+ -+/** -+ Read the Spanning Tree configuration. -+ The configuration can be modified using \ref IFX_ETHSW_STP_BPDU_RULE_SET. -+ -+ \param IFX_ETHSW_STP_BPDU_Rule_t Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_STP_BPDU_RULE_GET _IOWR(IFX_ETHSW_MAGIC, 0x09, IFX_ETHSW_STP_BPDU_Rule_t) -+ -+/** -+ Read the IEEE 802.1x filter configuration. -+ The parameters can be modified using \ref IFX_ETHSW_8021X_EAPOL_RULE_SET. -+ -+ \param IFX_ETHSW_8021X_EAPOL_Rule_t Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_8021X_EAPOL_RULE_GET _IOR(IFX_ETHSW_MAGIC, 0x0A, IFX_ETHSW_8021X_EAPOL_Rule_t) -+ -+/** -+ Set the IEEE 802.1x filter rule for a dedicated port. Filtered packets can be -+ redirected to one dedicated port (e.g. CPU port). -+ The switch supports the addition of a specific packet header to the filtered packets -+ that contains information like source port, priority and so on. -+ The parameters can be read using \ref IFX_ETHSW_8021X_EAPOL_RULE_GET. -+ -+ \param IFX_ETHSW_8021X_EAPOL_Rule_t Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_8021X_EAPOL_RULE_SET _IOW(IFX_ETHSW_MAGIC, 0x0B, IFX_ETHSW_8021X_EAPOL_Rule_t) -+ -+/** -+ Get the 802.1x port status for a switch port. -+ A configuration can be set using \ref IFX_ETHSW_8021X_PORT_CFG_SET -+ -+ \param IFX_ETHSW_8021X_portCfg_t Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_8021X_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x0C, IFX_ETHSW_8021X_portCfg_t) -+ -+/** -+ Set the 802.1x port status for a switch port. -+ The port configuration can be read using \ref IFX_ETHSW_8021X_PORT_CFG_GET. -+ -+ \param IFX_ETHSW_8021X_portCfg_t Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_8021X_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x0D, IFX_ETHSW_8021X_portCfg_t) -+ -+/*@}*/ /* ETHSW_IOCTL_BRIDGE */ -+ -+/** \addtogroup ETHSW_IOCTL_VLAN */ -+/*@{*/ -+ -+/** -+ Add VLAN ID to a reserved VLAN list. -+ The switch supports replacing the VID of received packets with the PVID of -+ the receiving port. This function adds a VID to the list of VIDs to replace. -+ All switch devices support adding VID=0, VID=1 and VID=FFF to be replaced. -+ Some devices also allow adding other VIDs to be replaced. -+ An added VID could be removed again by -+ calling \ref IFX_ETHSW_VLAN_RESERVED_REMOVE. -+ This configuration applies to the whole switch device. -+ -+ \param IFX_ETHSW_VLAN_reserved_t Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_RESERVED_ADD _IOW(IFX_ETHSW_MAGIC, 0x0E, IFX_ETHSW_VLAN_reserved_t) -+ -+/** -+ Remove VLAN ID from a reserved VLAN group list. -+ This function removes a VID replacement configuration from the switch -+ hardware. This replacement configuration replaces the VID of received -+ packets with the PVID of the receiving port. This configuration can be -+ added using \ref IFX_ETHSW_VLAN_RESERVED_ADD. -+ This configuration applies to the whole switch device. -+ -+ \param IFX_ETHSW_VLAN_reserved_t Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_RESERVED_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x0F, IFX_ETHSW_VLAN_reserved_t) -+ -+/** -+ Get VLAN Port Configuration. -+ This function returns the VLAN configuration of the given Port 'nPortId'. -+ -+ \param IFX_ETHSW_VLAN_portCfg_t Pointer to an -+ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter -+ 'nPortId', the switch API implementation fills out the remaining structure -+ elements. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x10, IFX_ETHSW_VLAN_portCfg_t) -+ -+/** -+ Set VLAN Port Configuration. -+ This function sets the VLAN configuration of the given Port 'nPortId'. -+ -+ \param IFX_ETHSW_VLAN_portCfg_t Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t -+ structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x11, IFX_ETHSW_VLAN_portCfg_t) -+ -+/** -+ Add a VLAN ID group to the active VLAN set of the -+ Ethernet switch hardware. -+ Based on this configuration, VLAN group port members can -+ be added using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. -+ The VLAN ID configuration can be removed again by -+ calling \ref IFX_ETHSW_VLAN_ID_DELETE. -+ -+ \param IFX_ETHSW_VLAN_IdCreate_t Pointer to -+ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_ID_CREATE _IOW(IFX_ETHSW_MAGIC, 0x12, IFX_ETHSW_VLAN_IdCreate_t) -+ -+/** -+ Remove a VLAN ID group from the active VLAN set of the switch -+ hardware. The VLAN ID group was set -+ using \ref IFX_ETHSW_VLAN_ID_CREATE. A VLAN ID group can only be -+ removed when no port group members are currently configured on the hardware. -+ This VLAN ID group membership configuration is done -+ using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD and can be -+ removed again using \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. -+ -+ \param IFX_ETHSW_VLAN_IdDelete_t Pointer to an -+ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. -+ -+ \remarks A VLAN ID can only be removed in case it was created by -+ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned -+ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_ID_DELETE _IOW(IFX_ETHSW_MAGIC, 0x13, IFX_ETHSW_VLAN_IdDelete_t) -+ -+/** -+ Add Ethernet port to port members of a given VLAN group. -+ The assignment can be removed using \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE. -+ -+ \param IFX_ETHSW_VLAN_portMemberAdd_t Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_PORT_MEMBER_ADD _IOW(IFX_ETHSW_MAGIC, 0x14, IFX_ETHSW_VLAN_portMemberAdd_t) -+ -+/** -+ Remove Ethernet port from port members of a given VLAN group. -+ This assignment was done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD. -+ -+ \param IFX_ETHSW_VLAN_portMemberRemove_t Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x15, IFX_ETHSW_VLAN_portMemberRemove_t) -+ -+/** -+ Read out all given VLAN group port memberships. Every command call -+ returns one VLAN and port membership pair with the corresponding -+ egress traffic tag behavior. Call the command in a loop till -+ Switch API sets the 'bLast' variable to read all VLAN port memberships. -+ Please set the 'bInitial' parameter for the first call starting the -+ read operation at the beginning of the VLAN table. -+ -+ \param IFX_ETHSW_VLAN_portMemberRead_t Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_PORT_MEMBER_READ _IOR(IFX_ETHSW_MAGIC, 0x16, IFX_ETHSW_VLAN_portMemberRead_t) -+ -+/** -+ Read out the FID of a given VLAN ID. -+ This VLAN ID can be added using \ref IFX_ETHSW_VLAN_ID_CREATE. -+ This function returns an error in case no valid configuration is -+ available for the given VLAN ID. -+ -+ \param IFX_ETHSW_VLAN_IdGet_t Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_VLAN_ID_GET _IOWR(IFX_ETHSW_MAGIC, 0x17, IFX_ETHSW_VLAN_IdGet_t) -+ -+/*@}*/ /* ETHSW_IOCTL_VLAN */ -+ -+/** \addtogroup ETHSW_IOCTL_QOS */ -+/*@{*/ -+ -+/** -+ Configures the Ethernet port based traffic class assignment of ingress packets. -+ It is used to identify the packet priority and the related egress -+ priority queue. For DSCP, the priority to queue assignment is done -+ using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. -+ For VLAN, the priority to queue assignment is done -+ using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. The current port configuration can be -+ read using \ref IFX_ETHSW_QOS_PORT_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_portCfg_t Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x18, IFX_ETHSW_QoS_portCfg_t) -+ -+/** -+ Read out the current Ethernet port traffic class of ingress packets. -+ It is used to identify the packet priority and the related egress -+ priority queue. The port configuration can be set -+ using \ref IFX_ETHSW_QOS_PORT_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_portCfg_t Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x19, IFX_ETHSW_QoS_portCfg_t) -+ -+/** -+ Initialize the QoS 64 DSCP mapping to the switch priority queues. -+ This configuration applies for the whole switch device. The table -+ configuration can be read using \ref IFX_ETHSW_QOS_DSCP_CLASS_GET. -+ -+ \param IFX_ETHSW_QoS_DSCP_ClassCfg_t Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_DSCP_CLASS_SET _IOW(IFX_ETHSW_MAGIC, 0x1A, IFX_ETHSW_QoS_DSCP_ClassCfg_t) -+ -+/** -+ Read out the QoS 64 DSCP mapping to the switch priority queues. -+ The table configuration can be set using \ref IFX_ETHSW_QOS_DSCP_CLASS_SET. -+ -+ \param IFX_ETHSW_QoS_DSCP_ClassCfg_t Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_DSCP_CLASS_GET _IOWR(IFX_ETHSW_MAGIC, 0x1B, IFX_ETHSW_QoS_DSCP_ClassCfg_t) -+ -+/** -+ Configure the PCP to traffic class mapping table. -+ This configuration applies to the entire switch device. -+ The table configuration can be read using \ref IFX_ETHSW_QOS_PCP_CLASS_GET. -+ -+ \param IFX_ETHSW_QoS_PCP_ClassCfg_t Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PCP_CLASS_SET _IOW(IFX_ETHSW_MAGIC, 0x1C, IFX_ETHSW_QoS_PCP_ClassCfg_t) -+ -+/** -+ Read out the PCP to traffic class mapping table. -+ The table configuration can be set using \ref IFX_ETHSW_QOS_PCP_CLASS_SET. -+ -+ \param IFX_ETHSW_QoS_PCP_ClassCfg_t Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PCP_CLASS_GET _IOWR(IFX_ETHSW_MAGIC, 0x1D, IFX_ETHSW_QoS_PCP_ClassCfg_t) -+ -+/** -+ Configures the DSCP to Drop Precedence assignment mapping table. -+ This mapping table is used to identify the switch internally used drop -+ precedence based on the DSCP value of the incoming packet. -+ The current mapping table configuration can be read -+ using \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t Pointer to the QoS -+ DSCP drop precedence parameters -+ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x1E, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t) -+ -+/** -+ Read out the current DSCP to Drop Precedence assignment mapping table. -+ The table can be configured -+ using \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t Pointer to the QoS -+ DSCP drop precedence parameters -+ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x1F, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t) -+ -+/** -+ Port Remarking Configuration. Ingress and Egress remarking options for -+ DSCP and PCP. Remarking is done either on the used traffic class or -+ the drop precedence. -+ The current configuration can be read -+ using \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_portRemarkingCfg_t Pointer to the remarking configuration -+ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x20, IFX_ETHSW_QoS_portRemarkingCfg_t) -+ -+/** -+ Read out the Port Remarking Configuration. Ingress and Egress remarking options for -+ DSCP and PCP. Remarking is done either on the used traffic class or -+ the drop precedence. -+ The current configuration can be set -+ using \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_portRemarkingCfg_t Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x21, IFX_ETHSW_QoS_portRemarkingCfg_t) -+ -+/** -+ Configure the traffic class to DSCP mapping table. -+ This table is global and valid for the entire switch device. -+ The table can be read using \ref IFX_ETHSW_QOS_CLASS_DSCP_GET. -+ -+ \param IFX_ETHSW_QoS_ClassDSCP_Cfg_t Pointer to the DSCP mapping parameter -+ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_CLASS_DSCP_SET _IOW(IFX_ETHSW_MAGIC, 0x22, IFX_ETHSW_QoS_ClassDSCP_Cfg_t) -+ -+/** -+ Read out the current traffic class to DSCP mapping table. -+ The table can be written using \ref IFX_ETHSW_QOS_CLASS_DSCP_SET. -+ -+ \param IFX_ETHSW_QoS_ClassDSCP_Cfg_t Pointer to the DSCP mapping parameter -+ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_CLASS_DSCP_GET _IOWR(IFX_ETHSW_MAGIC, 0x23, IFX_ETHSW_QoS_ClassDSCP_Cfg_t) -+ -+/** -+ Configure the traffic class to 802.1P (PCP) priority mapping table. -+ This table is global and valid for the entire switch device. -+ The table can be read using \ref IFX_ETHSW_QOS_CLASS_PCP_GET. -+ -+ \param IFX_ETHSW_QoS_ClassPCP_Cfg_t Pointer to the PCP priority mapping parameter -+ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_CLASS_PCP_SET _IOWR(IFX_ETHSW_MAGIC, 0x24, IFX_ETHSW_QoS_ClassPCP_Cfg_t) -+ -+/** -+ Read out the current traffic class to 802.1P (PCP) priority mapping table. -+ This table is global and valid for the entire switch device. -+ The table can be written using \ref IFX_ETHSW_QOS_CLASS_PCP_SET. -+ -+ \param IFX_ETHSW_QoS_ClassPCP_Cfg_t Pointer to the PCP priority mapping parameter -+ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_CLASS_PCP_GET _IOWR(IFX_ETHSW_MAGIC, 0x25, IFX_ETHSW_QoS_ClassPCP_Cfg_t) -+ -+/** This command configures a rate shaper instance with the rate and the -+ burst size. This instance can be assigned to QoS queues by -+ using \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN. -+ The total number of available rate shapers can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_ShaperCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SHAPER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x26, IFX_ETHSW_QoS_ShaperCfg_t) -+ -+/** This command retrieves the rate and the burst size configuration of a -+ rate shaper instance. A configuration can be modified -+ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. -+ The total number of available rate shapers can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_ShaperCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SHAPER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x27, IFX_ETHSW_QoS_ShaperCfg_t) -+ -+/** Assign one rate shaper instance to a QoS queue. The function returns with an -+ error in case there already are too many shaper instances assigned to a queue. -+ The queue instance can be enabled and configured -+ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. -+ To remove a rate shaper instance from a QoS queue, -+ please use \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN. -+ The total number of available rate shaper instances can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_ShaperQueue_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN _IOW(IFX_ETHSW_MAGIC, 0x28, IFX_ETHSW_QoS_ShaperQueue_t) -+ -+/** Deassign one rate shaper instance from a QoS queue. The function returns -+ with an error in case the requested instance is not currently assigned -+ to the queue. -+ The queue instance can be enabled and configured by -+ using \ref IFX_ETHSW_QOS_SHAPER_CFG_SET. -+ To assign a rate shaper instance to a QoS queue, -+ please use \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN. -+ The total number of available rate shapers can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_ShaperQueue_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN _IOW(IFX_ETHSW_MAGIC, 0x29, IFX_ETHSW_QoS_ShaperQueue_t) -+ -+/** Check whether a rate shaper instance is assigned to the egress queue. -+ The egress queue index is the function input parameter. -+ The switch API sets the boolean parameter 'bAssigned == IFX_TRUE' in case a -+ rate shaper is assigned and then sets 'nRateShaperId' to describe the rater -+ shaper instance. -+ The parameter 'bAssigned == IFX_FALSE' in case no rate shaper instance -+ is currently assigned to the queue instance. -+ The commands \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN allow a -+ rate shaper instance to be assigned, and \ref IFX_ETHSW_QOS_SHAPER_CFG_SET allows -+ for configuration of a shaper instance. -+ The total number of available rate shapers can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_ShaperQueueGet_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueueGet_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SHAPER_QUEUE_GET _IOW(IFX_ETHSW_MAGIC, 0x2A, IFX_ETHSW_QoS_ShaperQueueGet_t) -+ -+/** Configures the global WRED drop probability profile and thresholds of the device. -+ Given parameters are rounded to the segment size of the HW platform. -+ The supported segment size is given by the capability list by -+ using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_WRED_Cfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_WRED_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2B, IFX_ETHSW_QoS_WRED_Cfg_t) -+ -+/** Read out the global WRED drop probability profile and thresholds of the device. -+ Given parameters are rounded to the segment size of the HW platform. -+ The supported segment size is given by the capability list by -+ using \ref IFX_ETHSW_CAP_GET. -+ -+ \param IFX_ETHSW_QoS_WRED_Cfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_WRED_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x2C, IFX_ETHSW_QoS_WRED_Cfg_t) -+ -+/** Configures the WRED drop thresholds for a dedicated egress queue. -+ Given parameters are rounded to the segment size of the HW platform. -+ The supported segment size is given by the capability list by -+ using \ref IFX_ETHSW_CAP_GET. -+ The command \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET retrieves the current -+ configuration. -+ -+ \param IFX_ETHSW_QoS_WRED_QueueCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2D, IFX_ETHSW_QoS_WRED_QueueCfg_t) -+ -+/** Read out the WRED drop thresholds for a dedicated egress queue. -+ Given parameters are rounded to the segment size of the HW platform. -+ The supported segment size is given by the capability list by -+ using \ref IFX_ETHSW_CAP_GET. -+ The configuration can be changed by -+ using \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_WRED_QueueCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x2E, IFX_ETHSW_QoS_WRED_QueueCfg_t) -+ -+/** This command configures the parameters of a rate meter instance. -+ This instance can be assigned to an ingress/egress port by -+ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. It can also be used by the -+ flow classification engine. -+ The total number of available rate meters can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ The current configuration of a meter instance can be retrieved -+ using \ref IFX_ETHSW_QOS_METER_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_meterCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_METER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x2F, IFX_ETHSW_QoS_meterCfg_t) -+ -+/** Configure the parameters of a rate meter instance. -+ This instance can be assigned to an ingress/egress port -+ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. It can also be used by the -+ flow classification engine. -+ The total number of available rate meters can be retrieved by the -+ capability list using \ref IFX_ETHSW_CAP_GET. -+ The current configuration of a meter instance can be retrieved -+ using \ref IFX_ETHSW_QOS_METER_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_meterCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_METER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x30, IFX_ETHSW_QoS_meterCfg_t) -+ -+/** Assign a rate meter instance to an ingress and/or egress port. -+ A maximum of two meter IDs can be assigned to one single ingress port. -+ This meter instance to port assignment can be removed -+ using \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN. A list of all available -+ assignments can be read using \ref IFX_ETHSW_QOS_METER_PORT_GET. -+ -+ \param IFX_ETHSW_QoS_meterPort_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_METER_PORT_ASSIGN _IOW(IFX_ETHSW_MAGIC, 0x31, IFX_ETHSW_QoS_meterPort_t) -+ -+/** Deassign a rate meter instance from an ingress and/or egress port. -+ A maximum of two meter IDs can be assigned to one single ingress port. -+ The meter instance is given to the command and the port configuration is -+ returned. An instance to port assignment can be done -+ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. A list of all available -+ assignments can be read using \ref IFX_ETHSW_QOS_METER_PORT_GET. -+ -+ \param IFX_ETHSW_QoS_meterPort_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_METER_PORT_DEASSIGN _IOW(IFX_ETHSW_MAGIC, 0x32, IFX_ETHSW_QoS_meterPort_t) -+ -+/** Reads out all meter instance to port assignments that are done -+ using \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN. All assignments are read from an -+ internal table where every read call retrieves the next entry of the table. -+ Setting the parameter 'bInitial' starts the read operation at the beginning -+ of the table. The returned parameter 'bLast' indicates that the last -+ element of the table was returned. -+ -+ \param IFX_ETHSW_QoS_meterPortGet_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPortGet_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_METER_PORT_GET _IOWR(IFX_ETHSW_MAGIC, 0x33, IFX_ETHSW_QoS_meterPortGet_t) -+ -+/** This command configures one meter instances for storm control. -+ These instances can be used for ingress broadcast-, multicast- and -+ unknown unicast- packets. Some platforms support addition of additional meter -+ instances for this type of packet. -+ Repeated calls of \ref IFX_ETHSW_QOS_STORM_CFG_SET allow addition of -+ additional meter instances. -+ An assignment can be retrieved using \ref IFX_ETHSW_QOS_STORM_CFG_GET. -+ Setting the broadcast, multicast and unknown unicast packets boolean switch to zero -+ deletes all metering instance assignments. -+ -+ \param IFX_ETHSW_QoS_stormCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_stormCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_STORM_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x34, IFX_ETHSW_QoS_stormCfg_t) -+ -+/** Reads out the current meter instance assignment for storm control. This -+ configuration can be modified using \ref IFX_ETHSW_QOS_STORM_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_stormCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_stormCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_STORM_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x35, IFX_ETHSW_QoS_stormCfg_t) -+ -+/** This configuration decides how the egress queues, attached to a single port, -+ are scheduled to transmit the queued Ethernet packets. -+ The configuration differentiates between 'Strict Priority' and -+ 'weighted fair queuing'. This applies when multiple egress queues are -+ assigned to an Ethernet port. -+ Using the WFQ feature on a port requires the configuration of weights on all -+ given queues that are assigned to that port. -+ Strict Priority means that no dedicated weight is configured and the -+ queue can transmit following its priority status. -+ The given configuration can be read out -+ using \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET. -+ -+ \param IFX_ETHSW_QoS_schedulerCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SCHEDULER_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x36, IFX_ETHSW_QoS_schedulerCfg_t) -+ -+/** Read out the current scheduler configuration of a given egress port. This -+ configuration can be modified -+ using \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET. -+ -+ \param IFX_ETHSW_QoS_schedulerCfg_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_SCHEDULER_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x37, IFX_ETHSW_QoS_schedulerCfg_t) -+ -+/** Sets the Queue ID for one traffic class of one port. -+ The total amount of supported ports, queues and traffic classes can be -+ retrieved from the capability list using \ref IFX_ETHSW_CAP_GET. -+ Please note that the device comes along with a -+ default configuration and assignment. -+ -+ \param IFX_ETHSW_QoS_queuePort_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_queuePort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_QUEUE_PORT_SET _IOW(IFX_ETHSW_MAGIC, 0x38, IFX_ETHSW_QoS_queuePort_t) -+ -+/** Read out the traffic class and port assignment done -+ using \ref IFX_ETHSW_QOS_QUEUE_PORT_SET. -+ Please note that the device comes along with a -+ default configuration and assignment. -+ -+ \param IFX_ETHSW_QoS_queuePort_t Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_queuePort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_QOS_QUEUE_PORT_GET _IOWR(IFX_ETHSW_MAGIC, 0x39, IFX_ETHSW_QoS_queuePort_t) -+ -+/*@}*/ /* ETHSW_IOCTL_QOS */ -+ -+/** \addtogroup ETHSW_IOCTL_MULTICAST */ -+/*@{*/ -+ -+/** -+ Configure the switch multicast configuration. The currently used -+ configuration can be read using \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET. -+ -+ \param IFX_ETHSW_multicastSnoopCfg_t Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_SNOOP_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x3A, IFX_ETHSW_multicastSnoopCfg_t) -+ -+/** -+ Read out the current switch multicast configuration. -+ The configuration can be set using \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET. -+ -+ \param IFX_ETHSW_multicastSnoopCfg_t Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_SNOOP_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x3B, IFX_ETHSW_multicastSnoopCfg_t) -+ -+/** -+ Add static router port to the switch hardware multicast table. -+ These added router ports will not be removed by the router port learning aging process. -+ The router port learning is enabled over the parameter 'bLearningRouter' -+ over the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. -+ Router port learning and static added entries can both be used together. -+ In case of a sofware IGMP stack/daemon environemtn, the router port learning does -+ not have to be configured on the switch hardware. Instead the router port -+ management is handled by the IGMP stack/daemon. -+ A port can be removed using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. -+ -+ \param IFX_ETHSW_multicastRouter_t Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD _IOW(IFX_ETHSW_MAGIC, 0x3C, IFX_ETHSW_multicastRouter_t) -+ -+/** -+ Remove an Ethernet router port from the switch hardware multicast table. -+ A port can be added using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD. -+ -+ \param IFX_ETHSW_multicastRouter_t Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+#define IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE _IOW(IFX_ETHSW_MAGIC, 0x3D, IFX_ETHSW_multicastRouter_t) -+ -+/** -+ Check if a port has been selected as a router port, either by automatic learning or by manual setting. -+ A port can be added using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD. -+ A port can be removed again using \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE. -+ -+ \param IFX_ETHSW_multicastRouterRead_t Pointer to \ref IFX_ETHSW_multicastRouterRead_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+#define IFX_ETHSW_MULTICAST_ROUTER_PORT_READ _IOWR(IFX_ETHSW_MAGIC, 0x3E, IFX_ETHSW_multicastRouterRead_t) -+ -+/** -+ Adds a multicast group configuration to the multicast table. -+ No new entry is added in case this multicast group already -+ exists in the table. This commands adds a host member to -+ the multicast group. -+ A member can be removed again using \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE. -+ -+ \param IFX_ETHSW_multicastTable_t Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD _IOW(IFX_ETHSW_MAGIC, 0x3F, IFX_ETHSW_multicastTable_t) -+ -+/** -+ Remove an host member from a multicast group. The multicast group entry -+ is completely removed from the multicast table in case it has no -+ host member port left. -+ Group members can be added using \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD. -+ -+ \param IFX_ETHSW_multicastTable_t Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE _IOWR(IFX_ETHSW_MAGIC, 0x40, IFX_ETHSW_multicastTable_t) -+ -+/** -+ Read out the multicast membership table that is located inside the switch -+ hardware. The 'bInitial' parameter restarts the read operation at the beginning of -+ the table. Every following \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ call reads out -+ the next found entry. The 'bLast' parameter is set by the switch API in case -+ the last entry of the table is reached. -+ -+ \param IFX_ETHSW_multicastTableRead_t Pointer -+ to \ref IFX_ETHSW_multicastTableRead_t. -+ -+ \remarks The 'bInitial' parameter is reset during the read operation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ _IOWR(IFX_ETHSW_MAGIC, 0x41, IFX_ETHSW_multicastTableRead_t) -+ -+/*@}*/ /* ETHSW_IOCTL_MULTICAST */ -+ -+/** \addtogroup ETHSW_IOCTL_OAM */ -+/*@{*/ -+ -+/** Hardware Initialization. This command should be called right after the -+ Switch API software module is initialized and loaded. -+ It accesses the hardware platform, retrieving platform capabilities and -+ performing the first basic configuration. -+ -+ \param IFX_ETHSW_HW_Init_t Pointer to pre-allocated initialization structure -+ \ref IFX_ETHSW_HW_Init_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_HW_INIT _IOW(IFX_ETHSW_MAGIC, 0x42, IFX_ETHSW_HW_Init_t) -+ -+/** -+ Retrieve the version string of the currently version index. The returned -+ string format might vary between the device platforms used. This -+ means that the version information cannot be compared between different -+ device platforms. -+ All returned version information is in the form of zero-terminated character strings. -+ The returned strings are empty ('') in case the given version -+ index is out of range. -+ -+ \param IFX_ETHSW_version_t* The parameter points to a -+ \ref IFX_ETHSW_version_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+ \code -+ IFX_ETHSW_version_t param; -+ IFX_int32_t fd; -+ -+ memset (¶m, 0, sizeof(IFX_ETHSW_version_t)); -+ -+ while (1) -+ { -+ if (ioctl(fd, IFX_ETHSW_VERSION_GET, (IFX_int32_t) ¶m) -+ != IFX_SUCCESS) -+ { -+ printf("ERROR: TAPI version request failed!\n); -+ return IFX_ERROR; -+ } -+ -+ if ((strlen(param.cName) == 0) || (strlen(param.cVersion) == 0)) -+ // No more version entries found -+ break; -+ -+ printf("%s version: %s", param.cName, param.cVersion); -+ param.nId++; -+ } -+ -+ return IFX_SUCCESS; -+ \endcode -+*/ -+#define IFX_ETHSW_VERSION_GET _IOWR(IFX_ETHSW_MAGIC, 0x43, IFX_ETHSW_version_t) -+ -+/** This service returns the capability referenced by the provided index -+ (zero-based counting index value). The Switch API uses the index to return -+ the capability parameter from an internal list. For instance, -+ the capability list contains information about the amount of supported -+ features like number of supported VLAN groups or MAC table entries. -+ The command returns zero-length strings ('') in case the -+ requested index number is out of range. -+ -+ \param IFX_ETHSW_cap_t Pointer to pre-allocated capability -+ list structure \ref IFX_ETHSW_cap_t. -+ The switch API implementation fills out the structure with the supported -+ features, based on the provided 'nCapType' parameter. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \code -+ IFX_ETHSW_cap_t param; -+ IFX_int32_t fd; -+ IFX_int32_t i; -+ -+ // Open tapi file descriptor * -+ fd = open("/dev/switchapi/1", O_RDWR, 0x644); -+ -+ for (i = 0; i < IFX_ETHSW_CAP_TYPE_LAST, i++) -+ { -+ memset(¶m, 0, sizeof(param)); -+ param.nCapType = i; -+ //Get the cap list -+ if (ioctl(fd, IFX_ETHSW_CAP_GET, (IFX_int32_t) ¶m) == IFX_ERROR) -+ return IFX_ERROR; -+ -+ printf("%s: %d\n", param.cDesc, param.nCap); -+ } -+ -+ // Close open fd -+ close(fd); -+ return IFX_SUCCESS; -+ \endcode -+*/ -+#define IFX_ETHSW_CAP_GET _IOWR(IFX_ETHSW_MAGIC, 0x44, IFX_ETHSW_cap_t) -+ -+/** -+ Modify the switch configuration. -+ The configuration can be read using \ref IFX_ETHSW_CFG_GET. -+ The switch can be enabled using \ref IFX_ETHSW_ENABLE. -+ -+ \param IFX_ETHSW_cfg_t Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x45, IFX_ETHSW_cfg_t) -+ -+/** -+ Read the global switch configuration. -+ This configuration can be set using \ref IFX_ETHSW_CFG_SET. -+ -+ \param IFX_ETHSW_cfg_t Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ The structure is filled out by the switch implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x46, IFX_ETHSW_cfg_t) -+ -+/** -+ Enables the whole switch. The switch device is enabled with the default -+ configuration in case no other configuration is applied. -+ The switch can be disabled using the \ref IFX_ETHSW_DISABLE command -+ -+ \param IFX_void_t This command does not require any parameter structure -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_ENABLE _IO(IFX_ETHSW_MAGIC, 0x47) -+ -+/** -+ Disables the whole switch. -+ The switch can be enabled using the \ref IFX_ETHSW_ENABLE command -+ -+ \param IFX_void_t This command does not require any parameter structure -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_DISABLE _IO(IFX_ETHSW_MAGIC, 0x48) -+ -+/** -+ Read out the current Ethernet port configuration. -+ -+ \param IFX_ETHSW_portCfg_t Pointer to a port configuration -+ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. -+ The parameter 'nPortId' tells the driver which port parameter is requested. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x49, IFX_ETHSW_portCfg_t) -+ -+/** -+ Set the Ethernet port configuration. -+ -+ \param IFX_ETHSW_portCfg_t Pointer to an \ref IFX_ETHSW_portCfg_t structure -+ to configure the switch port hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4A, IFX_ETHSW_portCfg_t) -+ -+/** -+ Defines one port that is directly connected to the software running on a CPU. -+ This allows for the redirecting of protocol-specific packets to the CPU port and -+ special packet treatment when sent by the CPU. -+ If the CPU port cannot be set, the function returns an error code. -+ -+ \param IFX_ETHSW_CPU_PortCfg_t Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_CPU_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4B, IFX_ETHSW_CPU_PortCfg_t) -+ -+/** -+ Get the port that is directly connected to the software running on a CPU and defined as -+ CPU port. This port assignment can be set using \ref IFX_ETHSW_CPU_PORT_CFG_SET -+ if it is not fixed and defined by the switch device architecture. -+ -+ \param IFX_ETHSW_CPU_PortCfg_t Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_CPU_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4C, IFX_ETHSW_CPU_PortCfg_t) -+ -+/** -+ Configure an additional CPU port configuration. This configuration applies to -+ devices where the CPU port is fixed to one dedicated port. -+ -+ \param IFX_ETHSW_CPU_PortExtendCfg_t Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x4D, IFX_ETHSW_CPU_PortExtendCfg_t) -+ -+/** -+ Reads out additional CPU port configuration. This configuration applies to -+ devices where the CPU port is fixed to one dedicated port. -+ -+ \param IFX_ETHSW_CPU_PortExtendCfg_t Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+#define IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4E, IFX_ETHSW_CPU_PortExtendCfg_t) -+ -+/** -+ Read out the Ethernet port's speed, link status, and flow control status. -+ The information for one single port 'nPortId' is returned. -+ An error code is returned if the selected port does not exist. -+ -+ \param IFX_ETHSW_portLinkCfg_t Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_LINK_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x4F, IFX_ETHSW_portLinkCfg_t) -+ -+/** -+ Set the Ethernet port link, speed status and flow control status. -+ The configuration applies to a single port 'nPortId'. -+ -+ \param IFX_ETHSW_portLinkCfg_t Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_LINK_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x50, IFX_ETHSW_portLinkCfg_t) -+ -+/** -+ Configure the RGMII clocking parameter in case the Ethernet port is configured in RGMII mode. -+ The configuration can be read by calling \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET. -+ It applies to a single port 'nPortId'. -+ -+ \param IFX_ETHSW_portRGMII_ClkCfg_t Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_RGMII_CLK_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x51, IFX_ETHSW_portRGMII_ClkCfg_t) -+ -+/** -+ Read the RGMII clocking parameter in case the Ethernet port is configured in RGMII mode. -+ The configuration can be set by calling \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET. -+ It applies to a single port 'nPortId'. -+ -+ \param IFX_ETHSW_portRGMII_ClkCfg_t Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_RGMII_CLK_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x52, IFX_ETHSW_portRGMII_ClkCfg_t) -+ -+/** -+ Check whether the Ethernet switch hardware has detected an Ethernet PHY connected -+ to the given Ethernet port 'nPortId'. -+ -+ \param IFX_ETHSW_portPHY_Query_t Pointer to -+ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_PHY_QUERY _IOWR(IFX_ETHSW_MAGIC, 0x53, IFX_ETHSW_portPHY_Query_t) -+ -+/** -+ Read out the MDIO device address of an Ethernet PHY that is connected to -+ an Ethernet port. This device address is useful when accessing PHY -+ registers using the commands \ref IFX_ETHSW_MDIO_DATA_WRITE -+ and \ref IFX_ETHSW_MDIO_DATA_READ. -+ -+ \param IFX_ETHSW_portPHY_Addr_t Pointer to \ref IFX_ETHSW_portPHY_Addr_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_PHY_ADDR_GET _IOWR(IFX_ETHSW_MAGIC, 0x54, IFX_ETHSW_portPHY_Addr_t) -+ -+/** -+ Ingress and egress packets of one specific Ethernet port can be redirected to -+ the CPU port. The ingress and egress packet redirection can be configured -+ individually. This command reads out the current configuration of a -+ dedicated port. A new configuration can be applied -+ by calling \ref IFX_ETHSW_PORT_REDIRECT_SET. -+ -+ \param IFX_ETHSW_portRedirectCfg_t Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_REDIRECT_GET _IOWR(IFX_ETHSW_MAGIC, 0x55, IFX_ETHSW_portRedirectCfg_t) -+ -+/** -+ Select ingress and egress packets of one specific Ethernet port that can be -+ redirected to a port that is configured as the 'CPU port'. The ingress and -+ egress packet direction can be configured individually. -+ The packet filter of the original port still -+ applies to the packet (for example, MAC address learning is done for the -+ selected port and not for the CPU port). -+ On CPU port side, no additional learning, forwarding look up, -+ VLAN processing and queue selection is performed for redirected packets. -+ Depending on the hardware platform used, the CPU port has to be set in -+ advance using \ref IFX_ETHSW_CPU_PORT_CFG_SET. -+ The currently used configuration can be read -+ using \ref IFX_ETHSW_PORT_REDIRECT_GET. -+ -+ \param IFX_ETHSW_portRedirectCfg_t Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_PORT_REDIRECT_SET _IOW(IFX_ETHSW_MAGIC, 0x56, IFX_ETHSW_portRedirectCfg_t) -+ -+/** -+ Reads out the current monitor options for a -+ dedicated Ethernet port. This configuration can be set -+ using \ref IFX_ETHSW_MONITOR_PORT_CFG_SET. -+ -+ \param IFX_ETHSW_monitorPortCfg_t Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MONITOR_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x57, IFX_ETHSW_monitorPortCfg_t) -+ -+/** -+ Configures the monitor options for a -+ dedicated Ethernet port. This current configuration can be read back -+ using \ref IFX_ETHSW_MONITOR_PORT_CFG_GET. -+ -+ \param IFX_ETHSW_monitorPortCfg_t Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MONITOR_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x58, IFX_ETHSW_monitorPortCfg_t) -+ -+/** -+ Read out the Ethernet port statistic counter (RMON counter). -+ The zero-based 'nPortId' structure element describes the physical switch -+ port for the requested statistic information. -+ -+ \param IFX_ETHSW_RMON_cnt_t Pointer to pre-allocated -+ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is -+ an input parameter that describes from which port to read the RMON counter. -+ All remaining structure elements are filled with the counter values. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_RMON_GET _IOWR(IFX_ETHSW_MAGIC, 0x59, IFX_ETHSW_RMON_cnt_t) -+ -+/** -+ Clears an Ethernet port traffic statistic counter (RMON counter). -+ -+ \param IFX_ETHSW_RMON_clear_t Pointer to a pre-allocated -+ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is -+ an input parameter stating on which port to clear all RMON counters. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_RMON_CLEAR _IOW(IFX_ETHSW_MAGIC, 0x5A, IFX_ETHSW_RMON_clear_t) -+ -+/** -+ Read the MDIO interface configuration. -+ The parameters can be modified using \ref IFX_ETHSW_MDIO_CFG_SET. -+ -+ \param IFX_ETHSW_MDIO_cfg_t Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MDIO_CFG_GET _IOR(IFX_ETHSW_MAGIC, 0x5B, IFX_ETHSW_MDIO_cfg_t) -+ -+/** -+ Set the MDIO interface configuration. -+ The parameters can be read using \ref IFX_ETHSW_MDIO_CFG_GET. -+ The given frequency is rounded off to fitting to the hardware support. -+ \ref IFX_ETHSW_MDIO_CFG_GET will return the exact programmed (rounded) frequency value. -+ -+ \param IFX_ETHSW_MDIO_cfg_t Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MDIO_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x5C, IFX_ETHSW_MDIO_cfg_t) -+ -+/** -+ Read data from the MDIO Interface of the switch device. This function allows -+ various kinds of information to be read out for any attached device by register and -+ device addressing. -+ The 'nData' value (\ref IFX_ETHSW_MDIO_data_t) contains the read -+ device register. -+ A write operation can be done using \ref IFX_ETHSW_MDIO_DATA_WRITE. -+ -+ \param IFX_ETHSW_MDIO_data_t Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_MDIO_DATA_READ _IOWR(IFX_ETHSW_MAGIC, 0x5D, IFX_ETHSW_MDIO_data_t) -+ -+/** -+ Write data to the MDIO Interface of the switch device. This function allows -+ for configuration of any attached device by register and device addressing. -+ This applies to external and internal Ethernet PHYs as well. -+ The 'nData' value (\ref IFX_ETHSW_MDIO_data_t) is directly written to the -+ device register. -+ A read operation can be performed using \ref IFX_ETHSW_MDIO_DATA_READ. -+ -+ \param IFX_ETHSW_MDIO_data_t Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \code -+ IFX_ETHSW_MDIO_data_t phy; -+ -+ // access the device 2 -+ phy.nAddressDev = 2; -+ // PHY register 0 -+ phy.nAddressReg = 0; -+ // copy the helper PHY register union to the data field to configure -+ phy.nData = 0x1235; -+ -+ if (ioctl(fd, IFX_ETHSW_MDIO_DATA_WRITE, (int)&phy)) -+ return IFX_ERROR; -+ -+ // access the device 5 -+ phy.nAddressDev = 5; -+ // Device specific register 20 -+ phy.nAddressReg = 20; -+ // set the data field to configure -+ phy.nData = 0x1234; -+ -+ if (ioctl(fd, IFX_ETHSW_MDIO_DATA_WRITE, (int)&phy)) -+ return IFX_ERROR; -+ -+ return IFX_SUCCESS; -+ \endcode -+*/ -+#define IFX_ETHSW_MDIO_DATA_WRITE _IOW(IFX_ETHSW_MAGIC, 0x5E, IFX_ETHSW_MDIO_data_t) -+ -+/** -+ Set the Wake-on-LAN configuration. -+ The parameters can be read using \ref IFX_ETHSW_WOL_CFG_GET. -+ -+ \param IFX_ETHSW_WoL_Cfg_t Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_WOL_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x5F, IFX_ETHSW_WoL_Cfg_t) -+ -+/** -+ Read the Wake-on-LAN configuration. -+ The parameters can be modified using \ref IFX_ETHSW_WOL_CFG_SET. -+ -+ \param IFX_ETHSW_WoL_Cfg_t Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_WOL_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x60, IFX_ETHSW_WoL_Cfg_t) -+ -+/** -+ Set the current Wake-On-LAN status for a dedicated port. The -+ Wake-On-LAN specific parameter can be configured -+ using \ref IFX_ETHSW_WOL_CFG_SET. -+ -+ \param IFX_ETHSW_WoL_PortCfg_t Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_WOL_PORT_CFG_SET _IOW(IFX_ETHSW_MAGIC, 0x61, IFX_ETHSW_WoL_PortCfg_t) -+ -+/** -+ Read out the current status of the Wake-On-LAN feature -+ on a dedicated port. This status can be changed -+ using \ref IFX_ETHSW_WOL_PORT_CFG_SET. -+ The Wake-On-LAN specific parameter can be configured -+ using \ref IFX_ETHSW_WOL_CFG_SET. -+ -+ \param IFX_ETHSW_WoL_PortCfg_t Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_ETHSW_WOL_PORT_CFG_GET _IOWR(IFX_ETHSW_MAGIC, 0x62, IFX_ETHSW_WoL_PortCfg_t) -+ -+/*@}*/ /* ETHSW_IOCTL_OAM */ -+ -+#endif /* _IFX_ETHSW_H_ */ -diff --git a/include/switch_api/ifx_ethsw_PSB6970.h b/include/switch_api/ifx_ethsw_PSB6970.h -new file mode 100644 -index 0000000..766334d ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_PSB6970.h -@@ -0,0 +1,647 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef _IFX_ETHSW_PSB6970_H_ -+#define _IFX_ETHSW_PSB6970_H_ -+ -+#include "ifx_types.h" -+ -+/* =================================== */ -+/* Global typedef forward declarations */ -+/* =================================== */ -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+ -+/* IOCTL MAGIC */ -+#define IFX_PSB6970_MAGIC ('P') -+ -+/* Group definitions for Doxygen */ -+/** \defgroup PSB6970_IOCTL XWAY-ARX100 / XWAY TANTOS-xG Family Specific Ethernet Switch API -+ This chapter describes the XWAY ARX100 Family, XWAY TANTOS-0G, -+ XWAY TANTOS-2G and XWAY TANTOS-3G specific interfaces for accessing and -+ configuring the services of the Ethernet switch module. */ -+/*@{*/ -+/** \defgroup PSB6970_IOCTL_DEBUG Debug Features -+ XWAY TANTOS specific features for system integration and debug sessions. -+*/ -+/** \defgroup PSB6970_IOCTL_OAM Operation, Administration, and Management Functions -+ This chapter summarizes the functions that are provided to monitor the -+ data traffic passing through the device. -+*/ -+/** \defgroup PSB6970_IOCTL_POWER Power Management -+ Configure the XWAY TANTOS hardware specific power management. -+*/ -+/** \defgroup PSB6970_IOCTL_QOS Quality of Service Functions -+ Switch and port configuration for QoS. -+*/ -+/*@}*/ -+ -+/** \addtogroup PSB6970_IOCTL_OAM */ -+/*@{*/ -+ -+/** Reset selection. -+ Used by \ref IFX_PSB6970_reset_t. */ -+typedef enum -+{ -+ /** On-chip Ethernet PHY reset */ -+ IFX_PSB6970_RESET_EPHY = 0 -+}IFX_PSB6970_resetMode_t; -+ -+/** Reset selection. -+ Used by \ref IFX_PSB6970_RESET. */ -+typedef struct -+{ -+ /** Reset selection. */ -+ IFX_PSB6970_resetMode_t eReset; -+}IFX_PSB6970_reset_t; -+ -+/*@}*/ /* PSB6970_IOCTL_OAM */ -+ -+/** \addtogroup PSB6970_IOCTL_QOS */ -+/*@{*/ -+ -+/** WFQ Algorithm Selector per port. -+ Used by \ref IFX_PSB6970_QoS_portShaperCfg_t. */ -+typedef enum -+{ -+ /** Weight. WFQ instances are configured to assign a weight (ratio) to a queue instance. -+ All WFQ egress queues are configured using a ratio. */ -+ IFX_PSB6970_QoS_WFQ_WEIGHT = 0, -+ /** Rate. WFQ instances are configured to limit the egress traffic to a configured rate. */ -+ IFX_PSB6970_QoS_WFQ_RATE = 1 -+}IFX_PSB6970_QoS_WFQ_t; -+ -+/** Port-specific QoS configuration. -+ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET -+ and \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET. */ -+typedef struct -+{ -+ /** Port index. */ -+ IFX_uint32_t nPort; -+ /** WFQ Algorithm. Selection between ratio behavior -+ and rate limitation. */ -+ IFX_PSB6970_QoS_WFQ_t eWFQ_Type; -+}IFX_PSB6970_QoS_portShaperCfg_t; -+ -+/** Port-specific configuration for the priority queue rate shaper. -+ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET -+ and \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET. */ -+typedef struct -+{ -+ /** Port index. */ -+ IFX_uint32_t nPort; -+ /** Priority queue index (counting from zero). */ -+ IFX_uint8_t nTrafficClass; -+ /** Maximum average rate [in Mbit/s]. */ -+ IFX_uint32_t nRate; -+}IFX_PSB6970_QoS_portShaperStrictCfg_t; -+ -+/** Port-specific configuration for the weight fair queuing rate shaper. -+ The egress queues could be scheduled by assigned weights, -+ or the traffic limited by configured rate shapers. -+ The \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET command configures -+ the queues to work in weight or rate shaper mode. -+ Used by \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET -+ and \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET. */ -+typedef struct -+{ -+ /** Port index. */ -+ IFX_uint32_t nPort; -+ /** Priority queue index (counting from zero). */ -+ IFX_uint8_t nTrafficClass; -+ /** Rate / Weight. -+ -+ - Weight: Maximum average rate [in ratio], in case eWFQ_Type=IFX_PSB6970_QoS_WFQ_WEIGHT. -+ - Rate: Maximum average rate [in Mbit/s], in case eWFQ_Type=IFX_PSB6970_QoS_WFQ_RATE. -+ */ -+ IFX_uint32_t nRate; -+}IFX_PSB6970_QoS_portShaperWFQ_Cfg_t; -+ -+/** Port-specific configuration for the ingress rate policing. -+ Used by \ref IFX_PSB6970_QOS_PORT_POLICER_SET -+ and \ref IFX_PSB6970_QOS_PORT_POLICER_GET. */ -+typedef struct -+{ -+ /** Port index. */ -+ IFX_uint32_t nPort; -+ /** Maximum average rate [in Mbit/s]. */ -+ IFX_uint32_t nRate; -+}IFX_PSB6970_QoS_portPolicerCfg_t; -+ -+/** Qos storm control for egress packets. Different packet types can be -+ discarded if the egress packet rate reaches a defined threshold. -+ Used by \ref IFX_PSB6970_QOS_STORM_SET and \ref IFX_PSB6970_QOS_STORM_GET. */ -+typedef struct -+{ -+ /** Storm control for received boardcast packets. */ -+ IFX_boolean_t bBroadcast; -+ /** Storm control for received multicast packets. */ -+ IFX_boolean_t bMulticast; -+ /** Storm control for received unicasst packets. */ -+ IFX_boolean_t bUnicast; -+ /** 10 Mbit/s link threshold [in Mbit/s] for the storm control to discard. */ -+ IFX_uint32_t nThreshold10M; -+ /** 100 Mbit/s link threshold [in Mbit/s] for the storm control -+ to discard. */ -+ IFX_uint32_t nThreshold100M; -+}IFX_PSB6970_QoS_stormCfg_t; -+ -+/** Multi-Field priority classification fields. -+ Used by \ref IFX_PSB6970_QoS_MfcMatchField_t. */ -+typedef enum -+{ -+ /** UDP/TCP Source Port Filter. */ -+ IFX_PSB6970_QOS_MF_SRCPORT = 1, -+ /** UDP/TCP Destination Port Filter. */ -+ IFX_PSB6970_QOS_MF_DSTPORT = 2, -+ /** IP Protocol Filter. */ -+ IFX_PSB6970_QOS_MF_PROTOCOL = 4, -+ /** Ethertype Filter. */ -+ IFX_PSB6970_QOS_MF_ETHERTYPE = 8 -+}IFX_PSB6970_QoS_MfPrioClassfields_t; -+ -+/** Qos multi-field priority classification configuration for Ethernet ports. -+ Used by \ref IFX_PSB6970_QOS_MFC_PORT_CFG_SET -+ and \ref IFX_PSB6970_QOS_MFC_PORT_CFG_GET. */ -+typedef struct -+{ -+ /** Port index. */ -+ IFX_uint32_t nPort; -+ /** Use the UDP/TCP Port MFC priority classification rules to assign the -+ traffic class for ingress packets that match against a rule. */ -+ IFX_boolean_t bPriorityPort; -+ /** Use the EtherType MFC priority classification rules to assign the -+ traffic class for ingress packets that match against a rule. */ -+ IFX_boolean_t bPriorityEtherType; -+}IFX_PSB6970_QoS_MfcPortCfg_t; -+ -+/** QoS multi-field priority classification match fields structure. -+ Used by \ref IFX_PSB6970_QoS_MfcCfg_t and \ref IFX_PSB6970_QOS_MFC_DEL. */ -+typedef struct -+{ -+ /** Source port base. */ -+ IFX_uint16_t nPortSrc; -+ /** Destination port base */ -+ IFX_uint16_t nPortDst; -+ /** Check from nPortSrc till smaller nPortSrc + nPortSrcRange. */ -+ IFX_uint16_t nPortSrcRange; -+ /** Check from nPortDst till smaller nPortDst + nPortDstRange. */ -+ IFX_uint16_t nPortDstRange; -+ /** Protocol type. */ -+ IFX_uint8_t nProtocol; -+ /** Ether type. */ -+ IFX_uint16_t nEtherType; -+ /** Select the filtering field.*/ -+ IFX_PSB6970_QoS_MfPrioClassfields_t eFieldSelection; -+}IFX_PSB6970_QoS_MfcMatchField_t; -+ -+/** QoS multi-field priority classification info structure. -+ Used by \ref IFX_PSB6970_QoS_MfcCfg_t. */ -+typedef struct -+{ -+ /** Egress priority queue priority queues, Q3 > Q2 > Q1 > Q0. -+ The queue index starts counting from zero. */ -+ IFX_uint8_t nTrafficClass; -+ /** Output port selection. */ -+ IFX_ETHSW_portForward_t ePortForward; -+}IFX_PSB6970_QoS_MfcInfo_t; -+ -+/** QoS multi-field priority classification rule config structure. -+ Used by \ref IFX_PSB6970_QoS_MfcEntryRead_t and \ref IFX_PSB6970_QOS_MFC_ADD. */ -+typedef struct -+{ -+ /** Match fields. */ -+ IFX_PSB6970_QoS_MfcMatchField_t sFilterMatchField; -+ /** Filter info. */ -+ IFX_PSB6970_QoS_MfcInfo_t sFilterInfo; -+}IFX_PSB6970_QoS_MfcCfg_t; -+ -+/** QoS multi-field priority classification rule get all structure. -+ Used by \ref IFX_PSB6970_QOS_MFC_ENTRY_READ. */ -+typedef struct -+{ -+ /** Restart the get operation from the beginning of the table. Otherwise -+ return the next table entry (next to the entry that was returned -+ during the previous get operation). This boolean parameter is set by the -+ calling application. */ -+ IFX_boolean_t bInitial; -+ /** Indicates that the read operation has reached the last valid entry in the -+ table. This boolean parameter is set by the switch API. */ -+ IFX_boolean_t bLast; -+ /** This filter is filled out by the switch API. */ -+ IFX_PSB6970_QoS_MfcCfg_t sFilter; -+}IFX_PSB6970_QoS_MfcEntryRead_t; -+ -+/*@}*/ /* PSB6970_IOCTL_QOS */ -+ -+/** \addtogroup PSB6970_IOCTL_POWER */ -+/*@{*/ -+ -+/** Parameter structure for configuring the power management. -+ Used by \ref IFX_PSB6970_POWER_MANAGEMENT_SET -+ and \ref IFX_PSB6970_POWER_MANAGEMENT_GET. */ -+typedef struct -+{ -+ /** Enable/disable power management on this switch device instance. */ -+ IFX_boolean_t bEnable; -+}IFX_PSB6970_powerManagement_t; -+ -+/*@}*/ /* PSB6970_IOCTL_POWER */ -+ -+/** \addtogroup PSB6970_IOCTL_DEBUG */ -+/*@{*/ -+ -+/** Register access parameter to directly read or write switch -+ internal registers. -+ Used by \ref IFX_PSB6970_REGISTER_SET and \ref IFX_PSB6970_REGISTER_GET. */ -+typedef struct -+{ -+ /** Register Address Offset for read or write access. */ -+ IFX_uint32_t nRegAddr; -+ /** Value to write to or read from 'nRegAddr'. */ -+ IFX_uint32_t nData; -+}IFX_PSB6970_register_t; -+ -+/*@}*/ /* PSB6970_IOCTL_DEBUG */ -+ -+/* ------------------------------------------------------------------------- */ -+/* IOCTL Command Definitions */ -+/* ------------------------------------------------------------------------- */ -+ -+/** \addtogroup PSB6970_IOCTL_OAM */ -+/*@{*/ -+ -+/** -+ Forces a hardware reset of the switch device or switch macro. The device -+ automatically comes back out of reset and contains the initial values. -+ All previous configurations are lost. -+ -+ \param IFX_PSB6970_reset_t Pointer to an \ref IFX_PSB6970_reset_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \remarks Not supported for all devices -+*/ -+#define IFX_PSB6970_RESET _IOW(IFX_PSB6970_MAGIC, 0x01, IFX_PSB6970_reset_t) -+ -+/*@}*/ /* PSB6970_IOCTL_OAM */ -+ -+/** \addtogroup PSB6970_IOCTL_QOS */ -+/*@{*/ -+ -+/** -+ Configures the QoS rate shaper for the Ethernet port egress strict priority queues. -+ The current configuration can be -+ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET. -+ -+ \param IFX_PSB6970_QoS_portShaperCfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET _IOW(IFX_PSB6970_MAGIC, 0x02, IFX_PSB6970_QoS_portShaperCfg_t) -+ -+/** -+ Reads out the current rate shaper for the Ethernet port egress strict priority queues. -+ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET. -+ -+ \param IFX_PSB6970_QoS_portShaperCfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET _IOWR(IFX_PSB6970_MAGIC, 0x03, IFX_PSB6970_QoS_portShaperCfg_t) -+ -+/** -+ Configures the rate shaper for the Ethernet port egress strict priority queues. -+ The current configuration can be -+ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET. -+ -+ \param IFX_PSB6970_QoS_portShaperStrictCfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET _IOW(IFX_PSB6970_MAGIC, 0x04, IFX_PSB6970_QoS_portShaperStrictCfg_t) -+ -+/** -+ Reads out the current rate shaper for the Ethernet port egress strict priority queues. -+ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET. -+ -+ \param IFX_PSB6970_QoS_portShaperStrictCfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET _IOWR(IFX_PSB6970_MAGIC, 0x05, IFX_PSB6970_QoS_portShaperStrictCfg_t) -+ -+/** -+ Configures the rate shaper for the Ethernet port egress WFQ priority queues. -+ The current configuration can be -+ retrieved using \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET. -+ -+ \param IFX_PSB6970_QoS_portShaperWFQ_Cfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET _IOW(IFX_PSB6970_MAGIC, 0x06, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t) -+ -+/** -+ Reads out the current rate shaper for the Ethernet port egress WFQ priority queues. -+ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET. -+ -+ \param IFX_PSB6970_QoS_portShaperWFQ_Cfg_t Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET _IOWR(IFX_PSB6970_MAGIC, 0x07, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t) -+ -+/** -+ Configures the Ethernet port rate policing for the ingress packets. -+ The current configuration can be -+ retrieved using \ref IFX_PSB6970_QOS_PORT_POLICER_GET. -+ -+ \param IFX_PSB6970_QoS_portPolicerCfg_t Pointer to the rate -+ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for -+ the port. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_POLICER_SET _IOW(IFX_PSB6970_MAGIC, 0x08, IFX_PSB6970_QoS_portPolicerCfg_t) -+ -+/** -+ Read out the Ethernet port rate policing for the ingress packets. -+ The configuration can be set using \ref IFX_PSB6970_QOS_PORT_POLICER_SET. -+ -+ \param IFX_PSB6970_QoS_portPolicerCfg_t Pointer to the rate -+ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for -+ the port. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_PORT_POLICER_GET _IOWR(IFX_PSB6970_MAGIC, 0x09, IFX_PSB6970_QoS_portPolicerCfg_t) -+ -+/** -+ Configure and apply the QoS Multi-field priority classification rules on -+ Ethernet port level. -+ -+ \param IFX_PSB6970_QoS_MfcPortCfg_t Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_MFC_PORT_CFG_SET _IOW(IFX_PSB6970_MAGIC, 0x0A, IFX_PSB6970_QoS_MfcPortCfg_t) -+ -+/** -+ Read out the current status and configuration of the Ethernet port -+ level usage of the QoS Multi-field priority classification rules. -+ -+ \param IFX_PSB6970_QoS_MfcPortCfg_t Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_MFC_PORT_CFG_GET _IOWR(IFX_PSB6970_MAGIC, 0x0B, IFX_PSB6970_QoS_MfcPortCfg_t) -+ -+/** -+ Set a QoS Multi-field priority classification rule. -+ -+ \param IFX_PSB6970_QoS_MfcCfg_t Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_MFC_ADD _IOW(IFX_PSB6970_MAGIC, 0x0C, IFX_PSB6970_QoS_MfcCfg_t) -+ -+/** -+ Remove a QoS Multi-field priority classification rule. -+ -+ \param IFX_PSB6970_QoS_MfcMatchField_t Pointer to a -+ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcMatchField_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_MFC_DEL _IOW(IFX_PSB6970_MAGIC, 0x0D, IFX_PSB6970_QoS_MfcMatchField_t) -+ -+/** -+ Read an entry of the QoS Multi-field priority classification rules. -+ -+ If the parameter 'bInitial=TRUE', the GET operation starts at the beginning -+ of the rule set. Otherwise it continues at the entry that -+ follows the previous rule. -+ The function sets all fields to zero in case the end of the rule set has been reached. -+ To read out the complete rule set, this function can be called in a loop. -+ The Switch API sets 'bLast=IFX_TRUE' when the last entry has been read out. -+ This 'bLast' parameter could be the loop exit criteria. -+ -+ \param IFX_PSB6970_QoS_MfcEntryRead_t Pointer to a -+ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcEntryRead_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_MFC_ENTRY_READ _IOWR(IFX_PSB6970_MAGIC, 0x0E, IFX_PSB6970_QoS_MfcEntryRead_t) -+ -+/** -+ Set the egress storm control for different packet types. -+ It allows configuration of different threshold values for different link types. -+ The current configuration can be read out using \ref IFX_PSB6970_QOS_STORM_GET. -+ -+ \param IFX_PSB6970_QoS_stormCfg_t Pointer to a -+ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_STORM_SET _IOW(IFX_PSB6970_MAGIC, 0x0F, IFX_PSB6970_QoS_stormCfg_t) -+ -+/** -+ Read out the current configuration for the egress storm control. -+ The storm control is used for different packet types. -+ The configuration can be set using \ref IFX_PSB6970_QOS_STORM_SET. -+ -+ \param IFX_PSB6970_QoS_stormCfg_t Pointer to a -+ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_QOS_STORM_GET _IOWR(IFX_PSB6970_MAGIC, 0x10, IFX_PSB6970_QoS_stormCfg_t) -+ -+/*@}*/ /* PSB6970_IOCTL_QOS */ -+ -+/** \addtogroup PSB6970_IOCTL_POWER */ -+/*@{*/ -+ -+/** -+ Set the power management configuration. -+ The parameters can be read using \ref IFX_PSB6970_POWER_MANAGEMENT_GET. -+ -+ \param IFX_PSB6970_powerManagement_t Pointer to \ref IFX_PSB6970_powerManagement_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_POWER_MANAGEMENT_SET _IOW(IFX_PSB6970_MAGIC, 0x11, IFX_PSB6970_powerManagement_t) -+ -+/** -+ Read the power management configuration. -+ The parameters can be modified using \ref IFX_PSB6970_POWER_MANAGEMENT_SET. -+ -+ \param IFX_PSB6970_powerManagement_t Pointer to \ref IFX_PSB6970_powerManagement_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_POWER_MANAGEMENT_GET _IOWR(IFX_PSB6970_MAGIC, 0x12, IFX_PSB6970_powerManagement_t) -+ -+/*@}*/ /* PSB6970_IOCTL_POWER */ -+ -+/** \addtogroup PSB6970_IOCTL_DEBUG */ -+/*@{*/ -+ -+/** -+ Write to an internal register. The register offset defines which register to access -+ in which table. This routine only accesses the M4599_PDI and -+ the ETHSW_PDI of the switch. All PHY registers are accessed -+ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. -+ Note that the switch API implementation checks that the given address is -+ inside the valid address range. It returns with an error in case an invalid -+ address is given. -+ -+ \param IFX_PSB6970_register_t Pointer to \ref IFX_PSB6970_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_REGISTER_SET _IOW(IFX_PSB6970_MAGIC, 0x13, IFX_PSB6970_register_t) -+ -+/** -+ Read an internal register. The register offset defines which register to access -+ in which table. This routine only accesses the M4599_PDI and -+ the ETHSW_PDI of the switch. All PHY registers are accessed -+ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. -+ Note that the switch API implementation checks that the given address is -+ inside the valid address range. It returns with an error in case an invalid -+ address is given. -+ -+ \param IFX_PSB6970_register_t Pointer to \ref IFX_PSB6970_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_PSB6970_REGISTER_GET _IOWR(IFX_PSB6970_MAGIC, 0x14, IFX_PSB6970_register_t) -+ -+/*@}*/ /* PSB6970_IOCTL_DEBUG */ -+ -+#endif /* _IFX_ETHSW_PSB6970_H_ */ -diff --git a/include/switch_api/ifx_ethsw_PSB6970_core.h b/include/switch_api/ifx_ethsw_PSB6970_core.h -new file mode 100644 -index 0000000..a783710 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_PSB6970_core.h -@@ -0,0 +1,182 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_ral.h -+ \remarks PSB6970 Core Layer header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_PSB6970_CORE_H_ -+#define _IFX_ETHSW_PSB6970_CORE_H_ -+ -+#include "ifx_ethsw_api.h" -+#define IFX_PSB6970_MFC_ENTRY_MAX 8 -+#define IFX_PSB6970_MFC_RULES_MAX 24 -+#define IFX_PSB6970_REGISTER_NUMBER_MAX 0x122 -+#define IFX_PSB6970_VLAN_ENTRY_MAX 16 -+#define IFX_PSB6970_PORT_NUMBER_MAX 7 -+#define IFX_PSB6970_AR9_INTSW_PORT_NUMBER 3 -+#define IFX_PSB6970_TANTOSXG_PORT_NUMBER 7 -+#define IFX_AR9_REGISTER_NUMBER_MAX 0x1B4 -+/** Description */ -+typedef struct -+{ -+ /** Transparent Mode */ -+ IFX_boolean_t bTVM; -+ IFX_ETHSW_QoS_Scheduler_t eType; -+ IFX_boolean_t bPHYDown; -+ IFX_boolean_t eFlow; -+}IFX_PSB6970_portConfig_t; -+ -+/** Description */ -+typedef struct -+{ -+ IFX_boolean_t valid; -+ /* VLAN ID */ -+ IFX_uint16_t vid; -+ /* Forward ID */ -+ IFX_uint32_t fid; -+ /* Port Member */ -+ IFX_uint16_t pm; -+ /* Tag Member */ -+ IFX_uint16_t tm; -+}IFX_PSB6970_VLAN_tableEntry_t; -+ -+/** Description */ -+typedef struct -+{ -+ IFX_boolean_t bMF_ethertype; -+ IFX_uint16_t nVCET; -+}IFX_PSB6970_MFC_etherTypeEntry_t; -+typedef struct -+{ -+ IFX_boolean_t bMF_protocol; -+ IFX_uint8_t nPFR; -+}IFX_PSB6970_MFC_protocolEntry_t; -+typedef struct -+{ -+ IFX_boolean_t bMF_port; -+ IFX_boolean_t bPortSrc; -+ IFX_uint16_t nBasePt; -+ IFX_uint8_t nPRange; -+}IFX_PSB6970_MFC_portEntry_t; -+ -+typedef struct { -+ IFX_PSB6970_devType_t eDev; -+ IFX_PSB6970_portConfig_t PortConfig[IFX_PSB6970_PORT_NUMBER_MAX]; -+ IFX_boolean_t bVLAN_Aware; -+ IFX_PSB6970_VLAN_tableEntry_t VLAN_Table[IFX_PSB6970_VLAN_ENTRY_MAX]; -+ IFX_void_t *pRML_Dev; -+#ifdef IFX_ETHSW_API_COC -+ IFX_void_t *pPMCtx; -+#endif -+ IFX_uint8_t nPortNumber; -+ IFX_PSB6970_MFC_etherTypeEntry_t MFC_etherTypeEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; -+ IFX_PSB6970_MFC_protocolEntry_t MFC_protocolEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; -+ IFX_PSB6970_MFC_portEntry_t MFC_portEntrys[IFX_PSB6970_MFC_ENTRY_MAX]; -+ IFX_PSB6970_QoS_MfcCfg_t MFC_RulesEntrys[IFX_PSB6970_MFC_RULES_MAX]; -+ IFX_uint8_t RulesIndex; -+ IFX_uint32_t Registers[IFX_PSB6970_REGISTER_NUMBER_MAX]; -+ IFX_ETHSW_multicastSnoopMode_t eIGMP_Mode; -+ IFX_uint16_t vlan_table_index; -+} IFX_PSB6970_switchDev_t; -+ -+typedef struct -+{ -+ IFX_void_t *pDev; -+ IFX_PSB6970_devType_t eDev; -+}IFX_PSB6970_switchCoreInit_t; -+ -+typedef struct -+{ -+ IFX_uint8_t nTable_Index; -+ IFX_uint8_t nOP; // operation (1:add, 2:delete) -+ IFX_uint16_t nVId; -+ IFX_uint32_t nFId; -+}IFX_PSB6970_VLAN_Filter_registerOperation_t; -+ -+typedef enum -+{ -+ /** 1522 bytes */ -+ IFX_ETHSW_MAXPKTLEN_1522_BYTES = 0, -+ /** 1518 bytes */ -+ IFX_ETHSW_MAXPKTLEN_1518_BYTES = 1, -+ /** 1536 bytes */ -+ IFX_ETHSW_MAXPKTLEN_1536_BYTES = 2, -+ /** Reserved */ -+ IFX_ETHSW_MAXPKTLEN_RESERVED = 3 -+ -+}IFX_ETHSW_maxPacketLength_t; // xxx -+/** Command for access counter */ -+ -+typedef enum -+{ -+ IFX_PSB6970_CAC_INDIRECT_READ = 0, -+ IFX_PSB6970_CAC_GET_PORT_COUNTER = 1, -+ IFX_PSB6970_CAC_RESET_PORT_COUNTER = 2, -+ IFX_PSB6970_CAC_RESET_ALL_COUNTER = 3 -+}IFX_PSB6970_CAC_command_t; -+ -+/** Description */ -+typedef enum -+{ -+ /** Create a new address */ -+ IFX_PSB6970_MACTABLE_ENTRY_CREATE = 0x07, -+ IFX_PSB6970_MACTABLE_ENTRY_OVERWRITE = 0x0F, -+ IFX_PSB6970_MACTABLE_ENTRY_ERASE = 0x1F, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_EMPTY_ADDR = 0x20, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_PORT = 0x29, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_FID = 0x2A, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC = 0x2C, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_AND_FID = 0x2E, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_AND_PORT = 0x2D, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_FID_AND_PORT = 0x2B, -+ IFX_PSB6970_MACTABLE_ENTRY_SEARCH_BY_MAC_FID_AND_PORT = 0x2F, -+ IFX_PSB6970_MACTABLE_INIT_TO_LOCATION = 0x34, -+ IFX_PSB6970_MACTABLE_INIT_TO_FIRST = 0x30 -+}IFX_PSB6970_MAC_tableCommand_t; -+ -+/** Description */ -+typedef enum -+{ -+ /** */ -+ IFX_PSB6970_MAC_COMMAND_OK = 0, -+ IFX_PSB6970_MAC_COMMAND_ALL_ENTRY_USED = 1, -+ IFX_PSB6970_MAC_COMMAND_ENTRY_NOT_FOUND = 2, -+ IFX_PSB6970_MAC_COMMAND_TEMP_STATE = 3, -+ IFX_PSB6970_MAC_COMMAND_ERROR = 5 -+}IFX_PSB6970_MAC_commandResult_t; -+ -+/**********************/ -+/* Function Prototype */ -+/**********************/ -+IFX_return_t IFX_PSB6970_VLAN_awareEnable(IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_VLAN_awareDisable(IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_PHY_PDN_Set(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); -+IFX_return_t IFX_PSB6970_PHY_PDN_Clear(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); -+IFX_return_t IFX_PSB6970_portDisable(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_return_t IFX_PSB6970_portEnable(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_boolean_t IFX_PSB6970_PHY_linkStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_boolean_t IFX_PSB6970_PHY_mediumDetectStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_boolean_t IFX_PSB6970_portLinkStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_return_t IFX_PSB6970_VLAN_Table_Init ( IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_PortConfig_Init ( IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_VLAN_Table_Clear ( IFX_void_t *pDevCtx ); -+IFX_boolean_t IFX_PSB6970_VLAN_Id_Exist ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); -+IFX_return_t IFX_PSB6970_VLAN_Table_Print ( IFX_void_t *pDevCtx ); -+IFX_return_t IFX_PSB6970_PortConfig_Print ( IFX_void_t *pDevCtx ); -+IFX_uint8_t IFX_PSB6970_VLAN_Table_Index_Find ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); -+IFX_uint8_t IFX_PSB6970_VLAN_Table_Entry_Avariable ( IFX_void_t *pDevCtx ); -+IFX_return_t IFX_PSB6970_VLAN_Table_Entry_Set ( IFX_void_t *pDevCtx, IFX_uint8_t table_index, IFX_PSB6970_VLAN_tableEntry_t *pTable_Entry ); -+IFX_return_t IFX_PSB6970_VLAN_Table_Entry_Get ( IFX_void_t *pDevCtx, IFX_uint8_t table_index, IFX_PSB6970_VLAN_tableEntry_t *pTable_Entry ); -+IFX_boolean_t IFX_PSB6970_switchStatusGet(IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_switchDeviceEnable(IFX_void_t *pDevCtx); -+IFX_return_t IFX_PSB6970_switchDeviceDisable(IFX_void_t *pDevCtx); -+IFX_void_t *IFX_PSB6970_SwitchCoreInit(IFX_PSB6970_switchCoreInit_t *pInit ); -+IFX_return_t IFX_PSB6970_SwitchCoreCleanUP(IFX_void_t ); -+#endif /* _IFX_ETHSW_PSB6970_CORE_H_ */ -diff --git a/include/switch_api/ifx_ethsw_PSB6970_ll.h b/include/switch_api/ifx_ethsw_PSB6970_ll.h -new file mode 100644 -index 0000000..5284e37 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_PSB6970_ll.h -@@ -0,0 +1,1722 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef ____INCLUDE_IFX_ETHSW_PSB6970_LL_H -+#define ____INCLUDE_IFX_ETHSW_PSB6970_LL_H -+ -+#include "ifx_ethsw.h" -+#include "ifx_ethsw_PSB6970.h" -+ -+/* Group definitions for Doxygen */ -+/** \defgroup PSB6970_LL Ethernet Switch Application Kernel Interface -+ This chapter describes the entire interface to access and -+ configure the services of the switch module in OS kernel space. */ -+/*@{*/ -+/** \defgroup PSB6970_LL_BRIDGE Ethernet Bridging Functions -+ Ethernet bridging (or switching) is the basic task of the device. It -+ provides individual configurations per port and standard global -+ switch features. -+*/ -+/** \defgroup PSB6970_LL_DEBUG Debug Features -+ TANTOS specific features for system integration and debug sessions. -+*/ -+/** \defgroup PSB6970_LL_MULTICAST Multicast Functions -+ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, -+ MLDv1, and MLDv2. -+*/ -+/** \defgroup PSB6970_LL_OAM Operation, Administration, and Management Functions -+ This chapter summarizes the functions that are provided to monitor the -+ data traffic passing through the device. -+*/ -+/** \defgroup PSB6970_LL_POWER Power Management -+ Configure the TANTOS hardware specific power management. -+*/ -+/** \defgroup PSB6970_LL_QOS Quality of Service Functions -+ Switch and port configuration for Quality of Service (QoS). -+*/ -+/** \defgroup PSB6970_LL_VLAN VLAN Functions -+ This chapter describes VLAN bridging functionality. -+*/ -+/*@}*/ -+ -+/* ------------------------------------------------------------------------- */ -+/* Function Declaration */ -+/* ------------------------------------------------------------------------- */ -+ -+/** \addtogroup PSB6970_LL_BRIDGE */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_EAPOL_RULE_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_8021X_EAPOL_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_EAPOL_RULE_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_8021X_EAPOL_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_8021X_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_8021X_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_CLEAR command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MAC_TableClear(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableAdd_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MAC_TableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableAdd_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MAC_TableEntryQuery(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableQuery_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MAC_TableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRemove_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MAC_TableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRemove_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_BPDU_RULE_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_STP_BPDU_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_BPDU_RULE_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_STP_BPDU_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_STP_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_STP_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_BRIDGE */ -+/** \addtogroup PSB6970_LL_VLAN */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_CREATE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_IdCreate(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdCreate_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_DELETE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an -+ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. -+ -+ \remarks A VLAN ID can only be removed in case it was created by -+ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned -+ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_IdDelete(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdDelete_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_IdGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdGet_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an -+ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter -+ 'nPortId', the switch API implementation fills out the remaining structure -+ elements. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t -+ structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_PortMemberAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberAdd_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_PortMemberRead(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_PortMemberRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRemove_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_RESERVED_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_ReservedAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_RESERVED_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_VLAN_ReservedRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_VLAN */ -+/** \addtogroup PSB6970_LL_QOS */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_CLASS_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_DSCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_CLASS_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_DSCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PCP_CLASS_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PCP_CLASS_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_QOS */ -+/** \addtogroup PSB6970_LL_MULTICAST */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastRouterPortAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouterRead_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+IFX_return_t IFX_PSB6970_MulticastRouterPortRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouterRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+IFX_return_t IFX_PSB6970_MulticastRouterPortRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastSnoopCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastSnoopCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastTableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTableRead_t. -+ -+ \remarks The 'bInitial' parameter is reset during the read operation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastTableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTableRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MulticastTableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_MULTICAST */ -+/** \addtogroup PSB6970_LL_OAM */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_CPU_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_CPU_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_PSB6970_CPU_PortExtendCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_CPU_PortExtendCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CAP_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated capability -+ list structure \ref IFX_ETHSW_cap_t. -+ The switch API implementation fills out the structure with the supported -+ features, based on the provided 'nCapType' parameter. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_PSB6970_CapGet(IFX_void_t *pDevCtx, IFX_ETHSW_cap_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ The structure is filled out by the switch implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_DISABLE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_Disable(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_ENABLE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_Enable(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_HW_INIT command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated initialization structure -+ \ref IFX_ETHSW_HW_Init_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_HW_Init(IFX_void_t *pDevCtx, IFX_ETHSW_HW_Init_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MDIO_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MDIO_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_DATA_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MDIO_DataRead(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_DATA_WRITE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_PSB6970_MDIO_DataWrite(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MONITOR_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MonitorPortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MONITOR_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_MonitorPortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a port configuration -+ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. -+ The parameter 'nPortId' tells the driver which port parameter is requested. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_portCfg_t structure -+ to configure the switch port hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_LINK_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortLinkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_LINK_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortLinkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_PHY_ADDR_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_portPHY_Addr_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortPHY_AddrGet(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Addr_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_PHY_QUERY command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortPHY_Query(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Query_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortRGMII_ClkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortRGMII_ClkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_REDIRECT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortRedirectGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_REDIRECT_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PortRedirectSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_RMON_CLEAR command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a pre-allocated -+ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is -+ an input parameter stating on which port to clear all RMON counters. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_RMON_Clear(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_clear_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_RMON_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated -+ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is -+ an input parameter that describes from which port to read the RMON counter. -+ All remaining structure elements are filled with the counter values. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_RMON_Get(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_cnt_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VERSION_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar* The parameter points to a -+ \ref IFX_ETHSW_version_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+*/ -+IFX_return_t IFX_PSB6970_VersionGet(IFX_void_t *pDevCtx, IFX_ETHSW_version_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_WoL_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_WoL_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_WoL_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_WoL_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_OAM */ -+/** \addtogroup PSB6970_LL_OAM */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_RESET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_PSB6970_reset_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \remarks Not supported for all devices -+*/ -+IFX_return_t IFX_PSB6970_Reset(IFX_void_t *pDevCtx, IFX_PSB6970_reset_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_OAM */ -+/** \addtogroup PSB6970_LL_QOS */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_MFC_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_MfcAdd(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_MFC_DEL command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcMatchField_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_MfcDel(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcMatchField_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_MFC_ENTRY_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS Multi-field classification rule \ref IFX_PSB6970_QoS_MfcEntryRead_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_MfcEntryRead(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcEntryRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_MFC_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_MfcPortCfgGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_MFC_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a QOS Multi-field -+ classification rule \ref IFX_PSB6970_QoS_MfcPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_MfcPortCfgSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_MfcPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_POLICER_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for -+ the port. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortPolicerGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portPolicerCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_POLICER_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ policing parameter \ref IFX_PSB6970_QoS_portPolicerCfg_t for -+ the port. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortPolicerSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portPolicerCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperCfgGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperCfgSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperStrictGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperStrictCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_STRICT_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperStrictCfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperStrictSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperStrictCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperWfqGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_PORT_SHAPER_WFQ_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the rate -+ shaping parameter \ref IFX_PSB6970_QoS_portShaperWFQ_Cfg_t for -+ the port-specific priority queue. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_PortShaperWfqSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_portShaperWFQ_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_STORM_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_StormGet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_stormCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_QOS_STORM_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS storm control configuration \ref IFX_PSB6970_QoS_stormCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_QoS_StormSet(IFX_void_t *pDevCtx, IFX_PSB6970_QoS_stormCfg_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_QOS */ -+/** \addtogroup PSB6970_LL_POWER */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_POWER_MANAGEMENT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_PSB6970_powerManagement_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PowerManagementGet(IFX_void_t *pDevCtx, IFX_PSB6970_powerManagement_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_POWER_MANAGEMENT_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_PSB6970_powerManagement_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_STATUS_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_PowerManagementSet(IFX_void_t *pDevCtx, IFX_PSB6970_powerManagement_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_POWER */ -+/** \addtogroup PSB6970_LL_DEBUG */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_REGISTER_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_PSB6970_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_RegisterGet(IFX_void_t *pDevCtx, IFX_PSB6970_register_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_PSB6970_REGISTER_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_PSB6970_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_PSB6970_RegisterSet(IFX_void_t *pDevCtx, IFX_PSB6970_register_t *pPar); -+ -+/*@}*/ /* PSB6970_LL_DEBUG */ -+#endif /* ____INCLUDE_IFX_ETHSW_PSB6970_LL_H */ -diff --git a/include/switch_api/ifx_ethsw_api.h b/include/switch_api/ifx_ethsw_api.h -new file mode 100644 -index 0000000..724d0ee ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_api.h -@@ -0,0 +1,172 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_api.h" -+ \remarks -+ *****************************************************************************/ -+ -+#ifndef _IFX_SWITCH_API_H -+#define _IFX_SWITCH_API_H -+ -+#include "ifx_ethsw.h" -+#include "ifx_ethsw_PSB6970.h" -+#include "ifx_ethsw_ll_fkt.h" -+#include "regmapper.h" -+#include "Tantos3G.h" -+#include "AR9.h" -+#include "ifx_ethsw_flow.h" -+#include "VR9_switch.h" -+#include "VR9_top.h" -+ -+#ifdef IFXOS_SUPPORT -+ #define LINUX -+ /** This is the unsigned long datatype. -+ On 32bit systems it is 4 byte wide. -+ */ -+ typedef unsigned long IFX_ulong_t; -+ /** This is the size data type (32 or 64 bit) */ -+ typedef IFX_ulong_t IFX_size_t; -+ #include "ifxos_print.h" -+ #include "ifxos_thread.h" -+ #include "ifxos_memory_alloc.h" -+#else -+#ifdef __KERNEL__ -+ #include <asm/delay.h> -+ #include <linux/slab.h> -+ #include <linux/string.h> -+#endif -+#endif -+ -+#ifndef IFXOS_SUPPORT -+ #define IFXOS_PRINT_INT_RAW(fmt, args...) printk(fmt, ##args) -+ #define IFXOS_DBG_PRINT_USR(fmt, args...) printk(KERN_DEBUG fmt "\r", ##args) -+ #define IFXOS_USecSleep(n) udelay(n) -+ #define IFXOS_BlockAlloc(n) kmalloc(n, GFP_KERNEL) -+ #define IFXOS_BlockFree(n) kfree(n) -+#endif -+ -+#define PARAM_BUFFER_SIZE 2048 -+//#define GET_BITS(x, msb, lsb) (((x) & ((1 << ((msb) + 1)) - 1)) >> (lsb)) -+#define SET_BITS(x, msb, lsb, value) (((x) & ~(((1 << ((msb) + 1)) - 1) ^ ((1 << (lsb)) - 1))) | (((value) & ((1 << (1 + (msb) - (lsb))) - 1)) << (lsb))) -+#define IFX_ETHSW_DEV_MAX 2 -+#define SWITCH_API_MODULE_NAME "IFX ETHSW SWITCH API" -+#define SWITCH_API_DRIVER_VERSION "1.1.8.5" -+#define MICRO_CODE_VERSION "212" -+ -+extern unsigned int g_debug; -+#define IFX_ETHSW_DEBUG_PRINT(fmt, args...) -+ -+union ifx_sw_param -+{ -+ /* Ethernet Bridging Functions*/ -+ IFX_ETHSW_MAC_tableAdd_t MAC_tableAdd; -+ IFX_ETHSW_MAC_tableRead_t MAC_tableRead; -+ IFX_ETHSW_MAC_tableRemove_t MAC_tableRemove; -+ IFX_ETHSW_portCfg_t portcfg; -+ IFX_ETHSW_STP_portCfg_t STP_portCfg; -+ IFX_ETHSW_STP_BPDU_Rule_t STP_BPDU_Rule; -+ /* VLAN Functions */ -+ IFX_ETHSW_VLAN_IdCreate_t vlan_IdCreate; -+ IFX_ETHSW_VLAN_IdDelete_t vlan_IdDelete; -+ IFX_ETHSW_VLAN_IdGet_t vlan_IdGet; -+ IFX_ETHSW_VLAN_portCfg_t vlan_portcfg; -+ IFX_ETHSW_VLAN_portMemberAdd_t vlan_portMemberAdd; -+ IFX_ETHSW_VLAN_portMemberRead_t vlan_portMemberRead; -+ IFX_ETHSW_VLAN_portMemberRemove_t vlan_portMemberRemove; -+ IFX_ETHSW_VLAN_reserved_t vlan_Reserved; -+ IFX_ETHSW_VLAN_IdGet_t vlan_VidFid; -+ /* Operation, Administration, and Management Functions */ -+ IFX_ETHSW_cfg_t cfg_Data; -+ IFX_ETHSW_MDIO_cfg_t mdio_cfg; -+ IFX_ETHSW_MDIO_data_t mdio_Data; -+ IFX_ETHSW_portLinkCfg_t portlinkcfgGet; -+ IFX_ETHSW_portLinkCfg_t portlinkcfgSet; -+ IFX_ETHSW_portPHY_Addr_t phy_addr; -+ IFX_ETHSW_portRGMII_ClkCfg_t portRGMII_clkcfg; -+ IFX_ETHSW_CPU_PortExtendCfg_t portextendcfg; -+ IFX_ETHSW_portRedirectCfg_t portRedirectData; -+ IFX_ETHSW_RMON_clear_t RMON_clear; -+ IFX_ETHSW_RMON_cnt_t RMON_cnt; -+ IFX_FLOW_RMON_extendGet_t RMON_ExtendGet; -+ IFX_ETHSW_monitorPortCfg_t monitorPortCfg; -+ IFX_ETHSW_cap_t cap; -+ IFX_ETHSW_portPHY_Query_t phy_Query; -+ IFX_ETHSW_CPU_PortCfg_t CPU_PortCfg; -+ IFX_ETHSW_version_t Version; -+ IFX_PSB6970_reset_t Reset; -+ IFX_ETHSW_HW_Init_t HW_Init; -+ IFX_ETHSW_8021X_portCfg_t PNAC_portCfg; -+ IFX_ETHSW_8021X_EAPOL_Rule_t PNAC_EAPOL_Rule; -+ /* Multicast Functions */ -+ IFX_ETHSW_multicastRouter_t multicast_RouterPortAdd; -+ IFX_ETHSW_multicastRouter_t multicast_RouterPortRemove; -+ IFX_ETHSW_multicastRouterRead_t multicast_RouterPortRead; -+ IFX_ETHSW_multicastTable_t multicast_TableEntryAdd; -+ IFX_ETHSW_multicastTable_t multicast_TableEntryRemove; -+ IFX_ETHSW_multicastTableRead_t multicast_TableEntryRead; -+ IFX_ETHSW_multicastSnoopCfg_t multicast_SnoopCfgSet; -+ IFX_ETHSW_multicastSnoopCfg_t multicast_SnoopCfgGet; -+ /* Quality of Service Functions */ -+ IFX_ETHSW_QoS_portCfg_t qos_portcfg; -+ IFX_ETHSW_QoS_queuePort_t qos_queueport; -+ IFX_ETHSW_QoS_DSCP_ClassCfg_t qos_dscpclasscfgget; -+ IFX_ETHSW_QoS_DSCP_ClassCfg_t qos_dscpclasscfgset; -+ IFX_ETHSW_QoS_PCP_ClassCfg_t qos_pcpclasscfgget; -+ IFX_ETHSW_QoS_PCP_ClassCfg_t qos_pcpclasscfgset; -+ IFX_PSB6970_QoS_portShaperCfg_t qos_portShapterCfg; -+ IFX_PSB6970_QoS_portShaperStrictCfg_t qos_portShapterStrictCfg; -+ IFX_PSB6970_QoS_portShaperWFQ_Cfg_t qos_portShapterWFQ_Cfg; -+ IFX_PSB6970_QoS_portPolicerCfg_t qos_portPolicerCfg; -+ IFX_PSB6970_QoS_stormCfg_t qos_stormCfg; -+ IFX_PSB6970_QoS_MfcPortCfg_t qos_MfcPortCfg; -+ IFX_PSB6970_QoS_MfcCfg_t qos_MfcCfg; -+ IFX_PSB6970_QoS_MfcMatchField_t qos_MfcMatchField; -+ IFX_PSB6970_QoS_MfcEntryRead_t qos_MfcEntryRead; -+ IFX_ETHSW_QoS_ClassDSCP_Cfg_t qos_classdscpcfgget; -+ IFX_ETHSW_QoS_ClassDSCP_Cfg_t qos_classdscpcfgset; -+ IFX_ETHSW_QoS_ClassPCP_Cfg_t qos_classpcpcfgget; -+ IFX_ETHSW_QoS_ClassPCP_Cfg_t qos_classpcpcfgset; -+ IFX_ETHSW_QoS_ShaperCfg_t qos_shappercfg; -+ IFX_ETHSW_QoS_ShaperQueue_t qos_shapperqueue; -+ IFX_ETHSW_QoS_stormCfg_t qos_stormcfg; -+ IFX_ETHSW_QoS_schedulerCfg_t qos_schedulecfg; -+ IFX_ETHSW_QoS_WRED_Cfg_t qos_wredcfg; -+ IFX_ETHSW_QoS_WRED_QueueCfg_t qos_wredqueuecfg; -+ IFX_ETHSW_QoS_meterCfg_t qos_metercfg; -+ IFX_ETHSW_QoS_meterPort_t qos_meterport; -+ IFX_ETHSW_QoS_meterPortGet_t qos_meterportget; -+ IFX_ETHSW_QoS_portRemarkingCfg_t qos_portremarking; -+ /* Power Management Functions */ -+ IFX_PSB6970_powerManagement_t power_management; -+ /* Packet Classification Engine */ -+ IFX_FLOW_PCE_rule_t pce_rule; -+ IFX_FLOW_PCE_ruleDelete_t pce_ruledelete; -+ /* Debug Features */ -+#if defined(AR9) || defined(DANUBE) || defined(AMAZON_SE) -+ IFX_PSB6970_register_t register_access; -+#elif ( defined(VR9) || defined(AR10) || defined(HN1) ) -+ IFX_FLOW_register_t register_access; -+#endif -+}; -+ -+typedef enum -+{ -+ IFX_PSB6970_DEV_AR9 = 0, -+ IFX_PSB6970_DEV_TANTOS_3G, -+ IFX_PSB6970_DEV_TANTOS_0G, -+ IFX_PSB6970_DEV_MAX -+} IFX_PSB6970_devType_t; -+ -+typedef enum -+{ -+ IFX_FLOW_DEV_INT = 0, -+ IFX_FLOW_DEV_MAX -+} IFX_FLOW_devType_t; -+ -+#endif -diff --git a/include/switch_api/ifx_ethsw_core_platform.h b/include/switch_api/ifx_ethsw_core_platform.h -new file mode 100644 -index 0000000..51adcf6 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_core_platform.h -@@ -0,0 +1,94 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_core_platform.h -+ \remarks Platform dependancy Core Layer header file, for Infineon Ethernet -+ switch drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_CORE_PLATFORM_H_ -+#define _IFX_ETHSW_CORE_PLATFORM_H_ -+ -+#include "ifx_types.h" -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+#define SW_WRITE_REG32(data,addr) IFX_REG_W32((data), (volatile unsigned int *)addr) -+#define SW_READ_REG32(addr) IFX_REG_R32((volatile unsigned int *)addr) -+ -+#define VRX_RCU_BASE_ADDR (0xBF203000) -+#define VRX_INT_BASE_ADDR (0xBF107000) -+#define GSWIP_BASE_ADDR (0xBE108000) -+#define GSWIP_TOP_BASE_ADDR (GSWIP_BASE_ADDR + (0x0C40 * 4)) -+#define GSWIP_REG_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) -+ -+//#define VR9_CHIP_ID_MAGIC_NUMBER (0x101C0083) -+/* GPHY0 Firmware Base Address Register */ -+#define GFS_ADD0 (VRX_RCU_BASE_ADDR + 0x20) -+#if defined(CONFIG_VR9) -+/* GPHY1 Firmware Base Address Register */ -+#define GFS_ADD1 (VRX_RCU_BASE_ADDR + 0x68) -+#endif /*CONFIG_VR9 */ -+#if defined(CONFIG_AR10) -+/* GPHY1 Firmware Base Address Register */ -+#define GFS_ADD1 (VRX_RCU_BASE_ADDR + 0x58) -+/* GPHY2 Firmware Base Address Register */ -+#define GFS_ADD2 (VRX_RCU_BASE_ADDR + 0xAC) -+#endif /*CONFIG_AR10 */ -+/* Chip Identification Register */ -+#define MPS_CHIPID (VRX_INT_BASE_ADDR + 0x344) -+/* GPHY01 MDIO Address Register */ -+#define GFMDIO_ADD (VRX_RCU_BASE_ADDR + 0x44) -+/* PHY Address Register PORT 5 */ -+#define PHY_ADDR_5 (GSWIP_BASE_ADDR + (0xC50 * 4)) -+/* PHY Address Register PORT 4 */ -+#define PHY_ADDR_4 (GSWIP_BASE_ADDR + (0xC51 * 4)) -+/* PHY Address Register PORT 3 */ -+#define PHY_ADDR_3 (GSWIP_BASE_ADDR + (0xC52 * 4)) -+/* PHY Address Register PORT 2 */ -+#define PHY_ADDR_2 (GSWIP_BASE_ADDR + (0xC53 * 4)) -+/* PHY Address Register PORT 1 */ -+#define PHY_ADDR_1 (GSWIP_BASE_ADDR + (0xC54 * 4)) -+/* PHY Address Register PORT 0 */ -+#define PHY_ADDR_0 (GSWIP_BASE_ADDR + (0xC55 * 4)) -+/* Transmit and Receive Buffer Control Register */ -+#define MAC_PDI_CTRL_6 (GSWIP_BASE_ADDR + (0x951 * 4)) -+/* Transmit and Receive Buffer Control Register */ -+#define PMAC_RX_IPG (GSWIP_BASE_ADDR + (0xCCB * 4)) -+/** MDC Clock Configuration Register 0 */ -+#define MDC_CFG_0_REG (GSWIP_TOP_BASE_ADDR + (0x0B * 4)) -+#define MDC_CFG_0_PEN_SET(port) (0x1 << port ) -+#define MDC_CFG_0_PEN_GET(port, reg_data) ((reg_data >> port ) & 0x1 ) -+/** MDC Clock Configuration Register 1 */ -+#define MDC_CFG_1_REG -+/** MDIO Control Register */ -+#define MDIO_CTRL_REG (GSWIP_TOP_BASE_ADDR + (8 * 4)) -+/** MDIO Busy*/ -+#define MDIO_CTRL_MBUSY 0x1000 -+#define MDIO_CTRL_OP_MASK 0x0C00 -+#define MDIO_CTRL_OP_WR 0x0400 -+#define MDIO_CTRL_OP_RD 0x0800 -+#define MDIO_CTRL_PHYAD_SET(arg) ((arg & 0x1F) << 5) -+#define MDIO_CTRL_PHYAD_GET(arg) ( (arg >> 5 ) & 0x1F) -+#define MDIO_CTRL_REGAD(arg) ( arg & 0x1F) -+/** MDIO Read Data Register */ -+#define MDIO_READ_REG (GSWIP_TOP_BASE_ADDR + (9 * 4)) -+#define MDIO_READ_RDATA(arg) (arg & 0xFFFF) -+/** MDIO Write Data Register */ -+#define MDIO_WRITE_REG (GSWIP_TOP_BASE_ADDR + (0x0A * 4)) -+#define MDIO_READ_WDATA(arg) (arg & 0xFFFF) -+ -+/**********************/ -+/* Function Prototype */ -+/**********************/ -+IFX_int32_t platform_device_reset_trigger(IFX_void_t); -+IFX_int32_t platform_device_reset_release(IFX_void_t); -+IFX_int32_t platform_device_init(IFX_void_t *pDevCtx); -+ -+#endif /* _IFX_ETHSW_CORE_PLATFORM_H_ */ -diff --git a/include/switch_api/ifx_ethsw_flow.h b/include/switch_api/ifx_ethsw_flow.h -new file mode 100644 -index 0000000..d556133 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_flow.h -@@ -0,0 +1,845 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef _IFX_FLOW_FLOW_H_ -+#define _IFX_FLOW_FLOW_H_ -+ -+#include "ifx_types.h" -+#include "ifx_ethsw.h" -+ -+/* =================================== */ -+/* Global typedef forward declarations */ -+/* =================================== */ -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+ -+/* IOCTL MAGIC */ -+#define IFX_FLOW_MAGIC ('F') -+ -+/* Group definitions for Doxygen */ -+/** \defgroup FLOW_IOCTL XWAY VRX200 and XWAY GRX200 Family Specific Ethernet Switch API -+ This chapter describes the XWAY VRX200 and XWAY GRX200 Family specific -+ interfaces for accessing and configuring the services of the Ethernet switch module. -+ These features are a device-specific enhancement of the generic Switch API part. */ -+/*@{*/ -+ -+/** \defgroup FLOW_IOCTL_DEBUG Debug Features -+ XWAY VRX200 and XWAY GRX200 Family specific features for system -+ integration and debug sessions. -+*/ -+/** \defgroup FLOW_IOCTL_IRQ Interrupt Handling -+ Configure XWAY VRX200 and XWAY GRX200 Family specific hardware -+ support to generate interrupts -+ and read out the interrupt sources. -+*/ -+/** \defgroup FLOW_IOCTL_OAM Operation, Administration, and Management Functions -+ This chapter summarizes the functions that are provided to monitor the -+ data traffic passing through the device. -+*/ -+/** \defgroup FLOW_IOCTL_CLASSUNIT Packet Classification Engine -+ Configures and controls the classification unit of the XWAY VRX200 -+ and XWAY GRX200 Family hardware. -+*/ -+ -+/*@}*/ -+ -+/* -------------------------------------------------------------------------- */ -+/* Structure and Enumeration Type Defintions */ -+/* -------------------------------------------------------------------------- */ -+ -+/** \addtogroup FLOW_IOCTL_DEBUG */ -+/*@{*/ -+ -+/** Register access parameter to directly read or write switch -+ internal registers. -+ Used by \ref IFX_FLOW_REGISTER_SET and \ref IFX_FLOW_REGISTER_GET. */ -+typedef struct -+{ -+ /** Register Address Offset for read or write access. */ -+ IFX_uint16_t nRegAddr; -+ /** Value to write to or read from 'nRegAddr'. */ -+ IFX_uint16_t nData; -+}IFX_FLOW_register_t; -+ -+/*@}*/ /* FLOW_IOCTL_DEBUG */ -+ -+/** \addtogroup FLOW_IOCTL_IRQ */ -+/*@{*/ -+ -+/** Interrupt Source Selector. -+ Used by \ref IFX_FLOW_irq_t. */ -+typedef enum -+{ -+ /** Wake-on-LAN Interrupt. -+ The parameter 'nPortId' specifies the relative MAC port. */ -+ IFX_FLOW_IRQ_WOL = 0, -+ /** Port Limit Alert Interrupt. This interrupt is asserted when the number -+ of learned MAC addresses exceeds the configured limit for -+ the ingress port. -+ The parameter 'nPortId' specifies the relative MAC port. */ -+ IFX_FLOW_IRQ_LIMIT_ALERT = 1, -+ /** Port Lock Alert Interrupt. -+ This interrupt is asserted when a source MAC address is learned on a -+ locked port and is received on another port. -+ The parameter 'nPortId' specifies the relative MAC port. */ -+ IFX_FLOW_IRQ_LOCK_ALERT = 2 -+}IFX_FLOW_irqSrc_t; -+ -+/** Interrupt bits. Depending on the hardware device type, not all interrupts might be available. -+ Used by \ref IFX_FLOW_IRQ_MASK_GET, \ref IFX_FLOW_IRQ_MASK_SET, -+ \ref IFX_FLOW_IRQ_GET and \ref IFX_FLOW_IRQ_STATUS_CLEAR. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware dependent. -+ An error code is delivered if the selected port is not -+ available. This port parameter is needed for some interrupts -+ that are specified by 'nIrqSrc'. For all other interrupts, this -+ parameter is "don't care". */ -+ IFX_uint32_t nPortId; -+ /** Interrupt source. */ -+ IFX_FLOW_irqSrc_t eIrqSrc; -+}IFX_FLOW_irq_t; -+ -+/*@}*/ /* FLOW_IOCTL_IRQ */ -+ -+/** \addtogroup FLOW_IOCTL_CLASSUNIT */ -+/*@{*/ -+ -+/** Rule selection for IPv4/IPv6. -+ Used by \ref IFX_FLOW_PCE_pattern_t. */ -+typedef enum -+{ -+ /** Rule Pattern for IP selection disabled. */ -+ IFX_FLOW_PCE_IP_DISABLED = 0, -+ /** Rule Pattern for IPv4. */ -+ IFX_FLOW_PCE_IP_V4 = 1, -+ /** Rule Pattern for IPv6. */ -+ IFX_FLOW_PCE_IP_V6 = 2 -+}IFX_FLOW_PCE_IP_t; -+ -+/** Packet Classification Engine Pattern Configuration. -+ Used by \ref IFX_FLOW_PCE_rule_t. */ -+typedef struct -+{ -+ /** Index */ -+ IFX_int32_t nIndex; -+ -+ /** Index is used (enabled) or set to unused (disabled) */ -+ IFX_boolean_t bEnable; -+ -+ /** Port ID used */ -+ IFX_boolean_t bPortIdEnable; -+ /** Port ID */ -+ IFX_uint8_t nPortId; -+ -+ /** DSCP value used */ -+ IFX_boolean_t bDSCP_Enable; -+ /** DSCP value */ -+ IFX_uint8_t nDSCP; -+ -+ /** PCP value used */ -+ IFX_boolean_t bPCP_Enable; -+ /** PCP value */ -+ IFX_uint8_t nPCP; -+ -+ /** Packet length used */ -+ IFX_boolean_t bPktLngEnable; -+ /** Packet length */ -+ IFX_uint16_t nPktLng; -+ /** Packet length Range */ -+ IFX_uint16_t nPktLngRange; -+ -+ /** Destination MAC address used */ -+ IFX_boolean_t bMAC_DstEnable; -+ /** Destination MAC address */ -+ IFX_uint8_t nMAC_Dst[6]; -+ /** Destination MAC address mask. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint16_t nMAC_DstMask; -+ -+ /** Source MAC address used */ -+ IFX_boolean_t bMAC_SrcEnable; -+ /** Source MAC address */ -+ IFX_uint8_t nMAC_Src[6]; -+ /** Source MAC address mask. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint16_t nMAC_SrcMask; -+ -+ /** MSB Application field used */ -+ IFX_boolean_t bAppDataMSB_Enable; -+ /** MSB Application field. -+ The first 2 bytes of the packet content following the IP header -+ for TCP/UDP packets (source port field), or the first 2 bytes of packet content -+ following the Ethertype for non-IP packets. Any part of this -+ content can be masked-out by a programmable bit -+ mask 'nAppMaskRangeMSB'. */ -+ IFX_uint16_t nAppDataMSB; -+ /** MSB Application mask/range selection. -+ If set to IFX_TRUE, the field 'nAppMaskRangeMSB' is used as a -+ range parameter, otherwise it is used as a nibble mask field. */ -+ IFX_boolean_t bAppMaskRangeMSB_Select; -+ /** MSB Application mask/range. When used as a range parameter, -+ 1 bit represents 1 nibble mask of the 'nAppDataMSB' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint16_t nAppMaskRangeMSB; -+ -+ /** LSB Application used */ -+ IFX_boolean_t bAppDataLSB_Enable; -+ /** LSB Application field. -+ The following 2 bytes of the packet behind the 'nAppDataMSB' field. -+ This is the destination port field for TCP/UDP packets, -+ or byte 3 and byte 4 of the packet content following the Ethertype -+ for non-IP packets. Any part of this content can be masked-out -+ by a programmable bit mask 'nAppMaskRangeLSB'. */ -+ IFX_uint16_t nAppDataLSB; -+ /** LSB Application mask/range selection. -+ If set to IFX_TRUE, the field 'nAppMaskRangeLSB' is used as -+ a range parameter, otherwise it is used as a nibble mask field. */ -+ IFX_boolean_t bAppMaskRangeLSB_Select; -+ /** LSB Application mask/range. When used as a range parameter, -+ 1 bit represents 1 nibble mask of the 'nAppDataLSB' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint16_t nAppMaskRangeLSB; -+ -+ /** DIP Selection. */ -+ IFX_FLOW_PCE_IP_t eDstIP_Select; -+ /** DIP */ -+ IFX_ETHSW_IP_t nDstIP; -+ /** DIP Nibble Mask. -+ 1 bit represents 1 nibble mask of the 'nDstIP' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint32_t nDstIP_Mask; -+ -+ /** SIP Selection. */ -+ IFX_FLOW_PCE_IP_t eSrcIP_Select; -+ /** SIP */ -+ IFX_ETHSW_IP_t nSrcIP; -+ /** SIP Nibble Mask. -+ 1 bit represents 1 nibble mask of the 'nSrcIP' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint32_t nSrcIP_Mask; -+ -+ /** Ethertype used. */ -+ IFX_boolean_t bEtherTypeEnable; -+ /** Ethertype */ -+ IFX_uint16_t nEtherType; -+ /** Ethertype Mask. -+ 1 bit represents 1 nibble mask of the 'nEtherType' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint16_t nEtherTypeMask; -+ -+ /** IP protocol used */ -+ IFX_boolean_t bProtocolEnable; -+ /** IP protocol */ -+ IFX_uint8_t nProtocol; -+ /** IP protocol Mask. -+ 1 bit represents 1 nibble mask of the 'nProtocol' field. -+ Please clear the bits of the nibbles that are not marked out and set all other bits. -+ The LSB bit represents the lowest data nibble, the next bit the next nibble, -+ and so on. */ -+ IFX_uint8_t nProtocolMask; -+ -+ /** PPPoE used. */ -+ IFX_boolean_t bSessionIdEnable; -+ /** PPPoE */ -+ IFX_uint16_t nSessionId; -+ -+ /** VLAN used. */ -+ IFX_boolean_t bVid; -+ /** VLAN */ -+ IFX_uint16_t nVid; -+}IFX_FLOW_PCE_pattern_t; -+ -+/** IGMP Snooping Control. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disabled. IGMP Snooping is disabled. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_DISABLE = 0, -+ /** Default. Regular Packet. No IGMP Snooping action required. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_REGULAR = 1, -+ /** IGMP Report/Join Message. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_REPORT = 2, -+ /** IGMP Leave Message. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_LEAVE = 3, -+ /** Router Solicitation/Advertisement message. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_AD = 4, -+ /** IGMP Query Message. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY = 5, -+ /** IGMP Group Specific Query Message. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY_GROUP = 6, -+ /** IGMP General Query message without Router Solicitation. */ -+ IFX_FLOW_PCE_ACTION_IGMP_SNOOP_QUERY_NO_ROUTER = 7 -+}IFX_FLOW_PCE_ActionIGMP_Snoop_t; -+ -+/** MAC Address Learning control. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** MAC Address Learning action is disabled. MAC address learning is -+ not influenced by this rule. */ -+ IFX_FLOW_PCE_ACTION_LEARNING_DISABLE = 0, -+ /** Learning is based on the forwarding decision. If the packet is discarded, -+ the address is not learned. If the packet is forwarded to any egress port, -+ the address is learned. */ -+ IFX_FLOW_PCE_ACTION_LEARNING_REGULAR = 1, -+ /** Force No Learning. The address is not learned; forwarding decision -+ ignored. */ -+ IFX_FLOW_PCE_ACTION_LEARNING_FORCE_NOT = 2, -+ /** Force Learning. The address is learned, the forwarding decision ignored. -+ Note: The MAC Learning Control signals delivered to Port-Map filtering -+ and combined with Final Forwarding Decision. The result is used as a -+ feedback for MAC Address learning in the Bridging Table. */ -+ IFX_FLOW_PCE_ACTION_LEARNING_FORCE = 3 -+}IFX_FLOW_PCE_ActionLearning_t; -+ -+/** Flow Meter Assignment control. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Action Disable. */ -+ IFX_FLOW_PCE_ACTION_METER_DISABLE = 0, -+ /** Action Enable. Assign Flow-Meter-Num to Meter-ID-0. */ -+ IFX_FLOW_PCE_ACTION_METER_1 = 1, -+ /** Action Enable. Assign Flow-Meter-Num to Meter-ID-1. */ -+ IFX_FLOW_PCE_ACTION_METER_2 = 2, -+ /** Action Enable. Assign pair of meters: Flow-Meter-Num to Meter-ID-0. -+ Flow-Meter-Num+1 to Meter-ID-1. */ -+ IFX_FLOW_PCE_ACTION_METER_1_2 = 3 -+}IFX_FLOW_PCE_ActionMeter_t; -+ -+/** Traffic Class Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disabled. Traffic class action is disabled. */ -+ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_DISABLE = 0, -+ /** Regular Class. Traffic class action is enabled and the CoS -+ classification traffic class is used. */ -+ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_REGULAR = 1, -+ /** Alternative Class. Traffic class action is enabled and the -+ class of the 'nTrafficClassAlter' field is used. */ -+ IFX_FLOW_PCE_ACTION_TRAFFIC_CLASS_ALTERNATIVE = 2, -+}IFX_FLOW_PCE_ActionTrafficClass_t; -+ -+/** Interrupt Control Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disabled. Interrupt Control Action is disabled for this rule. */ -+ IFX_FLOW_PCE_ACTION_IRQ_DISABLE = 0, -+ /** Regular Packet. The Interrupt Control Action is enabled, the packet is -+ treated as a regular packet and no interrupt event is generated. */ -+ IFX_FLOW_PCE_ACTION_IRQ_REGULAR = 1, -+ /** Interrupt Event. The Interrupt Control Action is enabled and an -+ interrupt event is generated. */ -+ IFX_FLOW_PCE_ACTION_IRQ_EVENT = 2 -+}IFX_FLOW_PCE_ActionIrq_t; -+ -+/** Cross State Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disable. The Cross State Action is disabled. */ -+ IFX_FLOW_PCE_ACTION_CROSS_STATE_DISABLE = 0, -+ /** Regular Packet. The Cross State Action is enabled and the packet is -+ treated as a non-Cross-State packet (regular packet). Therefore it does -+ not ignore Port-State filtering rules. */ -+ IFX_FLOW_PCE_ACTION_CROSS_STATE_REGULAR = 1, -+ /** Cross-State packet. The Cross State Action is enabled and the packet is -+ treated as a Cross-State packet. It ignores the Port-State -+ filtering rules. */ -+ IFX_FLOW_PCE_ACTION_CROSS_STATE_CROSS = 2 -+}IFX_FLOW_PCE_ActionCrossState_t; -+ -+/** Critical Frame Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disable. The Critical Frame Action is disabled. */ -+ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_DISABLE = 0, -+ /** Regular Packet. The Critical Frame Action is enabled and the packet is -+ treated as a non-Critical Frame. */ -+ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_REGULAR = 1, -+ /** Critical Packet. The Critical Frame Action is enabled and the packet is -+ treated as a Critical Frame. */ -+ IFX_FLOW_PCE_ACTION_CRITICAL_FRAME_CRITICAL = 2 -+}IFX_FLOW_PCE_ActionCriticalFrame_t; -+ -+/** Timestamp Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disable. Timestamp Action is disabled for this rule. */ -+ IFX_FLOW_PCE_ACTION_TIMESTAMP_DISABLE = 0, -+ /** Regular Packet. The Timestamp Action is enabled for this rule. -+ The packet is treated as a regular packet and no timing information -+ is stored. */ -+ IFX_FLOW_PCE_ACTION_TIMESTAMP_REGULAR = 1, -+ /** Receive/Transmit Timing packet. Ingress and Egress Timestamps for -+ this packet should be stored. */ -+ IFX_FLOW_PCE_ACTION_TIMESTAMP_STORED = 2 -+}IFX_FLOW_PCE_ActionTimestamp_t; -+ -+/** Forwarding Group Action Selector. -+ This flow table action and the 'bFlowID_Action' action -+ can be used exclusively. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disable. Forwarding Group Action is disabled. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_DISABLE = 0, -+ /** Regular Packet. Forwarding Action enabled. Select Default -+ Port-Map (result of Default Forwarding Classification). */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_REGULAR = 1, -+ /** Discard. Discard the packets. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_DISCARD = 2, -+ /** Forward to the CPU port. This requires that the CPU port is previously -+ set by calling \ref IFX_ETHSW_CPU_PORT_CFG_SET. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_CPU = 3, -+ /** Forward to a portmap, selected by the parameter 'nForwardPortMap'. -+ Please note that this feature is not supported by all -+ hardware platforms. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_ALTERNATIVE = 4, -+ /** The packet is treated as Multicast Router -+ Solicitation/Advertisement or Query packet. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_MULTICAST_ROUTER = 5, -+ /** The packet is interpreted as Multicast packet and learned in the -+ multicast group table. */ -+ IFX_FLOW_PCE_ACTION_PORTMAP_MULTICAST_HW_TABLE = 6 -+}IFX_FLOW_PCE_ActionPortmap_t; -+ -+/** VLAN Group Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disabled. The VLAN Action is disabled. */ -+ IFX_FLOW_PCE_ACTION_VLAN_DISABLE = 0, -+ /** Regular VLAN. VLAN Action enabled. Select Default VLAN ID. */ -+ IFX_FLOW_PCE_ACTION_VLAN_REGULAR = 1, -+ /** Alternative VLAN. VLAN Action enabled. -+ Select Alternative VLAN as configured in 'nVLAN_Id'. It requires that -+ this VLAN ID is configured by -+ calling \ref IFX_ETHSW_VLAN_ID_CREATE in advance. */ -+ IFX_FLOW_PCE_ACTION_VLAN_ALTERNATIVE = 2 -+}IFX_FLOW_PCE_ActionVLAN_t; -+ -+/** Cross VLAN Action Selector. -+ Used by \ref IFX_FLOW_PCE_action_t. */ -+typedef enum -+{ -+ /** Disabled. The Cross VLAN Action is disabled. */ -+ IFX_FLOW_PCE_ACTION_CROSS_VLAN_DISABLE = 0, -+ /** Regular VLAN Packet. Do not ignore VLAN filtering rules. */ -+ IFX_FLOW_PCE_ACTION_CROSS_VLAN_REGULAR = 1, -+ /** Cross-VLAN packet. Ignore VLAN filtering rules.*/ -+ IFX_FLOW_PCE_ACTION_CROSS_VLAN_CROSS = 2 -+}IFX_FLOW_PCE_ActionCrossVLAN_t; -+ -+/** Packet Classification Engine Action Configuration. -+ Used by \ref IFX_FLOW_PCE_rule_t. */ -+typedef struct -+{ -+ /** Action "Traffic Class" Group. -+ Traffic class action enable */ -+ IFX_FLOW_PCE_ActionTrafficClass_t eTrafficClassAction; -+ /** Alternative Traffic class */ -+ IFX_uint8_t nTrafficClassAlternate; -+ -+ /** Action "IGMP Snooping" Group. -+ IGMP Snooping control and enable. Please note that the 'nPortMapAction' -+ configuration is ignored in case the IGMP snooping is enabled. -+ Here, on read operations, -+ 'nPortMapAction = IFX_FLOW_PCE_ACTION_PORTMAP_DISABLE' is returned. */ -+ IFX_FLOW_PCE_ActionIGMP_Snoop_t eSnoopingTypeAction; -+ -+ /** Action "Learning" Group. -+ Learning action control and enable */ -+ IFX_FLOW_PCE_ActionLearning_t eLearningAction; -+ -+ /** Action "Interrupt" Group. -+ Interrupt action generate and enable */ -+ IFX_FLOW_PCE_ActionIrq_t eIrqAction; -+ -+ /** Action "Cross State" Group. -+ Cross state action control and enable */ -+ IFX_FLOW_PCE_ActionCrossState_t eCrossStateAction; -+ -+ /** Action "Critical Frames" Group. -+ Critical Frame action control and enable */ -+ IFX_FLOW_PCE_ActionCriticalFrame_t eCritFrameAction; -+ -+ /** Action "Timestamp" Group. Time stamp action control and enable */ -+ IFX_FLOW_PCE_ActionTimestamp_t eTimestampAction; -+ -+ /** Action "Forwarding" Group. -+ Port map action enable. This port forwarding configuration is ignored -+ in case the action "IGMP Snooping" is enabled via the -+ parameter 'nSnoopingTypeAction'. */ -+ IFX_FLOW_PCE_ActionPortmap_t ePortMapAction; -+ /** Target portmap for forwarded packets, only used if selected by -+ 'nPortMapAction'. Forwarding is done -+ if 'nPortMapAction = IFX_FLOW_PCE_ACTION_PORTMAP_ALTERNATIVE'. -+ Every bit in the portmap represents one port (port 0 = LSB bit). */ -+ IFX_uint32_t nForwardPortMap; -+ -+ /** Action "Remarking" Group. Remarking action enable */ -+ IFX_boolean_t bRemarkAction; -+ /** PCP remarking enable. -+ Remarking enabling means that remarking is possible in case -+ the port configuration or metering enables remarking on that -+ packet. Disabling remarking means that it is forced to -+ not remarking this packet, independent of any port remarking of -+ metering configuration. */ -+ IFX_boolean_t bRemarkPCP; -+ /** DSCP remarking enable -+ Remarking enabling means that remarking is possible in case -+ the port configuration or metering enables remarking on that -+ packet. Disabling remarking means that it is forced to -+ not remarking this packet, independent of any port remarking of -+ metering configuration. */ -+ IFX_boolean_t bRemarkDSCP; -+ /** Class remarking enable -+ Remarking enabling means that remarking is possible in case -+ the port configuration or metering enables remarking on that -+ packet. Disabling remarking means that it is forced to -+ not remarking this packet, independent of any port remarking of -+ metering configuration. */ -+ IFX_boolean_t bRemarkClass; -+ -+ /** Action "Meter" Group. Meter action control and enable. */ -+ IFX_FLOW_PCE_ActionMeter_t eMeterAction; -+ /** Meter ID */ -+ IFX_uint8_t nMeterId; -+ -+ /** Action "RMON" Group. RMON action enable */ -+ IFX_boolean_t bRMON_Action; -+ /** Counter ID (The index starts counting from zero). */ -+ IFX_uint8_t nRMON_Id; -+ -+ /** Action "VLAN" Group. VLAN action enable */ -+ IFX_FLOW_PCE_ActionVLAN_t eVLAN_Action; -+ /** Alternative VLAN Id */ -+ IFX_uint16_t nVLAN_Id; -+ -+ /** Action "Cross VLAN" Group. Cross VLAN action enable */ -+ IFX_FLOW_PCE_ActionCrossVLAN_t eVLAN_CrossAction; -+ -+ /** Action "Flow ID". -+ The Switch supports enhancing the egress packets by a device specific -+ special tag header. This header contains detailed switch classification -+ results. One header file is a 'Flow ID', which can be explicitly set as -+ flow table action when hitting a table rule. -+ If selected, the Flow ID is given by the parameter 'nFlowID'. */ -+ IFX_boolean_t bFlowID_Action; -+ -+ /** Flow ID */ -+ IFX_uint16_t nFlowID; -+}IFX_FLOW_PCE_action_t; -+ -+/** Parameter to add/read a rule to/from the packet classification engine. -+ Used by \ref IFX_FLOW_PCE_RULE_WRITE and \ref IFX_FLOW_PCE_RULE_READ. */ -+typedef struct -+{ -+ /** Rule Pattern Part. */ -+ IFX_FLOW_PCE_pattern_t pattern; -+ /** Rule Action Part. */ -+ IFX_FLOW_PCE_action_t action; -+}IFX_FLOW_PCE_rule_t; -+ -+/** Parameter to delete a rule from the packet classification engine. -+ Used by \ref IFX_FLOW_PCE_RULE_DELETE. */ -+typedef struct -+{ -+ /** Action Index in the Packet Classification Engine. -+ It corresponds to the table rule index. */ -+ IFX_uint32_t nIndex; -+}IFX_FLOW_PCE_ruleDelete_t; -+ -+/*@}*/ /* FLOW_IOCTL_CLASSUNIT */ -+ -+/** \addtogroup FLOW_IOCTL_OAM */ -+/*@{*/ -+ -+/** Reset selection. -+ Used by \ref IFX_FLOW_reset_t. */ -+typedef enum -+{ -+ /** Switch Macro reset */ -+ IFX_FLOW_RESET_SWITCH = 0, -+ /** MDIO master interface reset */ -+ IFX_FLOW_RESET_MDIO = 1, -+}IFX_FLOW_resetMode_t; -+ -+/** Reset selection. -+ Used by \ref IFX_FLOW_RESET. */ -+typedef struct -+{ -+ /** Reset selection. */ -+ IFX_FLOW_resetMode_t eReset; -+}IFX_FLOW_reset_t; -+ -+/** Number of extended RMON counter. */ -+#define IFX_FLOW_RMON_EXTEND_NUM 24 -+ -+/** -+ Hardware platform extended RMON Counters. -+ This structure contains additional RMON counters of one Ethernet Switch Port. -+ These counters can be used by the packet classification engine and can be -+ freely assigned to dedicated packet rules and flows. -+ Used by \ref IFX_FLOW_RMON_EXTEND_GET. */ -+typedef struct -+{ -+ /** Ethernet Port number (zero-based counting). The valid range is hardware -+ dependent. An error code is delivered if the selected port is not -+ available. */ -+ IFX_uint8_t nPortId; -+ /** Traffic flow counters */ -+ IFX_uint32_t nTrafficFlowCnt[IFX_FLOW_RMON_EXTEND_NUM]; -+}IFX_FLOW_RMON_extendGet_t; -+ -+/*@}*/ /* FLOW_IOCTL_OAM */ -+ -+/* -------------------------------------------------------------------------- */ -+/* IOCTL Command Definitions */ -+/* -------------------------------------------------------------------------- */ -+ -+/** \addtogroup FLOW_IOCTL_DEBUG */ -+/*@{*/ -+ -+/** -+ Write to an internal register. The register offset defines which register to access in -+ which table. This routine only accesses the M4599_PDI and -+ the ETHSW_PDI of the switch. All PHY registers are accessed -+ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. -+ Note that the switch API implementation checks whether the given address is -+ inside the valid address range. It returns with an error in case an invalid -+ address is given. -+ -+ \param IFX_FLOW_register_t Pointer to \ref IFX_FLOW_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_REGISTER_SET _IOW(IFX_FLOW_MAGIC, 0x01, IFX_FLOW_register_t) -+ -+/** -+ Read an internal register. The register offset defines which register to access in -+ which table. This routine only accesses the M4599_PDI and -+ the ETHSW_PDI of the switch. All PHY registers are accessed -+ via \ref IFX_ETHSW_MDIO_DATA_WRITE and \ref IFX_ETHSW_MDIO_DATA_READ. -+ Note that the switch API implementation checks whether the given address is -+ inside the valid address range. It returns with an error in case an invalid -+ address is given. -+ -+ \param IFX_FLOW_register_t Pointer to \ref IFX_FLOW_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_REGISTER_GET _IOWR(IFX_FLOW_MAGIC, 0x02, IFX_FLOW_register_t) -+ -+/*@}*/ /* FLOW_IOCTL_DEBUG */ -+ -+/** \addtogroup FLOW_IOCTL_IRQ */ -+/*@{*/ -+/** -+ Get the interrupt enable configuration. This assignment can be set using \ref IFX_FLOW_IRQ_MASK_SET. -+ -+ \param IFX_FLOW_irq_t Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+#define IFX_FLOW_IRQ_MASK_GET _IOWR(IFX_FLOW_MAGIC, 0x03, IFX_FLOW_irq_t) -+ -+/** -+ Set the interrupt enable configuration. This assignment can be read using \ref IFX_FLOW_IRQ_MASK_GET. -+ Setting interrupts that are not supported by hardware results in an error response. -+ -+ \param IFX_FLOW_irq_t Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+#define IFX_FLOW_IRQ_MASK_SET _IOW(IFX_FLOW_MAGIC, 0x04, IFX_FLOW_irq_t) -+ -+/** -+ Read the interrupt status. Interrupt status indications can be cleared using \ref IFX_FLOW_IRQ_STATUS_CLEAR. -+ -+ \param IFX_FLOW_irq_t Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+#define IFX_FLOW_IRQ_GET _IOWR(IFX_FLOW_MAGIC, 0x05, IFX_FLOW_irq_t) -+ -+/** -+ Clear individual interrupt status bits. Interrupt status indications can be read using \ref IFX_FLOW_IRQ_GET. -+ -+ \param IFX_FLOW_irq_t Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+#define IFX_FLOW_IRQ_STATUS_CLEAR _IOW(IFX_FLOW_MAGIC, 0x06, IFX_FLOW_irq_t) -+ -+/*@}*/ /* FLOW_IOCTL_IRQ */ -+ -+/** \addtogroup FLOW_IOCTL_CLASSUNIT */ -+/*@{*/ -+ -+/** -+ This command writes a rule pattern and action to the table of the packet -+ classification engine. The pattern part describes the parameter to identify an -+ incoming packet to which the dedicated actions should be applied. -+ A rule can be read using the command \ref IFX_FLOW_PCE_RULE_READ. -+ -+ \param IFX_FLOW_PCE_rule_t Pointer to \ref IFX_FLOW_PCE_rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_PCE_RULE_WRITE _IOW(IFX_FLOW_MAGIC, 0x07, IFX_FLOW_PCE_rule_t) -+ -+/** -+ This command allows the reading out of a rule pattern and action of the -+ packet classification engine. -+ A rule can be written using the command \ref IFX_FLOW_PCE_RULE_WRITE. -+ -+ \param IFX_FLOW_PCE_rule_t Pointer to \ref IFX_FLOW_PCE_rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_PCE_RULE_READ _IOWR(IFX_FLOW_MAGIC, 0x08, IFX_FLOW_PCE_rule_t) -+ -+/** -+ This command deletes a complete rule from the packet classification engine. -+ A delete operation is done on the rule of a dedicated index 'nIndex'. -+ A rule can be written over using the command \ref IFX_FLOW_PCE_RULE_WRITE. -+ -+ \param IFX_FLOW_PCE_ruleDelete_t Pointer to \ref IFX_FLOW_PCE_ruleDelete_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_PCE_RULE_DELETE _IOW(IFX_FLOW_MAGIC, 0x09, IFX_FLOW_PCE_ruleDelete_t) -+ -+/*@}*/ /* FLOW_IOCTL_CLASSUNIT */ -+ -+/** \addtogroup FLOW_IOCTL_OAM */ -+/*@{*/ -+ -+/** -+ Forces a hardware reset of the switch device or switch macro. The device -+ automatically comes back out of reset and contains the initial values. -+ All previous configurations are lost. -+ -+ \param IFX_FLOW_reset_t Pointer to an \ref IFX_FLOW_reset_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \remarks Not supported for all devices -+*/ -+#define IFX_FLOW_RESET _IOW(IFX_FLOW_MAGIC, 0x0A, IFX_FLOW_reset_t) -+ -+/** -+ Read out additional traffic flow (RMON) counters. -+ The zero-based 'nPortId' structure element describes the physical switch -+ port for the requested statistic information. -+ -+ \param IFX_FLOW_RMON_extendGet_t Pointer to a pre-allocated -+ \ref IFX_FLOW_RMON_extendGet_t structure. The structure element 'nPortId' is -+ an input parameter that describes from which port to read the RMON counter. -+ All remaining structure elements are filled with the counter values. -+ The counter assignment needs to be done during the flow definition, -+ for example in \ref IFX_FLOW_PCE_RULE_WRITE. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+#define IFX_FLOW_RMON_EXTEND_GET _IOWR(IFX_FLOW_MAGIC, 0x0B, IFX_FLOW_RMON_extendGet_t) -+ -+/*@}*/ /* FLOW_IOCTL_OAM */ -+ -+#endif /* _IFX_FLOW_FLOW_H_ */ -diff --git a/include/switch_api/ifx_ethsw_flow_core.h b/include/switch_api/ifx_ethsw_flow_core.h -new file mode 100644 -index 0000000..6a0eb14 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_flow_core.h -@@ -0,0 +1,254 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_flow_core.h -+ \remarks FLOW Core Layer header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_FLOW_CORE_H_ -+#define _IFX_ETHSW_FLOW_CORE_H_ -+ -+//#include "ifx_ethsw_api.h" -+#include "ifx_ethsw_reg_access.h" -+#include "ifx_ethsw_pce.h" -+ -+ -+/**********************************/ -+/* External Variables & Functions */ -+/**********************************/ -+// checked: extern IFX_ETHSW_HL_DRV_CTX_t gHlDrvCtx; -+#define MAX_PORT_NUMBER 12 /* including virtual ports*/ -+#define MULTICAST_HW_TABLE_MAX 64 -+#define MAC_ADDRESS_LENGTH 6 -+ -+#define IFX_HW_VLAN_MAP_TABLE_MAX 64 -+#define IFX_FLOW_VLAN_ENTRY_MAX IFX_HW_VLAN_MAP_TABLE_MAX -+#define IFX_FLOW_PORT_NUMBER_MAX 7 -+#define IFX_HW_MAC_TABLE_MAX 2048 -+#define IFX_FLOW_INTERNAL_PORT_NUMBER 2 -+#define IFX_FLOW_EXTERNAL_PORT_NUMBER 3 -+#define IFX_FLOW_MULTICAST_SW_TBL_SIZE 64 -+#define IFX_FLOW_MULTICAST_HW_TBL_SIZE 64 -+ -+ -+//#define VRX_PLATFORM_CPU_PORT 6 -+#define VRX_CPU_PORT 6 -+#define ARX_CPU_PORT 6 -+#define GHN_CPU_PORT 2 -+#define VRX_PLATFORM_CAP_SEGNENT 256 -+#define VRX_PLATFORM_CAP_FID 64 -+#define IFX_ETHSW_RMON_COUNTER_OFFSET 64 -+#define IFX_ETHSW_FLOW_TOP_REG_OFFSET 0xC40 -+#define IFX_ETHSW_MAX_PACKET_LENGTH 9600 -+#define IFX_ETHSW_MAC_BRIDGE_TABLE_INDEX 0xB -+#define IFX_FLOW_PORT_STATE_LISTENING_ONLY 0 -+#define IFX_FLOW_PORT_STATE_RX_ENABLE_TX_DISABLE 1 -+#define IFX_FLOW_PORT_STATE_RX_DISABLE_TX_ENABLE 2 -+#define IFX_FLOW_PORT_STATE_LEARNING 4 -+#define IFX_FLOW_PORT_STATE_FORWARDING_ENABLE 7 -+#define RMON_EXTEND_TRAFFIC_FLOW_COUNT_1 0x28 -+/*PHY Reg 0x4 */ -+#define PHY_AN_ADV_10HDX 0x20 -+#define PHY_AN_ADV_10FDX 0x40 -+#define PHY_AN_ADV_100HDX 0x80 -+#define PHY_AN_ADV_100FDX 0x100 -+/*PHY Reg 0x9 */ -+#define PHY_AN_ADV_1000HDX 0x100 -+#define PHY_AN_ADV_1000FDX 0x200 -+ -+ -+#define DEFAULT_AGING_TIMEOUT 300 -+/* Define Aging Counter Mantissa Value */ -+#define AGETIMER_1_DAY 0xFB75 -+#define AGETIMER_1_HOUR 0xA7BA -+#define AGETIMER_300_SEC 0xDF84 -+#define AGETIMER_10_SEC 0x784 -+#define AGETIMER_1_SEC 0xBF -+ -+/* Define Duplex Mode */ -+#define DUPLEX_AUTO 0 -+#define DUPLEX_EN 1 -+#define DUPLEX_DIS 3 -+ -+/** Description */ -+typedef struct { -+ /* Cap Type */ -+ IFX_ETHSW_capType_t Cap_Type; -+ /* Description String */ -+ IFX_char_t Desci[IFX_ETHSW_CAP_STRING_LEN]; -+}IFX_ETHSW_CapDesc_t; -+ -+typedef struct { -+ /* STP State */ -+ IFX_ETHSW_STP_PortState_t ifx_stp_state; -+ /* 8021X State */ -+ IFX_ETHSW_8021X_portState_t ifx_8021_state; -+ /* PEN Register */ -+ IFX_uint8_t pen_reg; -+ /* PSTATE Register */ -+ IFX_uint8_t pstate_reg; -+ /* LRN limit */ -+ IFX_uint8_t lrnlim; -+}PORT_STATE_t; -+ -+/** Description */ -+typedef struct -+{ -+ /* Port Enable */ -+ IFX_boolean_t bPortEnable; -+ /** Transparent Mode */ -+ IFX_boolean_t bTVM; -+ /* Learning Limit Action */ -+ IFX_boolean_t bLearningLimitAction; -+ /* Automatic MAC address table learning locking */ -+ IFX_boolean_t bLearningPortLocked; -+ /* Automatic MAC address table learning limitation */ -+ IFX_uint16_t nLearningLimit; -+ /* Port State */ -+ IFX_uint16_t nPortState; -+ /* Port State for STP */ -+ IFX_ETHSW_STP_PortState_t ifx_stp_state; -+ /* Port State for 8021.x */ -+ IFX_ETHSW_8021X_portState_t ifx_8021x_state; -+}IFX_FLOW_portConfig_t; -+ -+/** Description */ -+typedef struct -+{ -+ /* 8021x Port Forwarding State */ -+ IFX_ETHSW_portForward_t eForwardPort; -+ /* 8021X Forwarding Port ID*/ -+ IFX_uint8_t n8021X_ForwardPortId; -+ /* STP port State */ -+ IFX_ETHSW_portForward_t eSTPPortState; -+ /* STP Port ID */ -+ IFX_uint16_t nSTP_PortID; -+}IFX_FLOW_STP_8021X_t; -+ -+/** Description */ -+typedef struct -+{ -+ IFX_boolean_t valid; -+ /* VLAN ID */ -+ IFX_uint16_t vid; -+ /* Forward ID */ -+ IFX_uint32_t fid; -+ /* Port Member */ -+ IFX_uint16_t pm; -+ /* Tag Member */ -+ IFX_uint16_t tm; -+ /* VID reserved */ -+ IFX_boolean_t reserved; -+}IFX_FLOW_VLAN_tableEntry_t; -+ -+typedef struct -+{ -+ /* PortMap */ -+ /* Src IP MSB index*/ -+ IFX_uint16_t SrcIp_MSB_Index; -+ /* Dis IP MSB index*/ -+ IFX_uint16_t DisIp_MSB_Index; -+ /* Src IP LSB index*/ -+ IFX_uint16_t SrcIp_LSB_Index; -+ /* Dis IP LSB index*/ -+ IFX_uint16_t DisIp_LSB_Index; -+ /* PortMap */ -+ IFX_uint16_t PortMap; -+ /* Membber Mode */ -+ IFX_uint16_t eModeMember; -+ /* Valid */ -+ IFX_boolean_t valid; -+} IFX_MulticastSW_table_Entry_t; -+ -+/** Description */ -+typedef struct -+{ -+ /* eIGMP_Mode */ -+ IFX_uint16_t eIGMP_Mode; -+ /* bIGMPv3 */ -+ IFX_boolean_t bIGMPv3; -+ /* eForwardPort */ -+ IFX_uint16_t eForwardPort; -+ /* nForwardPortId */ -+ IFX_uint8_t nForwardPortId; -+ /* bCrossVLAN */ -+ IFX_boolean_t bCrossVLAN; -+ /* nCOS */ -+ IFX_uint8_t nClassOfService; -+ /* Multicast SW Table */ -+ IFX_MulticastSW_table_Entry_t multicast_sw_table[IFX_FLOW_MULTICAST_SW_TBL_SIZE]; -+ /* Multicast Router Port */ -+ IFX_uint16_t eRouterPort; -+ /* SW Table side */ -+ IFX_uint8_t nSwTblSize; -+}IFX_FLOW_IGMP_t; -+ -+typedef struct { -+ IFX_FLOW_devType_t eDev; -+ IFX_FLOW_portConfig_t PortConfig[IFX_FLOW_PORT_NUMBER_MAX]; -+ IFX_boolean_t bVLAN_Aware; -+ IFX_FLOW_VLAN_tableEntry_t VLAN_Table[IFX_HW_VLAN_MAP_TABLE_MAX]; -+ IFX_FLOW_STP_8021X_t STP_8021x_Config; -+ IFX_FLOW_IGMP_t IGMP_Flags; -+ IFX_PCE_t PCE_Handler; -+ IFX_void_t *pRAL_Dev; -+ IFX_uint8_t nPortNumber; -+ IFX_uint8_t nTotalPortNumber; -+ IFX_uint8_t nManagementPortNumber; -+ IFX_uint32_t MAC_AgeTimer; -+ IFX_boolean_t bResetCalled; -+ IFX_boolean_t bHW_InitCalled; -+ IFX_uint8_t vlan_table_index; -+ IFX_uint16_t mac_table_index; -+ IFX_uint16_t multi_hw_table_index; -+ IFX_uint16_t multi_sw_table_index; -+ IFX_uint8_t nCPU_Port; -+ IFX_uint8_t multi_routerport_counter; -+ IFX_uint8_t meter_cnt; -+#ifdef IFX_ETHSW_API_COC -+ IFX_void_t *pPMCtx; -+#endif -+} IFX_FLOW_switchDev_t; -+ -+typedef struct -+{ -+ IFX_void_t *pDev; -+ IFX_FLOW_devType_t eDev; -+}IFX_FLOW_switchCoreInit_t; -+ -+typedef struct -+{ -+ IFX_uint8_t nTable_Index; -+ IFX_uint8_t nOP; // operation (1:add, 2:delete) -+ IFX_uint16_t nVId; -+ IFX_uint32_t nFId; -+}IFX_FLOW_VLAN_Filter_registerOperation_t; -+ -+/**********************/ -+/* Function Prototype */ -+/**********************/ -+ -+/**********************/ -+/* Function Prototype */ -+/**********************/ -+IFX_return_t IFX_FLOW_VLAN_Table_Print ( IFX_void_t *pDevCtx ); -+IFX_uint8_t IFX_FLOW_VLAN_Table_Index_Find ( IFX_void_t *pDevCtx, IFX_uint16_t vid ); -+ -+IFX_void_t *IFX_FLOW_SwitchCoreInit(IFX_FLOW_switchCoreInit_t *pInit ); -+void IFX_FLOW_SwitchCoreCleanUP(IFX_void_t ); -+ -+IFX_boolean_t IFX_FLOW_PHY_mediumDetectStatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+IFX_return_t IFX_FLOW_PHY_PDN_Set(IFX_void_t *pDevCtx, IFX_uint8_t PHYAD); -+IFX_return_t IFX_FLOW_PHY_PDN_Clear(IFX_void_t *pDevCtx, IFX_uint8_t nPHYAD); -+IFX_boolean_t IFX_FLOW_PHY_Link_Status_Get(IFX_void_t *pDevCtx, IFX_uint8_t nPortID); -+ -+extern IFX_uint32_t ifx_ethsw_ll_DirectAccessRead(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); -+extern IFX_return_t ifx_ethsw_ll_DirectAccessWrite(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); -+ -+#endif /* _IFX_ETHSW_PSB6970_CORE_H_ */ -diff --git a/include/switch_api/ifx_ethsw_flow_ll.h b/include/switch_api/ifx_ethsw_flow_ll.h -new file mode 100644 -index 0000000..e7a45a6 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_flow_ll.h -@@ -0,0 +1,2015 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef ____INCLUDE_IFX_ETHSW_FLOW_LL_H -+#define ____INCLUDE_IFX_ETHSW_FLOW_LL_H -+ -+#include "ifx_ethsw.h" -+#include "ifx_ethsw_flow.h" -+ -+/* Group definitions for Doxygen */ -+/** \defgroup FLOW_LL Ethernet Switch Application Kernel Interface -+ This chapter describes the entire interface to access and -+ configure the services of the switch module in OS kernel space. */ -+/*@{*/ -+/** \defgroup FLOW_LL_BRIDGE Ethernet Bridging Functions -+ Ethernet bridging (or switching) is the basic task of the device. It -+ provides individual configurations per port and standard global -+ switch features. -+*/ -+/** \defgroup FLOW_LL_CLASSUNIT Packet Classification Engine -+ Configures and controls the classification unit of the XWAY VRX200 -+ and XWAY GRX200 Family hardware. -+*/ -+/** \defgroup FLOW_LL_DEBUG Debug Features -+ XWAY VRX200 and XWAY GRX200 Family specific features for system -+ integration and debug sessions. -+*/ -+/** \defgroup FLOW_LL_IRQ Interrupt Handling -+ Configure XWAY VRX200 and XWAY GRX200 Family specific hardware -+ support to generate interrupts -+ and read out the interrupt sources. -+*/ -+/** \defgroup FLOW_LL_MULTICAST Multicast Functions -+ IGMP/MLD snooping configuration and support for IGMPv1, IGMPv2, IGMPv3, -+ MLDv1, and MLDv2. -+*/ -+/** \defgroup FLOW_LL_OAM Operation, Administration, and Management Functions -+ This chapter summarizes the functions that are provided to monitor the -+ data traffic passing through the device. -+*/ -+/** \defgroup FLOW_LL_QOS Quality of Service Functions -+ Switch and port configuration for Quality of Service (QoS). -+*/ -+/** \defgroup FLOW_LL_VLAN VLAN Functions -+ This chapter describes VLAN bridging functionality. -+*/ -+/*@}*/ -+ -+/* ------------------------------------------------------------------------- */ -+/* Function Declaration */ -+/* ------------------------------------------------------------------------- */ -+ -+/** \addtogroup FLOW_LL_BRIDGE */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_EAPOL_RULE_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_8021X_EAPOL_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_EAPOL_RULE_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_8021X_EAPOL_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_8021X_EAPOL_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_EAPOL_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_8021X_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_8021X_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ 802.1x port authorized state port -+ configuration \ref IFX_ETHSW_8021X_portCfg_t -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_8021X_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_8021X_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_CLEAR command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MAC_TableClear(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableAdd_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MAC_TableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableAdd_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_QUERY command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableQuery_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MAC_TableEntryQuery(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableQuery_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRead_t structure that is filled out by the switch -+ implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MAC_TableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MAC_TABLE_ENTRY_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a MAC table entry -+ \ref IFX_ETHSW_MAC_tableRemove_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MAC_TableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_MAC_tableRemove_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_BPDU_RULE_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_STP_BPDU_RuleGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_BPDU_RULE_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_BPDU_Rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_STP_BPDU_RuleSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_BPDU_Rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_STP_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_STP_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_STP_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_STP_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_STP_portCfg_t *pPar); -+ -+/*@}*/ /* FLOW_LL_BRIDGE */ -+/** \addtogroup FLOW_LL_VLAN */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_CREATE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_IdCreate_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_IdCreate(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdCreate_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_DELETE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an -+ \ref IFX_ETHSW_VLAN_IdDelete_t structure element. -+ -+ \remarks A VLAN ID can only be removed in case it was created by -+ \ref IFX_ETHSW_VLAN_ID_CREATE and is currently not assigned -+ to any Ethernet port (done using \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD). -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_IdDelete(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdDelete_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_ID_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_VLAN_IdGet_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_IdGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_IdGet_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an -+ \ref IFX_ETHSW_VLAN_portCfg_t structure element. Based on the parameter -+ 'nPortId', the switch API implementation fills out the remaining structure -+ elements. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_VLAN_portCfg_t -+ structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberAdd_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_PortMemberAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberAdd_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRead_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_PortMemberRead(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_PORT_MEMBER_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_portMemberRemove_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_PortMemberRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_portMemberRemove_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_RESERVED_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_ReservedAdd(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VLAN_RESERVED_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_VLAN_reserved_t structure element. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_VLAN_ReservedRemove(IFX_void_t *pDevCtx, IFX_ETHSW_VLAN_reserved_t *pPar); -+ -+/*@}*/ /* FLOW_LL_VLAN */ -+/** \addtogroup FLOW_LL_QOS */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_CLASS_DSCP_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the DSCP mapping parameter -+ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ClassDSCP_Get(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassDSCP_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_CLASS_DSCP_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the DSCP mapping parameter -+ \ref IFX_ETHSW_QoS_ClassDSCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ClassDSCP_Set(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassDSCP_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_CLASS_PCP_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the PCP priority mapping parameter -+ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ClassPCP_Get(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassPCP_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_CLASS_PCP_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the PCP priority mapping parameter -+ \ref IFX_ETHSW_QoS_ClassPCP_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ClassPCP_Set(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ClassPCP_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_CLASS_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_DSCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_CLASS_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_DSCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_DSCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS -+ DSCP drop precedence parameters -+ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_DSCP_DropPrecedenceCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_DSCP_DROP_PRECEDENCE_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS -+ DSCP drop precedence parameters -+ \ref IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_DSCP_DropPrecedenceCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_DSCP_DropPrecedenceCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_METER_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_MeterCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_METER_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_MeterCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_METER_PORT_ASSIGN command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_MeterPortAssign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPort_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_METER_PORT_DEASSIGN command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_MeterPortDeassign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPort_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_METER_PORT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_meterPortGet_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_MeterPortGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_meterPortGet_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PCP_CLASS_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PCP_ClassGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PCP_CLASS_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_PCP_ClassCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PCP_ClassSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_PCP_ClassCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a -+ QOS port priority control configuration \ref IFX_ETHSW_QoS_portCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the QoS filter parameters -+ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PortRemarkingCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portRemarkingCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_PORT_REMARKING_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the remarking configuration -+ \ref IFX_ETHSW_QoS_portRemarkingCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_PortRemarkingCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_portRemarkingCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_QUEUE_PORT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_queuePort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_QueuePortGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_queuePort_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_QUEUE_PORT_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_queuePort_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_QueuePortSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_queuePort_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SCHEDULER_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_SchedulerCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_schedulerCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SCHEDULER_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_schedulerCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_SchedulerCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_schedulerCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SHAPER_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ShaperCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SHAPER_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ShaperCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_ASSIGN command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ShaperQueueAssign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueue_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_DEASSIGN command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueue_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ShaperQueueDeassign(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueue_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_SHAPER_QUEUE_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_ShaperQueueGet_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_ShaperQueueGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_ShaperQueueGet_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_STORM_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_stormCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_StormCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_stormCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_STORM_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_stormCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_StormCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_stormCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_WRED_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_WredCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_WRED_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_Cfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_WredCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_WredQueueCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_QueueCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_QOS_WRED_QUEUE_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the parameters -+ structure \ref IFX_ETHSW_QoS_WRED_QueueCfg_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_QoS_WredQueueCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_QoS_WRED_QueueCfg_t *pPar); -+ -+/*@}*/ /* FLOW_LL_QOS */ -+/** \addtogroup FLOW_LL_MULTICAST */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastRouterPortAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouterRead_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+IFX_return_t IFX_FLOW_MulticastRouterPortRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouterRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_ROUTER_PORT_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_multicastRouter_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs (e.g. Ethernet port parameter out of range) -+*/ -+IFX_return_t IFX_FLOW_MulticastRouterPortRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastRouter_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastSnoopCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_SNOOP_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to the -+ multicast configuration \ref IFX_ETHSW_multicastSnoopCfg_t. -+ -+ \remarks IGMP/MLD snooping is disabled when -+ 'eIGMP_Mode = IFX_ETHSW_MULTICAST_SNOOP_MODE_SNOOPFORWARD'. -+ Then all other structure parameters are unused. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastSnoopCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_multicastSnoopCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_ADD command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastTableEntryAdd(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTableRead_t. -+ -+ \remarks The 'bInitial' parameter is reset during the read operation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastTableEntryRead(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTableRead_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MULTICAST_TABLE_ENTRY_REMOVE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_multicastTable_t. -+ -+ \remarks The Source IP parameter is ignored in case IGMPv3 support is -+ not enabled in the hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MulticastTableEntryRemove(IFX_void_t *pDevCtx, IFX_ETHSW_multicastTable_t *pPar); -+ -+/*@}*/ /* FLOW_LL_MULTICAST */ -+/** \addtogroup FLOW_LL_OAM */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_CPU_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_CPU_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_CPU_PortExtendCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CPU_PORT_EXTEND_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_CPU_PortExtendCfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_CPU_PortExtendCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_CPU_PortExtendCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CAP_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated capability -+ list structure \ref IFX_ETHSW_cap_t. -+ The switch API implementation fills out the structure with the supported -+ features, based on the provided 'nCapType' parameter. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_CapGet(IFX_void_t *pDevCtx, IFX_ETHSW_cap_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ The structure is filled out by the switch implementation. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_cfg_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_DISABLE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_Disable(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_ENABLE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_Enable(IFX_void_t *pDevCtx); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_HW_INIT command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated initialization structure -+ \ref IFX_ETHSW_HW_Init_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_HW_Init(IFX_void_t *pDevCtx, IFX_ETHSW_HW_Init_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MDIO_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MDIO_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_DATA_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MDIO_DataRead(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MDIO_DATA_WRITE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_MDIO_data_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_MDIO_DataWrite(IFX_void_t *pDevCtx, IFX_ETHSW_MDIO_data_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MONITOR_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MonitorPortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_MONITOR_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_monitorPortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_MonitorPortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_monitorPortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a port configuration -+ \ref IFX_ETHSW_portCfg_t structure to fill out by the driver. -+ The parameter 'nPortId' tells the driver which port parameter is requested. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_ETHSW_portCfg_t structure -+ to configure the switch port hardware. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_LINK_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to read out the port status. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortLinkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_LINK_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portLinkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortLinkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portLinkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_PHY_ADDR_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_portPHY_Addr_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortPHY_AddrGet(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Addr_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_PHY_QUERY command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portPHY_Query_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortPHY_Query(IFX_void_t *pDevCtx, IFX_ETHSW_portPHY_Query_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortRGMII_ClkCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_RGMII_CLK_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_ETHSW_portRGMII_ClkCfg_t structure to set the port configuration. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortRGMII_ClkCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRGMII_ClkCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_REDIRECT_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortRedirectGet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_PORT_REDIRECT_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer -+ to \ref IFX_ETHSW_portRedirectCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ \remarks Not all hardware platforms support this feature. The function -+ returns an error if this feature is not supported. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PortRedirectSet(IFX_void_t *pDevCtx, IFX_ETHSW_portRedirectCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_RMON_CLEAR command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a pre-allocated -+ \ref IFX_ETHSW_RMON_clear_t structure. The structure element 'nPortId' is -+ an input parameter stating on which port to clear all RMON counters. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_RMON_Clear(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_clear_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_RMON_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to pre-allocated -+ \ref IFX_ETHSW_RMON_cnt_t structure. The structure element 'nPortId' is -+ an input parameter that describes from which port to read the RMON counter. -+ All remaining structure elements are filled with the counter values. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_RMON_Get(IFX_void_t *pDevCtx, IFX_ETHSW_RMON_cnt_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_VERSION_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar* The parameter points to a -+ \ref IFX_ETHSW_version_t structure. -+ -+ \return Returns value as follows: -+ - IFX_SUCCESS: if successful -+ - IFX_ERROR: in case of an error -+ -+*/ -+IFX_return_t IFX_FLOW_VersionGet(IFX_void_t *pDevCtx, IFX_ETHSW_version_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_WoL_CfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_Cfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_WoL_CfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_Cfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_PORT_CFG_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_WoL_PortCfgGet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_ETHSW_WOL_PORT_CFG_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_ETHSW_WoL_PortCfg_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_WoL_PortCfgSet(IFX_void_t *pDevCtx, IFX_ETHSW_WoL_PortCfg_t *pPar); -+ -+/*@}*/ /* FLOW_LL_OAM */ -+/** \addtogroup FLOW_LL_DEBUG */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_REGISTER_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_FLOW_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_RegisterGet(IFX_void_t *pDevCtx, IFX_FLOW_register_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_REGISTER_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_FLOW_register_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_RegisterSet(IFX_void_t *pDevCtx, IFX_FLOW_register_t *pPar); -+ -+/*@}*/ /* FLOW_LL_DEBUG */ -+/** \addtogroup FLOW_LL_IRQ */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_IRQ_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_IrqGet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_IRQ_MASK_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_IrqMaskGet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_IRQ_MASK_SET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_IrqMaskSet(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_IRQ_STATUS_CLEAR command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to -+ an \ref IFX_FLOW_irq_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+*/ -+IFX_return_t IFX_FLOW_IrqStatusClear(IFX_void_t *pDevCtx, IFX_FLOW_irq_t *pPar); -+ -+/*@}*/ /* FLOW_LL_IRQ */ -+/** \addtogroup FLOW_LL_CLASSUNIT */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_PCE_RULE_DELETE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_FLOW_PCE_ruleDelete_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PceRuleDelete(IFX_void_t *pDevCtx, IFX_FLOW_PCE_ruleDelete_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_PCE_RULE_READ command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_FLOW_PCE_rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PceRuleRead(IFX_void_t *pDevCtx, IFX_FLOW_PCE_rule_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_PCE_RULE_WRITE command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to \ref IFX_FLOW_PCE_rule_t. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_PceRuleWrite(IFX_void_t *pDevCtx, IFX_FLOW_PCE_rule_t *pPar); -+ -+/*@}*/ /* FLOW_LL_CLASSUNIT */ -+/** \addtogroup FLOW_LL_OAM */ -+/*@{*/ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_RMON_EXTEND_GET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to a pre-allocated -+ \ref IFX_FLOW_RMON_extendGet_t structure. The structure element 'nPortId' is -+ an input parameter that describes from which port to read the RMON counter. -+ All remaining structure elements are filled with the counter values. -+ The counter assignment needs to be done during the flow definition, -+ for example in \ref IFX_FLOW_PCE_RULE_WRITE. -+ -+ \remarks The function returns an error in case the given 'nPortId' is -+ out of range. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+*/ -+IFX_return_t IFX_FLOW_RMON_ExtendGet(IFX_void_t *pDevCtx, IFX_FLOW_RMON_extendGet_t *pPar); -+ -+/** -+ This is the switch API low-level function for -+ the \ref IFX_FLOW_RESET command. -+ -+ \param pDevCtx This parameter is a pointer to the device context -+ which contains all information related to this special instance of the device. -+ \param pPar Pointer to an \ref IFX_FLOW_reset_t structure. -+ -+ \remarks The function returns an error code in case an error occurs. -+ The error code is described in \ref IFX_ETHSW_status_t. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurs -+ -+ \remarks Not supported for all devices -+*/ -+IFX_return_t IFX_FLOW_Reset(IFX_void_t *pDevCtx, IFX_FLOW_reset_t *pPar); -+ -+/*@}*/ /* FLOW_LL_OAM */ -+#endif /* ____INCLUDE_IFX_ETHSW_FLOW_LL_H */ -diff --git a/include/switch_api/ifx_ethsw_init.h b/include/switch_api/ifx_ethsw_init.h -new file mode 100644 -index 0000000..db11c6e ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_init.h -@@ -0,0 +1,29 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_init.h -+ \remarks Generic switch API header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_INIT_H_ -+#define _IFX_ETHSW_INIT_H_ -+ -+#include "ifx_ethsw_linux.h" -+#include "ifx_ethsw_PSB6970_core.h" -+#include "ifx_ethsw_flow_core.h" -+#include "ifx_ethsw_ral.h" -+#include "ifx_ethsw_rml.h" -+#include "ifx_ethsw_reg_access.h" -+ -+typedef struct { -+ IFX_uint8_t minorNum; -+ IFX_void_t *pCoreDev; -+} IFX_ETHSW_coreHandle_t; -+ -+#endif /* _IFX_ETHSW_INIT_H_ */ -diff --git a/include/switch_api/ifx_ethsw_kernel_api.h b/include/switch_api/ifx_ethsw_kernel_api.h -new file mode 100644 -index 0000000..a7edfec ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_kernel_api.h -@@ -0,0 +1,80 @@ -+/**************************************************************************** -+ -+ Copyright 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef _IFX_ETHSW_KERNEL_API_H_ -+#define _IFX_ETHSW_KERNEL_API_H_ -+ -+/* Group definitions for Doxygen */ -+/** \defgroup ETHSW_KERNELAPI Ethernet Switch Linux Kernel Interface -+ This chapter describes the entire interface to access and -+ configure the services of the Ethernet switch module -+ within the Linux kernel space. */ -+ -+/*@{*/ -+ -+/** Definition of the device handle that is retrieved during -+ the \ref ifx_ethsw_kopen call. This handle is used to access the switch -+ device while calling \ref ifx_ethsw_kioctl. */ -+typedef unsigned int IFX_ETHSW_HANDLE; -+ -+/** -+ Request a device handle for a dedicated Ethernet switch device. The switch -+ device is identified by the given device name (e.g. "/dev/switch/1"). -+ The device handle is the return value of this function. This handle is -+ used to access the switch parameter and features while -+ calling \ref ifx_ethsw_kioctl. Please call the function -+ \ref ifx_ethsw_kclose to release a device handle that is not needed anymore. -+ -+ \param name Pointer to the device name of the requested Ethernet switch device. -+ -+ \remarks The client kernel module should check the function return value. -+ A returned zero indicates that the resource allocation failed. -+ -+ \return Return the device handle in case the requested device is available. -+ It returns a zero in case the device does not exist or is blocked -+ by another application. -+*/ -+IFX_ETHSW_HANDLE ifx_ethsw_kopen(char *name); -+ -+/** -+ Calls the switch API driver implementation with the given command and the -+ parameter argument. The called Ethernet switch device is identified by the -+ given device handle. This handle was previously requested by -+ calling \ref ifx_ethsw_kopen. -+ -+ \param handle Ethernet switch device handle, given by \ref ifx_ethsw_kopen. -+ \param command Switch API command to perform. -+ \param arg Command arguments. This argument is basically a reference to -+ the command parameter structure. -+ -+ \remarks The commands and arguments are the same as normally used over -+ the Linux ioctl interface from user space. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurred. -+*/ -+int ifx_ethsw_kioctl(IFX_ETHSW_HANDLE handle, unsigned int command, unsigned int arg); -+ -+/** -+ Releases an Ethernet switch device handle which was previously -+ allocated by \ref ifx_ethsw_kopen. -+ -+ \param handle Ethernet switch device handle, given by \ref ifx_ethsw_kopen. -+ -+ \return Return value as follows: -+ - IFX_SUCCESS: if successful -+ - An error code in case an error occurred. -+*/ -+int ifx_ethsw_kclose(IFX_ETHSW_HANDLE handle); -+ -+/*@}*/ -+ -+#endif /* _IFX_ETHSW_KERNEL_API_H_ */ -diff --git a/include/switch_api/ifx_ethsw_linux.h b/include/switch_api/ifx_ethsw_linux.h -new file mode 100644 -index 0000000..b039bd7 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_linux.h -@@ -0,0 +1,64 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_linux.h -+ \remarks Generic switch API header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_LINUX_H_ -+#define _IFX_ETHSW_LINUX_H_ -+ -+#include "ifx_ethsw_api.h" -+/* function type declaration for the default IOCTL low-level function in -+ case the command cannot be found in the low-level function table, -+ or in case no low-level function table is provided.. */ -+typedef int (*IFX_ioctl_default_fkt) (void*, int, int); -+typedef struct -+{ -+ IFX_ETHSW_lowLevelFkts_t *pLlTable; -+ void *pLlHandle; -+ char paramBuffer[PARAM_BUFFER_SIZE]; -+ /** Default callback handler. This handler is called in case the command -+ cannot be found in the low-level function table, or in case no low-level -+ function table is provided. -+ Provide a 'NULL' pointer in case no default handler is provided. */ -+ IFX_ioctl_default_fkt default_handler; -+}IFX_ETHSW_ioctlHandle_t; -+ -+typedef struct -+{ -+ IFX_boolean_t bInternalSwitch; -+ /** Number of similar Low Level External Switch Devices */ -+ IFX_uint8_t nExternalSwitchNum; -+ IFX_ETHSW_ioctlHandle_t *pIoctlHandle; -+ /** Array of pEthSWDev pointers associated with this driver context */ -+ IFX_void_t *pEthSWDev[IFX_ETHSW_DEV_MAX]; -+} IFX_ETHSW_IOCTL_WRAPPER_CTX_t; -+ -+typedef struct -+{ -+ IFX_ETHSW_lowLevelFkts_t *pLlTable; -+ /** Default callback handler. This handler is called in case the command -+ cannot be found in the low-level function table, or in case no low-level -+ function table is provided. -+ Provide a 'NULL' pointer in case no default handler is provided. */ -+ IFX_ioctl_default_fkt default_handler; -+}IFX_ETHSW_IOCTL_wrapperInit_t; -+ -+typedef struct { -+ unsigned char minor_number; -+} IFX_ETHSW_devoneData_t; -+ -+IFX_return_t IFX_ETHSW_Drv_Register(IFX_uint32_t Major); -+IFX_return_t IFX_ETHSW_Drv_UnRegister (IFX_uint32_t Major); -+IFX_void_t *IFX_ETHSW_IOCTL_WrapperInit(IFX_ETHSW_IOCTL_wrapperInit_t *pInit); -+IFX_return_t IFX_ETHSW_IOCTL_WrapperDeviceAdd(IFX_ETHSW_IOCTL_WRAPPER_CTX_t *pIoctlDev, IFX_void_t *pCoreDev, IFX_uint8_t nMinorNum); -+IFX_return_t IFX_ETHSW_IOCTL_WrapperCleanUp(IFX_void_t); -+ -+#endif /* _IFX_ETHSW_LINUX_H_ */ -diff --git a/include/switch_api/ifx_ethsw_ll_fkt.h b/include/switch_api/ifx_ethsw_ll_fkt.h -new file mode 100644 -index 0000000..87168ee ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_ll_fkt.h -@@ -0,0 +1,41 @@ -+/**************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+*****************************************************************************/ -+#ifndef _IFX_ETHSW_LL_FKT_H -+#define _IFX_ETHSW_LL_FKT_H -+ -+#include "ifx_types.h" -+ -+/* general declaration fits for all low-level functions. */ -+typedef IFX_return_t (*IFX_ll_fkt) (IFX_void_t *, IFX_uint32_t); -+typedef struct IFX_ETHSW_lowLevelFkts_t IFX_ETHSW_lowLevelFkts_t; -+ -+/* Switch API low-level function tables to map all supported IOCTL commands */ -+struct IFX_ETHSW_lowLevelFkts_t -+{ -+ /* Some device have multiple tables to split the generic switch API features -+ and the device specific switch API features. Additional tables, if exist, -+ can be found under this next pointer. Every table comes along with a -+ different 'nType' parameter to differentiate. */ -+ IFX_ETHSW_lowLevelFkts_t *pNext; -+ /* IOCTL type of all commands listed in the table. */ -+ IFX_uint16_t nType; -+ /* Number of low-level functions listed in the table. */ -+ IFX_uint32_t nNumFkts; -+ /* Pointer to the first entry of the ioctl number table. This table is used -+ to check if the given ioctl command fits the the found low-level function -+ pointer under 'pFkts'. */ -+ // IFX_uint32_t *pIoctlCmds; -+ /* Pointer to the first entry of the function table. Table size is given -+ by the parameter 'nNumFkts'. */ -+ IFX_ll_fkt *pFkts; -+}; -+ -+#endif /* #ifndef _IFX_ETHSW_LL_FKT_H */ -diff --git a/include/switch_api/ifx_ethsw_pce.h b/include/switch_api/ifx_ethsw_pce.h -new file mode 100644 -index 0000000..451e6c3 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_pce.h -@@ -0,0 +1,385 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_pce.h -+ \remarks implement PCE header structure. -+ *****************************************************************************/ -+ -+#ifndef _IFX_ETHSW_PCE_H_ -+#define _IFX_ETHSW_PCE_H_ -+ -+#include "ifx_types.h" -+#include "ifx_ethsw_flow.h" -+#include "ifx_ethsw_api.h" -+ -+/* Definitions */ -+#ifndef IFX_DEBUG_PCE -+ #define IFX_DEBUG_PCE \ -+ { \ -+ printk("DEBUG:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__);\ -+ } -+#endif -+ -+#ifndef IFX_RETURN_PCETM -+ #define IFX_RETURN_PCETM \ -+ { \ -+ printk("ERROR:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__); \ -+ return (-1); \ -+ } -+#endif -+ -+#ifndef IFX_RETURN_PCE -+ #define IFX_RETURN_PCE \ -+ { \ -+ printk("ERROR:\n\tFile %s\n\tLine %d\n", __FILE__, __LINE__); \ -+ return (-1); \ -+ } -+#endif -+ -+#define IFX_PCE_PKG_LNG_TBL_SIZE 16 -+#define IFX_PCE_DASA_MAC_TBL_SIZE 64 -+#define IFX_PCE_APPL_TBL_SIZE 64 -+#define IFX_PCE_IP_DASA_MSB_TBL_SIZE 16 -+#define IFX_PCE_IP_DASA_LSB_TBL_SIZE 64 -+#define IFX_PCE_PTCL_TBL_SIZE 32 -+#define IFX_PCE_PPPOE_TBL_SIZE 16 -+#define IFX_PCE_VLAN_ACT_TBL_SIZE 64 -+ -+#define IFX_PCE_TBL_SIZE 64 -+ -+#define IFX_FLOW_PCE_MICROCODE_VALUES 64 -+#define NUM_OF_PORTS_INCLUDE_CPU_PORT 7 -+ -+/* Switch API Micro Code V0.3 */ -+// parser's microcode output field type -+enum { -+ -+ OUT_MAC0 = 0, -+ OUT_MAC1, -+ OUT_MAC2, -+ OUT_MAC3, -+ OUT_MAC4, -+ OUT_MAC5, -+ OUT_ETHTYP, -+ OUT_VTAG0, -+ OUT_VTAG1, -+ OUT_ITAG0, -+ OUT_ITAG1, /*10 */ -+ OUT_ITAG2, -+ OUT_ITAG3, -+ OUT_IP0, -+ OUT_IP1, -+ OUT_IP2, -+ OUT_IP3, -+ OUT_SIP0, -+ OUT_SIP1, -+ OUT_SIP2, -+ OUT_SIP3, /*20*/ -+ OUT_SIP4, -+ OUT_SIP5, -+ OUT_SIP6, -+ OUT_SIP7, -+ OUT_DIP0, -+ OUT_DIP1, -+ OUT_DIP2, -+ OUT_DIP3, -+ OUT_DIP4, -+ OUT_DIP5, /*30*/ -+ OUT_DIP6, -+ OUT_DIP7, -+ OUT_SESID, -+ OUT_PROT, -+ OUT_APP0, -+ OUT_APP1, -+ OUT_IGMP0, -+ OUT_IGMP1, -+ OUT_IPOFF, /*39*/ -+ OUT_NONE = 63 -+}; -+ -+// parser's microcode length type -+#define INSTR 0 -+#define IPV6 1 -+#define LENACCU 2 -+ -+// parser's microcode flag type -+enum { -+ FLAG_ITAG = 0, -+ FLAG_VLAN, -+ FLAG_SNAP, -+ FLAG_PPPOE, -+ FLAG_IPV6, -+ FLAG_IPV6FL, -+ FLAG_IPV4, -+ FLAG_IGMP, -+ FLAG_TU, -+ FLAG_HOP, -+ FLAG_NN1, /*10 */ -+ FLAG_NN2, -+ FLAG_END, -+ FLAG_NO, /*13*/ -+}; -+ -+typedef struct { -+ unsigned short val_3; -+ unsigned short val_2; -+ unsigned short val_1; -+ unsigned short val_0; -+} IFX_FLOW_PCE_MICROCODE_ROW; -+ -+typedef IFX_FLOW_PCE_MICROCODE_ROW IFX_FLOW_PCE_MICROCODE[IFX_FLOW_PCE_MICROCODE_VALUES]; -+ -+/** Provides the address of the configured/fetched lookup table. */ -+typedef enum -+{ -+ /** Parser microcode table */ -+ IFX_ETHSW_PCE_PARS_INDEX = 0x00, -+ IFX_ETHSW_PCE_ACTVLAN_INDEX = 0x01, -+ IFX_ETHSW_PCE_VLANMAP_INDEX = 0x02, -+ IFX_ETHSW_PCE_PPPOE_INDEX = 0x03, -+ IFX_ETHSW_PCE_PROTOCOL_INDEX = 0x04, -+ IFX_ETHSW_PCE_APPLICATION_INDEX = 0x05, -+ IFX_ETHSW_PCE_IP_DASA_MSB_INDEX = 0x06, -+ IFX_ETHSW_PCE_IP_DASA_LSB_INDEX = 0x07, -+ IFX_ETHSW_PCE_PACKET_INDEX = 0x08, -+ IFX_ETHSW_PCE_PCP_INDEX = 0x09, -+ IFX_ETHSW_PCE_DSCP_INDEX = 0x0A, -+ IFX_ETHSW_PCE_MAC_BRIDGE_INDEX = 0x0B, -+ IFX_ETHSW_PCE_MAC_DASA_INDEX = 0x0C, -+ IFX_ETHSW_PCE_MULTICAST_SW_INDEX= 0x0D, -+ IFX_ETHSW_PCE_MULTICAST_HW_INDEX= 0x0E, -+ IFX_ETHSW_PCE_TFLOW_INDEX = 0x0F, -+ IFX_ETHSW_PCE_REMARKING_INDEX = 0x10, -+ IFX_ETHSW_PCE_QUEUE_MAP_INDEX = 0x11, -+ IFX_ETHSW_PCE_METER_INS_0_INDEX = 0x12, -+ IFX_ETHSW_PCE_METER_INS_1_INDEX = 0x13 -+}LOOKUP_TABLE_ADDRESS_t; -+ -+ -+/** Description */ -+typedef enum -+{ -+ /** */ -+ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_ADRD = 0, -+ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_ADWR = 1, -+ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_KSRD = 2, -+ IFX_ETHSW_LOOKUP_TABLE_ACCESS_OP_MODE_KSWR = 3 -+}LOOKUP_TABLE_ACCESS_OPERATION_MODE_t; -+ -+typedef struct -+{ -+ /* key values */ -+ IFX_uint16_t key[8]; -+ /* mask nipples valid for the keys */ -+ IFX_uint16_t mask; -+ /* values */ -+ IFX_uint16_t val[5]; -+ /* choose the related table */ -+ IFX_uint16_t table; -+ /* address index/offset inside the table (zero based couting) */ -+ IFX_uint16_t table_index; -+ /* type: mask (0) or range (1) */ -+ IFX_uint16_t type:1; -+ /* entry is valid (1) or invalid (0) */ -+ IFX_uint16_t valid:1; -+ /* entry belongs to group in case it is not zero */ -+ IFX_uint16_t group:4; -+}IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t; -+ -+ -+typedef struct -+{ -+ /* Packet length */ -+ IFX_uint16_t pkg_lng; -+ /* Packet length range, in number of bytes */ -+ IFX_uint16_t pkg_lng_rng; -+}IFX_PCE_PKG_LNG_TBL_t; -+ -+typedef struct -+{ -+ /* MAC Address */ -+ IFX_uint8_t mac[6]; -+ /* MAC Address Mask */ -+ IFX_uint16_t mac_mask; -+} IFX_PCE_DASA_MAC_TBL_t; -+ -+typedef struct -+{ -+ /* Application data */ -+ IFX_uint16_t appl_data; -+ /* Mode = mask: Application data mask/ Mode = range: Application data range */ -+ IFX_uint16_t mask_range; -+ /* Type Flag: 0 --> Mask/ 11-->Range */ -+ IFX_uint8_t mask_range_type; -+} IFX_PCE_APPL_TBL_t; -+ -+typedef struct -+{ -+ /* IP address byte 15:8 */ -+ IFX_uint8_t ip_msb[8]; -+ /* Nibble mask */ -+ IFX_uint16_t mask; -+}IFX_PCE_IP_DASA_MSB_TBL_t; -+ -+typedef struct -+{ -+ /* IP address byte 7:0 */ -+ IFX_uint8_t ip_lsb[8]; -+ /* Nibble mask */ -+ IFX_uint16_t mask; -+}IFX_PCE_IP_DASA_LSB_TBL_t; -+ -+typedef struct -+{ -+ union { -+ /* Ethertype */ -+ IFX_uint16_t ethertype; -+ struct { -+ /* Protocol */ -+ IFX_uint16_t protocol:8; -+ /* Protocol Flags */ -+ IFX_uint16_t protocol_flags:8; -+ } prot; -+ } key; -+ union { -+ /* Ethertype Mask */ -+ IFX_uint16_t ethertype_mask; -+ struct { -+ /* reserved */ -+ IFX_uint16_t res:12; -+ /* Protocol Mask */ -+ IFX_uint16_t protocol_mask:2; -+ /* Protocol Flag Mask */ -+ IFX_uint16_t protocol_flag_mask:2; -+ } prot; -+ } mask; -+}IFX_PCE_PTCL_TBL_t; -+ -+typedef struct -+{ -+ /* PPPoE session ID */ -+ IFX_uint16_t sess_id; -+}IFX_PCE_PPPOE_TBL_t; -+ -+typedef struct -+{ -+ /* DSCP value */ -+ IFX_uint16_t dscp:7; -+ /* PCP value */ -+ IFX_uint16_t pcp:4; -+ /* Packet length */ -+ IFX_uint16_t pkt_lng_idx:5; -+ /* Destination MAC address */ -+ IFX_uint16_t dst_mac_addr_idx:8; -+ /* Source MAC address */ -+ IFX_uint16_t src_mac_addr_idx:8; -+ /* Destination Application field */ -+ IFX_uint16_t dst_appl_fld_idx:8; -+ /* Source Application field */ -+ IFX_uint16_t src_appl_fld_idx:8; -+ /* DIP MSB */ -+ IFX_uint16_t dip_msb_idx:8; -+ /* DIP LSB */ -+ IFX_uint16_t dip_lsb_idx:8; -+ /* SIP MSB */ -+ IFX_uint16_t sip_msb_idx:8; -+ /* SIP LSB */ -+ IFX_uint16_t sip_lsb_idx:8; -+ /* IP protocol */ -+ IFX_uint16_t ip_prot_idx:8; -+ /* Ethertype */ -+ IFX_uint16_t ethertype_idx:8; -+ /* PPPoE */ -+ IFX_uint16_t pppoe_idx:5; -+ /* VLAN */ -+ IFX_uint16_t vlan_idx:7; -+ /* Port ID */ -+ IFX_uint16_t port_id:8; -+}IFX_PCE_TBL_t; -+ -+typedef struct -+{ -+ /* table reference counter */ -+ IFX_uint16_t pkg_lng_tbl_cnt[IFX_PCE_PKG_LNG_TBL_SIZE]; -+ IFX_uint16_t dasa_mac_tbl_cnt[IFX_PCE_DASA_MAC_TBL_SIZE]; -+ IFX_uint16_t appl_tbl_cnt[IFX_PCE_APPL_TBL_SIZE]; -+ IFX_uint16_t ip_dasa_msb_tbl_cnt[IFX_PCE_IP_DASA_MSB_TBL_SIZE]; -+ IFX_uint16_t ip_dasa_lsb_tbl_cnt[IFX_PCE_IP_DASA_LSB_TBL_SIZE]; -+ IFX_uint16_t ptcl_tbl_cnt[IFX_PCE_PTCL_TBL_SIZE]; -+ IFX_uint16_t pppoe_tbl_cnt[IFX_PCE_PPPOE_TBL_SIZE]; -+ IFX_uint16_t vlan_act_tbl_cnt[IFX_PCE_VLAN_ACT_TBL_SIZE]; -+ /* cached tables */ -+ IFX_PCE_PKG_LNG_TBL_t pkg_lng_tbl[IFX_PCE_PKG_LNG_TBL_SIZE]; -+ IFX_PCE_DASA_MAC_TBL_t dasa_mac_tbl[IFX_PCE_DASA_MAC_TBL_SIZE]; -+ IFX_PCE_APPL_TBL_t appl_tbl[IFX_PCE_APPL_TBL_SIZE]; -+ IFX_PCE_IP_DASA_MSB_TBL_t ip_dasa_msb_tbl[IFX_PCE_IP_DASA_MSB_TBL_SIZE]; -+ IFX_PCE_IP_DASA_LSB_TBL_t ip_dasa_lsb_tbl[IFX_PCE_IP_DASA_LSB_TBL_SIZE]; -+ IFX_PCE_PTCL_TBL_t ptcl_tbl[IFX_PCE_PTCL_TBL_SIZE]; -+ IFX_PCE_PPPOE_TBL_t pppoe_tbl[IFX_PCE_PPPOE_TBL_SIZE]; -+}IFX_PCE_HANDLE_t; -+ -+typedef struct -+{ -+ /* Parameter for the sub-tables */ -+ IFX_PCE_HANDLE_t pce_sub_tbl; -+ IFX_PCE_TBL_t pce_tbl[IFX_PCE_TBL_SIZE]; -+ IFX_FLOW_PCE_action_t pce_act[IFX_PCE_TBL_SIZE]; -+ /* set if the entry is used */ -+ IFX_uint8_t pce_tbl_used[IFX_PCE_TBL_SIZE]; -+} IFX_PCE_t; -+ -+/* Function Declaration */ -+IFX_int32_t ifx_pce_table_init(IFX_PCE_t *pPCEHandle); -+IFX_int32_t ifx_pce_tm_pkg_lng_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PKG_LNG_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_pkg_lng_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_pkg_lng_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PKG_LNG_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_dasa_mac_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_DASA_MAC_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_dasa_mac_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_dasa_mac_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_DASA_MAC_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_appl_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_APPL_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_appl_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_appl_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_APPL_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_idx_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_ip_dasa_msb_tbl_idx_delete(IFX_PCE_HANDLE_t *pTmHandle,IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ip_dasa_lsb_tbl_index_search(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ptcl_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PTCL_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_ptcl_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_ptcl_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PTCL_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_pppoe_tbl_write(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_PPPOE_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_pppoe_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_pppoe_tbl_read(IFX_PCE_HANDLE_t *pTmHandle, IFX_int32_t index, IFX_PCE_PPPOE_TBL_t *pPar); -+IFX_int32_t ifx_pce_tm_vlan_act_tbl_delete(IFX_PCE_HANDLE_t *pTmHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_tm_print_tables(IFX_PCE_HANDLE_t *pTmHandle); -+IFX_int32_t get_ifx_pce_tm_vlan_act_tbl_index(IFX_PCE_HANDLE_t *pTmHandle,IFX_uint8_t index); -+IFX_int32_t ifx_pce_pattern_delete(IFX_PCE_t *pHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_action_delete(IFX_PCE_t *pHandle, IFX_uint32_t index); -+IFX_int32_t ifx_pce_rule_read(IFX_PCE_t *pHandle, IFX_FLOW_PCE_rule_t *pPar); -+IFX_int32_t ifx_pce_rule_write(IFX_PCE_t *pHandle, IFX_FLOW_PCE_rule_t *pPar); -+IFX_return_t ifx_ethsw_xwayflow_pce_table_write(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); -+IFX_return_t ifx_ethsw_xwayflow_pce_table_read(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); -+IFX_return_t ifx_ethsw_xwayflow_pce_table_cam_write(IFX_void_t *pDevCtx, IFX_ETHSW_XWAYFLOW_PCE_TABLE_ENTRY_t *pData); -+ -+IFX_int32_t find_software_tbl_entry(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_LSB_TBL_t *pPar); -+IFX_int32_t find_software_msb_tbl_entry(IFX_PCE_HANDLE_t *pTmHandle, IFX_PCE_IP_DASA_MSB_TBL_t *pPar); -+extern IFX_uint32_t ifx_ethsw_ll_DirectAccessRead(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); -+extern IFX_return_t ifx_ethsw_ll_DirectAccessWrite(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); -+ -+/* Micro Code Load */ -+//IFX_return_t IFX_VR9_Switch_PCE_Micro_Code_Int(IFX_void_t); -+IFX_return_t IFX_VR9_Switch_PCE_Micro_Code_Int(IFX_void_t *pDevCtx); -+ -+/* Debug Funtion */ -+IFX_int32_t ifx_pce_print_tables(IFX_PCE_t *pHandle); -+#endif /* _IFX_ETHSW_PCE_H_ */ -diff --git a/include/switch_api/ifx_ethsw_pm.h b/include/switch_api/ifx_ethsw_pm.h -new file mode 100644 -index 0000000..f021020 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_pm.h -@@ -0,0 +1,63 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_pm.h -+ \remarks power management header file -+ ****************************************************************************/ -+#ifndef _IFX_ETHSW_PM_H_ -+#define _IFX_ETHSW_PM_H_ -+ -+#include <ifx_ethsw_api.h> -+#include <linux/sched.h> -+#include <linux/kthread.h> -+ -+#if 0 -+// Support power management of external Tantos3G -+typedef enum -+{ -+ IFX_ETHSW_PM_MODULENR_TANTOS3G = 1, -+ IFX_ETHSW_PM_MODULENR_GSWIP = 2, -+ IFX_ETHSW_PM_MODULENR_MAX = 3 -+} IFX_PSB6970__t; -+#endif -+ -+#define IFX_ETHSW_PM_MODULENR_TANTOS3G 0x10 -+#define IFX_ETHSW_PM_MODULENR_GSWIP 0x20 -+ -+typedef struct { -+ IFX_void_t *pCoreDev; -+ IFX_boolean_t bPMThreadEnable; -+#ifndef IFXOS_SUPPORT -+ struct task_struct *pPMThread; -+ wait_queue_head_t PHY_wait; -+#endif -+#ifdef CONFIG_IFX_ETHSW_API_COC_PMCU -+ IFX_void_t *pPmcuCtx; -+#endif -+ IFX_void_t *pPlatCtx; -+} IFX_ETHSW_PM_CTX_t; -+ -+#ifdef IFXOS_SUPPORT -+ #define IFX_ETHSW_STACKSIZE 2048 -+ #define IFX_ETHSW_PRIORITY 64 -+ IFXOS_ThreadCtrl_t PHY_ThrCntrl; -+#endif -+ -+IFX_void_t *IFX_ETHSW_PM_powerManegementInit(IFX_void_t *pDev, IFX_uint8_t nModuleNr); -+IFX_return_t IFX_ETHSW_PM_powerManegementCleanUp(IFX_void_t *pCtx); -+IFX_boolean_t IFX_ETHSW_PM_powerManegementStatusGet(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_powerStateD0(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_powerStateD1(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_powerManagementActivated(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_powerManagementDeActivated(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_PM_linkForceSet(IFX_void_t *pCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bLinkForce); -+//IFX_return_t IFX_PSB6970_allPHY_powerup(IFX_void_t *pDevCtx); -+//IFX_return_t IFX_PSB6970_allPHY_powerdown(IFX_void_t *pDevCtx); -+ -+#endif /* _IFX_ETHSW_PM_H_ */ -diff --git a/include/switch_api/ifx_ethsw_pm_plat.h b/include/switch_api/ifx_ethsw_pm_plat.h -new file mode 100644 -index 0000000..3175cd6 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_pm_plat.h -@@ -0,0 +1,63 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_pm_plat.h -+ \remarks power management header file for platform dependency. -+ ****************************************************************************/ -+#ifndef _IFX_ETHSW_PM_PLAT_H_ -+#define _IFX_ETHSW_PM_PLAT_H_ -+#include <ifx_ethsw_api.h> -+ -+/*********************************************/ -+/* Structure and Enumeration Type Defintions */ -+/*********************************************/ -+#if defined(CONFIG_VR9) -+ #define PHY_NO 6 -+#endif /* CONFIG_VR9 */ -+#if defined(CONFIG_AR9) -+ #define PHY_NO 5 -+#endif /* CONFIG_AR9 */ -+typedef struct { -+ IFX_boolean_t bStatus; // for debug -+ IFX_boolean_t bLinkForce; -+ IFX_uint8_t nPHYAddr; -+} IFX_ETHSW_PHY_t; -+ -+typedef struct { -+ IFX_void_t *pPMCtx; -+ IFX_uint8_t nPHYNum; -+ IFX_ETHSW_PHY_t PHY[PHY_NO]; -+} IFX_ETHSW_PMPlatCTX_t; -+ -+/************************/ -+/* Function Propotype */ -+/************************/ -+IFX_void_t *IFX_ETHSW_PM_PLAT_Init(IFX_void_t *pCtx, IFX_uint8_t nModuleNr); -+IFX_return_t IFX_ETHSW_PM_PLAT_CleanUp(IFX_void_t *pCtx); -+IFX_boolean_t IFX_ETHSW_PHY_MDstatusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYAddr); -+IFX_boolean_t IFX_ETHSW_PHY_statusSet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bStatus); -+IFX_boolean_t IFX_ETHSW_PHY_statusGet(IFX_void_t *pDevCtx, IFX_uint8_t nPHYIdx); -+IFX_return_t IFX_ETHSW_PHY_powerDown(IFX_void_t *pDevCtx, IFX_uint8_t nPHYNum); -+IFX_return_t IFX_ETHSW_PHY_powerUp(IFX_void_t *pDevCtx, IFX_uint8_t nPHYNum); -+IFX_return_t IFX_ETHSW_AllPHY_powerDown(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); -+IFX_return_t IFX_ETHSW_AllPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); -+IFX_int_t IFX_ETHSW_AllPHY_LinkStatus(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); -+IFX_return_t IFX_ETHSW_PM_PLAT_linkForceSet(IFX_void_t *pPlatCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t bLinkForce); -+IFX_return_t IFX_ETHSW_PM_PLAT_linkForceGet(IFX_void_t *pPlatCtx, IFX_uint8_t nPHYIdx, IFX_boolean_t *pLinkForce); -+IFX_return_t IFX_ETHSW_PHY_Link_Up(IFX_void_t *pCtx); -+IFX_int_t IFX_ETHSW_PHY_Link_Status(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_PHY_Link_Down(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_EXT_PHY_Link_Up(IFX_void_t *pCtx) ; -+IFX_return_t IFX_ETHSW_INT_PHY_Link_Down(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_EXT_PHY_Link_Down(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_INT_PHY_Link_Up(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_AllintPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); -+IFX_return_t IFX_ETHSW_AllextPHY_powerUp(IFX_void_t *pDevCtx, IFX_void_t *pPlatCtx); -+ -+#endif /* _IFX_ETHSW_PM_PLAT_H_ */ -diff --git a/include/switch_api/ifx_ethsw_pm_pmcu.h b/include/switch_api/ifx_ethsw_pm_pmcu.h -new file mode 100644 -index 0000000..a1e3198 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_pm_pmcu.h -@@ -0,0 +1,36 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_pm_pmcu.h -+ \remarks power management header file -+ ****************************************************************************/ -+#ifndef _IFX_ETHSW_PM_PMCU_H_ -+#define _IFX_ETHSW_PM_PMCU_H_ -+ -+#include <ifx_ethsw_api.h> -+#include <ifx_pmcu.h> -+ -+/*********************************************/ -+/* Structure and Enumeration Type Defintions */ -+/*********************************************/ -+typedef struct { -+ IFX_void_t *pPMCtx; -+ IFX_PMCU_STATE_t ePMCU_State; -+ IFX_uint8_t nModuleNr; -+} IFX_ETHSW_PM_PMCUCtx_t; -+ -+ -+/************************/ -+/* Function Declaration */ -+/************************/ -+IFX_void_t *IFX_ETHSW_PM_PMCU_Init(IFX_void_t *pCtx, IFX_uint8_t nModuleNr); -+IFX_return_t IFX_ETHSW_PM_PMCU_CleanUp(IFX_void_t *pCtx); -+IFX_return_t IFX_ETHSW_PM_PMCU_StateReq(IFX_PMCU_STATE_t newState); -+ -+#endif /* _IFX_ETHSW_PM_PMCU_H_ */ -diff --git a/include/switch_api/ifx_ethsw_ral.h b/include/switch_api/ifx_ethsw_ral.h -new file mode 100644 -index 0000000..20c7094 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_ral.h -@@ -0,0 +1,56 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_ral.h -+ \remarks Register Access Layer header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_RAL_H_ -+#define _IFX_ETHSW_RAL_H_ -+ -+#include "ifx_ethsw_api.h" -+ -+#define REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) -+ -+#define IFX_PSB6970_AR9_BASEADDR (KSEG1 | 0x1E108000) -+#define IFX_PSB6970_TANTOS_3G_BASEADDR (KSEG1 | 0x1E1080CC) -+#define IFX_DANUBE_PPE_BASEADDR (KSEG1 | 0x1E191804) -+#define IFX_AMAZON_SE_PPE_BASEADDR (KSEG1 | 0x1E191804) -+ -+#define IFX_PSB6970_MDIO_OP_SHIFT 10 -+#define IFX_PSB6970_MDIO_MBUSY_SHIFT 15 -+#define IFX_PSB6970_MDIO_WD_SHIFT 16 -+#define IFX_PSB6970_MDIO_READ_OPERATION 0x02 -+#define IFX_PSB6970_MDIO_WRITE_OPERATION 0x01 -+ -+#define IFX_DANUBE_MDIO_RA_SHIFT 31 -+#define IFX_DANUBE_MDIO_RW_SHIFT 30 -+#define IFX_DANUBE_MDIO_REGADDR_SHIFT 16 -+#define IFX_AMAZON_SE_MDIO_RA_SHIFT 31 -+#define IFX_AMAZON_SE_MDIO_RW_SHIFT 30 -+#define IFX_AMAZON_SE_MDIO_REGADDR_SHIFT 16 -+typedef struct -+{ -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); -+ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); -+ IFX_PSB6970_devType_t eDev; -+ IFX_uint32_t nBaseAddress; -+} IFX_PSB6970_RAL_Dev_t; -+ -+typedef struct -+{ -+ IFX_PSB6970_devType_t eDev; -+}IFX_PSB6970_RAL_Init_t; -+ -+IFX_return_t IFX_PSB6970_RAL_Register_DirectRead(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); -+IFX_return_t IFX_PSB6970_RAL_Register_DirectWrite(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); -+IFX_return_t IFX_PSB6970_RAL_Register_MDIORead(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); -+IFX_return_t IFX_PSB6970_RAL_Register_MDIOWrite(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); -+IFX_void_t *IFX_PSB6970_RAL_init(IFX_PSB6970_RAL_Init_t *pInit); -+#endif /* _IFX_ETHSW_RAL_H_ */ -diff --git a/include/switch_api/ifx_ethsw_reg_access.h b/include/switch_api/ifx_ethsw_reg_access.h -new file mode 100644 -index 0000000..f2f00ce ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_reg_access.h -@@ -0,0 +1,38 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_reg_access.h" -+ \remarks -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_REG_ACCESS_H -+#define _IFX_ETHSW_REG_ACCESS_H -+ -+#include "ifx_ethsw_api.h" -+#include "ifx_ethsw_vr9_reg_access.h" -+ -+#define VR9_BASE_ADDRESS (KSEG1 | 0x1E108000) -+#define VR9_REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) -+ -+typedef struct -+{ -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int16_t, IFX_int16_t, IFX_int16_t, IFX_uint32_t); -+ IFX_uint32_t (* register_read)(IFX_void_t *, IFX_int16_t , IFX_int16_t , IFX_int16_t , IFX_uint32_t *); -+ IFX_FLOW_devType_t eDev; -+ IFX_uint32_t nBaseAddress; -+} IFX_FLOW_RAL_Dev_t; -+ -+typedef struct -+{ -+ IFX_FLOW_devType_t eDev; -+}IFX_FLOW_RAL_Init_t; -+ -+IFX_void_t *IFX_FLOW_RAL_init(IFX_FLOW_RAL_Init_t *pInit); -+ -+ -+#endif /* _IFX_ETHSW_REG_ACCESS.H */ -diff --git a/include/switch_api/ifx_ethsw_rml.h b/include/switch_api/ifx_ethsw_rml.h -new file mode 100644 -index 0000000..109aee6 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_rml.h -@@ -0,0 +1,49 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_rml.h -+ \remarks Register Mapping Layer header file, for Infineon Ethernet switch -+ drivers -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_RML_H_ -+#define _IFX_ETHSW_RML_H_ -+ -+#include "ifx_ethsw_api.h" -+ -+typedef struct -+{ -+ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); -+ IFX_void_t *pRegAccessHandle; -+ IFX_uint32_t nBaseAddress; -+ IFX_ETHSW_regMapper_t *tableHandle; -+} IFX_PSB6970_RML_Dev_t; -+ -+typedef struct -+{ -+ IFX_return_t (* register_read)(IFX_void_t *, IFX_int32_t, IFX_uint32_t *); -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t); -+ IFX_void_t *pRegAccessHandle; -+ IFX_uint32_t nBaseAddress; -+ IFX_PSB6970_devType_t eDev; -+}IFX_PSB6970_RML_Init_t; -+ -+ -+IFX_return_t IFX_PSB6970_RML_RegisterGet(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t * value); -+IFX_return_t IFX_PSB6970_RML_RegisterSet(IFX_void_t *pDevCtx , IFX_int32_t RegAddr, IFX_uint32_t value); -+IFX_return_t IFX_PSB6970_RML_Read(IFX_void_t * pDevCtx, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t *pvalue); -+IFX_return_t IFX_PSB6970_RML_Write(IFX_void_t *pDevCtx, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t value); -+IFX_void_t *IFX_PSB6970_RML_init(IFX_PSB6970_RML_Init_t *pInit); -+#endif /* _IFX_ETHSW_RML_H_ */ -diff --git a/include/switch_api/ifx_ethsw_vr9_reg_access.h b/include/switch_api/ifx_ethsw_vr9_reg_access.h -new file mode 100644 -index 0000000..e6fce10 ---- /dev/null -+++ b/include/switch_api/ifx_ethsw_vr9_reg_access.h -@@ -0,0 +1,23 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_reg_access.h" -+ \remarks -+ *****************************************************************************/ -+#ifndef _IFX_ETHSW_REG_ACCESS_H -+#define _IFX_ETHSW_REG_ACCESS_H -+ -+#include "ifx_types.h" -+ -+IFX_int32_t ifx_ethsw_ll_DirectAccessRead -+(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t * value); -+IFX_return_t ifx_ethsw_ll_DirectAccessWrite -+(IFX_void_t *pDevCtx, IFX_int16_t Offset, IFX_int16_t Shift, IFX_int16_t Size, IFX_uint32_t value); -+ -+#endif /* _IFX_ETHSW_REG_ACCESS.H */ -diff --git a/include/switch_api/ifx_switch_ll.h b/include/switch_api/ifx_switch_ll.h -new file mode 100644 -index 0000000..47b8aff ---- /dev/null -+++ b/include/switch_api/ifx_switch_ll.h -@@ -0,0 +1,101 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifx_ethsw_ll.h" -+ \remarks -+ *****************************************************************************/ -+ -+#ifndef _IFX_ETHSW_LL_ACCESS_H_ -+#define _IFX_ETHSW_LL_ACCESS_H_ -+ -+#include "ifx_ethsw.h" -+#include "regmapper.h" -+ -+#define INTERNAL_ACCESS 0 -+#define EXTERNAL_ACCESS 1 -+ -+#define AMAZON_S_SW (KSEG1 | 0x1E108000) -+#define BASE_ADDRESS (KSEG1 | 0x1E108000) -+#define REG32_ACCESS(addr) *((volatile IFX_int32_t *)(addr)) -+#define AMAZON_S_SW_REG(off) ((volatile IFX_int32_t*)(AMAZON_S_SW + (off))) -+ -+ -+#define IFX_DEV_TANTOS_3G_BASEADDR AMAZON_S_SW_REG(0x0cc) -+#define IFX_DEV_AR9_BASEADDR AMAZON_S_SW_REG(0x000) -+ -+ -+typedef enum -+{ -+ IFX_RML_DEV_TANTOS_3G, -+ IFX_RML_DEV_AR9 -+} IFX_RML_Dev_t; -+ -+typedef struct -+{ -+ /** ?? */ -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t ); -+ /** ?? */ -+ IFX_int32_t (* register_read)(IFX_ETHSW_regMapper_t *, IFX_int32_t, IFX_uint32_t *); -+ /** ?? */ -+ IFX_void_t * pRegAccessHandle; -+ /** ?? */ -+ IFX_uint32_t nBaseAddress; -+ /** ?? */ -+ IFX_RML_Dev_t eDev; -+ /** Low Level Ethernet Switch driverName */ -+ IFX_char_t *drvName; -+} IFX_ETHSW_RML_Init_t; -+ -+ -+typedef struct -+{ -+ /** ?? */ -+ IFX_return_t (* register_write)(IFX_void_t *, IFX_int32_t, IFX_uint32_t ); -+ /** ?? */ -+ IFX_int32_t (* register_read)(IFX_ETHSW_regMapper_t *, IFX_int32_t, IFX_uint32_t *); -+ /** ?? */ -+ IFX_void_t *pRegAccessHandle; -+ /** ?? */ -+ IFX_uint32_t nBaseAddress; -+ /** ?? */ -+ IFX_RML_Dev_t eDev; -+ /** ?? */ -+ IFX_ETHSW_regMapper_t *tableHandle; -+} RML_Dev_t; -+ -+ -+/* AMAZON_S GPORT SWITCH Register */ -+ -+#define AMAZON_S_BASEADDR (KSEG1 | 0x1E108000) -+#define AMAZON_S_DF_PORTMAP (AMAZON_S_BASEADDR + 0x02C) -+ -+ -+IFX_return_t IFX_ethsw_RML_Read(RML_Dev_t* pCxtHandle, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t *value); -+IFX_return_t IFX_ethsw_RML_Write(RML_Dev_t *pCxtHandle, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t value); -+ -+IFX_return_t IFX_ethsw_RML_Tantos3G_Read(RML_Dev_t* pCxtHandle, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t *value); -+ -+IFX_return_t IFX_ethsw_RML_Tantos3G_Write(RML_Dev_t *pCxtHandle, -+ IFX_ETHSW_regMapperSelector_t commonbit, -+ IFX_uint32_t portIdx, -+ IFX_uint32_t value); -+ -+IFX_return_t IFX_Register_RML_init(IFX_ETHSW_RML_Init_t *pInit); -+ -+#endif -+ -diff --git a/include/switch_api/ifx_types.h b/include/switch_api/ifx_types.h -new file mode 100644 -index 0000000..c28aaae ---- /dev/null -+++ b/include/switch_api/ifx_types.h -@@ -0,0 +1,118 @@ -+#ifndef _IFX_TYPES_H -+#define _IFX_TYPES_H -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ Module : ifx_types.h -+*******************************************************************************/ -+ -+/** \defgroup IFX_BASIC_TYPES Basic IFX Data Types -+ This section describes the basic IFX data type definitions.*/ -+/*@{*/ -+ -+/** This is the character datatype. */ -+typedef char IFX_char_t; -+/** This is the integer datatype. */ -+typedef signed int IFX_int_t; -+/** This is the unsigned integer datatype. */ -+typedef unsigned int IFX_uint_t; -+ -+/** This is the unsigned 8-bit datatype. */ -+typedef unsigned char IFX_uint8_t; -+/** This is the signed 8-bit datatype. */ -+typedef signed char IFX_int8_t; -+/** This is the unsigned 16-bit datatype. */ -+typedef unsigned short IFX_uint16_t; -+/** This is the signed 16-bit datatype. */ -+typedef signed short IFX_int16_t; -+/** This is the unsigned 32-bit datatype. */ -+typedef unsigned int IFX_uint32_t; -+/** This is the signed 32-bit datatype. */ -+typedef signed int IFX_int32_t; -+/** This is the unsigned 64-bit datatype. */ -+typedef unsigned long long int IFX_uint64_t; -+/** This is the signed 64-bit datatype. */ -+typedef signed long long int IFX_int64_t; -+/** This is the float datatype. */ -+typedef float IFX_float_t; -+/** This is the void datatype. */ -+typedef void IFX_void_t; -+ -+/** This is the volatile unsigned 8-bit datatype. */ -+typedef volatile IFX_uint8_t IFX_vuint8_t; -+/** This is the volatile signed 8-bit datatype. */ -+typedef volatile IFX_int8_t IFX_vint8_t; -+/** This is the volatile unsigned 16-bit datatype. */ -+typedef volatile IFX_uint16_t IFX_vuint16_t; -+/** This is the volatile signed 16-bit datatype. */ -+typedef volatile IFX_int16_t IFX_vint16_t; -+/** This is the volatile unsigned 32-bit datatype. */ -+typedef volatile IFX_uint32_t IFX_vuint32_t; -+/** This is the volatile signed 32-bit datatype. */ -+typedef volatile IFX_int32_t IFX_vint32_t; -+/** This is the volatile unsigned 64-bit datatype. */ -+typedef volatile IFX_uint64_t IFX_vuint64_t; -+/** This is the volatile signed 64-bit datatype. */ -+typedef volatile IFX_int64_t IFX_vint64_t; -+/** This is the volatile float datatype. */ -+typedef volatile IFX_float_t IFX_vfloat_t; -+ -+ -+/** A type for handling boolean issues. */ -+typedef enum { -+ /** False. */ -+ IFX_FALSE = 0, -+ /** True. */ -+ IFX_TRUE = 1 -+} IFX_boolean_t; -+ -+ -+/** This type is used for parameters that should enable and disable a -+dedicated feature. */ -+typedef enum { -+ /** Disable. */ -+ IFX_DISABLE = 0, -+ /** Enable. */ -+ IFX_ENABLE = 1 -+} IFX_enDis_t; -+ -+/** This type is used for parameters that should enable and disable a dedicated -+ feature. */ -+typedef IFX_enDis_t IFX_operation_t; -+ -+/** This type has two states, even and odd.*/ -+typedef enum { -+ /** Even. */ -+ IFX_EVEN = 0, -+ /** Odd. */ -+ IFX_ODD = 1 -+} IFX_evenOdd_t; -+ -+ -+/** This type has two states, high and low. */ -+typedef enum { -+ /** Low. */ -+ IFX_LOW = 0, -+ /** High. */ -+ IFX_HIGH = 1 -+} IFX_highLow_t; -+ -+/** This type has two states, success and error. */ -+typedef enum { -+ /** Operation failed. */ -+ IFX_ERROR = (-1), -+ /** Operation succeeded. */ -+ IFX_SUCCESS = 0 -+} IFX_return_t; -+ -+#define IFX_NULL ((void *)0) -+/*@}*/ /* IFX_BASIC_TYPES */ -+ -+#endif /* _IFX_TYPES_H */ -+ -diff --git a/include/switch_api/ifxmips_gphy_sw.h b/include/switch_api/ifxmips_gphy_sw.h -new file mode 100644 -index 0000000..617b706 ---- /dev/null -+++ b/include/switch_api/ifxmips_gphy_sw.h -@@ -0,0 +1,124 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ -+ \file ifxmips_gphy_sw.h -+ \remarks implement GPHY driver on VR9 platform -+ *****************************************************************************/ -+ -+#ifndef _IFXMIPS_GPHY_SW_H_ -+#define _IFXMIPS_GPHY_SW_H_ -+ -+#include <asm/ifx/ifx_rcu.h> -+#include <asm/ifx/ifx_pmu.h> -+#include <asm/ifx/ifx_gpio.h> -+ -+/** default board related configuration */ -+#if defined(CONFIG_MII0_PORT_ENABLED) -+#define CONFIG_MAC0 1 -+#else -+#define CONFIG_MAC0 0 -+#endif -+ -+#if defined(CONFIG_MII1_PORT_ENABLED) -+#define CONFIG_MAC1 1 -+#else -+#define CONFIG_MAC1 0 -+#endif -+ -+#if defined(CONFIG_MII2_PORT_ENABLED) -+#define CONFIG_MAC2 1 -+#else -+#define CONFIG_MAC2 0 -+#endif -+ -+#if defined(CONFIG_MII3_PORT_ENABLED) -+#define CONFIG_MAC3 1 -+#else -+#define CONFIG_MAC3 0 -+#endif -+ -+#if defined(CONFIG_MII4_PORT_ENABLED) -+#define CONFIG_MAC4 1 -+#else -+#define CONFIG_MAC4 0 -+#endif -+ -+#if defined(CONFIG_MII5_PORT_ENABLED) -+#define CONFIG_MAC5 1 -+#else -+#define CONFIG_MAC5 0 -+#endif -+ -+#if defined(CONFIG_MII0_RGMII_MAC_MODE) -+#define MII0_MODE_SETUP RGMII_MODE -+#elif defined(CONFIG_MII0_RMII_MAC_MODE) -+#define MII0_MODE_SETUP RMII_MAC_MODE -+#elif defined(CONFIG_MII0_RMII_PHY_MODE) -+#define MII0_MODE_SETUP RMII_PHY_MODE -+#elif defined(CONFIG_MII0_MII_MAC_MODE) -+#define MII0_MODE_SETUP MII_MAC_MODE -+#elif defined(CONFIG_MII0_MII_PHY_MODE) -+#define MII0_MODE_SETUP MII_PHY_MODE -+#endif -+ -+#if defined(CONFIG_MII1_RGMII_MAC_MODE) -+#define MII1_MODE_SETUP RGMII_MODE -+#elif defined(CONFIG_MII1_RMII_MAC_MODE) -+#define MII1_MODE_SETUP RMII_MAC_MODE -+#elif defined(CONFIG_MII1_RMII_PHY_MODE) -+#define MII1_MODE_SETUP RMII_PHY_MODE -+#elif defined(CONFIG_MII1_MII_MAC_MODE) -+#define MII1_MODE_SETUP MII_MAC_MODE -+#elif defined(CONFIG_MII1_MII_PHY_MODE) -+#define MII1_MODE_SETUP MII_PHY_MODE -+#endif -+ -+#if defined(CONFIG_MII2_GMII_MODE) -+#define MII2_MODE_SETUP GMII_MAC_MODE -+#elif defined(CONFIG_MII2_MII_MAC_MODE) -+#define MII2_MODE_SETUP MII_MAC_MODE -+#endif -+ -+#if defined(CONFIG_MII3_MII_MAC_MODE) -+#define MII3_MODE_SETUP MII_MAC_MODE -+#endif -+ -+#if defined(CONFIG_MII4_GMII_MODE) -+#define MII4_MODE_SETUP GMII_MAC_MODE -+#elif defined(CONFIG_MII4_MII_MAC_MODE) -+#define MII4_MODE_SETUP MII_MAC_MODE -+#endif -+ -+#if defined(CONFIG_MII5_RGMII_MODE) -+#define MII5_MODE_SETUP RGMII_MODE -+#elif defined(CONFIG_MII5_MII_MAC_MODE) -+#define MII5_MODE_SETUP MII_PHY_MODE -+#endif -+ -+ -+#ifdef CONFIG_SW_ROUTING_MODE -+ #define CONFIG_PMAC_DMA_ENABLE 1 /*g_pmac_dma */ -+ #define CONFIG_DMA_PMAC_ENABLE 1 /*g_dma_pmac*/ -+#else -+ #define CONFIG_PMAC_DMA_ENABLE 0 /*g_pmac_dma */ -+ #define CONFIG_DMA_PMAC_ENABLE 0 /*g_dma_pmac*/ -+#endif -+ -+#if defined(CONFIG_PMAC_DMA_ENABLE) && CONFIG_PMAC_DMA_ENABLE -+ #define NUM_ETH_INF 2 -+#else -+ #define NUM_ETH_INF 1 -+#endif -+ -+ -+#define GPHY_FW_LEN 65536 -+static const char gphy_fw_data[GPHY_FW_LEN]; -+ -+#endif /*_IFXMIPS_GPHY_SW_H_ */ -diff --git a/include/switch_api/ifxmips_sw_reg.h b/include/switch_api/ifxmips_sw_reg.h -new file mode 100644 -index 0000000..b988218 ---- /dev/null -+++ b/include/switch_api/ifxmips_sw_reg.h -@@ -0,0 +1,300 @@ -+/****************************************************************************** -+ -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file ifxmips_sw_reg.h -+ \remarks implement GPHY driver on VR9 platform -+ *****************************************************************************/ -+#ifndef _IFXMIPS_SW_REG_H -+#define _IFXMIPS_SW_REG_H -+ -+/** ========================== */ -+/* Include files */ -+/** =========================== */ -+#include <asm/ifx/ifx_regs.h> -+ -+/* ============================= */ -+/* Local Macros & Definitions */ -+/* ============================= */ -+ -+#define SW_WRITE_REG32(data,addr) IFX_REG_W32((data), (volatile unsigned int *)addr) -+#define SW_READ_REG32(addr) IFX_REG_R32((volatile unsigned int *)addr) -+ -+/** Registers Description */ -+ -+#define VR9_GPIO_BASE_ADDR (0xBE100B00) -+ -+/* Port 0 Direction Register */ -+#define P0_DIR (VR9_GPIO_BASE_ADDR + 0x18) -+/* Port 0 Alternate Function Select Register 0 */ -+#define P0_ALTSEL0 (VR9_GPIO_BASE_ADDR + 0x1C) -+/* Port 0 Alternate Function Select Register 1 */ -+#define P0_ALTSEL1 (VR9_GPIO_BASE_ADDR + 0x20) -+ -+ -+#define VR9_CGU_BASE_ADDR (0xBF103000) -+ -+/* Interface Clock Register */ -+#define IF_CLK (VR9_CGU_BASE_ADDR + 0x24) -+ -+ -+#define VR9_RCU_BASE_ADDR (0xBF203000) -+ -+/* Reset Request Register */ -+#define RST_REQ (VR9_RCU_BASE_ADDR + 0x10) -+/* GPHY0 Firmware Base Address Register */ -+#define GFS_ADD0 (VR9_RCU_BASE_ADDR + 0x20) -+/* GPHY1 Firmware Base Address Register */ -+#define GFS_ADD1 (VR9_RCU_BASE_ADDR + 0x68) -+ -+ -+#define VR9_PMU_BASE_ADDR (0xBF102000) -+ -+/* PMU Power down Control Register */ -+#define PMU_PWDCR (VR9_PMU_BASE_ADDR + 0x1C) -+ -+ -+#define VR9_SWIP_BASE_ADDR (0xBE108000) -+#define VR9_SWIP_TOP_BASE_ADDR (VR9_SWIP_BASE_ADDR + (0x0C40 * 4)) -+/** Switch Reset Control register */ -+#define ETHSW_SWRES_REG (VR9_SWIP_BASE_ADDR) -+/** Register Configuration Resets all registers to their default state (such as after a hardware reset). -+* 0B RUN reset is off, 1B STOP reset is active */ -+#define SWRES_R0 0x0001 -+/** Hardware Reset Reset all hardware modules except for the register settings. -+* 0B RUN reset is off, 1B STOP reset is active */ -+#define SWRES_R1 0x0002 -+ -+/** Ethernet Switch Clock Control Register */ -+#define ETHSW_CLK_REG (VR9_SWIP_BASE_ADDR + (1 * 4)) -+ -+/** MAC Frame Length Register */ -+#define MAC_FLEN_REG (VR9_SWIP_BASE_ADDR + (0x8C5 * 4) ) -+#define MAC_FLEN(arg) ( (arg & 0x3FFF)) -+ -+/** MAC Port Status Register */ -+#define MAC_0_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x900 * 4) ) -+#define MAC_1_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x90C * 4) ) -+#define MAC_2_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x918 * 4) ) -+#define MAC_3_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x924 * 4) ) -+#define MAC_4_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x930 * 4) ) -+#define MAC_5_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x93C * 4) ) -+#define MAC_6_PSTAT_REG (VR9_SWIP_BASE_ADDR + (0x948 * 4) ) -+ -+/** MAC Control Register 0 */ -+#define MAC_0_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x903 * 4) ) -+#define MAC_1_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x90F * 4) ) -+#define MAC_2_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x91B * 4) ) -+#define MAC_3_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x927 * 4) ) -+#define MAC_4_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x933 * 4) ) -+#define MAC_5_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x93F * 4) ) -+#define MAC_6_CTRL_0 (VR9_SWIP_BASE_ADDR + (0x94B * 4) ) -+ -+#define MAC_CTRL_0_FCON_MASK 0x0070 -+#define MAC_CTRL_0_FCON_AUTO 0x0000 -+#define MAC_CTRL_0_FCON_RX 0x0010 -+#define MAC_CTRL_0_FCON_TX 0x0020 -+#define MAC_CTRL_0_FCON_RXTX 0x0030 -+#define MAC_CTRL_0_FCON_NONE 0x0040 -+ -+#define MAC_CTRL_0_FDUP_MASK 0x000C -+#define MAC_CTRL_0_FDUP_AUTO 0x0000 -+#define MAC_CTRL_0_FDUP_EN 0x0004 -+#define MAC_CTRL_0_FDUP_DIS 0x000C -+ -+#define MAC_CTRL_0_GMII_MASK 0x0003 -+#define MAC_CTRL_0_GMII_AUTO 0x0000 -+#define MAC_CTRL_0_GMII_MII 0x0001 -+#define MAC_CTRL_0_GMII_RGMII 0x0002 -+ -+/** Ethernet Switch Fetch DMA Port Control -+ Controls per-port functions of the Fetch DMA */ -+#define FDMA_PCTRL_PORT6 (VR9_SWIP_BASE_ADDR + (0xAA4 * 4) ) -+/** Special Tag Insertion Enable(to egress frames )*/ -+#define FDMA_PCTRL_STEN (1 << 1) -+ -+/** VR9 Switch Subsystem Top Level Registers */ -+ -+/** Global Control Register 0 */ -+#define GLOB_CTRL_REG (VR9_SWIP_TOP_BASE_ADDR) -+/** Global Software Reset Reset all hardware modules excluding the register settings. -+* 0B OFF reset is off, 1B ON reset is active */ -+#define GLOB_CTRL_SWRES 0x0001 -+/** Global Hardware Reset Reset all hardware modules including the register settings. -+* 0B OFF reset is off, 1B ON reset is active */ -+#define GLOB_CTRL_HWRES 0x0002 -+/** Global Switch Macro Enable If set to OFF, the switch macro is inactive and frame forwarding is disabled. -+* 0B OFF switch macro is not active, 1B ON switch macro is active */ -+#define GLOB_CTRL_SE 0x8000 -+ -+/** MDIO Control Register */ -+#define MDIO_CTRL_REG (VR9_SWIP_TOP_BASE_ADDR + (8 * 4)) -+/** MDIO Busy*/ -+#define MDIO_CTRL_MBUSY 0x1000 -+#define MDIO_CTRL_OP_MASK 0x0C00 -+#define MDIO_CTRL_OP_WR 0x0400 -+#define MDIO_CTRL_OP_RD 0x0800 -+#define MDIO_CTRL_PHYAD_SET(arg) ((arg & 0x1F) << 5) -+#define MDIO_CTRL_PHYAD_GET(arg) ( (arg >> 5 ) & 0x1F) -+#define MDIO_CTRL_REGAD(arg) ( arg & 0x1F) -+ -+/** MDIO Read Data Register */ -+#define MDIO_READ_REG (VR9_SWIP_TOP_BASE_ADDR + (9 * 4)) -+#define MDIO_READ_RDATA(arg) (arg & 0xFFFF) -+ -+/** MDIO Write Data Register */ -+#define MDIO_WRITE_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0A * 4)) -+#define MDIO_READ_WDATA(arg) (arg & 0xFFFF) -+ -+/** MDC Clock Configuration Register 0 */ -+#define MDC_CFG_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0B * 4)) -+#define MDC_CFG_0_PEN_SET(port) (0x1 << port ) -+#define MDC_CFG_0_PEN_GET(port, reg_data) ((reg_data >> port ) & 0x1 ) -+/** MDC Clock Configuration Register 1 */ -+#define MDC_CFG_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x0C * 4)) -+ -+/** PHY Address Register PORT 5~0 */ -+#define PHY_ADDR_5 (VR9_SWIP_TOP_BASE_ADDR + (0x10 * 4)) -+#define PHY_ADDR_4 (VR9_SWIP_TOP_BASE_ADDR + (0x11 * 4)) -+#define PHY_ADDR_3 (VR9_SWIP_TOP_BASE_ADDR + (0x12 * 4)) -+#define PHY_ADDR_2 (VR9_SWIP_TOP_BASE_ADDR + (0x13 * 4)) -+#define PHY_ADDR_1 (VR9_SWIP_TOP_BASE_ADDR + (0x14 * 4)) -+#define PHY_ADDR_0 (VR9_SWIP_TOP_BASE_ADDR + (0x15 * 4)) -+/** Link Status Control */ -+#define PHY_ADDR_LINKST_MASK 0x6000 -+#define PHY_ADDR_LINKST_AUTO 0x0000 -+#define PHY_ADDR_LINKST_UP 0x2000 -+#define PHY_ADDR_LINKST_DOWN 0x4000 -+/** Speed Control */ -+#define PHY_ADDR_SPEED_MASK 0x1800 -+#define PHY_ADDR_SPEED_10 0x0000 -+#define PHY_ADDR_SPEED_100 0x0800 -+#define PHY_ADDR_SPEED_1000 0x1000 -+#define PHY_ADDR_SPEED_AUTO 0x1800 -+/** Full Duplex Control */ -+#define PHY_ADDR_FDUP_MASK 0x0600 -+#define PHY_ADDR_FDUP_AUTO 0x0000 -+#define PHY_ADDR_FDUP_EN 0x0200 -+#define PHY_ADDR_FDUP_DIS 0x0600 -+/** Flow Control Mode TX */ -+#define PHY_ADDR_FCONTX_MASK 0x0180 -+#define PHY_ADDR_FCONTX_AUTO 0x0000 -+#define PHY_ADDR_FCONTX_EN 0x0080 -+#define PHY_ADDR_FCONTX_DIS 0x0180 -+/** Flow Control Mode RX */ -+#define PHY_ADDR_FCONRX_MASK 0x0060 -+#define PHY_ADDR_FCONRX_AUTO 0x0000 -+#define PHY_ADDR_FCONRX_EN 0x0020 -+#define PHY_ADDR_FCONRX_DIS 0x0060 -+/** PHY Address */ -+#define PHY_ADDR_ADDR(arg) (arg & 0x1F) -+ -+/** PHY MDIO Polling Status per PORT */ -+#define MDIO_STAT_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x16 * 4)) -+#define MDIO_STAT_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x17 * 4)) -+#define MDIO_STAT_2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x18 * 4)) -+#define MDIO_STAT_3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x19 * 4)) -+#define MDIO_STAT_4_REG (VR9_SWIP_TOP_BASE_ADDR + (0x1A * 4)) -+#define MDIO_STAT_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x1B * 4)) -+/** PHY Active Status */ -+#define MDIO_STAT_PACT 0x0040 -+#define MDIO_STAT_LSTAT 0x0020 -+#define MDIO_STAT_SPEED(arg) ( (arg >> 0x3) & 0x03) -+#define MDIO_STAT_FDUP 0x0004 -+#define MDIO_STAT_RXPAUEN 0x0002 -+#define MDIO_STAT_TXPAUEN 0x0001 -+ -+/** xMII Control Registers */ -+/** xMII Port 0 Configuration register */ -+#define MII_CFG_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x36 * 4)) -+#define MII_CFG_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x38 * 4)) -+#define MII_CFG_2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3A * 4)) -+#define MII_CFG_3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3C * 4)) -+#define MII_CFG_4_REG (VR9_SWIP_TOP_BASE_ADDR + (0x3E * 4)) -+#define MII_CFG_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x40 * 4)) -+#define MII_CFG_RES 0x8000 -+#define MII_CFG_EN 0x4000 -+/** Bits are only valid in PHY Mode */ -+#define MII_CFG_CRS_SET(arg) ( (arg & 0x03) << 0x9) -+#define MII_CFG_CRS_GET(arg) ( (arg >> 0x9) & 0x03) -+/** RGMII In Band Status */ -+#define MII_CFG_RGMII_IBS 0x0100 -+/** RMII Reference Clock Direction of the Port */ -+#define MII_CFG_RMII_OUT 0x0080 -+/** xMII Port Interface Clock Rate */ -+#define MII_CFG_MIIRATE_MASK 0x0070 -+#define MII_CFG_MIIRATE_2_5MHZ 0x0000 -+#define MII_CFG_MIIRATE_25MHZ 0x0010 -+#define MII_CFG_MIIRATE_125MHZ 0x0020 -+#define MII_CFG_MIIRATE_50MHZ 0x0030 -+#define MII_CFG_MIIRATE_AUTO 0x0040 -+/** xMII Interface Mode */ -+#define MII_CFG_MIIMODE_MASK 0x000F -+#define MII_CFG_MIIMODE_MIIP 0x0000 -+#define MII_CFG_MIIMODE_MIIM 0x0001 -+#define MII_CFG_MIIMODE_RMIIP 0x0002 -+#define MII_CFG_MIIMODE_RMIIM 0x0003 -+#define MII_CFG_MIIMODE_RGMII 0x0004 -+ -+/** Configuration of Clock Delay for Port 0 (used for RGMII mode only)*/ -+#define MII_PCDU_0_REG (VR9_SWIP_TOP_BASE_ADDR + (0x37 * 4)) -+#define MII_PCDU_1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x39 * 4)) -+#define MII_PCDU_5_REG (VR9_SWIP_TOP_BASE_ADDR + (0x41 * 4)) -+#define MII_PCDU_RXLOCK 0x8000 -+#define MII_PCDU_TXLOCK 0x4000 -+#define MII_PCDU_RXSEL_CLK_MASK 0x3000 -+#define MII_PCDU_RXSEL_CLK_AUTO 0x0000 -+#define MII_PCDU_RXSEL_CLK_RXCLK 0x1000 -+#define MII_PCDU_RXSEL_CLK_CLKREF 0x2000 -+#define MII_PCDU_RXINIT 0x0800 -+#define MII_PCDU_RXPD 0x0400 -+#define MII_PCDU_RXDLY_MASK 0x0380 -+ -+#define MII_PCDU_TXSEL_CLK_MASK 0x0060 -+#define MII_PCDU_TXSEL_CLK_AUTO 0x0000 -+#define MII_PCDU_TXSEL_CLK_TXCLK 0x0020 -+#define MII_PCDU_TXSEL_CLK_CLKREF 0x0040 -+#define MII_PCDU_TXINIT 0x0010 -+#define MII_PCDU_TXPD 0x0008 -+#define MII_PCDU_TXDLY_MASK 0x0007 -+ -+/** PMAC Header Control Register */ -+#define PMAC_HD_CTL_REG (VR9_SWIP_TOP_BASE_ADDR + (0x82 * 4)) -+#define PMAC_HD_CTL_FC 0x0400 -+#define PMAC_HD_CTL_CCRC 0x0200 -+#define PMAC_HD_CTL_RST 0x0100 -+#define PMAC_HD_CTL_AST 0x0080 -+#define PMAC_HD_CTL_RXSH 0x0040 -+#define PMAC_HD_CTL_RL2 0x0020 -+#define PMAC_HD_CTL_RC 0x0010 -+#define PMAC_HD_CTL_AS 0x0008 -+#define PMAC_HD_CTL_AC 0x0004 -+#define PMAC_HD_CTL_TAG 0x0002 -+#define PMAC_HD_CTL_ADD 0x0001 -+ -+/** PMAC Type/Length register */ -+#define PMAC_TL_REG (VR9_SWIP_TOP_BASE_ADDR + (0x83 * 4)) -+/** PMAC Source Address Register */ -+#define PMAC_SA1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x84 * 4)) -+#define PMAC_SA2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x85 * 4)) -+#define PMAC_SA3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x86 * 4)) -+/** PMAC Destination Address Register */ -+#define PMAC_DA1_REG (VR9_SWIP_TOP_BASE_ADDR + (0x87 * 4)) -+#define PMAC_DA2_REG (VR9_SWIP_TOP_BASE_ADDR + (0x88 * 4)) -+#define PMAC_DA3_REG (VR9_SWIP_TOP_BASE_ADDR + (0x89 * 4)) -+/** PMAC VLAN register */ -+#define PMAC_VLAN_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8A * 4)) -+/** PMAC Inter Packet Gap in RX Direction */ -+#define PMAC_RX_IPG_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8B * 4)) -+/** PMAC Special Tag Ethertype */ -+#define PMAC_ST_ETYPE_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8C * 4)) -+/** PMAC Ethernet WAN Group */ -+#define PMAC_EWAN_REG (VR9_SWIP_TOP_BASE_ADDR + (0x8D * 4)) -+ -+#endif /*_IFXMIPS_SW_REG_H */ -diff --git a/include/switch_api/regmapper.h b/include/switch_api/regmapper.h -new file mode 100644 -index 0000000..879e6dc ---- /dev/null -+++ b/include/switch_api/regmapper.h -@@ -0,0 +1,27 @@ -+/**************************************************************************** -+ Copyright (c) 2010 -+ Lantiq Deutschland GmbH -+ Am Campeon 3; 85579 Neubiberg, Germany -+ -+ For licensing information, see the file 'LICENSE' in the root folder of -+ this software module. -+ -+ ***************************************************************************** -+ \file regmapper.h -+ \remarks switch API header file, for Infineon Ethernet switch drivers -+ *****************************************************************************/ -+ -+#ifndef _REGMAPPER_H -+#define _REGMAPPER_H -+ -+#include "ifx_types.h" -+#include "commonReg.h" -+ -+typedef struct -+{ -+ IFX_uint16_t nCommonBitEnum; -+ IFX_uint16_t nRegOffset; -+ IFX_uint8_t nBitPosition; -+ IFX_uint8_t nBitSize; -+}IFX_ETHSW_regMapper_t; -+#endif /* #ifndef _REGMAPPER_H */ --- -1.7.9.1 - |