diff options
Diffstat (limited to 'target/linux/lantiq/patches-3.2/0062-MIPS-lantiq-fixes-ar9-vr9-clock.patch')
| -rw-r--r-- | target/linux/lantiq/patches-3.2/0062-MIPS-lantiq-fixes-ar9-vr9-clock.patch | 116 |
1 files changed, 116 insertions, 0 deletions
diff --git a/target/linux/lantiq/patches-3.2/0062-MIPS-lantiq-fixes-ar9-vr9-clock.patch b/target/linux/lantiq/patches-3.2/0062-MIPS-lantiq-fixes-ar9-vr9-clock.patch new file mode 100644 index 0000000000..1362446cec --- /dev/null +++ b/target/linux/lantiq/patches-3.2/0062-MIPS-lantiq-fixes-ar9-vr9-clock.patch @@ -0,0 +1,116 @@ +From 42cfda7eaf263248257cef40b88e06b7a0666eb4 Mon Sep 17 00:00:00 2001 +From: John Crispin <blogic@openwrt.org> +Date: Sat, 17 Mar 2012 09:58:07 +0100 +Subject: [PATCH 62/73] MIPS: lantiq: fixes ar9/vr9 clock + +--- + arch/mips/lantiq/clk.h | 4 +++- + arch/mips/lantiq/xway/clk.c | 29 ++++++++++++++++++++++++----- + arch/mips/lantiq/xway/sysctrl.c | 13 ++++++++----- + 3 files changed, 35 insertions(+), 11 deletions(-) + +diff --git a/arch/mips/lantiq/clk.h b/arch/mips/lantiq/clk.h +index b34e675..010dfa7 100644 +--- a/arch/mips/lantiq/clk.h ++++ b/arch/mips/lantiq/clk.h +@@ -56,8 +56,10 @@ extern unsigned long ltq_danube_cpu_hz(void); + extern unsigned long ltq_danube_fpi_hz(void); + extern unsigned long ltq_danube_io_region_clock(void); + ++extern unsigned long ltq_ar9_cpu_hz(void); ++extern unsigned long ltq_ar9_fpi_hz(void); ++ + extern unsigned long ltq_vr9_cpu_hz(void); + extern unsigned long ltq_vr9_fpi_hz(void); +-extern unsigned long ltq_vr9_io_region_clock(void); + + #endif +diff --git a/arch/mips/lantiq/xway/clk.c b/arch/mips/lantiq/xway/clk.c +index 3635c9f..2bafc04 100644 +--- a/arch/mips/lantiq/xway/clk.c ++++ b/arch/mips/lantiq/xway/clk.c +@@ -217,6 +217,30 @@ unsigned long ltq_danube_cpu_hz(void) + } + } + ++unsigned long ltq_ar9_sys_hz(void) ++{ ++ if (((ltq_cgu_r32(LTQ_CGU_SYS) >> 3) & 0x3) == 0x2) ++ return CLOCK_393M; ++ return CLOCK_333M; ++} ++ ++unsigned long ltq_ar9_fpi_hz(void) ++{ ++ unsigned long sys = ltq_ar9_sys_hz(); ++ ++ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(0)) ++ return sys; ++ return sys >> 1; ++} ++ ++unsigned long ltq_ar9_cpu_hz(void) ++{ ++ if (ltq_cgu_r32(LTQ_CGU_SYS) & BIT(2)) ++ return ltq_ar9_fpi_hz(); ++ else ++ return ltq_ar9_sys_hz(); ++} ++ + unsigned long ltq_danube_fpi_hz(void) + { + unsigned long ddr_clock = DDR_HZ; +@@ -299,11 +323,6 @@ unsigned long ltq_vr9_fpi_hz(void) + return clk; + } + +-unsigned long ltq_vr9_io_region_clock(void) +-{ +- return ltq_vr9_fpi_hz(); +-} +- + unsigned long ltq_vr9_fpi_bus_clock(int fpi) + { + return ltq_vr9_fpi_hz(); +diff --git a/arch/mips/lantiq/xway/sysctrl.c b/arch/mips/lantiq/xway/sysctrl.c +index 9df048c..6771a7e 100644 +--- a/arch/mips/lantiq/xway/sysctrl.c ++++ b/arch/mips/lantiq/xway/sysctrl.c +@@ -237,6 +237,8 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("ltq_ebu", NULL, 0, PMU_EBU); + if (!ltq_is_vr9()) + clkdev_add_pmu("ltq_etop", NULL, 0, PMU_PPE); ++ if (!ltq_is_ase()) ++ clkdev_add_pci(); + if (ltq_is_ase()) { + if (ltq_cgu_r32(CGU_SYS) & (1 << 5)) + clkdev_add_static(CLOCK_266M, CLOCK_133M, CLOCK_133M); +@@ -246,7 +248,7 @@ void __init ltq_soc_init(void) + clkdev_add_pmu("ltq_etop", "ephy", 0, PMU_EPHY); + } else if (ltq_is_vr9()) { + clkdev_add_static(ltq_vr9_cpu_hz(), ltq_vr9_fpi_hz(), +- ltq_vr9_io_region_clock()); ++ ltq_vr9_fpi_hz()); + clkdev_add_pmu("ltq_pcie", "phy", 1, PMU1_PCIE_PHY); + clkdev_add_pmu("ltq_pcie", "bus", 0, PMU_PCIE_CLK); + clkdev_add_pmu("ltq_pcie", "msi", 1, PMU1_PCIE_MSI); +@@ -259,11 +261,12 @@ void __init ltq_soc_init(void) + PMU_SWITCH | PMU_PPE_DPLUS | PMU_PPE_DPLUM | + PMU_PPE_EMA | PMU_PPE_TC | PMU_PPE_SLL01 | + PMU_PPE_QSB); ++ } else if (ltq_is_ar9()) { ++ clkdev_add_static(ltq_ar9_cpu_hz(), ltq_ar9_fpi_hz(), ++ ltq_ar9_fpi_hz()); ++ clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); + } else { + clkdev_add_static(ltq_danube_cpu_hz(), ltq_danube_fpi_hz(), +- ltq_danube_io_region_clock()); +- clkdev_add_pci(); +- if (ltq_is_ar9()) +- clkdev_add_pmu("ltq_etop", "switch", 0, PMU_SWITCH); ++ ltq_danube_io_region_clock()); + } + } +-- +1.7.9.1 + |