diff options
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch | 97 |
1 files changed, 97 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch b/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch new file mode 100644 index 0000000000..fc4db15ea2 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0108-arm64-dts-qcom-ipq8074-fix-Gen3-PCIe-node.patch @@ -0,0 +1,97 @@ +From 625c90a8266e432ea15e109123ca941062b63f76 Mon Sep 17 00:00:00 2001 +From: Robert Marko <robimarko@gmail.com> +Date: Wed, 16 Nov 2022 22:48:40 +0100 +Subject: [PATCH] arm64: dts: qcom: ipq8074: fix Gen3 PCIe node + +IPQ8074 comes in 2 silicon versions: +* v1 with 2x Gen2 PCIe ports and QMP PHY-s +* v2 with 1x Gen3 and 1x Gen2 PCIe ports and QMP PHY-s + +v2 is the final and production version that is actually supported by the +kernel, however it looks like PCIe related nodes were added for the v1 SoC. + +Finish the PCIe fixup by using the correct compatible, adding missing ATU +register space, declaring max-link-speed, use correct ranges, add missing +clocks and resets. + +Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes") +Signed-off-by: Robert Marko <robimarko@gmail.com> +--- + arch/arm64/boot/dts/qcom/ipq8074.dtsi | 30 +++++++++++++++------------ + 1 file changed, 17 insertions(+), 13 deletions(-) + +--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi ++++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi +@@ -854,16 +854,18 @@ + }; + + pcie0: pci@20000000 { +- compatible = "qcom,pcie-ipq8074"; ++ compatible = "qcom,pcie-ipq8074-gen3"; + reg = <0x20000000 0xf1d>, + <0x20000f20 0xa8>, +- <0x00080000 0x2000>, ++ <0x20001000 0x1000>, ++ <0x00080000 0x4000>, + <0x20100000 0x1000>; +- reg-names = "dbi", "elbi", "parf", "config"; ++ reg-names = "dbi", "elbi", "atu", "parf", "config"; + device_type = "pci"; + linux,pci-domain = <0>; + bus-range = <0x00 0xff>; + num-lanes = <1>; ++ max-link-speed = <3>; + #address-cells = <3>; + #size-cells = <2>; + +@@ -871,9 +873,9 @@ + phy-names = "pciephy"; + + ranges = <0x81000000 0 0x20200000 0x20200000 +- 0 0x100000 /* downstream I/O */ +- 0x82000000 0 0x20300000 0x20300000 +- 0 0xd00000>; /* non-prefetchable memory */ ++ 0 0x10000>, /* downstream I/O */ ++ <0x82000000 0 0x20220000 0x20220000 ++ 0 0xfde0000>; /* non-prefetchable memory */ + + interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "msi"; +@@ -891,28 +893,30 @@ + clocks = <&gcc GCC_SYS_NOC_PCIE0_AXI_CLK>, + <&gcc GCC_PCIE0_AXI_M_CLK>, + <&gcc GCC_PCIE0_AXI_S_CLK>, +- <&gcc GCC_PCIE0_AHB_CLK>, +- <&gcc GCC_PCIE0_AUX_CLK>; +- ++ <&gcc GCC_PCIE0_AXI_S_BRIDGE_CLK>, ++ <&gcc GCC_PCIE0_RCHNG_CLK>; + clock-names = "iface", + "axi_m", + "axi_s", +- "ahb", +- "aux"; ++ "axi_bridge", ++ "rchng"; ++ + resets = <&gcc GCC_PCIE0_PIPE_ARES>, + <&gcc GCC_PCIE0_SLEEP_ARES>, + <&gcc GCC_PCIE0_CORE_STICKY_ARES>, + <&gcc GCC_PCIE0_AXI_MASTER_ARES>, + <&gcc GCC_PCIE0_AXI_SLAVE_ARES>, + <&gcc GCC_PCIE0_AHB_ARES>, +- <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>; ++ <&gcc GCC_PCIE0_AXI_MASTER_STICKY_ARES>, ++ <&gcc GCC_PCIE0_AXI_SLAVE_STICKY_ARES>; + reset-names = "pipe", + "sleep", + "sticky", + "axi_m", + "axi_s", + "ahb", +- "axi_m_sticky"; ++ "axi_m_sticky", ++ "axi_s_sticky"; + status = "disabled"; + }; + }; |