diff options
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch | 79 |
1 files changed, 79 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch b/target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch new file mode 100644 index 0000000000..7fcb190578 --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0023-v6.0-clk-qcom-ipq8074-add-USB-GDSCs.patch @@ -0,0 +1,79 @@ +From ff35d239b7b64f71d7dd9d0ce887647de2cacfcc Mon Sep 17 00:00:00 2001 +From: Robert Marko <robimarko@gmail.com> +Date: Sun, 15 May 2022 23:00:46 +0200 +Subject: [PATCH] clk: qcom: ipq8074: add USB GDSCs + +Add GDSC-s for each of the two USB controllers built-in the IPQ8074. + +Signed-off-by: Robert Marko <robimarko@gmail.com> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220515210048.483898-9-robimarko@gmail.com +--- + drivers/clk/qcom/Kconfig | 1 + + drivers/clk/qcom/gcc-ipq8074.c | 24 ++++++++++++++++++++++++ + 2 files changed, 25 insertions(+) + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -166,6 +166,7 @@ config IPQ_LCC_806X + + config IPQ_GCC_8074 + tristate "IPQ8074 Global Clock Controller" ++ select QCOM_GDSC + help + Support for global clock controller on ipq8074 devices. + Say Y if you want to use peripheral devices such as UART, SPI, +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -22,6 +22,7 @@ + #include "clk-alpha-pll.h" + #include "clk-regmap-divider.h" + #include "clk-regmap-mux.h" ++#include "gdsc.h" + #include "reset.h" + + enum { +@@ -4408,6 +4409,22 @@ static struct clk_branch gcc_pcie0_axi_s + }, + }; + ++static struct gdsc usb0_gdsc = { ++ .gdscr = 0x3e078, ++ .pd = { ++ .name = "usb0_gdsc", ++ }, ++ .pwrsts = PWRSTS_OFF_ON, ++}; ++ ++static struct gdsc usb1_gdsc = { ++ .gdscr = 0x3f078, ++ .pd = { ++ .name = "usb1_gdsc", ++ }, ++ .pwrsts = PWRSTS_OFF_ON, ++}; ++ + static const struct alpha_pll_config ubi32_pll_config = { + .l = 0x4e, + .config_ctl_val = 0x200d4aa8, +@@ -4811,6 +4828,11 @@ static const struct qcom_reset_map gcc_i + [GCC_PCIE1_AXI_MASTER_STICKY_ARES] = { 0x76040, 6 }, + }; + ++static struct gdsc *gcc_ipq8074_gdscs[] = { ++ [USB0_GDSC] = &usb0_gdsc, ++ [USB1_GDSC] = &usb1_gdsc, ++}; ++ + static const struct of_device_id gcc_ipq8074_match_table[] = { + { .compatible = "qcom,gcc-ipq8074" }, + { } +@@ -4833,6 +4855,8 @@ static const struct qcom_cc_desc gcc_ipq + .num_resets = ARRAY_SIZE(gcc_ipq8074_resets), + .clk_hws = gcc_ipq8074_hws, + .num_clk_hws = ARRAY_SIZE(gcc_ipq8074_hws), ++ .gdscs = gcc_ipq8074_gdscs, ++ .num_gdscs = ARRAY_SIZE(gcc_ipq8074_gdscs), + }; + + static int gcc_ipq8074_probe(struct platform_device *pdev) |