diff options
Diffstat (limited to 'target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch')
| -rw-r--r-- | target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch b/target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch new file mode 100644 index 0000000000..71fd33331d --- /dev/null +++ b/target/linux/ipq807x/patches-5.15/0021-v6.0-clk-qcom-ipq8074-add-PPE-crypto-clock.patch @@ -0,0 +1,52 @@ +From f91d0e8bd6c1f812bc2589050c05a90ee886c749 Mon Sep 17 00:00:00 2001 +From: Robert Marko <robimarko@gmail.com> +Date: Sun, 15 May 2022 23:00:42 +0200 +Subject: [PATCH] clk: qcom: ipq8074: add PPE crypto clock + +The built-in PPE engine has a dedicated clock for the EIP-197 crypto +engine. + +So, since the required clock currently missing add support for it. + +Signed-off-by: Robert Marko <robimarko@gmail.com> +Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> +Link: https://lore.kernel.org/r/20220515210048.483898-5-robimarko@gmail.com +--- + drivers/clk/qcom/gcc-ipq8074.c | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +--- a/drivers/clk/qcom/gcc-ipq8074.c ++++ b/drivers/clk/qcom/gcc-ipq8074.c +@@ -3183,6 +3183,24 @@ static struct clk_branch gcc_nss_ptp_ref + }, + }; + ++static struct clk_branch gcc_crypto_ppe_clk = { ++ .halt_reg = 0x68310, ++ .halt_bit = 31, ++ .clkr = { ++ .enable_reg = 0x68310, ++ .enable_mask = BIT(0), ++ .hw.init = &(struct clk_init_data){ ++ .name = "gcc_crypto_ppe_clk", ++ .parent_names = (const char *[]){ ++ "nss_ppe_clk_src" ++ }, ++ .num_parents = 1, ++ .flags = CLK_SET_RATE_PARENT, ++ .ops = &clk_branch2_ops, ++ }, ++ }, ++}; ++ + static struct clk_branch gcc_nssnoc_ce_apb_clk = { + .halt_reg = 0x6830c, + .clkr = { +@@ -4655,6 +4673,7 @@ static struct clk_regmap *gcc_ipq8074_cl + [GCC_PCIE0_RCHNG_CLK_SRC] = &pcie0_rchng_clk_src.clkr, + [GCC_PCIE0_RCHNG_CLK] = &gcc_pcie0_rchng_clk.clkr, + [GCC_PCIE0_AXI_S_BRIDGE_CLK] = &gcc_pcie0_axi_s_bridge_clk.clkr, ++ [GCC_CRYPTO_PPE_CLK] = &gcc_crypto_ppe_clk.clkr, + }; + + static const struct qcom_reset_map gcc_ipq8074_resets[] = { |