diff options
Diffstat (limited to 'target/linux/ipq806x')
3 files changed, 0 insertions, 237 deletions
diff --git a/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch b/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch deleted file mode 100644 index 6098cb8fe0..0000000000 --- a/target/linux/ipq806x/patches-5.4/093-1-v5.8-ipq806x-PCI-qcom-Add-missing-ipq806x-clocks-in-PCIe-driver.patch +++ /dev/null @@ -1,103 +0,0 @@ -From 8b6f0330b5f9a7543356bfa9e76d580f03aa2c1e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Mon, 15 Jun 2020 23:05:57 +0200 -Subject: PCI: qcom: Add missing ipq806x clocks in PCIe driver - -Aux and Ref clk are missing in PCIe qcom driver. Add support for this -optional clks for ipq8064/apq8064 SoC. - -Link: https://lore.kernel.org/r/20200615210608.21469-2-ansuelsmth@gmail.com -Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") -Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - drivers/pci/controller/dwc/pcie-qcom.c | 38 +++++++++++++++++++++++++++++----- - 1 file changed, 33 insertions(+), 5 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -103,6 +103,8 @@ struct qcom_pcie_resources_2_1_0 { - struct clk *iface_clk; - struct clk *core_clk; - struct clk *phy_clk; -+ struct clk *aux_clk; -+ struct clk *ref_clk; - struct reset_control *pci_reset; - struct reset_control *axi_reset; - struct reset_control *ahb_reset; -@@ -253,6 +255,14 @@ static int qcom_pcie_get_resources_2_1_0 - if (IS_ERR(res->phy_clk)) - return PTR_ERR(res->phy_clk); - -+ res->aux_clk = devm_clk_get_optional(dev, "aux"); -+ if (IS_ERR(res->aux_clk)) -+ return PTR_ERR(res->aux_clk); -+ -+ res->ref_clk = devm_clk_get_optional(dev, "ref"); -+ if (IS_ERR(res->ref_clk)) -+ return PTR_ERR(res->ref_clk); -+ - res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); - if (IS_ERR(res->pci_reset)) - return PTR_ERR(res->pci_reset); -@@ -285,6 +295,8 @@ static void qcom_pcie_deinit_2_1_0(struc - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); - clk_disable_unprepare(res->phy_clk); -+ clk_disable_unprepare(res->aux_clk); -+ clk_disable_unprepare(res->ref_clk); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); - } - -@@ -315,16 +327,28 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_assert_ahb; - } - -+ ret = clk_prepare_enable(res->core_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable core clock\n"); -+ goto err_clk_core; -+ } -+ - ret = clk_prepare_enable(res->phy_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable phy clock\n"); - goto err_clk_phy; - } - -- ret = clk_prepare_enable(res->core_clk); -+ ret = clk_prepare_enable(res->aux_clk); - if (ret) { -- dev_err(dev, "cannot prepare/enable core clock\n"); -- goto err_clk_core; -+ dev_err(dev, "cannot prepare/enable aux clock\n"); -+ goto err_clk_aux; -+ } -+ -+ ret = clk_prepare_enable(res->ref_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable ref clock\n"); -+ goto err_clk_ref; - } - - ret = reset_control_deassert(res->ahb_reset); -@@ -400,10 +424,14 @@ static int qcom_pcie_init_2_1_0(struct q - return 0; - - err_deassert_ahb: -- clk_disable_unprepare(res->core_clk); --err_clk_core: -+ clk_disable_unprepare(res->ref_clk); -+err_clk_ref: -+ clk_disable_unprepare(res->aux_clk); -+err_clk_aux: - clk_disable_unprepare(res->phy_clk); - err_clk_phy: -+ clk_disable_unprepare(res->core_clk); -+err_clk_core: - clk_disable_unprepare(res->iface_clk); - err_assert_ahb: - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); diff --git a/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch b/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch deleted file mode 100644 index 9600419710..0000000000 --- a/target/linux/ipq806x/patches-5.4/093-2-v5.8-ipq806x-PCI-qcom-Change-duplicate-PCI-reset-to-phy-reset.patch +++ /dev/null @@ -1,72 +0,0 @@ -From dd58318c019f10bc94db36df66af6c55d4c0cbba Mon Sep 17 00:00:00 2001 -From: Abhishek Sahu <absahu@codeaurora.org> -Date: Mon, 15 Jun 2020 23:05:59 +0200 -Subject: PCI: qcom: Change duplicate PCI reset to phy reset - -The deinit issues reset_control_assert for PCI twice and does not contain -phy reset. - -Link: https://lore.kernel.org/r/20200615210608.21469-4-ansuelsmth@gmail.com -Signed-off-by: Abhishek Sahu <absahu@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - drivers/pci/controller/dwc/pcie-qcom.c | 18 ++++++++---------- - 1 file changed, 8 insertions(+), 10 deletions(-) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -287,14 +287,14 @@ static void qcom_pcie_deinit_2_1_0(struc - { - struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; - -+ clk_disable_unprepare(res->phy_clk); - reset_control_assert(res->pci_reset); - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); -- reset_control_assert(res->pci_reset); -+ reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); -- clk_disable_unprepare(res->phy_clk); - clk_disable_unprepare(res->aux_clk); - clk_disable_unprepare(res->ref_clk); - regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); -@@ -333,12 +333,6 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_clk_core; - } - -- ret = clk_prepare_enable(res->phy_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable phy clock\n"); -- goto err_clk_phy; -- } -- - ret = clk_prepare_enable(res->aux_clk); - if (ret) { - dev_err(dev, "cannot prepare/enable aux clock\n"); -@@ -411,6 +405,12 @@ static int qcom_pcie_init_2_1_0(struct q - return ret; - } - -+ ret = clk_prepare_enable(res->phy_clk); -+ if (ret) { -+ dev_err(dev, "cannot prepare/enable phy clock\n"); -+ goto err_deassert_ahb; -+ } -+ - /* wait for clock acquisition */ - usleep_range(1000, 1500); - -@@ -428,8 +428,6 @@ err_deassert_ahb: - err_clk_ref: - clk_disable_unprepare(res->aux_clk); - err_clk_aux: -- clk_disable_unprepare(res->phy_clk); --err_clk_phy: - clk_disable_unprepare(res->core_clk); - err_clk_core: - clk_disable_unprepare(res->iface_clk); diff --git a/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch b/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch deleted file mode 100644 index fe31e55de3..0000000000 --- a/target/linux/ipq806x/patches-5.4/093-3-v5.8-ipq806x-PCI-qcom-Add-missing-reset-for-ipq806x.patch +++ /dev/null @@ -1,62 +0,0 @@ -From ee367e2cdd2202b5714982739e684543cd2cee0e Mon Sep 17 00:00:00 2001 -From: Ansuel Smith <ansuelsmth@gmail.com> -Date: Mon, 15 Jun 2020 23:06:00 +0200 -Subject: PCI: qcom: Add missing reset for ipq806x - -Add missing ext reset used by ipq8064 SoC in PCIe qcom driver. - -Link: https://lore.kernel.org/r/20200615210608.21469-5-ansuelsmth@gmail.com -Fixes: 82a823833f4e ("PCI: qcom: Add Qualcomm PCIe controller driver") -Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> -Cc: stable@vger.kernel.org # v4.5+ ---- - drivers/pci/controller/dwc/pcie-qcom.c | 12 ++++++++++++ - 1 file changed, 12 insertions(+) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -110,6 +110,7 @@ struct qcom_pcie_resources_2_1_0 { - struct reset_control *ahb_reset; - struct reset_control *por_reset; - struct reset_control *phy_reset; -+ struct reset_control *ext_reset; - struct regulator_bulk_data supplies[QCOM_PCIE_2_1_0_MAX_SUPPLY]; - }; - -@@ -279,6 +280,10 @@ static int qcom_pcie_get_resources_2_1_0 - if (IS_ERR(res->por_reset)) - return PTR_ERR(res->por_reset); - -+ res->ext_reset = devm_reset_control_get_optional_exclusive(dev, "ext"); -+ if (IS_ERR(res->ext_reset)) -+ return PTR_ERR(res->ext_reset); -+ - res->phy_reset = devm_reset_control_get_exclusive(dev, "phy"); - return PTR_ERR_OR_ZERO(res->phy_reset); - } -@@ -292,6 +297,7 @@ static void qcom_pcie_deinit_2_1_0(struc - reset_control_assert(res->axi_reset); - reset_control_assert(res->ahb_reset); - reset_control_assert(res->por_reset); -+ reset_control_assert(res->ext_reset); - reset_control_assert(res->phy_reset); - clk_disable_unprepare(res->iface_clk); - clk_disable_unprepare(res->core_clk); -@@ -351,6 +357,12 @@ static int qcom_pcie_init_2_1_0(struct q - goto err_deassert_ahb; - } - -+ ret = reset_control_deassert(res->ext_reset); -+ if (ret) { -+ dev_err(dev, "cannot deassert ext reset\n"); -+ goto err_deassert_ahb; -+ } -+ - /* enable PCIe clocks and resets */ - val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); - val &= ~BIT(0); |