diff options
Diffstat (limited to 'target/linux/ipq806x/patches/0007-ARM-qcom-Rename-various-msm-prefixed-functions-to-qc.patch')
| -rw-r--r-- | target/linux/ipq806x/patches/0007-ARM-qcom-Rename-various-msm-prefixed-functions-to-qc.patch | 105 |
1 files changed, 105 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches/0007-ARM-qcom-Rename-various-msm-prefixed-functions-to-qc.patch b/target/linux/ipq806x/patches/0007-ARM-qcom-Rename-various-msm-prefixed-functions-to-qc.patch new file mode 100644 index 0000000000..fc064b27a9 --- /dev/null +++ b/target/linux/ipq806x/patches/0007-ARM-qcom-Rename-various-msm-prefixed-functions-to-qc.patch @@ -0,0 +1,105 @@ +From 35eb6f73546d3b9475652a38fa641bd1a05a1ea1 Mon Sep 17 00:00:00 2001 +From: Kumar Gala <galak@codeaurora.org> +Date: Tue, 4 Feb 2014 15:38:45 -0600 +Subject: [PATCH 007/182] ARM: qcom: Rename various msm prefixed functions to + qcom + +As mach-qcom will support a number of different Qualcomm SoC platforms +we replace the msm prefix on function names with qcom to be a bit more +generic. + +Signed-off-by: Kumar Gala <galak@codeaurora.org> +--- + arch/arm/mach-qcom/board.c | 4 ++-- + arch/arm/mach-qcom/platsmp.c | 22 +++++++++++----------- + 2 files changed, 13 insertions(+), 13 deletions(-) + +diff --git a/arch/arm/mach-qcom/board.c b/arch/arm/mach-qcom/board.c +index 4529f6b..830f69c 100644 +--- a/arch/arm/mach-qcom/board.c ++++ b/arch/arm/mach-qcom/board.c +@@ -17,7 +17,7 @@ + #include <asm/mach/arch.h> + #include <asm/mach/map.h> + +-extern struct smp_operations msm_smp_ops; ++extern struct smp_operations qcom_smp_ops; + + static const char * const qcom_dt_match[] __initconst = { + "qcom,msm8660-surf", +@@ -31,7 +31,7 @@ static const char * const apq8074_dt_match[] __initconst = { + }; + + DT_MACHINE_START(QCOM_DT, "Qualcomm (Flattened Device Tree)") +- .smp = smp_ops(msm_smp_ops), ++ .smp = smp_ops(qcom_smp_ops), + .dt_compat = qcom_dt_match, + MACHINE_END + +diff --git a/arch/arm/mach-qcom/platsmp.c b/arch/arm/mach-qcom/platsmp.c +index 67823a7..9c53ea7 100644 +--- a/arch/arm/mach-qcom/platsmp.c ++++ b/arch/arm/mach-qcom/platsmp.c +@@ -30,7 +30,7 @@ extern void secondary_startup(void); + static DEFINE_SPINLOCK(boot_lock); + + #ifdef CONFIG_HOTPLUG_CPU +-static void __ref msm_cpu_die(unsigned int cpu) ++static void __ref qcom_cpu_die(unsigned int cpu) + { + wfi(); + } +@@ -42,7 +42,7 @@ static inline int get_core_count(void) + return ((read_cpuid_id() >> 4) & 3) + 1; + } + +-static void msm_secondary_init(unsigned int cpu) ++static void qcom_secondary_init(unsigned int cpu) + { + /* + * Synchronise with the boot thread. +@@ -70,7 +70,7 @@ static void prepare_cold_cpu(unsigned int cpu) + "address\n"); + } + +-static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) ++static int qcom_boot_secondary(unsigned int cpu, struct task_struct *idle) + { + static int cold_boot_done; + +@@ -108,7 +108,7 @@ static int msm_boot_secondary(unsigned int cpu, struct task_struct *idle) + * does not support the ARM SCU, so just set the possible cpu mask to + * NR_CPUS. + */ +-static void __init msm_smp_init_cpus(void) ++static void __init qcom_smp_init_cpus(void) + { + unsigned int i, ncores = get_core_count(); + +@@ -122,16 +122,16 @@ static void __init msm_smp_init_cpus(void) + set_cpu_possible(i, true); + } + +-static void __init msm_smp_prepare_cpus(unsigned int max_cpus) ++static void __init qcom_smp_prepare_cpus(unsigned int max_cpus) + { + } + +-struct smp_operations msm_smp_ops __initdata = { +- .smp_init_cpus = msm_smp_init_cpus, +- .smp_prepare_cpus = msm_smp_prepare_cpus, +- .smp_secondary_init = msm_secondary_init, +- .smp_boot_secondary = msm_boot_secondary, ++struct smp_operations qcom_smp_ops __initdata = { ++ .smp_init_cpus = qcom_smp_init_cpus, ++ .smp_prepare_cpus = qcom_smp_prepare_cpus, ++ .smp_secondary_init = qcom_secondary_init, ++ .smp_boot_secondary = qcom_boot_secondary, + #ifdef CONFIG_HOTPLUG_CPU +- .cpu_die = msm_cpu_die, ++ .cpu_die = qcom_cpu_die, + #endif + }; +-- +1.7.10.4 + |