diff options
Diffstat (limited to 'target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch')
-rw-r--r-- | target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch | 74 |
1 files changed, 0 insertions, 74 deletions
diff --git a/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch b/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch deleted file mode 100644 index 5440b2f7f8..0000000000 --- a/target/linux/ipq806x/patches-5.4/093-8-v5.8-ipq806x-PCI-qcom-Support-pci-speed-set-for-ipq806x.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 51ed2c2b60265006bde7531d10993cf24def0aee Mon Sep 17 00:00:00 2001 -From: Sham Muthayyan <smuthayy@codeaurora.org> -Date: Mon, 15 Jun 2020 23:06:07 +0200 -Subject: PCI: qcom: Support pci speed set for ipq806x - -Some SoC based on ipq8064/5 needs to be limited to pci GEN1 speed due to -some hardware limitations. Add support for speed setting defined by the -max-link-speed binding. If not defined the max speed is set to GEN2 by -default. - -Link: https://lore.kernel.org/r/20200615210608.21469-12-ansuelsmth@gmail.com -Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org> -Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com> -Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> -Reviewed-by: Rob Herring <robh@kernel.org> -Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> ---- - -Backported with light changes: -* One include is missing in kernel 5.4 - - drivers/pci/controller/dwc/pcie-qcom.c | 13 +++++++++++++ - 1 file changed, 13 insertions(+) - ---- a/drivers/pci/controller/dwc/pcie-qcom.c -+++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -27,6 +27,7 @@ - #include <linux/slab.h> - #include <linux/types.h> - -+#include "../../pci.h" - #include "pcie-designware.h" - - #define PCIE20_PARF_SYS_CTRL 0x00 -@@ -98,6 +99,8 @@ - #define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358 - #define SLV_ADDR_SPACE_SZ 0x10000000 - -+#define PCIE20_LNK_CONTROL2_LINK_STATUS2 0xa0 -+ - #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 - #define QCOM_PCIE_2_1_0_MAX_CLOCKS 5 - struct qcom_pcie_resources_2_1_0 { -@@ -184,6 +187,7 @@ struct qcom_pcie { - struct phy *phy; - struct gpio_desc *reset; - const struct qcom_pcie_ops *ops; -+ int gen; - }; - - #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) -@@ -399,6 +403,11 @@ static int qcom_pcie_init_2_1_0(struct q - /* wait for clock acquisition */ - usleep_range(1000, 1500); - -+ if (pcie->gen == 1) { -+ val = readl(pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); -+ val |= PCI_EXP_LNKSTA_CLS_2_5GB; -+ writel(val, pci->dbi_base + PCIE20_LNK_CONTROL2_LINK_STATUS2); -+ } - - /* Set the Max TLP size to 2K, instead of using default of 4K */ - writel(CFG_REMOTE_RD_REQ_BRIDGE_SIZE_2K, -@@ -1263,6 +1272,10 @@ static int qcom_pcie_probe(struct platfo - goto err_pm_runtime_put; - } - -+ pcie->gen = of_pci_get_max_link_speed(pdev->dev.of_node); -+ if (pcie->gen < 0) -+ pcie->gen = 2; -+ - res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "parf"); - pcie->parf = devm_ioremap_resource(dev, res); - if (IS_ERR(pcie->parf)) { |