diff options
Diffstat (limited to 'target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch | 144 |
1 files changed, 73 insertions, 71 deletions
diff --git a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch b/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch index 4d2da5f768..32fc297fe0 100644 --- a/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch +++ b/target/linux/ipq806x/patches-5.4/093-4-v5.8-ipq806x-PCI-qcom-Use-bulk-clk-api-and-assert-on-error.patch @@ -17,7 +17,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c -@@ -81,12 +81,9 @@ +@@ -99,12 +99,9 @@ #define SLV_ADDR_SPACE_SZ 0x10000000 #define QCOM_PCIE_2_1_0_MAX_SUPPLY 3 @@ -32,7 +32,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> struct reset_control *pci_reset; struct reset_control *axi_reset; struct reset_control *ahb_reset; -@@ -226,25 +223,21 @@ static int qcom_pcie_get_resources_2_1_0 +@@ -244,25 +241,21 @@ static int qcom_pcie_get_resources_2_1_0 if (ret) return ret; @@ -73,7 +73,7 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> res->pci_reset = devm_reset_control_get_exclusive(dev, "pci"); if (IS_ERR(res->pci_reset)) -@@ -274,17 +267,13 @@ static void qcom_pcie_deinit_2_1_0(struc +@@ -292,17 +285,13 @@ static void qcom_pcie_deinit_2_1_0(struc { struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0; @@ -92,111 +92,113 @@ Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com> regulator_bulk_disable(ARRAY_SIZE(res->supplies), res->supplies); } -@@ -302,36 +291,6 @@ static int qcom_pcie_init_2_1_0(struct q +@@ -321,47 +310,45 @@ static int qcom_pcie_init_2_1_0(struct q return ret; } - ret = reset_control_assert(res->ahb_reset); -- if (ret) { ++ ret = reset_control_deassert(res->ahb_reset); + if (ret) { - dev_err(dev, "cannot assert ahb reset\n"); - goto err_assert_ahb; -- } -- ++ dev_err(dev, "cannot deassert ahb reset\n"); ++ goto err_deassert_ahb; + } + - ret = clk_prepare_enable(res->iface_clk); -- if (ret) { ++ ret = reset_control_deassert(res->ext_reset); + if (ret) { - dev_err(dev, "cannot prepare/enable iface clock\n"); - goto err_assert_ahb; -- } -- -- ret = clk_prepare_enable(res->core_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable core clock\n"); -- goto err_clk_core; -- } -- -- ret = clk_prepare_enable(res->aux_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable aux clock\n"); -- goto err_clk_aux; -- } -- -- ret = clk_prepare_enable(res->ref_clk); -- if (ret) { -- dev_err(dev, "cannot prepare/enable ref clock\n"); -- goto err_clk_ref; -- } -- - ret = reset_control_deassert(res->ahb_reset); - if (ret) { - dev_err(dev, "cannot deassert ahb reset\n"); -@@ -341,48 +300,46 @@ static int qcom_pcie_init_2_1_0(struct q - ret = reset_control_deassert(res->ext_reset); - if (ret) { - dev_err(dev, "cannot deassert ext reset\n"); -- goto err_deassert_ahb; ++ dev_err(dev, "cannot deassert ext reset\n"); + goto err_deassert_ext; } -- /* enable PCIe clocks and resets */ -- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); -- val &= ~BIT(0); -- writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); -- -- /* enable external reference clock */ -- val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); -- val |= BIT(16); -- writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); -- - ret = reset_control_deassert(res->phy_reset); +- ret = clk_prepare_enable(res->core_clk); ++ ret = reset_control_deassert(res->phy_reset); if (ret) { - dev_err(dev, "cannot deassert phy reset\n"); -- return ret; +- dev_err(dev, "cannot prepare/enable core clock\n"); +- goto err_clk_core; ++ dev_err(dev, "cannot deassert phy reset\n"); + goto err_deassert_phy; } - ret = reset_control_deassert(res->pci_reset); +- ret = clk_prepare_enable(res->aux_clk); ++ ret = reset_control_deassert(res->pci_reset); if (ret) { - dev_err(dev, "cannot deassert pci reset\n"); -- return ret; +- dev_err(dev, "cannot prepare/enable aux clock\n"); +- goto err_clk_aux; ++ dev_err(dev, "cannot deassert pci reset\n"); + goto err_deassert_pci; } - ret = reset_control_deassert(res->por_reset); +- ret = clk_prepare_enable(res->ref_clk); ++ ret = reset_control_deassert(res->por_reset); if (ret) { - dev_err(dev, "cannot deassert por reset\n"); -- return ret; +- dev_err(dev, "cannot prepare/enable ref clock\n"); +- goto err_clk_ref; ++ dev_err(dev, "cannot deassert por reset\n"); + goto err_deassert_por; } - ret = reset_control_deassert(res->axi_reset); +- ret = reset_control_deassert(res->ahb_reset); ++ ret = reset_control_deassert(res->axi_reset); if (ret) { - dev_err(dev, "cannot deassert axi reset\n"); -- return ret; +- dev_err(dev, "cannot deassert ahb reset\n"); +- goto err_deassert_ahb; ++ dev_err(dev, "cannot deassert axi reset\n"); + goto err_deassert_axi; } -- ret = clk_prepare_enable(res->phy_clk); +- ret = reset_control_deassert(res->ext_reset); - if (ret) { -- dev_err(dev, "cannot prepare/enable phy clock\n"); +- dev_err(dev, "cannot deassert ext reset\n"); - goto err_deassert_ahb; - } + ret = clk_bulk_prepare_enable(ARRAY_SIZE(res->clks), res->clks); + if (ret) + goto err_clks; -+ -+ /* enable PCIe clocks and resets */ -+ val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); -+ val &= ~BIT(0); -+ writel(val, pcie->parf + PCIE20_PARF_PHY_CTRL); -+ -+ /* enable external reference clock */ -+ val = readl(pcie->parf + PCIE20_PARF_PHY_REFCLK); -+ val |= BIT(16); -+ writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + /* enable PCIe clocks and resets */ + val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL); +@@ -393,36 +380,6 @@ static int qcom_pcie_init_2_1_0(struct q + val |= PHY_REFCLK_SSP_EN; + writel(val, pcie->parf + PCIE20_PARF_PHY_REFCLK); + +- ret = reset_control_deassert(res->phy_reset); +- if (ret) { +- dev_err(dev, "cannot deassert phy reset\n"); +- return ret; +- } +- +- ret = reset_control_deassert(res->pci_reset); +- if (ret) { +- dev_err(dev, "cannot deassert pci reset\n"); +- return ret; +- } +- +- ret = reset_control_deassert(res->por_reset); +- if (ret) { +- dev_err(dev, "cannot deassert por reset\n"); +- return ret; +- } +- +- ret = reset_control_deassert(res->axi_reset); +- if (ret) { +- dev_err(dev, "cannot deassert axi reset\n"); +- return ret; +- } +- +- ret = clk_prepare_enable(res->phy_clk); +- if (ret) { +- dev_err(dev, "cannot prepare/enable phy clock\n"); +- goto err_deassert_ahb; +- } +- /* wait for clock acquisition */ usleep_range(1000, 1500); -@@ -396,15 +353,19 @@ static int qcom_pcie_init_2_1_0(struct q + +@@ -435,15 +392,19 @@ static int qcom_pcie_init_2_1_0(struct q return 0; |