diff options
Diffstat (limited to 'target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch | 35 |
1 files changed, 17 insertions, 18 deletions
diff --git a/target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch b/target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch index 197dd057d2..428a796e07 100644 --- a/target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch +++ b/target/linux/ipq806x/patches-4.4/096-06-usb-dwc3-core-improve-reset-sequence.patch @@ -24,11 +24,9 @@ Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> drivers/usb/dwc3/core.c | 48 ++++++++++++++++++------------------------------ 1 file changed, 18 insertions(+), 30 deletions(-) -diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c -index 17fd814..fa20f5a9 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c -@@ -67,23 +67,9 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 mode) +@@ -67,23 +67,9 @@ void dwc3_set_mode(struct dwc3 *dwc, u32 static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; @@ -53,7 +51,7 @@ index 17fd814..fa20f5a9 100644 usb_phy_init(dwc->usb2_phy); usb_phy_init(dwc->usb3_phy); ret = phy_init(dwc->usb2_generic_phy); -@@ -95,26 +81,28 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) +@@ -95,26 +81,28 @@ static int dwc3_core_soft_reset(struct d phy_exit(dwc->usb2_generic_phy); return ret; } @@ -63,6 +61,18 @@ index 17fd814..fa20f5a9 100644 - reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); - reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST; - dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); +- +- /* Clear USB2 PHY reset */ +- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); +- reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; +- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); +- +- mdelay(100); +- +- /* After PHYs are stable we can take Core out of reset state */ +- reg = dwc3_readl(dwc->regs, DWC3_GCTL); +- reg &= ~DWC3_GCTL_CORESOFTRESET; +- dwc3_writel(dwc->regs, DWC3_GCTL, reg); + /* + * We're resetting only the device side because, if we're in host mode, + * XHCI driver will reset the host block. If dwc3 was configured for @@ -70,25 +80,16 @@ index 17fd814..fa20f5a9 100644 + */ + if (dwc->dr_mode == USB_DR_MODE_HOST) + return 0; - -- /* Clear USB2 PHY reset */ -- reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); -- reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; -- dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg); ++ + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + reg |= DWC3_DCTL_CSFTRST; + dwc3_writel(dwc->regs, DWC3_DCTL, reg); - -- mdelay(100); ++ + do { + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (!(reg & DWC3_DCTL_CSFTRST)) + return 0; - -- /* After PHYs are stable we can take Core out of reset state */ -- reg = dwc3_readl(dwc->regs, DWC3_GCTL); -- reg &= ~DWC3_GCTL_CORESOFTRESET; -- dwc3_writel(dwc->regs, DWC3_GCTL, reg); ++ + udelay(1); + } while (--retries); @@ -97,5 +98,3 @@ index 17fd814..fa20f5a9 100644 } /** --- -cgit v0.12 |