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-rw-r--r--target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch25
-rw-r--r--target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch4
-rw-r--r--target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch6
3 files changed, 17 insertions, 18 deletions
diff --git a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
index e494d32881..df96ad5878 100644
--- a/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -19,7 +19,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -27,7 +27,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -46,14 +46,14 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -64,7 +64,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
bias-disable;
};
-+ pcie1_pins: pcie1_pinmux {
++ pcie0_pins: pcie0_pinmux {
+ mux {
+ pins = "gpio3";
+ drive-strength = <2>;
@@ -72,7 +72,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie2_pins: pcie2_pinmux {
++ pcie1_pins: pcie1_pinmux {
+ mux {
+ pins = "gpio48";
+ drive-strength = <2>;
@@ -80,7 +80,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ };
+ };
+
-+ pcie3_pins: pcie3_pinmux {
++ pcie2_pins: pcie2_pinmux {
+ mux {
+ pins = "gpio63";
+ drive-strength = <2>;
@@ -99,21 +99,21 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+ pcie0: pci@1b500000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 3 0>;
-+ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-0 = <&pcie0_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie1: pci@1b700000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 48 0>;
-+ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-0 = <&pcie1_pins>;
+ pinctrl-names = "default";
+ };
+
+ pcie2: pci@1b900000 {
+ status = "ok";
+ reset-gpio = <&qcom_pinmux 63 0>;
-+ pinctrl-0 = <&pcie3_pins>;
++ pinctrl-0 = <&pcie2_pins>;
+ pinctrl-names = "default";
+ };
};
@@ -125,11 +125,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
#include <dt-bindings/clock/qcom,lcc-ipq806x.h>
#include <dt-bindings/soc/qcom,gsbi.h>
+#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
-+#include <include/dt-bindings/interrupt-controller/arm-gic.h>
++#include <dt-bindings/interrupt-controller/arm-gic.h>
/ {
model = "Qualcomm IPQ8064";
-@@ -329,5 +331,128 @@
+@@ -329,5 +331,127 @@
#reset-cells = <1>;
};
@@ -255,6 +255,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+
+ status = "disabled";
+ };
-+
};
};
diff --git a/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
index 846f7384d1..f327050410 100644
--- a/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
+++ b/target/linux/ipq806x/patches-4.1/707-ARM-dts-qcom-add-mdio-nodes-to-ap148-db149.patch
@@ -39,7 +39,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
gsbi@16300000 {
@@ -144,5 +154,33 @@
- pinctrl-0 = <&pcie2_pins>;
+ pinctrl-0 = <&pcie1_pins>;
pinctrl-names = "default";
};
+
@@ -99,7 +99,7 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
gsbi2: gsbi@12480000 {
@@ -173,5 +183,44 @@
- pinctrl-0 = <&pcie3_pins>;
+ pinctrl-0 = <&pcie2_pins>;
pinctrl-names = "default";
};
+
diff --git a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
index 80197139ff..7f290d9384 100644
--- a/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
+++ b/target/linux/ipq806x/patches-4.1/708-ARM-dts-qcom-add-gmac-nodes-to-ipq806x-platforms.patch
@@ -116,10 +116,11 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
};
--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -578,5 +578,91 @@
+@@ -577,5 +577,91 @@
+
status = "disabled";
};
-
++
+ nss_common: syscon@03000000 {
+ compatible = "syscon";
+ reg = <0x03000000 0x0000FFFF>;
@@ -205,6 +206,5 @@ Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+
+ status = "disabled";
+ };
-+
};
};