diff options
Diffstat (limited to 'target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch')
| -rw-r--r-- | target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch | 142 |
1 files changed, 142 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch b/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch new file mode 100644 index 0000000000..292eb66d67 --- /dev/null +++ b/target/linux/ipq806x/patches-4.19/0034-0003-clk-qcom-Add-HFPLL-driver.patch @@ -0,0 +1,142 @@ +From cb546b797a0da4dbb1a0c76a2a357921887b6189 Mon Sep 17 00:00:00 2001 +From: Stephen Boyd <sboyd@codeaurora.org> +Date: Tue, 14 Aug 2018 17:42:22 +0530 +Subject: [PATCH 03/12] clk: qcom: Add HFPLL driver + +On some devices (MSM8974 for example), the HFPLLs are +instantiated within the Krait processor subsystem as separate +register regions. Add a driver for these PLLs so that we can +provide HFPLL clocks for use by the system. + +Cc: <devicetree@vger.kernel.org> +Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> +Signed-off-by: Sricharan R <sricharan@codeaurora.org> +Tested-by: Craig Tatlor <ctatlor97@gmail.com> +Signed-off-by: Stephen Boyd <sboyd@kernel.org> +--- + drivers/clk/qcom/Kconfig | 8 ++++ + drivers/clk/qcom/Makefile | 1 + + drivers/clk/qcom/hfpll.c | 96 +++++++++++++++++++++++++++++++++++++++ + 3 files changed, 105 insertions(+) + create mode 100644 drivers/clk/qcom/hfpll.c + +--- a/drivers/clk/qcom/Kconfig ++++ b/drivers/clk/qcom/Kconfig +@@ -272,3 +272,11 @@ config SPMI_PMIC_CLKDIV + Technologies, Inc. SPMI PMIC. It configures the frequency of + clkdiv outputs of the PMIC. These clocks are typically wired + through alternate functions on GPIO pins. ++ ++config QCOM_HFPLL ++ tristate "High-Frequency PLL (HFPLL) Clock Controller" ++ depends on COMMON_CLK_QCOM ++ help ++ Support for the high-frequency PLLs present on Qualcomm devices. ++ Say Y if you want to support CPU frequency scaling on devices ++ such as MSM8974, APQ8084, etc. +--- a/drivers/clk/qcom/Makefile ++++ b/drivers/clk/qcom/Makefile +@@ -44,3 +44,4 @@ obj-$(CONFIG_SDM_DISPCC_845) += dispcc-s + obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o + obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o + obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o ++obj-$(CONFIG_QCOM_HFPLL) += hfpll.o +--- /dev/null ++++ b/drivers/clk/qcom/hfpll.c +@@ -0,0 +1,96 @@ ++// SPDX-License-Identifier: GPL-2.0 ++// Copyright (c) 2018, The Linux Foundation. All rights reserved. ++ ++#include <linux/kernel.h> ++#include <linux/init.h> ++#include <linux/module.h> ++#include <linux/platform_device.h> ++#include <linux/of.h> ++#include <linux/clk.h> ++#include <linux/clk-provider.h> ++#include <linux/regmap.h> ++ ++#include "clk-regmap.h" ++#include "clk-hfpll.h" ++ ++static const struct hfpll_data hdata = { ++ .mode_reg = 0x00, ++ .l_reg = 0x04, ++ .m_reg = 0x08, ++ .n_reg = 0x0c, ++ .user_reg = 0x10, ++ .config_reg = 0x14, ++ .config_val = 0x430405d, ++ .status_reg = 0x1c, ++ .lock_bit = 16, ++ ++ .user_val = 0x8, ++ .user_vco_mask = 0x100000, ++ .low_vco_max_rate = 1248000000, ++ .min_rate = 537600000UL, ++ .max_rate = 2900000000UL, ++}; ++ ++static const struct of_device_id qcom_hfpll_match_table[] = { ++ { .compatible = "qcom,hfpll" }, ++ { } ++}; ++MODULE_DEVICE_TABLE(of, qcom_hfpll_match_table); ++ ++static const struct regmap_config hfpll_regmap_config = { ++ .reg_bits = 32, ++ .reg_stride = 4, ++ .val_bits = 32, ++ .max_register = 0x30, ++ .fast_io = true, ++}; ++ ++static int qcom_hfpll_probe(struct platform_device *pdev) ++{ ++ struct resource *res; ++ struct device *dev = &pdev->dev; ++ void __iomem *base; ++ struct regmap *regmap; ++ struct clk_hfpll *h; ++ struct clk_init_data init = { ++ .parent_names = (const char *[]){ "xo" }, ++ .num_parents = 1, ++ .ops = &clk_ops_hfpll, ++ }; ++ ++ h = devm_kzalloc(dev, sizeof(*h), GFP_KERNEL); ++ if (!h) ++ return -ENOMEM; ++ ++ res = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ base = devm_ioremap_resource(dev, res); ++ if (IS_ERR(base)) ++ return PTR_ERR(base); ++ ++ regmap = devm_regmap_init_mmio(&pdev->dev, base, &hfpll_regmap_config); ++ if (IS_ERR(regmap)) ++ return PTR_ERR(regmap); ++ ++ if (of_property_read_string_index(dev->of_node, "clock-output-names", ++ 0, &init.name)) ++ return -ENODEV; ++ ++ h->d = &hdata; ++ h->clkr.hw.init = &init; ++ spin_lock_init(&h->lock); ++ ++ return devm_clk_register_regmap(&pdev->dev, &h->clkr); ++} ++ ++static struct platform_driver qcom_hfpll_driver = { ++ .probe = qcom_hfpll_probe, ++ .driver = { ++ .name = "qcom-hfpll", ++ .of_match_table = qcom_hfpll_match_table, ++ }, ++}; ++module_platform_driver(qcom_hfpll_driver); ++ ++MODULE_DESCRIPTION("QCOM HFPLL Clock Driver"); ++MODULE_LICENSE("GPL v2"); ++MODULE_ALIAS("platform:qcom-hfpll"); |