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Diffstat (limited to 'target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch')
-rw-r--r--target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch30
1 files changed, 15 insertions, 15 deletions
diff --git a/target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch b/target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
index 0c2910f3af..57ee082c83 100644
--- a/target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
+++ b/target/linux/ipq806x/patches-4.14/0071-3-PCI-qcom-Fixed-IPQ806x-PCIE-init-changes.patch
@@ -13,7 +13,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+++ b/drivers/pci/dwc/pcie-qcom.c
@@ -52,7 +52,13 @@
#define PCIE_CAP_CPL_TIMEOUT_DISABLE 0x10
-
+
#define PCIE20_PARF_PHY_CTRL 0x40
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET_MASK (0x1f << 16)
+#define PHY_CTRL_PHY_TX0_TERM_OFFSET(x) (x << 16)
@@ -27,7 +27,7 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
#define PCIE20_PARF_MHI_CLOCK_RESET_CTRL 0x174
@@ -83,6 +89,18 @@
#define DBI_RO_WR_EN 1
-
+
#define PERST_DELAY_US 1000
+/* PARF registers */
+#define PCIE20_PARF_PCS_DEEMPH 0x34
@@ -41,21 +41,21 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+
+#define PCIE20_PARF_CONFIG_BITS 0x50
+#define PHY_RX0_EQ(x) (x << 24)
-
+
#define PCIE20_v3_PARF_SLV_ADDR_SPACE_SIZE 0x358
#define SLV_ADDR_SPACE_SZ 0x10000000
-@@ -102,6 +120,7 @@
+@@ -102,6 +120,7 @@ struct qcom_pcie_resources_2_1_0 {
struct regulator *vdda;
struct regulator *vdda_phy;
struct regulator *vdda_refclk;
+ uint8_t phy_tx0_term_offset;
};
-
+
struct qcom_pcie_resources_1_0_0 {
-@@ -179,6 +198,16 @@
-
+@@ -179,6 +198,16 @@ struct qcom_pcie {
+
#define to_qcom_pcie(x) dev_get_drvdata((x)->dev)
-
+
+static inline void
+writel_masked(void __iomem *addr, u32 clear_mask, u32 set_mask)
+{
@@ -69,10 +69,10 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
static void qcom_ep_reset_assert(struct qcom_pcie *pcie)
{
gpiod_set_value_cansleep(pcie->reset, 1);
-@@ -280,6 +309,10 @@
+@@ -280,6 +309,10 @@ static int qcom_pcie_get_resources_2_1_0
if (IS_ERR(res->ext_reset))
return PTR_ERR(res->ext_reset);
-
+
+ if (of_property_read_u8(dev->of_node, "phy-tx0-term-offset",
+ &res->phy_tx0_term_offset))
+ res->phy_tx0_term_offset = 0;
@@ -80,18 +80,18 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
res->phy_reset = devm_reset_control_get_exclusive(dev, "phy");
return PTR_ERR_OR_ZERO(res->phy_reset);
}
-@@ -309,7 +342,6 @@
+@@ -309,7 +342,6 @@ static int qcom_pcie_init_2_1_0(struct q
struct qcom_pcie_resources_2_1_0 *res = &pcie->res.v2_1_0;
struct dw_pcie *pci = pcie->pci;
struct device *dev = pci->dev;
- u32 val;
int ret;
-
+
ret = reset_control_assert(res->ahb_reset);
-@@ -378,15 +410,26 @@
+@@ -378,15 +410,26 @@ static int qcom_pcie_init_2_1_0(struct q
goto err_deassert_ahb;
}
-
+
- /* enable PCIe clocks and resets */
- val = readl(pcie->parf + PCIE20_PARF_PHY_CTRL);
- val &= ~BIT(0);
@@ -121,6 +121,6 @@ Signed-off-by: Sham Muthayyan <smuthayy@codeaurora.org>
+ /* Enable reference clock */
+ writel_masked(pcie->parf + PCIE20_PARF_PHY_REFCLK,
+ REF_USE_PAD, REF_SSP_EN);
-
+
ret = reset_control_deassert(res->phy_reset);
if (ret) {