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path: root/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch
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Diffstat (limited to 'target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch')
-rw-r--r--target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch80
1 files changed, 0 insertions, 80 deletions
diff --git a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch b/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch
deleted file mode 100644
index a99857e314..0000000000
--- a/target/linux/ipq806x/patches-4.1/115-add-pcie-aux-clk-dts.patch
+++ /dev/null
@@ -1,80 +0,0 @@
---- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
-+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
-@@ -392,15 +392,21 @@
-
- clocks = <&gcc PCIE_A_CLK>,
- <&gcc PCIE_H_CLK>,
-- <&gcc PCIE_PHY_CLK>;
-- clock-names = "core", "iface", "phy";
-+ <&gcc PCIE_PHY_CLK>,
-+ <&gcc PCIE_AUX_CLK>,
-+ <&gcc PCIE_ALT_REF_CLK>;
-+ clock-names = "core", "iface", "phy", "aux", "ref";
-+
-+ assigned-clocks = <&gcc PCIE_ALT_REF_CLK>;
-+ assigned-clock-rates = <100000000>;
-
- resets = <&gcc PCIE_ACLK_RESET>,
- <&gcc PCIE_HCLK_RESET>,
- <&gcc PCIE_POR_RESET>,
- <&gcc PCIE_PCI_RESET>,
-- <&gcc PCIE_PHY_RESET>;
-- reset-names = "axi", "ahb", "por", "pci", "phy";
-+ <&gcc PCIE_PHY_RESET>,
-+ <&gcc PCIE_EXT_RESET>;
-+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
-
- pinctrl-0 = <&pcie0_pins>;
- pinctrl-names = "default";
-@@ -438,15 +444,21 @@
-
- clocks = <&gcc PCIE_1_A_CLK>,
- <&gcc PCIE_1_H_CLK>,
-- <&gcc PCIE_1_PHY_CLK>;
-- clock-names = "core", "iface", "phy";
-+ <&gcc PCIE_1_PHY_CLK>,
-+ <&gcc PCIE_1_AUX_CLK>,
-+ <&gcc PCIE_1_ALT_REF_CLK>;
-+ clock-names = "core", "iface", "phy", "aux", "ref";
-+
-+ assigned-clocks = <&gcc PCIE_1_ALT_REF_CLK>;
-+ assigned-clock-rates = <100000000>;
-
- resets = <&gcc PCIE_1_ACLK_RESET>,
- <&gcc PCIE_1_HCLK_RESET>,
- <&gcc PCIE_1_POR_RESET>,
- <&gcc PCIE_1_PCI_RESET>,
-- <&gcc PCIE_1_PHY_RESET>;
-- reset-names = "axi", "ahb", "por", "pci", "phy";
-+ <&gcc PCIE_1_PHY_RESET>,
-+ <&gcc PCIE_1_EXT_RESET>;
-+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
-
- pinctrl-0 = <&pcie1_pins>;
- pinctrl-names = "default";
-@@ -484,15 +496,21 @@
-
- clocks = <&gcc PCIE_2_A_CLK>,
- <&gcc PCIE_2_H_CLK>,
-- <&gcc PCIE_2_PHY_CLK>;
-- clock-names = "core", "iface", "phy";
-+ <&gcc PCIE_2_PHY_CLK>,
-+ <&gcc PCIE_2_AUX_CLK>,
-+ <&gcc PCIE_2_ALT_REF_CLK>;
-+ clock-names = "core", "iface", "phy", "aux", "ref";
-+
-+ assigned-clocks = <&gcc PCIE_2_ALT_REF_CLK>;
-+ assigned-clock-rates = <100000000>;
-
- resets = <&gcc PCIE_2_ACLK_RESET>,
- <&gcc PCIE_2_HCLK_RESET>,
- <&gcc PCIE_2_POR_RESET>,
- <&gcc PCIE_2_PCI_RESET>,
-- <&gcc PCIE_2_PHY_RESET>;
-- reset-names = "axi", "ahb", "por", "pci", "phy";
-+ <&gcc PCIE_2_PHY_RESET>,
-+ <&gcc PCIE_2_EXT_RESET>;
-+ reset-names = "axi", "ahb", "por", "pci", "phy", "ext";
-
- pinctrl-0 = <&pcie2_pins>;
- pinctrl-names = "default";