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Diffstat (limited to 'target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch')
-rw-r--r--target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch268
1 files changed, 268 insertions, 0 deletions
diff --git a/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
new file mode 100644
index 0000000000..2613dff4df
--- /dev/null
+++ b/target/linux/ipq806x/patches-3.18/112-ARM-dts-qcom-add-pcie-nodes-to-ipq806x-platforms.patch
@@ -0,0 +1,268 @@
+From 5b40516b2f5fb9b2a7d6d3e2e924f12ec9d183a8 Mon Sep 17 00:00:00 2001
+From: Mathieu Olivari <mathieu@codeaurora.org>
+Date: Tue, 21 Apr 2015 19:01:42 -0700
+Subject: [PATCH 8/9] ARM: dts: qcom: add pcie nodes to ipq806x platforms
+
+qcom-pcie driver now supports version 0 of the controller. This change
+adds the corresponding entries to the IPQ806x dtsi file and
+corresponding platform (AP148).
+
+Signed-off-by: Mathieu Olivari <mathieu@codeaurora.org>
+---
+ arch/arm/boot/dts/qcom-ipq8064-ap148.dts | 30 ++++++++
+ arch/arm/boot/dts/qcom-ipq8064.dtsi | 124 +++++++++++++++++++++++++++++++
+ 2 files changed, 154 insertions(+)
+
+--- a/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
++++ b/arch/arm/boot/dts/qcom-ipq8064-ap148.dts
+@@ -30,6 +30,22 @@
+ bias-disable;
+ };
+
++ pcie1_pins: pcie1_pinmux {
++ mux {
++ pins = "gpio3";
++ drive-strength = <2>;
++ bias-disable;
++ };
++ };
++
++ pcie2_pins: pcie2_pinmux {
++ mux {
++ pins = "gpio48";
++ drive-strength = <2>;
++ bias-disable;
++ };
++ };
++
+ spi_pins: spi_pins {
+ mux {
+ pins = "gpio18", "gpio19", "gpio21";
+@@ -136,5 +152,19 @@
+ usb30@1 {
+ status = "ok";
+ };
++
++ pcie0: pci@1b500000 {
++ status = "ok";
++ reset-gpio = <&qcom_pinmux 3 0>;
++ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-names = "default";
++ };
++
++ pcie1: pci@1b700000 {
++ status = "ok";
++ reset-gpio = <&qcom_pinmux 48 0>;
++ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-names = "default";
++ };
+ };
+ };
+--- a/arch/arm/boot/dts/qcom-ipq8064-db149.dts
++++ b/arch/arm/boot/dts/qcom-ipq8064-db149.dts
+@@ -37,6 +37,30 @@
+ bias-disable;
+ };
+
++ pcie1_pins: pcie1_pinmux {
++ mux {
++ pins = "gpio3";
++ drive-strength = <2>;
++ bias-disable;
++ };
++ };
++
++ pcie2_pins: pcie2_pinmux {
++ mux {
++ pins = "gpio48";
++ drive-strength = <2>;
++ bias-disable;
++ };
++ };
++
++ pcie3_pins: pcie3_pinmux {
++ mux {
++ pins = "gpio63";
++ drive-strength = <2>;
++ bias-disable;
++ };
++ };
++
+ spi_pins: spi_pins {
+ mux {
+ pins = "gpio18", "gpio19", "gpio21";
+@@ -153,6 +177,27 @@
+ status = "ok";
+ };
+
++ pcie0: pci@1b500000 {
++ status = "ok";
++ reset-gpio = <&qcom_pinmux 3 0>;
++ pinctrl-0 = <&pcie1_pins>;
++ pinctrl-names = "default";
++ };
++
++ pcie1: pci@1b700000 {
++ status = "ok";
++ reset-gpio = <&qcom_pinmux 48 0>;
++ pinctrl-0 = <&pcie2_pins>;
++ pinctrl-names = "default";
++ };
++
++ pcie2: pci@1b900000 {
++ status = "ok";
++ reset-gpio = <&qcom_pinmux 63 0>;
++ pinctrl-0 = <&pcie3_pins>;
++ pinctrl-names = "default";
++ };
++
+ mdio0: mdio {
+ compatible = "virtual,mdio-gpio";
+ #address-cells = <1>;
+--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
++++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
+@@ -3,6 +3,7 @@
+ #include "skeleton.dtsi"
+ #include <dt-bindings/clock/qcom,gcc-ipq806x.h>
+ #include <dt-bindings/soc/qcom,gsbi.h>
++#include <dt-bindings/reset/qcom,gcc-ipq806x.h>
+
+ / {
+ model = "Qualcomm IPQ8064";
+@@ -306,6 +307,129 @@
+ #reset-cells = <1>;
+ };
+
++ pcie0: pci@1b500000 {
++ compatible = "qcom,pcie-v0";
++ reg = <0x1b500000 0x1000
++ 0x1b502000 0x80
++ 0x1b600000 0x100
++ 0x0ff00000 0x100000>;
++ reg-names = "dbi", "elbi", "parf", "config";
++ device_type = "pci";
++ linux,pci-domain = <0>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ ranges = <0x81000000 0 0 0x0fe00000 0 0x00100000 /* downstream I/O */
++ 0x82000000 0 0x00000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
++
++ interrupts = <GIC_SPI 35 IRQ_TYPE_NONE>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 36 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++ <0 0 0 2 &intc 0 37 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++ <0 0 0 3 &intc 0 38 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++ <0 0 0 4 &intc 0 39 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++
++ clocks = <&gcc PCIE_A_CLK>,
++ <&gcc PCIE_H_CLK>,
++ <&gcc PCIE_PHY_CLK>;
++ clock-names = "core", "iface", "phy";
++
++ resets = <&gcc PCIE_ACLK_RESET>,
++ <&gcc PCIE_HCLK_RESET>,
++ <&gcc PCIE_POR_RESET>,
++ <&gcc PCIE_PCI_RESET>,
++ <&gcc PCIE_PHY_RESET>;
++ reset-names = "axi", "ahb", "por", "pci", "phy";
++
++ status = "disabled";
++ };
++
++ pcie1: pci@1b700000 {
++ compatible = "qcom,pcie-v0";
++ reg = <0x1b700000 0x1000
++ 0x1b702000 0x80
++ 0x1b800000 0x100
++ 0x31f00000 0x100000>;
++ reg-names = "dbi", "elbi", "parf", "config";
++ device_type = "pci";
++ linux,pci-domain = <1>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ ranges = <0x81000000 0 0 0x31e00000 0 0x00100000 /* downstream I/O */
++ 0x82000000 0 0x00000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
++
++ interrupts = <GIC_SPI 57 IRQ_TYPE_NONE>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 58 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++ <0 0 0 2 &intc 0 59 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++ <0 0 0 3 &intc 0 60 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++ <0 0 0 4 &intc 0 61 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++
++ clocks = <&gcc PCIE_1_A_CLK>,
++ <&gcc PCIE_1_H_CLK>,
++ <&gcc PCIE_1_PHY_CLK>;
++ clock-names = "core", "iface", "phy";
++
++ resets = <&gcc PCIE_1_ACLK_RESET>,
++ <&gcc PCIE_1_HCLK_RESET>,
++ <&gcc PCIE_1_POR_RESET>,
++ <&gcc PCIE_1_PCI_RESET>,
++ <&gcc PCIE_1_PHY_RESET>;
++ reset-names = "axi", "ahb", "por", "pci", "phy";
++
++ status = "disabled";
++ };
++
++ pcie2: pci@1b900000 {
++ compatible = "qcom,pcie-v0";
++ reg = <0x1b900000 0x1000
++ 0x1b902000 0x80
++ 0x1ba00000 0x100
++ 0x35f00000 0x100000>;
++ reg-names = "dbi", "elbi", "parf", "config";
++ device_type = "pci";
++ linux,pci-domain = <2>;
++ bus-range = <0x00 0xff>;
++ num-lanes = <1>;
++ #address-cells = <3>;
++ #size-cells = <2>;
++
++ ranges = <0x81000000 0 0 0x35e00000 0 0x00100000 /* downstream I/O */
++ 0x82000000 0 0x00000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
++
++ interrupts = <GIC_SPI 71 IRQ_TYPE_NONE>;
++ interrupt-names = "msi";
++ #interrupt-cells = <1>;
++ interrupt-map-mask = <0 0 0 0x7>;
++ interrupt-map = <0 0 0 1 &intc 0 72 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
++ <0 0 0 2 &intc 0 73 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
++ <0 0 0 3 &intc 0 74 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
++ <0 0 0 4 &intc 0 75 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
++
++ clocks = <&gcc PCIE_2_A_CLK>,
++ <&gcc PCIE_2_H_CLK>,
++ <&gcc PCIE_2_PHY_CLK>;
++ clock-names = "core", "iface", "phy";
++
++ resets = <&gcc PCIE_2_ACLK_RESET>,
++ <&gcc PCIE_2_HCLK_RESET>,
++ <&gcc PCIE_2_POR_RESET>,
++ <&gcc PCIE_2_PCI_RESET>,
++ <&gcc PCIE_2_PHY_RESET>;
++ reset-names = "axi", "ahb", "por", "pci", "phy";
++
++ status = "disabled";
++ };
++
+ hs_phy_1: phy@100f8800 {
+ compatible = "qcom,dwc3-hs-usb-phy";
+ reg = <0x100f8800 0x30>;
+@@ -389,6 +513,5 @@
+ dr_mode = "host";
+ };
+ };
+-
+ };
+ };
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