diff options
Diffstat (limited to 'target/linux/imx6/patches-4.4')
20 files changed, 0 insertions, 1596 deletions
diff --git a/target/linux/imx6/patches-4.4/0005-ARM-dts-imx-add-gw553x-support.patch b/target/linux/imx6/patches-4.4/0005-ARM-dts-imx-add-gw553x-support.patch deleted file mode 100644 index 63225b3b4d..0000000000 --- a/target/linux/imx6/patches-4.4/0005-ARM-dts-imx-add-gw553x-support.patch +++ /dev/null @@ -1,18 +0,0 @@ ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -293,6 +293,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-gw54xx.dtb \ - imx6dl-gw551x.dtb \ - imx6dl-gw552x.dtb \ -+ imx6dl-gw553x.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-nit6xlite.dtb \ - imx6dl-nitrogen6x.dtb \ -@@ -322,6 +323,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6q-gw54xx.dtb \ - imx6q-gw551x.dtb \ - imx6q-gw552x.dtb \ -+ imx6q-gw553x.dtb \ - imx6q-hummingboard.dtb \ - imx6q-nitrogen6x.dtb \ - imx6q-nitrogen6_max.dtb \ diff --git a/target/linux/imx6/patches-4.4/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch b/target/linux/imx6/patches-4.4/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch deleted file mode 100644 index db166ed6fa..0000000000 --- a/target/linux/imx6/patches-4.4/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 57b82d9e79d77442bae3d2c13b98ceccb39fe5e2 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 10:49:31 -0800 -Subject: [PATCH 1/3] ARM: dts: imx: ventana: set GW54xx PMIC swbst regulator - as always-on - -The GW54xx PMIC swbst regulator is used for LVDS power, CANbus xceiver -and HDMI DDC and is enabled by the bootloader. Set the regulator to -always-on so that Linux doesn't turn it off thinking its not needed. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -260,6 +260,8 @@ - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; -+ regulator-boot-on; -+ regulator-always-on; - }; - - snvs_reg: vsnvs { diff --git a/target/linux/imx6/patches-4.4/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch b/target/linux/imx6/patches-4.4/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch deleted file mode 100644 index 2101fdfcf3..0000000000 --- a/target/linux/imx6/patches-4.4/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 473d0353979db3673a7aa365265ba9b00decd414 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 10:52:53 -0800 -Subject: [PATCH 2/3] ARM: dts: imx: ventana: fix GW53xx/GW54xx lvds channel - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +- - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -247,7 +247,7 @@ - &ldb { - status = "okay"; - -- lvds-channel@1 { -+ lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -338,7 +338,7 @@ - &ldb { - status = "okay"; - -- lvds-channel@1 { -+ lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; diff --git a/target/linux/imx6/patches-4.4/037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch b/target/linux/imx6/patches-4.4/037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch deleted file mode 100644 index c861e3848c..0000000000 --- a/target/linux/imx6/patches-4.4/037-ARM-dts-imx-ventana-Allow-HDMI-and-LVDS-to-work-simultaneously.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d86b202436b6f3111c4c37b8701daa0764d2ca55 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 11:10:00 -0800 -Subject: [PATCH 3/3] ARM: dts: imx: ventana: Allow HDMI and LVDS to work - simultaneously - -Currently it is not possible to have HDMI and LVDS working simultaneously, -because both ports try to use PLL5. - -Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be -driven from independent sources. - -With this change the LDB pixel clock goes to 68.57 MHz, which is still -within the valid range for the displays supported by the Ventana boards. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 7 +++++++ - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 7 +++++++ - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 7 +++++++ - 3 files changed, 21 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -151,6 +151,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -152,6 +152,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -142,6 +142,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; diff --git a/target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch b/target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch deleted file mode 100644 index 759f32e6f6..0000000000 --- a/target/linux/imx6/patches-4.4/040-ARM-dts-imx-ventana-add-pwm-nodes.patch +++ /dev/null @@ -1,264 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -174,6 +174,24 @@ - status = "okay"; - }; - -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ -+&pwm4 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */ -+ status = "disabled"; -+}; -+ - &uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; -@@ -294,6 +312,24 @@ - >; - }; - -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm4: pwm4grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -282,6 +282,18 @@ - status = "okay"; - }; - -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ - &pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -@@ -436,6 +448,18 @@ - >; - }; - -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -287,6 +287,18 @@ - }; - }; - -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ - &pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -@@ -442,6 +454,18 @@ - >; - }; - -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -378,6 +378,24 @@ - }; - }; - -+&pwm1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */ -+ status = "disabled"; -+}; -+ -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ - &pwm4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm4>; -@@ -537,6 +555,24 @@ - >; - }; - -+ pinctrl_pwm1: pwm1grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_pwm4: pwm4grp { - fsl,pins = < - MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 ---- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi -@@ -198,6 +198,18 @@ - status = "okay"; - }; - -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ - &ssi1 { - status = "okay"; - }; -@@ -290,6 +302,18 @@ - >; - }; - -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ---- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi -@@ -164,6 +164,18 @@ - status = "okay"; - }; - -+&pwm2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */ -+ status = "disabled"; -+}; -+ -+&pwm3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */ -+ status = "disabled"; -+}; -+ - &uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; -@@ -242,6 +254,18 @@ - >; - }; - -+ pinctrl_pwm2: pwm2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_pwm3: pwm3grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ >; -+ }; -+ - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 diff --git a/target/linux/imx6/patches-4.4/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch b/target/linux/imx6/patches-4.4/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch deleted file mode 100644 index da3571559e..0000000000 --- a/target/linux/imx6/patches-4.4/041-ARM-dts-imx-ventana-add-spi-support-for-gw52xx.patch +++ /dev/null @@ -1,33 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -158,6 +158,14 @@ - <&clks IMX6QDL_CLK_PLL3_USB_OTG>; - }; - -+&ecspi3 { -+ fsl,spi-num-chipselects = <1>; -+ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_ecspi3>; -+ status = "okay"; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; -@@ -357,6 +365,15 @@ - >; - }; - -+ pinctrl_ecspi3: escpi3grp { -+ fsl,pins = < -+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1 -+ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1 -+ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1 -+ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1 -+ >; -+ }; -+ - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 diff --git a/target/linux/imx6/patches-4.4/042-ARM-dts-imx-ventana-fix-PWM-pinmux-for-Ventana-boards.patch b/target/linux/imx6/patches-4.4/042-ARM-dts-imx-ventana-fix-PWM-pinmux-for-Ventana-boards.patch deleted file mode 100644 index d3cbfab5cd..0000000000 --- a/target/linux/imx6/patches-4.4/042-ARM-dts-imx-ventana-fix-PWM-pinmux-for-Ventana-boards.patch +++ /dev/null @@ -1,61 +0,0 @@ -commit 3371600cc36d2a6c19cc985660a21c6830f7e7cd -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu Jan 7 09:03:03 2016 -0800 - - ARM: dts: imx: ventana: fix PWM pinmux for Ventana boards - - Fix some invalid pwm pinmux configurations. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -320,13 +320,13 @@ - - pinctrl_pwm3: pwm3grp { - fsl,pins = < -- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - - pinctrl_pwm4: pwm4grp { - fsl,pins = < -- MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1 -+ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1 - >; - }; - ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -473,7 +473,7 @@ - - pinctrl_pwm3: pwm3grp { - fsl,pins = < -- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -462,7 +462,7 @@ - - pinctrl_pwm3: pwm3grp { - fsl,pins = < -- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - ---- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi -@@ -262,7 +262,7 @@ - - pinctrl_pwm3: pwm3grp { - fsl,pins = < -- MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1 -+ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1 - >; - }; - diff --git a/target/linux/imx6/patches-4.4/100-bootargs.patch b/target/linux/imx6/patches-4.4/100-bootargs.patch deleted file mode 100644 index 0954391203..0000000000 --- a/target/linux/imx6/patches-4.4/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts -@@ -19,4 +19,8 @@ - memory { - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx6/patches-4.4/110-serial-imx-repair-and-complete-handshaking.patch b/target/linux/imx6/patches-4.4/110-serial-imx-repair-and-complete-handshaking.patch deleted file mode 100644 index 82715b0cda..0000000000 --- a/target/linux/imx6/patches-4.4/110-serial-imx-repair-and-complete-handshaking.patch +++ /dev/null @@ -1,74 +0,0 @@ -From 90ebc4838666d148eac5bbac6f4044e5b25cd2d6 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> -Date: Sun, 18 Oct 2015 21:34:46 +0200 -Subject: [PATCH] serial: imx: repair and complete handshaking -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -The .get_mctrl callback should not report the status of RTS or LOOP, so -drop this. Instead implement reporting the state of CAR (aka DCD) and -RI. - -For .set_mctrl implement setting the DTR line. - -Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> -Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> -Signed-off-by: Petr Štetiar <ynezz@true.cz> ---- - drivers/tty/serial/imx.c | 23 +++++++++++++++++------ - 1 file changed, 17 insertions(+), 6 deletions(-) - ---- a/drivers/tty/serial/imx.c -+++ b/drivers/tty/serial/imx.c -@@ -148,8 +148,11 @@ - #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */ - #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */ - #define USR2_IDLE (1<<12) /* Idle condition */ -+#define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */ -+#define USR2_RIIN (1<<9) /* Ring Indicator Input */ - #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */ - #define USR2_WAKE (1<<7) /* Wake */ -+#define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */ - #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */ - #define USR2_TXDC (1<<3) /* Transmitter complete */ - #define USR2_BRCD (1<<2) /* Break condition */ -@@ -804,16 +807,19 @@ static unsigned int imx_tx_empty(struct - static unsigned int imx_get_mctrl(struct uart_port *port) - { - struct imx_port *sport = (struct imx_port *)port; -- unsigned int tmp = TIOCM_DSR | TIOCM_CAR; -+ unsigned int tmp = TIOCM_DSR; -+ unsigned usr1 = readl(sport->port.membase + USR1); - -- if (readl(sport->port.membase + USR1) & USR1_RTSS) -+ if (usr1 & USR1_RTSS) - tmp |= TIOCM_CTS; - -- if (readl(sport->port.membase + UCR2) & UCR2_CTS) -- tmp |= TIOCM_RTS; -- -- if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP) -- tmp |= TIOCM_LOOP; -+ /* in DCE mode DCDIN is always 0 */ -+ if (!(usr1 & USR2_DCDIN)) -+ tmp |= TIOCM_CAR; -+ -+ /* in DCE mode RIIN is always 0 */ -+ if (readl(sport->port.membase + USR2) & USR2_RIIN) -+ tmp |= TIOCM_RI; - - return tmp; - } -@@ -831,6 +837,11 @@ static void imx_set_mctrl(struct uart_po - writel(temp, sport->port.membase + UCR2); - } - -+ temp = readl(sport->port.membase + UCR3) & ~UCR3_DSR; -+ if (!(mctrl & TIOCM_DTR)) -+ temp |= UCR3_DSR; -+ writel(temp, sport->port.membase + UCR3); -+ - temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP; - if (mctrl & TIOCM_LOOP) - temp |= UTS_LOOP; diff --git a/target/linux/imx6/patches-4.4/111-serial-imx-fix-polarity-of-RI.patch b/target/linux/imx6/patches-4.4/111-serial-imx-fix-polarity-of-RI.patch deleted file mode 100644 index 0288298163..0000000000 --- a/target/linux/imx6/patches-4.4/111-serial-imx-fix-polarity-of-RI.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 9a061cea4477f26a1dfcc0a08dc20575016e91df Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> -Date: Thu, 24 Mar 2016 14:24:20 +0100 -Subject: [PATCH 1/3] serial: imx: fix polarity of RI -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -When in DTE mode, the bit USR2_RIIN is active low. So invert the logic -accordingly. - -Fixes: 90ebc4838666 ("serial: imx: repair and complete handshaking") -Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> -Signed-off-by: Petr Štetiar <ynezz@true.cz> ---- - drivers/tty/serial/imx.c | 6 +++--- - 1 file changed, 3 insertions(+), 3 deletions(-) - ---- a/drivers/tty/serial/imx.c -+++ b/drivers/tty/serial/imx.c -@@ -817,9 +817,9 @@ static unsigned int imx_get_mctrl(struct - if (!(usr1 & USR2_DCDIN)) - tmp |= TIOCM_CAR; - -- /* in DCE mode RIIN is always 0 */ -- if (readl(sport->port.membase + USR2) & USR2_RIIN) -- tmp |= TIOCM_RI; -+ if (sport->dte_mode) -+ if (!(readl(sport->port.membase + USR2) & USR2_RIIN)) -+ tmp |= TIOCM_RI; - - return tmp; - } diff --git a/target/linux/imx6/patches-4.4/112-serial-imx-let-irq-handler-return-IRQ_NONE-if-no-eve.patch b/target/linux/imx6/patches-4.4/112-serial-imx-let-irq-handler-return-IRQ_NONE-if-no-eve.patch deleted file mode 100644 index a4f2951590..0000000000 --- a/target/linux/imx6/patches-4.4/112-serial-imx-let-irq-handler-return-IRQ_NONE-if-no-eve.patch +++ /dev/null @@ -1,67 +0,0 @@ -From de4356da2cd1a1857513047997d81143cb95a4e1 Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> -Date: Thu, 24 Mar 2016 14:24:21 +0100 -Subject: [PATCH 2/3] serial: imx: let irq handler return IRQ_NONE if no event - was handled -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -This gives the irq core a chance to disable the serial interrupt in case -an event isn't cleared in the handler. - -Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> -Signed-off-by: Petr Štetiar <ynezz@true.cz> ---- - drivers/tty/serial/imx.c | 17 +++++++++++++---- - 1 file changed, 13 insertions(+), 4 deletions(-) - ---- a/drivers/tty/serial/imx.c -+++ b/drivers/tty/serial/imx.c -@@ -753,6 +753,7 @@ static irqreturn_t imx_int(int irq, void - struct imx_port *sport = dev_id; - unsigned int sts; - unsigned int sts2; -+ irqreturn_t ret = IRQ_NONE; - - sts = readl(sport->port.membase + USR1); - sts2 = readl(sport->port.membase + USR2); -@@ -762,26 +763,34 @@ static irqreturn_t imx_int(int irq, void - imx_dma_rxint(sport); - else - imx_rxint(irq, dev_id); -+ ret = IRQ_HANDLED; - } - - if ((sts & USR1_TRDY && - readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN) || - (sts2 & USR2_TXDC && -- readl(sport->port.membase + UCR4) & UCR4_TCEN)) -+ readl(sport->port.membase + UCR4) & UCR4_TCEN)) { - imx_txint(irq, dev_id); -+ ret = IRQ_HANDLED; -+ } - -- if (sts & USR1_RTSD) -+ if (sts & USR1_RTSD) { - imx_rtsint(irq, dev_id); -+ ret = IRQ_HANDLED; -+ } - -- if (sts & USR1_AWAKE) -+ if (sts & USR1_AWAKE) { - writel(USR1_AWAKE, sport->port.membase + USR1); -+ ret = IRQ_HANDLED; -+ } - - if (sts2 & USR2_ORE) { - sport->port.icount.overrun++; - writel(USR2_ORE, sport->port.membase + USR2); -+ ret = IRQ_HANDLED; - } - -- return IRQ_HANDLED; -+ return ret; - } - - /* diff --git a/target/linux/imx6/patches-4.4/113-serial-imx-make-sure-unhandled-irqs-are-disabled.patch b/target/linux/imx6/patches-4.4/113-serial-imx-make-sure-unhandled-irqs-are-disabled.patch deleted file mode 100644 index 1c7de3fa6e..0000000000 --- a/target/linux/imx6/patches-4.4/113-serial-imx-make-sure-unhandled-irqs-are-disabled.patch +++ /dev/null @@ -1,56 +0,0 @@ -From a58c6360b9eb3a2374b0b069ba9ce7baec0f26df Mon Sep 17 00:00:00 2001 -From: =?UTF-8?q?Uwe=20Kleine-K=C3=B6nig?= <u.kleine-koenig@pengutronix.de> -Date: Thu, 24 Mar 2016 14:24:22 +0100 -Subject: [PATCH 3/3] serial: imx: make sure unhandled irqs are disabled -MIME-Version: 1.0 -Content-Type: text/plain; charset=UTF-8 -Content-Transfer-Encoding: 8bit - -Make sure that events that are not handled in the irq function don't -trigger an interrupt. - -When the serial port is operated in DTE mode, the events for DCD and RI -events are enabled after a system reset by default. - -Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> -Signed-off-by: Petr Štetiar <ynezz@true.cz> ---- - drivers/tty/serial/imx.c | 23 ++++++++++++++++++++++- - 1 file changed, 22 insertions(+), 1 deletion(-) - ---- a/drivers/tty/serial/imx.c -+++ b/drivers/tty/serial/imx.c -@@ -1184,11 +1184,32 @@ static int imx_startup(struct uart_port - temp |= (UCR2_RXEN | UCR2_TXEN); - if (!sport->have_rtscts) - temp |= UCR2_IRTS; -+ /* -+ * make sure the edge sensitive RTS-irq is disabled, -+ * we're using RTSD instead. -+ */ -+ if (!is_imx1_uart(sport)) -+ temp &= ~UCR2_RTSEN; - writel(temp, sport->port.membase + UCR2); - - if (!is_imx1_uart(sport)) { - temp = readl(sport->port.membase + UCR3); -- temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP; -+ -+ /* -+ * The effect of RI and DCD differs depending on the UFCR_DCEDTE -+ * bit. In DCE mode they control the outputs, in DTE mode they -+ * enable the respective irqs. At least the DCD irq cannot be -+ * cleared on i.MX25 at least, so it's not usable and must be -+ * disabled. I don't have test hardware to check if RI has the -+ * same problem but I consider this likely so it's disabled for -+ * now, too. -+ */ -+ temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | -+ UCR3_RI | UCR3_DCD; -+ -+ if (sport->dte_mode) -+ temp &= ~(UCR3_RI | UCR3_DCD); -+ - writel(temp, sport->port.membase + UCR3); - } - diff --git a/target/linux/imx6/patches-4.4/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-4.4/202-net-igb-add-i210-i211-support-for-phy-read-write.patch deleted file mode 100644 index 2649f05a1f..0000000000 --- a/target/linux/imx6/patches-4.4/202-net-igb-add-i210-i211-support-for-phy-read-write.patch +++ /dev/null @@ -1,129 +0,0 @@ -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu May 15 00:12:26 2014 -0700 - - net: igb: add i210/i211 support for phy read/write - - The i210/i211 uses the MDICNFG register for the phy address instead of the - MDIC register. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -133,7 +133,7 @@ out: - s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -146,11 +146,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_READ)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ default: -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -175,6 +189,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - *data = (u16) mdic; - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - -@@ -189,7 +215,7 @@ out: - s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -202,12 +228,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = (((u32)data) | -- (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_WRITE)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ default: -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -231,6 +272,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - } - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - diff --git a/target/linux/imx6/patches-4.4/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-4.4/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch deleted file mode 100644 index 45a4a8b3d0..0000000000 --- a/target/linux/imx6/patches-4.4/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch +++ /dev/null @@ -1,260 +0,0 @@ -From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 15 May 2014 00:29:18 -0700 -Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr - -Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. -The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers -to this function. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +- - drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++--------- - drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++- - 3 files changed, 58 insertions(+), 26 deletions(-) - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -2154,7 +2154,7 @@ static s32 igb_read_phy_reg_82580(struct - if (ret_val) - goto out; - -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - -@@ -2179,7 +2179,7 @@ static s32 igb_write_phy_reg_82580(struc - if (ret_val) - goto out; - -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -130,9 +130,8 @@ out: - * Reads the MDI control regsiter in the PHY at offset and stores the - * information read to data. - **/ --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -151,14 +150,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = ((offset << E1000_MDIC_REG_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - default: - mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - } -@@ -212,9 +211,8 @@ out: - * - * Writes data to MDI control register in the PHY at offset. - **/ --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -233,7 +231,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -@@ -242,7 +240,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - default: - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_WRITE)); - break; - } -@@ -462,7 +460,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -471,8 +469,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - } - } - -- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -501,7 +499,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -510,8 +508,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h - } - } - -- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -2551,8 +2549,9 @@ out: - } - - /** -- * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * igb_write_reg_gs40g - Write GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to write to - * @offset: lower half is register offset to write to - * upper half is page to use. - * @data: data to write at register offset -@@ -2560,7 +2559,7 @@ out: - * Acquires semaphore, if necessary, then writes the data to PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2570,10 +2569,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000 - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2581,8 +2580,24 @@ release: - } - - /** -- * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to write to -+ * upper half is page to use. -+ * @data: data to write at register offset -+ * -+ * Acquires semaphore, if necessary, then writes the data to PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+{ -+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** -+ * igb_read_reg_gs40g - Read GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to read from - * @offset: lower half is register offset to read to - * upper half is page to use. - * @data: data to read at register offset -@@ -2590,7 +2605,7 @@ release: - * Acquires semaphore, if necessary, then reads the data in the PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2600,10 +2615,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_ - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2611,6 +2626,21 @@ release: - } - - /** -+ * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to read to -+ * upper half is page to use. -+ * @data: data to read at register offset -+ * -+ * Acquires semaphore, if necessary, then reads the data in the PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+{ -+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** - * igb_set_master_slave_mode - Setup PHY for Master/slave mode - * @hw: pointer to the HW structure - * ---- a/drivers/net/ethernet/intel/igb/e1000_phy.h -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h -@@ -62,8 +62,8 @@ void igb_power_up_phy_copper(struct e100 - void igb_power_down_phy_copper(struct e1000_hw *hw); - s32 igb_phy_init_script_igp3(struct e1000_hw *hw); - s32 igb_initialize_M88E1512_phy(struct e1000_hw *hw); --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); - s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); -@@ -73,6 +73,8 @@ s32 igb_phy_force_speed_duplex_82580(st - s32 igb_get_cable_length_82580(struct e1000_hw *hw); - s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_check_polarity_m88(struct e1000_hw *hw); - - /* IGP01E1000 Specific Registers */ diff --git a/target/linux/imx6/patches-4.4/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-4.4/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch deleted file mode 100644 index bbd972177b..0000000000 --- a/target/linux/imx6/patches-4.4/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 15 May 2014 12:36:23 -0700 -Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy - -If an i210 is configured for 1000BASE-BX link_mode and has an external phy -specified, then register an mii bus using the external phy address as -a mask. - -An i210 hooked to an external standard phy will be configured with a link_mo -of SGMII in which case phy ops will be configured and used internall in the -igb driver for link status. However, in certain cases one might be using a -backplane SerDes connection to something that talks on the mdio bus but is -not a standard phy, such as a switch. In this case by registering an mdio -bus a phy driver can manage the device. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++ - drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++ - drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++- - 3 files changed, 185 insertions(+), 5 deletions(-) - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -613,13 +613,25 @@ static s32 igb_get_invariants_82575(stru - switch (link_mode) { - case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: - hw->phy.media_type = e1000_media_type_internal_serdes; -+ if (igb_sgmii_uses_mdio_82575(hw)) { -+ u32 mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= E1000_MDICNFG_PHY_MASK; -+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; -+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", -+ hw->phy.addr); -+ } else { -+ hw_dbg("1000BASE_KX"); -+ } - break; - case E1000_CTRL_EXT_LINK_MODE_SGMII: - /* Get phy control interface type set (MDIO vs. I2C)*/ - if (igb_sgmii_uses_mdio_82575(hw)) { - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; -+ hw_dbg("SGMII with external MDIO PHY"); - break; -+ } else { -+ hw_dbg("SGMII with external I2C PHY"); - } - /* fall through for I2C based SGMII */ - case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: -@@ -636,8 +648,11 @@ static s32 igb_get_invariants_82575(stru - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; - } -+ hw_dbg("SERDES with external SFP"); - - break; -+ } else { -+ hw_dbg("SERDES"); - } - - /* do not change link mode for 100BaseFX */ ---- a/drivers/net/ethernet/intel/igb/e1000_hw.h -+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h -@@ -27,6 +27,7 @@ - #include <linux/delay.h> - #include <linux/io.h> - #include <linux/netdevice.h> -+#include <linux/phy.h> - - #include "e1000_regs.h" - #include "e1000_defines.h" -@@ -543,6 +544,12 @@ struct e1000_hw { - struct e1000_mbx_info mbx; - struct e1000_host_mng_dhcp_cookie mng_cookie; - -+#ifdef CONFIG_PHYLIB -+ /* Phylib and MDIO interface */ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ phy_interface_t phy_interface; -+#endif - union { - struct e1000_dev_spec_82575 _82575; - } dev_spec; ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -41,6 +41,7 @@ - #include <linux/if_vlan.h> - #include <linux/pci.h> - #include <linux/pci-aspm.h> -+#include <linux/phy.h> - #include <linux/delay.h> - #include <linux/interrupt.h> - #include <linux/ip.h> -@@ -2217,6 +2218,126 @@ static s32 igb_init_i2c(struct igb_adapt - return status; - } - -+ -+#ifdef CONFIG_PHYLIB -+/* -+ * MMIO/PHYdev support -+ */ -+ -+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct e1000_hw *hw = bus->priv; -+ u16 out; -+ int err; -+ -+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); -+ if (err) -+ return err; -+ return out; -+} -+ -+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 val) -+{ -+ struct e1000_hw *hw = bus->priv; -+ -+ return igb_write_reg_gs40g(hw, mii_id, regnum, val); -+} -+ -+static int igb_enet_mdio_reset(struct mii_bus *bus) -+{ -+ udelay(300); -+ return 0; -+} -+ -+static void igb_enet_mii_link(struct net_device *netdev) -+{ -+} -+ -+/* Probe the mdio bus for phys and connect them */ -+static int igb_enet_mii_probe(struct net_device *netdev) -+{ -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ struct phy_device *phy_dev = NULL; -+ int phy_id; -+ -+ /* check for attached phy */ -+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { -+ if (hw->mii_bus->phy_map[phy_id]) { -+ phy_dev = hw->mii_bus->phy_map[phy_id]; -+ break; -+ } -+ } -+ if (!phy_dev) { -+ netdev_err(netdev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII; -+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), -+ igb_enet_mii_link, hw->phy_interface); -+ if (IS_ERR(phy_dev)) { -+ netdev_err(netdev, "could not attach to PHY\n"); -+ return PTR_ERR(phy_dev); -+ } -+ -+ hw->phy_dev = phy_dev; -+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", -+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); -+ -+ return 0; -+} -+ -+/* Create and register mdio bus */ -+static int igb_enet_mii_init(struct pci_dev *pdev) -+{ -+ struct mii_bus *mii_bus; -+ struct net_device *netdev = pci_get_drvdata(pdev); -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ int err; -+ -+ mii_bus = mdiobus_alloc(); -+ if (mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ mii_bus->name = "igb_enet_mii_bus"; -+ mii_bus->read = igb_enet_mdio_read; -+ mii_bus->write = igb_enet_mdio_write; -+ mii_bus->reset = igb_enet_mdio_reset; -+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", -+ pci_name(pdev), hw->device_id + 1); -+ mii_bus->priv = hw; -+ mii_bus->parent = &pdev->dev; -+ mii_bus->phy_mask = ~(1 << hw->phy.addr); -+ -+ err = mdiobus_register(mii_bus); -+ if (err) { -+ printk(KERN_ERR "failed to register mii_bus: %d\n", err); -+ goto err_out_free_mdiobus; -+ } -+ hw->mii_bus = mii_bus; -+ -+ return 0; -+ -+err_out_free_mdiobus: -+ mdiobus_free(mii_bus); -+err_out: -+ return err; -+} -+ -+static void igb_enet_mii_remove(struct e1000_hw *hw) -+{ -+ if (hw->mii_bus) { -+ mdiobus_unregister(hw->mii_bus); -+ mdiobus_free(hw->mii_bus); -+ } -+} -+#endif /* CONFIG_PHYLIB */ -+ - /** - * igb_probe - Device Initialization Routine - * @pdev: PCI device information struct -@@ -2641,6 +2762,13 @@ static int igb_probe(struct pci_dev *pde - } - } - pm_runtime_put_noidle(&pdev->dev); -+ -+#ifdef CONFIG_PHYLIB -+ /* create and register the mdio bus if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_init(pdev); -+#endif -+ - return 0; - - err_register: -@@ -2788,6 +2916,10 @@ static void igb_remove(struct pci_dev *p - struct e1000_hw *hw = &adapter->hw; - - pm_runtime_get_noresume(&pdev->dev); -+#ifdef CONFIG_PHYLIB -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_remove(hw); -+#endif - #ifdef CONFIG_IGB_HWMON - igb_sysfs_exit(adapter); - #endif -@@ -3111,6 +3243,12 @@ static int __igb_open(struct net_device - if (!resuming) - pm_runtime_put(&pdev->dev); - -+#ifdef CONFIG_PHYLIB -+ /* Probe and connect to PHY if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_probe(netdev); -+#endif -+ - /* start the watchdog. */ - hw->mac.get_link_status = 1; - schedule_work(&adapter->watchdog_task); -@@ -7102,21 +7240,41 @@ void igb_alloc_rx_buffers(struct igb_rin - static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) - { - struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; - struct mii_ioctl_data *data = if_mii(ifr); - -- if (adapter->hw.phy.media_type != e1000_media_type_copper) -+ if (adapter->hw.phy.media_type != e1000_media_type_copper && -+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) - return -EOPNOTSUPP; - - switch (cmd) { - case SIOCGMIIPHY: -- data->phy_id = adapter->hw.phy.addr; -+ data->phy_id = hw->phy.addr; - break; - case SIOCGMIIREG: -- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, -- &data->val_out)) -- return -EIO; -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id, -+ data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } else { -+ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } - break; - case SIOCSMIIREG: -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_write_reg_gs40g(hw, data->phy_id, -+ data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } else { -+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } -+ break; - default: - return -EOPNOTSUPP; - } diff --git a/target/linux/imx6/patches-4.4/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-4.4/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch deleted file mode 100644 index fa9a8c3a0a..0000000000 --- a/target/linux/imx6/patches-4.4/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -336,6 +336,14 @@ endif # RTL8366_SMI - - source "drivers/net/phy/b53/Kconfig" - -+config GATEWORKS_GW16083 -+ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" -+ ---help--- -+ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a -+ Gateworks Ventana baseboard and provides a 7-port GbE managed -+ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP -+ ports" -+ - endif # PHYLIB - - config MICREL_KS8995MA ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -46,6 +46,7 @@ obj-$(CONFIG_DP83848_PHY) += dp83848.o - obj-$(CONFIG_DP83867_PHY) += dp83867.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_MICREL_PHY) += micrel.o -+obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-4.4/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-4.4/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch deleted file mode 100644 index a9214d598f..0000000000 --- a/target/linux/imx6/patches-4.4/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -158,6 +158,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -233,6 +233,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -226,6 +226,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -317,6 +317,11 @@ - }; - }; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { diff --git a/target/linux/imx6/patches-4.4/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch b/target/linux/imx6/patches-4.4/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch deleted file mode 100644 index 700513ab0a..0000000000 --- a/target/linux/imx6/patches-4.4/207-i2c-imx-add-retries-for-NAK-s-on-ventana-boards.patch +++ /dev/null @@ -1,22 +0,0 @@ ---- a/drivers/i2c/busses/i2c-imx.c -+++ b/drivers/i2c/busses/i2c-imx.c -@@ -468,6 +468,8 @@ static int i2c_imx_acked(struct imx_i2c_ - { - if (imx_i2c_read_reg(i2c_imx, IMX_I2C_I2SR) & I2SR_RXAK) { - dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); -+ if (i2c_imx->adapter.retries) -+ return -EAGAIN; - return -ENXIO; /* No ACK */ - } - -@@ -1073,6 +1075,10 @@ static int i2c_imx_probe(struct platform - i2c_imx->adapter.nr = pdev->id; - i2c_imx->adapter.dev.of_node = pdev->dev.of_node; - i2c_imx->base = base; -+ if (of_machine_is_compatible("gw,ventana") && phy_addr == 0x021a0000) { -+ dev_info(&pdev->dev, "Adding retries for Ventana GSC\n"); -+ i2c_imx->adapter.retries = 3; -+ } - - /* Get I2C clock */ - i2c_imx->clk = devm_clk_get(&pdev->dev, NULL); diff --git a/target/linux/imx6/patches-4.4/208-sky2-allow-mac-to-come-from-dt.patch b/target/linux/imx6/patches-4.4/208-sky2-allow-mac-to-come-from-dt.patch deleted file mode 100644 index 9a94212235..0000000000 --- a/target/linux/imx6/patches-4.4/208-sky2-allow-mac-to-come-from-dt.patch +++ /dev/null @@ -1,28 +0,0 @@ ---- a/drivers/net/ethernet/marvell/sky2.c -+++ b/drivers/net/ethernet/marvell/sky2.c -@@ -4812,7 +4812,24 @@ static struct net_device *sky2_init_netd - * 1) from device tree data - * 2) from internal registers set by bootloader - */ -- iap = of_get_mac_address(hw->pdev->dev.of_node); -+ -+ iap = NULL; -+ if (IS_ENABLED(CONFIG_OF)) { -+ struct device_node *np; -+ np = of_find_node_by_path("/aliases"); -+ if (np) { -+ const char *path = of_get_property(np, "sky2", NULL); -+ if (path) -+ np = of_find_node_by_path(path); -+ if (np) -+ path = of_get_mac_address(np); -+ if (path) -+ iap = (unsigned char *) path; -+ } -+ } -+ -+ if (!iap) -+ iap = of_get_mac_address(hw->pdev->dev.of_node); - if (iap) - memcpy(dev->dev_addr, iap, ETH_ALEN); - else diff --git a/target/linux/imx6/patches-4.4/209-ARM-imx-ventana-add-sky2-alias.patch b/target/linux/imx6/patches-4.4/209-ARM-imx-ventana-add-sky2-alias.patch deleted file mode 100644 index 490e015eb0..0000000000 --- a/target/linux/imx6/patches-4.4/209-ARM-imx-ventana-add-sky2-alias.patch +++ /dev/null @@ -1,20 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -15,6 +15,7 @@ - /* these are used by bootloader for disabling nodes */ - aliases { - ethernet1 = ð1; -+ sky2 = ð1; - led0 = &led0; - led1 = &led1; - led2 = &led2; ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -15,6 +15,7 @@ - /* these are used by bootloader for disabling nodes */ - aliases { - ethernet1 = ð1; -+ sky2 = ð1; - led0 = &led0; - led1 = &led1; - led2 = &led2; |