diff options
Diffstat (limited to 'target/linux/imx6/patches-4.1')
10 files changed, 0 insertions, 1406 deletions
diff --git a/target/linux/imx6/patches-4.1/020-ARM-dts-Gateworks-GW5510-support-i.MX6.patch b/target/linux/imx6/patches-4.1/020-ARM-dts-Gateworks-GW5510-support-i.MX6.patch deleted file mode 100644 index fce8eba660..0000000000 --- a/target/linux/imx6/patches-4.1/020-ARM-dts-Gateworks-GW5510-support-i.MX6.patch +++ /dev/null @@ -1,486 +0,0 @@ -From e9d6d6b62f306ba83e1441af5daf2809a6167474 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 7 May 2015 08:38:00 -0700 -Subject: [PATCH] ARM: dts: Gateworks GW5510 support (i.MX6) - -Add support for the Gateworks GW5510 board featuring: - * i.MX6 SoC - * up to 512MB DDR3 - * up to 2GB NAND flash - * 1x miniPCIe socket (with USB) - * HDMI out (micro-HDMI) - * HDMI in (micro-HDMI) (currently supported by only vendor kernel) - * TTL level I/O (supported by GW16111 breakout board): - * I2C - * 2x UART - * CAN - * 2x DIO (GPIO/PWM) - * USB OTG - -For more details see: - http://www.gateworks.com/product/item/ventana-gw5510-single-board-computer - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> -Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com> -Signed-off-by: Shawn Guo <shawn.guo@linaro.org> ---- - arch/arm/boot/dts/Makefile | 2 + - arch/arm/boot/dts/imx6dl-gw551x.dts | 55 ++++++ - arch/arm/boot/dts/imx6q-gw551x.dts | 55 ++++++ - arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 314 ++++++++++++++++++++++++++++++++++ - 4 files changed, 426 insertions(+) - create mode 100644 arch/arm/boot/dts/imx6dl-gw551x.dts - create mode 100644 arch/arm/boot/dts/imx6q-gw551x.dts - create mode 100644 arch/arm/boot/dts/imx6qdl-gw551x.dtsi - ---- a/arch/arm/boot/dts/Makefile -+++ b/arch/arm/boot/dts/Makefile -@@ -262,6 +262,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6dl-gw52xx.dtb \ - imx6dl-gw53xx.dtb \ - imx6dl-gw54xx.dtb \ -+ imx6dl-gw551x.dtb \ - imx6dl-gw552x.dtb \ - imx6dl-hummingboard.dtb \ - imx6dl-nitrogen6x.dtb \ -@@ -288,6 +289,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \ - imx6q-gw53xx.dtb \ - imx6q-gw5400-a.dtb \ - imx6q-gw54xx.dtb \ -+ imx6q-gw551x.dtb \ - imx6q-gw552x.dtb \ - imx6q-hummingboard.dtb \ - imx6q-nitrogen6x.dtb \ ---- /dev/null -+++ b/arch/arm/boot/dts/imx6dl-gw551x.dts -@@ -0,0 +1,55 @@ -+/* -+ * Copyright 2014 Gateworks Corporation -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this file; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "imx6dl.dtsi" -+#include "imx6qdl-gw551x.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 DualLite/Solo GW551X"; -+ compatible = "gw,imx6dl-gw551x", "gw,ventana", "fsl,imx6dl"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6q-gw551x.dts -@@ -0,0 +1,55 @@ -+/* -+ * Copyright 2014 Gateworks Corporation -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this file; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+/dts-v1/; -+#include "imx6q.dtsi" -+#include "imx6qdl-gw551x.dtsi" -+ -+/ { -+ model = "Gateworks Ventana i.MX6 Dual/Quad GW551X"; -+ compatible = "gw,imx6q-gw551x", "gw,ventana", "fsl,imx6q"; -+}; ---- /dev/null -+++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi -@@ -0,0 +1,314 @@ -+/* -+ * Copyright 2014 Gateworks Corporation -+ * -+ * This file is dual-licensed: you can use it either under the terms -+ * of the GPL or the X11 license, at your option. Note that this dual -+ * licensing only applies to this file, and not this project as a -+ * whole. -+ * -+ * a) This file is free software; you can redistribute it and/or -+ * modify it under the terms of the GNU General Public License as -+ * published by the Free Software Foundation; either version 2 of -+ * the License, or (at your option) any later version. -+ * -+ * This file is distributed in the hope that it will be useful, -+ * but WITHOUT ANY WARRANTY; without even the implied warranty of -+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -+ * GNU General Public License for more details. -+ * -+ * You should have received a copy of the GNU General Public -+ * License along with this file; if not, write to the Free -+ * Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, -+ * MA 02110-1301 USA -+ * -+ * Or, alternatively, -+ * -+ * b) Permission is hereby granted, free of charge, to any person -+ * obtaining a copy of this software and associated documentation -+ * files (the "Software"), to deal in the Software without -+ * restriction, including without limitation the rights to use, -+ * copy, modify, merge, publish, distribute, sublicense, and/or -+ * sell copies of the Software, and to permit persons to whom the -+ * Software is furnished to do so, subject to the following -+ * conditions: -+ * -+ * The above copyright notice and this permission notice shall be -+ * included in all copies or substantial portions of the Software. -+ * -+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, -+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES -+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND -+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT -+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, -+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING -+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR -+ * OTHER DEALINGS IN THE SOFTWARE. -+ */ -+ -+#include <dt-bindings/gpio/gpio.h> -+ -+/ { -+ /* these are used by bootloader for disabling nodes */ -+ aliases { -+ led0 = &led0; -+ nand = &gpmi; -+ ssi0 = &ssi1; -+ usb0 = &usbh1; -+ usb1 = &usbotg; -+ }; -+ -+ chosen { -+ bootargs = "console=ttymxc1,115200"; -+ }; -+ -+ leds { -+ compatible = "gpio-leds"; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpio_leds>; -+ -+ led0: user1 { -+ label = "user1"; -+ gpios = <&gpio4 7 GPIO_ACTIVE_LOW>; -+ default-state = "on"; -+ linux,default-trigger = "heartbeat"; -+ }; -+ }; -+ -+ memory { -+ reg = <0x10000000 0x20000000>; -+ }; -+ -+ regulators { -+ compatible = "simple-bus"; -+ #address-cells = <1>; -+ #size-cells = <0>; -+ -+ reg_5p0v: regulator@0 { -+ compatible = "regulator-fixed"; -+ reg = <0>; -+ regulator-name = "5P0V"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usb_h1_vbus: regulator@1 { -+ compatible = "regulator-fixed"; -+ reg = <1>; -+ regulator-name = "usb_h1_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ -+ reg_usb_otg_vbus: regulator@2 { -+ compatible = "regulator-fixed"; -+ reg = <2>; -+ regulator-name = "usb_otg_vbus"; -+ regulator-min-microvolt = <5000000>; -+ regulator-max-microvolt = <5000000>; -+ }; -+ }; -+}; -+ -+&can1 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_flexcan1>; -+ status = "okay"; -+}; -+ -+&gpmi { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_gpmi_nand>; -+ status = "okay"; -+}; -+ -+&hdmi { -+ ddc-i2c-bus = <&i2c3>; -+ status = "okay"; -+}; -+ -+&i2c1 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c1>; -+ status = "okay"; -+ -+ eeprom1: eeprom@50 { -+ compatible = "atmel,24c02"; -+ reg = <0x50>; -+ pagesize = <16>; -+ }; -+ -+ eeprom2: eeprom@51 { -+ compatible = "atmel,24c02"; -+ reg = <0x51>; -+ pagesize = <16>; -+ }; -+ -+ eeprom3: eeprom@52 { -+ compatible = "atmel,24c02"; -+ reg = <0x52>; -+ pagesize = <16>; -+ }; -+ -+ eeprom4: eeprom@53 { -+ compatible = "atmel,24c02"; -+ reg = <0x53>; -+ pagesize = <16>; -+ }; -+ -+ gpio: pca9555@23 { -+ compatible = "nxp,pca9555"; -+ reg = <0x23>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+ rtc: ds1672@68 { -+ compatible = "dallas,ds1672"; -+ reg = <0x68>; -+ }; -+}; -+ -+&i2c2 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c2>; -+ status = "okay"; -+}; -+ -+&i2c3 { -+ clock-frequency = <100000>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_i2c3>; -+ status = "okay"; -+ -+ gpio_exp: pca9555@24 { -+ compatible = "nxp,pca9555"; -+ reg = <0x24>; -+ gpio-controller; -+ #gpio-cells = <2>; -+ }; -+ -+}; -+ -+&pcie { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_pcie>; -+ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>; -+ status = "okay"; -+}; -+ -+&ssi1 { -+ status = "okay"; -+}; -+ -+&uart2 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart2>; -+ status = "okay"; -+}; -+ -+&uart3 { -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_uart3>; -+ status = "okay"; -+}; -+ -+&usbotg { -+ vbus-supply = <®_usb_otg_vbus>; -+ pinctrl-names = "default"; -+ pinctrl-0 = <&pinctrl_usbotg>; -+ disable-over-current; -+ status = "okay"; -+}; -+ -+&usbh1 { -+ vbus-supply = <®_usb_h1_vbus>; -+ status = "okay"; -+}; -+ -+&iomuxc { -+ imx6qdl-gw51xx { -+ pinctrl_flexcan1: flexcan1grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 -+ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1 -+ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x4001b0b0 /* CAN_STBY */ -+ >; -+ }; -+ -+ pinctrl_gpio_leds: gpioledsgrp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0 -+ >; -+ }; -+ -+ pinctrl_gpmi_nand: gpminandgrp { -+ fsl,pins = < -+ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 -+ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 -+ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 -+ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 -+ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 -+ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 -+ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 -+ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 -+ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 -+ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 -+ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 -+ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 -+ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 -+ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 -+ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 -+ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 -+ >; -+ }; -+ -+ pinctrl_i2c1: i2c1grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1 -+ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c2: i2c2grp { -+ fsl,pins = < -+ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 -+ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_i2c3: i2c3grp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1 -+ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 -+ >; -+ }; -+ -+ pinctrl_pcie: pciegrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ -+ >; -+ }; -+ -+ pinctrl_uart2: uart2grp { -+ fsl,pins = < -+ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_uart3: uart3grp { -+ fsl,pins = < -+ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 -+ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 -+ >; -+ }; -+ -+ pinctrl_usbotg: usbotggrp { -+ fsl,pins = < -+ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 -+ >; -+ }; -+ }; -+}; diff --git a/target/linux/imx6/patches-4.1/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch b/target/linux/imx6/patches-4.1/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch deleted file mode 100644 index db166ed6fa..0000000000 --- a/target/linux/imx6/patches-4.1/035-ARM-dts-imx-ventana-set-GW54xx-PMIC-swbst-regulator-.patch +++ /dev/null @@ -1,26 +0,0 @@ -From 57b82d9e79d77442bae3d2c13b98ceccb39fe5e2 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 10:49:31 -0800 -Subject: [PATCH 1/3] ARM: dts: imx: ventana: set GW54xx PMIC swbst regulator - as always-on - -The GW54xx PMIC swbst regulator is used for LVDS power, CANbus xceiver -and HDMI DDC and is enabled by the bootloader. Set the regulator to -always-on so that Linux doesn't turn it off thinking its not needed. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 ++ - 1 file changed, 2 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -260,6 +260,8 @@ - swbst_reg: swbst { - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5150000>; -+ regulator-boot-on; -+ regulator-always-on; - }; - - snvs_reg: vsnvs { diff --git a/target/linux/imx6/patches-4.1/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch b/target/linux/imx6/patches-4.1/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch deleted file mode 100644 index 2101fdfcf3..0000000000 --- a/target/linux/imx6/patches-4.1/036-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch +++ /dev/null @@ -1,33 +0,0 @@ -From 473d0353979db3673a7aa365265ba9b00decd414 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 10:52:53 -0800 -Subject: [PATCH 2/3] ARM: dts: imx: ventana: fix GW53xx/GW54xx lvds channel - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 2 +- - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 2 +- - 2 files changed, 2 insertions(+), 2 deletions(-) - ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -247,7 +247,7 @@ - &ldb { - status = "okay"; - -- lvds-channel@1 { -+ lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -338,7 +338,7 @@ - &ldb { - status = "okay"; - -- lvds-channel@1 { -+ lvds-channel@0 { - fsl,data-mapping = "spwg"; - fsl,data-width = <18>; - status = "okay"; diff --git a/target/linux/imx6/patches-4.1/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch b/target/linux/imx6/patches-4.1/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch deleted file mode 100644 index c861e3848c..0000000000 --- a/target/linux/imx6/patches-4.1/037-ARM-dts-imx-ventana-fix-GW53xx-GW54xx-lvds-channel.patch +++ /dev/null @@ -1,70 +0,0 @@ -From d86b202436b6f3111c4c37b8701daa0764d2ca55 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 5 Nov 2015 11:10:00 -0800 -Subject: [PATCH 3/3] ARM: dts: imx: ventana: Allow HDMI and LVDS to work - simultaneously - -Currently it is not possible to have HDMI and LVDS working simultaneously, -because both ports try to use PLL5. - -Move the LVDS clock parent to PLL3_USB_OTG, so that HDMI and LVDS can be -driven from independent sources. - -With this change the LDB pixel clock goes to 68.57 MHz, which is still -within the valid range for the displays supported by the Ventana boards. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 7 +++++++ - arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 7 +++++++ - arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 7 +++++++ - 3 files changed, 21 insertions(+) - ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -151,6 +151,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -152,6 +152,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -142,6 +142,13 @@ - status = "okay"; - }; - -+&clks { -+ assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, -+ <&clks IMX6QDL_CLK_LDB_DI1_SEL>; -+ assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>, -+ <&clks IMX6QDL_CLK_PLL3_USB_OTG>; -+}; -+ - &fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; diff --git a/target/linux/imx6/patches-4.1/100-bootargs.patch b/target/linux/imx6/patches-4.1/100-bootargs.patch deleted file mode 100644 index 0954391203..0000000000 --- a/target/linux/imx6/patches-4.1/100-bootargs.patch +++ /dev/null @@ -1,11 +0,0 @@ ---- a/arch/arm/boot/dts/imx6dl-wandboard.dts -+++ b/arch/arm/boot/dts/imx6dl-wandboard.dts -@@ -19,4 +19,8 @@ - memory { - reg = <0x10000000 0x40000000>; - }; -+ -+ chosen { -+ bootargs = "console=ttymxc0,115200"; -+ }; - }; diff --git a/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch b/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch deleted file mode 100644 index fb4b722569..0000000000 --- a/target/linux/imx6/patches-4.1/202-net-igb-add-i210-i211-support-for-phy-read-write.patch +++ /dev/null @@ -1,129 +0,0 @@ -Author: Tim Harvey <tharvey@gateworks.com> -Date: Thu May 15 00:12:26 2014 -0700 - - net: igb: add i210/i211 support for phy read/write - - The i210/i211 uses the MDICNFG register for the phy address instead of the - MDIC register. - - Signed-off-by: Tim Harvey <tharvey@gateworks.com> - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -135,7 +135,7 @@ out: - s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -148,11 +148,25 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_READ)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ default: -+ mdic = ((offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_READ)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -177,6 +191,18 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - *data = (u16) mdic; - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - -@@ -191,7 +217,7 @@ out: - s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) - { - struct e1000_phy_info *phy = &hw->phy; -- u32 i, mdic = 0; -+ u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - - if (offset > MAX_PHY_REG_ADDRESS) { -@@ -204,12 +230,27 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - * Control register. The MAC will take care of interfacing with the - * PHY to retrieve the desired data. - */ -- mdic = (((u32)data) | -- (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -- (E1000_MDIC_OP_WRITE)); -+ switch (hw->mac.type) { -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ default: -+ mdic = (((u32)data) | -+ (offset << E1000_MDIC_REG_SHIFT) | -+ (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (E1000_MDIC_OP_WRITE)); -+ break; -+ } - - wr32(E1000_MDIC, mdic); -+ wrfl(); - - /* Poll the ready bit to see if the MDI read completed - * Increasing the time out as testing showed failures with -@@ -233,6 +274,18 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - } - - out: -+ switch (hw->mac.type) { -+ /* restore MDICNFG to have phy's addr */ -+ case e1000_i210: -+ case e1000_i211: -+ mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -+ mdicnfg |= (hw->phy.addr << E1000_MDICNFG_PHY_SHIFT); -+ wr32(E1000_MDICNFG, mdicnfg); -+ break; -+ default: -+ break; -+ } - return ret_val; - } - diff --git a/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch b/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch deleted file mode 100644 index 7869b1cf53..0000000000 --- a/target/linux/imx6/patches-4.1/203-net-igb-add-phy-read-write-functions-that-accept-phy.patch +++ /dev/null @@ -1,260 +0,0 @@ -From 16df7dc5901c1cb2a40f6adbd0d9423768ed8210 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 15 May 2014 00:29:18 -0700 -Subject: [PATCH] net: igb: add phy read/write functions that accept phy addr - -Add igb_write_reg_gs40g/igb_read_reg_gs40g that can be passed a phy address. -The existing igb_write_phy_reg_gs40g/igb_read_phy_reg_gs40g become wrappers -to this function. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/net/ethernet/intel/igb/e1000_82575.c | 4 +- - drivers/net/ethernet/intel/igb/e1000_phy.c | 74 +++++++++++++++++++--------- - drivers/net/ethernet/intel/igb/e1000_phy.h | 6 ++- - 3 files changed, 58 insertions(+), 26 deletions(-) - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -2129,7 +2129,7 @@ static s32 igb_read_phy_reg_82580(struct - if (ret_val) - goto out; - -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - -@@ -2154,7 +2154,7 @@ static s32 igb_write_phy_reg_82580(struc - if (ret_val) - goto out; - -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, offset, data); - - hw->phy.ops.release(hw); - ---- a/drivers/net/ethernet/intel/igb/e1000_phy.c -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.c -@@ -132,9 +132,8 @@ out: - * Reads the MDI control regsiter in the PHY at offset and stores the - * information read to data. - **/ --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -153,14 +152,14 @@ s32 igb_read_phy_reg_mdic(struct e1000_h - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = ((offset << E1000_MDIC_REG_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - default: - mdic = ((offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_READ)); - break; - } -@@ -214,9 +213,8 @@ out: - * - * Writes data to MDI control register in the PHY at offset. - **/ --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { -- struct e1000_phy_info *phy = &hw->phy; - u32 i, mdicnfg, mdic = 0; - s32 ret_val = 0; - -@@ -235,7 +233,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - case e1000_i211: - mdicnfg = rd32(E1000_MDICNFG); - mdicnfg &= ~(E1000_MDICNFG_PHY_MASK); -- mdicnfg |= (phy->addr << E1000_MDICNFG_PHY_SHIFT); -+ mdicnfg |= (addr << E1000_MDICNFG_PHY_SHIFT); - wr32(E1000_MDICNFG, mdicnfg); - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -@@ -244,7 +242,7 @@ s32 igb_write_phy_reg_mdic(struct e1000_ - default: - mdic = (((u32)data) | - (offset << E1000_MDIC_REG_SHIFT) | -- (phy->addr << E1000_MDIC_PHY_SHIFT) | -+ (addr << E1000_MDIC_PHY_SHIFT) | - (E1000_MDIC_OP_WRITE)); - break; - } -@@ -464,7 +462,7 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -473,8 +471,8 @@ s32 igb_read_phy_reg_igp(struct e1000_hw - } - } - -- ret_val = igb_read_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_read_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -503,7 +501,7 @@ s32 igb_write_phy_reg_igp(struct e1000_h - goto out; - - if (offset > MAX_PHY_MULTI_PAGE_REG) { -- ret_val = igb_write_phy_reg_mdic(hw, -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, - IGP01E1000_PHY_PAGE_SELECT, - (u16)offset); - if (ret_val) { -@@ -512,8 +510,8 @@ s32 igb_write_phy_reg_igp(struct e1000_h - } - } - -- ret_val = igb_write_phy_reg_mdic(hw, MAX_PHY_REG_ADDRESS & offset, -- data); -+ ret_val = igb_write_phy_reg_mdic(hw, hw->phy.addr, -+ MAX_PHY_REG_ADDRESS & offset, data); - - hw->phy.ops.release(hw); - -@@ -2464,8 +2462,9 @@ out: - } - - /** -- * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * igb_write_reg_gs40g - Write GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to write to - * @offset: lower half is register offset to write to - * upper half is page to use. - * @data: data to write at register offset -@@ -2473,7 +2472,7 @@ out: - * Acquires semaphore, if necessary, then writes the data to PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2483,10 +2482,10 @@ s32 igb_write_phy_reg_gs40g(struct e1000 - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_write_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2494,8 +2493,24 @@ release: - } - - /** -- * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * igb_write_phy_reg_gs40g - Write GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to write to -+ * upper half is page to use. -+ * @data: data to write at register offset -+ * -+ * Acquires semaphore, if necessary, then writes the data to PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data) -+{ -+ return igb_write_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** -+ * igb_read_reg_gs40g - Read GS40G PHY register - * @hw: pointer to the HW structure -+ * @addr: phy address to read from - * @offset: lower half is register offset to read to - * upper half is page to use. - * @data: data to read at register offset -@@ -2503,7 +2518,7 @@ release: - * Acquires semaphore, if necessary, then reads the data in the PHY register - * at the offset. Release any acquired semaphores before exiting. - **/ --s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data) - { - s32 ret_val; - u16 page = offset >> GS40G_PAGE_SHIFT; -@@ -2513,10 +2528,10 @@ s32 igb_read_phy_reg_gs40g(struct e1000_ - if (ret_val) - return ret_val; - -- ret_val = igb_write_phy_reg_mdic(hw, GS40G_PAGE_SELECT, page); -+ ret_val = igb_write_phy_reg_mdic(hw, addr, GS40G_PAGE_SELECT, page); - if (ret_val) - goto release; -- ret_val = igb_read_phy_reg_mdic(hw, offset, data); -+ ret_val = igb_read_phy_reg_mdic(hw, addr, offset, data); - - release: - hw->phy.ops.release(hw); -@@ -2524,6 +2539,21 @@ release: - } - - /** -+ * igb_read_phy_reg_gs40g - Read GS40G PHY register -+ * @hw: pointer to the HW structure -+ * @offset: lower half is register offset to read to -+ * upper half is page to use. -+ * @data: data to read at register offset -+ * -+ * Acquires semaphore, if necessary, then reads the data in the PHY register -+ * at the offset. Release any acquired semaphores before exiting. -+ **/ -+s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data) -+{ -+ return igb_read_reg_gs40g(hw, hw->phy.addr, offset, data); -+} -+ -+/** - * igb_set_master_slave_mode - Setup PHY for Master/slave mode - * @hw: pointer to the HW structure - * ---- a/drivers/net/ethernet/intel/igb/e1000_phy.h -+++ b/drivers/net/ethernet/intel/igb/e1000_phy.h -@@ -61,8 +61,8 @@ s32 igb_phy_has_link(struct e1000_hw *h - void igb_power_up_phy_copper(struct e1000_hw *hw); - void igb_power_down_phy_copper(struct e1000_hw *hw); - s32 igb_phy_init_script_igp3(struct e1000_hw *hw); --s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 *data); --s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_phy_reg_mdic(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_read_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_i2c(struct e1000_hw *hw, u32 offset, u16 data); - s32 igb_read_sfp_data_byte(struct e1000_hw *hw, u16 offset, u8 *data); -@@ -72,6 +72,8 @@ s32 igb_phy_force_speed_duplex_82580(st - s32 igb_get_cable_length_82580(struct e1000_hw *hw); - s32 igb_read_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 *data); - s32 igb_write_phy_reg_gs40g(struct e1000_hw *hw, u32 offset, u16 data); -+s32 igb_read_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 *data); -+s32 igb_write_reg_gs40g(struct e1000_hw *hw, u8 addr, u32 offset, u16 data); - s32 igb_check_polarity_m88(struct e1000_hw *hw); - - /* IGP01E1000 Specific Registers */ diff --git a/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch b/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch deleted file mode 100644 index 01768e89cb..0000000000 --- a/target/linux/imx6/patches-4.1/204-net-igb-register-mii_bus-for-SerDes-w-external-phy.patch +++ /dev/null @@ -1,308 +0,0 @@ -From 03855caf93f7332a3f320228ba1a0e7baae8a749 Mon Sep 17 00:00:00 2001 -From: Tim Harvey <tharvey@gateworks.com> -Date: Thu, 15 May 2014 12:36:23 -0700 -Subject: [PATCH] net: igb: register mii_bus for SerDes w/ external phy - -If an i210 is configured for 1000BASE-BX link_mode and has an external phy -specified, then register an mii bus using the external phy address as -a mask. - -An i210 hooked to an external standard phy will be configured with a link_mo -of SGMII in which case phy ops will be configured and used internall in the -igb driver for link status. However, in certain cases one might be using a -backplane SerDes connection to something that talks on the mdio bus but is -not a standard phy, such as a switch. In this case by registering an mdio -bus a phy driver can manage the device. - -Signed-off-by: Tim Harvey <tharvey@gateworks.com> ---- - drivers/net/ethernet/intel/igb/e1000_82575.c | 15 +++ - drivers/net/ethernet/intel/igb/e1000_hw.h | 7 ++ - drivers/net/ethernet/intel/igb/igb_main.c | 168 ++++++++++++++++++++++++++- - 3 files changed, 185 insertions(+), 5 deletions(-) - ---- a/drivers/net/ethernet/intel/igb/e1000_82575.c -+++ b/drivers/net/ethernet/intel/igb/e1000_82575.c -@@ -598,13 +598,25 @@ static s32 igb_get_invariants_82575(stru - switch (link_mode) { - case E1000_CTRL_EXT_LINK_MODE_1000BASE_KX: - hw->phy.media_type = e1000_media_type_internal_serdes; -+ if (igb_sgmii_uses_mdio_82575(hw)) { -+ u32 mdicnfg = rd32(E1000_MDICNFG); -+ mdicnfg &= E1000_MDICNFG_PHY_MASK; -+ hw->phy.addr = mdicnfg >> E1000_MDICNFG_PHY_SHIFT; -+ hw_dbg("1000BASE_KX w/ external MDIO device at 0x%x\n", -+ hw->phy.addr); -+ } else { -+ hw_dbg("1000BASE_KX"); -+ } - break; - case E1000_CTRL_EXT_LINK_MODE_SGMII: - /* Get phy control interface type set (MDIO vs. I2C)*/ - if (igb_sgmii_uses_mdio_82575(hw)) { - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; -+ hw_dbg("SGMII with external MDIO PHY"); - break; -+ } else { -+ hw_dbg("SGMII with external I2C PHY"); - } - /* fall through for I2C based SGMII */ - case E1000_CTRL_EXT_LINK_MODE_PCIE_SERDES: -@@ -621,8 +633,11 @@ static s32 igb_get_invariants_82575(stru - hw->phy.media_type = e1000_media_type_copper; - dev_spec->sgmii_active = true; - } -+ hw_dbg("SERDES with external SFP"); - - break; -+ } else { -+ hw_dbg("SERDES"); - } - - /* do not change link mode for 100BaseFX */ ---- a/drivers/net/ethernet/intel/igb/e1000_hw.h -+++ b/drivers/net/ethernet/intel/igb/e1000_hw.h -@@ -27,6 +27,7 @@ - #include <linux/delay.h> - #include <linux/io.h> - #include <linux/netdevice.h> -+#include <linux/phy.h> - - #include "e1000_regs.h" - #include "e1000_defines.h" -@@ -543,6 +544,12 @@ struct e1000_hw { - struct e1000_mbx_info mbx; - struct e1000_host_mng_dhcp_cookie mng_cookie; - -+#ifdef CONFIG_PHYLIB -+ /* Phylib and MDIO interface */ -+ struct mii_bus *mii_bus; -+ struct phy_device *phy_dev; -+ phy_interface_t phy_interface; -+#endif - union { - struct e1000_dev_spec_82575 _82575; - } dev_spec; ---- a/drivers/net/ethernet/intel/igb/igb_main.c -+++ b/drivers/net/ethernet/intel/igb/igb_main.c -@@ -41,6 +41,7 @@ - #include <linux/if_vlan.h> - #include <linux/pci.h> - #include <linux/pci-aspm.h> -+#include <linux/phy.h> - #include <linux/delay.h> - #include <linux/interrupt.h> - #include <linux/ip.h> -@@ -2234,6 +2235,126 @@ static s32 igb_init_i2c(struct igb_adapt - return status; - } - -+ -+#ifdef CONFIG_PHYLIB -+/* -+ * MMIO/PHYdev support -+ */ -+ -+static int igb_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) -+{ -+ struct e1000_hw *hw = bus->priv; -+ u16 out; -+ int err; -+ -+ err = igb_read_reg_gs40g(hw, mii_id, regnum, &out); -+ if (err) -+ return err; -+ return out; -+} -+ -+static int igb_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, -+ u16 val) -+{ -+ struct e1000_hw *hw = bus->priv; -+ -+ return igb_write_reg_gs40g(hw, mii_id, regnum, val); -+} -+ -+static int igb_enet_mdio_reset(struct mii_bus *bus) -+{ -+ udelay(300); -+ return 0; -+} -+ -+static void igb_enet_mii_link(struct net_device *netdev) -+{ -+} -+ -+/* Probe the mdio bus for phys and connect them */ -+static int igb_enet_mii_probe(struct net_device *netdev) -+{ -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ struct phy_device *phy_dev = NULL; -+ int phy_id; -+ -+ /* check for attached phy */ -+ for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { -+ if (hw->mii_bus->phy_map[phy_id]) { -+ phy_dev = hw->mii_bus->phy_map[phy_id]; -+ break; -+ } -+ } -+ if (!phy_dev) { -+ netdev_err(netdev, "no PHY found\n"); -+ return -ENODEV; -+ } -+ -+ hw->phy_interface = PHY_INTERFACE_MODE_RGMII; -+ phy_dev = phy_connect(netdev, dev_name(&phy_dev->dev), -+ igb_enet_mii_link, hw->phy_interface); -+ if (IS_ERR(phy_dev)) { -+ netdev_err(netdev, "could not attach to PHY\n"); -+ return PTR_ERR(phy_dev); -+ } -+ -+ hw->phy_dev = phy_dev; -+ netdev_info(netdev, "igb PHY driver [%s] (mii_bus:phy_addr=%s)\n", -+ hw->phy_dev->drv->name, dev_name(&hw->phy_dev->dev)); -+ -+ return 0; -+} -+ -+/* Create and register mdio bus */ -+static int igb_enet_mii_init(struct pci_dev *pdev) -+{ -+ struct mii_bus *mii_bus; -+ struct net_device *netdev = pci_get_drvdata(pdev); -+ struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; -+ int err; -+ -+ mii_bus = mdiobus_alloc(); -+ if (mii_bus == NULL) { -+ err = -ENOMEM; -+ goto err_out; -+ } -+ -+ mii_bus->name = "igb_enet_mii_bus"; -+ mii_bus->read = igb_enet_mdio_read; -+ mii_bus->write = igb_enet_mdio_write; -+ mii_bus->reset = igb_enet_mdio_reset; -+ snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s-%x", -+ pci_name(pdev), hw->device_id + 1); -+ mii_bus->priv = hw; -+ mii_bus->parent = &pdev->dev; -+ mii_bus->phy_mask = ~(1 << hw->phy.addr); -+ -+ err = mdiobus_register(mii_bus); -+ if (err) { -+ printk(KERN_ERR "failed to register mii_bus: %d\n", err); -+ goto err_out_free_mdiobus; -+ } -+ hw->mii_bus = mii_bus; -+ -+ return 0; -+ -+err_out_free_mdiobus: -+ mdiobus_free(mii_bus); -+err_out: -+ return err; -+} -+ -+static void igb_enet_mii_remove(struct e1000_hw *hw) -+{ -+ if (hw->mii_bus) { -+ mdiobus_unregister(hw->mii_bus); -+ mdiobus_free(hw->mii_bus); -+ } -+} -+#endif /* CONFIG_PHYLIB */ -+ - /** - * igb_probe - Device Initialization Routine - * @pdev: PCI device information struct -@@ -2656,6 +2777,13 @@ static int igb_probe(struct pci_dev *pde - } - } - pm_runtime_put_noidle(&pdev->dev); -+ -+#ifdef CONFIG_PHYLIB -+ /* create and register the mdio bus if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_init(pdev); -+#endif -+ - return 0; - - err_register: -@@ -2799,6 +2927,10 @@ static void igb_remove(struct pci_dev *p - struct e1000_hw *hw = &adapter->hw; - - pm_runtime_get_noresume(&pdev->dev); -+#ifdef CONFIG_PHYLIB -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_remove(hw); -+#endif - #ifdef CONFIG_IGB_HWMON - igb_sysfs_exit(adapter); - #endif -@@ -3112,6 +3244,12 @@ static int __igb_open(struct net_device - if (!resuming) - pm_runtime_put(&pdev->dev); - -+#ifdef CONFIG_PHYLIB -+ /* Probe and connect to PHY if using ext phy */ -+ if (rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO) -+ igb_enet_mii_probe(netdev); -+#endif -+ - /* start the watchdog. */ - hw->mac.get_link_status = 1; - schedule_work(&adapter->watchdog_task); -@@ -7146,21 +7284,41 @@ void igb_alloc_rx_buffers(struct igb_rin - static int igb_mii_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd) - { - struct igb_adapter *adapter = netdev_priv(netdev); -+ struct e1000_hw *hw = &adapter->hw; - struct mii_ioctl_data *data = if_mii(ifr); - -- if (adapter->hw.phy.media_type != e1000_media_type_copper) -+ if (adapter->hw.phy.media_type != e1000_media_type_copper && -+ !(rd32(E1000_MDICNFG) & E1000_MDICNFG_EXT_MDIO)) - return -EOPNOTSUPP; - - switch (cmd) { - case SIOCGMIIPHY: -- data->phy_id = adapter->hw.phy.addr; -+ data->phy_id = hw->phy.addr; - break; - case SIOCGMIIREG: -- if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, -- &data->val_out)) -- return -EIO; -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_read_reg_gs40g(&adapter->hw, data->phy_id, -+ data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } else { -+ if (igb_read_phy_reg(&adapter->hw, data->reg_num & 0x1F, -+ &data->val_out)) -+ return -EIO; -+ } - break; - case SIOCSMIIREG: -+ if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211) { -+ if (igb_write_reg_gs40g(hw, data->phy_id, -+ data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } else { -+ if (igb_write_phy_reg(hw, data->reg_num & 0x1F, -+ data->val_in)) -+ return -EIO; -+ } -+ break; - default: - return -EOPNOTSUPP; - } diff --git a/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch b/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch deleted file mode 100644 index e8eafd143a..0000000000 --- a/target/linux/imx6/patches-4.1/205-phy-add-driver-for-GW16083-Ethernet-Expansion-Mezzan.patch +++ /dev/null @@ -1,27 +0,0 @@ ---- a/drivers/net/phy/Kconfig -+++ b/drivers/net/phy/Kconfig -@@ -293,6 +293,14 @@ endif # RTL8366_SMI - - source "drivers/net/phy/b53/Kconfig" - -+config GATEWORKS_GW16083 -+ tristate "Gateworks GW16083 Ethernet Expansion Mezzanine" -+ ---help--- -+ The Gateworks GW16083 Ethernet Expansion Mezzanine connects to a -+ Gateworks Ventana baseboard and provides a 7-port GbE managed -+ Ethernet switch with 4 dedicated GbE RJ45 ports, and 2 Gbe/SFP -+ ports" -+ - endif # PHYLIB - - config MICREL_KS8995MA ---- a/drivers/net/phy/Makefile -+++ b/drivers/net/phy/Makefile -@@ -40,6 +40,7 @@ obj-$(CONFIG_NATIONAL_PHY) += national.o - obj-$(CONFIG_DP83640_PHY) += dp83640.o - obj-$(CONFIG_STE10XP) += ste10Xp.o - obj-$(CONFIG_MICREL_PHY) += micrel.o -+obj-$(CONFIG_GATEWORKS_GW16083) += gw16083.o - obj-$(CONFIG_MDIO_OCTEON) += mdio-octeon.o - obj-$(CONFIG_MICREL_KS8995MA) += spi_ks8995.o - obj-$(CONFIG_AT803X_PHY) += at803x.o diff --git a/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch b/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch deleted file mode 100644 index 1b958a9849..0000000000 --- a/target/linux/imx6/patches-4.1/206-ARM-imx-ventana-added-GW16083-to-device-tree.patch +++ /dev/null @@ -1,56 +0,0 @@ ---- a/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi -@@ -158,6 +158,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi -@@ -225,6 +225,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi -@@ -226,6 +226,11 @@ - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { ---- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -+++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi -@@ -317,6 +317,11 @@ - }; - }; - }; -+ -+ gw16083: gw16083@52 { -+ compatible = "gateworks,gw16083"; -+ reg = <0x52>; -+ }; - }; - - &i2c3 { |