diff options
Diffstat (limited to 'target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch')
| -rw-r--r-- | target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch b/target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch new file mode 100644 index 0000000000..688de09a73 --- /dev/null +++ b/target/linux/imx6/patches-3.13/0005-PCI-designware-Fix-I-O-transfers-by-using-CPU-not-re.patch @@ -0,0 +1,67 @@ +From fce8591f73c6a30c231f220d1092362aae0b985c Mon Sep 17 00:00:00 2001 +From: Pratyush Anand <pratyush.anand@st.com> +Date: Wed, 11 Dec 2013 15:08:33 +0530 +Subject: [PATCH] PCI: designware: Fix I/O transfers by using CPU (not realio) + address + +pp->io_base, which is the input of the outbound IO address translation +unit, should be the CPU address. It was incorrectly programmed to the +realio address. + +We should pass global_io_offset rather than sys->io_offset to +pci_ioremap_io(), so we map the new window into the first available spot in +the Linux view of the I/O space. + +We must also pass CPU address instead of realio address to pci_ioremap_io(). + +This patch fixes above issue. It has been tested with Lecroy PTC in AIC +mode and Pericom PI7C9X2G303EL PCIe switch, which does not work otherwise. + +Tested-by: Mohit Kumar <mohit.kumar@st.com> +Tested-by: Tim Harvey <tharvey@gateworks.com> +Signed-off-by: Pratyush Anand <pratyush.anand@st.com> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Reviewed-by: Marek Vasut <marex@denx.de +Reviewed-by: Jagannadha Sutradharudu Teki <jagannadh.teki@gmail.com> +Acked-by: Arnd Bergmann <arnd@arndb.de> +Acked-by: Jingoo Han <jg1.han@samsung.com> +Cc: Richard Zhu <Hong-Xing.Zhu@freescale.com> +--- + drivers/pci/host/pcie-designware.c | 5 ++--- + 1 file changed, 2 insertions(+), 3 deletions(-) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -394,6 +394,7 @@ int __init dw_pcie_host_init(struct pcie + + global_io_offset); + pp->config.io_size = resource_size(&pp->io); + pp->config.io_bus_addr = range.pci_addr; ++ pp->io_base = range.cpu_addr; + } + if (restype == IORESOURCE_MEM) { + of_pci_range_to_resource(&range, np, &pp->mem); +@@ -419,7 +420,6 @@ int __init dw_pcie_host_init(struct pcie + + pp->cfg0_base = pp->cfg.start; + pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size; +- pp->io_base = pp->io.start; + pp->mem_base = pp->mem.start; + + pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base, +@@ -585,7 +585,6 @@ static int dw_pcie_wr_other_conf(struct + return ret; + } + +- + static int dw_pcie_valid_config(struct pcie_port *pp, + struct pci_bus *bus, int dev) + { +@@ -679,7 +678,7 @@ static int dw_pcie_setup(int nr, struct + + if (global_io_offset < SZ_1M && pp->config.io_size > 0) { + sys->io_offset = global_io_offset - pp->config.io_bus_addr; +- pci_ioremap_io(sys->io_offset, pp->io.start); ++ pci_ioremap_io(global_io_offset, pp->io_base); + global_io_offset += SZ_64K; + pci_add_resource_offset(&sys->resources, &pp->io, + sys->io_offset); |