diff options
Diffstat (limited to 'target/linux/imx6/patches-3.12')
20 files changed, 3767 insertions, 0 deletions
diff --git a/target/linux/imx6/patches-3.12/0001-ARM-dts-imx6qdl-add-pcie-device-node.patch b/target/linux/imx6/patches-3.12/0001-ARM-dts-imx6qdl-add-pcie-device-node.patch new file mode 100644 index 0000000000..d9c7377366 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0001-ARM-dts-imx6qdl-add-pcie-device-node.patch @@ -0,0 +1,38 @@ +From 3a57291fa4ca7f7647d826f5b47082ef306d839f Mon Sep 17 00:00:00 2001 +From: Sean Cross <xobs@kosagi.com> +Date: Thu, 26 Sep 2013 10:51:09 +0800 +Subject: [PATCH] ARM: dts: imx6qdl: add pcie device node + +Add pcie device node for imx6qdl. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/boot/dts/imx6qdl.dtsi | 16 ++++++++++++++++ + 1 file changed, 16 insertions(+) + +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -116,6 +116,22 @@ + arm,data-latency = <4 2 3>; + }; + ++ pcie: pcie@0x01000000 { ++ compatible = "fsl,imx6q-pcie", "snps,dw-pcie"; ++ reg = <0x01ffc000 0x4000>; /* DBI */ ++ #address-cells = <3>; ++ #size-cells = <2>; ++ device_type = "pci"; ++ ranges = <0x00000800 0 0x01f00000 0x01f00000 0 0x00080000 /* configuration space */ ++ 0x81000000 0 0 0x01f80000 0 0x00010000 /* downstream I/O */ ++ 0x82000000 0 0x01000000 0x01000000 0 0x00f00000>; /* non-prefetchable memory */ ++ num-lanes = <1>; ++ interrupts = <0 123 0x04>; ++ clocks = <&clks 189>, <&clks 187>, <&clks 206>, <&clks 144>; ++ clock-names = "pcie_ref_125m", "sata_ref_100m", "lvds_gate", "pcie_axi"; ++ status = "disabled"; ++ }; ++ + pmu { + compatible = "arm,cortex-a9-pmu"; + interrupts = <0 94 0x04>; diff --git a/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch b/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch new file mode 100644 index 0000000000..85212ca010 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0002-ARM-imx6q-Add-pll4_audio_div-to-clock-tree.patch @@ -0,0 +1,60 @@ +From 64990a431469a58b2949aca5be9d69e220d53892 Mon Sep 17 00:00:00 2001 +From: Nicolin Chen <b42378@freescale.com> +Date: Fri, 23 Aug 2013 19:20:34 +0800 +Subject: [PATCH] ARM: imx6q: Add pll4_audio_div to clock tree + +There's a pll4_audio_div clock, an extra divider for pll4, missing +in current clock tree, thus add it. + +Signed-off-by: Nicolin Chen <b42378@freescale.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/clk-imx6q.c | 9 +++++---- + 2 files changed, 6 insertions(+), 4 deletions(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -182,7 +182,7 @@ static const char *periph2_clk2_sels[] = { "pll3_usb_otg", "pll2_bus", }; + static const char *periph_sels[] = { "periph_pre", "periph_clk2", }; + static const char *periph2_sels[] = { "periph2_pre", "periph2_clk2", }; + static const char *axi_sels[] = { "periph", "pll2_pfd2_396m", "periph", "pll3_pfd1_540m", }; +-static const char *audio_sels[] = { "pll4_post_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; ++static const char *audio_sels[] = { "pll4_audio_div", "pll3_pfd2_508m", "pll3_pfd3_454m", "pll3_usb_otg", }; + static const char *gpu_axi_sels[] = { "axi", "ahb", }; + static const char *gpu2d_core_sels[] = { "axi", "pll3_usb_otg", "pll2_pfd0_352m", "pll2_pfd2_396m", }; + static const char *gpu3d_core_sels[] = { "mmdc_ch0_axi", "pll3_usb_otg", "pll2_pfd1_594m", "pll2_pfd2_396m", }; +@@ -196,7 +196,7 @@ static const char *ipu2_di0_sels[] = { "ipu2_di0_pre", "dummy", "dummy", "ldb_di + static const char *ipu2_di1_sels[] = { "ipu2_di1_pre", "dummy", "dummy", "ldb_di0", "ldb_di1", }; + static const char *hsi_tx_sels[] = { "pll3_120m", "pll2_pfd2_396m", }; + static const char *pcie_axi_sels[] = { "axi", "ahb", }; +-static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_post_div", }; ++static const char *ssi_sels[] = { "pll3_pfd2_508m", "pll3_pfd3_454m", "pll4_audio_div", }; + static const char *usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; + static const char *enfc_sels[] = { "pll2_pfd0_352m", "pll2_bus", "pll3_usb_otg", "pll2_pfd2_396m", }; + static const char *emi_sels[] = { "pll2_pfd2_396m", "pll3_usb_otg", "axi", "pll2_pfd0_352m", }; +@@ -205,7 +205,7 @@ static const char *vdo_axi_sels[] = { "axi", "ahb", }; + static const char *vpu_axi_sels[] = { "axi", "pll2_pfd2_396m", "pll2_pfd0_352m", }; + static const char *cko1_sels[] = { "pll3_usb_otg", "pll2_bus", "pll1_sys", "pll5_video_div", + "dummy", "axi", "enfc", "ipu1_di0", "ipu1_di1", "ipu2_di0", +- "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_post_div", }; ++ "ipu2_di1", "ahb", "ipg", "ipg_per", "ckil", "pll4_audio_div", }; + static const char *cko2_sels[] = { + "mmdc_ch0_axi", "mmdc_ch1_axi", "usdhc4", "usdhc1", + "gpu2d_axi", "dummy", "ecspi_root", "gpu3d_axi", +@@ -251,7 +251,7 @@ enum mx6q_clks { + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, +- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, clk_max ++ spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max + }; + + static struct clk *clk[clk_max]; +@@ -359,6 +359,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + clk[twd] = imx_clk_fixed_factor("twd", "arm", 1, 2); + + clk[pll4_post_div] = clk_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); ++ clk[pll4_audio_div] = clk_register_divider(NULL, "pll4_audio_div", "pll4_post_div", CLK_SET_RATE_PARENT, base + 0x170, 15, 1, 0, &imx_ccm_lock); + clk[pll5_post_div] = clk_register_divider_table(NULL, "pll5_post_div", "pll5_video", CLK_SET_RATE_PARENT, base + 0xa0, 19, 2, 0, post_div_table, &imx_ccm_lock); + clk[pll5_video_div] = clk_register_divider_table(NULL, "pll5_video_div", "pll5_post_div", CLK_SET_RATE_PARENT, base + 0x170, 30, 2, 0, video_div_table, &imx_ccm_lock); + diff --git a/target/linux/imx6/patches-3.12/0003-ARM-imx-add-soc-revision-helper-functions.patch b/target/linux/imx6/patches-3.12/0003-ARM-imx-add-soc-revision-helper-functions.patch new file mode 100644 index 0000000000..20ea995a88 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0003-ARM-imx-add-soc-revision-helper-functions.patch @@ -0,0 +1,52 @@ +From bfefdff8f91aa0a9ff1291d18d54498af276a6e5 Mon Sep 17 00:00:00 2001 +From: Shawn Guo <shawn.guo@linaro.org> +Date: Tue, 13 Aug 2013 13:54:02 +0800 +Subject: [PATCH] ARM: imx: add soc revision helper functions + +Similar to what we do for cpu type, the patch adds helper functions +imx_set_soc_revision() and imx_get_soc_revision() to maintain +imx_soc_revision in cpu.c. + +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/common.h | 2 ++ + arch/arm/mach-imx/cpu.c | 12 ++++++++++++ + 2 files changed, 14 insertions(+) + +--- a/arch/arm/mach-imx/common.h ++++ b/arch/arm/mach-imx/common.h +@@ -81,6 +81,8 @@ extern int imx6q_revision(void); + extern int mx53_display_revision(void); + extern void imx_set_aips(void __iomem *); + extern int mxc_device_init(void); ++void imx_set_soc_revision(unsigned int rev); ++unsigned int imx_get_soc_revision(void); + + enum mxc_cpu_pwr_mode { + WAIT_CLOCKED, /* wfi only */ +--- a/arch/arm/mach-imx/cpu.c ++++ b/arch/arm/mach-imx/cpu.c +@@ -8,11 +8,23 @@ + unsigned int __mxc_cpu_type; + EXPORT_SYMBOL(__mxc_cpu_type); + ++static unsigned int imx_soc_revision; ++ + void mxc_set_cpu_type(unsigned int type) + { + __mxc_cpu_type = type; + } + ++void imx_set_soc_revision(unsigned int rev) ++{ ++ imx_soc_revision = rev; ++} ++ ++unsigned int imx_get_soc_revision(void) ++{ ++ return imx_soc_revision; ++} ++ + void imx_print_silicon_rev(const char *cpu, int srev) + { + if (srev == IMX_CHIP_REVISION_UNKNOWN) diff --git a/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch b/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch new file mode 100644 index 0000000000..1e12531546 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0004-ARM-imx6q-use-common-soc-revision-helpers.patch @@ -0,0 +1,93 @@ +From 3f75978b3742157853618c5c6dd4a5f49aa950b1 Mon Sep 17 00:00:00 2001 +From: Shawn Guo <shawn.guo@linaro.org> +Date: Tue, 13 Aug 2013 14:10:29 +0800 +Subject: [PATCH] ARM: imx6q: use common soc revision helpers + +It calls imx_set_soc_revision() to set up soc revision in +imx6q_init_revision(), and replaces all the occurrences of +imx6q_revision() with common helper imx_get_soc_revision(). + +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/clk-imx6q.c | 5 +++-- + arch/arm/mach-imx/common.h | 1 - + arch/arm/mach-imx/mach-imx6q.c | 13 ++++--------- + 3 files changed, 7 insertions(+), 12 deletions(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -300,7 +300,7 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + WARN_ON(!base); + + /* Audio/video PLL post dividers do not work on i.MX6q revision 1.0 */ +- if (cpu_is_imx6q() && imx6q_revision() == IMX_CHIP_REVISION_1_0) { ++ if (cpu_is_imx6q() && imx_get_soc_revision() == IMX_CHIP_REVISION_1_0) { + post_div_table[1].div = 1; + post_div_table[2].div = 1; + video_div_table[1].div = 1; +@@ -574,7 +574,8 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + clk_register_clkdev(clk[pll4_post_div], "pll4_post_div", NULL); + clk_register_clkdev(clk[pll4_audio], "pll4_audio", NULL); + +- if ((imx6q_revision() != IMX_CHIP_REVISION_1_0) || cpu_is_imx6dl()) { ++ if ((imx_get_soc_revision() != IMX_CHIP_REVISION_1_0) || ++ cpu_is_imx6dl()) { + clk_set_parent(clk[ldb_di0_sel], clk[pll5_video_div]); + clk_set_parent(clk[ldb_di1_sel], clk[pll5_video_div]); + } +--- a/arch/arm/mach-imx/common.h ++++ b/arch/arm/mach-imx/common.h +@@ -73,7 +73,6 @@ extern void mxc_restart(enum reboot_mode, const char *); + extern void mxc_arch_reset_init(void __iomem *); + extern void mxc_arch_reset_init_dt(void); + extern int mx53_revision(void); +-extern int imx6q_revision(void); + extern int mx53_display_revision(void); + extern void imx_set_aips(void __iomem *); + extern int mxc_device_init(void); +--- a/arch/arm/mach-imx/mach-imx6q.c ++++ b/arch/arm/mach-imx/mach-imx6q.c +@@ -38,16 +38,10 @@ + #include "cpuidle.h" + #include "hardware.h" + +-static u32 chip_revision; +- +-int imx6q_revision(void) +-{ +- return chip_revision; +-} +- + static void __init imx6q_init_revision(void) + { + u32 rev = imx_anatop_get_digprog(); ++ u32 chip_revision; + + switch (rev & 0xff) { + case 0: +@@ -64,6 +58,7 @@ static void __init imx6q_init_revision(void) + } + + mxc_set_cpu_type(rev >> 16 & 0xff); ++ imx_set_soc_revision(chip_revision); + } + + static void imx6q_restart(enum reboot_mode mode, const char *cmd) +@@ -269,7 +264,7 @@ + * WAIT mode is broken on TO 1.0 and 1.1, so there is no point + * to run cpuidle on them. + */ +- if (imx6q_revision() > IMX_CHIP_REVISION_1_1) ++ if (imx_get_soc_revision() > IMX_CHIP_REVISION_1_1) + imx6q_cpuidle_init(); + + if (IS_ENABLED(CONFIG_ARM_IMX6Q_CPUFREQ)) { +@@ -298,7 +293,7 @@ + of_clk_init(NULL); + clocksource_of_init(); + imx_print_silicon_rev(cpu_is_imx6dl() ? "i.MX6DL" : "i.MX6Q", +- imx6q_revision()); ++ imx_get_soc_revision()); + } + + static const char *imx6q_dt_compat[] __initdata = { diff --git a/target/linux/imx6/patches-3.12/0005-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch b/target/linux/imx6/patches-3.12/0005-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch new file mode 100644 index 0000000000..5e62015738 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0005-ARM-imx-Add-LVDS-general-purpose-clocks-to-i.MX6Q.patch @@ -0,0 +1,58 @@ +From bf22172158cd6dcc5be6dc286ff5c33794dd0ae8 Mon Sep 17 00:00:00 2001 +From: Sean Cross <xobs@kosagi.com> +Date: Mon, 16 Sep 2013 08:20:52 +0000 +Subject: [PATCH] ARM: imx: Add LVDS general-purpose clocks to i.MX6Q + +The i.MX6 has two general-purpose LVDS clocks that can be driven +from a variety of sources. This patch adds a mux and a gate for +both of these clocks. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/clk-imx6q.c | 20 +++++++++++++++++++- + 2 files changed, 23 insertions(+), 1 deletion(-) + +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -217,6 +217,11 @@ static const char *cko2_sels[] = { + "uart_serial", "spdif", "asrc", "hsi_tx", + }; + static const char *cko_sels[] = { "cko1", "cko2", }; ++static const char *lvds_sels[] = { ++ "dummy", "dummy", "dummy", "dummy", "dummy", "dummy", ++ "pll4_audio", "pll5_video", "pll8_mlb", "enet_ref", ++ "pcie_ref", "sata_ref", ++}; + + enum mx6q_clks { + dummy, ckil, ckih, osc, pll2_pfd0_352m, pll2_pfd1_594m, pll2_pfd2_396m, +@@ -251,7 +256,8 @@ enum mx6q_clks { + ssi2_ipg, ssi3_ipg, rom, usbphy1, usbphy2, ldb_di0_div_3_5, ldb_di1_div_3_5, + sata_ref, sata_ref_100m, pcie_ref, pcie_ref_125m, enet_ref, usbphy1_gate, + usbphy2_gate, pll4_post_div, pll5_post_div, pll5_video_div, eim_slow, +- spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, clk_max ++ spdif, cko2_sel, cko2_podf, cko2, cko, vdoa, pll4_audio_div, ++ lvds1_sel, lvds2_sel, lvds1_gate, lvds2_gate, clk_max + }; + + static struct clk *clk[clk_max]; +@@ -342,6 +348,18 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + base + 0xe0, 0, 2, 0, clk_enet_ref_table, + &imx_ccm_lock); + ++ clk[lvds1_sel] = imx_clk_mux("lvds1_sel", base + 0x160, 0, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); ++ clk[lvds2_sel] = imx_clk_mux("lvds2_sel", base + 0x160, 5, 5, lvds_sels, ARRAY_SIZE(lvds_sels)); ++ ++ /* ++ * lvds1_gate and lvds2_gate are pseudo-gates. Both can be ++ * independently configured as clock inputs or outputs. We treat ++ * the "output_enable" bit as a gate, even though it's really just ++ * enabling clock output. ++ */ ++ clk[lvds1_gate] = imx_clk_gate("lvds1_gate", "dummy", base + 0x160, 10); ++ clk[lvds2_gate] = imx_clk_gate("lvds2_gate", "dummy", base + 0x160, 11); ++ + /* name parent_name reg idx */ + clk[pll2_pfd0_352m] = imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0); + clk[pll2_pfd1_594m] = imx_clk_pfd("pll2_pfd1_594m", "pll2_bus", base + 0x100, 1); diff --git a/target/linux/imx6/patches-3.12/0006-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch b/target/linux/imx6/patches-3.12/0006-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch new file mode 100644 index 0000000000..08e45dfaec --- /dev/null +++ b/target/linux/imx6/patches-3.12/0006-ARM-imx6q-clock-and-Kconfig-update-for-PCIe-support.patch @@ -0,0 +1,45 @@ +From 74b8031307c5d33d36742c26dd0921991bd5a255 Mon Sep 17 00:00:00 2001 +From: Sean Cross <xobs@kosagi.com> +Date: Thu, 26 Sep 2013 10:45:35 +0800 +Subject: [PATCH] ARM: imx6q: clock and Kconfig update for PCIe support + +Update imx6q clock initialization and Kconfig for PCIe support. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/Kconfig | 2 ++ + arch/arm/mach-imx/clk-imx6q.c | 4 ++++ + 2 files changed, 6 insertions(+) + +diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig +index e017915..270f786 100644 +--- a/arch/arm/mach-imx/Kconfig ++++ b/arch/arm/mach-imx/Kconfig +@@ -802,6 +802,8 @@ config SOC_IMX6Q + select HAVE_IMX_SRC + select HAVE_SMP + select MFD_SYSCON ++ select MIGHT_HAVE_PCI ++ select PCI_DOMAINS if PCI + select PINCTRL + select PINCTRL_IMX6Q + select PL310_ERRATA_588369 if CACHE_PL310 +diff --git a/arch/arm/mach-imx/clk-imx6q.c b/arch/arm/mach-imx/clk-imx6q.c +index e8e5bad..07bc0d8 100644 +--- a/arch/arm/mach-imx/clk-imx6q.c ++++ b/arch/arm/mach-imx/clk-imx6q.c +@@ -623,6 +623,10 @@ static void __init imx6q_clocks_init(struct device_node *ccm_node) + if (ret) + pr_warn("failed to set up CLKO: %d\n", ret); + ++ /* All existing boards with PCIe use LVDS1 */ ++ if (IS_ENABLED(CONFIG_PCI_IMX6)) ++ clk_set_parent(clk[lvds1_sel], clk[sata_ref]); ++ + /* Set initial power mode */ + imx6q_set_lpm(WAIT_CLOCKED); + +-- +1.8.4.1 + diff --git a/target/linux/imx6/patches-3.12/0007-ARM-dts-added-several-new-imx-pinmux-groups.patch b/target/linux/imx6/patches-3.12/0007-ARM-dts-added-several-new-imx-pinmux-groups.patch new file mode 100644 index 0000000000..105cb71162 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0007-ARM-dts-added-several-new-imx-pinmux-groups.patch @@ -0,0 +1,115 @@ +From 3f7fbfad3edc92227b9ae91050837a6d1de374f5 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Tue, 22 Oct 2013 21:51:25 -0700 +Subject: [PATCH] ARM: dts: added several new imx-pinmux groups + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/boot/dts/imx6qdl.dtsi | 60 ++++++++++++++++++++++++++++++++++++++++++ + 1 file changed, 60 insertions(+) + +--- a/arch/arm/boot/dts/imx6qdl.dtsi ++++ b/arch/arm/boot/dts/imx6qdl.dtsi +@@ -639,6 +639,14 @@ + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 + >; + }; ++ ++ pinctrl_audmux_4: audmux-4 { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D24__AUD5_RXFS 0x80000000 ++ MX6QDL_PAD_EIM_D25__AUD5_RXC 0x80000000 ++ MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000 ++ >; ++ }; + }; + + ecspi1 { +@@ -811,6 +819,28 @@ + MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1 + >; + }; ++ ++ /* No Strobe */ ++ pinctrl_gpmi_nand_2: gpmi-nand-2 { ++ fsl,pins = < ++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 ++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 ++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 ++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 ++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 ++ MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1 ++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 ++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 ++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 ++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 ++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 ++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 ++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 ++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 ++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 ++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 ++ >; ++ }; + }; + + hdmi_hdcp { +@@ -1058,6 +1088,13 @@ + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + >; + }; ++ ++ pinctrl_uart1_2: uart1grp-2 { ++ fsl,pins = < ++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1 ++ >; ++ }; + }; + + uart2 { +@@ -1076,6 +1113,13 @@ + MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1 + >; + }; ++ ++ pinctrl_uart2_3: uart2grp-3 { ++ fsl,pins = < ++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1 ++ >; ++ }; + }; + + uart3 { +@@ -1096,6 +1140,13 @@ + MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1 + >; + }; ++ ++ pinctrl_uart3_3: uart3grp-3 { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 ++ >; ++ }; + }; + + uart4 { +@@ -1107,6 +1158,15 @@ + }; + }; + ++ uart5 { ++ pinctrl_uart5_1: uart5grp-1 { ++ fsl,pins = < ++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1 ++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1 ++ >; ++ }; ++ }; ++ + usbotg { + pinctrl_usbotg_1: usbotggrp-1 { + fsl,pins = < diff --git a/target/linux/imx6/patches-3.12/0008-ARM-dts-add-Gateworks-Ventana-support.patch b/target/linux/imx6/patches-3.12/0008-ARM-dts-add-Gateworks-Ventana-support.patch new file mode 100644 index 0000000000..4e2070b5d6 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0008-ARM-dts-add-Gateworks-Ventana-support.patch @@ -0,0 +1,2240 @@ +From 02b02b9176fc62b97e58487e35af7df782a0047d Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Tue, 22 Oct 2013 21:51:26 -0700 +Subject: [PATCH] ARM: dts: add Gateworks Ventana support + +The Gateworks Ventana product family consists of several baseboard designs +based on the Freescale i.MX6 family of processors. Each baseboard has a +different set of possible features. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/boot/dts/Makefile | 9 + + arch/arm/boot/dts/imx6dl-gw51xx.dts | 19 ++ + arch/arm/boot/dts/imx6dl-gw52xx.dts | 19 ++ + arch/arm/boot/dts/imx6dl-gw53xx.dts | 19 ++ + arch/arm/boot/dts/imx6dl-gw54xx.dts | 19 ++ + arch/arm/boot/dts/imx6q-gw51xx.dts | 19 ++ + arch/arm/boot/dts/imx6q-gw52xx.dts | 23 ++ + arch/arm/boot/dts/imx6q-gw53xx.dts | 23 ++ + arch/arm/boot/dts/imx6q-gw5400-a.dts | 443 ++++++++++++++++++++++++++++++++ + arch/arm/boot/dts/imx6q-gw54xx.dts | 23 ++ + arch/arm/boot/dts/imx6qdl-gw51xx.dtsi | 272 ++++++++++++++++++++ + arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 373 +++++++++++++++++++++++++++ + arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 429 +++++++++++++++++++++++++++++++ + arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 457 ++++++++++++++++++++++++++++++++++ + 14 files changed, 2147 insertions(+) + create mode 100644 arch/arm/boot/dts/imx6dl-gw51xx.dts + create mode 100644 arch/arm/boot/dts/imx6dl-gw52xx.dts + create mode 100644 arch/arm/boot/dts/imx6dl-gw53xx.dts + create mode 100644 arch/arm/boot/dts/imx6dl-gw54xx.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw51xx.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw52xx.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw53xx.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw5400-a.dts + create mode 100644 arch/arm/boot/dts/imx6q-gw54xx.dts + create mode 100644 arch/arm/boot/dts/imx6qdl-gw51xx.dtsi + create mode 100644 arch/arm/boot/dts/imx6qdl-gw52xx.dtsi + create mode 100644 arch/arm/boot/dts/imx6qdl-gw53xx.dtsi + create mode 100644 arch/arm/boot/dts/imx6qdl-gw54xx.dtsi + +--- a/arch/arm/boot/dts/Makefile ++++ b/arch/arm/boot/dts/Makefile +@@ -131,10 +131,19 @@ dtb-$(CONFIG_ARCH_MXC) += \ + imx53-mba53.dtb \ + imx53-qsb.dtb \ + imx53-smd.dtb \ ++ imx6dl-gw51xx.dtb \ ++ imx6dl-gw52xx.dtb \ ++ imx6dl-gw53xx.dtb \ ++ imx6dl-gw54xx.dtb \ + imx6dl-sabreauto.dtb \ + imx6dl-sabresd.dtb \ + imx6dl-wandboard.dtb \ + imx6q-arm2.dtb \ ++ imx6q-gw51xx.dtb \ ++ imx6q-gw52xx.dtb \ ++ imx6q-gw53xx.dtb \ ++ imx6q-gw5400-a.dtb \ ++ imx6q-gw54xx.dtb \ + imx6q-phytec-pbab01.dtb \ + imx6q-sabreauto.dtb \ + imx6q-sabrelite.dtb \ +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw51xx.dts +@@ -0,0 +1,19 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw51xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite GW51XX"; ++ compatible = "gw,imx6dl-gw51xx", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw52xx.dts +@@ -0,0 +1,19 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw52xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite GW52XX"; ++ compatible = "gw,imx6dl-gw52xx", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw53xx.dts +@@ -0,0 +1,19 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw53xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite GW53XX"; ++ compatible = "gw,imx6dl-gw53xx", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6dl-gw54xx.dts +@@ -0,0 +1,19 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6dl.dtsi" ++#include "imx6qdl-gw54xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 DualLite GW54XX"; ++ compatible = "gw,imx6dl-gw54xx", "gw,ventana", "fsl,imx6dl"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw51xx.dts +@@ -0,0 +1,19 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++#include "imx6qdl-gw54xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Quad GW51XX"; ++ compatible = "gw,imx6q-gw51xx", "gw,ventana", "fsl,imx6q"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw52xx.dts +@@ -0,0 +1,23 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++#include "imx6qdl-gw52xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Quad GW52XX"; ++ compatible = "gw,imx6q-gw52xx", "gw,ventana", "fsl,imx6q"; ++}; ++ ++&sata { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw53xx.dts +@@ -0,0 +1,23 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++#include "imx6qdl-gw53xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Quad GW53XX"; ++ compatible = "gw,imx6q-gw53xx", "gw,ventana", "fsl,imx6q"; ++}; ++ ++&sata { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw5400-a.dts +@@ -0,0 +1,443 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++ ++/ { ++ model = "Gateworks Ventana GW5400-A"; ++ compatible = "gw,imx6q-gw5400-a", "gw,ventana", "fsl,imx6q"; ++ ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ ethernet0 = &fec; ++ ethernet1 = ð1; ++ i2c0 = &i2c1; ++ i2c1 = &i2c2; ++ i2c2 = &i2c3; ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ sky2 = ð1; ++ ssi0 = &ssi1; ++ spi0 = &ecspi1; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ usdhc2 = &usdhc3; ++ }; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 10 0>; /* 106 -> MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x40000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ gpios = <&gpio1 5 0>; ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_1p0v: 1p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P0V"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_h1_vbus: usb_h1_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 0>; ++ enable-active-high; ++ }; ++ }; ++ ++ sound { ++ compatible = "fsl,imx6q-sabrelite-sgtl5000", ++ "fsl,imx-audio-sgtl5000"; ++ model = "imx6q-sabrelite-sgtl5000"; ++ ssi-controller = <&ssi1>; ++ audio-codec = <&codec>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ mux-int-port = <1>; ++ mux-ext-port = <4>; ++ }; ++}; ++ ++&audmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_audmux_1>; ++ status = "okay"; ++}; ++ ++&ecspi1 { ++ fsl,spi-num-chipselects = <1>; ++ cs-gpios = <&gpio3 19 0>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_ecspi1_1>; ++ status = "okay"; ++ ++ flash: m25p80@0 { ++ compatible = "sst,w25q256"; ++ spi-max-frequency = <30000000>; ++ reg = <0>; ++ }; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rgmii"; ++ phy-reset-gpios = <&gpio1 30 0>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_1>; ++ status = "okay"; ++ ++ eeprom1: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom2: eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom3: eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom4: eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ gpio: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ hwmon: gsc@29 { ++ compatible = "gw,gsp"; ++ reg = <0x29>; ++ }; ++ ++ rtc: ds1672@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2_2>; ++ status = "okay"; ++ ++ pmic: pfuze100@08 { ++ compatible = "fsl,pfuze100"; ++ reg = <0x08>; ++ ++ regulators { ++ sw1a_reg: sw1ab { ++ regulator-min-microvolt = <300000>; ++ regulator-max-microvolt = <1875000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <6250>; ++ }; ++ ++ sw1c_reg: sw1c { ++ regulator-min-microvolt = <300000>; ++ regulator-max-microvolt = <1875000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <6250>; ++ }; ++ ++ sw2_reg: sw2 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3950000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3a_reg: sw3a { ++ regulator-min-microvolt = <400000>; ++ regulator-max-microvolt = <1975000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3b_reg: sw3b { ++ regulator-min-microvolt = <400000>; ++ regulator-max-microvolt = <1975000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw4_reg: sw4 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ swbst_reg: swbst { ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5150000>; ++ }; ++ ++ snvs_reg: vsnvs { ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vref_reg: vrefddr { ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vgen1_reg: vgen1 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1550000>; ++ }; ++ ++ vgen2_reg: vgen2 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1550000>; ++ }; ++ ++ vgen3_reg: vgen3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vgen4_reg: vgen4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vgen5_reg: vgen5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vgen6_reg: vgen6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ pciswitch: pex8609@3f { ++ compatible = "plx,pex8609"; ++ reg = <0x3f>; ++ }; ++ ++ pciclkgen: si52147@6b { ++ compatible = "sil,si52147"; ++ reg = <0x6b>; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3_2>; ++ status = "okay"; ++ ++ accelerometer: mma8450@1c { ++ compatible = "fsl,mma8450"; ++ reg = <0x1c>; ++ }; ++ ++ codec: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks 201>; ++ VDDA-supply = <&sw4_reg>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++ ++ hdmiin: adv7611@4c { ++ compatible = "adi,adv7611"; ++ reg = <0x4c>; ++ }; ++ ++ touchscreen: egalax_ts@04 { ++ compatible = "eeti,egalax_ts"; ++ reg = <0x04>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <12 2>; /* gpio7_12 active low */ ++ wakeup-gpios = <&gpio7 12 0>; ++ }; ++ ++ videoout: adv7393@2a { ++ compatible = "adi,adv7393"; ++ reg = <0x2a>; ++ }; ++ ++ videoin: adv7180@20 { ++ compatible = "adi,adv7180"; ++ reg = <0x20>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ ++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ ++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ ++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ ++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ ++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x80000000 /* GPS_PPS */ ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ ++ MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x80000000 /* user2 led */ ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ ++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ ++ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ status = "okay"; ++ lvds-channel@0 { ++ crtcs = <&ipu1 0>, <&ipu1 1>, <&ipu2 0>, <&ipu2 1>; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio1 29 0>; ++ status = "okay"; ++ ++ eth1: sky2@8 { /* MAC/PHY on bus 8 */ ++ compatible = "marvell,sky2"; ++ }; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_2>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5_1>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg_1>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc3_2>; ++ cd-gpios = <&gpio7 0 0>; ++ vmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6q-gw54xx.dts +@@ -0,0 +1,23 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/dts-v1/; ++#include "imx6q.dtsi" ++#include "imx6qdl-gw54xx.dtsi" ++ ++/ { ++ model = "Gateworks Ventana i.MX6 Quad GW54XX"; ++ compatible = "gw,imx6q-gw54xx", "gw,ventana", "fsl,imx6q"; ++}; ++ ++&sata { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw51xx.dtsi +@@ -0,0 +1,272 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ can0 = &can1; ++ ethernet0 = &fec; ++ led0 = &led0; ++ led1 = &led1; ++ nand = &gpmi; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ }; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x20000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ gpios = <&gpio1 26 0>; ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_5p0v: 5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5P0V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 0>; ++ enable-active-high; ++ }; ++ }; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rgmii"; ++ phy-reset-gpios = <&gpio1 30 0>; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand_2>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_1>; ++ status = "okay"; ++ ++ eeprom1: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom2: eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom3: eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom4: eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ gpio: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ hwmon: gsc@29 { ++ compatible = "gw,gsp"; ++ reg = <0x29>; ++ }; ++ ++ rtc: ds1672@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2_2>; ++ status = "okay"; ++ ++ pmic: ltc3676@3c { ++ compatible = "ltc,ltc3676"; ++ reg = <0x3c>; ++ ++ regulators { ++ sw1_reg: ltc3676__sw1 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw2_reg: ltc3676__sw2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3_reg: ltc3676__sw3 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw4_reg: ltc3676__sw4 { ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo2_reg: ltc3676__ldo2 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo4_reg: ltc3676__ldo4 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3_2>; ++ status = "okay"; ++ ++ videoin: adv7180@20 { ++ compatible = "adi,adv7180"; ++ reg = <0x20>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ ++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ ++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ ++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ ++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x80000000 /* PCIE_RST# */ ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ ++ >; ++ }; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio1 0 0>; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_2>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_3>; ++ status = "okay"; ++}; ++ ++&uart3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart3_3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5_1>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg_1>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi +@@ -0,0 +1,373 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ ethernet0 = &fec; ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ nand = &gpmi; ++ ssi0 = &ssi1; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ usdhc2 = &usdhc3; ++ }; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 1>; /* 111 - MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x20000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ gpios = <&gpio1 26 0>; ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_1p0v: 1p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P0V"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ }; ++ ++ /* remove this fixed regulator once ltc3676__sw2 driver available */ ++ reg_1p8v: 1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_5p0v: 5p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "5P0V"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 0>; ++ enable-active-high; ++ }; ++ }; ++ ++ sound { ++ compatible = "fsl,imx6q-sabrelite-sgtl5000", ++ "fsl,imx-audio-sgtl5000"; ++ model = "imx6q-sabrelite-sgtl5000"; ++ ssi-controller = <&ssi1>; ++ audio-codec = <&codec>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ mux-int-port = <1>; ++ mux-ext-port = <4>; ++ }; ++}; ++ ++&audmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_audmux_1>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rgmii"; ++ phy-reset-gpios = <&gpio1 30 0>; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand_2>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_1>; ++ status = "okay"; ++ ++ eeprom1: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom2: eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom3: eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom4: eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ gpio: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ hwmon: gsc@29 { ++ compatible = "gw,gsp"; ++ reg = <0x29>; ++ }; ++ ++ rtc: ds1672@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2_2>; ++ status = "okay"; ++ ++ pciswitch: pex8609@3f { ++ compatible = "plx,pex8609"; ++ reg = <0x3f>; ++ }; ++ ++ pmic: ltc3676@3c { ++ compatible = "ltc,ltc3676"; ++ reg = <0x3c>; ++ ++ regulators { ++ sw1_reg: ltc3676__sw1 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw2_reg: ltc3676__sw2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3_reg: ltc3676__sw3 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw4_reg: ltc3676__sw4 { ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo2_reg: ltc3676__ldo2 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo3_reg: ltc3676__ldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ ldo4_reg: ltc3676__ldo4 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3_2>; ++ status = "okay"; ++ ++ accelerometer: fxos8700@1e { ++ compatible = "fsl,fxos8700"; ++ reg = <0x13>; ++ }; ++ ++ codec: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks 169>; ++ VDDA-supply = <®_1p8v>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++ ++ touchscreen: egalax_ts@04 { ++ compatible = "eeti,egalax_ts"; ++ reg = <0x04>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <12 2>; /* gpio7_12 active low */ ++ wakeup-gpios = <&gpio7 12 0>; ++ }; ++ ++ videoin: adv7180@20 { ++ compatible = "adi,adv7180"; ++ reg = <0x20>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* MEZZ_DIO0 */ ++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* MEZZ_DIO1 */ ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ ++ MX6QDL_PAD_EIM_D31__GPIO3_IO31 0x80000000 /* VIDDEC_PDN# */ ++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x80000000 /* PHY Reset */ ++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE_RST# */ ++ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_PWDN */ ++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ ++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* USB_SEL_PCI */ ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ ++ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* LVDS_TCH# */ ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_CD# */ ++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x80000000 /* UART2_EN# */ ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ status = "okay"; ++ lvds-channel@0 { ++ crtcs = <&ipu1 0>, <&ipu1 1>; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio1 29 0>; ++ status = "okay"; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_2>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5_1>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg_1>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc3_2>; ++ cd-gpios = <&gpio7 0 0>; ++ vmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi +@@ -0,0 +1,429 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ can0 = &can1; ++ ethernet0 = &fec; ++ ethernet1 = ð1; ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ nand = &gpmi; ++ sky2 = ð1; ++ ssi0 = &ssi1; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ usdhc2 = &usdhc3; ++ }; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x40000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ gpios = <&gpio1 26 0>; ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_1p0v: 1p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P0V"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ }; ++ ++ /* remove when pmic 1p8 regulator available */ ++ reg_1p8v: 1p8v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P8V"; ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_h1_vbus: usb_h1_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 0>; ++ enable-active-high; ++ }; ++ }; ++ ++ sound { ++ compatible = "fsl,imx6q-sabrelite-sgtl5000", ++ "fsl,imx-audio-sgtl5000"; ++ model = "imx6q-sabrelite-sgtl5000"; ++ ssi-controller = <&ssi1>; ++ audio-codec = <&codec>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ mux-int-port = <1>; ++ mux-ext-port = <4>; ++ }; ++}; ++ ++&audmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_audmux_1>; ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1_1>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rgmii"; ++ phy-reset-gpios = <&gpio1 30 0>; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand_2>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_1>; ++ status = "okay"; ++ ++ eeprom1: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom2: eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom3: eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom4: eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ gpio: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ hwmon: gsc@29 { ++ compatible = "gw,gsp"; ++ reg = <0x29>; ++ }; ++ ++ rtc: ds1672@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2_2>; ++ status = "okay"; ++ ++ pciclkgen: si53156@6b { ++ compatible = "sil,si53156"; ++ reg = <0x6b>; ++ }; ++ ++ pciswitch: pex8606@3f { ++ compatible = "plx,pex8606"; ++ reg = <0x3f>; ++ }; ++ ++ pmic: ltc3676@3c { ++ compatible = "ltc,ltc3676"; ++ reg = <0x3c>; ++ ++ regulators { ++ /* VDD_SOC */ ++ sw1_reg: ltc3676__sw1 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_1P8 */ ++ sw2_reg: ltc3676__sw2 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_ARM */ ++ sw3_reg: ltc3676__sw3 { ++ regulator-min-microvolt = <1175000>; ++ regulator-max-microvolt = <1175000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_DDR */ ++ sw4_reg: ltc3676__sw4 { ++ regulator-min-microvolt = <1500000>; ++ regulator-max-microvolt = <1500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_2P5 */ ++ ldo2_reg: ltc3676__ldo2 { ++ regulator-min-microvolt = <2500000>; ++ regulator-max-microvolt = <2500000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_1P8 */ ++ ldo3_reg: ltc3676__ldo3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ /* VDD_HIGH */ ++ ldo4_reg: ltc3676__ldo4 { ++ regulator-min-microvolt = <3000000>; ++ regulator-max-microvolt = <3000000>; ++ }; ++ }; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3_2>; ++ status = "okay"; ++ ++ accelerometer: fxos8700@1e { ++ compatible = "fsl,fxos8700"; ++ reg = <0x1e>; ++ }; ++ ++ codec: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks 201>; ++ VDDA-supply = <®_1p8v>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++ ++ hdmiin: adv7611@4c { ++ compatible = "adi,adv7611"; ++ reg = <0x4c>; ++ }; ++ ++ touchscreen: egalax_ts@04 { ++ compatible = "eeti,egalax_ts"; ++ reg = <0x04>; ++ interrupt-parent = <&gpio1>; ++ interrupts = <11 2>; /* gpio1_11 active low */ ++ wakeup-gpios = <&gpio1 11 0>; ++ }; ++ ++ videoout: adv7393@2a { ++ compatible = "adi,adv7393"; ++ reg = <0x2a>; ++ }; ++ ++ videoin: adv7180@20 { ++ compatible = "adi,adv7180"; ++ reg = <0x20>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_A19__GPIO2_IO19 0x80000000 /* PCIE6EXP_DIO0 */ ++ MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x80000000 /* PCIE6EXP_DIO1 */ ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ ++ MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x80000000 /* GPS_SHDN */ ++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ ++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ ++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ ++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ ++ MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x80000000 /* PMIC_IRQ# */ ++ MX6QDL_PAD_GPIO_9__GPIO1_IO09 0x80000000 /* HUB_RST# */ ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* PCIE_WDIS# */ ++ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x80000000 /* ACCEL_IRQ# */ ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ ++ MX6QDL_PAD_KEY_COL4__GPIO4_IO14 0x80000000 /* USBOTG_OC# */ ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ ++ MX6QDL_PAD_SD2_CMD__GPIO1_IO11 0x80000000 /* TOUCH_IRQ# */ ++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x80000000 /* SD3_DET# */ ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ status = "okay"; ++ ++ lvds-channel@1 { ++ fsl,data-mapping = "spwg"; ++ fsl,data-width = <18>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: hsd100pxn1 { ++ clock-frequency = <65000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hback-porch = <220>; ++ hfront-porch = <40>; ++ vback-porch = <21>; ++ vfront-porch = <7>; ++ hsync-len = <60>; ++ vsync-len = <10>; ++ }; ++ }; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio1 29 0>; ++ status = "okay"; ++ ++ eth1: sky2@8 { /* MAC/PHY on bus 8 */ ++ compatible = "marvell,sky2"; ++ }; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_2>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5_1>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg_1>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc3_2>; ++ cd-gpios = <&gpio7 0 0>; ++ vmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; +--- /dev/null ++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi +@@ -0,0 +1,457 @@ ++/* ++ * Copyright 2013 Gateworks Corporation ++ * ++ * The code contained herein is licensed under the GNU General Public ++ * License. You may obtain a copy of the GNU General Public License ++ * Version 2 or later at the following locations: ++ * ++ * http://www.opensource.org/licenses/gpl-license.html ++ * http://www.gnu.org/copyleft/gpl.html ++ */ ++ ++/ { ++ /* these are used by bootloader for disabling nodes */ ++ aliases { ++ can0 = &can1; ++ ethernet0 = &fec; ++ ethernet1 = ð1; ++ led0 = &led0; ++ led1 = &led1; ++ led2 = &led2; ++ nand = &gpmi; ++ sky2 = ð1; ++ ssi0 = &ssi1; ++ usb0 = &usbh1; ++ usb1 = &usbotg; ++ usdhc2 = &usdhc3; ++ }; ++ ++ chosen { ++ bootargs = "console=ttymxc1,115200"; ++ }; ++ ++ leds { ++ compatible = "gpio-leds"; ++ ++ led0: user1 { ++ label = "user1"; ++ gpios = <&gpio4 6 0>; /* 102 -> MX6_PANLEDG */ ++ default-state = "on"; ++ linux,default-trigger = "heartbeat"; ++ }; ++ ++ led1: user2 { ++ label = "user2"; ++ gpios = <&gpio4 7 0>; /* 103 -> MX6_PANLEDR */ ++ default-state = "off"; ++ }; ++ ++ led2: user3 { ++ label = "user3"; ++ gpios = <&gpio4 15 1>; /* 111 -> MX6_LOCLED# */ ++ default-state = "off"; ++ }; ++ }; ++ ++ memory { ++ reg = <0x10000000 0x40000000>; ++ }; ++ ++ pps { ++ compatible = "pps-gpio"; ++ gpios = <&gpio1 26 0>; ++ status = "okay"; ++ }; ++ ++ regulators { ++ compatible = "simple-bus"; ++ ++ reg_1p0v: 1p0v { ++ compatible = "regulator-fixed"; ++ regulator-name = "1P0V"; ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <1000000>; ++ regulator-always-on; ++ }; ++ ++ reg_3p3v: 3p3v { ++ compatible = "regulator-fixed"; ++ regulator-name = "3P3V"; ++ regulator-min-microvolt = <3300000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_h1_vbus: usb_h1_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_h1_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ regulator-always-on; ++ }; ++ ++ reg_usb_otg_vbus: usb_otg_vbus { ++ compatible = "regulator-fixed"; ++ regulator-name = "usb_otg_vbus"; ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5000000>; ++ gpio = <&gpio3 22 0>; ++ enable-active-high; ++ }; ++ }; ++ ++ sound { ++ compatible = "fsl,imx6q-sabrelite-sgtl5000", ++ "fsl,imx-audio-sgtl5000"; ++ model = "imx6q-sabrelite-sgtl5000"; ++ ssi-controller = <&ssi1>; ++ audio-codec = <&codec>; ++ audio-routing = ++ "MIC_IN", "Mic Jack", ++ "Mic Jack", "Mic Bias", ++ "Headphone Jack", "HP_OUT"; ++ mux-int-port = <1>; ++ mux-ext-port = <4>; ++ }; ++}; ++ ++&audmux { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_audmux_1>; /* AUD4<->sgtl5000 */ ++ status = "okay"; ++}; ++ ++&can1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_flexcan1_1>; ++ status = "okay"; ++}; ++ ++&fec { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_enet_1>; ++ phy-mode = "rgmii"; ++ phy-reset-gpios = <&gpio1 30 0>; ++ status = "okay"; ++}; ++ ++&gpmi { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_gpmi_nand_2>; ++ status = "okay"; ++}; ++ ++&i2c1 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c1_1>; ++ status = "okay"; ++ ++ eeprom1: eeprom@50 { ++ compatible = "atmel,24c02"; ++ reg = <0x50>; ++ pagesize = <16>; ++ }; ++ ++ eeprom2: eeprom@51 { ++ compatible = "atmel,24c02"; ++ reg = <0x51>; ++ pagesize = <16>; ++ }; ++ ++ eeprom3: eeprom@52 { ++ compatible = "atmel,24c02"; ++ reg = <0x52>; ++ pagesize = <16>; ++ }; ++ ++ eeprom4: eeprom@53 { ++ compatible = "atmel,24c02"; ++ reg = <0x53>; ++ pagesize = <16>; ++ }; ++ ++ gpio: pca9555@23 { ++ compatible = "nxp,pca9555"; ++ reg = <0x23>; ++ gpio-controller; ++ #gpio-cells = <2>; ++ }; ++ ++ hwmon: gsc@29 { ++ compatible = "gw,gsp"; ++ reg = <0x29>; ++ }; ++ ++ rtc: ds1672@68 { ++ compatible = "dallas,ds1672"; ++ reg = <0x68>; ++ }; ++}; ++ ++&i2c2 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c2_2>; ++ status = "okay"; ++ ++ pmic: pfuze100@08 { ++ compatible = "fsl,pfuze100"; ++ reg = <0x08>; ++ ++ regulators { ++ sw1a_reg: sw1ab { ++ regulator-min-microvolt = <300000>; ++ regulator-max-microvolt = <1875000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <6250>; ++ }; ++ ++ sw1c_reg: sw1c { ++ regulator-min-microvolt = <300000>; ++ regulator-max-microvolt = <1875000>; ++ regulator-boot-on; ++ regulator-always-on; ++ regulator-ramp-delay = <6250>; ++ }; ++ ++ sw2_reg: sw2 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3950000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3a_reg: sw3a { ++ regulator-min-microvolt = <400000>; ++ regulator-max-microvolt = <1975000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw3b_reg: sw3b { ++ regulator-min-microvolt = <400000>; ++ regulator-max-microvolt = <1975000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ sw4_reg: sw4 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ swbst_reg: swbst { ++ regulator-min-microvolt = <5000000>; ++ regulator-max-microvolt = <5150000>; ++ }; ++ ++ snvs_reg: vsnvs { ++ regulator-min-microvolt = <1000000>; ++ regulator-max-microvolt = <3000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vref_reg: vrefddr { ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ vgen1_reg: vgen1 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1550000>; ++ }; ++ ++ vgen2_reg: vgen2 { ++ regulator-min-microvolt = <800000>; ++ regulator-max-microvolt = <1550000>; ++ }; ++ ++ vgen3_reg: vgen3 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ }; ++ ++ vgen4_reg: vgen4 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vgen5_reg: vgen5 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ ++ vgen6_reg: vgen6 { ++ regulator-min-microvolt = <1800000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-always-on; ++ }; ++ }; ++ }; ++ ++ pciswitch: pex8609@3f { ++ compatible = "plx,pex8609"; ++ reg = <0x3f>; ++ }; ++ ++ pciclkgen: si52147@6b { ++ compatible = "sil,si52147"; ++ reg = <0x6b>; ++ }; ++}; ++ ++&i2c3 { ++ clock-frequency = <100000>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_i2c3_2>; ++ status = "okay"; ++ ++ accelerometer: fxos8700@1e { ++ compatible = "fsl,fxos8700"; ++ reg = <0x1e>; ++ }; ++ ++ codec: sgtl5000@0a { ++ compatible = "fsl,sgtl5000"; ++ reg = <0x0a>; ++ clocks = <&clks 201>; ++ VDDA-supply = <&sw4_reg>; ++ VDDIO-supply = <®_3p3v>; ++ }; ++ ++ hdmiin: adv7611@4c { ++ compatible = "adi,adv7611"; ++ reg = <0x4c>; ++ }; ++ ++ touchscreen: egalax_ts@04 { ++ compatible = "eeti,egalax_ts"; ++ reg = <0x04>; ++ interrupt-parent = <&gpio7>; ++ interrupts = <12 2>; /* gpio7_12 active low */ ++ wakeup-gpios = <&gpio7 12 0>; ++ }; ++ ++ videoout: adv7393@2a { ++ compatible = "adi,adv7393"; ++ reg = <0x2a>; ++ }; ++ ++ videoin: adv7180@20 { ++ compatible = "adi,adv7180"; ++ reg = <0x20>; ++ }; ++}; ++ ++&iomuxc { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_hog>; ++ ++ hog { ++ pinctrl_hog: hoggrp { ++ fsl,pins = < ++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x80000000 /* OTG_PWR_EN */ ++ MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x80000000 /* SPINOR_CS0# */ ++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x80000000 /* GPS_PPS */ ++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x80000000 /* PCIE IRQ */ ++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x80000000 /* PCIE RST */ ++ MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x000130b0 /* AUD4_MCK */ ++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x80000000 /* CAN_STBY */ ++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x80000000 /* TOUCH_IRQ# */ ++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x80000000 /* user1 led */ ++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x80000000 /* user2 led */ ++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x80000000 /* user3 led */ ++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x80000000 /* USBHUB_RST# */ ++ MX6QDL_PAD_SD1_DAT3__GPIO1_IO21 0x80000000 /* MIPI_DIO */ ++ >; ++ }; ++ }; ++}; ++ ++&ldb { ++ status = "okay"; ++ ++ lvds-channel@1 { ++ fsl,data-mapping = "spwg"; ++ fsl,data-width = <18>; ++ status = "okay"; ++ ++ display-timings { ++ native-mode = <&timing0>; ++ timing0: hsd100pxn1 { ++ clock-frequency = <65000000>; ++ hactive = <1024>; ++ vactive = <768>; ++ hback-porch = <220>; ++ hfront-porch = <40>; ++ vback-porch = <21>; ++ vfront-porch = <7>; ++ hsync-len = <60>; ++ vsync-len = <10>; ++ }; ++ }; ++ }; ++}; ++ ++&pcie { ++ reset-gpio = <&gpio1 29 0>; ++ status = "okay"; ++ ++ eth1: sky2@8 { /* MAC/PHY on bus 8 */ ++ compatible = "marvell,sky2"; ++ }; ++}; ++ ++&ssi1 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&ssi2 { ++ fsl,mode = "i2s-slave"; ++ status = "okay"; ++}; ++ ++&uart1 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart1_2>; ++ status = "okay"; ++}; ++ ++&uart2 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart2_3>; ++ status = "okay"; ++}; ++ ++&uart5 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_uart5_1>; ++ status = "okay"; ++}; ++ ++&usbotg { ++ vbus-supply = <®_usb_otg_vbus>; ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usbotg_1>; ++ disable-over-current; ++ status = "okay"; ++}; ++ ++&usbh1 { ++ vbus-supply = <®_usb_h1_vbus>; ++ status = "okay"; ++}; ++ ++&usdhc3 { ++ pinctrl-names = "default"; ++ pinctrl-0 = <&pinctrl_usdhc3_2>; ++ cd-gpios = <&gpio7 0 0>; ++ vmmc-supply = <®_3p3v>; ++ status = "okay"; ++}; diff --git a/target/linux/imx6/patches-3.12/0009-imx-add-PCI-fixup-for-PEX860X-on-Gateworks-board.patch b/target/linux/imx6/patches-3.12/0009-imx-add-PCI-fixup-for-PEX860X-on-Gateworks-board.patch new file mode 100644 index 0000000000..c5b7bbef5e --- /dev/null +++ b/target/linux/imx6/patches-3.12/0009-imx-add-PCI-fixup-for-PEX860X-on-Gateworks-board.patch @@ -0,0 +1,60 @@ +From 079441036b20d9f3d23d1e96f0681b99349de05a Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Tue, 22 Oct 2013 21:51:28 -0700 +Subject: [PATCH] imx: add PCI fixup for PEX860X on Gateworks board + +The PEX860X has GPIO's which are used for PCI Reset lines on the +Gateworks Ventana boards. The GPIO's need to be set as output +level high so as to allow the PCIe devices to come out of reset. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +--- + arch/arm/mach-imx/mach-imx6q.c | 30 ++++++++++++++++++++++++++++++ + 1 file changed, 30 insertions(+) + +--- a/arch/arm/mach-imx/mach-imx6q.c ++++ b/arch/arm/mach-imx/mach-imx6q.c +@@ -23,6 +24,7 @@ + #include <linux/of_irq.h> + #include <linux/of_platform.h> + #include <linux/opp.h> ++#include <linux/pci.h> + #include <linux/phy.h> + #include <linux/reboot.h> + #include <linux/regmap.h> +@@ -78,6 +80,34 @@ static int ksz9031rn_phy_fixup(struct phy_device *dev) + return 0; + } + ++/* ++ * fixup for PLX PEX8909 bridge to configure GPIO1-7 as output High ++ * as they are used for slots1-7 PERST# ++ */ ++static void ventana_pciesw_early_fixup(struct pci_dev *dev) ++{ ++ u32 dw; ++ ++ if (!of_machine_is_compatible("gw,ventana")) ++ return; ++ ++ if (dev->devfn != 0) ++ return; ++ ++ pci_read_config_dword(dev, 0x62c, &dw); ++ dw |= 0xaaa8; // GPIO1-7 outputs ++ pci_write_config_dword(dev, 0x62c, dw); ++ ++ pci_read_config_dword(dev, 0x644, &dw); ++ dw |= 0xfe; // GPIO1-7 output high ++ pci_write_config_dword(dev, 0x644, dw); ++ ++ msleep(100); ++} ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8609, ventana_pciesw_early_fixup); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8606, ventana_pciesw_early_fixup); ++DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8604, ventana_pciesw_early_fixup); ++ + static int ar8031_phy_fixup(struct phy_device *dev) + { + u16 val; diff --git a/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch b/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch new file mode 100644 index 0000000000..c8e4db1f89 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0010-ARM-imx6q-Add-PCIe-bits-to-GPR-syscon-definition.patch @@ -0,0 +1,44 @@ +From 8d6a35fb13406f87d926fffeee0d70360ce3077d Mon Sep 17 00:00:00 2001 +From: Sean Cross <xobs@kosagi.com> +Date: Thu, 26 Sep 2013 11:24:46 +0800 +Subject: [PATCH] ARM: imx6q: Add PCIe bits to GPR syscon definition + +PCIe requires additional bits be defined for GPR8 and GPR12. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +--- + include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 8 ++++++++ + 1 file changed, 8 insertions(+) + +diff --git a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +index b6bdcd6..e00e9f3 100644 +--- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h ++++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h +@@ -241,6 +241,12 @@ + + #define IMX6Q_GPR5_L2_CLK_STOP BIT(8) + ++#define IMX6Q_GPR8_TX_SWING_LOW (0x7f << 25) ++#define IMX6Q_GPR8_TX_SWING_FULL (0x7f << 18) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB (0x3f << 12) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB (0x3f << 6) ++#define IMX6Q_GPR8_TX_DEEMPH_GEN1 (0x3f << 0) ++ + #define IMX6Q_GPR9_TZASC2_BYP BIT(1) + #define IMX6Q_GPR9_TZASC1_BYP BIT(0) + +@@ -273,7 +279,9 @@ + #define IMX6Q_GPR12_ARMP_AHB_CLK_EN BIT(26) + #define IMX6Q_GPR12_ARMP_ATB_CLK_EN BIT(25) + #define IMX6Q_GPR12_ARMP_APB_CLK_EN BIT(24) ++#define IMX6Q_GPR12_DEVICE_TYPE (0xf << 12) + #define IMX6Q_GPR12_PCIE_CTL_2 BIT(10) ++#define IMX6Q_GPR12_LOS_LEVEL (0x1f << 4) + + #define IMX6Q_GPR13_SDMA_STOP_REQ BIT(30) + #define IMX6Q_GPR13_CAN2_STOP_REQ BIT(29) +-- +1.8.4.1 + diff --git a/target/linux/imx6/patches-3.12/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch b/target/linux/imx6/patches-3.12/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch new file mode 100644 index 0000000000..46a46606a5 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0011-PCI-imx6-Add-support-for-i.MX6-PCIe-controller.patch @@ -0,0 +1,620 @@ +From bb38919ec56e0758c3ae56dfc091dcde1391353e Mon Sep 17 00:00:00 2001 +From: Sean Cross <xobs@kosagi.com> +Date: Thu, 26 Sep 2013 11:24:47 +0800 +Subject: [PATCH] PCI: imx6: Add support for i.MX6 PCIe controller + +Add support for the PCIe port present on the i.MX6 family of controllers. +These use the Synopsis Designware core tied to their own PHY. + +Signed-off-by: Sean Cross <xobs@kosagi.com> +Signed-off-by: Shawn Guo <shawn.guo@linaro.org> +Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> +Acked-by: Sascha Hauer <s.hauer@pengutronix.de> +--- + drivers/pci/host/Kconfig | 6 + + drivers/pci/host/Makefile | 1 + + drivers/pci/host/pci-imx6.c | 575 +++++++++++++++++++++ + 4 files changed, 588 insertions(+), 1 deletion(-) + create mode 100644 drivers/pci/host/pci-imx6.c + +--- a/drivers/pci/host/Kconfig ++++ b/drivers/pci/host/Kconfig +@@ -15,6 +15,12 @@ config PCI_EXYNOS + select PCIEPORTBUS + select PCIE_DW + ++config PCI_IMX6 ++ bool "Freescale i.MX6 PCIe controller" ++ depends on SOC_IMX6Q ++ select PCIEPORTBUS ++ select PCIE_DW ++ + config PCI_TEGRA + bool "NVIDIA Tegra PCIe controller" + depends on ARCH_TEGRA +--- a/drivers/pci/host/Makefile ++++ b/drivers/pci/host/Makefile +@@ -1,4 +1,5 @@ + obj-$(CONFIG_PCIE_DW) += pcie-designware.o + obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o ++obj-$(CONFIG_PCI_IMX6) += pci-imx6.o + obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o + obj-$(CONFIG_PCI_TEGRA) += pci-tegra.o +--- /dev/null ++++ b/drivers/pci/host/pci-imx6.c +@@ -0,0 +1,575 @@ ++/* ++ * PCIe host controller driver for Freescale i.MX6 SoCs ++ * ++ * Copyright (C) 2013 Kosagi ++ * http://www.kosagi.com ++ * ++ * Author: Sean Cross <xobs@kosagi.com> ++ * ++ * This program is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU General Public License version 2 as ++ * published by the Free Software Foundation. ++ */ ++ ++#include <linux/clk.h> ++#include <linux/delay.h> ++#include <linux/gpio.h> ++#include <linux/kernel.h> ++#include <linux/mfd/syscon.h> ++#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h> ++#include <linux/module.h> ++#include <linux/of_gpio.h> ++#include <linux/pci.h> ++#include <linux/platform_device.h> ++#include <linux/regmap.h> ++#include <linux/resource.h> ++#include <linux/signal.h> ++#include <linux/types.h> ++ ++#include "pcie-designware.h" ++ ++#define to_imx6_pcie(x) container_of(x, struct imx6_pcie, pp) ++ ++struct imx6_pcie { ++ int reset_gpio; ++ int power_on_gpio; ++ int wake_up_gpio; ++ int disable_gpio; ++ struct clk *lvds_gate; ++ struct clk *sata_ref_100m; ++ struct clk *pcie_ref_125m; ++ struct clk *pcie_axi; ++ struct pcie_port pp; ++ struct regmap *iomuxc_gpr; ++ void __iomem *mem_base; ++}; ++ ++/* PCIe Port Logic registers (memory-mapped) */ ++#define PL_OFFSET 0x700 ++#define PCIE_PHY_DEBUG_R0 (PL_OFFSET + 0x28) ++#define PCIE_PHY_DEBUG_R1 (PL_OFFSET + 0x2c) ++ ++#define PCIE_PHY_CTRL (PL_OFFSET + 0x114) ++#define PCIE_PHY_CTRL_DATA_LOC 0 ++#define PCIE_PHY_CTRL_CAP_ADR_LOC 16 ++#define PCIE_PHY_CTRL_CAP_DAT_LOC 17 ++#define PCIE_PHY_CTRL_WR_LOC 18 ++#define PCIE_PHY_CTRL_RD_LOC 19 ++ ++#define PCIE_PHY_STAT (PL_OFFSET + 0x110) ++#define PCIE_PHY_STAT_ACK_LOC 16 ++ ++/* PHY registers (not memory-mapped) */ ++#define PCIE_PHY_RX_ASIC_OUT 0x100D ++ ++#define PHY_RX_OVRD_IN_LO 0x1005 ++#define PHY_RX_OVRD_IN_LO_RX_DATA_EN (1 << 5) ++#define PHY_RX_OVRD_IN_LO_RX_PLL_EN (1 << 3) ++ ++static int pcie_phy_poll_ack(void __iomem *dbi_base, int exp_val) ++{ ++ u32 val; ++ u32 max_iterations = 10; ++ u32 wait_counter = 0; ++ ++ do { ++ val = readl(dbi_base + PCIE_PHY_STAT); ++ val = (val >> PCIE_PHY_STAT_ACK_LOC) & 0x1; ++ wait_counter++; ++ ++ if (val == exp_val) ++ return 0; ++ ++ udelay(1); ++ } while (wait_counter < max_iterations); ++ ++ return -ETIMEDOUT; ++} ++ ++static int pcie_phy_wait_ack(void __iomem *dbi_base, int addr) ++{ ++ u32 val; ++ int ret; ++ ++ val = addr << PCIE_PHY_CTRL_DATA_LOC; ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ val |= (0x1 << PCIE_PHY_CTRL_CAP_ADR_LOC); ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ val = addr << PCIE_PHY_CTRL_DATA_LOC; ++ writel(val, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */ ++static int pcie_phy_read(void __iomem *dbi_base, int addr , int *data) ++{ ++ u32 val, phy_ctl; ++ int ret; ++ ++ ret = pcie_phy_wait_ack(dbi_base, addr); ++ if (ret) ++ return ret; ++ ++ /* assert Read signal */ ++ phy_ctl = 0x1 << PCIE_PHY_CTRL_RD_LOC; ++ writel(phy_ctl, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ val = readl(dbi_base + PCIE_PHY_STAT); ++ *data = val & 0xffff; ++ ++ /* deassert Read signal */ ++ writel(0x00, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ return 0; ++} ++ ++static int pcie_phy_write(void __iomem *dbi_base, int addr, int data) ++{ ++ u32 var; ++ int ret; ++ ++ /* write addr */ ++ /* cap addr */ ++ ret = pcie_phy_wait_ack(dbi_base, addr); ++ if (ret) ++ return ret; ++ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* capture data */ ++ var |= (0x1 << PCIE_PHY_CTRL_CAP_DAT_LOC); ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ /* deassert cap data */ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack de-assertion */ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ /* assert wr signal */ ++ var = 0x1 << PCIE_PHY_CTRL_WR_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack */ ++ ret = pcie_phy_poll_ack(dbi_base, 1); ++ if (ret) ++ return ret; ++ ++ /* deassert wr signal */ ++ var = data << PCIE_PHY_CTRL_DATA_LOC; ++ writel(var, dbi_base + PCIE_PHY_CTRL); ++ ++ /* wait for ack de-assertion */ ++ ret = pcie_phy_poll_ack(dbi_base, 0); ++ if (ret) ++ return ret; ++ ++ writel(0x0, dbi_base + PCIE_PHY_CTRL); ++ ++ return 0; ++} ++ ++/* Added for PCI abort handling */ ++static int imx6q_pcie_abort_handler(unsigned long addr, ++ unsigned int fsr, struct pt_regs *regs) ++{ ++ /* ++ * If it was an imprecise abort, then we need to correct the ++ * return address to be _after_ the instruction. ++ */ ++ if (fsr & (1 << 10)) ++ regs->ARM_pc += 4; ++ return 0; ++} ++ ++static int imx6_pcie_assert_core_reset(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16); ++ ++ gpio_set_value(imx6_pcie->reset_gpio, 0); ++ msleep(100); ++ gpio_set_value(imx6_pcie->reset_gpio, 1); ++ ++ return 0; ++} ++ ++static int imx6_pcie_deassert_core_reset(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ int ret; ++ ++ if (gpio_is_valid(imx6_pcie->power_on_gpio)) ++ gpio_set_value(imx6_pcie->power_on_gpio, 1); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1, ++ IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16); ++ ++ ret = clk_prepare_enable(imx6_pcie->sata_ref_100m); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable sata_ref_100m\n"); ++ goto err_sata_ref; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->pcie_ref_125m); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable pcie_ref_125m\n"); ++ goto err_pcie_ref; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->lvds_gate); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable lvds_gate\n"); ++ goto err_lvds_gate; ++ } ++ ++ ret = clk_prepare_enable(imx6_pcie->pcie_axi); ++ if (ret) { ++ dev_err(pp->dev, "unable to enable pcie_axi\n"); ++ goto err_pcie_axi; ++ } ++ ++ /* allow the clocks to stabilize */ ++ usleep_range(200, 500); ++ ++ return 0; ++ ++err_pcie_axi: ++ clk_disable_unprepare(imx6_pcie->lvds_gate); ++err_lvds_gate: ++ clk_disable_unprepare(imx6_pcie->pcie_ref_125m); ++err_pcie_ref: ++ clk_disable_unprepare(imx6_pcie->sata_ref_100m); ++err_sata_ref: ++ return ret; ++ ++} ++ ++static void imx6_pcie_init_phy(struct pcie_port *pp) ++{ ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 0 << 10); ++ ++ /* configure constant input signal to the pcie ctrl and phy */ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_DEVICE_TYPE, PCI_EXP_TYPE_ROOT_PORT << 12); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_LOS_LEVEL, 9 << 4); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN1, 0 << 0); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB, 0 << 6); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB, 20 << 12); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_SWING_FULL, 127 << 18); ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8, ++ IMX6Q_GPR8_TX_SWING_LOW, 127 << 25); ++} ++ ++static void imx6_pcie_host_init(struct pcie_port *pp) ++{ ++ int count = 0; ++ struct imx6_pcie *imx6_pcie = to_imx6_pcie(pp); ++ ++ imx6_pcie_assert_core_reset(pp); ++ ++ imx6_pcie_init_phy(pp); ++ ++ imx6_pcie_deassert_core_reset(pp); ++ ++ dw_pcie_setup_rc(pp); ++ ++ regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, ++ IMX6Q_GPR12_PCIE_CTL_2, 1 << 10); ++ ++ while (!dw_pcie_link_up(pp)) { ++ usleep_range(100, 1000); ++ count++; ++ if (count >= 10) { ++ dev_err(pp->dev, "phy link never came up\n"); ++ dev_dbg(pp->dev, ++ "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", ++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R0), ++ readl(pp->dbi_base + PCIE_PHY_DEBUG_R1)); ++ break; ++ } ++ } ++ ++ return; ++} ++ ++static int imx6_pcie_link_up(struct pcie_port *pp) ++{ ++ u32 rc, ltssm, rx_valid, temp; ++ ++ /* link is debug bit 36, debug register 1 starts at bit 32 */ ++ rc = readl(pp->dbi_base + PCIE_PHY_DEBUG_R1) & (0x1 << (36 - 32)); ++ if (rc) ++ return -EAGAIN; ++ ++ /* ++ * From L0, initiate MAC entry to gen2 if EP/RC supports gen2. ++ * Wait 2ms (LTSSM timeout is 24ms, PHY lock is ~5us in gen2). ++ * If (MAC/LTSSM.state == Recovery.RcvrLock) ++ * && (PHY/rx_valid==0) then pulse PHY/rx_reset. Transition ++ * to gen2 is stuck ++ */ ++ pcie_phy_read(pp->dbi_base, PCIE_PHY_RX_ASIC_OUT, &rx_valid); ++ ltssm = readl(pp->dbi_base + PCIE_PHY_DEBUG_R0) & 0x3F; ++ ++ if (rx_valid & 0x01) ++ return 0; ++ ++ if (ltssm != 0x0d) ++ return 0; ++ ++ dev_err(pp->dev, "transition to gen2 is stuck, reset PHY!\n"); ++ ++ pcie_phy_read(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, &temp); ++ temp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN ++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); ++ pcie_phy_write(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, temp); ++ ++ usleep_range(2000, 3000); ++ ++ pcie_phy_read(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, &temp); ++ temp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN ++ | PHY_RX_OVRD_IN_LO_RX_PLL_EN); ++ pcie_phy_write(pp->dbi_base, ++ PHY_RX_OVRD_IN_LO, temp); ++ ++ return 0; ++} ++ ++static struct pcie_host_ops imx6_pcie_host_ops = { ++ .link_up = imx6_pcie_link_up, ++ .host_init = imx6_pcie_host_init, ++}; ++ ++static int imx6_add_pcie_port(struct pcie_port *pp, ++ struct platform_device *pdev) ++{ ++ int ret; ++ ++ pp->irq = platform_get_irq(pdev, 0); ++ if (!pp->irq) { ++ dev_err(&pdev->dev, "failed to get irq\n"); ++ return -ENODEV; ++ } ++ ++ pp->root_bus_nr = -1; ++ pp->ops = &imx6_pcie_host_ops; ++ ++ spin_lock_init(&pp->conf_lock); ++ ret = dw_pcie_host_init(pp); ++ if (ret) { ++ dev_err(&pdev->dev, "failed to initialize host\n"); ++ return ret; ++ } ++ ++ return 0; ++} ++ ++static int __init imx6_pcie_probe(struct platform_device *pdev) ++{ ++ struct imx6_pcie *imx6_pcie; ++ struct pcie_port *pp; ++ struct device_node *np = pdev->dev.of_node; ++ struct resource *dbi_base; ++ int ret; ++ ++ imx6_pcie = devm_kzalloc(&pdev->dev, sizeof(*imx6_pcie), GFP_KERNEL); ++ if (!imx6_pcie) ++ return -ENOMEM; ++ ++ pp = &imx6_pcie->pp; ++ pp->dev = &pdev->dev; ++ ++ /* Added for PCI abort handling */ ++ hook_fault_code(16 + 6, imx6q_pcie_abort_handler, SIGBUS, 0, ++ "imprecise external abort"); ++ ++ dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); ++ if (!dbi_base) { ++ dev_err(&pdev->dev, "dbi_base memory resource not found\n"); ++ return -ENODEV; ++ } ++ ++ pp->dbi_base = devm_ioremap_resource(&pdev->dev, dbi_base); ++ if (IS_ERR(pp->dbi_base)) { ++ dev_err(&pdev->dev, "unable to remap dbi_base\n"); ++ ret = PTR_ERR(pp->dbi_base); ++ goto err; ++ } ++ ++ /* Fetch GPIOs */ ++ imx6_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); ++ if (!gpio_is_valid(imx6_pcie->reset_gpio)) { ++ dev_err(&pdev->dev, "no reset-gpio defined\n"); ++ ret = -ENODEV; ++ } ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->reset_gpio, ++ GPIOF_OUT_INIT_LOW, ++ "PCIe reset"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get reset gpio\n"); ++ goto err; ++ } ++ ++ imx6_pcie->power_on_gpio = of_get_named_gpio(np, "power-on-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->power_on_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->power_on_gpio, ++ GPIOF_OUT_INIT_LOW, ++ "PCIe power enable"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get power-on gpio\n"); ++ goto err; ++ } ++ } ++ ++ imx6_pcie->wake_up_gpio = of_get_named_gpio(np, "wake-up-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->wake_up_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->wake_up_gpio, ++ GPIOF_IN, ++ "PCIe wake up"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get wake-up gpio\n"); ++ goto err; ++ } ++ } ++ ++ imx6_pcie->disable_gpio = of_get_named_gpio(np, "disable-gpio", 0); ++ if (gpio_is_valid(imx6_pcie->disable_gpio)) { ++ ret = devm_gpio_request_one(&pdev->dev, ++ imx6_pcie->disable_gpio, ++ GPIOF_OUT_INIT_HIGH, ++ "PCIe disable endpoint"); ++ if (ret) { ++ dev_err(&pdev->dev, "unable to get disable-ep gpio\n"); ++ goto err; ++ } ++ } ++ ++ /* Fetch clocks */ ++ imx6_pcie->lvds_gate = devm_clk_get(&pdev->dev, "lvds_gate"); ++ if (IS_ERR(imx6_pcie->lvds_gate)) { ++ dev_err(&pdev->dev, ++ "lvds_gate clock select missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->lvds_gate); ++ goto err; ++ } ++ ++ imx6_pcie->sata_ref_100m = devm_clk_get(&pdev->dev, "sata_ref_100m"); ++ if (IS_ERR(imx6_pcie->sata_ref_100m)) { ++ dev_err(&pdev->dev, ++ "sata_ref_100m clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->sata_ref_100m); ++ goto err; ++ } ++ ++ imx6_pcie->pcie_ref_125m = devm_clk_get(&pdev->dev, "pcie_ref_125m"); ++ if (IS_ERR(imx6_pcie->pcie_ref_125m)) { ++ dev_err(&pdev->dev, ++ "pcie_ref_125m clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->pcie_ref_125m); ++ goto err; ++ } ++ ++ imx6_pcie->pcie_axi = devm_clk_get(&pdev->dev, "pcie_axi"); ++ if (IS_ERR(imx6_pcie->pcie_axi)) { ++ dev_err(&pdev->dev, ++ "pcie_axi clock source missing or invalid\n"); ++ ret = PTR_ERR(imx6_pcie->pcie_axi); ++ goto err; ++ } ++ ++ /* Grab GPR config register range */ ++ imx6_pcie->iomuxc_gpr = ++ syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr"); ++ if (IS_ERR(imx6_pcie->iomuxc_gpr)) { ++ dev_err(&pdev->dev, "unable to find iomuxc registers\n"); ++ ret = PTR_ERR(imx6_pcie->iomuxc_gpr); ++ goto err; ++ } ++ ++ ret = imx6_add_pcie_port(pp, pdev); ++ if (ret < 0) ++ goto err; ++ ++ platform_set_drvdata(pdev, imx6_pcie); ++ return 0; ++ ++err: ++ return ret; ++} ++ ++static const struct of_device_id imx6_pcie_of_match[] = { ++ { .compatible = "fsl,imx6q-pcie", }, ++ {}, ++}; ++MODULE_DEVICE_TABLE(of, imx6_pcie_of_match); ++ ++static struct platform_driver imx6_pcie_driver = { ++ .driver = { ++ .name = "imx6q-pcie", ++ .owner = THIS_MODULE, ++ .of_match_table = of_match_ptr(imx6_pcie_of_match), ++ }, ++}; ++ ++/* Freescale PCIe driver does not allow module unload */ ++ ++static int __init imx6_pcie_init(void) ++{ ++ return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); ++} ++module_init(imx6_pcie_init); ++ ++MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); ++MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); ++MODULE_LICENSE("GPL v2"); diff --git a/target/linux/imx6/patches-3.12/0021-pfuze100-allow-misprogrammed-id.patch b/target/linux/imx6/patches-3.12/0021-pfuze100-allow-misprogrammed-id.patch new file mode 100644 index 0000000000..a9399a9297 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0021-pfuze100-allow-misprogrammed-id.patch @@ -0,0 +1,20 @@ +--- a/drivers/regulator/pfuze100-regulator.c ++++ b/drivers/regulator/pfuze100-regulator.c +@@ -308,9 +308,14 @@ static int pfuze_identify(struct pfuze_c + if (ret) + return ret; + +- if (value & 0x0f) { +- dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); +- return -ENODEV; ++ switch (value & 0xf) { ++ case 0x0: ++ /* Freescale misprogrammed 1-3% of parts prior to week 8 of 2013 as ID=8 */ ++ case 0x8: ++ break; ++ default: ++ dev_warn(pfuze_chip->dev, "Illegal ID: %x\n", value); ++ return -ENODEV; + } + + ret = regmap_read(pfuze_chip->regmap, PFUZE100_REVID, &value); diff --git a/target/linux/imx6/patches-3.12/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch b/target/linux/imx6/patches-3.12/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch new file mode 100644 index 0000000000..de93ac8f42 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0030-PCI-imx6-remove-outbound-io-mem-ATU-region-mapping.patch @@ -0,0 +1,104 @@ +From: Tim Harvey <tharvey@gateworks.com> +Subject: [PATCH] PCI: imx6: remove outbound io/mem ATU region mapping + +The IMX6 iATU is used for address translation between the AXI bus +address space and PCI address space. This is used for type0 and type1 +config cycles but is not necessary for outbound io/mem regions. + +This patch removes the calls that inappropriately re-configures the ATU +viewport for outbound memory and IO after config cycles and removes them +altogether as they are not necessary. + +This resolves issues with PCI devices behind switches and has been tested with +a Gige device behind a PLX PEX860x switch. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/host/pcie-designware.c | 41 +++--------------------------------- + 1 file changed, 3 insertions(+), 38 deletions(-) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -43,7 +43,6 @@ + #define PCIE_ATU_VIEWPORT 0x900 + #define PCIE_ATU_REGION_INBOUND (0x1 << 31) + #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31) +-#define PCIE_ATU_REGION_INDEX1 (0x1 << 0) + #define PCIE_ATU_REGION_INDEX0 (0x0 << 0) + #define PCIE_ATU_CR1 0x904 + #define PCIE_ATU_TYPE_MEM (0x0 << 0) +@@ -264,8 +263,8 @@ static void dw_pcie_prog_viewport_cfg0(s + + static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev) + { +- /* Program viewport 1 : OUTBOUND : CFG1 */ +- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, ++ /* Program viewport 0 : OUTBOUND : CFG1 */ ++ dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, + PCIE_ATU_VIEWPORT); + dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); +@@ -275,38 +274,8 @@ static void dw_pcie_prog_viewport_cfg1(s + PCIE_ATU_LIMIT); + dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET); + dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET); +-} +- +-static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp) +-{ +- /* Program viewport 0 : OUTBOUND : MEM */ +- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0, +- PCIE_ATU_VIEWPORT); +- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1); +- dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); +- dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE); +- dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE); +- dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1, +- PCIE_ATU_LIMIT); +- dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET); +- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr), +- PCIE_ATU_UPPER_TARGET); +-} +- +-static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp) +-{ +- /* Program viewport 1 : OUTBOUND : IO */ +- dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1, +- PCIE_ATU_VIEWPORT); +- dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1); ++ dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1); + dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2); +- dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE); +- dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE); +- dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1, +- PCIE_ATU_LIMIT); +- dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET); +- dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr), +- PCIE_ATU_UPPER_TARGET); + } + + static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus, +@@ -322,11 +291,9 @@ static int dw_pcie_rd_other_conf(struct + if (bus->parent->number == pp->root_bus_nr) { + dw_pcie_prog_viewport_cfg0(pp, busdev); + ret = cfg_read(pp->va_cfg0_base + address, where, size, val); +- dw_pcie_prog_viewport_mem_outbound(pp); + } else { + dw_pcie_prog_viewport_cfg1(pp, busdev); + ret = cfg_read(pp->va_cfg1_base + address, where, size, val); +- dw_pcie_prog_viewport_io_outbound(pp); + } + + return ret; +@@ -345,11 +312,9 @@ static int dw_pcie_wr_other_conf(struct + if (bus->parent->number == pp->root_bus_nr) { + dw_pcie_prog_viewport_cfg0(pp, busdev); + ret = cfg_write(pp->va_cfg0_base + address, where, size, val); +- dw_pcie_prog_viewport_mem_outbound(pp); + } else { + dw_pcie_prog_viewport_cfg1(pp, busdev); + ret = cfg_write(pp->va_cfg1_base + address, where, size, val); +- dw_pcie_prog_viewport_io_outbound(pp); + } + + return ret; diff --git a/target/linux/imx6/patches-3.12/0031-PCI-imx6-init-must-be-early.patch b/target/linux/imx6/patches-3.12/0031-PCI-imx6-init-must-be-early.patch new file mode 100644 index 0000000000..0546d9c8fa --- /dev/null +++ b/target/linux/imx6/patches-3.12/0031-PCI-imx6-init-must-be-early.patch @@ -0,0 +1,24 @@ +From 8c8c877d8490c9d51210ee9e90d5f4d740f115c9 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Thu, 17 Oct 2013 15:55:47 -0700 +Subject: [PATCH 3/5] PCI: imx6: init must be early + +If driver init is not early the pcie port driver gets initalized +first and interrupts are not configured for the imx6 pcie driver. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/host/pci-imx6.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -568,7 +568,7 @@ static int __init imx6_pcie_init(void) + { + return platform_driver_probe(&imx6_pcie_driver, imx6_pcie_probe); + } +-module_init(imx6_pcie_init); ++fs_initcall(imx6_pcie_init); + + MODULE_AUTHOR("Sean Cross <xobs@kosagi.com>"); + MODULE_DESCRIPTION("Freescale i.MX6 PCIe host controller driver"); diff --git a/target/linux/imx6/patches-3.12/0032-PCI-imx6-fix-imprecise-abort-handler.patch b/target/linux/imx6/patches-3.12/0032-PCI-imx6-fix-imprecise-abort-handler.patch new file mode 100644 index 0000000000..5cef4114f4 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0032-PCI-imx6-fix-imprecise-abort-handler.patch @@ -0,0 +1,36 @@ +From 8590081d5328fe59d4f72aaadafb47fb91d8dc7c Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Thu, 17 Oct 2013 15:52:16 -0700 +Subject: [PATCH] PCI: imx6: fix imprecise abort handler + +An imprecise abort is triggered when a port behind a switch is accessed +and no device is present. At enumeration, imprecise aborts are not enabled +thus this ends up getting deferred until the kernel has completed init. At +that point we must not adjust PC - the handler must do nothing, but a handler +must exist. + +This fixes random crashes that occur right after freeing init. +This is against linux-pci/host-imx6. + +Acked-by: Marek Vasut <marex@denx.de> +Tested-by: Marek Vasut <marex@denx.de> +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/host/pci-imx6.c | 6 ------ + 1 file changed, 6 deletions(-) + +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -200,12 +200,6 @@ static int pcie_phy_write(void __iomem * + static int imx6q_pcie_abort_handler(unsigned long addr, + unsigned int fsr, struct pt_regs *regs) + { +- /* +- * If it was an imprecise abort, then we need to correct the +- * return address to be _after_ the instruction. +- */ +- if (fsr & (1 << 10)) +- regs->ARM_pc += 4; + return 0; + } + diff --git a/target/linux/imx6/patches-3.12/0033-PCI-imx6-increase-link-startup.patch b/target/linux/imx6/patches-3.12/0033-PCI-imx6-increase-link-startup.patch new file mode 100644 index 0000000000..a94a166908 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0033-PCI-imx6-increase-link-startup.patch @@ -0,0 +1,24 @@ +From 11e8d0ed8cc3b415767961555efc2885791a9391 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Thu, 17 Oct 2013 15:57:28 -0700 +Subject: [PATCH 4/5] PCI: imx6: increase link startup + +An increase link startup delay is required when certain PCI switches are +attached to the root complex. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/host/pci-imx6.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/pci/host/pci-imx6.c ++++ b/drivers/pci/host/pci-imx6.c +@@ -318,7 +318,7 @@ static void imx6_pcie_host_init(struct p + while (!dw_pcie_link_up(pp)) { + usleep_range(100, 1000); + count++; +- if (count >= 10) { ++ if (count >= 200) { + dev_err(pp->dev, "phy link never came up\n"); + dev_dbg(pp->dev, + "DEBUG_R0: 0x%08x, DEBUG_R1: 0x%08x\n", diff --git a/target/linux/imx6/patches-3.12/0034-PCI-imx6-swizzle-interrupts.patch b/target/linux/imx6/patches-3.12/0034-PCI-imx6-swizzle-interrupts.patch new file mode 100644 index 0000000000..348cc66495 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0034-PCI-imx6-swizzle-interrupts.patch @@ -0,0 +1,28 @@ +From 73a0e49b562da9b06e487fb8e051075543495be5 Mon Sep 17 00:00:00 2001 +From: Tim Harvey <tharvey@gateworks.com> +Date: Thu, 17 Oct 2013 15:50:48 -0700 +Subject: [PATCH 1/5] PCI: imx6: swizzle interrupts + + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +--- + drivers/pci/host/pcie-designware.c | 8 +++++++- + 1 file changed, 7 insertions(+), 1 deletion(-) + +--- a/drivers/pci/host/pcie-designware.c ++++ b/drivers/pci/host/pcie-designware.c +@@ -447,7 +447,13 @@ int dw_pcie_map_irq(const struct pci_dev + { + struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata); + +- return pp->irq; ++ switch (pin) { ++ case 1: return pp->irq - 1; ++ case 2: return pp->irq - 2; ++ case 3: return pp->irq - 3; ++ case 4: return pp->irq; ++ default: return -1; ++ } + } + + static struct hw_pci dw_pci = { diff --git a/target/linux/imx6/patches-3.12/0040-i2c-imx-retry-on-NAK.patch b/target/linux/imx6/patches-3.12/0040-i2c-imx-retry-on-NAK.patch new file mode 100644 index 0000000000..e876c6ed49 --- /dev/null +++ b/target/linux/imx6/patches-3.12/0040-i2c-imx-retry-on-NAK.patch @@ -0,0 +1,38 @@ +From: Tim Harvey <tharvey@gateworks.com> +Subject: [PATCH] i2c: imx: retry on NAK + +In case of busy i2c try again to get ACK. + +Signed-off-by: Tim Harvey <tharvey@gateworks.com> +Tested-by: Luka Perkov <luka@openwrt.org> +--- + drivers/i2c/busses/i2c-imx.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +--- a/drivers/i2c/busses/i2c-imx.c ++++ b/drivers/i2c/busses/i2c-imx.c +@@ -62,6 +62,7 @@ + + /* Default value */ + #define IMX_I2C_BIT_RATE 100000 /* 100kHz */ ++#define IMX_I2C_MAX_RETRIES 3 /* number of retries to attempt */ + + /* IMX I2C registers */ + #define IMX_I2C_IADR 0x00 /* i2c slave address */ +@@ -198,7 +199,7 @@ static int i2c_imx_acked(struct imx_i2c_ + { + if (readb(i2c_imx->base + IMX_I2C_I2SR) & I2SR_RXAK) { + dev_dbg(&i2c_imx->adapter.dev, "<%s> No ACK\n", __func__); +- return -EIO; /* No ACK */ ++ return -EAGAIN; /* try again */ + } + + dev_dbg(&i2c_imx->adapter.dev, "<%s> ACK received\n", __func__); +@@ -533,6 +534,7 @@ static int __init i2c_imx_probe(struct p + i2c_imx->adapter.dev.parent = &pdev->dev; + i2c_imx->adapter.nr = pdev->id; + i2c_imx->adapter.dev.of_node = pdev->dev.of_node; ++ i2c_imx->adapter.retries = IMX_I2C_MAX_RETRIES; + i2c_imx->base = base; + + pinctrl = devm_pinctrl_get_select_default(&pdev->dev); diff --git a/target/linux/imx6/patches-3.12/020-marvell-sky2-macdt.patch b/target/linux/imx6/patches-3.12/020-marvell-sky2-macdt.patch new file mode 100644 index 0000000000..96486b1518 --- /dev/null +++ b/target/linux/imx6/patches-3.12/020-marvell-sky2-macdt.patch @@ -0,0 +1,57 @@ +--- a/drivers/net/ethernet/marvell/sky2.c ++++ b/drivers/net/ethernet/marvell/sky2.c +@@ -44,6 +44,8 @@ + #include <linux/prefetch.h> + #include <linux/debugfs.h> + #include <linux/mii.h> ++#include <linux/of_device.h> ++#include <linux/of_net.h> + + #include <asm/irq.h> + +@@ -4748,6 +4750,7 @@ static struct net_device *sky2_init_netd + { + struct sky2_port *sky2; + struct net_device *dev = alloc_etherdev(sizeof(*sky2)); ++ unsigned char *iap, tmpaddr[ETH_ALEN]; + + if (!dev) + return NULL; +@@ -4802,8 +4805,36 @@ + + dev->features |= dev->hw_features; + ++ /* ++ * Try to get mac address in the following order: ++ * 1) from device tree data ++ * 2) from internal registers set by bootloader ++ */ ++ iap = NULL; ++ if (IS_ENABLED(CONFIG_OF)) { ++ struct device_node *np; ++ np = of_find_node_by_path("/aliases"); ++ if (np) { ++ const char *path = of_get_property(np, "sky2", NULL); ++ if (path) ++ np = of_find_node_by_path(path); ++ if (np) ++ path = of_get_mac_address(np); ++ if (path) ++ iap = (unsigned char *) path; ++ } ++ } ++ ++ /* ++ * 2) mac registers set by bootloader ++ */ ++ if (!iap || !is_valid_ether_addr(iap)) { ++ memcpy_fromio(&tmpaddr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); ++ iap = &tmpaddr[0]; ++ } ++ + /* read the mac address */ +- memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN); ++ memcpy(dev->dev_addr, iap, ETH_ALEN); + + return dev; + } diff --git a/target/linux/imx6/patches-3.12/100-bootargs.patch b/target/linux/imx6/patches-3.12/100-bootargs.patch new file mode 100644 index 0000000000..0954391203 --- /dev/null +++ b/target/linux/imx6/patches-3.12/100-bootargs.patch @@ -0,0 +1,11 @@ +--- a/arch/arm/boot/dts/imx6dl-wandboard.dts ++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts +@@ -19,4 +19,8 @@ + memory { + reg = <0x10000000 0x40000000>; + }; ++ ++ chosen { ++ bootargs = "console=ttymxc0,115200"; ++ }; + }; |