aboutsummaryrefslogtreecommitdiffstats
path: root/target/linux/imx/patches-5.4
diff options
context:
space:
mode:
Diffstat (limited to 'target/linux/imx/patches-5.4')
-rw-r--r--target/linux/imx/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch481
-rw-r--r--target/linux/imx/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch581
-rw-r--r--target/linux/imx/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch434
-rw-r--r--target/linux/imx/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch549
-rw-r--r--target/linux/imx/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch68
-rw-r--r--target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx-ventana-add-fxos8700-on-gateworks-boards.patch57
-rw-r--r--target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch54
-rw-r--r--target/linux/imx/patches-5.4/006-v5.8-ARM-dts-imx6qdl-gw552x-add-USB-OTG-support.patch45
-rw-r--r--target/linux/imx/patches-5.4/007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch76
-rw-r--r--target/linux/imx/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch69
-rw-r--r--target/linux/imx/patches-5.4/009-v5.8-ARM-dts-imx6qdl-gw5910-add-support-for-bcm4330-bt.patch82
-rw-r--r--target/linux/imx/patches-5.4/010-v5.8-ARM-dts-imx6qdl-gw5910-fix-wlan-regulator.patch33
-rw-r--r--target/linux/imx/patches-5.4/100-bootargs.patch11
-rw-r--r--target/linux/imx/patches-5.4/301-apalis-ixora-dts-leds.patch86
-rw-r--r--target/linux/imx/patches-5.4/302-apalis-ixora-dts-reset-button.patch76
15 files changed, 2702 insertions, 0 deletions
diff --git a/target/linux/imx/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch b/target/linux/imx/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch
new file mode 100644
index 0000000000..e830897704
--- /dev/null
+++ b/target/linux/imx/patches-5.4/001-ARM-dts-imx-Add-GW5907-board-support.patch
@@ -0,0 +1,481 @@
+From 125120298dc05bb55a8874f07aa3f4bb6056bfb3 Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Wed, 8 Jan 2020 07:44:21 -0800
+Subject: [PATCH 1/4] ARM: dts: imx: Add GW5907 board support
+
+The Gateworks GW5907 is an IMX6 SoC based single board computer with:
+ - IMX6Q or IMX6DL
+ - 32bit DDR3 DRAM
+ - FEC GbE Phy
+ - bi-color front-panel LED
+ - 256MB NAND boot device
+ - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
+ - Digital IO expander (pca9555)
+ - Joystick 12bit adc (ads1015)
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Reviewed-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/imx6dl-gw5907.dts | 14 ++
+ arch/arm/boot/dts/imx6q-gw5907.dts | 14 ++
+ arch/arm/boot/dts/imx6qdl-gw5907.dtsi | 399 ++++++++++++++++++++++++++++++++++
+ 4 files changed, 429 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6dl-gw5907.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-gw5907.dts
+ create mode 100644 arch/arm/boot/dts/imx6qdl-gw5907.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -418,6 +418,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6dl-gw560x.dtb \
+ imx6dl-gw5903.dtb \
+ imx6dl-gw5904.dtb \
++ imx6dl-gw5907.dtb \
+ imx6dl-hummingboard.dtb \
+ imx6dl-hummingboard-emmc-som-v15.dtb \
+ imx6dl-hummingboard-som-v15.dtb \
+@@ -489,6 +490,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6q-gw560x.dtb \
+ imx6q-gw5903.dtb \
+ imx6q-gw5904.dtb \
++ imx6q-gw5907.dtb \
+ imx6q-h100.dtb \
+ imx6q-hummingboard.dtb \
+ imx6q-hummingboard-emmc-som-v15.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6dl-gw5907.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-gw5907.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5907";
++ compatible = "gw,imx6dl-gw5907", "gw,ventana", "fsl,imx6dl";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-gw5907.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-gw5907.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5907";
++ compatible = "gw,imx6q-gw5907", "gw,ventana", "fsl,imx6q";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-gw5907.dtsi
+@@ -0,0 +1,398 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ /* these are used by bootloader for disabling nodes */
++ aliases {
++ led0 = &led0;
++ led1 = &led1;
++ nand = &gpmi;
++ usb0 = &usbh1;
++ usb1 = &usbotg;
++ };
++
++ chosen {
++ stdout-path = &uart2;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ led0: user1 {
++ label = "user1";
++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++
++ led1: user2 {
++ label = "user2";
++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
++ };
++ };
++
++ memory@10000000 {
++ device_type = "memory";
++ reg = <0x10000000 0x20000000>;
++ };
++
++ pps {
++ compatible = "pps-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pps>;
++ gpios = <&gpio1 26 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_5p0v: regulator-5p0v {
++ compatible = "regulator-fixed";
++ regulator-name = "5P0V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ reg_usb_otg_vbus: regulator-usb-otg-vbus {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_otg_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ gpio = <&gpio3 22 GPIO_ACTIVE_HIGH>;
++ enable-active-high;
++ };
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii-id";
++ phy-reset-gpios = <&gpio1 30 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "okay";
++};
++
++&hdmi {
++ ddc-i2c-bus = <&i2c3>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ gpio@23 {
++ compatible = "nxp,pca9555";
++ reg = <0x23>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ eeprom@50 {
++ compatible = "atmel,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ eeprom@51 {
++ compatible = "atmel,24c02";
++ reg = <0x51>;
++ pagesize = <16>;
++ };
++
++ eeprom@52 {
++ compatible = "atmel,24c02";
++ reg = <0x52>;
++ pagesize = <16>;
++ };
++
++ eeprom@53 {
++ compatible = "atmel,24c02";
++ reg = <0x53>;
++ pagesize = <16>;
++ };
++
++ rtc@68 {
++ compatible = "dallas,ds1672";
++ reg = <0x68>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ gpio@20 {
++ compatible = "nxp,pca9555";
++ reg = <0x20>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ adc@48 {
++ compatible = "ti,ads1015";
++ reg = <0x48>;
++ #address-cells = <1>;
++ #size-cells = <0>;
++
++ channel@4 {
++ reg = <4>;
++ ti,gain = <0>;
++ ti,datarate = <5>;
++ };
++
++ channel@5 {
++ reg = <5>;
++ ti,gain = <0>;
++ ti,datarate = <5>;
++ };
++
++ channel@6 {
++ reg = <6>;
++ ti,gain = <0>;
++ ti,datarate = <5>;
++ };
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++ status = "disabled";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++ status = "disabled";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
++ status = "disabled";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3>;
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usb_otg_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usbh1 {
++ status = "okay";
++};
++
++&wdog1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_wdog>;
++ fsl,ext-reset-output;
++};
++
++&iomuxc {
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
++ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
++ >;
++ };
++
++ pinctrl_pps: ppsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RXD1__GPIO1_IO26 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm2: pwm2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3: uart3grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x1b0b0
++ >;
++ };
++
++ pinctrl_wdog: wdoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
++ >;
++ };
++};
diff --git a/target/linux/imx/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch b/target/linux/imx/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch
new file mode 100644
index 0000000000..5c52bde70d
--- /dev/null
+++ b/target/linux/imx/patches-5.4/002-ARM-dts-imx-Add-GW5910-board-support.patch
@@ -0,0 +1,581 @@
+From a1fb69366bb16753f0fba6a891fbef5cdd97cfbe Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Wed, 8 Jan 2020 07:44:22 -0800
+Subject: [PATCH 2/4] ARM: dts: imx: Add GW5910 board support
+
+The Gateworks GW5910 is an IMX6 SoC based single board computer with:
+ - IMX6Q or IMX6DL
+ - 32bit DDR3 DRAM
+ - FEC GbE RJ45 front-panel
+ - 1x miniPCIe socket with PCI Gen2, USB2
+ - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
+ - 5V to 60V DC input barrel jack
+ - 3axis accelerometer (lis2de12)
+ - GPS (ublox ZOE-M8Q)
+ - bi-color front-panel LED
+ - 256MB NAND boot device
+ - microSD socket (with UHS-I support)
+ - user pushbutton
+ - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
+ - Dual-Band Wireless MCU (CC1352, UART/I2S interrconnect to IMX6)
+ - WiFi/Bluetooth/BLE module (Sterling-LSW, SDIO/UART interconnect to IMX6)
+ - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
+ - off-board SPI connector (1x chip-select)
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/imx6dl-gw5910.dts | 14 +
+ arch/arm/boot/dts/imx6q-gw5910.dts | 14 +
+ arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 491 ++++++++++++++++++++++++++++++++++
+ 4 files changed, 521 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6dl-gw5910.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-gw5910.dts
+ create mode 100644 arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -419,6 +419,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6dl-gw5903.dtb \
+ imx6dl-gw5904.dtb \
+ imx6dl-gw5907.dtb \
++ imx6dl-gw5910.dtb \
+ imx6dl-hummingboard.dtb \
+ imx6dl-hummingboard-emmc-som-v15.dtb \
+ imx6dl-hummingboard-som-v15.dtb \
+@@ -491,6 +492,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6q-gw5903.dtb \
+ imx6q-gw5904.dtb \
+ imx6q-gw5907.dtb \
++ imx6q-gw5910.dtb \
+ imx6q-h100.dtb \
+ imx6q-hummingboard.dtb \
+ imx6q-hummingboard-emmc-som-v15.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6dl-gw5910.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-gw5910.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5910";
++ compatible = "gw,imx6dl-gw5910", "gw,ventana", "fsl,imx6dl";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-gw5910.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-gw5910.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5910";
++ compatible = "gw,imx6q-gw5910", "gw,ventana", "fsl,imx6q";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+@@ -0,0 +1,489 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ /* these are used by bootloader for disabling nodes */
++ aliases {
++ led0 = &led0;
++ led1 = &led1;
++ led2 = &led2;
++ };
++
++ chosen {
++ stdout-path = &uart2;
++ };
++
++ memory@10000000 {
++ device_type = "memory";
++ reg = <0x10000000 0x20000000>;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ led0: user1 {
++ label = "user1";
++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++
++ led1: user2 {
++ label = "user2";
++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
++ };
++
++ led2: user3 {
++ label = "user3";
++ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
++ };
++ };
++
++ pps {
++ compatible = "pps-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pps>;
++ gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_5p0v: regulator-5p0v {
++ compatible = "regulator-fixed";
++ regulator-name = "5P0V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++
++ reg_wl: regulator-wl {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_reg_wl>;
++ compatible = "regulator-fixed";
++ regulator-name = "wl";
++ gpio = <&gpio1 5 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_bt: regulator-bt {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_reg_bt>;
++ compatible = "regulator-fixed";
++ regulator-name = "bt";
++ gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ startup-delay-us = <100>;
++ enable-active-high;
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++};
++
++
++&ecspi3 {
++ cs-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi3>;
++ status = "okay";
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii-id";
++ status = "okay";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ gpio@23 {
++ compatible = "nxp,pca9555";
++ reg = <0x23>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ eeprom@50 {
++ compatible = "atmel,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ eeprom@51 {
++ compatible = "atmel,24c02";
++ reg = <0x51>;
++ pagesize = <16>;
++ };
++
++ eeprom@52 {
++ compatible = "atmel,24c02";
++ reg = <0x52>;
++ pagesize = <16>;
++ };
++
++ eeprom@53 {
++ compatible = "atmel,24c02";
++ reg = <0x53>;
++ pagesize = <16>;
++ };
++
++ rtc@68 {
++ compatible = "dallas,ds1672";
++ reg = <0x68>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ accel@19 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_accel>;
++ compatible = "st,lis2de12";
++ reg = <0x19>;
++ st,drdy-int-pin = <1>;
++ interrupt-parent = <&gpio7>;
++ interrupts = <13 0>;
++ interrupt-names = "INT1";
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio3 20 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++ status = "disabled";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++ status = "disabled";
++};
++
++/* off-board RS232 */
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++/* serial console */
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++/* Sterling-LWB Bluetooth */
++&uart4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart4>;
++ uart-has-rtscts;
++ status = "okay";
++};
++
++/* GPS */
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_5p0v>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usbh1 {
++ status = "okay";
++};
++
++/* Sterling-LWB SDIO WiFi */
++&usdhc2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usdhc2>;
++ vmmc-supply = <&reg_3p3v>;
++ non-removable;
++ bus-width = <4>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
++ vmmc-supply = <&reg_3p3v>;
++ status = "okay";
++};
++
++&wdog1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_wdog>;
++ fsl,ext-reset-output;
++};
++
++&iomuxc {
++ pinctrl_accel: accelmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
++ >;
++ };
++
++ pinctrl_ecspi3: escpi3grp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
++ MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
++ MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
++ MX6QDL_PAD_DISP0_DAT3__GPIO4_IO24 0x100b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D20__GPIO3_IO20 0x1b0b0
++ >;
++ };
++
++ pinctrl_pps: ppsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_DISP_CLK__GPIO4_IO16 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm2: pwm2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_reg_bt: regbtgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
++ >;
++ };
++
++ pinctrl_reg_wl: regwlgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart4: uart4grp {
++ fsl,pins = <
++ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT13__UART4_RX_DATA 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT16__UART4_RTS_B 0x1b0b1
++ MX6QDL_PAD_CSI0_DAT17__UART4_CTS_B 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
++ >;
++ };
++
++ pinctrl_usdhc2: usdhc2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
++ MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
++ MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
++ MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
++ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
++ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x170b9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
++ >;
++ };
++
++ pinctrl_wdog: wdoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
++ >;
++ };
++};
diff --git a/target/linux/imx/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch b/target/linux/imx/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch
new file mode 100644
index 0000000000..32f344c588
--- /dev/null
+++ b/target/linux/imx/patches-5.4/003-ARM-dts-imx-Add-GW5913-board-support.patch
@@ -0,0 +1,434 @@
+From 169e12f99cf9d5fce752564f32fd8df96461de43 Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Wed, 8 Jan 2020 07:44:23 -0800
+Subject: [PATCH 3/4] ARM: dts: imx: Add GW5913 board support
+
+The Gateworks GW5913 is an IMX6 SoC based single board computer with:
+ - IMX6Q or IMX6DL
+ - 32bit DDR3 DRAM
+ - FEC GbE RJ45 front-panel
+ - 1x miniPCIe socket with PCI Gen2, USB2
+ - 1x miniPCIe socket with PCI Gen2, USB2, nanoSIM
+ - 6V to 60V DC input connector
+ - GPS (ublox ZOE-M8Q)
+ - bi-color front-panel LED
+ - 256MB NAND boot device
+ - nanoSIM socket
+ - user pushbutton
+ - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Reviewed-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/imx6dl-gw5913.dts | 14 ++
+ arch/arm/boot/dts/imx6q-gw5913.dts | 14 ++
+ arch/arm/boot/dts/imx6qdl-gw5913.dtsi | 348 ++++++++++++++++++++++++++++++++++
+ 4 files changed, 378 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6dl-gw5913.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-gw5913.dts
+ create mode 100644 arch/arm/boot/dts/imx6qdl-gw5913.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6dl-gw5904.dtb \
+ imx6dl-gw5907.dtb \
+ imx6dl-gw5910.dtb \
++ imx6dl-gw5913.dtb \
+ imx6dl-hummingboard.dtb \
+ imx6dl-hummingboard-emmc-som-v15.dtb \
+ imx6dl-hummingboard-som-v15.dtb \
+@@ -493,6 +494,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6q-gw5904.dtb \
+ imx6q-gw5907.dtb \
+ imx6q-gw5910.dtb \
++ imx6q-gw5913.dtb \
+ imx6q-h100.dtb \
+ imx6q-hummingboard.dtb \
+ imx6q-hummingboard-emmc-som-v15.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6dl-gw5913.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6dl.dtsi"
++#include "imx6qdl-gw5913.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5913";
++ compatible = "gw,imx6dl-gw5913", "gw,ventana", "fsl,imx6dl";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-gw5913.dts
+@@ -0,0 +1,14 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++
++#include "imx6q.dtsi"
++#include "imx6qdl-gw5913.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5913";
++ compatible = "gw,imx6q-gw5913", "gw,ventana", "fsl,imx6q";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-gw5913.dtsi
+@@ -0,0 +1,347 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ /* these are used by bootloader for disabling nodes */
++ aliases {
++ led0 = &led0;
++ led1 = &led1;
++ nand = &gpmi;
++ usb0 = &usbh1;
++ usb1 = &usbotg;
++ };
++
++ chosen {
++ stdout-path = &uart2;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ led0: user1 {
++ label = "user1";
++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++
++ led1: user2 {
++ label = "user2";
++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
++ };
++ };
++
++ memory@10000000 {
++ device_type = "memory";
++ reg = <0x10000000 0x20000000>;
++ };
++
++ pps {
++ compatible = "pps-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pps>;
++ gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_5p0v: regulator-5p0v {
++ compatible = "regulator-fixed";
++ regulator-name = "5P0V";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii-id";
++ status = "okay";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ gpio@23 {
++ compatible = "nxp,pca9555";
++ reg = <0x23>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ eeprom@50 {
++ compatible = "atmel,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ eeprom@51 {
++ compatible = "atmel,24c02";
++ reg = <0x51>;
++ pagesize = <16>;
++ };
++
++ eeprom@52 {
++ compatible = "atmel,24c02";
++ reg = <0x52>;
++ pagesize = <16>;
++ };
++
++ eeprom@53 {
++ compatible = "atmel,24c02";
++ reg = <0x53>;
++ pagesize = <16>;
++ };
++
++ rtc@68 {
++ compatible = "dallas,ds1672";
++ reg = <0x68>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio1 0 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++ status = "disabled";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++ status = "disabled";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
++ status = "disabled";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3>;
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ status = "okay";
++};
++
++&usbotg {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
++&usbh1 {
++ status = "okay";
++};
++
++&wdog1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_wdog>;
++ fsl,ext-reset-output;
++};
++
++&iomuxc {
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
++ MX6QDL_PAD_ENET_TXD0__GPIO1_IO30 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
++ >;
++ };
++
++ pinctrl_pps: ppsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm2: pwm2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart3: uart3grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
++ >;
++ };
++
++ pinctrl_wdog: wdoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
++ >;
++ };
++};
diff --git a/target/linux/imx/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch b/target/linux/imx/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch
new file mode 100644
index 0000000000..da733ff357
--- /dev/null
+++ b/target/linux/imx/patches-5.4/004-ARM-dts-imx-Add-GW5912-board-support.patch
@@ -0,0 +1,549 @@
+From 9a820b55817011f53771e6bfebae5fe059f0a534 Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Wed, 8 Jan 2020 07:44:24 -0800
+Subject: [PATCH 4/4] ARM: dts: imx: Add GW5912 board support
+
+The Gateworks GW5912 is an IMX6 SoC based single board computer with:
+ - IMX6Q or IMX6DL
+ - 32bit DDR3 DRAM
+ - GbE RJ45 front-panel
+ - 4x miniPCIe socket with PCI Gen2, USB2
+ - 1x miniPCIe socket with PCI Gen2, USB2, mSATA
+ - 1x miniPCIe socket with PCI Gen2, USB2, mezzanine
+ - 10V to 60V DC input barrel jack
+ - 3axis accelerometer (lis2de12)
+ - GPS (ublox ZOE-M8Q)
+ - bi-color front-panel LED
+ - 256MB NAND boot device
+ - nanoSIM/microSD socket (with UHS-I support)
+ - user pushbutton
+ - Gateworks System Controller (hwmon, pushbutton controller, EEPROM)
+ - CAN Bus transceiver (mcp2562)
+ - RS232 transceiver (1x UART with flow-control or 2x UART (build option)
+ - off-board SPI connector (1x chip-select)
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Reviewed-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/Makefile | 2 +
+ arch/arm/boot/dts/imx6dl-gw5912.dts | 13 +
+ arch/arm/boot/dts/imx6q-gw5912.dts | 13 +
+ arch/arm/boot/dts/imx6qdl-gw5912.dtsi | 461 ++++++++++++++++++++++++++++++++++
+ 4 files changed, 489 insertions(+)
+ create mode 100644 arch/arm/boot/dts/imx6dl-gw5912.dts
+ create mode 100644 arch/arm/boot/dts/imx6q-gw5912.dts
+ create mode 100644 arch/arm/boot/dts/imx6qdl-gw5912.dtsi
+
+--- a/arch/arm/boot/dts/Makefile
++++ b/arch/arm/boot/dts/Makefile
+@@ -420,6 +420,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6dl-gw5904.dtb \
+ imx6dl-gw5907.dtb \
+ imx6dl-gw5910.dtb \
++ imx6dl-gw5912.dtb \
+ imx6dl-gw5913.dtb \
+ imx6dl-hummingboard.dtb \
+ imx6dl-hummingboard-emmc-som-v15.dtb \
+@@ -494,6 +495,7 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
+ imx6q-gw5904.dtb \
+ imx6q-gw5907.dtb \
+ imx6q-gw5910.dtb \
++ imx6q-gw5912.dtb \
+ imx6q-gw5913.dtb \
+ imx6q-h100.dtb \
+ imx6q-hummingboard.dtb \
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6dl-gw5912.dts
+@@ -0,0 +1,13 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++#include "imx6dl.dtsi"
++#include "imx6qdl-gw5912.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 DualLite/Solo GW5912";
++ compatible = "gw,imx6dl-gw5912", "gw,ventana", "fsl,imx6dl";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6q-gw5912.dts
+@@ -0,0 +1,13 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++/dts-v1/;
++#include "imx6q.dtsi"
++#include "imx6qdl-gw5912.dtsi"
++
++/ {
++ model = "Gateworks Ventana i.MX6 Dual/Quad GW5912";
++ compatible = "gw,imx6q-gw5912", "gw,ventana", "fsl,imx6q";
++};
+--- /dev/null
++++ b/arch/arm/boot/dts/imx6qdl-gw5912.dtsi
+@@ -0,0 +1,459 @@
++// SPDX-License-Identifier: GPL-2.0
++/*
++ * Copyright 2019 Gateworks Corporation
++ */
++
++#include <dt-bindings/gpio/gpio.h>
++
++/ {
++ /* these are used by bootloader for disabling nodes */
++ aliases {
++ led0 = &led0;
++ led1 = &led1;
++ led2 = &led2;
++ nand = &gpmi;
++ usb0 = &usbh1;
++ usb1 = &usbotg;
++ };
++
++ chosen {
++ stdout-path = &uart2;
++ };
++
++ leds {
++ compatible = "gpio-leds";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpio_leds>;
++
++ led0: user1 {
++ label = "user1";
++ gpios = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDG */
++ default-state = "on";
++ linux,default-trigger = "heartbeat";
++ };
++
++ led1: user2 {
++ label = "user2";
++ gpios = <&gpio4 7 GPIO_ACTIVE_HIGH>; /* MX6_PANLEDR */
++ };
++
++ led2: user3 {
++ label = "user3";
++ gpios = <&gpio4 15 GPIO_ACTIVE_LOW>; /* MX6_LOCLED# */
++ };
++ };
++
++ memory@10000000 {
++ device_type = "memory";
++ reg = <0x10000000 0x40000000>;
++ };
++
++ pps {
++ compatible = "pps-gpio";
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pps>;
++ gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>;
++ };
++
++ reg_3p3v: regulator-3p3v {
++ compatible = "regulator-fixed";
++ regulator-name = "3P3V";
++ regulator-min-microvolt = <3300000>;
++ regulator-max-microvolt = <3300000>;
++ regulator-always-on;
++ };
++
++ reg_usb_vbus: regulator-5p0v {
++ compatible = "regulator-fixed";
++ regulator-name = "usb_vbus";
++ regulator-min-microvolt = <5000000>;
++ regulator-max-microvolt = <5000000>;
++ regulator-always-on;
++ };
++};
++
++&can1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_flexcan1>;
++ status = "okay";
++};
++
++&ecspi2 {
++ cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_ecspi2>;
++ status = "okay";
++};
++
++&fec {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_enet>;
++ phy-mode = "rgmii-id";
++ status = "okay";
++};
++
++&gpmi {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_gpmi_nand>;
++ status = "okay";
++};
++
++&i2c1 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c1>;
++ status = "okay";
++
++ gpio@23 {
++ compatible = "nxp,pca9555";
++ reg = <0x23>;
++ gpio-controller;
++ #gpio-cells = <2>;
++ };
++
++ eeprom@50 {
++ compatible = "atmel,24c02";
++ reg = <0x50>;
++ pagesize = <16>;
++ };
++
++ eeprom@51 {
++ compatible = "atmel,24c02";
++ reg = <0x51>;
++ pagesize = <16>;
++ };
++
++ eeprom@52 {
++ compatible = "atmel,24c02";
++ reg = <0x52>;
++ pagesize = <16>;
++ };
++
++ eeprom@53 {
++ compatible = "atmel,24c02";
++ reg = <0x53>;
++ pagesize = <16>;
++ };
++
++ rtc@68 {
++ compatible = "dallas,ds1672";
++ reg = <0x68>;
++ };
++};
++
++&i2c2 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c2>;
++ status = "okay";
++};
++
++&i2c3 {
++ clock-frequency = <100000>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_i2c3>;
++ status = "okay";
++
++ accel@19 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_accel>;
++ compatible = "st,lis2de12";
++ reg = <0x19>;
++ st,drdy-int-pin = <1>;
++ interrupt-parent = <&gpio7>;
++ interrupts = <13 0>;
++ interrupt-names = "INT1";
++ };
++};
++
++&pcie {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pcie>;
++ reset-gpio = <&gpio1 29 GPIO_ACTIVE_LOW>;
++ status = "okay";
++};
++
++&pwm1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm1>; /* MX6_DIO0 */
++ status = "disabled";
++};
++
++&pwm2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm2>; /* MX6_DIO1 */
++ status = "disabled";
++};
++
++&pwm3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm3>; /* MX6_DIO2 */
++ status = "disabled";
++};
++
++&pwm4 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_pwm4>; /* MX6_DIO3 */
++ status = "disabled";
++};
++
++&uart1 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart1>;
++ rts-gpios = <&gpio7 12 GPIO_ACTIVE_HIGH>;
++ status = "okay";
++};
++
++&uart2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart2>;
++ status = "okay";
++};
++
++&uart5 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart5>;
++ status = "okay";
++};
++
++&usbotg {
++ vbus-supply = <&reg_usb_vbus>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ dr_mode = "host";
++ status = "okay";
++};
++
++&usbh1 {
++ vbus-supply = <&reg_usb_vbus>;
++ status = "okay";
++};
++
++&usdhc3 {
++ pinctrl-names = "default", "state_100mhz", "state_200mhz";
++ pinctrl-0 = <&pinctrl_usdhc3>;
++ pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
++ pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
++ cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
++ vmmc-supply = <&reg_3p3v>;
++ no-1-8-v; /* firmware will remove if board revision supports */
++ status = "okay";
++};
++
++&wdog1 {
++ status = "disabled";
++};
++
++&wdog2 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_wdog>;
++ fsl,ext-reset-output;
++ status = "okay";
++};
++
++&iomuxc {
++ pinctrl_accel: accelmuxgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b1
++ >;
++ };
++
++ pinctrl_enet: enetgrp {
++ fsl,pins = <
++ MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
++ MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
++ MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
++ MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
++ MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
++ MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
++ MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b030
++ MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b030
++ MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b030
++ MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b030
++ MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b030
++ MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b030
++ MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
++ MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
++ MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
++ >;
++ };
++
++ pinctrl_ecspi2: escpi2grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1
++ MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1
++ MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1
++ MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1
++ >;
++ };
++
++ pinctrl_flexcan1: flexcan1grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1
++ MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b1
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x4001b0b0
++ >;
++ };
++
++ pinctrl_gpio_leds: gpioledsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL0__GPIO4_IO06 0x1b0b0
++ MX6QDL_PAD_KEY_ROW0__GPIO4_IO07 0x1b0b0
++ MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x1b0b0
++ >;
++ };
++
++ pinctrl_gpmi_nand: gpminandgrp {
++ fsl,pins = <
++ MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
++ MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
++ MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
++ MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
++ MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
++ MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
++ MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
++ MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
++ MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
++ MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
++ MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
++ MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
++ MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
++ MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
++ MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
++ >;
++ };
++
++ pinctrl_i2c1: i2c1grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
++ MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
++ MX6QDL_PAD_GPIO_4__GPIO1_IO04 0x0001b0b0
++ >;
++ };
++
++ pinctrl_i2c2: i2c2grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
++ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_i2c3: i2c3grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
++ MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
++ >;
++ };
++
++ pinctrl_pcie: pciegrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_TX_EN__GPIO1_IO28 0x1b0b0
++ MX6QDL_PAD_ENET_TXD1__GPIO1_IO29 0x1b0b0
++ >;
++ };
++
++ pinctrl_pps: ppsgrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm1: pwm1grp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm2: pwm2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT2__PWM2_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm3: pwm3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_pwm4: pwm4grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT2__PWM4_OUT 0x1b0b1
++ >;
++ };
++
++ pinctrl_uart1: uart1grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
++ MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x4001b0b1
++ >;
++ };
++
++ pinctrl_uart2: uart2grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT4__UART2_RX_DATA 0x1b0b1
++ MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b1
++ >;
++ };
++
++ pinctrl_uart5: uart5grp {
++ fsl,pins = <
++ MX6QDL_PAD_KEY_COL1__UART5_TX_DATA 0x1b0b1
++ MX6QDL_PAD_KEY_ROW1__UART5_RX_DATA 0x1b0b1
++ >;
++ };
++
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x13059
++ >;
++ };
++
++ pinctrl_usdhc3: usdhc3grp {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x17059 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x17059
++ >;
++ };
++
++ pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170b9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100b9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170b9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170b9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170b9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170b9
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170b9 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170b9
++ >;
++ };
++
++ pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
++ fsl,pins = <
++ MX6QDL_PAD_SD3_CMD__SD3_CMD 0x170f9
++ MX6QDL_PAD_SD3_CLK__SD3_CLK 0x100f9
++ MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x170f9
++ MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x170f9
++ MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x170f9
++ MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x170f9
++ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x170f9 /* CD */
++ MX6QDL_PAD_NANDF_CS1__SD3_VSELECT 0x170f9
++ >;
++ };
++
++ pinctrl_wdog: wdoggrp {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT3__WDOG2_B 0x1b0b0
++ >;
++ };
++};
diff --git a/target/linux/imx/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch b/target/linux/imx/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch
new file mode 100644
index 0000000000..f05c1f1ec1
--- /dev/null
+++ b/target/linux/imx/patches-5.4/005-v5.7-ARM-dts-imx6qdl-gw553x-add-lsm9ds1-iio-imu-magn-supp.patch
@@ -0,0 +1,68 @@
+From 62e7f0b553038e3a1a1b2b067dd1fbdacd634e37 Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Fri, 14 Feb 2020 13:02:41 -0800
+Subject: [PATCH] ARM: dts: imx6qdl-gw553x: add lsm9ds1 iio imu/magn support
+
+Add one node for the accel/gyro i2c device and another for the separate
+magnetometer device in the lsm9ds1.
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw553x.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw553x.dtsi
+@@ -173,6 +173,25 @@
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
++ magn@1c {
++ compatible = "st,lsm9ds1-magn";
++ reg = <0x1c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mag>;
++ interrupt-parent = <&gpio1>;
++ interrupts = <2 IRQ_TYPE_EDGE_RISING>;
++ };
++
++ imu@6a {
++ compatible = "st,lsm9ds1-imu";
++ reg = <0x6a>;
++ st,drdy-int-pin = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_imu>;
++ interrupt-parent = <&gpio7>;
++ interrupts = <13 IRQ_TYPE_LEVEL_HIGH>;
++ };
++
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ reg = <0x3c>;
+@@ -426,6 +445,12 @@
+ >;
+ };
+
++ pinctrl_imu: imugrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
++ >;
++ };
++
+ pinctrl_ipu1_csi0: ipu1csi0grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
+@@ -449,6 +474,12 @@
+ >;
+ };
+
++ pinctrl_mag: maggrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
++ >;
++ };
++
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0
diff --git a/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx-ventana-add-fxos8700-on-gateworks-boards.patch b/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx-ventana-add-fxos8700-on-gateworks-boards.patch
new file mode 100644
index 0000000000..1d8844fb0d
--- /dev/null
+++ b/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx-ventana-add-fxos8700-on-gateworks-boards.patch
@@ -0,0 +1,57 @@
+From 66d19a4f8d0fa7539f90cad64d793b4dac6f6e5d Mon Sep 17 00:00:00 2001
+From: Robert Jones <rjones@gateworks.com>
+Date: Fri, 14 Feb 2020 13:01:55 -0800
+Subject: [PATCH] ARM: dts: imx: ventana: add fxos8700 on gateworks boards
+
+Add fxos8700 iio imu entries for Gateworks ventana SBCs.
+
+Signed-off-by: Robert Jones <rjones@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw52xx.dtsi | 5 +++++
+ arch/arm/boot/dts/imx6qdl-gw53xx.dtsi | 5 +++++
+ arch/arm/boot/dts/imx6qdl-gw54xx.dtsi | 5 +++++
+ 3 files changed, 15 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw52xx.dtsi
+@@ -313,6 +313,11 @@
+ interrupts = <12 2>;
+ wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ };
++
++ accel@1e {
++ compatible = "nxp,fxos8700";
++ reg = <0x1e>;
++ };
+ };
+
+ &ldb {
+--- a/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw53xx.dtsi
+@@ -304,6 +304,11 @@
+ interrupts = <11 2>;
+ wakeup-gpios = <&gpio1 11 GPIO_ACTIVE_LOW>;
+ };
++
++ accel@1e {
++ compatible = "nxp,fxos8700";
++ reg = <0x1e>;
++ };
+ };
+
+ &ldb {
+--- a/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw54xx.dtsi
+@@ -361,6 +361,11 @@
+ interrupts = <12 2>;
+ wakeup-gpios = <&gpio7 12 GPIO_ACTIVE_LOW>;
+ };
++
++ accel@1e {
++ compatible = "nxp,fxos8700";
++ reg = <0x1e>;
++ };
+ };
+
+ &ldb {
diff --git a/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch b/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch
new file mode 100644
index 0000000000..72a98a2b15
--- /dev/null
+++ b/target/linux/imx/patches-5.4/006-v5.7-ARM-dts-imx6qdl-gw5910-add-CC1352-UART.patch
@@ -0,0 +1,54 @@
+From d2cf2f91ba5b6d7696b1870e28017a3e1a7a1bb8 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Fri, 28 Feb 2020 11:46:07 -0800
+Subject: [PATCH] ARM: dts: imx6qdl-gw5910: add CC1352 UART
+
+The GW5910-C revision adds a TI CC1352 connected to IMX UART4
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 25 +++++++++++++++++++++++++
+ 1 file changed, 25 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+@@ -218,6 +218,14 @@
+ status = "okay";
+ };
+
++/* cc1352 */
++&uart3 {
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_uart3>;
++ uart-has-rtscts;
++ status = "okay";
++};
++
+ /* Sterling-LWB Bluetooth */
+ &uart4 {
+ pinctrl-names = "default";
+@@ -409,6 +417,23 @@
+ >;
+ };
+
++ pinctrl_uart3: uart3grp {
++ fsl,pins = <
++ MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
++ MX6QDL_PAD_EIM_D23__UART3_RTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1
++ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x4001b0b1 /* DIO20 */
++ MX6QDL_PAD_DISP0_DAT11__GPIO5_IO05 0x4001b0b1 /* DIO14 */
++ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x4001b0b1 /* DIO15 */
++ MX6QDL_PAD_DISP0_DAT14__GPIO5_IO08 0x1b0b1 /* TMS */
++ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b1 /* TCK */
++ MX6QDL_PAD_DISP0_DAT16__GPIO5_IO10 0x1b0b1 /* TDO */
++ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x1b0b1 /* TDI */
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x4001b0b1 /* RST# */
++ >;
++ };
++
+ pinctrl_uart4: uart4grp {
+ fsl,pins = <
+ MX6QDL_PAD_CSI0_DAT12__UART4_TX_DATA 0x1b0b1
diff --git a/target/linux/imx/patches-5.4/006-v5.8-ARM-dts-imx6qdl-gw552x-add-USB-OTG-support.patch b/target/linux/imx/patches-5.4/006-v5.8-ARM-dts-imx6qdl-gw552x-add-USB-OTG-support.patch
new file mode 100644
index 0000000000..8d436be631
--- /dev/null
+++ b/target/linux/imx/patches-5.4/006-v5.8-ARM-dts-imx6qdl-gw552x-add-USB-OTG-support.patch
@@ -0,0 +1,45 @@
+From 957743b79b1ebb710f5498b61a212cebc302e685 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Wed, 29 Apr 2020 08:22:35 -0700
+Subject: [PATCH 01/20] ARM: dts: imx6qdl-gw552x: add USB OTG support
+
+The GW552x-B board revision adds USB OTG support.
+
+Enable the device-tree node and configure the OTG_ID pin.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw552x.dtsi | 14 ++++++++++++++
+ 1 file changed, 14 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw552x.dtsi
+@@ -258,6 +258,14 @@
+ status = "okay";
+ };
+
++&usbotg {
++ vbus-supply = <&reg_5p0v>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_usbotg>;
++ disable-over-current;
++ status = "okay";
++};
++
+ &wdog1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_wdog>;
+@@ -359,6 +367,12 @@
+ >;
+ };
+
++ pinctrl_usbotg: usbotggrp {
++ fsl,pins = <
++ MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x13059
++ >;
++ };
++
+ pinctrl_wdog: wdoggrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT8__WDOG1_B 0x1b0b0
diff --git a/target/linux/imx/patches-5.4/007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch b/target/linux/imx/patches-5.4/007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch
new file mode 100644
index 0000000000..537b6f4d67
--- /dev/null
+++ b/target/linux/imx/patches-5.4/007-v5.8-ARM-dts-imx6qdl-gw560x-add-lsm9ds1-iio-imu-magn-supp.patch
@@ -0,0 +1,76 @@
+From 9e72702a3d9a967edac02d8e937bce2b68b77814 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 12 May 2020 13:59:37 -0700
+Subject: [PATCH 05/20] ARM: dts: imx6qdl-gw560x: add lsm9ds1 iio imu/magn
+ support
+
+Add one node for the accel/gyro i2c device and another for the separate
+magnetometer device in the lsm9ds1.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw560x.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw560x.dtsi
+@@ -295,6 +295,15 @@
+ VDDIO-supply = <&reg_3p3v>;
+ };
+
++ magn@1c {
++ compatible = "st,lsm9ds1-magn";
++ reg = <0x1c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mag>;
++ interrupt-parent = <&gpio5>;
++ interrupts = <9 IRQ_TYPE_EDGE_RISING>;
++ };
++
+ tca8418: keypad@34 {
+ compatible = "ti,tca8418";
+ pinctrl-names = "default";
+@@ -389,6 +398,16 @@
+ };
+ };
+ };
++
++ imu@6a {
++ compatible = "st,lsm9ds1-imu";
++ reg = <0x6a>;
++ st,drdy-int-pin = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_imu>;
++ interrupt-parent = <&gpio5>;
++ interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ &i2c3 {
+@@ -609,6 +628,12 @@
+ >;
+ };
+
++ pinctrl_imu: imugrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT12__GPIO5_IO06 0x1b0b0
++ >;
++ };
++
+ pinctrl_keypad: keypadgrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT17__GPIO5_IO11 0x0001b0b0 /* KEYPAD_IRQ# */
+@@ -616,6 +641,12 @@
+ >;
+ };
+
++ pinctrl_mag: maggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT15__GPIO5_IO09 0x1b0b0
++ >;
++ };
++
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT10__GPIO4_IO31 0x1b0b0 /* PCI_RST# */
diff --git a/target/linux/imx/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch b/target/linux/imx/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch
new file mode 100644
index 0000000000..4d24b40535
--- /dev/null
+++ b/target/linux/imx/patches-5.4/008-v5.8-ARM-dts-imx6qdl-gw5904-add-lsm9ds1-iio-imu-magn-supp.patch
@@ -0,0 +1,69 @@
+From c8756cbad816954be912ba32277ccd55fe7acc01 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 12 May 2020 13:59:56 -0700
+Subject: [PATCH 06/20] ARM: dts: imx6qdl-gw5904: add lsm9ds1 iio imu/magn
+ support
+
+Add one node for the accel/gyro i2c device and another for the separate
+magnetometer device in the lsm9ds1.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw5904.dtsi | 31 +++++++++++++++++++++++++++++++
+ 1 file changed, 31 insertions(+)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw5904.dtsi
+@@ -248,6 +248,15 @@
+ pinctrl-0 = <&pinctrl_i2c2>;
+ status = "okay";
+
++ magn@1c {
++ compatible = "st,lsm9ds1-magn";
++ reg = <0x1c>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_mag>;
++ interrupt-parent = <&gpio5>;
++ interrupts = <17 IRQ_TYPE_EDGE_RISING>;
++ };
++
+ ltc3676: pmic@3c {
+ compatible = "lltc,ltc3676";
+ reg = <0x3c>;
+@@ -320,6 +329,16 @@
+ };
+ };
+ };
++
++ imu@6a {
++ compatible = "st,lsm9ds1-imu";
++ reg = <0x6a>;
++ st,drdy-int-pin = <1>;
++ pinctrl-names = "default";
++ pinctrl-0 = <&pinctrl_imu>;
++ interrupt-parent = <&gpio4>;
++ interrupts = <18 IRQ_TYPE_LEVEL_HIGH>;
++ };
+ };
+
+ &i2c3 {
+@@ -501,6 +520,18 @@
+ >;
+ };
+
++ pinctrl_imu: imugrp {
++ fsl,pins = <
++ MX6QDL_PAD_DI0_PIN2__GPIO4_IO18 0x1b0b0
++ >;
++ };
++
++ pinctrl_mag: maggrp {
++ fsl,pins = <
++ MX6QDL_PAD_DISP0_DAT23__GPIO5_IO17 0x1b0b0
++ >;
++ };
++
+ pinctrl_pcie: pciegrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */
diff --git a/target/linux/imx/patches-5.4/009-v5.8-ARM-dts-imx6qdl-gw5910-add-support-for-bcm4330-bt.patch b/target/linux/imx/patches-5.4/009-v5.8-ARM-dts-imx6qdl-gw5910-add-support-for-bcm4330-bt.patch
new file mode 100644
index 0000000000..545a6fddd5
--- /dev/null
+++ b/target/linux/imx/patches-5.4/009-v5.8-ARM-dts-imx6qdl-gw5910-add-support-for-bcm4330-bt.patch
@@ -0,0 +1,82 @@
+From d40edafe80569c5b4d8893c1cdd1060c54ef433c Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 12 May 2020 14:54:15 -0700
+Subject: [PATCH 07/20] ARM: dts: imx6qdl-gw5910: add support for bcm4330-bt
+
+The Sterling-LWB has a BCM4330 which has a UART based bluetooth
+HCI. Add support for binding to the bcm_hci driver to take care
+of handling the shutdown gpio and loading firmware.
+
+Because the shutdown gpio is more of an enable than a regulator
+go ahead and replace the regulator with a shutdown-gpio.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 32 ++++++++++++--------------------
+ 1 file changed, 12 insertions(+), 20 deletions(-)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+@@ -81,19 +81,6 @@
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+-
+- reg_bt: regulator-bt {
+- pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_reg_bt>;
+- compatible = "regulator-fixed";
+- regulator-name = "bt";
+- gpio = <&gpio1 2 GPIO_ACTIVE_HIGH>;
+- startup-delay-us = <100>;
+- enable-active-high;
+- regulator-min-microvolt = <3300000>;
+- regulator-max-microvolt = <3300000>;
+- regulator-always-on;
+- };
+ };
+
+
+@@ -229,9 +216,14 @@
+ /* Sterling-LWB Bluetooth */
+ &uart4 {
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_uart4>;
++ pinctrl-0 = <&pinctrl_uart4>,<&pinctrl_bten>;
+ uart-has-rtscts;
+ status = "okay";
++
++ bluetooth {
++ compatible = "brcm,bcm4330-bt";
++ shutdown-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
++ };
+ };
+
+ /* GPS */
+@@ -286,6 +278,12 @@
+ >;
+ };
+
++ pinctrl_bten: btengrp {
++ fsl,pins = <
++ MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
++ >;
++ };
++
+ pinctrl_ecspi3: escpi3grp {
+ fsl,pins = <
+ MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
+@@ -391,12 +389,6 @@
+ >;
+ };
+
+- pinctrl_reg_bt: regbtgrp {
+- fsl,pins = <
+- MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b1
+- >;
+- };
+-
+ pinctrl_reg_wl: regwlgrp {
+ fsl,pins = <
+ MX6QDL_PAD_GPIO_5__GPIO1_IO05 0x1b0b1
diff --git a/target/linux/imx/patches-5.4/010-v5.8-ARM-dts-imx6qdl-gw5910-fix-wlan-regulator.patch b/target/linux/imx/patches-5.4/010-v5.8-ARM-dts-imx6qdl-gw5910-fix-wlan-regulator.patch
new file mode 100644
index 0000000000..ce2fa2ee90
--- /dev/null
+++ b/target/linux/imx/patches-5.4/010-v5.8-ARM-dts-imx6qdl-gw5910-fix-wlan-regulator.patch
@@ -0,0 +1,33 @@
+From 4792ff641cc8993606013d27d84cda59d8cc76c5 Mon Sep 17 00:00:00 2001
+From: Tim Harvey <tharvey@gateworks.com>
+Date: Tue, 12 May 2020 15:02:34 -0700
+Subject: [PATCH 08/20] ARM: dts: imx6qdl-gw5910: fix wlan regulator
+
+Connect the wl_reg regulator to usdhc2 such that it can be enabled
+and disabled as needed. There is no need for this to be always-on.
+
+Signed-off-by: Tim Harvey <tharvey@gateworks.com>
+Signed-off-by: Shawn Guo <shawnguo@kernel.org>
+---
+ arch/arm/boot/dts/imx6qdl-gw5910.dtsi | 3 +--
+ 1 file changed, 1 insertion(+), 2 deletions(-)
+
+--- a/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
++++ b/arch/arm/boot/dts/imx6qdl-gw5910.dtsi
+@@ -79,7 +79,6 @@
+ enable-active-high;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+- regulator-always-on;
+ };
+ };
+
+@@ -249,7 +248,7 @@
+ &usdhc2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_usdhc2>;
+- vmmc-supply = <&reg_3p3v>;
++ vmmc-supply = <&reg_wl>;
+ non-removable;
+ bus-width = <4>;
+ status = "okay";
diff --git a/target/linux/imx/patches-5.4/100-bootargs.patch b/target/linux/imx/patches-5.4/100-bootargs.patch
new file mode 100644
index 0000000000..cf63a3bdb1
--- /dev/null
+++ b/target/linux/imx/patches-5.4/100-bootargs.patch
@@ -0,0 +1,11 @@
+--- a/arch/arm/boot/dts/imx6dl-wandboard.dts
++++ b/arch/arm/boot/dts/imx6dl-wandboard.dts
+@@ -16,4 +16,8 @@
+ device_type = "memory";
+ reg = <0x10000000 0x40000000>;
+ };
++
++ chosen {
++ bootargs = "console=ttymxc0,115200";
++ };
+ };
diff --git a/target/linux/imx/patches-5.4/301-apalis-ixora-dts-leds.patch b/target/linux/imx/patches-5.4/301-apalis-ixora-dts-leds.patch
new file mode 100644
index 0000000000..bae9df1734
--- /dev/null
+++ b/target/linux/imx/patches-5.4/301-apalis-ixora-dts-leds.patch
@@ -0,0 +1,86 @@
+arm: dts: apalis-ixora: Add status LEDs aliases
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+@@ -60,6 +60,10 @@
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
++ led-boot = &led_boot;
++ led-failsafe = &led_failsafe;
++ led-running = &led_running;
++ led-upgrade = &led_upgrade;
+ };
+
+ chosen {
+@@ -127,22 +131,22 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+- led4-green {
++ led_running: led4-green {
+ label = "LED_4_GREEN";
+ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+- led4-red {
++ led_upgrade: led4-red {
+ label = "LED_4_RED";
+ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+- led5-green {
++ led_boot: led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+- led5-red {
++ led_failsafe: led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+@@ -61,6 +61,10 @@
+ i2c2 = &i2c2;
+ rtc0 = &rtc_i2c;
+ rtc1 = &snvs_rtc;
++ led-boot = &led_boot;
++ led-failsafe = &led_failsafe;
++ led-running = &led_running;
++ led-upgrade = &led_upgrade;
+ };
+
+ chosen {
+@@ -128,22 +132,22 @@
+ pinctrl-names = "default";
+ pinctrl-0 = <&pinctrl_leds_ixora>;
+
+- led4-green {
++ led_running: led4-green {
+ label = "LED_4_GREEN";
+- gpios = <&gpio1 14 GPIO_ACTIVE_HIGH>;
++ gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>;
+ };
+
+- led4-red {
++ led_upgrade: led4-red {
+ label = "LED_4_RED";
+- gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>;
++ gpios = <&gpio1 21 GPIO_ACTIVE_HIGH>;
+ };
+
+- led5-green {
++ led_boot: led5-green {
+ label = "LED_5_GREEN";
+ gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>;
+ };
+
+- led5-red {
++ led_failsafe: led5-red {
+ label = "LED_5_RED";
+ gpios = <&gpio2 2 GPIO_ACTIVE_HIGH>;
+ };
diff --git a/target/linux/imx/patches-5.4/302-apalis-ixora-dts-reset-button.patch b/target/linux/imx/patches-5.4/302-apalis-ixora-dts-reset-button.patch
new file mode 100644
index 0000000000..f5afb66371
--- /dev/null
+++ b/target/linux/imx/patches-5.4/302-apalis-ixora-dts-reset-button.patch
@@ -0,0 +1,76 @@
+arm: dts: apalis-ixora: Add switch3 as reset button
+
+Signed-off-by: Petr Štetiar <ynezz@true.cz>
+
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora-v1.1.dts
+@@ -74,7 +74,7 @@
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_gpio_keys>;
++ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
+
+ wakeup {
+ label = "Wake-Up";
+@@ -83,6 +83,13 @@
+ debounce-interval = <10>;
+ wakeup-source;
+ };
++
++ reset {
++ label = "reset";
++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <10>;
++ };
+ };
+
+ lcd_display: disp0 {
+@@ -298,4 +305,10 @@
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
++
++ pinctrl_switch3_ixora: switch3ixora {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++ >;
++ };
+ };
+--- a/arch/arm/boot/dts/imx6q-apalis-ixora.dts
++++ b/arch/arm/boot/dts/imx6q-apalis-ixora.dts
+@@ -73,7 +73,7 @@
+ gpio-keys {
+ compatible = "gpio-keys";
+ pinctrl-names = "default";
+- pinctrl-0 = <&pinctrl_gpio_keys>;
++ pinctrl-0 = <&pinctrl_gpio_keys &pinctrl_switch3_ixora>;
+
+ wakeup {
+ label = "Wake-Up";
+@@ -82,6 +82,13 @@
+ debounce-interval = <10>;
+ wakeup-source;
+ };
++
++ reset {
++ label = "reset";
++ gpios = <&gpio1 16 GPIO_ACTIVE_LOW>;
++ linux,code = <KEY_RESTART>;
++ debounce-interval = <10>;
++ };
+ };
+
+ lcd_display: disp0 {
+@@ -299,4 +306,10 @@
+ MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
+ >;
+ };
++
++ pinctrl_switch3_ixora: switch3ixora {
++ fsl,pins = <
++ MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
++ >;
++ };
+ };