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Diffstat (limited to 'target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch')
-rw-r--r--target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch87
1 files changed, 0 insertions, 87 deletions
diff --git a/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch b/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch
deleted file mode 100644
index e1fcb15d5a..0000000000
--- a/target/linux/generic/pending-5.4/447-mtd-spinand-gigadevice-Add-support-for-GD5F4GQ4xC.patch
+++ /dev/null
@@ -1,87 +0,0 @@
-From 30521ccfb4597f91b9e5c7967acef9c7c85e58a8 Mon Sep 17 00:00:00 2001
-From: Hauke Mehrtens <hauke@hauke-m.de>
-Date: Wed, 12 Aug 2020 22:50:26 +0200
-Subject: [PATCH v2 447/447] mtd: spinand: gigadevice: Add support for
- GD5F4GQ4xC
-
-This adds support for the following 4GiB chips:
-GD5F4GQ4RCYIG 1.8V
-GD5F4GQ4UCYIG 3.3V
-
-The datasheet can be found here:
-https://www.novitronic.ch/sixcms/media.php/2/DS-00173-GD5F4GQ4xCxIG-Rev1.574695.pdf
-
-The GD5F4GQ4UCYIGT (3.3V) version is used on the Imagination
-Technologies Creator Ci40 (Marduk), the 1.8V version was not tested.
-
-This device only works in single SPI mode and not in dual or quad mode
-for me on this board.
-
-Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
----
- drivers/mtd/nand/spi/gigadevice.c | 49 +++++++++++++++++++++++++++++++
- 1 file changed, 49 insertions(+)
-
---- a/drivers/mtd/nand/spi/gigadevice.c
-+++ b/drivers/mtd/nand/spi/gigadevice.c
-@@ -132,6 +132,35 @@ static const struct mtd_ooblayout_ops gd
- .free = gd5fxgq4_variant2_ooblayout_free,
- };
-
-+static int gd5fxgq4xc_ooblayout_256_ecc(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
-+{
-+ if (section)
-+ return -ERANGE;
-+
-+ oobregion->offset = 128;
-+ oobregion->length = 128;
-+
-+ return 0;
-+}
-+
-+static int gd5fxgq4xc_ooblayout_256_free(struct mtd_info *mtd, int section,
-+ struct mtd_oob_region *oobregion)
-+{
-+ if (section)
-+ return -ERANGE;
-+
-+ oobregion->offset = 1;
-+ oobregion->length = 127;
-+
-+ return 0;
-+}
-+
-+static const struct mtd_ooblayout_ops gd5fxgq4xc_oob_256_ops = {
-+ .ecc = gd5fxgq4xc_ooblayout_256_ecc,
-+ .free = gd5fxgq4xc_ooblayout_256_free,
-+};
-+
- static int gd5fxgq4uexxg_ecc_get_status(struct spinand_device *spinand,
- u8 status)
- {
-@@ -222,6 +251,24 @@ static const struct spinand_info gigadev
- SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout,
- gd5fxgq4xa_ecc_get_status)),
-+ SPINAND_INFO("GD5F4GQ4RC", 0xa468,
-+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
-+ gd5fxgq4ufxxg_ecc_get_status)),
-+ SPINAND_INFO("GD5F4GQ4UC", 0xb468,
-+ NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
-+ NAND_ECCREQ(8, 512),
-+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f,
-+ &write_cache_variants,
-+ &update_cache_variants),
-+ SPINAND_HAS_QE_BIT,
-+ SPINAND_ECCINFO(&gd5fxgq4xc_oob_256_ops,
-+ gd5fxgq4ufxxg_ecc_get_status)),
- SPINAND_INFO("GD5F1GQ4UExxG", 0xd1,
- NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
- NAND_ECCREQ(8, 512),