diff options
Diffstat (limited to 'target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch')
| -rw-r--r-- | target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch | 67 |
1 files changed, 67 insertions, 0 deletions
diff --git a/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch new file mode 100644 index 0000000000..034cd2a8f0 --- /dev/null +++ b/target/linux/generic/pending-5.4/446-mtd-spinand-gigadevice-Add-QE-Bit.patch @@ -0,0 +1,67 @@ +From f72e99ada020a81e3e4ef79c0a83ede7e9d6c7b1 Mon Sep 17 00:00:00 2001 +From: Hauke Mehrtens <hauke@hauke-m.de> +Date: Sun, 16 Aug 2020 14:42:17 +0200 +Subject: [PATCH v2 446/447] mtd: spinand: gigadevice: Add QE Bit + +The following GigaDevice chips have the QE BIT in the feature flags, I +checked the datasheets, but did not try this. +* GD5F1GQ4xExxG +* GD5F1GQ4xFxxG +* GD5F1GQ4UAYIG +* GD5F4GQ4UAYIG + +The Quad operations like 0xEB mention that the QE bit has to be set. + +Fixes: c93c613214ac ("mtd: spinand: add support for GigaDevice GD5FxGQ4xA") +Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> +--- + drivers/mtd/nand/spi/gigadevice.c | 10 +++++----- + 1 file changed, 5 insertions(+), 5 deletions(-) + +--- a/drivers/mtd/nand/spi/gigadevice.c ++++ b/drivers/mtd/nand/spi/gigadevice.c +@@ -201,7 +201,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F2GQ4xA", 0xF2, +@@ -210,7 +210,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F4GQ4xA", 0xF4, +@@ -219,7 +219,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4xa_ooblayout, + gd5fxgq4xa_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UExxG", 0xd1, +@@ -228,7 +228,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4uexxg_ecc_get_status)), + SPINAND_INFO("GD5F1GQ4UFxxG", 0xb148, +@@ -237,7 +237,7 @@ static const struct spinand_info gigadev + SPINAND_INFO_OP_VARIANTS(&read_cache_variants_f, + &write_cache_variants, + &update_cache_variants), +- 0, ++ SPINAND_HAS_QE_BIT, + SPINAND_ECCINFO(&gd5fxgq4_variant2_ooblayout, + gd5fxgq4ufxxg_ecc_get_status)), + }; |