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-rw-r--r--target/linux/generic/patches-3.18/020-ssb_update.patch9
1 files changed, 5 insertions, 4 deletions
diff --git a/target/linux/generic/patches-3.18/020-ssb_update.patch b/target/linux/generic/patches-3.18/020-ssb_update.patch
index 7afba07763..f94d160fc6 100644
--- a/target/linux/generic/patches-3.18/020-ssb_update.patch
+++ b/target/linux/generic/patches-3.18/020-ssb_update.patch
@@ -78,18 +78,19 @@
}
--- a/drivers/ssb/driver_pcicore.c
+++ b/drivers/ssb/driver_pcicore.c
-@@ -357,6 +357,15 @@ static void ssb_pcicore_init_hostmode(st
+@@ -357,6 +357,16 @@ static void ssb_pcicore_init_hostmode(st
pcicore_write32(pc, SSB_PCICORE_SBTOPCI2,
SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA);
+ /*
+ * Accessing PCI config without a proper delay after devices reset (not
-+ * GPIO reset) was causing reboots on WRT300N v1.0.
++ * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704).
+ * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it
+ * completely. Flushing all writes was also tested but with no luck.
++ * The same problem was reported for WRT350N v1 (BCM4705), so we just
++ * sleep here unconditionally.
+ */
-+ if (pc->dev->bus->chip_id == 0x4704)
-+ usleep_range(1000, 2000);
++ usleep_range(1000, 2000);
+
/* Enable PCI bridge BAR0 prefetch and burst */
val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;