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-rw-r--r--target/linux/generic/patches-3.10/001-Revert-MIPS-microMIPS-Support-dynamic-ASID-sizing.patch82
1 files changed, 82 insertions, 0 deletions
diff --git a/target/linux/generic/patches-3.10/001-Revert-MIPS-microMIPS-Support-dynamic-ASID-sizing.patch b/target/linux/generic/patches-3.10/001-Revert-MIPS-microMIPS-Support-dynamic-ASID-sizing.patch
new file mode 100644
index 0000000000..7a44a620ec
--- /dev/null
+++ b/target/linux/generic/patches-3.10/001-Revert-MIPS-microMIPS-Support-dynamic-ASID-sizing.patch
@@ -0,0 +1,82 @@
+From 8ea6cd7af124ad070b44a7f60e225e45e3f38f79 Mon Sep 17 00:00:00 2001
+From: David Daney <david.daney@cavium.com>
+Date: Mon, 13 May 2013 13:56:43 -0700
+Subject: [PATCH 1/3] Revert "MIPS: microMIPS: Support dynamic ASID sizing."
+
+This reverts commit f6b06d9361a008afb93b97fb3683a6e92d69d0f4.
+
+The next revert depends on this one, so this has to go too.
+
+Signed-off-by: David Daney <david.daney@cavium.com>
+Cc: linux-mips@linux-mips.org
+Cc: linux-kernel@vger.kernel.org
+Cc: "Steven J. Hill" <Steven.Hill@imgtec.com>
+Cc: David Daney <david.daney@cavium.com>
+Patchwork: https://patchwork.linux-mips.org/patch/5241/
+Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
+---
+ arch/mips/mm/tlbex.c | 34 ++--------------------------------
+ 1 file changed, 2 insertions(+), 32 deletions(-)
+
+--- a/arch/mips/mm/tlbex.c
++++ b/arch/mips/mm/tlbex.c
+@@ -309,32 +309,13 @@ static int check_for_high_segbits __cpui
+ static void __cpuinit insn_fixup(unsigned int **start, unsigned int **stop,
+ unsigned int i_const)
+ {
+- unsigned int **p;
++ unsigned int **p, *ip;
+
+ for (p = start; p < stop; p++) {
+-#ifndef CONFIG_CPU_MICROMIPS
+- unsigned int *ip;
+-
+ ip = *p;
+ *ip = (*ip & 0xffff0000) | i_const;
+-#else
+- unsigned short *ip;
+-
+- ip = ((unsigned short *)((unsigned int)*p - 1));
+- if ((*ip & 0xf000) == 0x4000) {
+- *ip &= 0xfff1;
+- *ip |= (i_const << 1);
+- } else if ((*ip & 0xf000) == 0x6000) {
+- *ip &= 0xfff1;
+- *ip |= ((i_const >> 2) << 1);
+- } else {
+- ip++;
+- *ip = i_const;
+- }
+-#endif
+- local_flush_icache_range((unsigned long)ip,
+- (unsigned long)ip + sizeof(*ip));
+ }
++ local_flush_icache_range((unsigned long)*p, (unsigned long)((*p) + 1));
+ }
+
+ #define asid_insn_fixup(section, const) \
+@@ -354,14 +335,6 @@ static void __cpuinit setup_asid(unsigne
+ extern asmlinkage void handle_ri_rdhwr_vivt(void);
+ unsigned long *vivt_exc;
+
+-#ifdef CONFIG_CPU_MICROMIPS
+- /*
+- * Worst case optimised microMIPS addiu instructions support
+- * only a 3-bit immediate value.
+- */
+- if(inc > 7)
+- panic("Invalid ASID increment value!");
+-#endif
+ asid_insn_fixup(__asid_inc, inc);
+ asid_insn_fixup(__asid_mask, mask);
+ asid_insn_fixup(__asid_version_mask, version_mask);
+@@ -369,9 +342,6 @@ static void __cpuinit setup_asid(unsigne
+
+ /* Patch up the 'handle_ri_rdhwr_vivt' handler. */
+ vivt_exc = (unsigned long *) &handle_ri_rdhwr_vivt;
+-#ifdef CONFIG_CPU_MICROMIPS
+- vivt_exc = (unsigned long *)((unsigned long) vivt_exc - 1);
+-#endif
+ vivt_exc++;
+ *vivt_exc = (*vivt_exc & ~mask) | mask;
+