diff options
Diffstat (limited to 'target/linux/generic/patches-2.6.33/975-ssb_update.patch')
| -rw-r--r-- | target/linux/generic/patches-2.6.33/975-ssb_update.patch | 644 |
1 files changed, 644 insertions, 0 deletions
diff --git a/target/linux/generic/patches-2.6.33/975-ssb_update.patch b/target/linux/generic/patches-2.6.33/975-ssb_update.patch new file mode 100644 index 0000000000..fbc8f517b0 --- /dev/null +++ b/target/linux/generic/patches-2.6.33/975-ssb_update.patch @@ -0,0 +1,644 @@ +--- a/drivers/ssb/driver_chipcommon.c ++++ b/drivers/ssb/driver_chipcommon.c +@@ -233,6 +233,8 @@ void ssb_chipcommon_init(struct ssb_chip + { + if (!cc->dev) + return; /* We don't have a ChipCommon */ ++ if (cc->dev->id.revision >= 11) ++ cc->status = chipco_read32(cc, SSB_CHIPCO_CHIPSTAT); + ssb_pmu_init(cc); + chipco_powercontrol_init(cc); + ssb_chipco_set_clockmode(cc, SSB_CLKMODE_FAST); +@@ -370,6 +372,7 @@ u32 ssb_chipco_gpio_control(struct ssb_c + { + return chipco_write32_masked(cc, SSB_CHIPCO_GPIOCTL, mask, value); + } ++EXPORT_SYMBOL(ssb_chipco_gpio_control); + + u32 ssb_chipco_gpio_intmask(struct ssb_chipcommon *cc, u32 mask, u32 value) + { +--- a/drivers/ssb/driver_chipcommon_pmu.c ++++ b/drivers/ssb/driver_chipcommon_pmu.c +@@ -332,6 +332,12 @@ static void ssb_pmu_pll_init(struct ssb_ + case 0x5354: + ssb_pmu0_pllinit_r0(cc, crystalfreq); + break; ++ case 0x4322: ++ if (cc->pmu.rev == 2) { ++ chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A); ++ chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0); ++ } ++ break; + default: + ssb_printk(KERN_ERR PFX + "ERROR: PLL init unknown for device %04X\n", +@@ -417,6 +423,7 @@ static void ssb_pmu_resources_init(struc + + switch (bus->chip_id) { + case 0x4312: ++ case 0x4322: + /* We keep the default settings: + * min_msk = 0xCBB + * max_msk = 0x7FFFF +--- a/drivers/ssb/driver_mipscore.c ++++ b/drivers/ssb/driver_mipscore.c +@@ -270,7 +270,6 @@ void ssb_mipscore_init(struct ssb_mipsco + set_irq(dev, irq++); + } + break; +- /* fallthrough */ + case SSB_DEV_PCI: + case SSB_DEV_ETHERNET: + case SSB_DEV_ETHERNET_GBIT: +@@ -281,6 +280,10 @@ void ssb_mipscore_init(struct ssb_mipsco + set_irq(dev, irq++); + break; + } ++ /* fallthrough */ ++ case SSB_DEV_EXTIF: ++ set_irq(dev, 0); ++ break; + } + } + ssb_dprintk(KERN_INFO PFX "after irq reconfiguration\n"); +--- a/drivers/ssb/driver_pcicore.c ++++ b/drivers/ssb/driver_pcicore.c +@@ -246,20 +246,12 @@ static struct pci_controller ssb_pcicore + .pci_ops = &ssb_pcicore_pciops, + .io_resource = &ssb_pcicore_io_resource, + .mem_resource = &ssb_pcicore_mem_resource, +- .mem_offset = 0x24000000, + }; + +-static u32 ssb_pcicore_pcibus_iobase = 0x100; +-static u32 ssb_pcicore_pcibus_membase = SSB_PCI_DMA; +- + /* This function is called when doing a pci_enable_device(). + * We must first check if the device is a device on the PCI-core bridge. */ + int ssb_pcicore_plat_dev_init(struct pci_dev *d) + { +- struct resource *res; +- int pos, size; +- u32 *base; +- + if (d->bus->ops != &ssb_pcicore_pciops) { + /* This is not a device on the PCI-core bridge. */ + return -ENODEV; +@@ -268,27 +260,6 @@ int ssb_pcicore_plat_dev_init(struct pci + ssb_printk(KERN_INFO "PCI: Fixing up device %s\n", + pci_name(d)); + +- /* Fix up resource bases */ +- for (pos = 0; pos < 6; pos++) { +- res = &d->resource[pos]; +- if (res->flags & IORESOURCE_IO) +- base = &ssb_pcicore_pcibus_iobase; +- else +- base = &ssb_pcicore_pcibus_membase; +- res->flags |= IORESOURCE_PCI_FIXED; +- if (res->end) { +- size = res->end - res->start + 1; +- if (*base & (size - 1)) +- *base = (*base + size) & ~(size - 1); +- res->start = *base; +- res->end = res->start + size - 1; +- *base += size; +- pci_write_config_dword(d, PCI_BASE_ADDRESS_0 + (pos << 2), res->start); +- } +- /* Fix up PCI bridge BAR0 only */ +- if (d->bus->number == 0 && PCI_SLOT(d->devfn) == 0) +- break; +- } + /* Fix up interrupt lines */ + d->irq = ssb_mips_irq(extpci_core->dev) + 2; + pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); +--- a/drivers/ssb/main.c ++++ b/drivers/ssb/main.c +@@ -833,6 +833,9 @@ int ssb_bus_pcibus_register(struct ssb_b + if (!err) { + ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on " + "PCI device %s\n", dev_name(&host_pci->dev)); ++ } else { ++ ssb_printk(KERN_ERR PFX "Failed to register PCI version" ++ " of SSB with error %d\n", err); + } + + return err; +--- a/drivers/ssb/pci.c ++++ b/drivers/ssb/pci.c +@@ -167,7 +167,7 @@ err_pci: + } + + /* Get the word-offset for a SSB_SPROM_XXX define. */ +-#define SPOFF(offset) (((offset) - SSB_SPROM_BASE) / sizeof(u16)) ++#define SPOFF(offset) ((offset) / sizeof(u16)) + /* Helper to extract some _offset, which is one of the SSB_SPROM_XXX defines. */ + #define SPEX16(_outvar, _offset, _mask, _shift) \ + out->_outvar = ((in[SPOFF(_offset)] & (_mask)) >> (_shift)) +@@ -253,7 +253,7 @@ static int sprom_do_read(struct ssb_bus + int i; + + for (i = 0; i < bus->sprom_size; i++) +- sprom[i] = ioread16(bus->mmio + SSB_SPROM_BASE + (i * 2)); ++ sprom[i] = ioread16(bus->mmio + bus->sprom_offset + (i * 2)); + + return 0; + } +@@ -284,7 +284,7 @@ static int sprom_do_write(struct ssb_bus + ssb_printk("75%%"); + else if (i % 2) + ssb_printk("."); +- writew(sprom[i], bus->mmio + SSB_SPROM_BASE + (i * 2)); ++ writew(sprom[i], bus->mmio + bus->sprom_offset + (i * 2)); + mmiowb(); + msleep(20); + } +@@ -620,6 +620,14 @@ static int ssb_pci_sprom_get(struct ssb_ + int err = -ENOMEM; + u16 *buf; + ++ if (!ssb_is_sprom_available(bus)) { ++ ssb_printk(KERN_ERR PFX "No SPROM available!\n"); ++ return -ENODEV; ++ } ++ ++ bus->sprom_offset = (bus->chipco.dev->id.revision < 31) ? ++ SSB_SPROM_BASE1 : SSB_SPROM_BASE31; ++ + buf = kcalloc(SSB_SPROMSIZE_WORDS_R123, sizeof(u16), GFP_KERNEL); + if (!buf) + goto out; +--- a/drivers/ssb/sprom.c ++++ b/drivers/ssb/sprom.c +@@ -175,3 +175,17 @@ const struct ssb_sprom *ssb_get_fallback + { + return fallback_sprom; + } ++ ++/* http://bcm-v4.sipsolutions.net/802.11/IsSpromAvailable */ ++bool ssb_is_sprom_available(struct ssb_bus *bus) ++{ ++ /* status register only exists on chipcomon rev >= 11 and we need check ++ for >= 31 only */ ++ /* this routine differs from specs as we do not access SPROM directly ++ on PCMCIA */ ++ if (bus->bustype == SSB_BUSTYPE_PCI && ++ bus->chipco.dev->id.revision >= 31) ++ return bus->chipco.capabilities & SSB_CHIPCO_CAP_SPROM; ++ ++ return true; ++} +--- a/drivers/ssb/ssb_private.h ++++ b/drivers/ssb/ssb_private.h +@@ -196,7 +196,7 @@ extern int ssb_devices_thaw(struct ssb_f + #ifdef CONFIG_SSB_B43_PCI_BRIDGE + extern int __init b43_pci_ssb_bridge_init(void); + extern void __exit b43_pci_ssb_bridge_exit(void); +-#else /* CONFIG_SSB_B43_PCI_BRIDGR */ ++#else /* CONFIG_SSB_B43_PCI_BRIDGE */ + static inline int b43_pci_ssb_bridge_init(void) + { + return 0; +@@ -204,6 +204,6 @@ static inline int b43_pci_ssb_bridge_ini + static inline void b43_pci_ssb_bridge_exit(void) + { + } +-#endif /* CONFIG_SSB_PCIHOST */ ++#endif /* CONFIG_SSB_B43_PCI_BRIDGE */ + + #endif /* LINUX_SSB_PRIVATE_H_ */ +--- a/include/linux/ssb/ssb.h ++++ b/include/linux/ssb/ssb.h +@@ -305,6 +305,7 @@ struct ssb_bus { + /* ID information about the Chip. */ + u16 chip_id; + u16 chip_rev; ++ u16 sprom_offset; + u16 sprom_size; /* number of words in sprom */ + u8 chip_package; + +@@ -394,6 +395,9 @@ extern int ssb_bus_sdiobus_register(stru + + extern void ssb_bus_unregister(struct ssb_bus *bus); + ++/* Does the device have an SPROM? */ ++extern bool ssb_is_sprom_available(struct ssb_bus *bus); ++ + /* Set a fallback SPROM. + * See kdoc at the function definition for complete documentation. */ + extern int ssb_arch_set_fallback_sprom(const struct ssb_sprom *sprom); +--- a/include/linux/ssb/ssb_driver_chipcommon.h ++++ b/include/linux/ssb/ssb_driver_chipcommon.h +@@ -53,6 +53,7 @@ + #define SSB_CHIPCO_CAP_64BIT 0x08000000 /* 64-bit Backplane */ + #define SSB_CHIPCO_CAP_PMU 0x10000000 /* PMU available (rev >= 20) */ + #define SSB_CHIPCO_CAP_ECI 0x20000000 /* ECI available (rev >= 20) */ ++#define SSB_CHIPCO_CAP_SPROM 0x40000000 /* SPROM present */ + #define SSB_CHIPCO_CORECTL 0x0008 + #define SSB_CHIPCO_CORECTL_UARTCLK0 0x00000001 /* Drive UART with internal clock */ + #define SSB_CHIPCO_CORECTL_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ +@@ -385,6 +386,7 @@ + + + /** Chip specific Chip-Status register contents. */ ++#define SSB_CHIPCO_CHST_4322_SPROM_EXISTS 0x00000040 /* SPROM present */ + #define SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL 0x00000003 + #define SSB_CHIPCO_CHST_4325_DEFCIS_SEL 0 /* OTP is powered up, use def. CIS, no SPROM */ + #define SSB_CHIPCO_CHST_4325_SPROM_SEL 1 /* OTP is powered up, SPROM is present */ +@@ -398,6 +400,18 @@ + #define SSB_CHIPCO_CHST_4325_RCAL_VALUE_SHIFT 4 + #define SSB_CHIPCO_CHST_4325_PMUTOP_2B 0x00000200 /* 1 for 2b, 0 for to 2a */ + ++/** Macros to determine SPROM presence based on Chip-Status register. */ ++#define SSB_CHIPCO_CHST_4312_SPROM_PRESENT(status) \ ++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_OTP_SEL) ++#define SSB_CHIPCO_CHST_4322_SPROM_PRESENT(status) \ ++ (status & SSB_CHIPCO_CHST_4322_SPROM_EXISTS) ++#define SSB_CHIPCO_CHST_4325_SPROM_PRESENT(status) \ ++ (((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_DEFCIS_SEL) && \ ++ ((status & SSB_CHIPCO_CHST_4325_SPROM_OTP_SEL) != \ ++ SSB_CHIPCO_CHST_4325_OTP_SEL)) ++ + + + /** Clockcontrol masks and values **/ +@@ -564,6 +578,7 @@ struct ssb_chipcommon_pmu { + struct ssb_chipcommon { + struct ssb_device *dev; + u32 capabilities; ++ u32 status; + /* Fast Powerup Delay constant */ + u16 fast_pwrup_delay; + struct ssb_chipcommon_pmu pmu; +--- a/include/linux/ssb/ssb_regs.h ++++ b/include/linux/ssb/ssb_regs.h +@@ -170,26 +170,27 @@ + #define SSB_SPROMSIZE_WORDS_R4 220 + #define SSB_SPROMSIZE_BYTES_R123 (SSB_SPROMSIZE_WORDS_R123 * sizeof(u16)) + #define SSB_SPROMSIZE_BYTES_R4 (SSB_SPROMSIZE_WORDS_R4 * sizeof(u16)) +-#define SSB_SPROM_BASE 0x1000 +-#define SSB_SPROM_REVISION 0x107E ++#define SSB_SPROM_BASE1 0x1000 ++#define SSB_SPROM_BASE31 0x0800 ++#define SSB_SPROM_REVISION 0x007E + #define SSB_SPROM_REVISION_REV 0x00FF /* SPROM Revision number */ + #define SSB_SPROM_REVISION_CRC 0xFF00 /* SPROM CRC8 value */ + #define SSB_SPROM_REVISION_CRC_SHIFT 8 + + /* SPROM Revision 1 */ +-#define SSB_SPROM1_SPID 0x1004 /* Subsystem Product ID for PCI */ +-#define SSB_SPROM1_SVID 0x1006 /* Subsystem Vendor ID for PCI */ +-#define SSB_SPROM1_PID 0x1008 /* Product ID for PCI */ +-#define SSB_SPROM1_IL0MAC 0x1048 /* 6 bytes MAC address for 802.11b/g */ +-#define SSB_SPROM1_ET0MAC 0x104E /* 6 bytes MAC address for Ethernet */ +-#define SSB_SPROM1_ET1MAC 0x1054 /* 6 bytes MAC address for 802.11a */ +-#define SSB_SPROM1_ETHPHY 0x105A /* Ethernet PHY settings */ ++#define SSB_SPROM1_SPID 0x0004 /* Subsystem Product ID for PCI */ ++#define SSB_SPROM1_SVID 0x0006 /* Subsystem Vendor ID for PCI */ ++#define SSB_SPROM1_PID 0x0008 /* Product ID for PCI */ ++#define SSB_SPROM1_IL0MAC 0x0048 /* 6 bytes MAC address for 802.11b/g */ ++#define SSB_SPROM1_ET0MAC 0x004E /* 6 bytes MAC address for Ethernet */ ++#define SSB_SPROM1_ET1MAC 0x0054 /* 6 bytes MAC address for 802.11a */ ++#define SSB_SPROM1_ETHPHY 0x005A /* Ethernet PHY settings */ + #define SSB_SPROM1_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ + #define SSB_SPROM1_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ + #define SSB_SPROM1_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM1_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM1_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM1_BINF 0x105C /* Board info */ ++#define SSB_SPROM1_BINF 0x005C /* Board info */ + #define SSB_SPROM1_BINF_BREV 0x00FF /* Board Revision */ + #define SSB_SPROM1_BINF_CCODE 0x0F00 /* Country Code */ + #define SSB_SPROM1_BINF_CCODE_SHIFT 8 +@@ -197,63 +198,63 @@ + #define SSB_SPROM1_BINF_ANTBG_SHIFT 12 + #define SSB_SPROM1_BINF_ANTA 0xC000 /* Available A-PHY antennas */ + #define SSB_SPROM1_BINF_ANTA_SHIFT 14 +-#define SSB_SPROM1_PA0B0 0x105E +-#define SSB_SPROM1_PA0B1 0x1060 +-#define SSB_SPROM1_PA0B2 0x1062 +-#define SSB_SPROM1_GPIOA 0x1064 /* General Purpose IO pins 0 and 1 */ ++#define SSB_SPROM1_PA0B0 0x005E ++#define SSB_SPROM1_PA0B1 0x0060 ++#define SSB_SPROM1_PA0B2 0x0062 ++#define SSB_SPROM1_GPIOA 0x0064 /* General Purpose IO pins 0 and 1 */ + #define SSB_SPROM1_GPIOA_P0 0x00FF /* Pin 0 */ + #define SSB_SPROM1_GPIOA_P1 0xFF00 /* Pin 1 */ + #define SSB_SPROM1_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM1_GPIOB 0x1066 /* General Purpuse IO pins 2 and 3 */ ++#define SSB_SPROM1_GPIOB 0x0066 /* General Purpuse IO pins 2 and 3 */ + #define SSB_SPROM1_GPIOB_P2 0x00FF /* Pin 2 */ + #define SSB_SPROM1_GPIOB_P3 0xFF00 /* Pin 3 */ + #define SSB_SPROM1_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM1_MAXPWR 0x1068 /* Power Amplifier Max Power */ ++#define SSB_SPROM1_MAXPWR 0x0068 /* Power Amplifier Max Power */ + #define SSB_SPROM1_MAXPWR_BG 0x00FF /* B-PHY and G-PHY (in dBm Q5.2) */ + #define SSB_SPROM1_MAXPWR_A 0xFF00 /* A-PHY (in dBm Q5.2) */ + #define SSB_SPROM1_MAXPWR_A_SHIFT 8 +-#define SSB_SPROM1_PA1B0 0x106A +-#define SSB_SPROM1_PA1B1 0x106C +-#define SSB_SPROM1_PA1B2 0x106E +-#define SSB_SPROM1_ITSSI 0x1070 /* Idle TSSI Target */ ++#define SSB_SPROM1_PA1B0 0x006A ++#define SSB_SPROM1_PA1B1 0x006C ++#define SSB_SPROM1_PA1B2 0x006E ++#define SSB_SPROM1_ITSSI 0x0070 /* Idle TSSI Target */ + #define SSB_SPROM1_ITSSI_BG 0x00FF /* B-PHY and G-PHY*/ + #define SSB_SPROM1_ITSSI_A 0xFF00 /* A-PHY */ + #define SSB_SPROM1_ITSSI_A_SHIFT 8 +-#define SSB_SPROM1_BFLLO 0x1072 /* Boardflags (low 16 bits) */ +-#define SSB_SPROM1_AGAIN 0x1074 /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM1_BFLLO 0x0072 /* Boardflags (low 16 bits) */ ++#define SSB_SPROM1_AGAIN 0x0074 /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM1_AGAIN_BG 0x00FF /* B-PHY and G-PHY */ + #define SSB_SPROM1_AGAIN_BG_SHIFT 0 + #define SSB_SPROM1_AGAIN_A 0xFF00 /* A-PHY */ + #define SSB_SPROM1_AGAIN_A_SHIFT 8 + + /* SPROM Revision 2 (inherits from rev 1) */ +-#define SSB_SPROM2_BFLHI 0x1038 /* Boardflags (high 16 bits) */ +-#define SSB_SPROM2_MAXP_A 0x103A /* A-PHY Max Power */ ++#define SSB_SPROM2_BFLHI 0x0038 /* Boardflags (high 16 bits) */ ++#define SSB_SPROM2_MAXP_A 0x003A /* A-PHY Max Power */ + #define SSB_SPROM2_MAXP_A_HI 0x00FF /* Max Power High */ + #define SSB_SPROM2_MAXP_A_LO 0xFF00 /* Max Power Low */ + #define SSB_SPROM2_MAXP_A_LO_SHIFT 8 +-#define SSB_SPROM2_PA1LOB0 0x103C /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1LOB1 0x103E /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1LOB2 0x1040 /* A-PHY PowerAmplifier Low Settings */ +-#define SSB_SPROM2_PA1HIB0 0x1042 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_PA1HIB1 0x1044 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_PA1HIB2 0x1046 /* A-PHY PowerAmplifier High Settings */ +-#define SSB_SPROM2_OPO 0x1078 /* OFDM Power Offset from CCK Level */ ++#define SSB_SPROM2_PA1LOB0 0x003C /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1LOB1 0x003E /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1LOB2 0x0040 /* A-PHY PowerAmplifier Low Settings */ ++#define SSB_SPROM2_PA1HIB0 0x0042 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_PA1HIB1 0x0044 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_PA1HIB2 0x0046 /* A-PHY PowerAmplifier High Settings */ ++#define SSB_SPROM2_OPO 0x0078 /* OFDM Power Offset from CCK Level */ + #define SSB_SPROM2_OPO_VALUE 0x00FF + #define SSB_SPROM2_OPO_UNUSED 0xFF00 +-#define SSB_SPROM2_CCODE 0x107C /* Two char Country Code */ ++#define SSB_SPROM2_CCODE 0x007C /* Two char Country Code */ + + /* SPROM Revision 3 (inherits most data from rev 2) */ +-#define SSB_SPROM3_IL0MAC 0x104A /* 6 bytes MAC address for 802.11b/g */ +-#define SSB_SPROM3_OFDMAPO 0x102C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_OFDMALPO 0x1030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_OFDMAHPO 0x1034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ +-#define SSB_SPROM3_GPIOLDC 0x1042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMAPO 0x002C /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMALPO 0x0030 /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_OFDMAHPO 0x0034 /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */ ++#define SSB_SPROM3_GPIOLDC 0x0042 /* GPIO LED Powersave Duty Cycle (4 bytes, BigEndian) */ + #define SSB_SPROM3_GPIOLDC_OFF 0x0000FF00 /* Off Count */ + #define SSB_SPROM3_GPIOLDC_OFF_SHIFT 8 + #define SSB_SPROM3_GPIOLDC_ON 0x00FF0000 /* On Count */ + #define SSB_SPROM3_GPIOLDC_ON_SHIFT 16 +-#define SSB_SPROM3_CCKPO 0x1078 /* CCK Power Offset */ ++#define SSB_SPROM3_IL0MAC 0x004A /* 6 bytes MAC address for 802.11b/g */ ++#define SSB_SPROM3_CCKPO 0x0078 /* CCK Power Offset */ + #define SSB_SPROM3_CCKPO_1M 0x000F /* 1M Rate PO */ + #define SSB_SPROM3_CCKPO_2M 0x00F0 /* 2M Rate PO */ + #define SSB_SPROM3_CCKPO_2M_SHIFT 4 +@@ -264,100 +265,100 @@ + #define SSB_SPROM3_OFDMGPO 0x107A /* G-PHY OFDM Power Offset (4 bytes, BigEndian) */ + + /* SPROM Revision 4 */ +-#define SSB_SPROM4_IL0MAC 0x104C /* 6 byte MAC address for a/b/g/n */ +-#define SSB_SPROM4_ETHPHY 0x105A /* Ethernet PHY settings ?? */ ++#define SSB_SPROM4_BFLLO 0x0044 /* Boardflags (low 16 bits) */ ++#define SSB_SPROM4_BFLHI 0x0046 /* Board Flags Hi */ ++#define SSB_SPROM4_IL0MAC 0x004C /* 6 byte MAC address for a/b/g/n */ ++#define SSB_SPROM4_CCODE 0x0052 /* Country Code (2 bytes) */ ++#define SSB_SPROM4_GPIOA 0x0056 /* Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ ++#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ ++#define SSB_SPROM4_GPIOA_P1_SHIFT 8 ++#define SSB_SPROM4_GPIOB 0x0058 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ ++#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ ++#define SSB_SPROM4_GPIOB_P3_SHIFT 8 ++#define SSB_SPROM4_ETHPHY 0x005A /* Ethernet PHY settings ?? */ + #define SSB_SPROM4_ETHPHY_ET0A 0x001F /* MII Address for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1A 0x03E0 /* MII Address for enet1 */ + #define SSB_SPROM4_ETHPHY_ET1A_SHIFT 5 + #define SSB_SPROM4_ETHPHY_ET0M (1<<14) /* MDIO for enet0 */ + #define SSB_SPROM4_ETHPHY_ET1M (1<<15) /* MDIO for enet1 */ +-#define SSB_SPROM4_CCODE 0x1052 /* Country Code (2 bytes) */ +-#define SSB_SPROM4_ANTAVAIL 0x105D /* Antenna available bitfields */ +-#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 +-#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 +-#define SSB_SPROM4_BFLLO 0x1044 /* Boardflags (low 16 bits) */ +-#define SSB_SPROM4_AGAIN01 0x105E /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM4_ANTAVAIL 0x005D /* Antenna available bitfields */ ++#define SSB_SPROM4_ANTAVAIL_A 0x00FF /* A-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_A_SHIFT 0 ++#define SSB_SPROM4_ANTAVAIL_BG 0xFF00 /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM4_ANTAVAIL_BG_SHIFT 8 ++#define SSB_SPROM4_AGAIN01 0x005E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM4_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM4_AGAIN0_SHIFT 0 + #define SSB_SPROM4_AGAIN1 0xFF00 /* Antenna 1 */ + #define SSB_SPROM4_AGAIN1_SHIFT 8 +-#define SSB_SPROM4_AGAIN23 0x1060 ++#define SSB_SPROM4_AGAIN23 0x0060 + #define SSB_SPROM4_AGAIN2 0x00FF /* Antenna 2 */ + #define SSB_SPROM4_AGAIN2_SHIFT 0 + #define SSB_SPROM4_AGAIN3 0xFF00 /* Antenna 3 */ + #define SSB_SPROM4_AGAIN3_SHIFT 8 +-#define SSB_SPROM4_BFLHI 0x1046 /* Board Flags Hi */ +-#define SSB_SPROM4_MAXP_BG 0x1080 /* Max Power BG in path 1 */ ++#define SSB_SPROM4_MAXP_BG 0x0080 /* Max Power BG in path 1 */ + #define SSB_SPROM4_MAXP_BG_MASK 0x00FF /* Mask for Max Power BG */ + #define SSB_SPROM4_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ + #define SSB_SPROM4_ITSSI_BG_SHIFT 8 +-#define SSB_SPROM4_MAXP_A 0x108A /* Max Power A in path 1 */ ++#define SSB_SPROM4_MAXP_A 0x008A /* Max Power A in path 1 */ + #define SSB_SPROM4_MAXP_A_MASK 0x00FF /* Mask for Max Power A */ + #define SSB_SPROM4_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ + #define SSB_SPROM4_ITSSI_A_SHIFT 8 +-#define SSB_SPROM4_GPIOA 0x1056 /* Gen. Purpose IO # 0 and 1 */ +-#define SSB_SPROM4_GPIOA_P0 0x00FF /* Pin 0 */ +-#define SSB_SPROM4_GPIOA_P1 0xFF00 /* Pin 1 */ +-#define SSB_SPROM4_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM4_GPIOB 0x1058 /* Gen. Purpose IO # 2 and 3 */ +-#define SSB_SPROM4_GPIOB_P2 0x00FF /* Pin 2 */ +-#define SSB_SPROM4_GPIOB_P3 0xFF00 /* Pin 3 */ +-#define SSB_SPROM4_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM4_PA0B0 0x1082 /* The paXbY locations are */ +-#define SSB_SPROM4_PA0B1 0x1084 /* only guesses */ +-#define SSB_SPROM4_PA0B2 0x1086 +-#define SSB_SPROM4_PA1B0 0x108E +-#define SSB_SPROM4_PA1B1 0x1090 +-#define SSB_SPROM4_PA1B2 0x1092 ++#define SSB_SPROM4_PA0B0 0x0082 /* The paXbY locations are */ ++#define SSB_SPROM4_PA0B1 0x0084 /* only guesses */ ++#define SSB_SPROM4_PA0B2 0x0086 ++#define SSB_SPROM4_PA1B0 0x008E ++#define SSB_SPROM4_PA1B1 0x0090 ++#define SSB_SPROM4_PA1B2 0x0092 + + /* SPROM Revision 5 (inherits most data from rev 4) */ +-#define SSB_SPROM5_BFLLO 0x104A /* Boardflags (low 16 bits) */ +-#define SSB_SPROM5_BFLHI 0x104C /* Board Flags Hi */ +-#define SSB_SPROM5_IL0MAC 0x1052 /* 6 byte MAC address for a/b/g/n */ +-#define SSB_SPROM5_CCODE 0x1044 /* Country Code (2 bytes) */ +-#define SSB_SPROM5_GPIOA 0x1076 /* Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM5_CCODE 0x0044 /* Country Code (2 bytes) */ ++#define SSB_SPROM5_BFLLO 0x004A /* Boardflags (low 16 bits) */ ++#define SSB_SPROM5_BFLHI 0x004C /* Board Flags Hi */ ++#define SSB_SPROM5_IL0MAC 0x0052 /* 6 byte MAC address for a/b/g/n */ ++#define SSB_SPROM5_GPIOA 0x0076 /* Gen. Purpose IO # 0 and 1 */ + #define SSB_SPROM5_GPIOA_P0 0x00FF /* Pin 0 */ + #define SSB_SPROM5_GPIOA_P1 0xFF00 /* Pin 1 */ + #define SSB_SPROM5_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM5_GPIOB 0x1078 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM5_GPIOB 0x0078 /* Gen. Purpose IO # 2 and 3 */ + #define SSB_SPROM5_GPIOB_P2 0x00FF /* Pin 2 */ + #define SSB_SPROM5_GPIOB_P3 0xFF00 /* Pin 3 */ + #define SSB_SPROM5_GPIOB_P3_SHIFT 8 + + /* SPROM Revision 8 */ +-#define SSB_SPROM8_BOARDREV 0x1082 /* Board revision */ +-#define SSB_SPROM8_BFLLO 0x1084 /* Board flags (bits 0-15) */ +-#define SSB_SPROM8_BFLHI 0x1086 /* Board flags (bits 16-31) */ +-#define SSB_SPROM8_BFL2LO 0x1088 /* Board flags (bits 32-47) */ +-#define SSB_SPROM8_BFL2HI 0x108A /* Board flags (bits 48-63) */ +-#define SSB_SPROM8_IL0MAC 0x108C /* 6 byte MAC address */ +-#define SSB_SPROM8_CCODE 0x1092 /* 2 byte country code */ +-#define SSB_SPROM8_ANTAVAIL 0x109C /* Antenna available bitfields*/ +-#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ +-#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 +-#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ +-#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 +-#define SSB_SPROM8_AGAIN01 0x109E /* Antenna Gain (in dBm Q5.2) */ ++#define SSB_SPROM8_BOARDREV 0x0082 /* Board revision */ ++#define SSB_SPROM8_BFLLO 0x0084 /* Board flags (bits 0-15) */ ++#define SSB_SPROM8_BFLHI 0x0086 /* Board flags (bits 16-31) */ ++#define SSB_SPROM8_BFL2LO 0x0088 /* Board flags (bits 32-47) */ ++#define SSB_SPROM8_BFL2HI 0x008A /* Board flags (bits 48-63) */ ++#define SSB_SPROM8_IL0MAC 0x008C /* 6 byte MAC address */ ++#define SSB_SPROM8_CCODE 0x0092 /* 2 byte country code */ ++#define SSB_SPROM8_GPIOA 0x0096 /*Gen. Purpose IO # 0 and 1 */ ++#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ ++#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ ++#define SSB_SPROM8_GPIOA_P1_SHIFT 8 ++#define SSB_SPROM8_GPIOB 0x0098 /* Gen. Purpose IO # 2 and 3 */ ++#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ ++#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ ++#define SSB_SPROM8_GPIOB_P3_SHIFT 8 ++#define SSB_SPROM8_ANTAVAIL 0x009C /* Antenna available bitfields*/ ++#define SSB_SPROM8_ANTAVAIL_A 0xFF00 /* A-PHY bitfield */ ++#define SSB_SPROM8_ANTAVAIL_A_SHIFT 8 ++#define SSB_SPROM8_ANTAVAIL_BG 0x00FF /* B-PHY and G-PHY bitfield */ ++#define SSB_SPROM8_ANTAVAIL_BG_SHIFT 0 ++#define SSB_SPROM8_AGAIN01 0x009E /* Antenna Gain (in dBm Q5.2) */ + #define SSB_SPROM8_AGAIN0 0x00FF /* Antenna 0 */ + #define SSB_SPROM8_AGAIN0_SHIFT 0 + #define SSB_SPROM8_AGAIN1 0xFF00 /* Antenna 1 */ + #define SSB_SPROM8_AGAIN1_SHIFT 8 +-#define SSB_SPROM8_AGAIN23 0x10A0 ++#define SSB_SPROM8_AGAIN23 0x00A0 + #define SSB_SPROM8_AGAIN2 0x00FF /* Antenna 2 */ + #define SSB_SPROM8_AGAIN2_SHIFT 0 + #define SSB_SPROM8_AGAIN3 0xFF00 /* Antenna 3 */ + #define SSB_SPROM8_AGAIN3_SHIFT 8 +-#define SSB_SPROM8_GPIOA 0x1096 /*Gen. Purpose IO # 0 and 1 */ +-#define SSB_SPROM8_GPIOA_P0 0x00FF /* Pin 0 */ +-#define SSB_SPROM8_GPIOA_P1 0xFF00 /* Pin 1 */ +-#define SSB_SPROM8_GPIOA_P1_SHIFT 8 +-#define SSB_SPROM8_GPIOB 0x1098 /* Gen. Purpose IO # 2 and 3 */ +-#define SSB_SPROM8_GPIOB_P2 0x00FF /* Pin 2 */ +-#define SSB_SPROM8_GPIOB_P3 0xFF00 /* Pin 3 */ +-#define SSB_SPROM8_GPIOB_P3_SHIFT 8 +-#define SSB_SPROM8_RSSIPARM2G 0x10A4 /* RSSI params for 2GHz */ ++#define SSB_SPROM8_RSSIPARM2G 0x00A4 /* RSSI params for 2GHz */ + #define SSB_SPROM8_RSSISMF2G 0x000F + #define SSB_SPROM8_RSSISMC2G 0x00F0 + #define SSB_SPROM8_RSSISMC2G_SHIFT 4 +@@ -365,7 +366,7 @@ + #define SSB_SPROM8_RSSISAV2G_SHIFT 8 + #define SSB_SPROM8_BXA2G 0x1800 + #define SSB_SPROM8_BXA2G_SHIFT 11 +-#define SSB_SPROM8_RSSIPARM5G 0x10A6 /* RSSI params for 5GHz */ ++#define SSB_SPROM8_RSSIPARM5G 0x00A6 /* RSSI params for 5GHz */ + #define SSB_SPROM8_RSSISMF5G 0x000F + #define SSB_SPROM8_RSSISMC5G 0x00F0 + #define SSB_SPROM8_RSSISMC5G_SHIFT 4 +@@ -373,47 +374,47 @@ + #define SSB_SPROM8_RSSISAV5G_SHIFT 8 + #define SSB_SPROM8_BXA5G 0x1800 + #define SSB_SPROM8_BXA5G_SHIFT 11 +-#define SSB_SPROM8_TRI25G 0x10A8 /* TX isolation 2.4&5.3GHz */ ++#define SSB_SPROM8_TRI25G 0x00A8 /* TX isolation 2.4&5.3GHz */ + #define SSB_SPROM8_TRI2G 0x00FF /* TX isolation 2.4GHz */ + #define SSB_SPROM8_TRI5G 0xFF00 /* TX isolation 5.3GHz */ + #define SSB_SPROM8_TRI5G_SHIFT 8 +-#define SSB_SPROM8_TRI5GHL 0x10AA /* TX isolation 5.2/5.8GHz */ ++#define SSB_SPROM8_TRI5GHL 0x00AA /* TX isolation 5.2/5.8GHz */ + #define SSB_SPROM8_TRI5GL 0x00FF /* TX isolation 5.2GHz */ + #define SSB_SPROM8_TRI5GH 0xFF00 /* TX isolation 5.8GHz */ + #define SSB_SPROM8_TRI5GH_SHIFT 8 +-#define SSB_SPROM8_RXPO 0x10AC /* RX power offsets */ ++#define SSB_SPROM8_RXPO 0x00AC /* RX power offsets */ + #define SSB_SPROM8_RXPO2G 0x00FF /* 2GHz RX power offset */ + #define SSB_SPROM8_RXPO5G 0xFF00 /* 5GHz RX power offset */ + #define SSB_SPROM8_RXPO5G_SHIFT 8 +-#define SSB_SPROM8_MAXP_BG 0x10C0 /* Max Power 2GHz in path 1 */ ++#define SSB_SPROM8_MAXP_BG 0x00C0 /* Max Power 2GHz in path 1 */ + #define SSB_SPROM8_MAXP_BG_MASK 0x00FF /* Mask for Max Power 2GHz */ + #define SSB_SPROM8_ITSSI_BG 0xFF00 /* Mask for path 1 itssi_bg */ + #define SSB_SPROM8_ITSSI_BG_SHIFT 8 +-#define SSB_SPROM8_PA0B0 0x10C2 /* 2GHz power amp settings */ +-#define SSB_SPROM8_PA0B1 0x10C4 +-#define SSB_SPROM8_PA0B2 0x10C6 +-#define SSB_SPROM8_MAXP_A 0x10C8 /* Max Power 5.3GHz */ ++#define SSB_SPROM8_PA0B0 0x00C2 /* 2GHz power amp settings */ ++#define SSB_SPROM8_PA0B1 0x00C4 ++#define SSB_SPROM8_PA0B2 0x00C6 ++#define SSB_SPROM8_MAXP_A 0x00C8 /* Max Power 5.3GHz */ + #define SSB_SPROM8_MAXP_A_MASK 0x00FF /* Mask for Max Power 5.3GHz */ + #define SSB_SPROM8_ITSSI_A 0xFF00 /* Mask for path 1 itssi_a */ + #define SSB_SPROM8_ITSSI_A_SHIFT 8 +-#define SSB_SPROM8_MAXP_AHL 0x10CA /* Max Power 5.2/5.8GHz */ ++#define SSB_SPROM8_MAXP_AHL 0x00CA /* Max Power 5.2/5.8GHz */ + #define SSB_SPROM8_MAXP_AH_MASK 0x00FF /* Mask for Max Power 5.8GHz */ + #define SSB_SPROM8_MAXP_AL_MASK 0xFF00 /* Mask for Max Power 5.2GHz */ + #define SSB_SPROM8_MAXP_AL_SHIFT 8 +-#define SSB_SPROM8_PA1B0 0x10CC /* 5.3GHz power amp settings */ +-#define SSB_SPROM8_PA1B1 0x10CE +-#define SSB_SPROM8_PA1B2 0x10D0 +-#define SSB_SPROM8_PA1LOB0 0x10D2 /* 5.2GHz power amp settings */ +-#define SSB_SPROM8_PA1LOB1 0x10D4 +-#define SSB_SPROM8_PA1LOB2 0x10D6 +-#define SSB_SPROM8_PA1HIB0 0x10D8 /* 5.8GHz power amp settings */ +-#define SSB_SPROM8_PA1HIB1 0x10DA +-#define SSB_SPROM8_PA1HIB2 0x10DC +-#define SSB_SPROM8_CCK2GPO 0x1140 /* CCK power offset */ +-#define SSB_SPROM8_OFDM2GPO 0x1142 /* 2.4GHz OFDM power offset */ +-#define SSB_SPROM8_OFDM5GPO 0x1146 /* 5.3GHz OFDM power offset */ +-#define SSB_SPROM8_OFDM5GLPO 0x114A /* 5.2GHz OFDM power offset */ +-#define SSB_SPROM8_OFDM5GHPO 0x114E /* 5.8GHz OFDM power offset */ ++#define SSB_SPROM8_PA1B0 0x00CC /* 5.3GHz power amp settings */ ++#define SSB_SPROM8_PA1B1 0x00CE ++#define SSB_SPROM8_PA1B2 0x00D0 ++#define SSB_SPROM8_PA1LOB0 0x00D2 /* 5.2GHz power amp settings */ ++#define SSB_SPROM8_PA1LOB1 0x00D4 ++#define SSB_SPROM8_PA1LOB2 0x00D6 ++#define SSB_SPROM8_PA1HIB0 0x00D8 /* 5.8GHz power amp settings */ ++#define SSB_SPROM8_PA1HIB1 0x00DA ++#define SSB_SPROM8_PA1HIB2 0x00DC ++#define SSB_SPROM8_CCK2GPO 0x0140 /* CCK power offset */ ++#define SSB_SPROM8_OFDM2GPO 0x0142 /* 2.4GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GPO 0x0146 /* 5.3GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GLPO 0x014A /* 5.2GHz OFDM power offset */ ++#define SSB_SPROM8_OFDM5GHPO 0x014E /* 5.8GHz OFDM power offset */ + + /* Values for SSB_SPROM1_BINF_CCODE */ + enum { |