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Diffstat (limited to 'target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch')
-rw-r--r--target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch41
1 files changed, 41 insertions, 0 deletions
diff --git a/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch b/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch
new file mode 100644
index 0000000000..0fa7ed483f
--- /dev/null
+++ b/target/linux/cns3xxx/patches-4.19/093-add-virt-pci-io-mapping.patch
@@ -0,0 +1,41 @@
+--- a/arch/arm/mach-cns3xxx/cns3xxx.h
++++ b/arch/arm/mach-cns3xxx/cns3xxx.h
+@@ -162,11 +162,13 @@
+ #define CNS3XXX_L2C_BASE 0x92000000 /* L2 Cache Control */
+
+ #define CNS3XXX_PCIE0_MEM_BASE 0xA0000000 /* PCIe Port 0 IO/Memory Space */
++#define CNS3XXX_PCIE0_MEM_BASE_VIRT 0xE0000000
+
+ #define CNS3XXX_PCIE0_HOST_BASE 0xAB000000 /* PCIe Port 0 RC Base */
+ #define CNS3XXX_PCIE0_HOST_BASE_VIRT 0xE1000000
+
+ #define CNS3XXX_PCIE0_IO_BASE 0xAC000000 /* PCIe Port 0 */
++#define CNS3XXX_PCIE0_IO_BASE_VIRT 0xE2000000
+
+ #define CNS3XXX_PCIE0_CFG0_BASE 0xAD000000 /* PCIe Port 0 CFG Type 0 */
+ #define CNS3XXX_PCIE0_CFG0_BASE_VIRT 0xE3000000
+@@ -175,13 +177,16 @@
+ #define CNS3XXX_PCIE0_CFG1_BASE_VIRT 0xE4000000
+
+ #define CNS3XXX_PCIE0_MSG_BASE 0xAF000000 /* PCIe Port 0 Message Space */
++#define CNS3XXX_PCIE0_MSG_BASE_VIRT 0xE5000000
+
+ #define CNS3XXX_PCIE1_MEM_BASE 0xB0000000 /* PCIe Port 1 IO/Memory Space */
++#define CNS3XXX_PCIE1_MEM_BASE_VIRT 0xE8000000
+
+ #define CNS3XXX_PCIE1_HOST_BASE 0xBB000000 /* PCIe Port 1 RC Base */
+ #define CNS3XXX_PCIE1_HOST_BASE_VIRT 0xE9000000
+
+ #define CNS3XXX_PCIE1_IO_BASE 0xBC000000 /* PCIe Port 1 */
++#define CNS3XXX_PCIE1_IO_BASE_VIRT 0xEA000000
+
+ #define CNS3XXX_PCIE1_CFG0_BASE 0xBD000000 /* PCIe Port 1 CFG Type 0 */
+ #define CNS3XXX_PCIE1_CFG0_BASE_VIRT 0xEB000000
+@@ -190,6 +195,7 @@
+ #define CNS3XXX_PCIE1_CFG1_BASE_VIRT 0xEC000000
+
+ #define CNS3XXX_PCIE1_MSG_BASE 0xBF000000 /* PCIe Port 1 Message Space */
++#define CNS3XXX_PCIE1_MSG_BASE_VIRT 0xED000000
+
+ /*
+ * Testchip peripheral and fpga gic regions